* Re: [PATCH v3 1/4] devicetree: hwmon: Add bindings for ADC128D818
From: Rob Herring @ 2017-01-10 5:35 UTC (permalink / raw)
To: Alexander Koch
Cc: linux-kernel, linux-hwmon, Mark Rutland, Jean Delvare,
Guenter Roeck, Michael Hornung, devicetree
In-Reply-To: <20170106103817.11588-2-mail@alexanderkoch.net>
On Fri, Jan 06, 2017 at 11:38:14AM +0100, Alexander Koch wrote:
> Add bindings documentation for the ADC128D818 driver, featuring default I2C
> properties along with the optional 'mode' property for chip operation mode
> selection (see datasheet, sec. 8.4.1).
>
> Signed-off-by: Alexander Koch <mail@alexanderkoch.net>
> Acked-by: Michael Hornung <mhornung.linux@gmail.com>
> ---
> .../devicetree/bindings/hwmon/adc128d818.txt | 39 ++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/hwmon/adc128d818.txt
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 1/4] clk: stm32f7: Add stm32f7 clock DT bindings for STM32F746 boards
From: Rob Herring @ 2017-01-10 5:35 UTC (permalink / raw)
To: gabriel.fernandez
Cc: Mark Rutland, devicetree, daniel.thompson, radoslaw.pietrzyk,
Alexandre Torgue, Arnd Bergmann, Nicolas Pitre, andrea.merello,
Michael Turquette, olivier.bideau, Stephen Boyd, Russell King,
linux-kernel, ludovic.barre, Maxime Coquelin, amelie.delaunay,
linux-clk, linux-arm-kernel, kernel
In-Reply-To: <1483711165-17149-2-git-send-email-gabriel.fernandez@st.com>
On Fri, Jan 06, 2017 at 02:59:22PM +0100, gabriel.fernandez@st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
>
> This patch introduces the stm32f7 clock DT bindings.
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
> .../devicetree/bindings/clock/st,stm32-rcc.txt | 20 ++++++++++++++++++++
> include/dt-bindings/clock/stm32fx-clock.h | 20 ++++++++++++++++++++
> 2 files changed, 40 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 1/3] dt-bindings: gpio: Add binding documentation for gpio-thunderx
From: Rob Herring @ 2017-01-10 5:35 UTC (permalink / raw)
To: David Daney
Cc: Linus Walleij, Alexandre Courbot, Mark Rutland, linux-gpio,
devicetree, linux-kernel, David Daney
In-Reply-To: <1483744980-25898-2-git-send-email-ddaney.cavm@gmail.com>
On Fri, Jan 06, 2017 at 03:22:58PM -0800, David Daney wrote:
> From: David Daney <david.daney@cavium.com>
>
> Signed-off-by: David Daney <david.daney@cavium.com>
> ---
> .../devicetree/bindings/gpio/gpio-thunderx.txt | 27 ++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/gpio/gpio-thunderx.txt
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v3 13/24] platform: add video-multiplexer subdevice driver
From: Rob Herring @ 2017-01-10 5:35 UTC (permalink / raw)
To: Steve Longerbeam
Cc: mark.rutland, andrew-ct.chen, minghsiu.tsai, nick, songjun.wu,
hverkuil, robert.jarzmik, devel, markus.heiser,
laurent.pinchart+renesas, linux, geert, Sascha Hauer, linux-media,
devicetree, kernel, arnd, mchehab, bparrot, Steve Longerbeam,
horms+renesas, tiffany.lin, linux-arm-kernel,
niklas.soderlund+renesas, gregkh, linux-kernel,
jean-christophe.trotin, p.zabel, fabio.estevam, shawnguo,
sudipm.mukherjee
In-Reply-To: <1483755102-24785-14-git-send-email-steve_longerbeam@mentor.com>
On Fri, Jan 06, 2017 at 06:11:31PM -0800, Steve Longerbeam wrote:
> From: Philipp Zabel <p.zabel@pengutronix.de>
>
> This driver can handle SoC internal and external video bus multiplexers,
> controlled either by register bit fields or by a GPIO. The subdevice
> passes through frame interval and mbus configuration of the active input
> to the output side.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
>
> --
>
> - fixed a cut&paste error in vidsw_remove(): v4l2_async_register_subdev()
> should be unregister.
>
> - added media_entity_cleanup() and v4l2_device_unregister_subdev()
> to vidsw_remove().
>
> - there was a line left over from a previous iteration that negated
> the new way of determining the pad count just before it which
> has been removed (num_pads = of_get_child_count(np)).
>
> - Philipp Zabel has developed a set of patches that allow adding
> to the subdev async notifier waiting list using a chaining method
> from the async registered callbacks (v4l2_of_subdev_registered()
> and the prep patches for that). For now, I've removed the use of
> v4l2_of_subdev_registered() for the vidmux driver's registered
> callback. This doesn't affect the functionality of this driver,
> but allows for it to be merged now, before adding the chaining
> support.
>
> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
> ---
> .../bindings/media/video-multiplexer.txt | 59 +++
> drivers/media/platform/Kconfig | 8 +
> drivers/media/platform/Makefile | 2 +
> drivers/media/platform/video-multiplexer.c | 472 +++++++++++++++++++++
> 4 files changed, 541 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/video-multiplexer.txt
> create mode 100644 drivers/media/platform/video-multiplexer.c
>
> diff --git a/Documentation/devicetree/bindings/media/video-multiplexer.txt b/Documentation/devicetree/bindings/media/video-multiplexer.txt
> new file mode 100644
> index 0000000..9d133d9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/video-multiplexer.txt
> @@ -0,0 +1,59 @@
> +Video Multiplexer
> +=================
> +
> +Video multiplexers allow to select between multiple input ports. Video received
> +on the active input port is passed through to the output port. Muxes described
> +by this binding may be controlled by a syscon register bitfield or by a GPIO.
> +
> +Required properties:
> +- compatible : should be "video-multiplexer"
This should have an SoC/chip specific compatible string additionally.
Just need a note to that effect here, but i.MX will need a compat
string.
> +- reg: should be register base of the register containing the control bitfield
> +- bit-mask: bitmask of the control bitfield in the control register
> +- bit-shift: bit offset of the control bitfield in the control register
> +- gpios: alternatively to reg, bit-mask, and bit-shift, a single GPIO phandle
> + may be given to switch between two inputs
> +- #address-cells: should be <1>
> +- #size-cells: should be <0>
> +- port@*: at least three port nodes containing endpoints connecting to the
> + source and sink devices according to of_graph bindings. The last port is
> + the output port, all others are inputs.
^ permalink raw reply
* Re: [PATCH v1 1/3] dt: bindings: add thermal device driver for zx2967
From: Rob Herring @ 2017-01-10 5:35 UTC (permalink / raw)
To: Baoyou Xie
Cc: mark.rutland, jun.nie, akpm, geert+renesas, linux-pm, gregkh,
xie.baoyou, linux-kernel, edubezval, devicetree, chen.chaokai,
linux-arm-kernel, wang.qiang01, rui.zhang, mchehab, shawnguo,
davem, linux
In-Reply-To: <1483767488-19778-1-git-send-email-baoyou.xie@linaro.org>
On Sat, Jan 07, 2017 at 01:38:06PM +0800, Baoyou Xie wrote:
> This patch adds dt-binding documentation for zx2967 family thermal sensor.
>
> Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
> ---
> .../devicetree/bindings/thermal/zx2967-thermal.txt | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v5 2/3] dmaeninge: xilinx_dma: Fix bug in multiple frame stores scenario in vdma
From: Rob Herring @ 2017-01-10 5:35 UTC (permalink / raw)
To: Kedareswara rao Appana
Cc: mark.rutland, moritz.fischer, Jose.Abreu, devicetree, vinod.koul,
michal.simek, linux-kernel, laurent.pinchart, luis, dmaengine,
dan.j.williams, appanad, soren.brinkmann, linux-arm-kernel
In-Reply-To: <1483771530-8545-3-git-send-email-appanad@xilinx.com>
On Sat, Jan 07, 2017 at 12:15:29PM +0530, Kedareswara rao Appana wrote:
> When VDMA is configured for more than one frame in the h/w
> for example h/w is configured for n number of frames and user
> Submits n number of frames and triggered the DMA using issue_pending API.
> In the current driver flow we are submitting one frame at a time
> but we should submit all the n number of frames at one time as the h/w
> Is configured for n number of frames.
>
> This patch fixes this issue.
>
> Reviewed-by: Jose Abreu <joabreu@synopsys.com>
> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
> ---
> Changes for v5:
> ---> Updated xlnx,fstore-config property to xlnx,fstore-enable
> and updated description as suggested by Rob.
> Changes for v4:
> ---> Add Check for framestore configuration on Transmit case as well
> as suggested by Jose Abreu.
> ---> Modified the dev_dbg checks to dev_warn checks as suggested
> by Jose Abreu.
> Changes for v3:
> ---> Added Checks for frame store configuration. If frame store
> Configuration is not present at the h/w level and user
> Submits less frames added debug prints in the driver as relevant.
> Changes for v2:
> ---> Fixed race conditions in the driver as suggested by Jose Abreu
> ---> Fixed unnecessray if else checks in the vdma_start_transfer
> as suggested by Laurent Pinchart.
>
> .../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 2 +
Acked-by: Rob Herring <robh@kernel.org>
> drivers/dma/xilinx/xilinx_dma.c | 78 +++++++++++++++-------
> 2 files changed, 57 insertions(+), 23 deletions(-)
^ permalink raw reply
* Re: [PATCH] adc: add adc driver for Hisilicon BVT SOCs
From: Rob Herring @ 2017-01-10 5:35 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Allen Liu, knaack.h, lars, pmeerw, mark.rutland, akinobu.mita,
ludovic.desroches, krzk, vilhelm.gray, ksenija.stanojevic,
zhiyong.tao, daniel.baluta, leonard.crestez, ray.jui,
raveendra.padasalagi, mranostay, amsfield22, linux-iio,
devicetree, linux-kernel, xuejiancheng, kevin.lixu
In-Reply-To: <41fbfc45-9f9a-c2cf-9c27-c4d5a39a400a@kernel.org>
On Sat, Jan 07, 2017 at 12:51:31PM -0500, Jonathan Cameron wrote:
> On 07/01/17 05:16, Allen Liu wrote:
> > Add ADC driver for the ADC controller found on HiSilicon BVT SOCs, like Hi3516CV300, etc.
> > The ADC controller is primarily in charge of detecting voltage.
> >
> > Reviewed-by: Kevin Li <kevin.lixu@hisilicon.com>
> > Signed-off-by: Allen Liu <liurenzhong@hisilicon.com>
> Hi Allen,
>
> One quick submission process note first. It is very important to clearly identify new
> versions of a patch and what changes have occurred since the previous posting.
>
> So the email title should have been [PATCH V2] adc...
>
> Also, below the --- please add a brief change log.
>
> The driver is coming together nicely. A few minor points inline.
>
> Jonathan
> > ---
> > .../devicetree/bindings/iio/adc/hibvt-lsadc.txt | 23 ++
> > drivers/iio/adc/Kconfig | 10 +
> > drivers/iio/adc/Makefile | 1 +
> > drivers/iio/adc/hibvt_lsadc.c | 335 +++++++++++++++++++++
> > 4 files changed, 369 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt
> > create mode 100644 drivers/iio/adc/hibvt_lsadc.c
> >
> > diff --git a/Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt b/Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt
> > new file mode 100644
> > index 0000000..fce1ff4
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt
> > @@ -0,0 +1,23 @@
> > +Hisilicon BVT Low Speed (LS) A/D Converter bindings
> > +
> > +Required properties:
> > +- compatible: should be "hisilicon,<name>-lsadc"
> > + - "hisilicon,hi3516cv300-lsadc": for hi3516cv300
> > +
> > +- reg: physical base address of the controller and length of memory mapped
> > + region.
> > +- interrupts: The interrupt number for the ADC device.
> Ideally refer to the standard interrupt binding document.
> Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
>
> > +
> > +Optional properties:
> > +- resets: Must contain an entry for each entry in reset-names if need support
> > + this option. See ../../reset/reset.txt for details.
> Don't use a relative path in a binding document. It's far too likely to
> be broken by a reorganization of the docs and cannot be grepped for.
However, in the filtered DT tree, the base path is already different. I
haven't looked but I'm sure we have a mixture of different forms.
My preference would be just "reset/reset.txt" or ".../reset/reset.txt".
We generally try to avoid bindings referring to other kernel docs, so
this should be sufficient.
Rob
^ permalink raw reply
* Re: [PATCH RFC 3/4] dt-bindings: correct marvell orion MDIO binding document
From: Rob Herring @ 2017-01-10 5:35 UTC (permalink / raw)
To: Russell King
Cc: Thomas Petazzoni, Andrew Lunn, Jason Cooper, Gregory Clement,
Mark Rutland, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Marcin Wojtas, Sebastian Hesselbarth,
netdev-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <E1cPpAk-0005uJ-TM-eh5Bv4kxaXIk46pC+1QYvQNdhmdF6hFW@public.gmane.org>
On Sat, Jan 07, 2017 at 11:28:30AM +0000, Russell King wrote:
> Correct the Marvell Orion MDIO binding document to properly reflect the
> cases where an interrupt is present. Augment the examples to show this.
>
> Signed-off-by: Russell King <rmk+kernel-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>
> ---
> .../devicetree/bindings/net/marvell-orion-mdio.txt | 17 +++++++++++++++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply
* Re: [PATCH] Documentation: display: fix wrong documentation paths
From: Rob Herring @ 2017-01-10 5:35 UTC (permalink / raw)
To: Yegor Yefremov; +Cc: linux-kernel, devicetree, airlied
In-Reply-To: <1483823686-9361-1-git-send-email-yegorslists@googlemail.com>
On Sat, Jan 07, 2017 at 10:14:45PM +0100, Yegor Yefremov wrote:
> Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
> ---
> Documentation/devicetree/bindings/display/arm,pl11x.txt | 2 +-
> Documentation/devicetree/bindings/display/bridge/analogix_dp.txt | 2 +-
> Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt | 2 +-
> Documentation/devicetree/bindings/display/exynos/exynos7-decon.txt | 2 +-
> Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt | 2 +-
> Documentation/devicetree/bindings/display/imx/fsl,imx-fb.txt | 2 +-
> Documentation/devicetree/bindings/display/imx/ldb.txt | 2 +-
> Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +-
> Documentation/devicetree/bindings/display/msm/dsi.txt | 2 +-
> Documentation/devicetree/bindings/display/msm/edp.txt | 2 +-
> Documentation/devicetree/bindings/display/msm/hdmi.txt | 2 +-
> Documentation/devicetree/bindings/display/panel/samsung,ld9040.txt | 2 +-
> Documentation/devicetree/bindings/display/panel/samsung,s6e8aa0.txt | 2 +-
> .../devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt | 2 +-
> Documentation/devicetree/bindings/display/tilcdc/panel.txt | 2 +-
> 15 files changed, 15 insertions(+), 15 deletions(-)
Applied, thanks.
Rob
^ permalink raw reply
* Re: [PATCH] of: remove redundant memset in overlay
From: Rob Herring @ 2017-01-10 5:35 UTC (permalink / raw)
To: YiPing Xu; +Cc: pantelis.antoniou, frowand.list, devicetree, linux-kernel
In-Reply-To: <1483787067-108430-1-git-send-email-xuyiping@hisilicon.com>
On Sat, Jan 07, 2017 at 07:04:27PM +0800, YiPing Xu wrote:
> From: XuYing <xuyiping@hisilicon.com>
>
> memset in of_build_overlay_info is redundant, the ovinfo has been
> zeroed in of_fill_overlay_info when error.
>
> Signed-off-by: YiPing Xu <xuyiping@hisilicon.com>
> ---
> drivers/of/overlay.c | 1 -
> 1 file changed, 1 deletion(-)
Applied, thanks.
Rob
^ permalink raw reply
* Re: [PATCH 1/4] Documentation: devicetree: Add vendor prefix for AsiaRF
From: Rob Herring @ 2017-01-10 5:35 UTC (permalink / raw)
To: Andreas Färber
Cc: linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Matthias Brugger,
Paul Lai, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Mark Rutland
In-Reply-To: <20170108133100.10428-2-afaerber-l3A5Bk7waGM@public.gmane.org>
On Sun, Jan 08, 2017 at 02:30:57PM +0100, Andreas Färber wrote:
> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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To unsubscribe from this list: send the line "unsubscribe devicetree" in
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More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 2/4] Documentation: devicetree: arm: mediatek: Add Geek Force board
From: Rob Herring @ 2017-01-10 5:36 UTC (permalink / raw)
To: Andreas Färber
Cc: linux-mediatek, Matthias Brugger, Paul Lai, linux-arm-kernel,
linux-kernel, devicetree, Mark Rutland
In-Reply-To: <20170108133100.10428-3-afaerber@suse.de>
On Sun, Jan 08, 2017 at 02:30:58PM +0100, Andreas Färber wrote:
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> Documentation/devicetree/bindings/arm/mediatek.txt | 3 +++
> 1 file changed, 3 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v4] iio:temperature: Add support for TI TMP007 sensor
From: Rob Herring @ 2017-01-10 5:36 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: jic23-DgEjT+Ai2ygdnm+yROfE0A, pmeerw-jW+XmwGofnusTnJN9+BGXg,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170109025526.GA9601-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Mon, Jan 09, 2017 at 08:25:26AM +0530, Manivannan Sadhasivam wrote:
> This patch adds support for TI TMP007 - 16 bit IR thermopile sensor with integrated Math engine.
> Sensor takes care of calculating the object temperature with the help of calibrated constants stored in non-volatile memory,
> thereby reducing the calculation overhead.
>
> Signed-off-by: Manivannan Sadhasivam <manivannanece23-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>
> Changes since v3:
>
> 1. Removed caching of status register
> 2. Modified comments for data validity
> 3. Added possible address combinations in dTree bindings file
>
> .../devicetree/bindings/iio/temperature/tmp007.txt | 27 ++
This could be documented under trivial-devices.txt, but doesn't hurt to
have it here.
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> drivers/iio/temperature/Kconfig | 10 +
> drivers/iio/temperature/Makefile | 1 +
> drivers/iio/temperature/tmp007.c | 345 +++++++++++++++++++++
> 4 files changed, 383 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/temperature/tmp007.txt
> create mode 100644 drivers/iio/temperature/tmp007.c
^ permalink raw reply
* Re: [PATCH v7 1/2] mtd: arasan: Add device tree binding documentation
From: Rob Herring @ 2017-01-10 5:36 UTC (permalink / raw)
To: Punnaiah Choudary Kalluri
Cc: dwmw2, computersforpeace, boris.brezillon, marek.vasut, richard,
cyrille.pitchen, mark.rutland, linux-kernel, linux-mtd,
devicetree, michals, kalluripunnaiahchoudary, kpc528,
Punnaiah Choudary Kalluri
In-Reply-To: <1483930734-10309-1-git-send-email-punnaia@xilinx.com>
On Mon, Jan 09, 2017 at 08:28:53AM +0530, Punnaiah Choudary Kalluri wrote:
> This patch adds the dts binding document for arasan nand flash
> controller.
>
> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
> ---
> Changes in v7:
> - Corrected the acronyms those should be in caps
> changes in v6:
> - Removed num-cs property
> - Separated nandchip from nand controller
> changes in v5:
> - None
> Changes in v4:
> - Added num-cs property
> - Added clock support
> Changes in v3:
> - None
> Changes in v2:
> - None
> ---
> .../devicetree/bindings/mtd/arasan_nfc.txt | 38 ++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/arasan_nfc.txt
>
> diff --git a/Documentation/devicetree/bindings/mtd/arasan_nfc.txt b/Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> new file mode 100644
> index 0000000..f20adfc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> @@ -0,0 +1,38 @@
> +Arasan NAND Flash Controller with ONFI 3.1 support
> +
> +Required properties:
> +- compatible: Should be "arasan,nfc-v3p10"
Needs a note that it must also have an SoC specific compatible string.
> +- reg: Memory map for module access
> +- interrupt-parent: Interrupt controller the interrupt is routed through
> +- interrupts: Should contain the interrupt for the device
> +- clock-name: List of input clocks - "clk_sys", "clk_flash"
clk_ is redundant.
> + (See clock bindings for details)
> +- clocks: Clock phandles (see clock bindings for details)
> +
> +Optional properties:
> +- arasan,has-mdma: Enables DMA support
> +
> +For NAND partition information please refer the below file
> +Documentation/devicetree/bindings/mtd/partition.txt
> +
> +Example:
> + nand0: nand@ff100000 {
> + compatible = "arasan,nfc-v3p10"
> + reg = <0x0 0xff100000 0x1000>;
> + clock-name = "clk_sys", "clk_flash"
> + clocks = <&misc_clk &misc_clk>;
> + interrupt-parent = <&gic>;
> + interrupts = <0 14 4>;
> + arasan,has-mdma;
> + #address-cells = <1>;
> + #size-cells = <0>
> +
> + nand@0 {
> + reg = <0>
> + partition@0 {
> + label = "filesystem";
> + reg = <0x0 0x0 0x1000000>;
> + };
> + (...)
> + };
> + };
> --
> 2.7.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v4 1/2] ARM: dts: at91: add devicetree for the Axentia TSE-850
From: Rob Herring @ 2017-01-10 5:36 UTC (permalink / raw)
To: Peter Rosin
Cc: linux-kernel, Mark Rutland, Russell King, Nicolas Ferre,
Alexandre Belloni, Jean-Christophe Plagniol-Villard,
linux-arm-kernel, devicetree
In-Reply-To: <1483951529-11738-2-git-send-email-peda@axentia.se>
On Mon, Jan 09, 2017 at 09:45:28AM +0100, Peter Rosin wrote:
> Signed-off-by: Peter Rosin <peda@axentia.se>
> ---
> Documentation/devicetree/bindings/arm/axentia.txt | 19 ++
> MAINTAINERS | 8 +
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/at91-linea.dtsi | 53 +++++
> arch/arm/boot/dts/at91-tse850-3.dts | 274 ++++++++++++++++++++++
> 5 files changed, 355 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/axentia.txt
> create mode 100644 arch/arm/boot/dts/at91-linea.dtsi
> create mode 100644 arch/arm/boot/dts/at91-tse850-3.dts
>
> diff --git a/Documentation/devicetree/bindings/arm/axentia.txt b/Documentation/devicetree/bindings/arm/axentia.txt
> new file mode 100644
> index 000000000000..ea3fb96ae465
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/axentia.txt
> @@ -0,0 +1,19 @@
> +Device tree bindings for Axentia ARM devices
> +============================================
> +
> +Linea CPU module
> +----------------
> +
> +Required root node properties:
> +compatible = "axentia,linea",
> + "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
> +and following the rules from atmel-at91.txt for a sama5d31 SoC.
> +
> +
> +TSE-850 v3 board
> +----------------
> +
> +Required root node properties:
> +compatible = "axentia,tse850v3", "axentia,linea",
> + "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
> +and following the rules from above for the axentia,linea CPU module.
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 97b78cc5aa51..5c2ea6e9cd7f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2346,6 +2346,14 @@ S: Maintained
> F: Documentation/devicetree/bindings/sound/axentia,*
> F: sound/soc/atmel/tse850-pcm5142.c
>
> +AXENTIA ARM DEVICES
> +M: Peter Rosin <peda@axentia.se>
> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> +S: Maintained
> +F: Documentation/devicetree/bindings/arm/axentia.txt
> +F: arch/arm/boot/dts/at91-linea.dtsi
> +F: arch/arm/boot/dts/at91-tse850-3.dts
> +
> AZ6007 DVB DRIVER
> M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
> M: Mauro Carvalho Chehab <mchehab@kernel.org>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 9a7375c388a8..7632849866de 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -48,6 +48,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
> at91-kizbox2.dtb \
> at91-sama5d2_xplained.dtb \
> at91-sama5d3_xplained.dtb \
> + at91-tse850-3.dtb \
> sama5d31ek.dtb \
> sama5d33ek.dtb \
> sama5d34ek.dtb \
> diff --git a/arch/arm/boot/dts/at91-linea.dtsi b/arch/arm/boot/dts/at91-linea.dtsi
> new file mode 100644
> index 000000000000..20d982153a45
> --- /dev/null
> +++ b/arch/arm/boot/dts/at91-linea.dtsi
> @@ -0,0 +1,53 @@
> +/*
> + * at91-linea.dtsi - Device Tree Include file for the Axentia Linea Module.
> + *
> + * Copyright (C) 2017 Axentia Technologies AB
> + *
> + * Author: Peter Rosin <peda@axentia.se>
> + *
> + * Licensed under GPLv2 or later.
> + */
> +
> +#include "sama5d31.dtsi"
> +
> +/ {
> + compatible = "axentia,linea",
> + "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
> +
> + memory {
memory@20000000 is preferred though if that causes bootloader problems
this is fine.
Acked-by: Rob Herring <robh@kernel.org>
Rob
^ permalink raw reply
* Re: [PATCH v3 4/5] dt: bindings: i2c-mux-pca954x: Add documentation for i2c-mux-irq-mask-en
From: Rob Herring @ 2017-01-10 5:36 UTC (permalink / raw)
To: Phil Reid; +Cc: peda, wsa, mark.rutland, linux-i2c, devicetree
In-Reply-To: <1483952576-5308-5-git-send-email-preid@electromag.com.au>
On Mon, Jan 09, 2017 at 05:02:55PM +0800, Phil Reid wrote:
> Unfortunately some hardware device will assert their irq line immediately
> on power on and provide no mechanism to mask the irq. As the i2c muxes
> provide no method to mask irq line this provides a work around by keeping
> the parent irq masked until enough device drivers have loaded to service
> all pending interrupts.
>
> For example the the ltc1760 assert its SMBALERT irq immediately on power
> on. With two ltc1760 attached to bus 0 & 1 on a pca954x mux when the first
> device is registered irq are enabled and fire continuously as the second
> device driver has not yet loaded. Setting this parameter to 0x3 while
> delay the irq being enabled until both devices are ready.
>
> Acked-by: Peter Rosin <peda@axentia.se>
> Signed-off-by: Phil Reid <preid@electromag.com.au>
> ---
> Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt | 3 +++
> 1 file changed, 3 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH] pinctrl: qcom: Add msm8998 pinctrl driver
From: Rob Herring @ 2017-01-10 5:36 UTC (permalink / raw)
To: Imran Khan
Cc: andy.gross, Linus Walleij, Mark Rutland, David Brown,
open list:PIN CONTROL SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:ARM/QUALCOMM SUPPORT,
open list:ARM/QUALCOMM SUPPORT
In-Reply-To: <1483974019-8235-1-git-send-email-kimran@codeaurora.org>
On Mon, Jan 09, 2017 at 08:30:17PM +0530, Imran Khan wrote:
> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for msm8998.
>
> Signed-off-by: Imran Khan <kimran@codeaurora.org>
> ---
> .../bindings/pinctrl/qcom,msm8998-pinctrl.txt | 200 ++
Acked-by: Rob Herring <robh@kernel.org>
> drivers/pinctrl/qcom/Kconfig | 8 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-msm8998.c | 1933 ++++++++++++++++++++
> 4 files changed, 2142 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
> create mode 100644 drivers/pinctrl/qcom/pinctrl-msm8998.c
^ permalink raw reply
* [PATCH] drivers: hwmon: fix semicolon.cocci warnings
From: Julia Lawall @ 2017-01-10 5:41 UTC (permalink / raw)
To: Jaghathiswari Rankappagounder Natarajan
Cc: openbmc, joel, jdelvare, linux, linux-hwmon, linux-kernel, corbet,
linux-doc, robh+dt, mark.rutland, devicetree, kbuild-all
Remove unneeded semicolon.
Generated by: scripts/coccinelle/misc/semicolon.cocci
CC: Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>
Signed-off-by: Julia Lawall <julia.lawall@lip6.fr>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
---
url:
https://github.com/0day-ci/linux/commits/Jaghathiswari-Rankappagounder-Natar
ajan/Support-for-ASPEED-AST2400-AST2500-PWM-and-Fan-Tach-driver/20170110-093
628
base:
https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git
hwmon-next
aspeed-pwm-tacho.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/hwmon/aspeed-pwm-tacho.c
+++ b/drivers/hwmon/aspeed-pwm-tacho.c
@@ -522,7 +522,7 @@ static u32 aspeed_get_fan_tach_ch_rpm(st
if (timeout > 1)
return 0;
msleep(sec);
- };
+ }
raw_data = (ioread32(base + ASPEED_PTCR_RESULT)) &
RESULT_VALUE_MASK;
^ permalink raw reply
* [PATCH] drivers: hwmon: fix device_node_continue.cocci warnings
From: Julia Lawall @ 2017-01-10 5:48 UTC (permalink / raw)
To: Jaghathiswari Rankappagounder Natarajan
Cc: openbmc, joel, jdelvare, linux, linux-hwmon, linux-kernel, corbet,
linux-doc, robh+dt, mark.rutland, devicetree, kbuild-all
Device node iterators put the previous value of the index variable, so an
explicit put causes a double put.
Generated by: scripts/coccinelle/iterators/device_node_continue.cocci
CC: Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>
Signed-off-by: Julia Lawall <julia.lawall@lip6.fr>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
---
The patch would not be needed if aspeed_create_type etc perform a second
get, beyond the one in the iterator.
aspeed-pwm-tacho.c | 3 ---
1 file changed, 3 deletions(-)
--- a/drivers/hwmon/aspeed-pwm-tacho.c
+++ b/drivers/hwmon/aspeed-pwm-tacho.c
@@ -833,21 +833,18 @@ static int aspeed_pwm_tacho_probe(struct
type_np = of_get_child_by_name(np, "type_values");
for_each_child_of_node(type_np, child) {
aspeed_create_type(child, priv, type_index++);
- of_node_put(child);
}
of_node_put(type_np);
pwm_np = of_get_child_by_name(np, "pwm_port");
for_each_child_of_node(pwm_np, child) {
aspeed_create_pwm_port(child, priv, pwm_index++,
group_index++);
- of_node_put(child);
}
of_node_put(pwm_np);
fan_tach_np = of_get_child_by_name(np, "fan_tach_channel");
for_each_child_of_node(fan_tach_np, child) {
aspeed_create_fan_tach_channel(&pdev->dev, child, priv,
fan_index++, group_index++);
- of_node_put(child);
}
of_node_put(fan_tach_np);
of_node_put(np);
^ permalink raw reply
* [PATCH] drivers: hwmon: fix ptr_ret.cocci warnings
From: Julia Lawall @ 2017-01-10 5:49 UTC (permalink / raw)
To: Jaghathiswari Rankappagounder Natarajan
Cc: openbmc-uLR06cmDAlY/bJ5BZ2RsiQ, joel-U3u1mxZcP9KHXe+LvDLADg,
jdelvare-IBi9RG/b67k, linux-0h96xk9xTtrk1uMJSBkQmQ,
linux-hwmon-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, corbet-T1hC0tSOHrs,
linux-doc-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
kbuild-all-JC7UmRfGjtg
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
Generated by: scripts/coccinelle/api/ptr_ret.cocci
CC: Jaghathiswari Rankappagounder Natarajan <jaghu-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Signed-off-by: Julia Lawall <julia.lawall-L2FTfq7BK8M@public.gmane.org>
Signed-off-by: Fengguang Wu <fengguang.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
---
aspeed-pwm-tacho.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
--- a/drivers/hwmon/aspeed-pwm-tacho.c
+++ b/drivers/hwmon/aspeed-pwm-tacho.c
@@ -855,10 +855,7 @@ static int aspeed_pwm_tacho_probe(struct
hwmon = devm_hwmon_device_register_with_groups(&pdev->dev,
"aspeed_pwm_tacho",
priv, priv->groups);
- if (IS_ERR(hwmon))
- return PTR_ERR(hwmon);
-
- return 0;
+ return PTR_ERR_OR_ZERO(hwmon);
}
static const struct of_device_id of_pwm_tacho_match_table[] = {
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH] drivers: hwmon: fix platform_no_drv_owner.cocci warnings
From: Julia Lawall @ 2017-01-10 5:50 UTC (permalink / raw)
To: Jaghathiswari Rankappagounder Natarajan
Cc: openbmc-uLR06cmDAlY/bJ5BZ2RsiQ, joel-U3u1mxZcP9KHXe+LvDLADg,
jdelvare-IBi9RG/b67k, linux-0h96xk9xTtrk1uMJSBkQmQ,
linux-hwmon-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, corbet-T1hC0tSOHrs,
linux-doc-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA
Remove .owner field if calls are used which set it automatically
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
CC: Jaghathiswari Rankappagounder Natarajan <jaghu-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Signed-off-by: Julia Lawall <julia.lawall-L2FTfq7BK8M@public.gmane.org>
Signed-off-by: Fengguang Wu <fengguang.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
---
aspeed-pwm-tacho.c | 1 -
1 file changed, 1 deletion(-)
--- a/drivers/hwmon/aspeed-pwm-tacho.c
+++ b/drivers/hwmon/aspeed-pwm-tacho.c
@@ -872,7 +872,6 @@ static struct platform_driver aspeed_pwm
.probe = aspeed_pwm_tacho_probe,
.driver = {
.name = "aspeed_pwm_tacho",
- .owner = THIS_MODULE,
.of_match_table = of_pwm_tacho_match_table,
},
};
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v7 1/2] mtd: arasan: Add device tree binding documentation
From: Punnaiah Choudary @ 2017-01-10 6:00 UTC (permalink / raw)
To: Rob Herring
Cc: Punnaiah Choudary Kalluri, dwmw2@infradead.org, Brian Norris,
boris.brezillon, marek.vasut, richard, cyrille.pitchen,
Mark Rutland, linux-kernel@vger.kernel.org,
linux-mtd@lists.infradead.org, devicetree@vger.kernel.org,
michals, punnaia, Punnaiah Choudary Kalluri
In-Reply-To: <20170110053605.yqclykdgi3tgndnp@rob-hp-laptop>
[-- Attachment #1: Type: text/plain, Size: 3257 bytes --]
Hi Rob,
Thanks for the review.
On Tue, Jan 10, 2017 at 11:06 AM, Rob Herring <robh@kernel.org> wrote:
> On Mon, Jan 09, 2017 at 08:28:53AM +0530, Punnaiah Choudary Kalluri wrote:
> > This patch adds the dts binding document for arasan nand flash
> > controller.
> >
> > Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
> > ---
> > Changes in v7:
> > - Corrected the acronyms those should be in caps
> > changes in v6:
> > - Removed num-cs property
> > - Separated nandchip from nand controller
> > changes in v5:
> > - None
> > Changes in v4:
> > - Added num-cs property
> > - Added clock support
> > Changes in v3:
> > - None
> > Changes in v2:
> > - None
> > ---
> > .../devicetree/bindings/mtd/arasan_nfc.txt | 38
> ++++++++++++++++++++++
> > 1 file changed, 38 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> >
> > diff --git a/Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> b/Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> > new file mode 100644
> > index 0000000..f20adfc
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> > @@ -0,0 +1,38 @@
> > +Arasan NAND Flash Controller with ONFI 3.1 support
> > +
> > +Required properties:
> > +- compatible: Should be "arasan,nfc-v3p10"
>
> Needs a note that it must also have an SoC specific compatible string.
>
Sorry, i couldnt understand this comment. could you elaborate bit
>
> > +- reg: Memory map for module access
> > +- interrupt-parent: Interrupt controller the interrupt is routed through
> > +- interrupts: Should contain the interrupt for the device
> > +- clock-name: List of input clocks - "clk_sys", "clk_flash"
>
> clk_ is redundant.
>
I have defined these clock names as per the controller data sheet.
So, i feel it is fine to have them in sync with the datasheet.
Please let me know if you still want me to change this.
> > + (See clock bindings for details)
> > +- clocks: Clock phandles (see clock bindings for details)
> > +
> > +Optional properties:
> > +- arasan,has-mdma: Enables DMA support
> > +
> > +For NAND partition information please refer the below file
> > +Documentation/devicetree/bindings/mtd/partition.txt
> > +
> > +Example:
> > + nand0: nand@ff100000 {
> > + compatible = "arasan,nfc-v3p10"
> > + reg = <0x0 0xff100000 0x1000>;
> > + clock-name = "clk_sys", "clk_flash"
> > + clocks = <&misc_clk &misc_clk>;
> > + interrupt-parent = <&gic>;
> > + interrupts = <0 14 4>;
> > + arasan,has-mdma;
> > + #address-cells = <1>;
> > + #size-cells = <0>
> > +
> > + nand@0 {
> > + reg = <0>
> > + partition@0 {
> > + label = "filesystem";
> > + reg = <0x0 0x0 0x1000000>;
> > + };
> > + (...)
> > + };
> > + };
> > --
> > 2.7.4
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe devicetree" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
>
[-- Attachment #2: Type: text/html, Size: 5189 bytes --]
^ permalink raw reply
* RE: [PATCH v7 1/2] mtd: arasan: Add device tree binding documentation
From: Punnaiah Choudary Kalluri @ 2017-01-10 6:03 UTC (permalink / raw)
To: Rob Herring
Cc: dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org,
computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org,
marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
richard-/L3Ra7n9ekc@public.gmane.org,
cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Michal Simek,
kalluripunnaiahchoudary-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
kpc528-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
In-Reply-To: <20170110053605.yqclykdgi3tgndnp@rob-hp-laptop>
Hi Rob,
Thanks for the review.
> -----Original Message-----
> From: Rob Herring [mailto:robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
> Sent: Tuesday, January 10, 2017 11:06 AM
> To: Punnaiah Choudary Kalluri <punnaia-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> Cc: dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org; computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org;
> boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org; marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org;
> richard-/L3Ra7n9ekc@public.gmane.org; cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org; mark.rutland-5wv7dgnIgG8@public.gmane.org; linux-
> kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org;
> devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Michal Simek <michals-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>;
> kalluripunnaiahchoudary-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; kpc528-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; Punnaiah
> Choudary Kalluri <punnaia-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> Subject: Re: [PATCH v7 1/2] mtd: arasan: Add device tree binding
> documentation
>
> On Mon, Jan 09, 2017 at 08:28:53AM +0530, Punnaiah Choudary Kalluri wrote:
> > This patch adds the dts binding document for arasan nand flash
> > controller.
> >
> > Signed-off-by: Punnaiah Choudary Kalluri <punnaia-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> > ---
> > Changes in v7:
> > - Corrected the acronyms those should be in caps
> > changes in v6:
> > - Removed num-cs property
> > - Separated nandchip from nand controller
> > changes in v5:
> > - None
> > Changes in v4:
> > - Added num-cs property
> > - Added clock support
> > Changes in v3:
> > - None
> > Changes in v2:
> > - None
> > ---
> > .../devicetree/bindings/mtd/arasan_nfc.txt | 38
> ++++++++++++++++++++++
> > 1 file changed, 38 insertions(+)
> > create mode 100644
> Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> >
> > diff --git a/Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> b/Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> > new file mode 100644
> > index 0000000..f20adfc
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mtd/arasan_nfc.txt
> > @@ -0,0 +1,38 @@
> > +Arasan NAND Flash Controller with ONFI 3.1 support
> > +
> > +Required properties:
> > +- compatible: Should be "arasan,nfc-v3p10"
>
> Needs a note that it must also have an SoC specific compatible string.
>
Sorry, I couldn't understand this comment. Could you elaborate it?
> > +- reg: Memory map for module access
> > +- interrupt-parent: Interrupt controller the interrupt is routed through
> > +- interrupts: Should contain the interrupt for the device
> > +- clock-name: List of input clocks - "clk_sys", "clk_flash"
>
> clk_ is redundant.
>
I have defined these clock names as per the controller data sheet.
So, I feel it is fine to have them in sync with the datasheet.
Please let me know if you still want me to change this.
Regards,
Punnaiah
> > + (See clock bindings for details)
> > +- clocks: Clock phandles (see clock bindings for details)
> > +
> > +Optional properties:
> > +- arasan,has-mdma: Enables DMA support
> > +
> > +For NAND partition information please refer the below file
> > +Documentation/devicetree/bindings/mtd/partition.txt
> > +
> > +Example:
> > + nand0: nand@ff100000 {
> > + compatible = "arasan,nfc-v3p10"
> > + reg = <0x0 0xff100000 0x1000>;
> > + clock-name = "clk_sys", "clk_flash"
> > + clocks = <&misc_clk &misc_clk>;
> > + interrupt-parent = <&gic>;
> > + interrupts = <0 14 4>;
> > + arasan,has-mdma;
> > + #address-cells = <1>;
> > + #size-cells = <0>
> > +
> > + nand@0 {
> > + reg = <0>
> > + partition@0 {
> > + label = "filesystem";
> > + reg = <0x0 0x0 0x1000000>;
> > + };
> > + (...)
> > + };
> > + };
> > --
> > 2.7.4
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe devicetree" in
> > the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
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^ permalink raw reply
* Re: [PATCH v4 1/2] ARM: dts: at91: add devicetree for the Axentia TSE-850
From: Peter Rosin @ 2017-01-10 6:07 UTC (permalink / raw)
To: Rob Herring
Cc: linux-kernel, Mark Rutland, Russell King, Nicolas Ferre,
Alexandre Belloni, Jean-Christophe Plagniol-Villard,
linux-arm-kernel, devicetree
In-Reply-To: <20170110053606.sqtnsbuawwa6s535@rob-hp-laptop>
On 2017-01-10 06:36, Rob Herring wrote:
> On Mon, Jan 09, 2017 at 09:45:28AM +0100, Peter Rosin wrote:
>> Signed-off-by: Peter Rosin <peda@axentia.se>
>> ---
>> Documentation/devicetree/bindings/arm/axentia.txt | 19 ++
>> MAINTAINERS | 8 +
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/at91-linea.dtsi | 53 +++++
>> arch/arm/boot/dts/at91-tse850-3.dts | 274 ++++++++++++++++++++++
>> 5 files changed, 355 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/axentia.txt
>> create mode 100644 arch/arm/boot/dts/at91-linea.dtsi
>> create mode 100644 arch/arm/boot/dts/at91-tse850-3.dts
>>
>> diff --git a/Documentation/devicetree/bindings/arm/axentia.txt b/Documentation/devicetree/bindings/arm/axentia.txt
>> new file mode 100644
>> index 000000000000..ea3fb96ae465
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/axentia.txt
>> @@ -0,0 +1,19 @@
>> +Device tree bindings for Axentia ARM devices
>> +============================================
>> +
>> +Linea CPU module
>> +----------------
>> +
>> +Required root node properties:
>> +compatible = "axentia,linea",
>> + "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
>> +and following the rules from atmel-at91.txt for a sama5d31 SoC.
>> +
>> +
>> +TSE-850 v3 board
>> +----------------
>> +
>> +Required root node properties:
>> +compatible = "axentia,tse850v3", "axentia,linea",
>> + "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
>> +and following the rules from above for the axentia,linea CPU module.
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 97b78cc5aa51..5c2ea6e9cd7f 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -2346,6 +2346,14 @@ S: Maintained
>> F: Documentation/devicetree/bindings/sound/axentia,*
>> F: sound/soc/atmel/tse850-pcm5142.c
>>
>> +AXENTIA ARM DEVICES
>> +M: Peter Rosin <peda@axentia.se>
>> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
>> +S: Maintained
>> +F: Documentation/devicetree/bindings/arm/axentia.txt
>> +F: arch/arm/boot/dts/at91-linea.dtsi
>> +F: arch/arm/boot/dts/at91-tse850-3.dts
>> +
>> AZ6007 DVB DRIVER
>> M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
>> M: Mauro Carvalho Chehab <mchehab@kernel.org>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 9a7375c388a8..7632849866de 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -48,6 +48,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
>> at91-kizbox2.dtb \
>> at91-sama5d2_xplained.dtb \
>> at91-sama5d3_xplained.dtb \
>> + at91-tse850-3.dtb \
>> sama5d31ek.dtb \
>> sama5d33ek.dtb \
>> sama5d34ek.dtb \
>> diff --git a/arch/arm/boot/dts/at91-linea.dtsi b/arch/arm/boot/dts/at91-linea.dtsi
>> new file mode 100644
>> index 000000000000..20d982153a45
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/at91-linea.dtsi
>> @@ -0,0 +1,53 @@
>> +/*
>> + * at91-linea.dtsi - Device Tree Include file for the Axentia Linea Module.
>> + *
>> + * Copyright (C) 2017 Axentia Technologies AB
>> + *
>> + * Author: Peter Rosin <peda@axentia.se>
>> + *
>> + * Licensed under GPLv2 or later.
>> + */
>> +
>> +#include "sama5d31.dtsi"
>> +
>> +/ {
>> + compatible = "axentia,linea",
>> + "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
>> +
>> + memory {
>
> memory@20000000 is preferred though if that causes bootloader problems
> this is fine.
But then I get a dtb with one memory node from sama5d3.dtsi with
reg = <0x20000000 0x8000000> and one memory@20000000 node with this
different reg content. Not pretty. Is that really preferred, even
if it works?
> Acked-by: Rob Herring <robh@kernel.org>
Thanks!
Cheers,
peda
^ permalink raw reply
* Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy
From: Vivek Gautam @ 2017-01-10 6:07 UTC (permalink / raw)
To: Jaehoon Chung, linux-pci-u79uwXL29TY76Z2rM5mHXA
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, kgene-DgEjT+Ai2ygdnm+yROfE0A,
krzk-DgEjT+Ai2ygdnm+yROfE0A, kishon-l0cyMroinI0,
jingoohan1-Re5JQEeQqe8AvxtiuMwx3w,
pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ,
alim.akhtar-Sze3O3UU22JBDgjK7y7TUQ, cpgs-Sze3O3UU22JBDgjK7y7TUQ
In-Reply-To: <20170104123435.30740-3-jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Hi Jaehoon,
On 01/04/2017 06:04 PM, Jaehoon Chung wrote:
> This patch supports to use Generic Phy framework for Exynos PCIe phy.
> When Exynos that supported the pcie want to use the PCIe,
> it needs to control the phy resgister.
> But it should be more complex to control in their own PCIe device drivers.
>
> Currently, there is an exynos5440 case to support the pcie.
> So this driver is based on Exynos5440 PCIe.
> In future, will support the Other exynos SoCs likes exynos5433, exynos7.
>
> Signed-off-by: Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> ---
> Changelog on V2:
> - Not include the codes relevant to pci-exynos.
> - Remove the getting child node.
>
> drivers/phy/Kconfig | 9 ++
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-exynos-pcie.c | 280 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 290 insertions(+)
> create mode 100644 drivers/phy/phy-exynos-pcie.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index e8eb7f2..2dddef4 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -331,6 +331,15 @@ config PHY_EXYNOS5_USBDRD
> This driver provides PHY interface for USB 3.0 DRD controller
> present on Exynos5 SoC series.
>
> +config PHY_EXYNOS_PCIE
> + bool "Exynos PCIe PHY driver"
> + depends on ARCH_EXYNOS && OF
> + depends on PCI_EXYNOS
> + select GENERIC_PHY
> + help
> + Enable PCIe PHY support for Exynos SoC series.
> + This driver provides PHY interface for Exynos PCIe controller.
> +
> config PHY_PISTACHIO_USB
> tristate "IMG Pistachio USB2.0 PHY driver"
> depends on MACH_PISTACHIO
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 65eb2f4..081aeb4 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o
> phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
> phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
> obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
> +obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
> obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
> obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
> diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
> new file mode 100644
> index 0000000..b57f49b
> --- /dev/null
> +++ b/drivers/phy/phy-exynos-pcie.c
> @@ -0,0 +1,280 @@
> +/*
> + * Samsung EXYNOS SoC series PCIe PHY driver
> + *
> + * Phy provider for PCIe controller on Exynos SoC series
> + *
> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.
> + * Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +
> +/* PCIe Purple registers */
> +#define PCIE_PHY_GLOBAL_RESET 0x000
> +#define PCIE_PHY_COMMON_RESET 0x004
> +#define PCIE_PHY_CMN_REG 0x008
> +#define PCIE_PHY_MAC_RESET 0x00c
> +#define PCIE_PHY_PLL_LOCKED 0x010
> +#define PCIE_PHY_TRSVREG_RESET 0x020
> +#define PCIE_PHY_TRSV_RESET 0x024
> +
> +/* PCIe PHY registers */
> +#define PCIE_PHY_IMPEDANCE 0x004
> +#define PCIE_PHY_PLL_DIV_0 0x008
> +#define PCIE_PHY_PLL_BIAS 0x00c
> +#define PCIE_PHY_DCC_FEEDBACK 0x014
> +#define PCIE_PHY_PLL_DIV_1 0x05c
> +#define PCIE_PHY_COMMON_POWER 0x064
> +#define PCIE_PHY_COMMON_PD_CMN BIT(3)
> +#define PCIE_PHY_TRSV0_EMP_LVL 0x084
> +#define PCIE_PHY_TRSV0_DRV_LVL 0x088
> +#define PCIE_PHY_TRSV0_RXCDR 0x0ac
> +#define PCIE_PHY_TRSV0_POWER 0x0c4
> +#define PCIE_PHY_TRSV0_PD_TSV BIT(7)
> +#define PCIE_PHY_TRSV0_LVCC 0x0dc
> +#define PCIE_PHY_TRSV1_EMP_LVL 0x144
> +#define PCIE_PHY_TRSV1_RXCDR 0x16c
> +#define PCIE_PHY_TRSV1_POWER 0x184
> +#define PCIE_PHY_TRSV1_PD_TSV BIT(7)
> +#define PCIE_PHY_TRSV1_LVCC 0x19c
> +#define PCIE_PHY_TRSV2_EMP_LVL 0x204
> +#define PCIE_PHY_TRSV2_RXCDR 0x22c
> +#define PCIE_PHY_TRSV2_POWER 0x244
> +#define PCIE_PHY_TRSV2_PD_TSV BIT(7)
> +#define PCIE_PHY_TRSV2_LVCC 0x25c
> +#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
> +#define PCIE_PHY_TRSV3_RXCDR 0x2ec
> +#define PCIE_PHY_TRSV3_POWER 0x304
> +#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
> +#define PCIE_PHY_TRSV3_LVCC 0x31c
> +
> +struct exynos_pcie_phy_data {
> + struct phy_ops *ops;
> +};
> +
> +/* For Exynos pcie phy */
> +struct exynos_pcie_phy {
> + const struct exynos_pcie_phy_data *drv_data;
> + void __iomem *phy_base;
> + void __iomem *blk_base; /* For exynos5440 */
> +};
> +
> +static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
> +{
> + writel(val, base + offset);
> +}
> +
> +static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset)
> +{
> + return readl(base + offset);
> +}
> +
> +/* For Exynos5440 specific functions */
> +static int exynos5440_pcie_phy_init(struct phy *phy)
> +{
> + struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> +
> + /* DCC feedback control off */
> + exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
> +
> + /* set TX/RX impedance */
> + exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
> +
> + /* set 50Mhz PHY clock */
> + exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
> + exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
> +
> + /* set TX Differential output for lane 0 */
> + exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
> +
> + /* set TX Pre-emphasis Level Control for lane 0 to minimum */
> + exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
> +
> + /* set RX clock and data recovery bandwidth */
> + exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
> + exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
> + exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
> + exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
> + exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
> +
> + /* change TX Pre-emphasis Level Control for lanes */
> + exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
> + exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
> + exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
> + exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
> +
> + /* set LVCC */
> + exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
> + exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
> + exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
> + exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
> +
> + /* pulse for common reset */
> + exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET);
> + udelay(500);
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
> +
> + return 0;
> +}
> +
> +static int exynos5440_pcie_phy_power_on(struct phy *phy)
> +{
> + struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> + u32 val;
> +
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG);
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET);
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
> + val &= ~PCIE_PHY_COMMON_PD_CMN;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
> + val &= ~PCIE_PHY_TRSV0_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
> + val &= ~PCIE_PHY_TRSV1_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
> + val &= ~PCIE_PHY_TRSV2_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
> + val &= ~PCIE_PHY_TRSV3_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
> +
> + return 0;
> +}
> +
> +static int exynos5440_pcie_phy_power_off(struct phy *phy)
> +{
> + struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> + u32 val;
> +
> + while (exynos_pcie_phy_readl(ep->phy_base,
> + PCIE_PHY_PLL_LOCKED) == 0) {
No timeout for this ? Is it possible that the PLL was never locked
and this ends up in infinite loop.
Please use a readl_poll_timeout() instead.
> + val = exynos_pcie_phy_readl(ep->blk_base,
> + PCIE_PHY_PLL_LOCKED);
it is possible that the while condition check above is true (the
register reads to 0),
but this assignment makes ' val = 1' ?
If that the case then debug message below can be misleading.
> + dev_info(&phy->dev, "PLL Locked: 0x%x\n", val);
Possibly, you don't want to fill up the console with these logs until
the PLL is locked. dev_dbg() ?
> + }
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
> + val |= PCIE_PHY_COMMON_PD_CMN;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
> + val |= PCIE_PHY_TRSV0_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
> + val |= PCIE_PHY_TRSV1_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
> + val |= PCIE_PHY_TRSV2_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
> + val |= PCIE_PHY_TRSV3_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
> +
> + return 0;
> +}
> +
> +static int exynos5440_pcie_phy_reset(struct phy *phy)
> +{
> + struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> +
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET);
> + exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET);
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET);
> +
> + return 0;
> +}
> +
> +static struct phy_ops exynos5440_phy_ops = {
const ?
> + .init = exynos5440_pcie_phy_init,
> + .power_on = exynos5440_pcie_phy_power_on,
> + .power_off = exynos5440_pcie_phy_power_off,
> + .reset = exynos5440_pcie_phy_reset,
> +};
> +
> +static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = {
> + .ops = &exynos5440_phy_ops,
> +};
> +
> +static const struct of_device_id exynos_pcie_phy_match[] = {
> + {
> + .compatible = "samsung,exynos5440-pcie-phy",
> + .data = &exynos5440_pcie_phy_data,
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, exynos_pcie_phy_match);
> +
> +static int exynos_pcie_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct exynos_pcie_phy *exynos_phy;
> + struct phy *generic_phy;
> + struct phy_provider *phy_provider;
> + struct resource *res;
> + const struct exynos_pcie_phy_data *drv_data;
> +
> + drv_data = of_device_get_match_data(dev);
> + if (!drv_data)
> + return -ENODEV;
> +
> + exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
> + if (!exynos_phy)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + exynos_phy->phy_base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(exynos_phy->phy_base))
> + return PTR_ERR(exynos_phy->phy_base);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> + exynos_phy->blk_base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(exynos_phy->phy_base))
> + return PTR_ERR(exynos_phy->phy_base);
> +
> + exynos_phy->drv_data = drv_data;
> +
> + generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops);
> + if (IS_ERR(generic_phy)) {
> + dev_err(dev, "failed to create PHY\n");
> + return PTR_ERR(generic_phy);
> + }
> +
> + phy_set_drvdata(generic_phy, exynos_phy);
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> + return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static struct platform_driver exynos_pcie_phy_driver = {
> + .probe = exynos_pcie_phy_probe,
> + .driver = {
> + .of_match_table = exynos_pcie_phy_match,
> + .name = "exynos_pcie_phy",
> + }
> +};
> +module_platform_driver(exynos_pcie_phy_driver);
MODULE_LICENSE("GPL") ??
MODULE_DESCRIPTION() as well.
Regards
Vivek
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