* Re: [PATCH v2 1/2] devicetree: add Garmin vendor prefix
From: Marek Vasut @ 2017-01-17 1:52 UTC (permalink / raw)
To: Matt Ranostay
Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Jonathan Cameron, Rob Herring
In-Reply-To: <CAJ_EiSQ+kfNnoDsed67v_1CLui7Fp2qMsx67bYMvQ0Y98jO+Aw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 01/17/2017 02:50 AM, Matt Ranostay wrote:
> On Mon, Jan 16, 2017 at 5:07 PM, Marek Vasut <marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>> On 12/29/2016 06:13 AM, Matt Ranostay wrote:
>>
>> Some commit message / description of the company would be useful.
>>
>>> Cc: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>>> Signed-off-by: Matt Ranostay <matt-sk+viVC6FLCDq+mSdOJa79kegs52MxvZ@public.gmane.org>
>>> ---
>>> Changes from v1:
>>> * switch to stock ticker for Garmin Limited
>>>
>>> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
>>> index 16d3b5e7f5d1..5749bfc5fc5b 100644
>>> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
>>> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
>>> @@ -107,6 +107,7 @@ firefly Firefly
>>> focaltech FocalTech Systems Co.,Ltd
>>> friendlyarm Guangzhou FriendlyARM Computer Tech Co., Ltd
>>> fsl Freescale Semiconductor
>>> +grmn Garmin Limited
>>
>> Why grmn ? Why not 'garmin' ? Also, the rest uses Ltd. , so make it
>> consistent ?
>>
>
> As already stated GRMN is the US stock ticker... and is the "correct way" :)
So we should use the US stock tickers for DT vendor prefixes now ?
>>> ge General Electric Company
>>> geekbuying GeekBuying
>>> gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
>>>
>>
>>
>> --
>> Best regards,
>> Marek Vasut
--
Best regards,
Marek Vasut
^ permalink raw reply
* Re: [PATCH v11 03/12] drm/mediatek: add *driver_data for different hardware settings
From: CK Hu @ 2017-01-17 2:37 UTC (permalink / raw)
To: YT Shen
Cc: Mark Rutland, devicetree, srv_heupstream, emil.l.velikov,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Matthias Brugger, yingjoe.chen, linux-arm-kernel
In-Reply-To: <1484117473-46644-4-git-send-email-yt.shen@mediatek.com>
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> There are some hardware settings changed, between MT8173 & MT2701:
> DISP_OVL address offset changed, color format definition changed.
> DISP_RDMA fifo size changed.
> DISP_COLOR offset changed.
> MIPI_TX pll setting changed.
> And add prefix for mtk_ddp_main & mtk_ddp_ext & mutex_mod.
>
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 41 ++++++++++++-----
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 18 +++++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 71 +++++++++++++++--------------
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 57 +++++++++++++++++++----
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 25 +++++++---
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 ++++
> drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 24 +++++++++-
> 7 files changed, 181 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index ce2759f..4552178 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -35,18 +35,27 @@
> #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n))
> #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n))
> #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n))
> -#define DISP_REG_OVL_ADDR(n) (0x0f40 + 0x20 * (n))
> +#define DISP_REG_OVL_ADDR_MT8173 0x0f40
> +#define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n))
>
> #define OVL_RDMA_MEM_GMC 0x40402020
>
> #define OVL_CON_BYTE_SWAP BIT(24)
> -#define OVL_CON_CLRFMT_RGB565 (0 << 12)
> -#define OVL_CON_CLRFMT_RGB888 (1 << 12)
> +#define OVL_CON_CLRFMT_RGB (1 << 12)
> #define OVL_CON_CLRFMT_RGBA8888 (2 << 12)
> #define OVL_CON_CLRFMT_ARGB8888 (3 << 12)
> +#define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
> + 0 : OVL_CON_CLRFMT_RGB)
> +#define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
> + OVL_CON_CLRFMT_RGB : 0)
> #define OVL_CON_AEN BIT(8)
> #define OVL_CON_ALPHA 0xff
>
> +struct mtk_disp_ovl_data {
> + unsigned int addr;
> + bool fmt_rgb565_is_0;
> +};
> +
> /**
> * struct mtk_disp_ovl - DISP_OVL driver structure
> * @ddp_comp - structure containing type enum and hardware resources
> @@ -55,6 +64,7 @@
> struct mtk_disp_ovl {
> struct mtk_ddp_comp ddp_comp;
> struct drm_crtc *crtc;
> + const struct mtk_disp_ovl_data *data;
> };
>
> static inline struct mtk_disp_ovl *comp_to_ovl(struct mtk_ddp_comp *comp)
> @@ -141,18 +151,18 @@ static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx)
> writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
> }
>
> -static unsigned int ovl_fmt_convert(unsigned int fmt)
> +static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
> {
> switch (fmt) {
> default:
> case DRM_FORMAT_RGB565:
> - return OVL_CON_CLRFMT_RGB565;
> + return OVL_CON_CLRFMT_RGB565(ovl);
> case DRM_FORMAT_BGR565:
> - return OVL_CON_CLRFMT_RGB565 | OVL_CON_BYTE_SWAP;
> + return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP;
> case DRM_FORMAT_RGB888:
> - return OVL_CON_CLRFMT_RGB888;
> + return OVL_CON_CLRFMT_RGB888(ovl);
> case DRM_FORMAT_BGR888:
> - return OVL_CON_CLRFMT_RGB888 | OVL_CON_BYTE_SWAP;
> + return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;
> case DRM_FORMAT_RGBX8888:
> case DRM_FORMAT_RGBA8888:
> return OVL_CON_CLRFMT_ARGB8888;
> @@ -171,6 +181,7 @@ static unsigned int ovl_fmt_convert(unsigned int fmt)
> static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> struct mtk_plane_state *state)
> {
> + struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
> struct mtk_plane_pending_state *pending = &state->pending;
> unsigned int addr = pending->addr;
> unsigned int pitch = pending->pitch & 0xffff;
> @@ -182,7 +193,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> if (!pending->enable)
> mtk_ovl_layer_off(comp, idx);
>
> - con = ovl_fmt_convert(fmt);
> + con = ovl_fmt_convert(ovl, fmt);
> if (idx != 0)
> con |= OVL_CON_AEN | OVL_CON_ALPHA;
>
> @@ -190,7 +201,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx));
> writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx));
> writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx));
> - writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(idx));
> + writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(ovl, idx));
>
> if (pending->enable)
> mtk_ovl_layer_on(comp, idx);
> @@ -267,6 +278,8 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev)
> return ret;
> }
>
> + priv->data = of_device_get_match_data(dev);
> +
> platform_set_drvdata(pdev, priv);
>
> ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
> @@ -290,8 +303,14 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev)
> return 0;
> }
>
> +static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
> + .addr = DISP_REG_OVL_ADDR_MT8173,
> + .fmt_rgb565_is_0 = true,
> +};
> +
> static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
> - { .compatible = "mediatek,mt8173-disp-ovl", },
> + { .compatible = "mediatek,mt8173-disp-ovl",
> + .data = &mt8173_ovl_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 21eff6f..e5e5318 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -38,6 +38,11 @@
> #define RDMA_FIFO_UNDERFLOW_EN BIT(31)
> #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16)
> #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
> +#define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size)
> +
> +struct mtk_disp_rdma_data {
> + unsigned int fifo_size;
> +};
>
> /**
> * struct mtk_disp_rdma - DISP_RDMA driver structure
> @@ -47,6 +52,7 @@
> struct mtk_disp_rdma {
> struct mtk_ddp_comp ddp_comp;
> struct drm_crtc *crtc;
> + const struct mtk_disp_rdma_data *data;
> };
>
> static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
> @@ -114,6 +120,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> {
> unsigned int threshold;
> unsigned int reg;
> + struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
>
> rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
> rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
> @@ -126,7 +133,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> */
> threshold = width * height * vrefresh * 4 * 7 / 1000000;
> reg = RDMA_FIFO_UNDERFLOW_EN |
> - RDMA_FIFO_PSEUDO_SIZE(SZ_8K) |
> + RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) |
> RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
> writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
> }
> @@ -211,6 +218,8 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev)
> return ret;
> }
>
> + priv->data = of_device_get_match_data(dev);
> +
> platform_set_drvdata(pdev, priv);
>
> ret = component_add(dev, &mtk_disp_rdma_component_ops);
> @@ -227,8 +236,13 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev)
> return 0;
> }
>
> +static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = {
> + .fifo_size = SZ_8K,
> +};
> +
> static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
> - { .compatible = "mediatek,mt8173-disp-rdma", },
> + { .compatible = "mediatek,mt8173-disp-rdma",
> + .data = &mt8173_rdma_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 17ba935..8030769 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -36,21 +36,21 @@
> #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
> #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
>
> -#define MUTEX_MOD_DISP_OVL0 BIT(11)
> -#define MUTEX_MOD_DISP_OVL1 BIT(12)
> -#define MUTEX_MOD_DISP_RDMA0 BIT(13)
> -#define MUTEX_MOD_DISP_RDMA1 BIT(14)
> -#define MUTEX_MOD_DISP_RDMA2 BIT(15)
> -#define MUTEX_MOD_DISP_WDMA0 BIT(16)
> -#define MUTEX_MOD_DISP_WDMA1 BIT(17)
> -#define MUTEX_MOD_DISP_COLOR0 BIT(18)
> -#define MUTEX_MOD_DISP_COLOR1 BIT(19)
> -#define MUTEX_MOD_DISP_AAL BIT(20)
> -#define MUTEX_MOD_DISP_GAMMA BIT(21)
> -#define MUTEX_MOD_DISP_UFOE BIT(22)
> -#define MUTEX_MOD_DISP_PWM0 BIT(23)
> -#define MUTEX_MOD_DISP_PWM1 BIT(24)
> -#define MUTEX_MOD_DISP_OD BIT(25)
> +#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
> +#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
> +#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
> +#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
> +#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
> +#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
> +#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
> +#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
> +#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
> +#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
> +#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
> +#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
> +#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
> +#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
> +#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
>
> #define MUTEX_SOF_SINGLE_MODE 0
> #define MUTEX_SOF_DSI0 1
> @@ -77,24 +77,25 @@ struct mtk_ddp {
> struct clk *clk;
> void __iomem *regs;
> struct mtk_disp_mutex mutex[10];
> + const unsigned int *mutex_mod;
> };
>
> -static const unsigned int mutex_mod[DDP_COMPONENT_ID_MAX] = {
> - [DDP_COMPONENT_AAL] = MUTEX_MOD_DISP_AAL,
> - [DDP_COMPONENT_COLOR0] = MUTEX_MOD_DISP_COLOR0,
> - [DDP_COMPONENT_COLOR1] = MUTEX_MOD_DISP_COLOR1,
> - [DDP_COMPONENT_GAMMA] = MUTEX_MOD_DISP_GAMMA,
> - [DDP_COMPONENT_OD] = MUTEX_MOD_DISP_OD,
> - [DDP_COMPONENT_OVL0] = MUTEX_MOD_DISP_OVL0,
> - [DDP_COMPONENT_OVL1] = MUTEX_MOD_DISP_OVL1,
> - [DDP_COMPONENT_PWM0] = MUTEX_MOD_DISP_PWM0,
> - [DDP_COMPONENT_PWM1] = MUTEX_MOD_DISP_PWM1,
> - [DDP_COMPONENT_RDMA0] = MUTEX_MOD_DISP_RDMA0,
> - [DDP_COMPONENT_RDMA1] = MUTEX_MOD_DISP_RDMA1,
> - [DDP_COMPONENT_RDMA2] = MUTEX_MOD_DISP_RDMA2,
> - [DDP_COMPONENT_UFOE] = MUTEX_MOD_DISP_UFOE,
> - [DDP_COMPONENT_WDMA0] = MUTEX_MOD_DISP_WDMA0,
> - [DDP_COMPONENT_WDMA1] = MUTEX_MOD_DISP_WDMA1,
> +static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL,
> + [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
> + [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
> + [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD,
> + [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1,
> + [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0,
> + [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1,
> + [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1,
> + [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2,
> + [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE,
> + [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0,
> + [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> };
>
> static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> @@ -247,7 +248,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
> break;
> default:
> reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
> - reg |= mutex_mod[id];
> + reg |= ddp->mutex_mod[id];
> writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
> return;
> }
> @@ -273,7 +274,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
> break;
> default:
> reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
> - reg &= ~mutex_mod[id];
> + reg &= ~(ddp->mutex_mod[id]);
> writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
> break;
> }
> @@ -326,6 +327,8 @@ static int mtk_ddp_probe(struct platform_device *pdev)
> return PTR_ERR(ddp->regs);
> }
>
> + ddp->mutex_mod = of_device_get_match_data(dev);
> +
> platform_set_drvdata(pdev, ddp);
>
> return 0;
> @@ -337,7 +340,7 @@ static int mtk_ddp_remove(struct platform_device *pdev)
> }
>
> static const struct of_device_id ddp_driver_dt_match[] = {
> - { .compatible = "mediatek,mt8173-disp-mutex" },
> + { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod},
> {},
> };
> MODULE_DEVICE_TABLE(of, ddp_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 48cc01f..3ff788c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -39,9 +39,10 @@
> #define DISP_REG_UFO_START 0x0000
>
> #define DISP_COLOR_CFG_MAIN 0x0400
> -#define DISP_COLOR_START 0x0c00
> -#define DISP_COLOR_WIDTH 0x0c50
> -#define DISP_COLOR_HEIGHT 0x0c54
> +#define DISP_COLOR_START_MT8173 0x0c00
> +#define DISP_COLOR_START(comp) ((comp)->data->color_offset)
> +#define DISP_COLOR_WIDTH(comp) (DISP_COLOR_START(comp) + 0x50)
> +#define DISP_COLOR_HEIGHT(comp) (DISP_COLOR_START(comp) + 0x54)
>
> #define DISP_AAL_EN 0x0000
> #define DISP_AAL_SIZE 0x0030
> @@ -80,6 +81,20 @@
> #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
> #define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0)
>
> +struct mtk_disp_color_data {
> + unsigned int color_offset;
> +};
> +
> +struct mtk_disp_color {
> + struct mtk_ddp_comp ddp_comp;
> + const struct mtk_disp_color_data *data;
> +};
> +
> +static inline struct mtk_disp_color *comp_to_color(struct mtk_ddp_comp *comp)
> +{
> + return container_of(comp, struct mtk_disp_color, ddp_comp);
> +}
> +
> void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
> unsigned int CFG)
> {
> @@ -107,15 +122,19 @@ static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc)
> {
> - writel(w, comp->regs + DISP_COLOR_WIDTH);
> - writel(h, comp->regs + DISP_COLOR_HEIGHT);
> + struct mtk_disp_color *color = comp_to_color(comp);
> +
> + writel(w, comp->regs + DISP_COLOR_WIDTH(color));
> + writel(h, comp->regs + DISP_COLOR_HEIGHT(color));
> }
>
> static void mtk_color_start(struct mtk_ddp_comp *comp)
> {
> + struct mtk_disp_color *color = comp_to_color(comp);
> +
> writel(COLOR_BYPASS_ALL | COLOR_SEQ_SEL,
> comp->regs + DISP_COLOR_CFG_MAIN);
> - writel(0x1, comp->regs + DISP_COLOR_START);
> + writel(0x1, comp->regs + DISP_COLOR_START(color));
> }
>
> static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
> @@ -264,6 +283,16 @@ struct mtk_ddp_comp_match {
> [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
> };
>
> +static const struct mtk_disp_color_data mt8173_color_driver_data = {
> + .color_offset = DISP_COLOR_START_MT8173,
> +};
> +
> +static const struct of_device_id mtk_disp_color_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8173-disp-color",
> + .data = &mt8173_color_driver_data},
> + {},
> +};
> +
> int mtk_ddp_comp_get_id(struct device_node *node,
> enum mtk_ddp_comp_type comp_type)
> {
> @@ -286,10 +315,24 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
> enum mtk_ddp_comp_type type;
> struct device_node *larb_node;
> struct platform_device *larb_pdev;
> + const struct of_device_id *match;
> + struct mtk_disp_color *color;
>
> if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX)
> return -EINVAL;
>
> + type = mtk_ddp_matches[comp_id].type;
> + if (type == MTK_DISP_COLOR) {
> + devm_kfree(dev, comp);
> + color = devm_kzalloc(dev, sizeof(*color), GFP_KERNEL);
> + if (!color)
> + return -ENOMEM;
> +
> + match = of_match_node(mtk_disp_color_driver_dt_match, node);
> + color->data = match->data;
> + comp = &color->ddp_comp;
> + }
> +
> comp->id = comp_id;
> comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs;
>
> @@ -308,8 +351,6 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
> if (IS_ERR(comp->clk))
> comp->clk = NULL;
>
> - type = mtk_ddp_matches[comp_id].type;
> -
> /* Only DMA capable components need the LARB property */
> comp->larb_dev = NULL;
> if (type != MTK_DISP_OVL &&
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 4b7fe7e..074fe31 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -128,7 +128,7 @@ static int mtk_atomic_commit(struct drm_device *drm,
> .atomic_commit = mtk_atomic_commit,
> };
>
> -static const enum mtk_ddp_comp_id mtk_ddp_main[] = {
> +static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> DDP_COMPONENT_OVL0,
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_AAL,
> @@ -139,7 +139,7 @@ static int mtk_atomic_commit(struct drm_device *drm,
> DDP_COMPONENT_PWM0,
> };
>
> -static const enum mtk_ddp_comp_id mtk_ddp_ext[] = {
> +static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
> DDP_COMPONENT_OVL1,
> DDP_COMPONENT_COLOR1,
> DDP_COMPONENT_GAMMA,
> @@ -147,6 +147,13 @@ static int mtk_atomic_commit(struct drm_device *drm,
> DDP_COMPONENT_DPI0,
> };
>
> +static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> + .main_path = mt8173_mtk_ddp_main,
> + .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
> + .ext_path = mt8173_mtk_ddp_ext,
> + .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
> +};
> +
> static int mtk_drm_kms_init(struct drm_device *drm)
> {
> struct mtk_drm_private *private = drm->dev_private;
> @@ -189,17 +196,19 @@ static int mtk_drm_kms_init(struct drm_device *drm)
> * and each statically assigned to a crtc:
> * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
> */
> - ret = mtk_drm_crtc_create(drm, mtk_ddp_main, ARRAY_SIZE(mtk_ddp_main));
> + ret = mtk_drm_crtc_create(drm, private->data->main_path,
> + private->data->main_len);
> if (ret < 0)
> goto err_component_unbind;
> /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
> - ret = mtk_drm_crtc_create(drm, mtk_ddp_ext, ARRAY_SIZE(mtk_ddp_ext));
> + ret = mtk_drm_crtc_create(drm, private->data->ext_path,
> + private->data->ext_len);
> if (ret < 0)
> goto err_component_unbind;
>
> /* Use OVL device for all DMA memory allocations */
> - np = private->comp_node[mtk_ddp_main[0]] ?:
> - private->comp_node[mtk_ddp_ext[0]];
> + np = private->comp_node[private->data->main_path[0]] ?:
> + private->comp_node[private->data->ext_path[0]];
> pdev = of_find_device_by_node(np);
> if (!pdev) {
> ret = -ENODEV;
> @@ -362,6 +371,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
>
> mutex_init(&private->commit.lock);
> INIT_WORK(&private->commit.work, mtk_atomic_work);
> + private->data = of_device_get_match_data(dev);
>
> mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> private->config_regs = devm_ioremap_resource(dev, mem);
> @@ -513,7 +523,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
> mtk_drm_sys_resume);
>
> static const struct of_device_id mtk_drm_of_ids[] = {
> - { .compatible = "mediatek,mt8173-mmsys", },
> + { .compatible = "mediatek,mt8173-mmsys",
> + .data = &mt8173_mmsys_driver_data},
> { }
> };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index aa93894..fa0b106 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -28,6 +28,13 @@
> struct drm_property;
> struct regmap;
>
> +struct mtk_mmsys_driver_data {
> + const enum mtk_ddp_comp_id *main_path;
> + unsigned int main_len;
> + const enum mtk_ddp_comp_id *ext_path;
> + unsigned int ext_len;
> +};
> +
> struct mtk_drm_private {
> struct drm_device *drm;
> struct device *dma_dev;
> @@ -40,6 +47,7 @@ struct mtk_drm_private {
> void __iomem *config_regs;
> struct device_node *comp_node[DDP_COMPONENT_ID_MAX];
> struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX];
> + const struct mtk_mmsys_driver_data *data;
>
> struct {
> struct drm_atomic_state *state;
> diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
> index 1c366f8..c4a0165 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
> @@ -16,6 +16,7 @@
> #include <linux/delay.h>
> #include <linux/io.h>
> #include <linux/module.h>
> +#include <linux/of_device.h>
> #include <linux/platform_device.h>
> #include <linux/phy/phy.h>
>
> @@ -87,6 +88,9 @@
>
> #define MIPITX_DSI_PLL_CON2 0x58
>
> +#define MIPITX_DSI_PLL_TOP 0x64
> +#define RG_DSI_MPPLL_PRESERVE (0xff << 8)
> +
> #define MIPITX_DSI_PLL_PWR 0x68
> #define RG_DSI_MPPLL_SDM_PWR_ON BIT(0)
> #define RG_DSI_MPPLL_SDM_ISO_EN BIT(1)
> @@ -123,10 +127,15 @@
> #define SW_LNT2_HSTX_PRE_OE BIT(24)
> #define SW_LNT2_HSTX_OE BIT(25)
>
> +struct mtk_mipitx_data {
> + const u32 mppll_preserve;
> +};
> +
> struct mtk_mipi_tx {
> struct device *dev;
> void __iomem *regs;
> unsigned int data_rate;
> + const struct mtk_mipitx_data *driver_data;
> struct clk_hw pll_hw;
> struct clk *pll;
> };
> @@ -243,6 +252,10 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
> mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
> RG_DSI_MPPLL_SDM_SSC_EN);
>
> + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
> + RG_DSI_MPPLL_PRESERVE,
> + mipi_tx->driver_data->mppll_preserve);
> +
> return 0;
> }
>
> @@ -255,6 +268,9 @@ static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw)
> mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
> RG_DSI_MPPLL_PLL_EN);
>
> + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
> + RG_DSI_MPPLL_PRESERVE, 0);
> +
> mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
> RG_DSI_MPPLL_SDM_ISO_EN |
> RG_DSI_MPPLL_SDM_PWR_ON,
> @@ -391,6 +407,7 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev)
> if (!mipi_tx)
> return -ENOMEM;
>
> + mipi_tx->driver_data = of_device_get_match_data(dev);
> mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> mipi_tx->regs = devm_ioremap_resource(dev, mem);
> if (IS_ERR(mipi_tx->regs)) {
> @@ -448,8 +465,13 @@ static int mtk_mipi_tx_remove(struct platform_device *pdev)
> return 0;
> }
>
> +static const struct mtk_mipitx_data mt8173_mipitx_data = {
> + .mppll_preserve = (0 << 8)
> +};
> +
> static const struct of_device_id mtk_mipi_tx_match[] = {
> - { .compatible = "mediatek,mt8173-mipi-tx", },
> + { .compatible = "mediatek,mt8173-mipi-tx",
> + .data = &mt8173_mipitx_data },
> {},
> };
>
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^ permalink raw reply
* Re: [PATCH v11 04/12] drm/mediatek: add shadow register support
From: CK Hu @ 2017-01-17 2:47 UTC (permalink / raw)
To: YT Shen
Cc: Mark Rutland, devicetree, srv_heupstream, emil.l.velikov,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Matthias Brugger, yingjoe.chen, linux-arm-kernel
In-Reply-To: <1484117473-46644-5-git-send-email-yt.shen@mediatek.com>
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> We need to acquire mutex before using the resources,
> and need to release it after finished.
> So we don't need to write registers in the blanking period.
>
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 75 ++++++++++++++++++++-------------
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 25 +++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 2 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 4 files changed, 74 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 01a21dd..b9b82e5 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -329,6 +329,42 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
> pm_runtime_put(drm->dev);
> }
>
> +static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
> +{
> + struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
> + struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
> + struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
> + unsigned int i;
> +
> + /*
> + * TODO: instead of updating the registers here, we should prepare
> + * working registers in atomic_commit and let the hardware command
> + * queue update module registers on vblank.
> + */
> + if (state->pending_config) {
> + mtk_ddp_comp_config(ovl, state->pending_width,
> + state->pending_height,
> + state->pending_vrefresh, 0);
> +
> + state->pending_config = false;
> + }
> +
> + if (mtk_crtc->pending_planes) {
> + for (i = 0; i < OVL_LAYER_NR; i++) {
> + struct drm_plane *plane = &mtk_crtc->planes[i];
> + struct mtk_plane_state *plane_state;
> +
> + plane_state = to_mtk_plane_state(plane->state);
> +
> + if (plane_state->pending.config) {
> + mtk_ddp_comp_layer_config(ovl, i, plane_state);
> + plane_state->pending.config = false;
> + }
> + }
> + mtk_crtc->pending_planes = false;
> + }
> +}
> +
> static void mtk_drm_crtc_enable(struct drm_crtc *crtc)
> {
> struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
> @@ -405,6 +441,7 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> struct drm_crtc_state *old_crtc_state)
> {
> struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
> + struct mtk_drm_private *priv = crtc->dev->dev_private;
> unsigned int pending_planes = 0;
> int i;
>
> @@ -426,6 +463,12 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> if (crtc->state->color_mgmt_changed)
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> +
> + if (priv->data->shadow_register) {
> + mtk_disp_mutex_acquire(mtk_crtc->mutex);
> + mtk_crtc_ddp_config(crtc);
> + mtk_disp_mutex_release(mtk_crtc->mutex);
> + }
> }
>
> static const struct drm_crtc_funcs mtk_crtc_funcs = {
> @@ -471,36 +514,10 @@ static int mtk_drm_crtc_init(struct drm_device *drm,
> void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl)
> {
> struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
> - struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
> - unsigned int i;
> + struct mtk_drm_private *priv = crtc->dev->dev_private;
>
> - /*
> - * TODO: instead of updating the registers here, we should prepare
> - * working registers in atomic_commit and let the hardware command
> - * queue update module registers on vblank.
> - */
> - if (state->pending_config) {
> - mtk_ddp_comp_config(ovl, state->pending_width,
> - state->pending_height,
> - state->pending_vrefresh, 0);
> -
> - state->pending_config = false;
> - }
> -
> - if (mtk_crtc->pending_planes) {
> - for (i = 0; i < OVL_LAYER_NR; i++) {
> - struct drm_plane *plane = &mtk_crtc->planes[i];
> - struct mtk_plane_state *plane_state;
> -
> - plane_state = to_mtk_plane_state(plane->state);
> -
> - if (plane_state->pending.config) {
> - mtk_ddp_comp_layer_config(ovl, i, plane_state);
> - plane_state->pending.config = false;
> - }
> - }
> - mtk_crtc->pending_planes = false;
> - }
> + if (!priv->data->shadow_register)
> + mtk_crtc_ddp_config(crtc);
>
> mtk_drm_finish_page_flip(mtk_crtc);
> }
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 8030769..b77d456 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -12,6 +12,7 @@
> */
>
> #include <linux/clk.h>
> +#include <linux/iopoll.h>
> #include <linux/module.h>
> #include <linux/of_device.h>
> #include <linux/platform_device.h>
> @@ -32,10 +33,13 @@
> #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
>
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> +#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
> #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
>
> +#define INT_MUTEX BIT(1)
> +
> #define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
> #define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
> #define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
> @@ -300,6 +304,27 @@ void mtk_disp_mutex_disable(struct mtk_disp_mutex *mutex)
> writel(0, ddp->regs + DISP_REG_MUTEX_EN(mutex->id));
> }
>
> +void mtk_disp_mutex_acquire(struct mtk_disp_mutex *mutex)
> +{
> + struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
> + mutex[mutex->id]);
> + u32 tmp;
> +
> + writel(1, ddp->regs + DISP_REG_MUTEX_EN(mutex->id));
> + writel(1, ddp->regs + DISP_REG_MUTEX(mutex->id));
> + if (readl_poll_timeout_atomic(ddp->regs + DISP_REG_MUTEX(mutex->id),
> + tmp, tmp & INT_MUTEX, 1, 10000))
> + pr_err("could not acquire mutex %d\n", mutex->id);
> +}
> +
> +void mtk_disp_mutex_release(struct mtk_disp_mutex *mutex)
> +{
> + struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
> + mutex[mutex->id]);
> +
> + writel(0, ddp->regs + DISP_REG_MUTEX(mutex->id));
> +}
> +
> static int mtk_ddp_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> index 92c1175..f9a7991 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> @@ -37,5 +37,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
> enum mtk_ddp_comp_id id);
> void mtk_disp_mutex_unprepare(struct mtk_disp_mutex *mutex);
> void mtk_disp_mutex_put(struct mtk_disp_mutex *mutex);
> +void mtk_disp_mutex_acquire(struct mtk_disp_mutex *mutex);
> +void mtk_disp_mutex_release(struct mtk_disp_mutex *mutex);
>
> #endif /* MTK_DRM_DDP_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index fa0b106..94f8b66 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -33,6 +33,7 @@ struct mtk_mmsys_driver_data {
> unsigned int main_len;
> const enum mtk_ddp_comp_id *ext_path;
> unsigned int ext_len;
> + bool shadow_register;
> };
>
> struct mtk_drm_private {
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^ permalink raw reply
* Re: [PATCH 08/22] power: supply: add AC power supply driver for AXP20X and AXP22X PMICs
From: Sebastian Reichel @ 2017-01-17 3:00 UTC (permalink / raw)
To: Quentin Schulz
Cc: mark.rutland, devicetree, lars, linux-pm, linux-iio, linux,
linux-kernel, wens, robh+dt, linux-arm-kernel, pmeerw, knaack.h,
maxime.ripard, bonbons, lee.jones, thomas.petazzoni, jic23,
icenowy
In-Reply-To: <20170102163723.7939-9-quentin.schulz@free-electrons.com>
[-- Attachment #1.1: Type: text/plain, Size: 1695 bytes --]
Hi Quentin,
The driver looks mostly fine. I do have a two comments, though.
On Mon, Jan 02, 2017 at 05:37:08PM +0100, Quentin Schulz wrote:
> [...]
>
> +static int axp20x_ac_power_probe(struct platform_device *pdev)
> +{
> + static const char * const axp20x_irq_names[] = { "ACIN_PLUGIN",
> + "ACIN_REMOVAL", NULL };
>
> + static const char * const *irq_names;
> + const struct power_supply_desc *ac_power_desc;
> + int i, irq, ret;
> +
> + if (!of_device_is_available(pdev->dev.of_node))
> + return -ENODEV;
> +
> + if (!axp20x) {
> + dev_err(&pdev->dev, "Parent drvdata not set\n");
> + return -EINVAL;
> + }
axp20x will no longer be needed after implementing below
comments.
> [...]
> + irq_names = axp20x_irq_names;
Just rename axp20x_irq_names into irq_names, since its only used
here.
> [...]
>
> + power->np = pdev->dev.of_node;
This can be dropped, it's not used at all.
> + power->regmap = axp20x->regmap;
power->regmap = dev_get_regmap(pdev->dev.parent, NULL);
> [...]
> + /* Request irqs after registering, as irqs may trigger immediately */
> + for (i = 0; irq_names[i]; i++) {
> + irq = platform_get_irq_byname(pdev, irq_names[i]);
> + if (irq < 0) {
> + dev_warn(&pdev->dev, "No IRQ for %s: %d\n",
> + irq_names[i], irq);
> + continue;
> + }
> + irq = regmap_irq_get_virq(axp20x->regmap_irqc, irq);
The mapping should actually happen in the mfd driver, so that
the platform resource contains a valid irq.
> + ret = devm_request_any_context_irq(&pdev->dev, irq,
> + axp20x_ac_power_irq, 0,
> + DRVNAME, power);
> + if (ret < 0)
> + dev_warn(&pdev->dev, "Error requesting %s IRQ: %d\n",
> + irq_names[i], ret);
> + }
-- Sebastian
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^ permalink raw reply
* [PATCH 0/2] ARM64: meson-gxm: R-Box Pro enablement
From: Andreas Färber @ 2017-01-17 3:06 UTC (permalink / raw)
To: linux-amlogic
Cc: devicetree, Kevin Hilman, linux-kernel, Carlo Caione,
Andreas Färber, linux-arm-kernel
Hello,
This mini-series adds initial support for the Amlogic S912 based
R-Box Pro TV boxes.
Patch 1 should apply today, patch 2 depends on Martin's Bluetooth series.
Wifi further depends on: https://patchwork.kernel.org/patch/9518447/
(and /etc/wifi/AP6255/nvram.txt as /lib/firmware/brcm/brcmfmac43455-sdio.txt)
Regards,
Andreas
Cc: devicetree@vger.kernel.org
Andreas Färber (2):
ARM64: dts: meson-gxm: Add R-Box Pro
ARM64: dts: meson-gxm-rbox-pro: Enable Bluetooth
arch/arm64/boot/dts/amlogic/Makefile | 1 +
arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts | 249 +++++++++++++++++++++
2 files changed, 250 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
--
2.10.2
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^ permalink raw reply
* [PATCH 1/2] ARM64: dts: meson-gxm: Add R-Box Pro
From: Andreas Färber @ 2017-01-17 3:06 UTC (permalink / raw)
To: linux-amlogic
Cc: Carlo Caione, Kevin Hilman, linux-arm-kernel, linux-kernel,
Andreas Färber, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, devicetree
In-Reply-To: <20170117030611.23827-1-afaerber@suse.de>
The R-Box Pro is a TV box derived from Amlogic q200 reference design.
It uses an AP6255 Wifi module. It features an LED tube that lights a
surrounding stripe and the top logo in blue or red or pink'ish - blue
is on by default, and red (i.e., pink) is configured as panic indicator.
This device is available in at least two models, with 2 GB vs. 3 GB RAM
as well as varying eMMC size. The intent is to handle this with a single
.dts that gets the actual RAM size from U-Boot.
The vendor prefix remains to be clarified, therefore no dedicated board
compatible string yet.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts | 240 +++++++++++++++++++++
2 files changed, 241 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index 0d7bfbf7d922..66bc809a5eae 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-nexbox-a95x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q201.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
new file mode 100644
index 000000000000..9f04fa4e5aec
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
@@ -0,0 +1,240 @@
+/*
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * Based on nexbox-a1:
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-gxm.dtsi"
+
+/ {
+ compatible = "amlogic,s912", "amlogic,meson-gxm";
+ model = "R-Box Pro";
+
+ aliases {
+ serial0 = &uart_AO;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 3 GiB */
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "rbox-pro:blue:on";
+ gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ red {
+ label = "rbox-pro:red:standby";
+ gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ retain-state-suspended;
+ panic-indicator;
+ };
+ };
+
+ vddio_boot: regulator-vddio-boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcc_3v3: regulator-vcc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+ðmac {
+ status = "okay";
+
+ pinctrl-0 = <ð_pins>;
+ pinctrl-names = "default";
+
+ /* Select external PHY by default */
+ phy-handle = <&external_phy>;
+
+ snps,reset-gpio = <&gpio GPIOZ_14 0>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+
+ amlogic,tx-delay-ns = <2>;
+
+ /* External PHY is in RGMII */
+ phy-mode = "rgmii";
+};
+
+&external_mdio {
+ external_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ max-speed = <1000>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+
+ brcmf: brcmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
--
2.10.2
^ permalink raw reply related
* [PATCH 2/2] ARM64: dts: meson-gxm-rbox-pro: Enable Bluetooth
From: Andreas Färber @ 2017-01-17 3:06 UTC (permalink / raw)
To: linux-amlogic
Cc: Mark Rutland, devicetree, Kevin Hilman, Will Deacon, linux-kernel,
Rob Herring, Catalin Marinas, Carlo Caione, Andreas Färber,
linux-arm-kernel
In-Reply-To: <20170117030611.23827-1-afaerber@suse.de>
Add an SDIO reset GPIO and enable the serial used by the AP6255
Bluetooth module. Based on work by Martin Blumenstingl.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
index 9f04fa4e5aec..6ea225f584bd 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
@@ -58,6 +58,7 @@
aliases {
serial0 = &uart_AO;
+ serial1 = &uart_A;
};
chosen {
@@ -122,7 +123,8 @@
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>,
+ <&gpio GPIOX_17 GPIO_ACTIVE_LOW>;
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
@@ -238,3 +240,10 @@
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
+
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+};
--
2.10.2
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v3 1/3] dt: bindings: add documentation for zx2967 family reset controller
From: Baoyou Xie @ 2017-01-17 3:22 UTC (permalink / raw)
To: jun.nie, p.zabel, robh+dt, mark.rutland
Cc: devicetree, xie.baoyou, linux-kernel, chen.chaokai, wang.qiang01,
baoyou.xie, shawnguo, linux-arm-kernel
This patch adds dt-binding documentation for zx2967 family
reset controller.
Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
Reviewed-by: Shawn Guo <shawnguo@kernel.org>
---
.../devicetree/bindings/reset/zte,zx2967-reset.txt | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt
diff --git a/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt b/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt
new file mode 100644
index 0000000..b015508
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt
@@ -0,0 +1,20 @@
+ZTE zx2967 SoCs Reset Controller
+=======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: should be one of the following.
+ * zte,zx296718-reset
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #reset-cells: must be 1.
+
+example:
+
+ reset: reset-controller@1461060 {
+ compatible = "zte,zx296718-reset";
+ reg = <0x01461060 0x8>;
+ #reset-cells = <1>;
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH v3 2/3] MAINTAINERS: add zx2967 reset controller driver to ARM ZTE architecture
From: Baoyou Xie @ 2017-01-17 3:22 UTC (permalink / raw)
To: jun.nie, p.zabel, robh+dt, mark.rutland
Cc: devicetree, xie.baoyou, linux-kernel, chen.chaokai, wang.qiang01,
baoyou.xie, shawnguo, linux-arm-kernel
In-Reply-To: <1484623377-16208-1-git-send-email-baoyou.xie@linaro.org>
Add the zx2967 reset controller driver as maintained by ARM ZTE
architecture maintainers, as they're parts of the core IP.
Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e63063b..5fb9b62 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1987,9 +1987,11 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-zx/
F: drivers/clk/zte/
+F: drivers/reset/reset-zx2967.c
F: drivers/soc/zte/
F: Documentation/devicetree/bindings/arm/zte.txt
F: Documentation/devicetree/bindings/clock/zx296702-clk.txt
+F: Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt
F: Documentation/devicetree/bindings/soc/zte/
F: include/dt-bindings/soc/zx*.h
--
2.7.4
^ permalink raw reply related
* [PATCH v3 3/3] reset: zx2967: add reset controller driver for ZTE's zx2967 family
From: Baoyou Xie @ 2017-01-17 3:22 UTC (permalink / raw)
To: jun.nie, p.zabel, robh+dt, mark.rutland
Cc: linux-arm-kernel, devicetree, linux-kernel, shawnguo, baoyou.xie,
xie.baoyou, chen.chaokai, wang.qiang01
In-Reply-To: <1484623377-16208-1-git-send-email-baoyou.xie@linaro.org>
This patch adds reset controller driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
---
drivers/reset/Kconfig | 6 +++
drivers/reset/Makefile | 1 +
drivers/reset/reset-zx2967.c | 106 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 113 insertions(+)
create mode 100644 drivers/reset/reset-zx2967.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 172dc96..f4cdfe9 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -86,6 +86,12 @@ config RESET_UNIPHIER
Say Y if you want to control reset signals provided by System Control
block, Media I/O block, Peripheral Block.
+config RESET_ZX2967
+ bool "ZTE ZX2967 Reset Driver"
+ depends on ARCH_ZX || COMPILE_TEST
+ help
+ This enables the reset controller driver for ZTE's zx2967 family.
+
config RESET_ZYNQ
bool "ZYNQ Reset Driver" if COMPILE_TEST
default ARCH_ZYNQ
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 13b346e..2cd3f6c 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -13,4 +13,5 @@ obj-$(CONFIG_RESET_STM32) += reset-stm32.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_TI_SYSCON_RESET) += reset-ti-syscon.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
+obj-$(CONFIG_RESET_ZX2967) += reset-zx2967.o
obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
diff --git a/drivers/reset/reset-zx2967.c b/drivers/reset/reset-zx2967.c
new file mode 100644
index 0000000..5d82151
--- /dev/null
+++ b/drivers/reset/reset-zx2967.c
@@ -0,0 +1,106 @@
+/*
+ * ZTE's zx2967 family reset controller driver
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie <baoyou.xie@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+
+struct zx2967_reset {
+ void __iomem *reg_base;
+ spinlock_t lock;
+ struct reset_controller_dev rcdev;
+};
+
+static int zx2967_reset_act(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+ struct zx2967_reset *reset = NULL;
+ int bank = id / 32;
+ int offset = id % 32;
+ u32 reg;
+ unsigned long flags;
+
+ reset = container_of(rcdev, struct zx2967_reset, rcdev);
+
+ spin_lock_irqsave(&reset->lock, flags);
+
+ reg = readl_relaxed(reset->reg_base + (bank * 4));
+ if (assert)
+ reg &= ~BIT(offset);
+ else
+ reg |= BIT(offset);
+ writel_relaxed(reg, reset->reg_base + (bank * 4));
+
+ spin_unlock_irqrestore(&reset->lock, flags);
+
+ return 0;
+}
+
+static int zx2967_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return zx2967_reset_act(rcdev, id, true);
+}
+
+static int zx2967_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return zx2967_reset_act(rcdev, id, false);
+}
+
+static struct reset_control_ops zx2967_reset_ops = {
+ .assert = zx2967_reset_assert,
+ .deassert = zx2967_reset_deassert,
+};
+
+static int zx2967_reset_probe(struct platform_device *pdev)
+{
+ struct zx2967_reset *reset;
+ struct resource *res;
+
+ reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
+ if (!reset)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ reset->reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(reset->reg_base))
+ return PTR_ERR(reset->reg_base);
+
+ spin_lock_init(&reset->lock);
+
+ reset->rcdev.owner = THIS_MODULE;
+ reset->rcdev.nr_resets = resource_size(res) * 8;
+ reset->rcdev.ops = &zx2967_reset_ops;
+ reset->rcdev.of_node = pdev->dev.of_node;
+
+ return devm_reset_controller_register(&pdev->dev, &reset->rcdev);
+}
+
+static const struct of_device_id zx2967_reset_dt_ids[] = {
+ { .compatible = "zte,zx296718-reset", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx2967_reset_dt_ids);
+
+static struct platform_driver zx2967_reset_driver = {
+ .probe = zx2967_reset_probe,
+ .driver = {
+ .name = "zx2967-reset",
+ .of_match_table = zx2967_reset_dt_ids,
+ },
+};
+
+builtin_platform_driver(zx2967_reset_driver);
+
+MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
+MODULE_DESCRIPTION("ZTE zx2967 Reset Controller Driver");
+MODULE_LICENSE("GPL");
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v1 2/2] arm: dts: mt2701: add nor flash node
From: Thomas Petazzoni @ 2017-01-17 3:32 UTC (permalink / raw)
To: Boris Brezillon
Cc: Mark Rutland, devicetree, Guochun Mao, Richard Weinberger,
Russell King, linux-kernel, Marek Vasut, Rob Herring, linux-mtd,
Matthias Brugger, linux-mediatek, Cyrille Pitchen, Brian Norris,
David Woodhouse, linux-arm-kernel
In-Reply-To: <20170113175628.1793f433@bbrezillon>
Hello,
On Fri, 13 Jan 2017 17:56:28 +0100, Boris Brezillon wrote:
> because both compatible are referring to very specific IP version. It's
> not the same as
>
> compatible = "mediatek,mt8173-nor", "mediatek,mt81xx-nor";
mt81xx-nor is a bogus compatible string, and DT binding maintainers
will not accept it. They don't want compatible strings with "wildcards".
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH 1/2] ARM64: dts: meson-gxm: Add R-Box Pro
From: Andreas Färber @ 2017-01-17 3:35 UTC (permalink / raw)
To: linux-amlogic
Cc: Mark Rutland, devicetree, Kevin Hilman, Will Deacon, linux-kernel,
Rob Herring, Catalin Marinas, Carlo Caione, linux-arm-kernel
In-Reply-To: <20170117030611.23827-2-afaerber@suse.de>
Am 17.01.2017 um 04:06 schrieb Andreas Färber:
> + leds {
> + compatible = "gpio-leds";
> +
> + blue {
> + label = "rbox-pro:blue:on";
> + gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
> + default-state = "on";
> + };
> +
> + red {
> + label = "rbox-pro:red:standby";
> + gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + retain-state-suspended;
> + panic-indicator;
> + };
> + };
The original property names for these two were led and red. If anyone
has better label names than the above, please speak up. Ditto for
vega-s95. On the odroidc2 it's called alive but uses heartbeat there.
The vendor device tree had a third "mcu" GPIO in the sysled node,
GPIOAO_6, which leads to immediate power-off. I tried using
"gpio-poweroff" to configure this pin, but that driver fails to
initialize because some pm callback is already registered - I assume
from psci, which apparently succeeds to power-off the system, too. For
comparison, the S905 based Vega S95 Telos has no such mcu property. Any
thoughts?
Also, any ideas how best to switch from blue to red for suspend? Add
pinctrl properties above? systemd service doing echo from userspace? I
assume in Android the Amlogic sysled driver handles all that logic -
didn't find any suspend equivalent to gpio-poweroff.
Regards,
Andreas
--
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GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
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^ permalink raw reply
* Re: [PATCH v1 2/2] arm: dts: mt2701: add nor flash node
From: Thomas Petazzoni @ 2017-01-17 3:36 UTC (permalink / raw)
To: Boris Brezillon
Cc: Marek Vasut, Rob Herring, Mark Rutland, devicetree, Guochun Mao,
Richard Weinberger, Russell King, linux-kernel, linux-mtd,
Matthias Brugger, linux-mediatek, Cyrille Pitchen, Brian Norris,
David Woodhouse, linux-arm-kernel
In-Reply-To: <20170116094032.6f471f11@bbrezillon>
Hello,
(Side note: you guys should learn about stripping irrelevant parts of
an e-mail when replying!)
On Mon, 16 Jan 2017 09:40:32 +0100, Boris Brezillon wrote:
> > Well this is OK I guess, but then you can also use "mediatek,mt8173-nor"
> > as the oldest supported compatible and be done with it, no ? It looks a
> > bit crappy though, I admit that ...
>
> Let's stop bikeshedding and wait for DT maintainers feedback
> before taking a decision ;-).
>
> Rob, Mark, any opinion?
I agree that a clarification would be good. There are really two
options:
1. Have two compatible strings in the DT, the one that matches the
exact SoC where the IP is found (first compatible string) and the
one that matches some other SoC where the same IP is found (second
compatible string). Originally, Linux only supports the second
compatible string in its device driver, but if it happens that a
difference is found between two IPs that we thought were the same,
we can add support for the first compatible string in the driver,
with a slightly different behavior.
2. Have a single compatible string in the DT, matching the exact SoC
where the IP is found. This involves adding immediately this
compatible string in the corresponding driver.
I've not really been able to figure out which of the two options is the
most future-proof/appropriate.
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH 17/22] power: supply: add battery driver for AXP20X and AXP22X PMICs
From: Sebastian Reichel @ 2017-01-17 3:46 UTC (permalink / raw)
To: Quentin Schulz
Cc: mark.rutland, devicetree, lars, linux-pm, linux-iio, linux,
linux-kernel, wens, robh+dt, linux-arm-kernel, pmeerw, knaack.h,
maxime.ripard, bonbons, lee.jones, thomas.petazzoni, jic23,
icenowy
In-Reply-To: <20170102163723.7939-18-quentin.schulz@free-electrons.com>
[-- Attachment #1.1: Type: text/plain, Size: 2347 bytes --]
Hi Quentin,
Just a couple of small things in this patch.
On Mon, Jan 02, 2017 at 05:37:17PM +0100, Quentin Schulz wrote:
> [...]
> + case POWER_SUPPLY_PROP_CURRENT_NOW:
> + ret = regmap_read(axp20x_batt->regmap, AXP20X_PWR_INPUT_STATUS,
> + ®);
> + if (ret)
> + return ret;
> +
> + if (reg & AXP20X_PWR_STATUS_BAT_CHARGING)
> + chan = axp20x_batt->batt_chrg_i;
> + else
> + chan = axp20x_batt->batt_dischrg_i;
> +
> + ret = iio_read_channel_processed(chan, &val->intval);
> + if (ret)
> + return ret;
> +
> + /*
> + * IIO framework gives mV but Power Supply framework gives µV.
> + */
Nit: Volt -> Ampere
> + val->intval *= 1000;
> + break;
>
> [...]
>
> +static int axp20x_power_probe(struct platform_device *pdev)
> +{
> + struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
> + struct axp20x_batt_ps *axp20x_batt;
> + struct power_supply_config psy_cfg = {};
> +
> + axp20x_batt = devm_kzalloc(&pdev->dev, sizeof(*axp20x_batt),
> + GFP_KERNEL);
> + if (!axp20x_batt)
> + return -ENOMEM;
> +
> + axp20x_batt->batt_v = devm_iio_channel_get(&pdev->dev, "batt_v");
> + if (IS_ERR(axp20x_batt->batt_v)) {
> + if (PTR_ERR(axp20x_batt->batt_v) == -ENODEV)
> + return -EPROBE_DEFER;
> + return PTR_ERR(axp20x_batt->batt_v);
> + }
> +
> + axp20x_batt->batt_chrg_i = devm_iio_channel_get(&pdev->dev,
> + "batt_chrg_i");
> + if (IS_ERR(axp20x_batt->batt_chrg_i)) {
> + if (PTR_ERR(axp20x_batt->batt_chrg_i) == -ENODEV)
> + return -EPROBE_DEFER;
> + return PTR_ERR(axp20x_batt->batt_chrg_i);
> + }
> +
> + axp20x_batt->batt_dischrg_i = devm_iio_channel_get(&pdev->dev,
> + "batt_dischrg_i");
> + if (IS_ERR(axp20x_batt->batt_dischrg_i)) {
> + if (PTR_ERR(axp20x_batt->batt_dischrg_i) == -ENODEV)
> + return -EPROBE_DEFER;
> + return PTR_ERR(axp20x_batt->batt_dischrg_i);
> + }
> +
> + axp20x_batt->regmap = axp20x->regmap;
> + platform_set_drvdata(pdev, axp20x_batt);
Please use drv_get_regmap(pdev->dev.parent, NULL) instead (and drop
axp20x).
> + psy_cfg.drv_data = axp20x_batt;
> + psy_cfg.of_node = pdev->dev.of_node;
> +
> + axp20x_batt->axp_id = (int)of_device_get_match_data(&pdev->dev);
use (uintptr_t) to avoid compiler warnings on systems with sizeof
int != sizeof ptr.
-- Sebastian
[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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^ permalink raw reply
* [PATCH 0/5] ARM: OMAP2+: Add earlycon support
From: Lokesh Vutla @ 2017-01-17 4:03 UTC (permalink / raw)
To: Tony Lindgren, Linux OMAP Mailing List
Cc: Device Tree Mailing List, Rob Herring, Tero Kristo, Sekhar Nori,
Vignesh R, Nishanth Menon, Lokesh Vutla
This series adds earlycon support for all am33xx, am43xx, am57xx, dra7xx
based TI platforms. With this series just passing "earlycon" in bootargs
is sufficient for early debug.
Tested with omap2plus_defconfig + CONFIG_SERIAL_8250.
Lokesh Vutla (5):
ARM: OMAP2+: omap_hwmod: Add support for earlycon
ARM: dts: am33xx: Add stdout-path property
ARM: dts: am43xx: Add stdout-path property
ARM: dts: am57xx: Add stdout-path property
ARM: dts: dra7xx: Add stdout-path property
arch/arm/boot/dts/am335x-evm.dts | 4 +++
arch/arm/boot/dts/am335x-evmsk.dts | 4 +++
arch/arm/boot/dts/am335x-icev2.dts | 4 +++
arch/arm/boot/dts/am437x-gp-evm.dts | 4 +++
arch/arm/boot/dts/am437x-idk-evm.dts | 4 +++
arch/arm/boot/dts/am437x-sk-evm.dts | 4 +++
arch/arm/boot/dts/am43x-epos-evm.dts | 4 +++
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 4 +++
arch/arm/boot/dts/am57xx-idk-common.dtsi | 4 +++
arch/arm/boot/dts/dra7-evm.dts | 4 +++
arch/arm/boot/dts/dra72-evm-common.dtsi | 4 +++
arch/arm/mach-omap2/omap_hwmod.c | 36 +++++++++++++++++++++++++
12 files changed, 80 insertions(+)
--
2.11.0
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^ permalink raw reply
* [PATCH 1/5] ARM: OMAP2+: omap_hwmod: Add support for earlycon
From: Lokesh Vutla @ 2017-01-17 4:03 UTC (permalink / raw)
To: Tony Lindgren, Linux OMAP Mailing List
Cc: Device Tree Mailing List, Rob Herring, Tero Kristo, Sekhar Nori,
Vignesh R, Nishanth Menon, Lokesh Vutla
In-Reply-To: <20170117040336.21700-1-lokeshvutla-l0cyMroinI0@public.gmane.org>
Hwmod core tries to reset and idles each IP that is registered with hwmod.
In case of earlycon, that specific uart IP cannot be reset or keep it in
idle state else earlycon hangs once hwmod resets that uart IP. So add support
to not reset uart that is being used as earlycon only if CONFIG_SERIAL_EARLYCON
is enabled.
Signed-off-by: Lokesh Vutla <lokeshvutla-l0cyMroinI0@public.gmane.org>
---
arch/arm/mach-omap2/omap_hwmod.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index e8b988714a09..7b1ac69a2209 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3249,6 +3249,39 @@ int __init omap_hwmod_setup_one(const char *oh_name)
}
/**
+ * omap_hwmod_setup_earlycon_flags - set up flags for early console
+ *
+ * Enable DEBUG_OMAPUART_FLAGS for uart hwmod that is being used as
+ * early concole so that hwmod core doesn't reset and keep it in idle
+ * that specific uart.
+ */
+#ifdef CONFIG_SERIAL_EARLYCON
+static void __init omap_hwmod_setup_earlycon_flags(void)
+{
+ struct device_node *np;
+ struct omap_hwmod *oh;
+ const char *uart;
+
+ np = of_find_node_by_path("/chosen");
+ if (!np)
+ np = of_find_node_by_path("/chosen@0");
+
+ if (np) {
+ uart = of_get_property(np, "stdout-path", NULL);
+ if (uart) {
+ np = of_find_node_by_path(uart);
+ if (np) {
+ uart = of_get_property(np, "ti,hwmods", NULL);
+ oh = omap_hwmod_lookup(uart);
+ if (oh)
+ oh->flags |= DEBUG_OMAPUART_FLAGS;
+ }
+ }
+ }
+}
+#endif
+
+/**
* omap_hwmod_setup_all - set up all registered IP blocks
*
* Initialize and set up all IP blocks registered with the hwmod code.
@@ -3261,6 +3294,9 @@ static int __init omap_hwmod_setup_all(void)
_ensure_mpu_hwmod_is_setup(NULL);
omap_hwmod_for_each(_init, NULL);
+#ifdef CONFIG_SERIAL_EARLYCON
+ omap_hwmod_setup_earlycon_flags();
+#endif
omap_hwmod_for_each(_setup, NULL);
return 0;
--
2.11.0
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^ permalink raw reply related
* [PATCH 2/5] ARM: dts: am33xx: Add stdout-path property
From: Lokesh Vutla @ 2017-01-17 4:03 UTC (permalink / raw)
To: Tony Lindgren, Linux OMAP Mailing List
Cc: Device Tree Mailing List, Rob Herring, Tero Kristo, Sekhar Nori,
Vignesh R, Nishanth Menon, Lokesh Vutla
In-Reply-To: <20170117040336.21700-1-lokeshvutla-l0cyMroinI0@public.gmane.org>
Add stdout-path property in /chosen node so that earlycon can be
used by just adding earlycon in bootargs.
Signed-off-by: Lokesh Vutla <lokeshvutla-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/am335x-evm.dts | 4 ++++
arch/arm/boot/dts/am335x-evmsk.dts | 4 ++++
arch/arm/boot/dts/am335x-icev2.dts | 4 ++++
3 files changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index c2186ec2834b..1c37a7c1ea17 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -25,6 +25,10 @@
reg = <0x80000000 0x10000000>; /* 256 MB */
};
+ chosen {
+ stdout-path = &uart0;
+ };
+
vbat: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index e2548d1ce753..9e43c443738a 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -32,6 +32,10 @@
reg = <0x80000000 0x10000000>; /* 256 MB */
};
+ chosen {
+ stdout-path = &uart0;
+ };
+
vbat: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts
index 1463df3b5b19..ff9417ce93c0 100644
--- a/arch/arm/boot/dts/am335x-icev2.dts
+++ b/arch/arm/boot/dts/am335x-icev2.dts
@@ -24,6 +24,10 @@
reg = <0x80000000 0x10000000>; /* 256 MB */
};
+ chosen {
+ stdout-path = &uart3;
+ };
+
vbat: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
--
2.11.0
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^ permalink raw reply related
* [PATCH 3/5] ARM: dts: am43xx: Add stdout-path property
From: Lokesh Vutla @ 2017-01-17 4:03 UTC (permalink / raw)
To: Tony Lindgren, Linux OMAP Mailing List
Cc: Device Tree Mailing List, Rob Herring, Tero Kristo, Sekhar Nori,
Vignesh R, Nishanth Menon, Lokesh Vutla
In-Reply-To: <20170117040336.21700-1-lokeshvutla-l0cyMroinI0@public.gmane.org>
Add stdout-path property in /chosen node so that earlycon can be
used by just adding earlycon in bootargs.
Signed-off-by: Lokesh Vutla <lokeshvutla-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/am437x-gp-evm.dts | 4 ++++
arch/arm/boot/dts/am437x-idk-evm.dts | 4 ++++
arch/arm/boot/dts/am437x-sk-evm.dts | 4 ++++
arch/arm/boot/dts/am43x-epos-evm.dts | 4 ++++
4 files changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 957840cc7b78..a4f31739057f 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -23,6 +23,10 @@
display0 = &lcd0;
};
+ chosen {
+ stdout-path = &uart0;
+ };
+
evm_v3_3d: fixedregulator-v3_3d {
compatible = "regulator-fixed";
regulator-name = "evm_v3_3d";
diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts
index b76a7c0264a5..c1f7f9336e64 100644
--- a/arch/arm/boot/dts/am437x-idk-evm.dts
+++ b/arch/arm/boot/dts/am437x-idk-evm.dts
@@ -18,6 +18,10 @@
model = "TI AM437x Industrial Development Kit";
compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43";
+ chosen {
+ stdout-path = &uart0;
+ };
+
v24_0d: fixed-regulator-v24_0d {
compatible = "regulator-fixed";
regulator-name = "V24_0D";
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index 319d94205350..4dc54bee2f36 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -24,6 +24,10 @@
display0 = &lcd0;
};
+ chosen {
+ stdout-path = &uart0;
+ };
+
/* fixed 32k external oscillator clock */
clk_32k_rtc: clk_32k_rtc {
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 9d35c3f07cad..9acd4ccdec4e 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -24,6 +24,10 @@
display0 = &lcd0;
};
+ chosen {
+ stdout-path = &uart0;
+ };
+
vmmcsd_fixed: fixedregulator-sd {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
--
2.11.0
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^ permalink raw reply related
* [PATCH 4/5] ARM: dts: am57xx: Add stdout-path property
From: Lokesh Vutla @ 2017-01-17 4:03 UTC (permalink / raw)
To: Tony Lindgren, Linux OMAP Mailing List
Cc: Device Tree Mailing List, Rob Herring, Tero Kristo, Sekhar Nori,
Vignesh R, Nishanth Menon, Lokesh Vutla
In-Reply-To: <20170117040336.21700-1-lokeshvutla-l0cyMroinI0@public.gmane.org>
Add stdout-path property in /chosen node so that earlycon can be
used by just adding earlycon in bootargs.
Signed-off-by: Lokesh Vutla <lokeshvutla-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 4 ++++
arch/arm/boot/dts/am57xx-idk-common.dtsi | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
index 78bee26361f1..3a95db7da71f 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
@@ -22,6 +22,10 @@
display0 = &hdmi0;
};
+ chosen {
+ stdout-path = &uart3;
+ };
+
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi
index 814a720d5c3d..0d341c545b01 100644
--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
@@ -14,6 +14,10 @@
rtc1 = &rtc;
};
+ chosen {
+ stdout-path = &uart3;
+ };
+
vmain: fixedregulator-vmain {
compatible = "regulator-fixed";
regulator-name = "VMAIN";
--
2.11.0
--
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* [PATCH 5/5] ARM: dts: dra7xx: Add stdout-path property
From: Lokesh Vutla @ 2017-01-17 4:03 UTC (permalink / raw)
To: Tony Lindgren, Linux OMAP Mailing List
Cc: Device Tree Mailing List, Rob Herring, Tero Kristo, Sekhar Nori,
Vignesh R, Nishanth Menon, Lokesh Vutla
In-Reply-To: <20170117040336.21700-1-lokeshvutla-l0cyMroinI0@public.gmane.org>
Add stdout-path property in /chosen node so that earlycon can be
used by just adding earlycon in bootargs.
Tested-by: Vignesh R <vigneshr-l0cyMroinI0@public.gmane.org>
Signed-off-by: Lokesh Vutla <lokeshvutla-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/dra7-evm.dts | 4 ++++
arch/arm/boot/dts/dra72-evm-common.dtsi | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 132f2be10889..b3923c049edb 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -21,6 +21,10 @@
reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
};
+ chosen {
+ stdout-path = &uart1;
+ };
+
evm_3v3_sd: fixedregulator-sd {
compatible = "regulator-fixed";
regulator-name = "evm_3v3_sd";
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index e50fbeea96e0..45b62138cbde 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -18,6 +18,10 @@
display0 = &hdmi0;
};
+ chosen {
+ stdout-path = &uart1;
+ };
+
evm_12v0: fixedregulator-evm12v0 {
/* main supply */
compatible = "regulator-fixed";
--
2.11.0
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* RE: [PATCH 1/2] dt-bindings: document renesas-ostm timer
From: Chris Brandt @ 2017-01-17 4:16 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Russell King, Daniel Lezcano, Thomas Gleixner, Geert Uytterhoeven,
devicetree@vger.kernel.org, Linux-Renesas
In-Reply-To: <CAMuHMdVC2BV6=jT1CZ+X92=_th-cEc0=hsiyRYxU5qMLoMVPMw@mail.gmail.com>
Hi Geert,
On Monday, January 16, 2017, Geert Uytterhoeven wrote:
> > Do you think it would be better if a driver instance only does 1
> > thing: Either 'clocksource' or 'clock event'??
> > Then, I would make 2 ostm nodes and pass in the mode I would like it
> operate in?
> >
> > For example:
> >
> > &ostm0 {
> > mode = "clocksource";
> > status = "okay";
> > };
> >
> > &ostm1 {
> > mode = "clock-event";
> > status = "okay";
> > };
>
> Again, that's software policy, not hardware description.
>
> As they're independent channels, it doesn't matter which one is used for
> which function, right?
Correct.
> You could use the first probed channel for the most important function
> (clocksource?), and the second one for the other function (clockevent).
> So there's no need for specifying this in DT.
>
> Does that make sense?
That works for me. I'll modify the driver and retest. Thanks for the idea!
Chris
^ permalink raw reply
* RE: [PATCH] ARM: dts: r7s72100: fix sdhi clock define
From: Chris Brandt @ 2017-01-17 4:27 UTC (permalink / raw)
To: Wolfram Sang, Geert Uytterhoeven
Cc: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Linux-Renesas,
Wolfram Sang
In-Reply-To: <20170116114023.GA3029@katana>
Hi Wolfram and Geert,
On Monday, January 16, 2017, Wolfram Sang:
> > > and then in the code do:
> > >
> > > struct *cd_clk;
> > > cd_clk = devm_clk_get(&pdev->dev, "cd");
> > > if (cd_clk) {
> > > clk_prepare_enable(cd_clk);
> > > }
> > >
> > > (this simple 1-line fix patch is getting a lot more complicated)
> >
> > Disclaimer: I don't know how/if the SDHI core manages clocks, and may
> > interfere. Adding Wolfram.
>
> Thanks for the heads up.
>
> We have special callbacks for en-/disabling clocks:
> sh_mobile_sdhi_clk_enable() and sh_mobile_sdhi_clk_disable().
>
> I think those functions should get the above if-blocks (without curly
> braces) to ensure we always have consistent 00 or 11 settings.
Well....
I was going to try and cheat and in the probe, enable both the core
and card-detect clocks, but, not save the card-detect clock pointer.
Basically, once it is turned on, it is never turned off (since it was intended
to be used for low power operation anyway).
The reason is that would then keep me from having to modify the existing
functions sh_mobile_sdhi_clk_enable/disable.
Is anyone going to have an issue if I turn the card-detect clock on but never
turn it off???? That was the patch that I was going to test out and submit.
Chris
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^ permalink raw reply
* Re: [PATCH v11 05/12] drm/mediatek: add BLS component
From: CK Hu @ 2017-01-17 5:07 UTC (permalink / raw)
To: YT Shen
Cc: Mark Rutland, devicetree, srv_heupstream, emil.l.velikov,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Matthias Brugger, yingjoe.chen, linux-arm-kernel
In-Reply-To: <1484117473-46644-6-git-send-email-yt.shen@mediatek.com>
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> Add BLS component for PWM + GAMMA function
>
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 5 ++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 3ff788c..f6e853a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -255,6 +255,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
> [MTK_DISP_PWM] = "pwm",
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> + [MTK_DISP_BLS] = "bls",
> };
>
> struct mtk_ddp_comp_match {
> @@ -265,6 +266,7 @@ struct mtk_ddp_comp_match {
>
> static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal },
> + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
> [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
> [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
> [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL },
> @@ -336,7 +338,8 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
> comp->id = comp_id;
> comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs;
>
> - if (comp_id == DDP_COMPONENT_DPI0 ||
> + if (comp_id == DDP_COMPONENT_BLS ||
> + comp_id == DDP_COMPONENT_DPI0 ||
> comp_id == DDP_COMPONENT_DSI0 ||
> comp_id == DDP_COMPONENT_PWM0) {
> comp->regs = NULL;
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 22a33ee..0828cf8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -36,11 +36,13 @@ enum mtk_ddp_comp_type {
> MTK_DISP_PWM,
> MTK_DISP_MUTEX,
> MTK_DISP_OD,
> + MTK_DISP_BLS,
> MTK_DDP_COMP_TYPE_MAX,
> };
>
> enum mtk_ddp_comp_id {
> DDP_COMPONENT_AAL,
> + DDP_COMPONENT_BLS,
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> DDP_COMPONENT_DPI0,
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^ permalink raw reply
* Re: [PATCH v11 06/12] drm/mediatek: update display module connections
From: CK Hu @ 2017-01-17 5:19 UTC (permalink / raw)
To: YT Shen
Cc: Mark Rutland, devicetree, srv_heupstream, emil.l.velikov,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Matthias Brugger, yingjoe.chen, linux-arm-kernel
In-Reply-To: <1484117473-46644-7-git-send-email-yt.shen@mediatek.com>
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> update connections for OVL, RDMA, BLS, DSI
>
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index b77d456..a9b209c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -32,6 +32,10 @@
> #define DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN 0x0c8
> #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
>
> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
> +#define DISP_REG_CONFIG_OUT_SEL 0x04c
> +#define DISP_REG_CONFIG_DSI_SEL 0x050
> +
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> @@ -71,6 +75,10 @@
> #define DPI0_SEL_IN_RDMA1 0x1
> #define COLOR1_SEL_IN_OVL1 0x1
>
> +#define OVL_MOUT_EN_RDMA 0x1
> +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
> +#define DSI_SEL_IN_BLS 0x0
> +
> struct mtk_disp_mutex {
> int id;
> bool claimed;
> @@ -111,6 +119,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> value = OVL0_MOUT_EN_COLOR0;
> + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> + value = OVL_MOUT_EN_RDMA;
> } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) {
> *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> value = OD_MOUT_EN_RDMA0;
> @@ -148,6 +159,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> value = COLOR1_SEL_IN_OVL1;
> + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DSI_SEL;
> + value = DSI_SEL_IN_BLS;
> } else {
> value = 0;
> }
> @@ -155,6 +169,15 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
> return value;
> }
>
> +static void mtk_ddp_sout_sel(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0)
> + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> + config_regs + DISP_REG_CONFIG_OUT_SEL);
> +}
> +
> void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next)
> @@ -167,6 +190,8 @@ void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
> writel_relaxed(reg, config_regs + addr);
> }
>
> + mtk_ddp_sout_sel(config_regs, cur, next);
> +
> value = mtk_ddp_sel_in(cur, next, &addr);
> if (value) {
> reg = readl_relaxed(config_regs + addr) | value;
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^ permalink raw reply
* Re: [PATCH] pcie: ti: Provide patch to force GEN1 PCIe operation
From: Kishon Vijay Abraham I @ 2017-01-17 5:35 UTC (permalink / raw)
To: Joao Pinto, Lukasz Majewski,
jingoohan1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Cc: Bjorn Helgaas, Rob Herring, Mark Rutland,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
linux-pci-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <76d18446-78c9-87f2-22ad-f7ea38771285-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>
Hi Joao,
On Monday 16 January 2017 10:31 PM, Joao Pinto wrote:
>
> Hi,
>
> Às 10:13 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:
>> + Joao, Jingoo
>>
>> Hi,
>>
>> On Monday 16 January 2017 03:01 PM, Lukasz Majewski wrote:
>>> Hi Kishon,
>>>
>>>> Hi Łukasz,
>>>>
>>>> On Monday 16 January 2017 12:19 PM, Lukasz Majewski wrote:
>>>>> Hi Kishon,
>>>>>
>>>>>> Hi,
>>>>>>
>>>>>> On Sunday 15 January 2017 06:49 PM, Lukasz Majewski wrote:
>>>>>>> Some devices (due to e.g. bad PCIe signal integrity) require to
>>>>>>> run with forced GEN1 speed on PCIe bus.
>>>>>>>
>>>>>>> This patch changes the speed explicitly on dra7 based devices when
>>>>>>> proper device tree attribute is defined for the PCIe controller.
>>>>>>>
>>>>>>> Signed-off-by: Lukasz Majewski <lukma-ynQEQJNshbs@public.gmane.org>
>>>>>>
>>>>>> Bjorn has already queued a patch to do the same thing
>>>>>> https://urldefense.proofpoint.com/v2/url?u=https-3A__git.kernel.org_cgit_linux_kernel_git_helgaas_pci.git_log_-3Fh-3Dpci_host-2Ddra7xx&d=DwIDaQ&c=DPL6_X_6JkXFx7AXWqB0tg&r=s2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io_kx0&m=zD82T5n4WcL7Ga-NSY2NI7KE75xQ99hN-mW2yX46wQk&s=E8zk1CbKxGH-f3fw_WpXxFU-A8BLkgA8NusCaxk1SvA&e=
>>>>>
>>>>> It seems like Bjorn only modifies CAP registers.
>>>>
>>>> The patch also modifies the LNKCTL2 register.
>>>>>
>>>>> He also needs to change register with 0x080C offset to actually
>>>>> ( PCIECTRL_PL_WIDTH_SPEED_CTL )
>>>>
>>>> This bit is used to initiate speed change (after the link is
>>>> initialized in GEN1). Resetting the bit (like what you have done
>>>> here) prevents speed change.
>>>
>>> This is strange, but e2e advised me to do things as I did in the patch
>>> to _force_ GEN1 operation on PCIe2 port [1] (AM5728)
>>>
>>> Link:
>>> [1] https://urldefense.proofpoint.com/v2/url?u=https-3A__e2e.ti.com_support_arm_sitara-5Farm_f_791_t_566421&d=DwIDaQ&c=DPL6_X_6JkXFx7AXWqB0tg&r=s2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io_kx0&m=zD82T5n4WcL7Ga-NSY2NI7KE75xQ99hN-mW2yX46wQk&s=uXLwglyRYqKpwp1JSxkOWmKpQ2wjfhgofpm8DCfquNw&e=
>>>
>>> Both patches modify 0x5180 007C register to set GEN1 capability
>>> (PCI_EXP_LNKCAP_SLS_2_5GB)
>>>
>>> The problem is with second register (in your patch):
>>>
>>> From SPRUHZ6G TRM:
>>>
>>> PCIECTRL_EP_DBICS_LNK_CAS_2 (0x5180 00A0)
>>> - TRGT_LINK_SPEED (Reset 0x1) - "Target Link Speed" - no more
>>> description in TRM
>>>
>>> It is set to PCI_EXP_LNKCAP_SLS_2_5GB = 0x1, which is the same as
>>> default /reset value.
>>
>> The default value is 0x2 (or else none of the cards would have enumerated in GEN2)
>>>
>>>
>>> Could you clarify which way to _force_ PCIe GEN1 operation is correct?
>>> Mine shows differences in lspci output (as posted in [1]).
>>
>> You'll see the difference even with the patch in Bjorn's tree ;-)
>>
>> I think these are 2 different approaches to keep the link at GEN1. Joao or
>> Jingoo, do you have any suggestion here?
>
> I studied the Databook, and both approaches seem to be right, dependently of the
> Core configuration and setup.
>
> The standard manual speed change sequence is:
> a) Write to PCIE_CAP_TARGET_LINK_SPEED (indicating desired speed)
> b) Clear "Directed Speed Change"
> c) Set "Directed Speed Change"
>
> If "Directed Speed Change" is set (DEFAULT_GEN2_SPEED_CHANGE is the default
> value), it will execute LTSSM to initiate speed change to Gen2 or Gen3, after
> link is started in Gen1, and then the bit is automatically cleared.
>
> Lukasz is reseting this bit, in order to avoid the LTSSM to be executed, which
> is correct. There is another way to prevent this automatic speed change, which
> is to set GEN1 speed before link up which might be difficult in some setups, so
> Kishon's also right.
Just for my understanding, why do you think this will be difficult in some setups?
>
> In my opinion Lukasz approach would be the one that might be more universal and
> more "secure".
IMHO setting link control in the standard PCIe header space should be more
universal. I'm not sure about the secure part though.
Thanks
Kishon
>
> Joao
>
>
>>
>>>
>>>>
>>>> IMO the better way is to set the LNKCTL2 to GEN1 instead of hacking
>>>> the IP register.
>>>
>>> From the original patch description:
>>>
>>> "Add support to force Root Complex to work in GEN1 mode if so desired,
>>> but don't force GEN1 mode on any board just yet."
>>>
>>> Are there any (floating around) patches allowing forcing GEN1 operation
>>> on any board (I would like to reuse/port them to my current solution)?
>>
>> For setting to GEN1 mode, "max-link-speed" should be set to 1 in dt with the
>> patch in Bjorn's tree.
>>
>> Thanks
>> Kishon
>>
>
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