* Re: [PATCH] ARM: dts: am33x, da816x, da814x: Remove useless register address
From: Tony Lindgren @ 2017-01-17 16:28 UTC (permalink / raw)
To: Alexandre Bailon
Cc: nsekhar-l0cyMroinI0, khilman-rdvid1DuHRBWk0Htik3J/w,
vinod.koul-ral2JQCrhuEAvxtiuMwx3w,
dmaengine-u79uwXL29TY76Z2rM5mHXA, ptitiano-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA, b-liu-l0cyMroinI0,
sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <08fc8b99-e6c4-7282-8023-b0d37956428c-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
* Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> [170117 08:17]:
> On 01/17/2017 04:47 PM, Tony Lindgren wrote:
> > * Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> [170117 05:55]:
> >> In order to make CPPI 4.1 DMA driver more generic, accesses to USBSS
> >> have been removed. So it is not required anymore to define "glue"
> >> register's address and size in DT.
> >> Remove "glue" register from cppi41dma node.
> >
> > Is this OK to queue later on after all the dependencies have been
> > merged?
> It should be queued on same time as "[PATCH v2 3/7] dmaengine: cppi41:
> Remove usbss_mem", so yes I guess it is OK.
Sounds like it will break things then.. Please read about "flag day"
changes and why they are not accepted.
You should make the driver work with the old and new binding, then
we can just drop the old binding later on from the dts files.
Regards,
Tony
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^ permalink raw reply
* Re: [PATCH v2 0/7] dmaengine: cppi41: Make CPPI 4.1 driver more generic
From: Tony Lindgren @ 2017-01-17 16:20 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Alexandre Bailon, vinod.koul-ral2JQCrhuEAvxtiuMwx3w,
b-liu-l0cyMroinI0, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
dmaengine-u79uwXL29TY76Z2rM5mHXA, nsekhar-l0cyMroinI0,
khilman-rdvid1DuHRBWk0Htik3J/w, ptitiano-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <28b57293-4395-4281-0c64-19f299e6eaf6-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
* Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> [170117 08:06]:
> On 01/17/2017 06:55 PM, Tony Lindgren wrote:
>
> > > Most of the patch of this series were part of
> > > "[PATCH 00/11] dmaengine: cppi41: Add dma support to da8xx"
> > >
> > > This series intend to make the CPPI 4.1 more generic in order to
> > > add a new platform (the DA8xx).
> > > To achieve that, all the IRQ code present in CPPI 4.1 driver has been moved
> > > to MUSB DSPS driver.
> > > Other changes mainly update the glue layer and platform code to make the
> > > whole driver more generic.
> >
> > So does da8xx use CPPI 4.1 DMA for other devices also in addition to
> > musb?
>
> No. DA8xx CPPI 4.1 is implemented as a part of the MUSB peripheral.
> But there were a SoC (support for which never got merged upstream) where
> CPPI 4.1 DMA is not limited to USB.
OK thanks for confirming it may pop up in some other devices too.
Anyways that means we can make the cppi41.c runtime PM support simpler
as it's always guaranteed to be enabled when in use with musb.
Regards,
Tony
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^ permalink raw reply
* Re: [PATCH v2 05/10] ASoC: Add sun8i digital audio codec
From: Mylene Josserand @ 2017-01-17 16:20 UTC (permalink / raw)
To: lgirdwood, broonie, perex, tiwai, maxime.ripard, wens, mturquette,
sboyd, mark.rutland, robh+dt
Cc: linux-kernel, linux-arm-kernel, linux-clk, alsa-devel, devicetree,
linux-sunxi, thomas.petazzoni, alexandre.belloni
In-Reply-To: <20170117140230.23142-6-mylene.josserand@free-electrons.com>
Hello everyone,
On 17/01/2017 15:02, Mylène Josserand wrote:
> Add the sun8i audio codec which handles the digital register of
> A33 codec.
> The driver handles only the basic playback from the DAC to headphones.
> All other features (microphone, capture, etc) will be added later.
>
> Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
[...]
> +static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params)
> +{
> + unsigned int rate = params_rate(params);
> +
> + switch (rate) {
> + case 8000:
> + case 7350:
> + return 0x0;
> + case 11025:
> + return 0x1;
> + case 12000:
> + return 0x2;
> + case 16000:
> + return 0x3;
> + case 22050:
> + return 0x4;
> + case 24000:
> + return 0x5;
> + case 32000:
> + return 0x6;
> + case 44100:
> + return 0x7;
> + case 48000:
> + return 0x8;
> + case 96000:
> + return 0x9;
> + case 192000:
> + return 0xa;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static u32 sun8i_codec_get_mod_freq(struct snd_pcm_hw_params *params)
> +{
> + unsigned int rate = params_rate(params);
> +
> + switch (rate) {
> + case 176400:
> + case 88200:
> + case 44100:
> + case 22050:
> + case 11025:
> + return 22579200;
> +
> + case 192000:
> + case 128000:
> + case 96000:
> + case 64000:
> + case 48000:
> + case 32000:
> + case 24000:
> + case 16000:
> + case 12000:
> + case 8000:
> + return 24576000;
> +
> + default:
> + return 0;
> + }
> +}
This function is not used anymore, I will remove it in v3 (once I will
get some reviews).
> +
> +static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
> +{
> + struct sun8i_codec *scodec = snd_soc_codec_get_drvdata(dai->codec);
> + u32 value;
> +
> + /* clock masters */
> + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
> + case SND_SOC_DAIFMT_CBS_CFS: /* DAI Slave */
> + value = 0x0; /* Codec Master */
> + break;
> + case SND_SOC_DAIFMT_CBM_CFM: /* DAI Master */
> + value = 0x1; /* Codec Slave */
> + break;
> + default:
> + return -EINVAL;
> + }
> + regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
> + BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD),
> + value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD);
> +
> + /* clock inversion */
> + switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
> + case SND_SOC_DAIFMT_NB_NF: /* Normal */
> + value = 0x0;
> + break;
> + case SND_SOC_DAIFMT_IB_IF: /* Inversion */
> + value = 0x1;
> + break;
> + default:
> + return -EINVAL;
> + }
> + regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
> + BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV),
> + value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV);
> + regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
> + BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV),
> + value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV);
> +
> + /* DAI format */
> + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
> + case SND_SOC_DAIFMT_I2S:
> + value = 0x0;
> + break;
> + case SND_SOC_DAIFMT_LEFT_J:
> + value = 0x1;
> + break;
> + case SND_SOC_DAIFMT_RIGHT_J:
> + value = 0x2;
> + break;
> + case SND_SOC_DAIFMT_DSP_A:
> + case SND_SOC_DAIFMT_DSP_B:
> + value = 0x3;
> + break;
> + default:
> + return -EINVAL;
> + }
> + regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
> + BIT(SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT),
> + value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT);
> +
> + return 0;
> +}
> +
> +static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
> + struct snd_pcm_hw_params *params,
> + struct snd_soc_dai *dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
Same things for these variables.
> + struct sun8i_codec *scodec = snd_soc_codec_get_drvdata(dai->codec);
> + u32 clk_freq;
> + int sample_rate, err;
ditto for "clk_freq" and "err" ones.
Sorry about that.
Best regards,
--
Mylène Josserand, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH] ARM: dts: am33x, da816x, da814x: Remove useless register address
From: Alexandre Bailon @ 2017-01-17 16:16 UTC (permalink / raw)
To: Tony Lindgren
Cc: nsekhar-l0cyMroinI0, khilman-rdvid1DuHRBWk0Htik3J/w,
vinod.koul-ral2JQCrhuEAvxtiuMwx3w,
dmaengine-u79uwXL29TY76Z2rM5mHXA, ptitiano-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA, b-liu-l0cyMroinI0,
sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170117154752.GH7403-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
On 01/17/2017 04:47 PM, Tony Lindgren wrote:
> * Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> [170117 05:55]:
>> In order to make CPPI 4.1 DMA driver more generic, accesses to USBSS
>> have been removed. So it is not required anymore to define "glue"
>> register's address and size in DT.
>> Remove "glue" register from cppi41dma node.
>
> Is this OK to queue later on after all the dependencies have been
> merged?
It should be queued on same time as "[PATCH v2 3/7] dmaengine: cppi41:
Remove usbss_mem", so yes I guess it is OK.
>
> Regards,
>
> Tony
>
Best Regards,
Alexandre
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^ permalink raw reply
* [PATCH v2 4/4] arm: dts: nsp: Add USB nodes to device tree
From: Yendapally Reddy Dhananjaya Reddy @ 2017-01-17 16:14 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Ray Jui, Scott Branden,
Jon Mason, Florian Fainelli, Kishon Vijay Abraham I
Cc: bcm-kernel-feedback-list, devicetree, linux-kernel,
linux-arm-kernel, netdev, Yendapally Reddy Dhananjaya Reddy
In-Reply-To: <1484669670-4201-1-git-send-email-yendapally.reddy@broadcom.com>
Add USB nodes to the Northstar plus device tree file
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 56 ++++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm958625k.dts | 16 ++++++++++++
2 files changed, 72 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index b6142bd..94b3231 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -259,6 +259,34 @@
status = "disabled";
};
+ xhci: usb@29000 {
+ compatible = "generic-xhci";
+ reg = <0x29000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci0: usb@2a000 {
+ compatible = "generic-ehci";
+ reg = <0x2a000 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ohci0: usb@2b000 {
+ compatible = "generic-ohci";
+ reg = <0x2b000 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ mdio: mdio@32000 {
+ compatible = "brcm,iproc-mdio";
+ reg = <0x32000 0x8>;
+ };
+
rng: rng@33000 {
compatible = "brcm,bcm-nsp-rng";
reg = <0x33000 0x14>;
@@ -358,6 +386,29 @@
"sata2";
};
+ mdio-mux {
+ compatible = "mdio-mux-mmioreg";
+ mdio-parent-bus = <&mdio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x32000 0x4>;
+ mux-mask = <0x200>;
+
+ mdio@0 {
+ reg = <0x00>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_phy: usb-phy@10 {
+ compatible = "brcm,nsp-usb3-phy";
+ reg = <0x10>;
+ usb3-ctrl-syscon = <&usb3_ctrl>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
pinctrl: pinctrl@3f1c0 {
compatible = "brcm,nsp-pinmux";
reg = <0x3f1c0 0x04>,
@@ -406,6 +457,11 @@
phy-names = "sata-phy";
};
};
+
+ usb3_ctrl: syscon@104408 {
+ compatible = "brcm,nsp-usb3-ctrl", "syscon";
+ reg = <0x104408 0x3fc>;
+ };
};
pcie0: pcie@18012000 {
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 59d96fb..1da22dc 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -53,6 +53,22 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
--
2.1.0
^ permalink raw reply related
* [PATCH v2 3/4] phy: Add USB3 PHY support for Broadcom NSP SoC
From: Yendapally Reddy Dhananjaya Reddy @ 2017-01-17 16:14 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Ray Jui, Scott Branden,
Jon Mason, Florian Fainelli, Kishon Vijay Abraham I
Cc: bcm-kernel-feedback-list, devicetree, linux-kernel,
linux-arm-kernel, netdev, Yendapally Reddy Dhananjaya Reddy
In-Reply-To: <1484669670-4201-1-git-send-email-yendapally.reddy@broadcom.com>
This patch adds support for Broadcom NSP USB3 PHY
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
drivers/phy/Kconfig | 8 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-bcm-nsp-usb3.c | 176 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 185 insertions(+)
create mode 100644 drivers/phy/phy-bcm-nsp-usb3.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index e8eb7f2..f95aa0d 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -486,4 +486,12 @@ config PHY_MESON8B_USB2
and GXBB SoCs.
If unsure, say N.
+config PHY_NSP_USB3
+ tristate "Broadcom NorthStar plus USB3 PHY driver"
+ depends on OF && (ARCH_BCM_NSP || COMPILE_TEST)
+ select GENERIC_PHY
+ default ARCH_BCM_NSP
+ help
+ Enable this to support the Broadcom Northstar plus USB3 PHY.
+ If unsure, say N.
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 65eb2f4..a96acd8 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -59,3 +59,4 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o
obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
+obj-$(CONFIG_PHY_NSP_USB3) += phy-bcm-nsp-usb3.o
diff --git a/drivers/phy/phy-bcm-nsp-usb3.c b/drivers/phy/phy-bcm-nsp-usb3.c
new file mode 100644
index 0000000..0033382
--- /dev/null
+++ b/drivers/phy/phy-bcm-nsp-usb3.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2016 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mdio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+#define NSP_USB3_RST_CTRL_OFFSET 0x3f8
+
+/* mdio reg access */
+#define NSP_USB3_PHY_BASE_ADDR_REG 0x1f
+
+#define NSP_USB3_PHY_PLL30_BLOCK 0x8000
+#define NSP_USB3_PLL_CONTROL 0x01
+#define NSP_USB3_PLLA_CONTROL0 0x0a
+#define NSP_USB3_PLLA_CONTROL1 0x0b
+
+#define NSP_USB3_PHY_TX_PMD_BLOCK 0x8040
+#define NSP_USB3_TX_PMD_CONTROL1 0x01
+
+#define NSP_USB3_PHY_PIPE_BLOCK 0x8060
+#define NSP_USB3_LFPS_CMP 0x02
+#define NSP_USB3_LFPS_DEGLITCH 0x03
+
+struct nsp_usb3_phy {
+ struct regmap *usb3_ctrl;
+ struct phy *phy;
+ struct mdio_device *mdiodev;
+};
+
+static int nsp_usb3_phy_init(struct phy *phy)
+{
+ struct nsp_usb3_phy *iphy = phy_get_drvdata(phy);
+ struct mii_bus *bus = iphy->mdiodev->bus;
+ int addr = iphy->mdiodev->addr;
+ u32 data;
+ int rc;
+
+ rc = regmap_read(iphy->usb3_ctrl, 0, &data);
+ if (rc)
+ return rc;
+ data |= 1;
+ rc = regmap_write(iphy->usb3_ctrl, 0, data);
+ if (rc)
+ return rc;
+
+ rc = regmap_write(iphy->usb3_ctrl, NSP_USB3_RST_CTRL_OFFSET, 1);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PHY_BASE_ADDR_REG,
+ NSP_USB3_PHY_PLL30_BLOCK);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PLL_CONTROL, 0x1000);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PLLA_CONTROL0, 0x6400);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PLLA_CONTROL1, 0xc000);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PLLA_CONTROL1, 0x8000);
+ if (rc)
+ return rc;
+
+ rc = regmap_write(iphy->usb3_ctrl, NSP_USB3_RST_CTRL_OFFSET, 0);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PLL_CONTROL, 0x9000);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PHY_BASE_ADDR_REG,
+ NSP_USB3_PHY_PIPE_BLOCK);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_LFPS_CMP, 0xf30d);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_LFPS_DEGLITCH, 0x6302);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PHY_BASE_ADDR_REG,
+ NSP_USB3_PHY_TX_PMD_BLOCK);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_TX_PMD_CONTROL1, 0x1003);
+
+ return rc;
+}
+
+static struct phy_ops nsp_usb3_phy_ops = {
+ .init = nsp_usb3_phy_init,
+};
+
+static int nsp_usb3_phy_probe(struct mdio_device *mdiodev)
+{
+ struct device *dev = &mdiodev->dev;
+ struct phy_provider *provider;
+ struct nsp_usb3_phy *iphy;
+
+ iphy = devm_kzalloc(dev, sizeof(*iphy), GFP_KERNEL);
+ if (!iphy)
+ return -ENOMEM;
+ iphy->mdiodev = mdiodev;
+
+ iphy->usb3_ctrl = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "usb3-ctrl-syscon");
+ if (IS_ERR(iphy->usb3_ctrl))
+ return PTR_ERR(iphy->usb3_ctrl);
+
+ iphy->phy = devm_phy_create(dev, dev->of_node, &nsp_usb3_phy_ops);
+ if (IS_ERR(iphy->phy)) {
+ dev_err(dev, "failed to create PHY\n");
+ return PTR_ERR(iphy->phy);
+ }
+
+ phy_set_drvdata(iphy->phy, iphy);
+
+ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(provider)) {
+ dev_err(dev, "could not register PHY provider\n");
+ return PTR_ERR(provider);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id nsp_usb3_phy_of_match[] = {
+ {.compatible = "brcm,nsp-usb3-phy",},
+ { /* sentinel */ }
+};
+
+static struct mdio_driver nsp_usb3_phy_driver = {
+ .mdiodrv = {
+ .driver = {
+ .name = "nsp-usb3-phy",
+ .of_match_table = nsp_usb3_phy_of_match,
+ },
+ },
+ .probe = nsp_usb3_phy_probe,
+};
+
+mdio_module_driver(nsp_usb3_phy_driver);
+
+MODULE_DESCRIPTION("Broadcom NSP USB3 PHY driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com");
--
2.1.0
^ permalink raw reply related
* [PATCH v2 2/4] net: phy: Initialize mdio clock at probe function
From: Yendapally Reddy Dhananjaya Reddy @ 2017-01-17 16:14 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Ray Jui, Scott Branden,
Jon Mason, Florian Fainelli, Kishon Vijay Abraham I
Cc: bcm-kernel-feedback-list, devicetree, linux-kernel,
linux-arm-kernel, netdev, Yendapally Reddy Dhananjaya Reddy
In-Reply-To: <1484669670-4201-1-git-send-email-yendapally.reddy@broadcom.com>
Initialize mdio clock divisor in probe function. The ext bus
bit available in the same register will be used by mdio mux
to enable external mdio.
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
drivers/net/phy/mdio-bcm-iproc.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/mdio-bcm-iproc.c b/drivers/net/phy/mdio-bcm-iproc.c
index c0b4e65..46fe1ae 100644
--- a/drivers/net/phy/mdio-bcm-iproc.c
+++ b/drivers/net/phy/mdio-bcm-iproc.c
@@ -81,8 +81,6 @@ static int iproc_mdio_read(struct mii_bus *bus, int phy_id, int reg)
if (rc)
return rc;
- iproc_mdio_config_clk(priv->base);
-
/* Prepare the read operation */
cmd = (MII_DATA_TA_VAL << MII_DATA_TA_SHIFT) |
(reg << MII_DATA_RA_SHIFT) |
@@ -112,8 +110,6 @@ static int iproc_mdio_write(struct mii_bus *bus, int phy_id,
if (rc)
return rc;
- iproc_mdio_config_clk(priv->base);
-
/* Prepare the write operation */
cmd = (MII_DATA_TA_VAL << MII_DATA_TA_SHIFT) |
(reg << MII_DATA_RA_SHIFT) |
@@ -163,6 +159,8 @@ static int iproc_mdio_probe(struct platform_device *pdev)
bus->read = iproc_mdio_read;
bus->write = iproc_mdio_write;
+ iproc_mdio_config_clk(priv->base);
+
rc = of_mdiobus_register(bus, pdev->dev.of_node);
if (rc) {
dev_err(&pdev->dev, "MDIO bus registration failed\n");
--
2.1.0
^ permalink raw reply related
* [PATCH v2 1/4] dt-bindings: phy: Add documentation for NSP USB3 PHY
From: Yendapally Reddy Dhananjaya Reddy @ 2017-01-17 16:14 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Ray Jui, Scott Branden,
Jon Mason, Florian Fainelli, Kishon Vijay Abraham I
Cc: bcm-kernel-feedback-list, devicetree, linux-kernel,
linux-arm-kernel, netdev, Yendapally Reddy Dhananjaya Reddy
In-Reply-To: <1484669670-4201-1-git-send-email-yendapally.reddy@broadcom.com>
Add documentation for USB3 PHY available in Northstar plus SoC
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
.../devicetree/bindings/phy/brcm,nsp-usb3-phy.txt | 39 ++++++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt b/Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt
new file mode 100644
index 0000000..e68ae5d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt
@@ -0,0 +1,39 @@
+Broadcom USB3 phy binding for northstar plus SoC
+The USB3 phy is internal to the SoC and is accessed using mdio interface.
+
+Required mdio bus properties:
+- reg: Should be 0x0 for SoC internal USB3 phy
+- #address-cells: must be 1
+- #size-cells: must be 0
+
+Required USB3 PHY properties:
+- compatible: should be "brcm,nsp-usb3-phy"
+- reg: USB3 Phy address on SoC internal MDIO bus and it should be 0x10.
+- usb3-ctrl-syscon: handler of syscon node defining physical address
+ of usb3 control register.
+- #phy-cells: must be 0
+
+Required usb3 control properties:
+- compatible: should be "brcm,nsp-usb3-ctrl"
+- reg: offset and length of the control registers
+
+Example:
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_phy: usb-phy@10 {
+ compatible = "brcm,nsp-usb3-phy";
+ reg = <0x10>;
+ usb3-ctrl-syscon = <&usb3_ctrl>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ usb3_ctrl: syscon@104408 {
+ compatible = "brcm,nsp-usb3-ctrl", "syscon";
+ reg = <0x104408 0x3fc>;
+ };
--
2.1.0
^ permalink raw reply related
* [PATCH v2 0/4] USB support for Broadcom NSP SoC
From: Yendapally Reddy Dhananjaya Reddy @ 2017-01-17 16:14 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Ray Jui, Scott Branden,
Jon Mason, Florian Fainelli, Kishon Vijay Abraham I
Cc: bcm-kernel-feedback-list, devicetree, linux-kernel,
linux-arm-kernel, netdev, Yendapally Reddy Dhananjaya Reddy
This patch set contains the usb support for Broadcom NSP SoC. The
usb3 phy is internal to the SoC and is accessed through mdio interface.
The mdio interface can be used to access either internal usb3 phy or
external ethernet phy using a multiplexer.
The first patch provides the documentation details for usb3 phy. The
second patch provides the changes to the mdio bus driver. The third
patch provides the phy driver and fourth patch provides the enable
method for usb.
This patch series has been tested on NSP bcm958625HR board.
This patch series is based on v4.10.0-rc3 and is available from
github-repo: https://github.com/Broadcom/cygnus-linux.git
branch:nsp-usb-v2
Changes in v2:
* Remove separate nsp mux driver as suggested by Andrew Lunn
* Addressed comments from Scott and Rob
Yendapally Reddy Dhananjaya Reddy (4):
dt-bindings: phy: Add documentation for NSP USB3 PHY
net: phy: Initialize mdio clock at probe function
phy: Add USB3 PHY support for Broadcom NSP SoC
arm: dts: nsp: Add USB nodes to device tree
.../devicetree/bindings/phy/brcm,nsp-usb3-phy.txt | 39 +++++
arch/arm/boot/dts/bcm-nsp.dtsi | 56 +++++++
arch/arm/boot/dts/bcm958625k.dts | 16 ++
drivers/net/phy/mdio-bcm-iproc.c | 6 +-
drivers/phy/Kconfig | 8 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-bcm-nsp-usb3.c | 176 +++++++++++++++++++++
7 files changed, 298 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt
create mode 100644 drivers/phy/phy-bcm-nsp-usb3.c
--
2.1.0
^ permalink raw reply
* [PATCH v3 5/5] dt-bindings: Document the STM32 USB OTG DWC2 core binding
From: Bruno Herrera @ 2017-01-17 16:12 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w,
alexandre.torgue-qxv4g6HH51o, johnyoun-HKixBCOQz3hWk0Htik3J/w,
felipe.balbi-VuQAYsv1563Yd54FQh9/CA
Cc: linux-usb-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170117161237.3802-1-bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
This patch adds the documentation for STM32F4x9 USB OTG FS/HS compatible strings.
Signed-off-by: Bruno Herrera <bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
Documentation/devicetree/bindings/usb/dwc2.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
index 6c7c2bce..637223a 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -14,6 +14,10 @@ Required properties:
- "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;
- "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs;
- snps,dwc2: A generic DWC2 USB controller with default parameters.
+ - "st,stm32f4xx-fsotg": The DWC2 USB FS/HS controller instance in STM32F4xx SoCs
+ configured in FS mode;
+ - "st,stm32f4xx-hsotg": The DWC2 USB HS controller instance in STM32F4xx SoCs
+ configured in HS mode;
- reg : Should contain 1 register range (address and length)
- interrupts : Should contain 1 interrupt
- clocks: clock provider specifier
--
2.10.1 (Apple Git-78)
--
To unsubscribe from this list: send the line "unsubscribe linux-usb" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v3 4/5] ARM: dts: stm32: Enable USB HS in FS mode (embedded phy) on stm32f429-disco
From: Bruno Herrera @ 2017-01-17 16:12 UTC (permalink / raw)
To: robh+dt, mark.rutland, mcoquelin.stm32, alexandre.torgue,
johnyoun, felipe.balbi
Cc: devicetree, linux-usb, linux-arm-kernel
In-Reply-To: <20170117161237.3802-1-bruherrera@gmail.com>
This patch enables USB HS working in FS mode on stm32f429-disco
with 5V VBUS enable.
Signed-off-by: Bruno Herrera <bruherrera@gmail.com>
---
arch/arm/boot/dts/stm32f429-disco.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts
index 7d0415e..0b2b017 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -88,6 +88,14 @@
gpios = <&gpioa 0 0>;
};
};
+
+ /* This turns on vbus for otg for host mode (dwc2) */
+ vcc5v_otg: vcc5v-otg-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpioc 4 0>;
+ regulator-name = "vcc5_host1";
+ regulator-always-on;
+ };
};
&clk_hse {
@@ -99,3 +107,11 @@
pinctrl-names = "default";
status = "okay";
};
+
+&usbotg_hs {
+ compatible = "st,stm32f4xx-fsotg";
+ dr_mode = "host";
+ pinctrl-0 = <&usbotg_fs_pins_b>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--
2.10.1 (Apple Git-78)
^ permalink raw reply related
* [PATCH v3 3/5] ARM: dts: stm32: Enable USB FS on stm32f469-disco
From: Bruno Herrera @ 2017-01-17 16:12 UTC (permalink / raw)
To: robh+dt, mark.rutland, mcoquelin.stm32, alexandre.torgue,
johnyoun, felipe.balbi
Cc: devicetree, linux-usb, linux-arm-kernel
In-Reply-To: <20170117161237.3802-1-bruherrera@gmail.com>
This patch enables USB FS on stm32f469-disco with 5V VBUS enable.
Signed-off-by: Bruno Herrera <bruherrera@gmail.com>
---
arch/arm/boot/dts/stm32f469-disco.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index 8877c00..3e0a83e 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -68,6 +68,15 @@
soc {
dma-ranges = <0xc0000000 0x0 0x10000000>;
};
+
+ /* This turns on vbus for otg for host mode (dwc2) */
+ vcc5v_otg: vcc5v-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpiob 2 0>;
+ regulator-name = "vcc5_host1";
+ regulator-always-on;
+ };
};
&rcc {
@@ -81,3 +90,10 @@
&usart3 {
status = "okay";
};
+
+&usbotg_fs {
+ dr_mode = "host";
+ pinctrl-0 = <&usbotg_fs_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--
2.10.1 (Apple Git-78)
^ permalink raw reply related
* [PATCH v3 2/5] ARM: dts: stm32: Add USB FS support for STM32F429 MCU
From: Bruno Herrera @ 2017-01-17 16:12 UTC (permalink / raw)
To: robh+dt, mark.rutland, mcoquelin.stm32, alexandre.torgue,
johnyoun, felipe.balbi
Cc: devicetree, linux-usb, linux-arm-kernel
In-Reply-To: <20170117161237.3802-1-bruherrera@gmail.com>
This patch adds the USB pins and nodes for USB FS core.
Signed-off-by: Bruno Herrera <bruherrera@gmail.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index e4dae0e..26f2395 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -316,6 +316,28 @@
};
};
+ usbotg_fs_pins_a: usbotg_fs@0 {
+ pins {
+ pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
+ <STM32F429_PA11_FUNC_OTG_FS_DM>,
+ <STM32F429_PA12_FUNC_OTG_FS_DP>;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ usbotg_fs_pins_b: usbotg_fs@1 {
+ pins {
+ pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
+ <STM32F429_PB14_FUNC_OTG_HS_DM>,
+ <STM32F429_PB15_FUNC_OTG_HS_DP>;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
usbotg_hs_pins_a: usbotg_hs@0 {
pins {
pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
@@ -420,6 +442,15 @@
status = "disabled";
};
+ usbotg_fs: usb@50000000 {
+ compatible = "st,stm32f4xx-fsotg";
+ reg = <0x50000000 0x40000>;
+ interrupts = <67>;
+ clocks = <&rcc 0 39>;
+ clock-names = "otg";
+ status = "disabled";
+ };
+
rng: rng@50060800 {
compatible = "st,stm32-rng";
reg = <0x50060800 0x400>;
--
2.10.1 (Apple Git-78)
^ permalink raw reply related
* [PATCH v3 1/5] usb: dwc2: Add support for STM32F429/439/469 USB OTG HS/FS in FS mode (internal PHY)
From: Bruno Herrera @ 2017-01-17 16:12 UTC (permalink / raw)
To: robh+dt, mark.rutland, mcoquelin.stm32, alexandre.torgue,
johnyoun, felipe.balbi
Cc: devicetree, linux-usb, linux-arm-kernel
In-Reply-To: <20170117161237.3802-1-bruherrera@gmail.com>
This patch introduces a new parameter to activate USB OTG HS/FS core embedded
phy transceiver. The STM32F4x9 SoC uses the GGPIO register to enable the transceiver.
Also add the dwc2_core_params structure for stm32f4 otg fs.
Signed-off-by: Bruno Herrera <bruherrera@gmail.com>
---
drivers/usb/dwc2/core.h | 4 ++++
drivers/usb/dwc2/hcd.c | 13 +++++++++++-
drivers/usb/dwc2/hw.h | 2 ++
drivers/usb/dwc2/params.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 69 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 9548d3e..e3199c5 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -430,6 +430,9 @@ enum dwc2_ep0_state {
* needed.
* 0 - No (default)
* 1 - Yes
+ * @activate_transceiver: Activate internal transceiver using GGPIO register.
+ * 0 - Deactivate the transceiver (default)
+ * 1 - Activate the transceiver
* @g_dma: Enables gadget dma usage (default: autodetect).
* @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
* @g_rx_fifo_size: The periodic rx fifo size for the device, in
@@ -501,6 +504,7 @@ struct dwc2_core_params {
int uframe_sched;
int external_id_pin_ctl;
int hibernation;
+ int activate_transceiver;
/*
* The following parameters are *only* set via device
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 911c3b3..6bee529 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -118,7 +118,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
{
- u32 usbcfg, i2cctl;
+ u32 usbcfg, ggpio, i2cctl;
int retval = 0;
/*
@@ -142,6 +142,17 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
return retval;
}
}
+
+ ggpio = dwc2_readl(hsotg->regs + GGPIO);
+ if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN) &&
+ (hsotg->params.activate_transceiver > 0)) {
+ dev_dbg(hsotg->dev, "Activating transceiver\n");
+ /* STM32F4xx uses the GGPIO register as general core
+ * configuration register.
+ */
+ ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
+ dwc2_writel(ggpio, hsotg->regs + GGPIO);
+ }
}
/*
diff --git a/drivers/usb/dwc2/hw.h b/drivers/usb/dwc2/hw.h
index 5be056b..a84e93b 100644
--- a/drivers/usb/dwc2/hw.h
+++ b/drivers/usb/dwc2/hw.h
@@ -225,6 +225,8 @@
#define GPVNDCTL HSOTG_REG(0x0034)
#define GGPIO HSOTG_REG(0x0038)
+#define GGPIO_STM32_OTG_GCCFG_PWRDWN (1 << 16)
+
#define GUID HSOTG_REG(0x003c)
#define GSNPSID HSOTG_REG(0x0040)
#define GHWCFG1 HSOTG_REG(0x0044)
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 11fe68a..dbb054d 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -192,6 +192,37 @@ static const struct dwc2_core_params params_amlogic = {
.hibernation = -1,
};
+static const struct dwc2_core_params params_stm32f4_otgfs = {
+ .otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE,
+ .otg_ver = -1,
+ .dma_desc_enable = 0,
+ .dma_desc_fs_enable = 0,
+ .speed = DWC2_SPEED_PARAM_FULL,
+ .enable_dynamic_fifo = -1,
+ .en_multiple_tx_fifo = -1,
+ .host_rx_fifo_size = 128, /* 128 DWORDs */
+ .host_nperio_tx_fifo_size = 96, /* 96 DWORDs */
+ .host_perio_tx_fifo_size = 96, /* 96 DWORDs */
+ .max_transfer_size = -1,
+ .max_packet_count = 256,
+ .host_channels = -1,
+ .phy_type = DWC2_PHY_TYPE_PARAM_FS,
+ .phy_utmi_width = -1,
+ .phy_ulpi_ddr = -1,
+ .phy_ulpi_ext_vbus = -1,
+ .i2c_enable = 0,
+ .ulpi_fs_ls = -1,
+ .host_support_fs_ls_low_power = -1,
+ .host_ls_low_power_phy_clk = -1,
+ .ts_dline = -1,
+ .reload_ctl = -1,
+ .ahbcfg = -1,
+ .uframe_sched = 0,
+ .external_id_pin_ctl = -1,
+ .hibernation = -1,
+ .activate_transceiver = 1,
+};
+
static const struct dwc2_core_params params_default = {
.otg_cap = -1,
.otg_ver = -1,
@@ -240,6 +271,8 @@ const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = "amlogic,meson8b-usb", .data = ¶ms_amlogic },
{ .compatible = "amlogic,meson-gxbb-usb", .data = ¶ms_amlogic },
{ .compatible = "amcc,dwc-otg", .data = NULL },
+ { .compatible = "st,stm32f4xx-fsotg", .data = ¶ms_stm32f4_otgfs },
+ { .compatible = "st,stm32f4xx-hsotg", .data = NULL },
{},
};
MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
@@ -1044,6 +1077,23 @@ static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
hsotg->params.hibernation = val;
}
+static void dwc2_set_param_activate_transceiver(struct dwc2_hsotg *hsotg,
+ int val)
+{
+ if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
+ if (val >= 0) {
+ dev_err(hsotg->dev,
+ "'%d' invalid for parameter activate transceiver\n",
+ val);
+ dev_err(hsotg->dev, "activate transceiver must be 0 or 1\n");
+ }
+ val = 0;
+ dev_dbg(hsotg->dev, "Setting activate transceiver to %d\n", val);
+ }
+
+ hsotg->params.activate_transceiver = val;
+}
+
static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
{
int i;
@@ -1158,6 +1208,7 @@ static void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
dwc2_set_param_hibernation(hsotg, params->hibernation);
+ dwc2_set_param_activate_transceiver(hsotg, params->activate_transceiver);
/*
* Set devicetree-only parameters. These parameters do not
--
2.10.1 (Apple Git-78)
^ permalink raw reply related
* [PATCH v3 0/5] usb: dwc2: Add support for USB OTG on STM32F4x9
From: Bruno Herrera @ 2017-01-17 16:12 UTC (permalink / raw)
To: robh+dt, mark.rutland, mcoquelin.stm32, alexandre.torgue,
johnyoun, felipe.balbi
Cc: devicetree, linux-usb, linux-arm-kernel
The STM32F4x9 MCU family has two DWC2 USB OTG cores on it. One core is
USB OTG FS and other core is USB OTG HS. The USB FS core only works with
its internal phy whilst the USF HS core can work in HS with external ulpi
phy or in FS/LS speed with the embedded FS PHY.
The goal of this patch series is to enable the use of USB OTG FS/HS cores
in FS mode using the internal phy.
Changes since v3:
- Removed commented lines from patch (sent by mistake)
- Split DTS patch by boards and SOC
- Removed unnecessary pinctrl nodes from DTS files
Changes since v2:
- Rename driver variables to meet the driver standard
- Add compatible string for HS core
Changes since v1:
- Add dwc2_core_params structure for stm32f4 otg fs
- Add compatible string for FS core/mode
- Use GGPIO register to deativate power down of the phy
Bruno Herrera (5):
usb: dwc2: Add support for STM32F429/439/469 USB OTG HS/FS in FS mode
(internal PHY)
ARM: dts: stm32: Add USB FS support for STM32F429 MCU
ARM: dts: stm32: Enable USB FS on stm32f469-disco
ARM: dts: stm32: Enable USB HS in FS mode (embedded phy) on
stm32f429-disco
dt-bindings: Document the STM32 USB OTG DWC2 core binding
Documentation/devicetree/bindings/usb/dwc2.txt | 4 ++
arch/arm/boot/dts/stm32f429-disco.dts | 16 ++++++++
arch/arm/boot/dts/stm32f429.dtsi | 31 ++++++++++++++++
arch/arm/boot/dts/stm32f469-disco.dts | 16 ++++++++
drivers/usb/dwc2/core.h | 4 ++
drivers/usb/dwc2/hcd.c | 13 ++++++-
drivers/usb/dwc2/hw.h | 2 +
drivers/usb/dwc2/params.c | 51 ++++++++++++++++++++++++++
8 files changed, 136 insertions(+), 1 deletion(-)
--
2.10.1 (Apple Git-78)
^ permalink raw reply
* Re: [PATCH v2 0/7] dmaengine: cppi41: Make CPPI 4.1 driver more generic
From: Sergei Shtylyov @ 2017-01-17 16:05 UTC (permalink / raw)
To: Tony Lindgren, Alexandre Bailon
Cc: vinod.koul-ral2JQCrhuEAvxtiuMwx3w, b-liu-l0cyMroinI0,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, dmaengine-u79uwXL29TY76Z2rM5mHXA,
nsekhar-l0cyMroinI0, khilman-rdvid1DuHRBWk0Htik3J/w,
ptitiano-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170117155545.GI7403-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
On 01/17/2017 06:55 PM, Tony Lindgren wrote:
>> Most of the patch of this series were part of
>> "[PATCH 00/11] dmaengine: cppi41: Add dma support to da8xx"
>>
>> This series intend to make the CPPI 4.1 more generic in order to
>> add a new platform (the DA8xx).
>> To achieve that, all the IRQ code present in CPPI 4.1 driver has been moved
>> to MUSB DSPS driver.
>> Other changes mainly update the glue layer and platform code to make the
>> whole driver more generic.
>
> So does da8xx use CPPI 4.1 DMA for other devices also in addition to
> musb?
No. DA8xx CPPI 4.1 is implemented as a part of the MUSB peripheral.
But there were a SoC (support for which never got merged upstream) where CPPI
4.1 DMA is not limited to USB.
> Regards,
>
> Tony
MBR, Sergei
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^ permalink raw reply
* Re: [PATCH v2 04/14] sata: ahci-da850: get the sata clock using a connector id
From: Sergei Shtylyov @ 2017-01-17 16:02 UTC (permalink / raw)
To: Bartosz Golaszewski, Kevin Hilman, Sekhar Nori, Patrick Titiano,
Michael Turquette, Tejun Heo, Rob Herring, Mark Rutland,
Russell King, David Lechner
Cc: linux-ide, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <1484655976-25382-5-git-send-email-bgolaszewski@baylibre.com>
Hello!
On 01/17/2017 03:26 PM, Bartosz Golaszewski wrote:
> In preparation for using two clocks in the driver (the sysclk2-based
> clock and the external REFCLK), check if we got a functional clock
> after calling ahci_platform_get_resources(). If not, retry calling
> get_clk() with con_id specified.
clk_get().
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
> drivers/ata/ahci_da850.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/ata/ahci_da850.c b/drivers/ata/ahci_da850.c
> index 267a3d3..18f57c2 100644
> --- a/drivers/ata/ahci_da850.c
> +++ b/drivers/ata/ahci_da850.c
> @@ -71,12 +71,28 @@ static int ahci_da850_probe(struct platform_device *pdev)
> struct ahci_host_priv *hpriv;
> struct resource *res;
> void __iomem *pwrdn_reg;
> + struct clk *clk;
> int rc;
>
> hpriv = ahci_platform_get_resources(pdev);
> if (IS_ERR(hpriv))
> return PTR_ERR(hpriv);
>
> + /*
> + * Internally ahci_platform_get_resources() calls clk_get(dev, NULL)
> + * when trying to obtain the first clock. This SATA controller uses
> + * two clocks for which we specify two connector ids. If we don't
It's called connection ID, IIRC.
[...]
MBR, Sergei
^ permalink raw reply
* Re: [PATCH v2 0/7] dmaengine: cppi41: Make CPPI 4.1 driver more generic
From: Tony Lindgren @ 2017-01-17 15:55 UTC (permalink / raw)
To: Alexandre Bailon
Cc: vinod.koul-ral2JQCrhuEAvxtiuMwx3w, b-liu-l0cyMroinI0,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, dmaengine-u79uwXL29TY76Z2rM5mHXA,
nsekhar-l0cyMroinI0, khilman-rdvid1DuHRBWk0Htik3J/w,
ptitiano-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170117134540.9988-1-abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
* Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> [170117 05:46]:
> Most of the patch of this series were part of
> "[PATCH 00/11] dmaengine: cppi41: Add dma support to da8xx"
>
> This series intend to make the CPPI 4.1 more generic in order to
> add a new platform (the DA8xx).
> To achieve that, all the IRQ code present in CPPI 4.1 driver has been moved
> to MUSB DSPS driver.
> Other changes mainly update the glue layer and platform code to make the
> whole driver more generic.
So does da8xx use CPPI 4.1 DMA for other devices also in addition to
musb?
Regards,
Tony
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^ permalink raw reply
* Re: [PATCH v3] mtd: spi-nor: add dt support for Everspin MRAMs
From: Rafał Miłecki @ 2017-01-17 15:49 UTC (permalink / raw)
To: Cyrille Pitchen
Cc: Uwe Kleine-König, Masahiko Iwamoto, Jagan Teki, Marek Vasut,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Sascha Hauer, Geert Uytterhoeven, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <82a0b0f7-a94b-70b5-1a5e-e5c04943a684-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
On 17 January 2017 at 14:57, Cyrille Pitchen <cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org> wrote:
> Le 17/01/2017 à 14:16, Rafał Miłecki a écrit :
>> On 17 January 2017 at 12:03, Uwe Kleine-König
>> <u.kleine-koenig-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
>>> The MR25 family doesn't support JEDEC, so they need explicit mentioning
>>> in the list of supported spi IDs. This makes it possible to add these
>>> using for example:
>>>
>>> compatible = "everspin,mr25h40";
>>
>> (...)
>>
>>> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
>>> index 2c91c03e7eb0..3e920ec5c4d3 100644
>>> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
>>> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
>>> @@ -14,6 +14,8 @@ Required properties:
>>> at25df641
>>> at26df081a
>>> mr25h256
>>> + mr25h10
>>> + mr25h40
>>> mx25l4005a
>>> mx25l1606e
>>> mx25l6405d
>>
>> Uh, this is getting a never-ending-story...
>> If these chipsets don't support JEDEC, should we keep them in jedec,spi-nor.txt?
>>
>
> Maybe not but I think the new compatible strings should be documented
> somewhere. Currently jedec,spi-nor.txt already documents all the
> "m25p*-nonjedec" memories. So maybe just renaming the jedec,spi-nor.txt
> file into spi-nor.txt or mtd,spi-nor.txt could be a solution. Otherwise, we
> can let it as is. I have no idea of what would be the best solution.
>
> To be honest, I don't always fully understand the DT policy/philosophy and
> its requirements. I just thought when a new property or a new value is
> introduced it has to be documented.
> Generally speaking, when DT is involved in some series of patches, it often
> generates many discussions about the proper way to do thinks and about
> choosing the best between many technically functional solutions.
>
> If you think jedec,spi-nor.txt is not suited to document the new value for
> the compatible string, why not, I perfectly understand your point.
>
> I don't mind choosing another way. I just want to be sure that, if not all,
> most of people agree on that solution and if possible, it is compliant with
> DT policy so everybody is happy and works together.
> That's why I involve DT people, even if it's a small detail, so they can
> advise us.
>
> Anyway, at some point we have to take a decision to carry on thinks.
> So actually, I would like to avoid a never-ending story :)
Sounds OK to me, I'm not DT expert though ;)
--
Rafał
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^ permalink raw reply
* Re: [PATCH] ARM: dts: am33x, da816x, da814x: Remove useless register address
From: Tony Lindgren @ 2017-01-17 15:47 UTC (permalink / raw)
To: Alexandre Bailon
Cc: nsekhar-l0cyMroinI0, khilman-rdvid1DuHRBWk0Htik3J/w,
vinod.koul-ral2JQCrhuEAvxtiuMwx3w,
dmaengine-u79uwXL29TY76Z2rM5mHXA, ptitiano-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA, b-liu-l0cyMroinI0,
sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170117135420.10197-1-abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
* Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> [170117 05:55]:
> In order to make CPPI 4.1 DMA driver more generic, accesses to USBSS
> have been removed. So it is not required anymore to define "glue"
> register's address and size in DT.
> Remove "glue" register from cppi41dma node.
Is this OK to queue later on after all the dependencies have been
merged?
Regards,
Tony
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^ permalink raw reply
* [PATCH v2] ARM: dts: da850: Add the CPPI 4.1 DMA to the USB OTG controller
From: Alexandre Bailon @ 2017-01-17 15:32 UTC (permalink / raw)
To: nsekhar-l0cyMroinI0, khilman-rdvid1DuHRBWk0Htik3J/w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: vinod.koul-ral2JQCrhuEAvxtiuMwx3w,
dmaengine-u79uwXL29TY76Z2rM5mHXA, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
b-liu-l0cyMroinI0,
sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8,
devicetree-u79uwXL29TY76Z2rM5mHXA, Alexandre Bailon
This adds the CPPI 4.1 DMA controller to the USB OTG controller.
Signed-off-by: Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
arch/arm/boot/dts/da850.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 104155d..35f1af4 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -396,12 +396,39 @@
usb0: usb@200000 {
compatible = "ti,da830-musb";
reg = <0x200000 0x10000>;
+ ranges;
interrupts = <58>;
interrupt-names = "mc";
dr_mode = "otg";
phys = <&usb_phy 0>;
phy-names = "usb-phy";
status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ dmas = <&cppi41dma 0 0 &cppi41dma 1 0
+ &cppi41dma 2 0 &cppi41dma 3 0
+ &cppi41dma 0 1 &cppi41dma 1 1
+ &cppi41dma 2 1 &cppi41dma 3 1>;
+ dma-names =
+ "rx1", "rx2", "rx3", "rx4",
+ "tx1", "tx2", "tx3", "tx4";
+
+ cppi41dma: dma-controller@201000 {
+ compatible = "ti,da8xx-cppi41";
+ reg = <0x201000 0x1000
+ 0x202000 0x1000
+ 0x204000 0x4000>;
+ reg-names = "glue", "controller",
+ "scheduler", "queuemgr";
+ interrupts = <58>;
+ interrupt-names = "glue";
+ #dma-cells = <2>;
+ #dma-channels = <4>;
+ #dma-requests = <256>;
+ status = "okay";
+ };
};
mdio: mdio@224000 {
compatible = "ti,davinci_mdio";
--
2.10.2
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^ permalink raw reply related
* Re: [PATCH v2 3/3] can: ti_hecc: Add DT support for TI HECC module
From: Yegor Yefremov @ 2017-01-17 15:31 UTC (permalink / raw)
To: linux-can@vger.kernel.org
Cc: linux-omap@vger.kernel.org, devicetree, robh+dt, Andrey Skvortsov,
hs, Anton Glukhov, Yegor Yefremov, Marc Kleine-Budde
In-Reply-To: <CAGm1_kuZfrEKS+UVaP=A-LqA5Q7grZrd5iKAjXbqms42oiwEqQ@mail.gmail.com>
On Wed, Jan 11, 2017 at 3:24 PM, Yegor Yefremov
<yegorslists@googlemail.com> wrote:
> On Wed, Jan 11, 2017 at 3:05 PM, <yegorslists@googlemail.com> wrote:
>> From: Anton Glukhov <anton.a.glukhov@gmail.com>
>>
>> These patch set adds device tree support for TI HECC module.
>>
>> Signed-off-by: Anton Glukhov <anton.a.glukhov@gmail.com>
>> Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
>> ---
>> Changes v1 -> v2:
>> - change compatible to "ti,am3505"
>> - remove CONFIG_OF
>> - don't set int_line to 0 explicitly
>>
>> drivers/net/can/ti_hecc.c | 54 +++++++++++++++++++++++++++++++++++++++++++----
>> 1 file changed, 50 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/net/can/ti_hecc.c b/drivers/net/can/ti_hecc.c
>> index 680d1ff..fd3d9fc 100644
>> --- a/drivers/net/can/ti_hecc.c
>> +++ b/drivers/net/can/ti_hecc.c
>> @@ -46,6 +46,8 @@
>> #include <linux/platform_device.h>
>> #include <linux/clk.h>
>> #include <linux/io.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>>
>> #include <linux/can/dev.h>
>> #include <linux/can/error.h>
>> @@ -872,19 +874,62 @@ static const struct net_device_ops ti_hecc_netdev_ops = {
>> .ndo_change_mtu = can_change_mtu,
>> };
>>
>> +static const struct of_device_id ti_hecc_dt_ids[] = {
>> + {
>> + .compatible = "ti,am3505",
>> + },
>> + { }
>> +};
>> +MODULE_DEVICE_TABLE(of, ti_hecc_dt_ids);
>> +
>> +static struct ti_hecc_platform_data *hecc_parse_dt(struct device *dev)
>> +{
>> + struct ti_hecc_platform_data *pdata;
>> + struct device_node *np = dev->of_node;
>> +
>> + pdata = devm_kzalloc(dev, sizeof(struct ti_hecc_platform_data), GFP_KERNEL);
>> + if (!pdata)
>> + return ERR_PTR(-ENOMEM);
>> +
>> + if (of_property_read_u32(np, "ti,scc-ram-offset", &pdata->scc_ram_offset)) {
>> + dev_err(dev, "Missing scc-ram-offset property in the DT.\n");
>> + return ERR_PTR(-EINVAL);
>> + }
>> +
>> + if (of_property_read_u32(np, "ti,hecc-ram-offset", &pdata->hecc_ram_offset)) {
>> + dev_err(dev, "Missing hecc-ram-offset property in the DT.\n");
>> + return ERR_PTR(-EINVAL);
>> + }
>> +
>> + if (of_property_read_u32(np, "ti,mbx-offset", &pdata->mbx_offset)) {
>> + dev_err(dev, "Missing mbx-offset property in the DT.\n");
>> + return ERR_PTR(-EINVAL);
>> + }
>> +
>> + of_property_read_u32(dev->of_node, "ti,int-line", &pdata->int_line);
>> +
>> + return pdata;
>> +}
>> +
>> static int ti_hecc_probe(struct platform_device *pdev)
>> {
>> struct net_device *ndev = (struct net_device *)0;
>> struct ti_hecc_priv *priv;
>> - struct ti_hecc_platform_data *pdata;
>> + struct ti_hecc_platform_data *pdata = dev_get_platdata(&pdev->dev);
>> + struct device_node *np = pdev->dev.of_node;
>> struct resource *mem, *irq;
>> void __iomem *addr;
>> int err = -ENODEV;
>>
>> - pdata = dev_get_platdata(&pdev->dev);
>> + if (!pdata && np) {
>> + pdata = hecc_parse_dt(&pdev->dev);
>> + if (IS_ERR(pdata))
>> + return PTR_ERR(pdata);
>> + }
>> +
>> if (!pdata) {
>> - dev_err(&pdev->dev, "No platform data\n");
>> - goto probe_exit;
>> + dev_err(&pdev->dev, "Platform data missing\n");
>> + return -EINVAL;
>> }
>>
>> mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> @@ -1037,6 +1082,7 @@ static int ti_hecc_resume(struct platform_device *pdev)
>> static struct platform_driver ti_hecc_driver = {
>> .driver = {
>> .name = DRV_NAME,
>> + .of_match_table = ti_hecc_dt_ids,
>> },
>> .probe = ti_hecc_probe,
>> .remove = ti_hecc_remove,
>> --
>> 2.1.4
>>
>
> So far the CAN interface will be registered, but I get following issue
> with clock for HECC:
>
> [ 6.574174] CAN device driver interface
> [ 6.663318] ------------[ cut here ]------------
> [ 6.668220] WARNING: CPU: 0 PID: 115 at drivers/clk/clk.c:652
> clk_core_enable+0xdc/0x268
> [ 6.676676] Modules linked in: ti_hecc(+) can_dev
> snd_soc_omap_mcbsp omap_wdt snd_soc_omap snd_soc_tlv320aic23_i2c
> snd_soc_tlv320aic23 snd_soc_core ehci_omap snd_pcm_dmaengine snd_pcm
> ehci_hcd snd_timer snd at24 soundcore nvmem_core gpio_pca953x usbcore
> [ 6.700227] CPU: 0 PID: 115 Comm: udevd Not tainted 4.10.0-rc3 #2
> [ 6.706595] Hardware name: Generic AM3517 (Flattened Device Tree)
> [ 6.713000] [<c010fff8>] (unwind_backtrace) from [<c010c178>]
> (show_stack+0x10/0x14)
> [ 6.721108] [<c010c178>] (show_stack) from [<c0518fcc>]
> (dump_stack+0xac/0xe0)
> [ 6.728682] [<c0518fcc>] (dump_stack) from [<c0136d60>] (__warn+0xd8/0x104)
> [ 6.735973] [<c0136d60>] (__warn) from [<c0136e38>]
> (warn_slowpath_null+0x20/0x28)
> [ 6.743898] [<c0136e38>] (warn_slowpath_null) from [<c0595530>]
> (clk_core_enable+0xdc/0x268)
> [ 6.752730] [<c0595530>] (clk_core_enable) from [<c05966d0>]
> (clk_core_enable_lock+0x18/0x2c)
> [ 6.761670] [<c05966d0>] (clk_core_enable_lock) from [<bf17202c>]
> (ti_hecc_probe+0x188/0x3d0 [ti_hecc])
> [ 6.771616] [<bf17202c>] (ti_hecc_probe [ti_hecc]) from
> [<c05f5930>] (platform_drv_probe+0x50/0xb0)
> [ 6.781095] [<c05f5930>] (platform_drv_probe) from [<c05f3998>]
> (driver_probe_device+0x1f8/0x2cc)
> [ 6.790379] [<c05f3998>] (driver_probe_device) from [<c05f3b2c>]
> (__driver_attach+0xc0/0xc4)
> [ 6.799208] [<c05f3b2c>] (__driver_attach) from [<c05f1e3c>]
> (bus_for_each_dev+0x6c/0xa0)
> [ 6.807763] [<c05f1e3c>] (bus_for_each_dev) from [<c05f2ef8>]
> (bus_add_driver+0x100/0x210)
> [ 6.816410] [<c05f2ef8>] (bus_add_driver) from [<c05f4968>]
> (driver_register+0x78/0xf4)
> [ 6.824785] [<c05f4968>] (driver_register) from [<c0101874>]
> (do_one_initcall+0x3c/0x170)
> [ 6.833342] [<c0101874>] (do_one_initcall) from [<c023b4c8>]
> (do_init_module+0x5c/0x1b8)
> [ 6.841818] [<c023b4c8>] (do_init_module) from [<c01d9a08>]
> (load_module+0x1d2c/0x23f8)
> [ 6.850194] [<c01d9a08>] (load_module) from [<c01da2f0>]
> (SyS_finit_module+0xa4/0xb8)
> [ 6.858392] [<c01da2f0>] (SyS_finit_module) from [<c0107760>]
> (ret_fast_syscall+0x0/0x1c)
> [ 6.866939] ---[ end trace b502c707901327dc ]---
> [ 6.875799] ti_hecc 5c050000.can: device registered
> (reg_base=d0b1c000, irq=40)
>
> Going to take a closer look at this.
I've fixed this issue. One needs to use clk_prepare_enable() instead
of clk_enable().
Can it be, that earlier all OMAP clocks were "prepared", so that one
could begin with clk_enable() right away?
Will make a separate patch.
Yegor
^ permalink raw reply
* [PATCH v9 5/5] ARM: configs: stm32: Add I2C support for STM32 defconfig
From: M'boumba Cedric Madianga @ 2017-01-17 15:27 UTC (permalink / raw)
To: wsa, robh+dt, mcoquelin.stm32, alexandre.torgue, linus.walleij,
patrice.chotard, linux, linux-i2c, devicetree, linux-arm-kernel,
linux-kernel, u.kleine-koenig
Cc: M'boumba Cedric Madianga
In-Reply-To: <1484666821-20551-1-git-send-email-cedric.madianga@gmail.com>
This patch adds I2C support for STM32 default configuration
Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
---
arch/arm/configs/stm32_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 5a72d69..323d2a3 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -47,6 +47,9 @@ CONFIG_SERIAL_NONSTANDARD=y
CONFIG_SERIAL_STM32=y
CONFIG_SERIAL_STM32_CONSOLE=y
# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_STM32F4=y
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_NEW_LEDS=y
--
1.9.1
^ permalink raw reply related
* [PATCH v9 4/5] ARM: dts: stm32: Add I2C1 support for STM32429 eval board
From: M'boumba Cedric Madianga @ 2017-01-17 15:27 UTC (permalink / raw)
To: wsa, robh+dt, mcoquelin.stm32, alexandre.torgue, linus.walleij,
patrice.chotard, linux, linux-i2c, devicetree, linux-arm-kernel,
linux-kernel, u.kleine-koenig
Cc: M'boumba Cedric Madianga
In-Reply-To: <1484666821-20551-1-git-send-email-cedric.madianga@gmail.com>
This patch adds I2C1 instance support for STM32x9I-Eval board.
Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
---
arch/arm/boot/dts/stm32429i-eval.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 76f7206..c943539 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -146,3 +146,9 @@
pinctrl-names = "default";
status = "okay";
};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins_b>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--
1.9.1
^ permalink raw reply related
* [PATCH v9 3/5] ARM: dts: stm32: Add I2C1 support for STM32F429 SoC
From: M'boumba Cedric Madianga @ 2017-01-17 15:26 UTC (permalink / raw)
To: wsa, robh+dt, mcoquelin.stm32, alexandre.torgue, linus.walleij,
patrice.chotard, linux, linux-i2c, devicetree, linux-arm-kernel,
linux-kernel, u.kleine-koenig
Cc: M'boumba Cedric Madianga
In-Reply-To: <1484666821-20551-1-git-send-email-cedric.madianga@gmail.com>
This patch adds I2C1 support for STM32F429 SoC
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index e4dae0e..5b063e9 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -48,6 +48,7 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
+#include <dt-bindings/mfd/stm32f4-rcc.h>
/ {
clocks {
@@ -153,6 +154,18 @@
status = "disabled";
};
+ i2c1: i2c@40005400 {
+ compatible = "st,stm32f4-i2c";
+ reg = <0x40005400 0x400>;
+ interrupts = <31>,
+ <32>;
+ resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
usart7: serial@40007800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40007800 0x400>;
@@ -355,6 +368,16 @@
slew-rate = <2>;
};
};
+
+ i2c1_pins_b: i2c1@0 {
+ pins {
+ pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
+ <STM32F429_PB6_FUNC_I2C1_SCL>;
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <3>;
+ };
+ };
};
rcc: rcc@40023810 {
--
1.9.1
^ permalink raw reply related
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