* [PATCH 1/2] dt-bindings: arm, gic: Fix binding example for a virt-capable GIC
From: Marc Zyngier @ 2017-01-18 10:53 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: Mark Rutland, Heiko Stuebner, Tony Lindgren, arm, Magnus Damm,
Russell King, Krzysztof Kozlowski, Javier Martinez Canillas,
Chen-Yu Tsai, Kukjin Kim, Tsahee Zidenberg, Jason Cooper,
Simon Horman, Santosh Shilimkar, Matthias Brugger,
Thomas Gleixner, Sascha Hauer, Antoine Tenart, Rob Herring,
Benoît Cousson, Fabio Estevam, Maxime Ripard, Shawn Guo
In-Reply-To: <1484736811-24002-1-git-send-email-marc.zyngier@arm.com>
The joys of copy/paste: the example of a virtualization capable GIC
in the DT binding was wrong, and propagated to dozens of platforms.
Oh well. Let's fix the source of the crap before tackling individual
offenders.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
index 5393e2a..a3d51ed 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
@@ -107,11 +107,11 @@ Required properties:
Example:
interrupt-controller@2c001000 {
- compatible = "arm,cortex-a15-gic";
+ compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x2c001000 0x1000>,
- <0x2c002000 0x1000>,
+ <0x2c002000 0x2000>,
<0x2c004000 0x2000>,
<0x2c006000 0x2000>;
interrupts = <1 9 0xf04>;
--
2.1.4
^ permalink raw reply related
* [PATCH 2/2] ARM: DTS: Fix register map for virt-capable GIC
From: Marc Zyngier @ 2017-01-18 10:53 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: Thomas Gleixner, Jason Cooper, Rob Herring, Mark Rutland,
Tsahee Zidenberg, Antoine Tenart, Russell King,
Benoît Cousson, Tony Lindgren, Kukjin Kim,
Krzysztof Kozlowski, Javier Martinez Canillas, Shawn Guo,
Sascha Hauer, Fabio Estevam, Santosh Shilimkar, Matthias Brugger,
Simon Horman, Magnus Damm
In-Reply-To: <1484736811-24002-1-git-send-email-marc.zyngier@arm.com>
Since everybody copied my own mistake from the DT binding example,
let's address all the offenders in one swift go.
Most of them got the CPU interface size wrong (4kB, while it should
be 8kB), except for both keystone platforms which got the control
interface wrong (4kB instead of 8kB).
In the couple of cases were I knew for sure what implementation
was used, I've added the "arm,gic-400" compatible string. I'm 99%
sure that this is what everyong is using, but short of having the
TRM for all the other SoCs, I've let them alone.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm/boot/dts/alpine.dtsi | 2 +-
arch/arm/boot/dts/axm55xx.dtsi | 2 +-
arch/arm/boot/dts/dra7.dtsi | 2 +-
arch/arm/boot/dts/ecx-2000.dts | 2 +-
arch/arm/boot/dts/exynos3250.dtsi | 2 +-
arch/arm/boot/dts/exynos5.dtsi | 2 +-
arch/arm/boot/dts/exynos5260.dtsi | 2 +-
arch/arm/boot/dts/exynos5440.dtsi | 2 +-
arch/arm/boot/dts/imx6ul.dtsi | 4 ++--
arch/arm/boot/dts/keystone-k2g.dtsi | 2 +-
arch/arm/boot/dts/keystone.dtsi | 2 +-
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
arch/arm/boot/dts/mt2701.dtsi | 2 +-
arch/arm/boot/dts/mt6580.dtsi | 2 +-
arch/arm/boot/dts/mt6589.dtsi | 2 +-
arch/arm/boot/dts/mt7623.dtsi | 2 +-
arch/arm/boot/dts/mt8127.dtsi | 2 +-
arch/arm/boot/dts/mt8135.dtsi | 2 +-
arch/arm/boot/dts/omap5.dtsi | 2 +-
arch/arm/boot/dts/r8a73a4.dtsi | 2 +-
arch/arm/boot/dts/r8a7743.dtsi | 2 +-
arch/arm/boot/dts/r8a7745.dtsi | 2 +-
arch/arm/boot/dts/r8a7790.dtsi | 2 +-
arch/arm/boot/dts/r8a7791.dtsi | 2 +-
arch/arm/boot/dts/r8a7792.dtsi | 2 +-
arch/arm/boot/dts/r8a7793.dtsi | 2 +-
arch/arm/boot/dts/r8a7794.dtsi | 2 +-
arch/arm/boot/dts/rk1108.dtsi | 2 +-
arch/arm/boot/dts/rk3036.dtsi | 2 +-
arch/arm/boot/dts/rk322x.dtsi | 2 +-
arch/arm/boot/dts/rk3288.dtsi | 2 +-
arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
arch/arm/boot/dts/sun7i-a20.dtsi | 4 ++--
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
37 files changed, 40 insertions(+), 40 deletions(-)
diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
index db8752f..d0eefc3 100644
--- a/arch/arm/boot/dts/alpine.dtsi
+++ b/arch/arm/boot/dts/alpine.dtsi
@@ -93,7 +93,7 @@
interrupt-controller;
reg = <0x0 0xfb001000 0x0 0x1000>,
<0x0 0xfb002000 0x0 0x2000>,
- <0x0 0xfb004000 0x0 0x1000>,
+ <0x0 0xfb004000 0x0 0x2000>,
<0x0 0xfb006000 0x0 0x2000>;
interrupts =
<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi
index a9d6d59..47799f5 100644
--- a/arch/arm/boot/dts/axm55xx.dtsi
+++ b/arch/arm/boot/dts/axm55xx.dtsi
@@ -62,7 +62,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0x20 0x01001000 0 0x1000>,
- <0x20 0x01002000 0 0x1000>,
+ <0x20 0x01002000 0 0x2000>,
<0x20 0x01004000 0 0x2000>,
<0x20 0x01006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 1faf24a..a9ffa49 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -57,7 +57,7 @@
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x0 0x48211000 0x0 0x1000>,
- <0x0 0x48212000 0x0 0x1000>,
+ <0x0 0x48212000 0x0 0x2000>,
<0x0 0x48214000 0x0 0x2000>,
<0x0 0x48216000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
index 2ccbb57f..c15e7e0 100644
--- a/arch/arm/boot/dts/ecx-2000.dts
+++ b/arch/arm/boot/dts/ecx-2000.dts
@@ -99,7 +99,7 @@
interrupt-controller;
interrupts = <1 9 0xf04>;
reg = <0xfff11000 0x1000>,
- <0xfff12000 0x1000>,
+ <0xfff12000 0x2000>,
<0xfff14000 0x2000>,
<0xfff16000 0x2000>;
};
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index ba17ee1..9c28ef4 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -234,7 +234,7 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10481000 0x1000>,
- <0x10482000 0x1000>,
+ <0x10482000 0x2000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
interrupts = <GIC_PPI 9
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 7fd870e..678c08e 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -94,7 +94,7 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10481000 0x1000>,
- <0x10482000 0x1000>,
+ <0x10482000 0x2000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
interrupts = <GIC_PPI 9
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index 5818718..5e88c96 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -167,7 +167,7 @@
#size-cells = <0>;
interrupt-controller;
reg = <0x10481000 0x1000>,
- <0x10482000 0x1000>,
+ <0x10482000 0x2000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
interrupts = <GIC_PPI 9
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 2a2e570..77d35bb 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -40,7 +40,7 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x2E1000 0x1000>,
- <0x2E2000 0x1000>,
+ <0x2E2000 0x2000>,
<0x2E4000 0x2000>,
<0x2E6000 0x2000>;
interrupts = <GIC_PPI 9
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 39845a7..ac5371a 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -91,11 +91,11 @@
};
intc: interrupt-controller@00a01000 {
- compatible = "arm,cortex-a7-gic";
+ compatible = "arm,gic-400", "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
- <0x00a02000 0x1000>,
+ <0x00a02000 0x2000>,
<0x00a04000 0x2000>,
<0x00a06000 0x2000>;
};
diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
index 63c7cf0..07bf300 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -45,7 +45,7 @@
interrupt-controller;
reg = <0x0 0x02561000 0x0 0x1000>,
<0x0 0x02562000 0x0 0x2000>,
- <0x0 0x02564000 0x0 0x1000>,
+ <0x0 0x02564000 0x0 0x2000>,
<0x0 0x02566000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index 02708ba..aaff6816 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -35,7 +35,7 @@
interrupt-controller;
reg = <0x0 0x02561000 0x0 0x1000>,
<0x0 0x02562000 0x0 0x2000>,
- <0x0 0x02564000 0x0 0x1000>,
+ <0x0 0x02564000 0x0 0x2000>,
<0x0 0x02566000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 282d854..45ea57f 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -110,11 +110,11 @@
ranges;
gic: interrupt-controller@1400000 {
- compatible = "arm,cortex-a7-gic";
+ compatible = "arm,gic-400", "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x1401000 0x0 0x1000>,
- <0x0 0x1402000 0x0 0x1000>,
+ <0x0 0x1402000 0x0 0x2000>,
<0x0 0x1404000 0x0 0x2000>,
<0x0 0x1406000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 7eab6f4..454d099 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -170,7 +170,7 @@
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10211000 0 0x1000>,
- <0 0x10212000 0 0x1000>,
+ <0 0x10212000 0 0x2000>,
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi
index 06fdf6c..a349dba 100644
--- a/arch/arm/boot/dts/mt6580.dtsi
+++ b/arch/arm/boot/dts/mt6580.dtsi
@@ -91,7 +91,7 @@
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0x10211000 0x1000>,
- <0x10212000 0x1000>,
+ <0x10212000 0x2000>,
<0x10214000 0x2000>,
<0x10216000 0x2000>;
};
diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
index 88b3cb1..0d6f60a 100644
--- a/arch/arm/boot/dts/mt6589.dtsi
+++ b/arch/arm/boot/dts/mt6589.dtsi
@@ -102,7 +102,7 @@
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0x10211000 0x1000>,
- <0x10212000 0x1000>,
+ <0x10212000 0x2000>,
<0x10214000 0x2000>,
<0x10216000 0x2000>;
};
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index fd2b614..19a54a3 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -104,7 +104,7 @@
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10211000 0 0x1000>,
- <0 0x10212000 0 0x1000>,
+ <0 0x10212000 0 0x2000>,
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
index 52086c8..916c095 100644
--- a/arch/arm/boot/dts/mt8127.dtsi
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -129,7 +129,7 @@
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10211000 0 0x1000>,
- <0 0x10212000 0 0x1000>,
+ <0 0x10212000 0 0x2000>,
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 1d7f92b..a97b4ee 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -221,7 +221,7 @@
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10211000 0 0x1000>,
- <0 0x10212000 0 0x1000>,
+ <0 0x10212000 0 0x2000>,
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 7cd92ba..71b4809 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -92,7 +92,7 @@
interrupt-controller;
#interrupt-cells = <3>;
reg = <0 0x48211000 0 0x1000>,
- <0 0x48212000 0 0x1000>,
+ <0 0x48212000 0 0x2000>,
<0 0x48214000 0 0x2000>,
<0 0x48216000 0 0x2000>;
interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 53183ff..14a66ca 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -465,7 +465,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 216cb1f..172a944 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -55,7 +55,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 0b2e2f3..7390ec0 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -55,7 +55,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 0c8900d..ac38764 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -183,7 +183,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 8721466..28039db 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -114,7 +114,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 6ced3c1..1ed5c88 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -88,7 +88,7 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 2fb527c..934c097 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -105,7 +105,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index fb576db..09f7823 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -71,7 +71,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi
index d770023..d6194bf 100644
--- a/arch/arm/boot/dts/rk1108.dtsi
+++ b/arch/arm/boot/dts/rk1108.dtsi
@@ -215,7 +215,7 @@
#address-cells = <0>;
reg = <0x32011000 0x1000>,
- <0x32012000 0x1000>,
+ <0x32012000 0x2000>,
<0x32014000 0x2000>,
<0x32016000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 4ed49a2..ff9b90b 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -189,7 +189,7 @@
#address-cells = <0>;
reg = <0x10139000 0x1000>,
- <0x1013a000 0x1000>,
+ <0x1013a000 0x2000>,
<0x1013c000 0x2000>,
<0x1013e000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 9d3aee5..9dff822 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -443,7 +443,7 @@
#address-cells = <0>;
reg = <0x32011000 0x1000>,
- <0x32012000 0x1000>,
+ <0x32012000 0x2000>,
<0x32014000 0x2000>,
<0x32016000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 4fad133..af46cba 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1110,7 +1110,7 @@
#address-cells = <0>;
reg = <0xffc01000 0x1000>,
- <0xffc02000 0x1000>,
+ <0xffc02000 0x2000>,
<0xffc04000 0x2000>,
<0xffc06000 0x2000>;
interrupts = <GIC_PPI 9 0xf04>;
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 2b26175..6ed505a 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -861,7 +861,7 @@
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
+ <0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index f7db067..3c24832 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -1686,9 +1686,9 @@
};
gic: interrupt-controller@01c81000 {
- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
+ <0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index e4991a7..49dfe86 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -489,7 +489,7 @@
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
+ <0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index d3473f8..04c3fdd 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -217,7 +217,7 @@
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
+ <0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 6c14a6f..292abd0 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -580,7 +580,7 @@
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
+ <0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 979ad1a..b7b5831 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -613,7 +613,7 @@
gic: interrupt-controller@01c41000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c41000 0x1000>,
- <0x01c42000 0x1000>,
+ <0x01c42000 0x2000>,
<0x01c44000 0x2000>,
<0x01c46000 0x2000>;
interrupt-controller;
--
2.1.4
^ permalink raw reply related
* Re: [PATCH v4] ARM64: dts: meson-gx: Add reserved memory zone and usable memory range
From: Neil Armstrong @ 2017-01-18 10:57 UTC (permalink / raw)
To: Andreas Färber, Kevin Hilman
Cc: devicetree@vger.kernel.org, xypron.glpk,
linux-kernel@vger.kernel.org, Carlo Caione, Olof Johansson,
linux-amlogic, linux-arm-kernel@lists.infradead.org
In-Reply-To: <04113569-e342-77ff-f79a-2c9c4dc4c602@suse.de>
On 01/18/2017 01:00 AM, Andreas Färber wrote:
> Hi Neil,
>
> Am 17.01.2017 um 09:21 schrieb Neil Armstrong:
>> As I finally understand, the real issue here is the usage of the "linux,useable-memory" property that
>> overrides the reg property that is changed by the bootloader to provide the "real" memory size.
>
> Yes, exactly. It assured that 0..0x01000000 was always unavailable, as
> intended, but at the same time it ignored any lowered or heightened
> upper limit coming from the bootloader side.
>
> As a rule of thumb, any nodes that have device_type set can be expected
> to be modified during boot.
>
>> As I understand the mainline U-Boot does it right, and it's a good news, and it seems uEFI need to provide
>> some specialized memory range aswell, but the vendor U-Boot versions only provide the full memory range here.
>> It seems obvious that whatever range is provided by u-boot, the first 16MiB should be reserved.
>>
>> The stress-ng package provides this "stress" command and is used to force the kernel to map more memory
>> zones,
>
> Thanks, its binary is called stress-ng in openSUSE Tumbleweed. ;)
>
>> but I also got the issue while running a fully fledged Desktop Environment thanks to the
>> recently merged DRM driver.
>
> I'll happily test once HDMI is ready. :)
>
>> You may not be able to trigger the issue since it seems Amlogic reduces this reserved size on GXL/GXM :
>> https://github.com/khadas/linux/commit/698df2c6cfbb0d1a9359743208e83517b31da6ce
>> But it should be confirmed.
>
> Confirming no issues on three runs on meson-gxm-rbox-pro:
>
> boxer:~ # stress-ng --vm 4 --vm-bytes 128M --timeout 10s &
> [1] 2528
> boxer:~ # stress-ng: info: [2528] dispatching hogs: 4 vm
> stress-ng: info: [2528] cache allocate: default cache size: 256K
> stress-ng: info: [2528] successful run completed in 10.07s
>
> [1]+ Done stress-ng --vm 4 --vm-bytes 128M --timeout 10s
> boxer:~ # stress-ng --vm 4 --vm-bytes 128M --timeout 10s
> stress-ng: info: [2537] dispatching hogs: 4 vm
> stress-ng: info: [2537] cache allocate: default cache size: 256K
> stress-ng: info: [2537] successful run completed in 10.07s
> boxer:~ # stress-ng --vm 4 --vm-bytes 128M --timeout 10s
> stress-ng: info: [2546] dispatching hogs: 4 vm
> stress-ng: info: [2546] cache allocate: default cache size: 256K
> stress-ng: info: [2546] successful run completed in 10.07s
> boxer:~ #
For 2 GiB boards, you may need to increase the vm threads :
# stress-ng --vm 16 --vm-bytes 128M --timeout 10s
stress-ng: info: [1292] dispatching hogs: 16 vm
stress-ng: info: [1292] cache allocate: default cache size: 512K
stress: info: [1275] dispatching hogs: 0 cpu, 0 io, 16 vm, 0 hdd
[ 948.832694] Bad mode in Error handler detected on CPU1, code 0xbf000000 -- SError
[ 948.832812] Bad mode in Error handler detected on CPU3, code 0xbf000000 -- SError
[ 948.832832] CPU: 3 PID: 1279 Comm: stress Not tainted 4.10.0-rc4-00004-gba7e7b8 #14
...
On a Wetek Play2 board with 2GiB.
>
>> Kevin asked me initially to handle this "start of ddr" reserved zone via a reserved-memory entry, but
>> at that time it seemed a better idea to use "linux,useable-memory", but I recon it may be an error.
>>
>> I will push a v5 with a supplementary reserved-memory entry and will postpone the boards memory size
>> fixup for a future DTS cleanup.
>>
>> Andreas, is this ok for you ?
>
> Yes, sounds fine to me, thanks. I'll note a few more nits to consider.
>
> Kevin, I noticed that this supposedly applied patch did not show up in
> linux-next for testing - could you merge your fixes branch into for-next
> please for those of us working on new stuff?
>
>> This issue exists since forever on mainline linux, and even 4.9 has it.
>> Olof, How could a similar fix go in 4.9 stable ?
>
> I guess it would then be best to consider splitting this patch up per
> board/SoC so that you can set appropriate Fixes: headers indicating how
> far back each one needs to be fixed.
>
> Regards,
> Andreas
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v4] ARM64: dts: meson-gx: Add reserved memory zone and usable memory range
From: Neil Armstrong @ 2017-01-18 10:58 UTC (permalink / raw)
To: Andreas Färber
Cc: devicetree@vger.kernel.org, Kevin Hilman,
linux-kernel@vger.kernel.org, Olof Johansson, xypron.glpk,
Carlo Caione, linux-amlogic, linux-arm-kernel@lists.infradead.org
In-Reply-To: <6bba535f-42bc-3e4b-129b-adc39152cfeb@suse.de>
On 01/18/2017 01:27 AM, Andreas Färber wrote:
> Am 18.01.2017 um 01:00 schrieb Andreas Färber:
>> Am 17.01.2017 um 09:21 schrieb Neil Armstrong:
>>> The stress-ng package provides this "stress" command and is used to force the kernel to map more memory
>>> zones, but I also got the issue while running a fully fledged Desktop Environment thanks to the
>>> recently merged DRM driver.
>>> You may not be able to trigger the issue since it seems Amlogic reduces this reserved size on GXL/GXM :
>>> https://github.com/khadas/linux/commit/698df2c6cfbb0d1a9359743208e83517b31da6ce
>>> But it should be confirmed.
>>
>> Confirming no issues on three runs on meson-gxm-rbox-pro:
>>
>> boxer:~ # stress-ng --vm 4 --vm-bytes 128M --timeout 10s &
>> [1] 2528
>> boxer:~ # stress-ng: info: [2528] dispatching hogs: 4 vm
>> stress-ng: info: [2528] cache allocate: default cache size: 256K
>> stress-ng: info: [2528] successful run completed in 10.07s
>>
>> [1]+ Done stress-ng --vm 4 --vm-bytes 128M --timeout 10s
>> boxer:~ # stress-ng --vm 4 --vm-bytes 128M --timeout 10s
>> stress-ng: info: [2537] dispatching hogs: 4 vm
>> stress-ng: info: [2537] cache allocate: default cache size: 256K
>> stress-ng: info: [2537] successful run completed in 10.07s
>> boxer:~ # stress-ng --vm 4 --vm-bytes 128M --timeout 10s
>> stress-ng: info: [2546] dispatching hogs: 4 vm
>> stress-ng: info: [2546] cache allocate: default cache size: 256K
>> stress-ng: info: [2546] successful run completed in 10.07s
>> boxer:~ #
>
> Similar results on meson-gxbb-vega-s95-telos (except 512K cache size),
> with both mainline EFI and vendor U-Boot.
>
> I notice that I don't have CONFIG_DRM enabled - maybe related?
Yes, It may add more pressure on the memory allocation.
Neil
>
> Regards,
> Andreas
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH] i2c: core: helper function to detect slave mode
From: Andy Shevchenko @ 2017-01-18 10:59 UTC (permalink / raw)
To: Vladimir Zapolskiy, Luis Oliveira, Andy Shevchenko
Cc: Wolfram Sang, Rob Herring, Mark Rutland, Jarkko Nikula,
Mika Westerberg, linux-i2c, devicetree,
linux-kernel@vger.kernel.org, Ramiro.Oliveira, Joao Pinto,
CARLOS.PALMINHA
In-Reply-To: <f751ffbe-f9f8-c5bd-3b1a-2edd91152a78@mleia.com>
On Tue, 2017-01-17 at 01:14 +0200, Vladimir Zapolskiy wrote:
> review comments then, for example it is not obvious that on a platform
> with both CONFIG_ACPI and CONFIG_OF enabled there should be an
> exclusive
> selection of only one of two possible branches as in your code etc.
ACPI and DT approach differently to this property. Like I already said
to you check GPIO library where we have similarities.
--
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy
^ permalink raw reply
* Re: [PATCH v7 4/8] PWM: add PWM driver for STM32 plaftorm
From: Benjamin Gaignard @ 2017-01-18 11:15 UTC (permalink / raw)
To: Thierry Reding
Cc: Mark Rutland, devicetree, Lars-Peter Clausen, Alexandre Torgue,
Linux PWM List, linux-iio, Linus Walleij, Arnaud Pouliquen,
Linux Kernel Mailing List, robh+dt, linux-arm-kernel,
Peter Meerwald-Stadler, Hartmut Knaack, Gerald Baeza,
Fabrice Gasnier, Lee Jones, Linaro Kernel Mailman List,
Jonathan Cameron, Benjamin Gaignard
In-Reply-To: <20170118100817.GF18989@ulmo.ba.sec>
2017-01-18 11:08 GMT+01:00 Thierry Reding <thierry.reding@gmail.com>:
> On Thu, Jan 05, 2017 at 10:25:40AM +0100, Benjamin Gaignard wrote:
>> This driver adds support for PWM driver on STM32 platform.
>> The SoC have multiple instances of the hardware IP and each
>> of them could have small differences: number of channels,
>> complementary output, auto reload register size...
>>
>> version 6:
>> - change st,breakinput parameter to make it usuable for stm32f7 too.
>>
>> version 4:
>> - detect at probe time hardware capabilities
>> - fix comments done on v2 and v3
>> - use PWM atomic ops
>>
>> version 2:
>> - only keep one comptatible
>> - use DT parameters to discover hardware block configuration
>>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>> ---
>> drivers/pwm/Kconfig | 9 +
>> drivers/pwm/Makefile | 1 +
>> drivers/pwm/pwm-stm32.c | 434 ++++++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 444 insertions(+)
>> create mode 100644 drivers/pwm/pwm-stm32.c
>>
>> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
>> index f92dd41..88035c0 100644
>> --- a/drivers/pwm/Kconfig
>> +++ b/drivers/pwm/Kconfig
>> @@ -397,6 +397,15 @@ config PWM_STI
>> To compile this driver as a module, choose M here: the module
>> will be called pwm-sti.
>>
>> +config PWM_STM32
>> + tristate "STMicroelectronics STM32 PWM"
>> + depends on (ARCH_STM32 && OF && MFD_STM32_TIMERS) || COMPILE_TEST
>> + help
>> + Generic PWM framework driver for STM32 SoCs.
>> +
>> + To compile this driver as a module, choose M here: the module
>> + will be called pwm-stm32.
>> +
>> config PWM_STMPE
>> bool "STMPE expander PWM export"
>> depends on MFD_STMPE
>> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
>> index a48bdb5..346a83b 100644
>> --- a/drivers/pwm/Makefile
>> +++ b/drivers/pwm/Makefile
>> @@ -38,6 +38,7 @@ obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
>> obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
>> obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
>> obj-$(CONFIG_PWM_STI) += pwm-sti.o
>> +obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
>> obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o
>> obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o
>> obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o
>> diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c
>> new file mode 100644
>> index 0000000..fcf0a78
>> --- /dev/null
>> +++ b/drivers/pwm/pwm-stm32.c
>> @@ -0,0 +1,434 @@
>> +/*
>> + * Copyright (C) STMicroelectronics 2016
>> + *
>> + * Author: Gerald Baeza <gerald.baeza@st.com>
>> + *
>> + * License terms: GNU General Public License (GPL), version 2
>> + *
>> + * Inspired by timer-stm32.c from Maxime Coquelin
>> + * pwm-atmel.c from Bo Shen
>> + */
>> +
>> +#include <linux/mfd/stm32-timers.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pwm.h>
>> +#include <linux/of.h>
>
> Can you please sort these alphabetically?
sure
>
>> +
>> +#define CCMR_CHANNEL_SHIFT 8
>> +#define CCMR_CHANNEL_MASK 0xFF
>> +#define MAX_BREAKINPUT 2
>
> Okay, this answers my question regarding the st,breakinput property. I
> still think it'd be good to have this in the binding documentation just
> to avoid having to look at implementation to find out.
>
>> +
>> +struct stm32_pwm {
>> + struct pwm_chip chip;
>> + struct device *dev;
>> + struct clk *clk;
>> + struct regmap *regmap;
>> + unsigned int caps;
>
> This seems completely unused?
Yes I will remove it
>
>> + unsigned int npwm;
>
> It's somewhat redundant to have this here, since the same information is
> already contained in struct pwm_chip.npwm.
>
> Since you use this primarily for detection, how about you make the
> stm32_pwm_detect_channels() function return the value and store it in a
> local variable in ->probe()? That might be useful also because you
> need to check the return value of regmap_update_bits() which technically
> could fail.
>
I will remove npwm field and put the result of stm32_pwm_detect_channels()
directly on chip.npwm.
regmap functions could failed (even if I haven't experiment that case)
but testing all
return make the code unreadable so I have decide to not test it....
>> + u32 max_arr;
>> + bool have_complementary_output;
>> +};
>> +
>> +struct stm32_breakinput {
>> + u32 index;
>> + u32 level;
>> + u32 filter;
>> +};
>> +
>> +static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
>> +{
>> + return container_of(chip, struct stm32_pwm, chip);
>> +}
>> +
>> +static u32 active_channels(struct stm32_pwm *dev)
>> +{
>> + u32 ccer;
>> +
>> + regmap_read(dev->regmap, TIM_CCER, &ccer);
>> +
>> + return ccer & TIM_CCER_CCXE;
>> +}
>
> This looks like something that you could track in software, but this is
> probably fine, too. Again, technically regmap_read() could fail, so you
> might want to consider adding some code to handle it. In practice it
> probably won't, so maybe you don't.
TIM_CCER_CCXE is a value that IIO timer can also read (not write) so
I have keep the same logic for pwm driver.
>
>> +
>> +static int write_ccrx(struct stm32_pwm *dev, struct pwm_device *pwm,
>> + u32 value)
>> +{
>> + switch (pwm->hwpwm) {
>> + case 0:
>> + return regmap_write(dev->regmap, TIM_CCR1, value);
>> + case 1:
>> + return regmap_write(dev->regmap, TIM_CCR2, value);
>> + case 2:
>> + return regmap_write(dev->regmap, TIM_CCR3, value);
>> + case 3:
>> + return regmap_write(dev->regmap, TIM_CCR4, value);
>> + }
>> + return -EINVAL;
>> +}
>> +
>> +static int stm32_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
>> + int duty_ns, int period_ns)
>> +{
>> + struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
>> + unsigned long long prd, div, dty;
>> + unsigned int prescaler = 0;
>> + u32 ccmr, mask, shift;
>> +
>> + /* Period and prescaler values depends on clock rate */
>> + div = (unsigned long long)clk_get_rate(priv->clk) * period_ns;
>> +
>> + do_div(div, NSEC_PER_SEC);
>> + prd = div;
>> +
>> + while (div > priv->max_arr) {
>> + prescaler++;
>> + div = prd;
>> + do_div(div, (prescaler + 1));
>
> Nit: there's no need for the parentheses here.
okay
>> + }
>> +
>> + prd = div;
>> +
>> + if (prescaler > MAX_TIM_PSC) {
>> + dev_err(chip->dev, "prescaler exceeds the maximum value\n");
>> + return -EINVAL;
>> + }
>> +
>> + /*
>> + * All channels share the same prescaler and counter so when two
>> + * channels are active at the same we can't change them
>
> Nit: "at the same time"?
okay
>
>> + */
>> + if (active_channels(priv) & ~(1 << pwm->hwpwm * 4)) {
>> + u32 psc, arr;
>> +
>> + regmap_read(priv->regmap, TIM_PSC, &psc);
>> + regmap_read(priv->regmap, TIM_ARR, &arr);
>> +
>> + if ((psc != prescaler) || (arr != prd - 1))
>> + return -EBUSY;
>> + }
>> +
>> + regmap_write(priv->regmap, TIM_PSC, prescaler);
>> + regmap_write(priv->regmap, TIM_ARR, prd - 1);
>> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
>> +
>> + /* Calculate the duty cycles */
>> + dty = prd * duty_ns;
>> + do_div(dty, period_ns);
>> +
>> + write_ccrx(priv, pwm, dty);
>> +
>> + /* Configure output mode */
>> + shift = (pwm->hwpwm & 0x1) * CCMR_CHANNEL_SHIFT;
>> + ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
>> + mask = CCMR_CHANNEL_MASK << shift;
>> +
>> + if (pwm->hwpwm < 2)
>> + regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
>> + else
>> + regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
>> +
>> + regmap_update_bits(priv->regmap, TIM_BDTR,
>> + TIM_BDTR_MOE | TIM_BDTR_AOE,
>> + TIM_BDTR_MOE | TIM_BDTR_AOE);
>> +
>> + return 0;
>> +}
>> +
>> +static int stm32_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
>> + enum pwm_polarity polarity)
>> +{
>> + u32 mask;
>> + struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
>> +
>> + mask = TIM_CCER_CC1P << (pwm->hwpwm * 4);
>> + if (priv->have_complementary_output)
>> + mask |= TIM_CCER_CC1NP << (pwm->hwpwm * 4);
>> +
>> + regmap_update_bits(priv->regmap, TIM_CCER, mask,
>> + polarity == PWM_POLARITY_NORMAL ? 0 : mask);
>> +
>> + return 0;
>> +}
>> +
>> +static int stm32_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
>> +{
>> + u32 mask;
>> + struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
>> +
>> + clk_enable(priv->clk);
>
> This can fail, so its return value should be checked. Also, I don't see
> a clk_prepare() anywhere. Is that something that maybe the MFD driver
> should be doing? It currently isn't.
I will check the return value.
You are right clk_prepare() is done in mfd driver when calling
devm_regmap_init_mmio_clk()
>
>> +
>> + /* Enable channel */
>> + mask = TIM_CCER_CC1E << (pwm->hwpwm * 4);
>> + if (priv->have_complementary_output)
>> + mask |= TIM_CCER_CC1NE << (pwm->hwpwm * 4);
>> +
>> + regmap_update_bits(priv->regmap, TIM_CCER, mask, mask);
>> +
>> + /* Make sure that registers are updated */
>> + regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
>> +
>> + /* Enable controller */
>> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
>> +
>> + return 0;
>> +}
>> +
>> +static void stm32_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
>> +{
>> + u32 mask;
>> + struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
>> +
>> + /* Disable channel */
>> + mask = TIM_CCER_CC1E << (pwm->hwpwm * 4);
>> + if (priv->have_complementary_output)
>> + mask |= TIM_CCER_CC1NE << (pwm->hwpwm * 4);
>> +
>> + regmap_update_bits(priv->regmap, TIM_CCER, mask, 0);
>> +
>> + /* When all channels are disabled, we can disable the controller */
>> + if (!active_channels(priv))
>> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
>> +
>> + clk_disable(priv->clk);
>> +}
>> +
>> +static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
>> + struct pwm_state *state)
>> +{
>> + struct pwm_state curstate;
>> + bool enabled;
>> + int ret;
>> +
>> + pwm_get_state(pwm, &curstate);
>> + enabled = curstate.enabled;
>
> There should be no need to do this in drivers. pwm_get_state() is for
> PWM API users. Drivers can directly dereference pwm->state.
ok
>
>> +
>> + if (enabled && !state->enabled) {
>> + stm32_pwm_disable(chip, pwm);
>> + return 0;
>> + }
>> +
>> + if (state->polarity != curstate.polarity && enabled)
>> + stm32_pwm_set_polarity(chip, pwm, state->polarity);
>
> So that's kind of a violation of atomic API semantics. The above means
> that if you have a PWM in the following state:
>
> enabled: no
> polarity: normal
>
> and want to set this:
>
> enabled: yes
> polarity: inversed
>
> then you will ignore the new polarity setting. What's the reason for
> "&& enabled) in the conditional above?
There is no reason, I will remove it.
>> +
>> + ret = stm32_pwm_config(chip, pwm, state->duty_cycle, state->period);
>> + if (ret)
>> + return ret;
>> +
>> + if (!enabled && state->enabled)
>> + ret = stm32_pwm_enable(chip, pwm);
>> +
>> + return ret;
>> +}
>
> Would it be possible to merge stm32_pwm_disable(), stm32_pwm_enable(),
> stm32_pwm_set_polarity() and stm32_pwm_config() into stm32_pwm_apply()?
> Part of the reason for the atomic API was to make it easier to write
> these drivers, but your implementation effectively copies what the
> transitional helpers do.
>
> It might not make a difference technically in your case, but I think
> it'd make the implementation more compact and set a better example for
> future reference.
hmm... it will create a fat function with lot of where
enabling/disabling/configuration
will be mixed I'm really not convince that will more compact and readable.
>
>> +
>> +static const struct pwm_ops stm32pwm_ops = {
>> + .owner = THIS_MODULE,
>> + .apply = stm32_pwm_apply,
>> +};
>> +
>> +static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
>> + int level, int filter)
>> +{
>> + u32 bdtr = TIM_BDTR_BKE;
>> +
>> + if (level)
>> + bdtr |= TIM_BDTR_BKP;
>> +
>> + bdtr |= (filter & TIM_BDTR_BKF_MASK) << TIM_BDTR_BKF_SHIFT;
>> +
>> + regmap_update_bits(priv->regmap,
>> + TIM_BDTR, TIM_BDTR_BKE | TIM_BDTR_BKP | TIM_BDTR_BKF,
>> + bdtr);
>> +
>> + regmap_read(priv->regmap, TIM_BDTR, &bdtr);
>> +
>> + return (bdtr & TIM_BDTR_BKE) ? 0 : -EINVAL;
>> +}
>> +
>> +static int stm32_pwm_set_breakinput2(struct stm32_pwm *priv,
>> + int level, int filter)
>> +{
>> + u32 bdtr = TIM_BDTR_BK2E;
>> +
>> + if (level)
>> + bdtr |= TIM_BDTR_BK2P;
>> +
>> + bdtr |= (filter & TIM_BDTR_BKF_MASK) << TIM_BDTR_BK2F_SHIFT;
>> +
>> + regmap_update_bits(priv->regmap,
>> + TIM_BDTR, TIM_BDTR_BK2E |
>> + TIM_BDTR_BK2P |
>> + TIM_BDTR_BK2F,
>> + bdtr);
>> +
>> + regmap_read(priv->regmap, TIM_BDTR, &bdtr);
>> +
>> + return (bdtr & TIM_BDTR_BK2E) ? 0 : -EINVAL;
>> +}
>
> As far as I can tell the only difference here is the various bit
> positions. Can you collapse the above two functions and add a new
> parameter to unify some code?
Yes it is all about bit shifting, I had try unify those two functions
with index has additional parameter
but it just add if() before each lines so no real benefit for code size.
>
>> +
>> +static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv,
>> + struct device_node *np)
>> +{
>> + struct stm32_breakinput breakinput[MAX_BREAKINPUT];
>> + int nb, ret, i, array_size;
>> +
>> + nb = of_property_count_elems_of_size(np, "st,breakinput",
>> + sizeof(struct stm32_breakinput));
>> +
>> + /*
>> + * Because "st,breakinput" parameter is optional do not make probe
>> + * failed if it doesn't exist.
>> + */
>> + if (nb <= 0)
>> + return 0;
>> +
>> + if (nb > MAX_BREAKINPUT)
>> + return -EINVAL;
>> +
>> + array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
>> + ret = of_property_read_u32_array(np, "st,breakinput",
>> + &breakinput[0].index, array_size);
>
> Maybe (u32 *)breakinput? That would make it more resilient against
> changes in ordering of fields in the struct. Granted, that's not likely
> to change, but I think it's a good idea in general to write code in a
> way that's safe in a more general case. That way if somebody ever were
> to copy from your code and then decide to reorder fields in their code
> things wouldn't fall apart.
Yes it is not suppose to change but I will use (u32 *)breakinput.
>> + if (ret)
>> + return ret;
>> +
>> + for (i = 0; i < nb && !ret; i++) {
>> + switch (breakinput[i].index) {
>> + case 0:
>> + {
>> + ret = stm32_pwm_set_breakinput(priv,
>> + breakinput[i].level,
>> + breakinput[i].filter);
>> + break;
>> + }
>
> Curly braces are unnecessary here.
removed
>
>> + case 1:
>> + {
>> + ret = stm32_pwm_set_breakinput2(priv,
>> + breakinput[i].level,
>> + breakinput[i].filter);
>> +
>> + break;
>> + }
>> + default:
>> + {
>> + ret = -EINVAL;
>> + break;
>> + }
>> + }
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
>> +{
>> + u32 ccer;
>> +
>> + /*
>> + * If complementary bit doesn't exist writing 1 will have no
>> + * effect so we can detect it.
>> + */
>> + regmap_update_bits(priv->regmap,
>> + TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE);
>> + regmap_read(priv->regmap, TIM_CCER, &ccer);
>> + regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0);
>
> This is strange: why are we disabling outputs here? Shouldn't the last
> line here undo the first instead?
Yes it should TIM_CCER_CC1NE not TIM_CCER_CCXE, I will fix it, thanks
>
>> +
>> + priv->have_complementary_output = (ccer != 0);
>> +}
>> +
>> +static void stm32_pwm_detect_channels(struct stm32_pwm *priv)
>> +{
>> + u32 ccer;
>> +
>> + /*
>> + * If channels enable bits don't exist writing 1 will have no
>> + * effect so we can detect and count them.
>> + */
>> + regmap_update_bits(priv->regmap,
>> + TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE);
>> + regmap_read(priv->regmap, TIM_CCER, &ccer);
>> + regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0);
>
> Does this have the potential to glitch? I suspect that the clock may not
> be on at this point and therefore no PWM outputs will be generated, but
> is that guaranteed to always be the case?
Set TIM_CCER_CCXE isn't enough to enable PWM generation, TIM_CR1_CEN
in TIM_CR1 register must also to set so no risk of glitch here
>
> Thierry
--
Benjamin Gaignard
Graphic Study Group
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
_______________________________________________
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^ permalink raw reply
* Re: [PATCH v7 4/8] PWM: add PWM driver for STM32 plaftorm
From: Benjamin Gaignard @ 2017-01-18 11:16 UTC (permalink / raw)
To: Thierry Reding
Cc: Mark Rutland, devicetree, Lars-Peter Clausen, Alexandre Torgue,
Linux PWM List, linux-iio, Linus Walleij, Arnaud Pouliquen,
Linux Kernel Mailing List, robh+dt, linux-arm-kernel,
Peter Meerwald-Stadler, Hartmut Knaack, Gerald Baeza,
Fabrice Gasnier, Lee Jones, Linaro Kernel Mailman List,
Jonathan Cameron, Benjamin Gaignard
In-Reply-To: <20170118101628.GG18989@ulmo.ba.sec>
2017-01-18 11:16 GMT+01:00 Thierry Reding <thierry.reding@gmail.com>:
> On Thu, Jan 05, 2017 at 10:25:40AM +0100, Benjamin Gaignard wrote:
> [...]
>> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
>> index f92dd41..88035c0 100644
>> --- a/drivers/pwm/Kconfig
>> +++ b/drivers/pwm/Kconfig
>> @@ -397,6 +397,15 @@ config PWM_STI
>> To compile this driver as a module, choose M here: the module
>> will be called pwm-sti.
>>
>> +config PWM_STM32
>> + tristate "STMicroelectronics STM32 PWM"
>> + depends on (ARCH_STM32 && OF && MFD_STM32_TIMERS) || COMPILE_TEST
>
> One other thing: is the dependency on ARCH_STM32 and OF necessary here?
> ARCH_STM32 and OF are both pulled in by MFD_STM32_TIMERS. The dependency
> is probably fine for MFD_STM32_TIMERS, though even there && OF seems too
> much, since it's already pulled in via ARCH_STM32 -> ARM_SINGLE_ARMV7M
> -> USE_OF.
Said like that MFD_STM32_TIMERS is enough so I will keep this one
Thanks
>
> Thierry
--
Benjamin Gaignard
Graphic Study Group
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 2/2] ARM: DTS: Fix register map for virt-capable GIC
From: Heiko Stübner @ 2017-01-18 11:25 UTC (permalink / raw)
To: Marc Zyngier
Cc: Mark Rutland, Tony Lindgren, arm, Magnus Damm, Russell King,
Krzysztof Kozlowski, Javier Martinez Canillas, Chen-Yu Tsai,
Kukjin Kim, Tsahee Zidenberg, devicetree, Jason Cooper,
Simon Horman, Santosh Shilimkar, Matthias Brugger,
Thomas Gleixner, Sascha Hauer, linux-arm-kernel, Antoine Tenart,
linux-kernel, Rob Herring, Benoît Cousson, Fabio Estevam
In-Reply-To: <1484736811-24002-3-git-send-email-marc.zyngier@arm.com>
Am Mittwoch, 18. Januar 2017, 10:53:31 CET schrieb Marc Zyngier:
> Since everybody copied my own mistake from the DT binding example,
> let's address all the offenders in one swift go.
>
> Most of them got the CPU interface size wrong (4kB, while it should
> be 8kB), except for both keystone platforms which got the control
> interface wrong (4kB instead of 8kB).
>
> In the couple of cases were I knew for sure what implementation
> was used, I've added the "arm,gic-400" compatible string. I'm 99%
> sure that this is what everyong is using, but short of having the
> TRM for all the other SoCs, I've let them alone.
>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
for the Rockchip parts
Acked-by: Heiko Stuebner <heiko@sntech.de>
> diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi
> index d770023..d6194bf 100644
> --- a/arch/arm/boot/dts/rk1108.dtsi
> +++ b/arch/arm/boot/dts/rk1108.dtsi
> @@ -215,7 +215,7 @@
> #address-cells = <0>;
>
> reg = <0x32011000 0x1000>,
> - <0x32012000 0x1000>,
> + <0x32012000 0x2000>,
> <0x32014000 0x2000>,
> <0x32016000 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_HIGH)>;
> diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
> index 4ed49a2..ff9b90b 100644
> --- a/arch/arm/boot/dts/rk3036.dtsi
> +++ b/arch/arm/boot/dts/rk3036.dtsi
> @@ -189,7 +189,7 @@
> #address-cells = <0>;
>
> reg = <0x10139000 0x1000>,
> - <0x1013a000 0x1000>,
> + <0x1013a000 0x2000>,
> <0x1013c000 0x2000>,
> <0x1013e000 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
> diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
> index 9d3aee5..9dff822 100644
> --- a/arch/arm/boot/dts/rk322x.dtsi
> +++ b/arch/arm/boot/dts/rk322x.dtsi
> @@ -443,7 +443,7 @@
> #address-cells = <0>;
>
> reg = <0x32011000 0x1000>,
> - <0x32012000 0x1000>,
> + <0x32012000 0x2000>,
> <0x32014000 0x2000>,
> <0x32016000 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index 4fad133..af46cba 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -1110,7 +1110,7 @@
> #address-cells = <0>;
>
> reg = <0xffc01000 0x1000>,
> - <0xffc02000 0x1000>,
> + <0xffc02000 0x2000>,
> <0xffc04000 0x2000>,
> <0xffc06000 0x2000>;
> interrupts = <GIC_PPI 9 0xf04>;
^ permalink raw reply
* Re: [PATCH 0/4] Bluetooth support for GXBB/GXL/GXM based devices
From: Martin Blumenstingl @ 2017-01-18 11:25 UTC (permalink / raw)
To: linux-serial, linux-amlogic, jslaby, gregkh, khilman, carlo
Cc: mark.rutland, devicetree, Martin Blumenstingl, catalin.marinas,
will.deacon, robh+dt, linux-arm-kernel
In-Reply-To: <20170115223255.10350-1-martin.blumenstingl@googlemail.com>
Kevin,
On Sun, Jan 15, 2017 at 11:32 PM, Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:
> This adds the missing kernel bits for Bluetooth support on the
> Tronsmart Vega S95 (GXBB based) boards as well as for the GXL
> P230/P231 and GXM Q200/Q201 reference boards.
>
> The Bluetooth functionality on these boards is provided by the
> SDIO wifi/Bluetooth combo-chip (Broadcom bcm43xx based). The
> Bluetooth module on that combo-chip has to be taken out of reset,
> which is taken care of the GPIO in the sdio_pwrseq.
>
> Once the module is taken out of reset it can be set up from userspace
> using the "hciattach" tool from bluez, which talks to the Bluetooth
> module which is connected to one of the serial ports (in our case
> uart_A). To get the Bluetooth module initialized within the timeout
> defined by "hciattach" (and to achieve usable speeds for Bluetooth
> transfers) the communication uses a speed of 2000000 baud, which was
> not supported by meson_uart before.
>
> NOTE: The .dts-changes from this series depends on my previous series
> "add support for uart_AO_B" - see [0]
>
>
> [0] http://lists.infradead.org/pipermail/linux-amlogic/2017-January/001982.html
>
>
> Martin Blumenstingl (4):
> tty: serial: meson: allow baud-rates higher than 115200
> ARM64: dts: meson-gx: add the serial CTS and RTS pin groups
Neil just informed me that Rob Herring is working on defining the UART
Bluetooth device properly using devicetree (preparation for this is
named "[PATCH v2 0/9] Serial slave device bus", see [0] for the
mailing-list conversation and [1] for a WiP git repo).
This means that there will be a better solution than the one proposed
in the meson-gx-p23x-q20x and meson-gxbb-vega-s95 patches (patches #1
and #2 are not affected by this), namely:
- I'm currently (ab)using sdio-pwrseq node to power on the UART
Bluetooth module, this can solved by specifying a bluetooth { } node
inside the &uart_A node in the future and providing the corresponding
GPIOs there
- all the userspace commands will not be necessary once
drivers/bluetooth/hci_bcm.c is changed to the serio framework and gets
devicetree support
> ARM64: dts: meson-gx-p23x-q20x: enable the Bluetooth module
> ARM64: dts: meson-gxbb-vega-s95: enable the Bluetooth module
>
> .../arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 12 ++++++-
> .../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 9 +++++
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 40 ++++++++++++++++++++++
> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 40 ++++++++++++++++++++++
> drivers/tty/serial/meson_uart.c | 2 +-
> 5 files changed, 101 insertions(+), 2 deletions(-)
>
> --
> 2.11.0
>
[0] http://marc.info/?l=linux-serial&m=148460728417109&w=2
[1] https://git.kernel.org/cgit/linux/kernel/git/robh/linux.git/log/?h=serial-bus-v3
^ permalink raw reply
* Re: [PATCH 2/2] ARM: DTS: Fix register map for virt-capable GIC
From: Matthias Brugger @ 2017-01-18 11:29 UTC (permalink / raw)
To: Marc Zyngier, linux-kernel, devicetree, linux-arm-kernel
Cc: Mark Rutland, Heiko Stuebner, Tony Lindgren, Magnus Damm,
Russell King, Krzysztof Kozlowski, Javier Martinez Canillas,
Chen-Yu Tsai, arm, Tsahee Zidenberg, Jason Cooper, Simon Horman,
Santosh Shilimkar, Thomas Gleixner, Sascha Hauer, Antoine Tenart,
Rob Herring, Kukjin Kim, Benoît Cousson, Fabio Estevam,
Maxime Ripard, Shawn Guo
In-Reply-To: <1484736811-24002-3-git-send-email-marc.zyngier@arm.com>
On 18/01/17 11:53, Marc Zyngier wrote:
> Since everybody copied my own mistake from the DT binding example,
> let's address all the offenders in one swift go.
>
> Most of them got the CPU interface size wrong (4kB, while it should
> be 8kB), except for both keystone platforms which got the control
> interface wrong (4kB instead of 8kB).
>
> In the couple of cases were I knew for sure what implementation
> was used, I've added the "arm,gic-400" compatible string. I'm 99%
> sure that this is what everyong is using, but short of having the
> TRM for all the other SoCs, I've let them alone.
>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
> arch/arm/boot/dts/alpine.dtsi | 2 +-
> arch/arm/boot/dts/axm55xx.dtsi | 2 +-
> arch/arm/boot/dts/dra7.dtsi | 2 +-
> arch/arm/boot/dts/ecx-2000.dts | 2 +-
> arch/arm/boot/dts/exynos3250.dtsi | 2 +-
> arch/arm/boot/dts/exynos5.dtsi | 2 +-
> arch/arm/boot/dts/exynos5260.dtsi | 2 +-
> arch/arm/boot/dts/exynos5440.dtsi | 2 +-
> arch/arm/boot/dts/imx6ul.dtsi | 4 ++--
> arch/arm/boot/dts/keystone-k2g.dtsi | 2 +-
> arch/arm/boot/dts/keystone.dtsi | 2 +-
> arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
> arch/arm/boot/dts/mt2701.dtsi | 2 +-
> arch/arm/boot/dts/mt6580.dtsi | 2 +-
> arch/arm/boot/dts/mt6589.dtsi | 2 +-
> arch/arm/boot/dts/mt7623.dtsi | 2 +-
> arch/arm/boot/dts/mt8127.dtsi | 2 +-
> arch/arm/boot/dts/mt8135.dtsi | 2 +-
for the Mediatek SoCs:
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
> arch/arm/boot/dts/omap5.dtsi | 2 +-
> arch/arm/boot/dts/r8a73a4.dtsi | 2 +-
> arch/arm/boot/dts/r8a7743.dtsi | 2 +-
> arch/arm/boot/dts/r8a7745.dtsi | 2 +-
> arch/arm/boot/dts/r8a7790.dtsi | 2 +-
> arch/arm/boot/dts/r8a7791.dtsi | 2 +-
> arch/arm/boot/dts/r8a7792.dtsi | 2 +-
> arch/arm/boot/dts/r8a7793.dtsi | 2 +-
> arch/arm/boot/dts/r8a7794.dtsi | 2 +-
> arch/arm/boot/dts/rk1108.dtsi | 2 +-
> arch/arm/boot/dts/rk3036.dtsi | 2 +-
> arch/arm/boot/dts/rk322x.dtsi | 2 +-
> arch/arm/boot/dts/rk3288.dtsi | 2 +-
> arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
> arch/arm/boot/dts/sun7i-a20.dtsi | 4 ++--
> arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
> arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
> arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
> arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
> 37 files changed, 40 insertions(+), 40 deletions(-)
>
> diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
> index db8752f..d0eefc3 100644
> --- a/arch/arm/boot/dts/alpine.dtsi
> +++ b/arch/arm/boot/dts/alpine.dtsi
> @@ -93,7 +93,7 @@
> interrupt-controller;
> reg = <0x0 0xfb001000 0x0 0x1000>,
> <0x0 0xfb002000 0x0 0x2000>,
> - <0x0 0xfb004000 0x0 0x1000>,
> + <0x0 0xfb004000 0x0 0x2000>,
> <0x0 0xfb006000 0x0 0x2000>;
> interrupts =
> <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi
> index a9d6d59..47799f5 100644
> --- a/arch/arm/boot/dts/axm55xx.dtsi
> +++ b/arch/arm/boot/dts/axm55xx.dtsi
> @@ -62,7 +62,7 @@
> #address-cells = <0>;
> interrupt-controller;
> reg = <0x20 0x01001000 0 0x1000>,
> - <0x20 0x01002000 0 0x1000>,
> + <0x20 0x01002000 0 0x2000>,
> <0x20 0x01004000 0 0x2000>,
> <0x20 0x01006000 0 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 1faf24a..a9ffa49 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -57,7 +57,7 @@
> interrupt-controller;
> #interrupt-cells = <3>;
> reg = <0x0 0x48211000 0x0 0x1000>,
> - <0x0 0x48212000 0x0 0x1000>,
> + <0x0 0x48212000 0x0 0x2000>,
> <0x0 0x48214000 0x0 0x2000>,
> <0x0 0x48216000 0x0 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
> index 2ccbb57f..c15e7e0 100644
> --- a/arch/arm/boot/dts/ecx-2000.dts
> +++ b/arch/arm/boot/dts/ecx-2000.dts
> @@ -99,7 +99,7 @@
> interrupt-controller;
> interrupts = <1 9 0xf04>;
> reg = <0xfff11000 0x1000>,
> - <0xfff12000 0x1000>,
> + <0xfff12000 0x2000>,
> <0xfff14000 0x2000>,
> <0xfff16000 0x2000>;
> };
> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
> index ba17ee1..9c28ef4 100644
> --- a/arch/arm/boot/dts/exynos3250.dtsi
> +++ b/arch/arm/boot/dts/exynos3250.dtsi
> @@ -234,7 +234,7 @@
> #interrupt-cells = <3>;
> interrupt-controller;
> reg = <0x10481000 0x1000>,
> - <0x10482000 0x1000>,
> + <0x10482000 0x2000>,
> <0x10484000 0x2000>,
> <0x10486000 0x2000>;
> interrupts = <GIC_PPI 9
> diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
> index 7fd870e..678c08e 100644
> --- a/arch/arm/boot/dts/exynos5.dtsi
> +++ b/arch/arm/boot/dts/exynos5.dtsi
> @@ -94,7 +94,7 @@
> #interrupt-cells = <3>;
> interrupt-controller;
> reg = <0x10481000 0x1000>,
> - <0x10482000 0x1000>,
> + <0x10482000 0x2000>,
> <0x10484000 0x2000>,
> <0x10486000 0x2000>;
> interrupts = <GIC_PPI 9
> diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
> index 5818718..5e88c96 100644
> --- a/arch/arm/boot/dts/exynos5260.dtsi
> +++ b/arch/arm/boot/dts/exynos5260.dtsi
> @@ -167,7 +167,7 @@
> #size-cells = <0>;
> interrupt-controller;
> reg = <0x10481000 0x1000>,
> - <0x10482000 0x1000>,
> + <0x10482000 0x2000>,
> <0x10484000 0x2000>,
> <0x10486000 0x2000>;
> interrupts = <GIC_PPI 9
> diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
> index 2a2e570..77d35bb 100644
> --- a/arch/arm/boot/dts/exynos5440.dtsi
> +++ b/arch/arm/boot/dts/exynos5440.dtsi
> @@ -40,7 +40,7 @@
> #interrupt-cells = <3>;
> interrupt-controller;
> reg = <0x2E1000 0x1000>,
> - <0x2E2000 0x1000>,
> + <0x2E2000 0x2000>,
> <0x2E4000 0x2000>,
> <0x2E6000 0x2000>;
> interrupts = <GIC_PPI 9
> diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
> index 39845a7..ac5371a 100644
> --- a/arch/arm/boot/dts/imx6ul.dtsi
> +++ b/arch/arm/boot/dts/imx6ul.dtsi
> @@ -91,11 +91,11 @@
> };
>
> intc: interrupt-controller@00a01000 {
> - compatible = "arm,cortex-a7-gic";
> + compatible = "arm,gic-400", "arm,cortex-a7-gic";
> #interrupt-cells = <3>;
> interrupt-controller;
> reg = <0x00a01000 0x1000>,
> - <0x00a02000 0x1000>,
> + <0x00a02000 0x2000>,
> <0x00a04000 0x2000>,
> <0x00a06000 0x2000>;
> };
> diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
> index 63c7cf0..07bf300 100644
> --- a/arch/arm/boot/dts/keystone-k2g.dtsi
> +++ b/arch/arm/boot/dts/keystone-k2g.dtsi
> @@ -45,7 +45,7 @@
> interrupt-controller;
> reg = <0x0 0x02561000 0x0 0x1000>,
> <0x0 0x02562000 0x0 0x2000>,
> - <0x0 0x02564000 0x0 0x1000>,
> + <0x0 0x02564000 0x0 0x2000>,
> <0x0 0x02566000 0x0 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>;
> diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
> index 02708ba..aaff6816 100644
> --- a/arch/arm/boot/dts/keystone.dtsi
> +++ b/arch/arm/boot/dts/keystone.dtsi
> @@ -35,7 +35,7 @@
> interrupt-controller;
> reg = <0x0 0x02561000 0x0 0x1000>,
> <0x0 0x02562000 0x0 0x2000>,
> - <0x0 0x02564000 0x0 0x1000>,
> + <0x0 0x02564000 0x0 0x2000>,
> <0x0 0x02566000 0x0 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>;
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index 282d854..45ea57f 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -110,11 +110,11 @@
> ranges;
>
> gic: interrupt-controller@1400000 {
> - compatible = "arm,cortex-a7-gic";
> + compatible = "arm,gic-400", "arm,cortex-a7-gic";
> #interrupt-cells = <3>;
> interrupt-controller;
> reg = <0x0 0x1401000 0x0 0x1000>,
> - <0x0 0x1402000 0x0 0x1000>,
> + <0x0 0x1402000 0x0 0x2000>,
> <0x0 0x1404000 0x0 0x2000>,
> <0x0 0x1406000 0x0 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 7eab6f4..454d099 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -170,7 +170,7 @@
> #interrupt-cells = <3>;
> interrupt-parent = <&gic>;
> reg = <0 0x10211000 0 0x1000>,
> - <0 0x10212000 0 0x1000>,
> + <0 0x10212000 0 0x2000>,
> <0 0x10214000 0 0x2000>,
> <0 0x10216000 0 0x2000>;
> };
> diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi
> index 06fdf6c..a349dba 100644
> --- a/arch/arm/boot/dts/mt6580.dtsi
> +++ b/arch/arm/boot/dts/mt6580.dtsi
> @@ -91,7 +91,7 @@
> #interrupt-cells = <3>;
> interrupt-parent = <&gic>;
> reg = <0x10211000 0x1000>,
> - <0x10212000 0x1000>,
> + <0x10212000 0x2000>,
> <0x10214000 0x2000>,
> <0x10216000 0x2000>;
> };
> diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
> index 88b3cb1..0d6f60a 100644
> --- a/arch/arm/boot/dts/mt6589.dtsi
> +++ b/arch/arm/boot/dts/mt6589.dtsi
> @@ -102,7 +102,7 @@
> #interrupt-cells = <3>;
> interrupt-parent = <&gic>;
> reg = <0x10211000 0x1000>,
> - <0x10212000 0x1000>,
> + <0x10212000 0x2000>,
> <0x10214000 0x2000>,
> <0x10216000 0x2000>;
> };
> diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
> index fd2b614..19a54a3 100644
> --- a/arch/arm/boot/dts/mt7623.dtsi
> +++ b/arch/arm/boot/dts/mt7623.dtsi
> @@ -104,7 +104,7 @@
> #interrupt-cells = <3>;
> interrupt-parent = <&gic>;
> reg = <0 0x10211000 0 0x1000>,
> - <0 0x10212000 0 0x1000>,
> + <0 0x10212000 0 0x2000>,
> <0 0x10214000 0 0x2000>,
> <0 0x10216000 0 0x2000>;
> };
> diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
> index 52086c8..916c095 100644
> --- a/arch/arm/boot/dts/mt8127.dtsi
> +++ b/arch/arm/boot/dts/mt8127.dtsi
> @@ -129,7 +129,7 @@
> #interrupt-cells = <3>;
> interrupt-parent = <&gic>;
> reg = <0 0x10211000 0 0x1000>,
> - <0 0x10212000 0 0x1000>,
> + <0 0x10212000 0 0x2000>,
> <0 0x10214000 0 0x2000>,
> <0 0x10216000 0 0x2000>;
> };
> diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
> index 1d7f92b..a97b4ee 100644
> --- a/arch/arm/boot/dts/mt8135.dtsi
> +++ b/arch/arm/boot/dts/mt8135.dtsi
> @@ -221,7 +221,7 @@
> #interrupt-cells = <3>;
> interrupt-parent = <&gic>;
> reg = <0 0x10211000 0 0x1000>,
> - <0 0x10212000 0 0x1000>,
> + <0 0x10212000 0 0x2000>,
> <0 0x10214000 0 0x2000>,
> <0 0x10216000 0 0x2000>;
> };
> diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
> index 7cd92ba..71b4809 100644
> --- a/arch/arm/boot/dts/omap5.dtsi
> +++ b/arch/arm/boot/dts/omap5.dtsi
> @@ -92,7 +92,7 @@
> interrupt-controller;
> #interrupt-cells = <3>;
> reg = <0 0x48211000 0 0x1000>,
> - <0 0x48212000 0 0x1000>,
> + <0 0x48212000 0 0x2000>,
> <0 0x48214000 0 0x2000>,
> <0 0x48216000 0 0x2000>;
> interrupt-parent = <&gic>;
> diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
> index 53183ff..14a66ca 100644
> --- a/arch/arm/boot/dts/r8a73a4.dtsi
> +++ b/arch/arm/boot/dts/r8a73a4.dtsi
> @@ -465,7 +465,7 @@
> #address-cells = <0>;
> interrupt-controller;
> reg = <0 0xf1001000 0 0x1000>,
> - <0 0xf1002000 0 0x1000>,
> + <0 0xf1002000 0 0x2000>,
> <0 0xf1004000 0 0x2000>,
> <0 0xf1006000 0 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
> index 216cb1f..172a944 100644
> --- a/arch/arm/boot/dts/r8a7743.dtsi
> +++ b/arch/arm/boot/dts/r8a7743.dtsi
> @@ -55,7 +55,7 @@
> #address-cells = <0>;
> interrupt-controller;
> reg = <0 0xf1001000 0 0x1000>,
> - <0 0xf1002000 0 0x1000>,
> + <0 0xf1002000 0 0x2000>,
> <0 0xf1004000 0 0x2000>,
> <0 0xf1006000 0 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
> diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
> index 0b2e2f3..7390ec0 100644
> --- a/arch/arm/boot/dts/r8a7745.dtsi
> +++ b/arch/arm/boot/dts/r8a7745.dtsi
> @@ -55,7 +55,7 @@
> #address-cells = <0>;
> interrupt-controller;
> reg = <0 0xf1001000 0 0x1000>,
> - <0 0xf1002000 0 0x1000>,
> + <0 0xf1002000 0 0x2000>,
> <0 0xf1004000 0 0x2000>,
> <0 0xf1006000 0 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
> diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
> index 0c8900d..ac38764 100644
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -183,7 +183,7 @@
> #address-cells = <0>;
> interrupt-controller;
> reg = <0 0xf1001000 0 0x1000>,
> - <0 0xf1002000 0 0x1000>,
> + <0 0xf1002000 0 0x2000>,
> <0 0xf1004000 0 0x2000>,
> <0 0xf1006000 0 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
> index 8721466..28039db 100644
> --- a/arch/arm/boot/dts/r8a7791.dtsi
> +++ b/arch/arm/boot/dts/r8a7791.dtsi
> @@ -114,7 +114,7 @@
> #address-cells = <0>;
> interrupt-controller;
> reg = <0 0xf1001000 0 0x1000>,
> - <0 0xf1002000 0 0x1000>,
> + <0 0xf1002000 0 0x2000>,
> <0 0xf1004000 0 0x2000>,
> <0 0xf1006000 0 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
> index 6ced3c1..1ed5c88 100644
> --- a/arch/arm/boot/dts/r8a7792.dtsi
> +++ b/arch/arm/boot/dts/r8a7792.dtsi
> @@ -88,7 +88,7 @@
> #interrupt-cells = <3>;
> interrupt-controller;
> reg = <0 0xf1001000 0 0x1000>,
> - <0 0xf1002000 0 0x1000>,
> + <0 0xf1002000 0 0x2000>,
> <0 0xf1004000 0 0x2000>,
> <0 0xf1006000 0 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
> diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
> index 2fb527c..934c097 100644
> --- a/arch/arm/boot/dts/r8a7793.dtsi
> +++ b/arch/arm/boot/dts/r8a7793.dtsi
> @@ -105,7 +105,7 @@
> #address-cells = <0>;
> interrupt-controller;
> reg = <0 0xf1001000 0 0x1000>,
> - <0 0xf1002000 0 0x1000>,
> + <0 0xf1002000 0 0x2000>,
> <0 0xf1004000 0 0x2000>,
> <0 0xf1006000 0 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
> index fb576db..09f7823 100644
> --- a/arch/arm/boot/dts/r8a7794.dtsi
> +++ b/arch/arm/boot/dts/r8a7794.dtsi
> @@ -71,7 +71,7 @@
> #address-cells = <0>;
> interrupt-controller;
> reg = <0 0xf1001000 0 0x1000>,
> - <0 0xf1002000 0 0x1000>,
> + <0 0xf1002000 0 0x2000>,
> <0 0xf1004000 0 0x2000>,
> <0 0xf1006000 0 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi
> index d770023..d6194bf 100644
> --- a/arch/arm/boot/dts/rk1108.dtsi
> +++ b/arch/arm/boot/dts/rk1108.dtsi
> @@ -215,7 +215,7 @@
> #address-cells = <0>;
>
> reg = <0x32011000 0x1000>,
> - <0x32012000 0x1000>,
> + <0x32012000 0x2000>,
> <0x32014000 0x2000>,
> <0x32016000 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
> diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
> index 4ed49a2..ff9b90b 100644
> --- a/arch/arm/boot/dts/rk3036.dtsi
> +++ b/arch/arm/boot/dts/rk3036.dtsi
> @@ -189,7 +189,7 @@
> #address-cells = <0>;
>
> reg = <0x10139000 0x1000>,
> - <0x1013a000 0x1000>,
> + <0x1013a000 0x2000>,
> <0x1013c000 0x2000>,
> <0x1013e000 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
> index 9d3aee5..9dff822 100644
> --- a/arch/arm/boot/dts/rk322x.dtsi
> +++ b/arch/arm/boot/dts/rk322x.dtsi
> @@ -443,7 +443,7 @@
> #address-cells = <0>;
>
> reg = <0x32011000 0x1000>,
> - <0x32012000 0x1000>,
> + <0x32012000 0x2000>,
> <0x32014000 0x2000>,
> <0x32016000 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index 4fad133..af46cba 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -1110,7 +1110,7 @@
> #address-cells = <0>;
>
> reg = <0xffc01000 0x1000>,
> - <0xffc02000 0x1000>,
> + <0xffc02000 0x2000>,
> <0xffc04000 0x2000>,
> <0xffc06000 0x2000>;
> interrupts = <GIC_PPI 9 0xf04>;
> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> index 2b26175..6ed505a 100644
> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> @@ -861,7 +861,7 @@
> gic: interrupt-controller@01c81000 {
> compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> reg = <0x01c81000 0x1000>,
> - <0x01c82000 0x1000>,
> + <0x01c82000 0x2000>,
> <0x01c84000 0x2000>,
> <0x01c86000 0x2000>;
> interrupt-controller;
> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
> index f7db067..3c24832 100644
> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> @@ -1686,9 +1686,9 @@
> };
>
> gic: interrupt-controller@01c81000 {
> - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> + compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> reg = <0x01c81000 0x1000>,
> - <0x01c82000 0x1000>,
> + <0x01c82000 0x2000>,
> <0x01c84000 0x2000>,
> <0x01c86000 0x2000>;
> interrupt-controller;
> diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> index e4991a7..49dfe86 100644
> --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> @@ -489,7 +489,7 @@
> gic: interrupt-controller@01c81000 {
> compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> reg = <0x01c81000 0x1000>,
> - <0x01c82000 0x1000>,
> + <0x01c82000 0x2000>,
> <0x01c84000 0x2000>,
> <0x01c86000 0x2000>;
> interrupt-controller;
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index d3473f8..04c3fdd 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -217,7 +217,7 @@
> gic: interrupt-controller@01c81000 {
> compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> reg = <0x01c81000 0x1000>,
> - <0x01c82000 0x1000>,
> + <0x01c82000 0x2000>,
> <0x01c84000 0x2000>,
> <0x01c86000 0x2000>;
> interrupt-controller;
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index 6c14a6f..292abd0 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -580,7 +580,7 @@
> gic: interrupt-controller@01c81000 {
> compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> reg = <0x01c81000 0x1000>,
> - <0x01c82000 0x1000>,
> + <0x01c82000 0x2000>,
> <0x01c84000 0x2000>,
> <0x01c86000 0x2000>;
> interrupt-controller;
> diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
> index 979ad1a..b7b5831 100644
> --- a/arch/arm/boot/dts/sun9i-a80.dtsi
> +++ b/arch/arm/boot/dts/sun9i-a80.dtsi
> @@ -613,7 +613,7 @@
> gic: interrupt-controller@01c41000 {
> compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> reg = <0x01c41000 0x1000>,
> - <0x01c42000 0x1000>,
> + <0x01c42000 0x2000>,
> <0x01c44000 0x2000>,
> <0x01c46000 0x2000>;
> interrupt-controller;
>
^ permalink raw reply
* Re: [PATCH v7 4/8] PWM: add PWM driver for STM32 plaftorm
From: Thierry Reding @ 2017-01-18 11:37 UTC (permalink / raw)
To: Benjamin Gaignard
Cc: Lee Jones, robh+dt, Mark Rutland, Alexandre Torgue, devicetree,
Linux Kernel Mailing List, Linux PWM List, Jonathan Cameron,
Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler,
linux-iio, linux-arm-kernel, Fabrice Gasnier, Gerald Baeza,
Arnaud Pouliquen, Linus Walleij, Linaro Kernel Mailman List,
Benjamin Gaignard
In-Reply-To: <CA+M3ks64VEE8a0oeiA8J-T5FDzwWTo=pdaMACy+pz7EyOQY-Jg@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 4616 bytes --]
On Wed, Jan 18, 2017 at 12:15:58PM +0100, Benjamin Gaignard wrote:
> 2017-01-18 11:08 GMT+01:00 Thierry Reding <thierry.reding@gmail.com>:
> > On Thu, Jan 05, 2017 at 10:25:40AM +0100, Benjamin Gaignard wrote:
[...]
> >> +static u32 active_channels(struct stm32_pwm *dev)
> >> +{
> >> + u32 ccer;
> >> +
> >> + regmap_read(dev->regmap, TIM_CCER, &ccer);
> >> +
> >> + return ccer & TIM_CCER_CCXE;
> >> +}
> >
> > This looks like something that you could track in software, but this is
> > probably fine, too. Again, technically regmap_read() could fail, so you
> > might want to consider adding some code to handle it. In practice it
> > probably won't, so maybe you don't.
>
> TIM_CCER_CCXE is a value that IIO timer can also read (not write) so
> I have keep the same logic for pwm driver.
Would that not be racy? What happens if after active_channels() here,
the IIO timer modifies the TIM_CCER register?
> >> + ret = stm32_pwm_config(chip, pwm, state->duty_cycle, state->period);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + if (!enabled && state->enabled)
> >> + ret = stm32_pwm_enable(chip, pwm);
> >> +
> >> + return ret;
> >> +}
> >
> > Would it be possible to merge stm32_pwm_disable(), stm32_pwm_enable(),
> > stm32_pwm_set_polarity() and stm32_pwm_config() into stm32_pwm_apply()?
> > Part of the reason for the atomic API was to make it easier to write
> > these drivers, but your implementation effectively copies what the
> > transitional helpers do.
> >
> > It might not make a difference technically in your case, but I think
> > it'd make the implementation more compact and set a better example for
> > future reference.
>
> hmm... it will create a fat function with lot of where
> enabling/disabling/configuration
> will be mixed I'm really not convince that will more compact and readable.
I don't object to splitting this up into separate functions, I just
don't think the functions should correspond to the legacy ones. One
variant that I think could work out nicely would be to have one
function that precomputes the various values, call in from ->apply()
and then do only the register writes along with a couple of
conditionals depending on enable state, for example.
> >> +static const struct pwm_ops stm32pwm_ops = {
> >> + .owner = THIS_MODULE,
> >> + .apply = stm32_pwm_apply,
> >> +};
> >> +
> >> +static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
> >> + int level, int filter)
> >> +{
> >> + u32 bdtr = TIM_BDTR_BKE;
> >> +
> >> + if (level)
> >> + bdtr |= TIM_BDTR_BKP;
> >> +
> >> + bdtr |= (filter & TIM_BDTR_BKF_MASK) << TIM_BDTR_BKF_SHIFT;
> >> +
> >> + regmap_update_bits(priv->regmap,
> >> + TIM_BDTR, TIM_BDTR_BKE | TIM_BDTR_BKP | TIM_BDTR_BKF,
> >> + bdtr);
> >> +
> >> + regmap_read(priv->regmap, TIM_BDTR, &bdtr);
> >> +
> >> + return (bdtr & TIM_BDTR_BKE) ? 0 : -EINVAL;
> >> +}
> >> +
> >> +static int stm32_pwm_set_breakinput2(struct stm32_pwm *priv,
> >> + int level, int filter)
> >> +{
> >> + u32 bdtr = TIM_BDTR_BK2E;
> >> +
> >> + if (level)
> >> + bdtr |= TIM_BDTR_BK2P;
> >> +
> >> + bdtr |= (filter & TIM_BDTR_BKF_MASK) << TIM_BDTR_BK2F_SHIFT;
> >> +
> >> + regmap_update_bits(priv->regmap,
> >> + TIM_BDTR, TIM_BDTR_BK2E |
> >> + TIM_BDTR_BK2P |
> >> + TIM_BDTR_BK2F,
> >> + bdtr);
> >> +
> >> + regmap_read(priv->regmap, TIM_BDTR, &bdtr);
> >> +
> >> + return (bdtr & TIM_BDTR_BK2E) ? 0 : -EINVAL;
> >> +}
> >
> > As far as I can tell the only difference here is the various bit
> > positions. Can you collapse the above two functions and add a new
> > parameter to unify some code?
>
> Yes it is all about bit shifting, I had try unify those two functions
> with index has additional parameter
> but it just add if() before each lines so no real benefit for code size.
How about if you precompute the values and masks? Something like:
u32 bke = (index == 0) ? ... : ...;
u32 bkp = (index == 0) ? ... : ...;
u32 bkf = (index == 0) ? ... : ...;
u32 mask = (index == 0) ? ... : ...;
bdtr = bke | bkf;
if (level)
bdtr |= bkp;
regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
regmap_read(priv->regmap, TIM_BDTR, &bdtr);
return (bdtr & bke) ? 0 : -EINVAL;
?
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^ permalink raw reply
* Re: [PATCH 2/2] ARM: DTS: Fix register map for virt-capable GIC
From: Robin Murphy @ 2017-01-18 11:57 UTC (permalink / raw)
To: Marc Zyngier, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Mark Rutland, Heiko Stuebner, Tony Lindgren,
arm-DgEjT+Ai2ygdnm+yROfE0A, Magnus Damm, Russell King,
Krzysztof Kozlowski, Javier Martinez Canillas, Chen-Yu Tsai,
Kukjin Kim, Tsahee Zidenberg, Jason Cooper, Simon Horman,
Santosh Shilimkar, Matthias Brugger, Thomas Gleixner,
Sascha Hauer, Antoine Tenart, Rob Herring, Benoît Cousson
In-Reply-To: <1484736811-24002-3-git-send-email-marc.zyngier-5wv7dgnIgG8@public.gmane.org>
On 18/01/17 10:53, Marc Zyngier wrote:
> Since everybody copied my own mistake from the DT binding example,
> let's address all the offenders in one swift go.
>
> Most of them got the CPU interface size wrong (4kB, while it should
> be 8kB), except for both keystone platforms which got the control
> interface wrong (4kB instead of 8kB).
>
> In the couple of cases were I knew for sure what implementation
where
> was used, I've added the "arm,gic-400" compatible string. I'm 99%
> sure that this is what everyong is using, but short of having the
everyone
> TRM for all the other SoCs, I've let them alone.
>
> Signed-off-by: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
> ---
[...]
> diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
> index 63c7cf0..07bf300 100644
> --- a/arch/arm/boot/dts/keystone-k2g.dtsi
> +++ b/arch/arm/boot/dts/keystone-k2g.dtsi
> @@ -45,7 +45,7 @@
> interrupt-controller;
> reg = <0x0 0x02561000 0x0 0x1000>,
> <0x0 0x02562000 0x0 0x2000>,
> - <0x0 0x02564000 0x0 0x1000>,
> + <0x0 0x02564000 0x0 0x2000>,
> <0x0 0x02566000 0x0 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>;
> diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
> index 02708ba..aaff6816 100644
> --- a/arch/arm/boot/dts/keystone.dtsi
> +++ b/arch/arm/boot/dts/keystone.dtsi
> @@ -35,7 +35,7 @@
> interrupt-controller;
> reg = <0x0 0x02561000 0x0 0x1000>,
> <0x0 0x02562000 0x0 0x2000>,
> - <0x0 0x02564000 0x0 0x1000>,
> + <0x0 0x02564000 0x0 0x2000>,
> <0x0 0x02566000 0x0 0x2000>;
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>;
FWIW I happen to have some public Keystone TRMs handy from my DMA offset
investigations, and both K2G and K2H explicitly say it's a GIC-400 too.
Robin.
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^ permalink raw reply
* Re: [PATCH 1/2] ARM: dts: dra7-evm: increase QSPI SPL partition size
From: Sekhar Nori @ 2017-01-18 11:58 UTC (permalink / raw)
To: Tony Lindgren, B, Ravi
Cc: devicetree@vger.kernel.org, linux-omap@vger.kernel.org,
Sekhar Nori, bcousson@baylibre.com,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20170117232743.GA7403@atomide.com>
Hi Tony,
On Wednesday 18 January 2017 04:57 AM, Tony Lindgren wrote:
> * B, Ravi <ravibabu@ti.com> [170117 00:15]:
>> Hi Tony
>>
>>> * Ravi Babu <ravibabu@ti.com> [170113 04:41]:
>>>> The SPL size for DRA74x platform has increased and is now more than
>>>> 64KB. Increase QSPI SPL partition size to 256KB for DRA74x EVM.
>>>>
>>>> QSPI partition numbering changes because of this.
>>
>>> And this will break the existing partitions potentially..
>>> See what was discussed on the list few days ago in thread "[PATCH 1/6] ARM: dts: am335x-phycore-som: Update NAND partition table".
>>
>>> It's best to have these left empty or as they originally were and let u-boot configure the partitions.
>>
>> Agree with you. For dra7xx platform the SPL size has been increased to 256KB and hence the existing QSPI SPL partition in kernel (64K size) will break when latest mainline u-boot is used.
>> Here only SPL partition has been changed and other partition & size is NOT changed and kept intact. I feel it will not break the existing partitions for dra7xx platform.
>
> What about the renumbering of partitions in your patch?
Thats true, partitions will get renumbered. But mtd numbering can change
depending on probe order of devices anyway. So usespace which uses
hardcoded mtd partition numbers is pretty fragile already, I guess.
>
> Probably just best to make the partition information empty in the
> kernel as discussed.
Given that existing dtbs already have the partition information, wont
this be treated as a regression for someone upgrading to new kernel?
Going forward, is the preference that new boards shall not have
partition information in DT?
Thanks,
Sekhar
^ permalink raw reply
* Re: [PATCH v4 1/2] power: reset: add linkstation-reset driver
From: Roger Shimizu @ 2017-01-18 12:08 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Andrew Lunn, Florian Fainelli, Ryan Tandy, linux-pm,
Herbert Valerio Riedel, devicetree, Martin Michlmayr,
linux-arm-kernel, Sylver Bruneau
In-Reply-To: <20170107150451.17912-2-rogershimizu@gmail.com>
Dear Sebastian,
On Sun, Jan 8, 2017 at 12:04 AM, Roger Shimizu <rogershimizu@gmail.com> wrote:
> Buffalo Linkstation / KuroBox and their variants need magic command
> sending to UART1 to power-off.
>
> Power driver linkstation-reset implements the magic command and I/O
> routine, which come from files listed below:
> - arch/arm/mach-orion5x/kurobox_pro-setup.c
> - arch/arm/mach-orion5x/terastation_pro2-setup.c
I think there's not much concern regarding to this series.
Could you kindly help to apply this patch?
Thank you!
Cheers,
--
Roger Shimizu, GMT +9 Tokyo
PGP/GPG: 4096R/6C6ACD6417B3ACB1
^ permalink raw reply
* [PATCH 1/3] arm64: dts: juno: Add dma-ranges property
From: Robin Murphy @ 2017-01-18 12:12 UTC (permalink / raw)
To: linux-arm-kernel, devicetree; +Cc: lorenzo.pieralisi, liviu.dudau, sudeep.holla
The interconnects around Juno have a 40-bit address width, and DMA
masters have no restrictions beyond their own individual limitations.
Describe this to ensure that DT-based DMA masks get set up correctly
for all devices capable of 40-bit addressing.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
These apply on top of Sudeep's for-next/updates/juno branch, which
supercedes the .dtsi cleanup I had locally to make this one work.
Robin.
arch/arm64/boot/dts/arm/juno-base.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 44db27776b9d..5e7640d6ec69 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -4,6 +4,7 @@
/*
* Devices shared by all Juno boards
*/
+ dma-ranges = <0 0 0 0 0x100 0>;
memtimer: timer@2a810000 {
compatible = "arm,armv7-timer-mem";
--
2.11.0.dirty
^ permalink raw reply related
* [PATCH 2/3] arm64: dts: juno: Add ETR SMMU power domain
From: Robin Murphy @ 2017-01-18 12:12 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: sudeep.holla-5wv7dgnIgG8, lorenzo.pieralisi-5wv7dgnIgG8,
liviu.dudau-5wv7dgnIgG8
In-Reply-To: <74595d6d866518db7cfabc39b4cf9b54d3be9bde.1484741104.git.robin.murphy-5wv7dgnIgG8@public.gmane.org>
It is not at all clear from the documentation, but straightforward to
determine in practice, that the ETR SMMU is actually in the DEBUGSYS
power domain. Add that to the DT so that anyone brave enough to enable
said SMMU doesn't experience a system lockup on boot, especially a
sneaky one which goes away as soon as you connect an external debugger
to have a look at where it's stuck (thus powering up DEBUGSYS by other
means and allowing it to make progress again before actually halting...)
Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 5e7640d6ec69..37225dfdc995 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -52,6 +52,7 @@
#iommu-cells = <1>;
#global-interrupts = <1>;
dma-coherent;
+ power-domains = <&scpi_devpd 0>;
status = "disabled";
};
--
2.11.0.dirty
--
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^ permalink raw reply related
* [PATCH 3/3] arm64: dts: juno: Remove Motherboard USB node
From: Robin Murphy @ 2017-01-18 12:12 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: sudeep.holla-5wv7dgnIgG8, lorenzo.pieralisi-5wv7dgnIgG8,
liviu.dudau-5wv7dgnIgG8
In-Reply-To: <74595d6d866518db7cfabc39b4cf9b54d3be9bde.1484741104.git.robin.murphy-5wv7dgnIgG8@public.gmane.org>
The first batch of Juno boards included a discrete USB controller chip
as a contingency in case of issues with the USB 2.0 IP integrated into
the SoC. As it turned out, the latter was fine, and to the best of my
knowledge the motherboard USB was never even brought up and validated.
Since this also isn't present on later boards, and uses a compatible
string undocumented and unmatched by any driver in the kernel, let's
just tidy it away for ever to avoid any confusion.
Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
---
arch/arm64/boot/dts/arm/juno-motherboard.dtsi | 7 -------
1 file changed, 7 deletions(-)
diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
index 3ad4c3000611..098601657f82 100644
--- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
@@ -131,13 +131,6 @@
vddvario-supply = <&mb_fixed_3v3>;
};
- usb@5,00000000 {
- compatible = "nxp,usb-isp1763";
- reg = <5 0x00000000 0x20000>;
- bus-width = <16>;
- interrupts = <4>;
- };
-
iofpga@3,00000000 {
compatible = "simple-bus";
#address-cells = <1>;
--
2.11.0.dirty
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^ permalink raw reply related
* Re: [PATCH v5 5/5] i2c: mux: pca954x: Add irq-mask-enable to delay enabling irqs
From: Peter Rosin @ 2017-01-18 12:19 UTC (permalink / raw)
To: Phil Reid, wsa-z923LK4zBo2bacvFa/9K2g,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1484640029-22870-6-git-send-email-preid-qgqNFa1JUf/o2iN0hyhwsIdd74u8MsAO@public.gmane.org>
On 2017-01-17 09:00, Phil Reid wrote:
> Unfortunately some hardware device will assert their irq line immediately
> on power on and provide no mechanism to mask the irq. As the i2c muxes
> provide no method to mask irq line this provides a work around by keeping
> the parent irq masked until enough device drivers have loaded to service
> all pending interrupts.
>
> For example the the ltc1760 assert its SMBALERT irq immediately on power
> on. With two ltc1760 attached to bus 0 & 1 on a pca954x mux when the first
> device is registered irq are enabled and fire continuously as the second
> device driver has not yet loaded. Setting this parameter to <1 1> will
> delay the irq being enabled until both devices are ready.
>
> Signed-off-by: Phil Reid <preid-qgqNFa1JUf/o2iN0hyhwsIdd74u8MsAO@public.gmane.org>
> ---
> drivers/i2c/muxes/i2c-mux-pca954x.c | 33 ++++++++++++++++++++++++++++++---
> 1 file changed, 30 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/i2c/muxes/i2c-mux-pca954x.c b/drivers/i2c/muxes/i2c-mux-pca954x.c
> index f55da88..012b2ef 100644
> --- a/drivers/i2c/muxes/i2c-mux-pca954x.c
> +++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
> @@ -76,6 +76,19 @@ struct chip_desc {
> } muxtype;
> };
>
> +/*
> + * irq_mask_enable: Provides a mechanism to work around hardware that asserts
> + * their irq immediately on power on. It allows the enabling of the irq to be
> + * delayed until the corresponding bits in the the irq_mask are set thru
> + * irq_unmask.
> + * For example the ltc1760 assert its SMBALERT irq immediately on power on.
> + * With two ltc1760 attached to bus 0 & 1 on a pca954x mux when the first
> + * device is registered irq are enabled and fire continuously as the second
> + * device driver has not yet loaded. Setting this parameter to 0x3 while
> + * delay the irq being enabled until both devices are ready.
> + * This workaround will not work if two devices share an interrupt on the
> + * same bus segment.
It will also not work if something shares the interrupt with the pca954x mux,
on the parent side of the mux, so to speak. Then that other driver may
potentially enable the irq "behind the back" of the pca954x driver.
> + */
> struct pca954x {
> const struct chip_desc *chip;
>
> @@ -84,7 +97,9 @@ struct pca954x {
> struct i2c_client *client;
>
> struct irq_domain *irq;
> + unsigned int irq_mask_enable;
> unsigned int irq_mask;
> + bool irq_enabled;
> spinlock_t lock;
> };
>
> @@ -266,8 +281,10 @@ static void pca954x_irq_mask(struct irq_data *idata)
> spin_lock_irqsave(&data->lock, flags);
>
> data->irq_mask &= ~BIT(pos);
> - if (!data->irq_mask)
> + if (data->irq_enabled && !data->irq_mask) {
> disable_irq(data->client->irq);
> + data->irq_enabled = false;
> + }
When irq_mask_enable is non-zero, I think the parent irq should be masked
when the first irq from the set in irq_mask_enable is masked. For symmetry.
Like so (untested):
if (data->irq_enabled) {
if (!data->irq_mask ||
(data->irq_mask & mask_enable) != mask_enable) {
disable_irq(data->client->irq);
data->irq_enabled = false;
}
}
Hmm, this whole thing is fiddly and while it solves your problem it doesn't
allow for solving the more general problem when there are "problematic"
devices mixed with other devices. At least, I don't see it. And the
limitations we are walking into with tracking number of enables etc suggests
that we are attacking this at the wrong level. Maybe you should try to work
around the hw limitations not in the pca954x driver, but in the irq core?
I.e. have the irq core check, for each irq, for a property that specifies
the depth at which each irq should be unmasked. This new property should
probably be located in the interrupt-controller node? Then the code can
unmask interrupts when the depth hits this mark, instead of always unmasking
the interrupt when the depth changes from zero to one. You are then adding
the workaround at a level where there is enough information to fix the
more general problem. I think?
But, once again, I'm no irq expert and would desperately like a second
opinion on this stuff...
>
> spin_unlock_irqrestore(&data->lock, flags);
> }
> @@ -275,14 +292,18 @@ static void pca954x_irq_mask(struct irq_data *idata)
> static void pca954x_irq_unmask(struct irq_data *idata)
> {
> struct pca954x *data = irq_data_get_irq_chip_data(idata);
> + unsigned int mask_enable = data->irq_mask_enable;
> unsigned int pos = idata->hwirq;
> unsigned long flags;
>
> spin_lock_irqsave(&data->lock, flags);
>
> - if (!data->irq_mask)
> - enable_irq(data->client->irq);
> data->irq_mask |= BIT(pos);
> + if (!data->irq_enabled
> + && (data->irq_mask & mask_enable) == mask_enable) {
I think the coding standard says that the && should be at the end of the
first line. Didn't checkpatch complain?
Cheers,
peda
> + enable_irq(data->client->irq);
> + data->irq_enabled = true;
> + }
>
> spin_unlock_irqrestore(&data->lock, flags);
> }
> @@ -305,6 +326,7 @@ static int pca954x_irq_setup(struct i2c_mux_core *muxc)
> {
> struct pca954x *data = i2c_mux_priv(muxc);
> struct i2c_client *client = data->client;
> + u32 irq_mask_enable[PCA954X_MAX_NCHANS] = { 0 };
> int c, err, irq;
>
> if (!data->chip->has_irq || client->irq <= 0)
> @@ -312,6 +334,9 @@ static int pca954x_irq_setup(struct i2c_mux_core *muxc)
>
> spin_lock_init(&data->lock);
>
> + of_property_read_u32_array(client->dev.of_node, "nxp,irq-mask-enable",
> + irq_mask_enable, data->chip->nchans);
> +
> data->irq = irq_domain_add_linear(client->dev.of_node,
> data->chip->nchans,
> &irq_domain_simple_ops, data);
> @@ -319,6 +344,8 @@ static int pca954x_irq_setup(struct i2c_mux_core *muxc)
> return -ENODEV;
>
> for (c = 0; c < data->chip->nchans; c++) {
> + data->irq_mask_enable |= irq_mask_enable[c] ? BIT(c) : 0;
> + WARN_ON(irq_mask_enable[c] > 1);
> irq = irq_create_mapping(data->irq, c);
> irq_set_chip_data(irq, data);
> irq_set_chip_and_handler(irq, &pca954x_irq_chip,
>
--
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^ permalink raw reply
* [PATCH v2 0/3] Support for USB DRD Phy driver for NS2
From: Raviteja Garimella @ 2017-01-18 12:20 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kishon Vijay Abraham I, Ray Jui,
Scott Branden, Jon Mason, Catalin Marinas, Will Deacon
Cc: devicetree, bcm-kernel-feedback-list, linux-kernel,
linux-arm-kernel
Changes from v1:
===============
1. Initialize file operatiosn .owner field with THIS_MODULE
2. Remove unnecessary gpio example in DT bindings documentation.
This is previously acked by Rob Herring <robh@kernel.org>.
Introduction:
This patch adds support for USB Dual Role Device Phy for Broadcom
Northstar2 SoC. Apart from the new phy driver, this patchset contains
changes to Kconfig, Makefile, and Device tree files.
This patchset is tested on Broadcom NS2 BCM958712K reference board.
Repo: https://github.com/Broadcom/arm64-linux.git
Branch: ns2_drdphy_v2
Raviteja Garimella (3):
Add DT bindings documentation for NS2 USB DRD phy
Broadcom USB DRD Phy driver for Northstar2
DT nodes for Broadcom Northstar2 USB DRD Phy
.../devicetree/bindings/phy/brcm,ns2-drd-phy.txt | 30 ++
arch/arm64/boot/dts/broadcom/ns2.dtsi | 14 +
drivers/phy/Kconfig | 13 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-bcm-ns2-usbdrd.c | 588 +++++++++++++++++++++
5 files changed, 646 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/brcm,ns2-drd-phy.txt
create mode 100644 drivers/phy/phy-bcm-ns2-usbdrd.c
--
2.1.0
^ permalink raw reply
* [PATCH v2 1/3] Add DT bindings documentation for NS2 USB DRD phy
From: Raviteja Garimella @ 2017-01-18 12:20 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kishon Vijay Abraham I, Ray Jui,
Scott Branden, Jon Mason, Catalin Marinas, Will Deacon
Cc: devicetree, bcm-kernel-feedback-list, linux-kernel,
linux-arm-kernel
In-Reply-To: <1484742004-6792-1-git-send-email-raviteja.garimella@broadcom.com>
This patch adds documentation for NS2 DRD Phy driver DT bindings
Signed-off-by: Raviteja Garimella <raviteja.garimella@broadcom.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/phy/brcm,ns2-drd-phy.txt | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/brcm,ns2-drd-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/brcm,ns2-drd-phy.txt b/Documentation/devicetree/bindings/phy/brcm,ns2-drd-phy.txt
new file mode 100644
index 0000000..04f063a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/brcm,ns2-drd-phy.txt
@@ -0,0 +1,30 @@
+BROADCOM NORTHSTAR2 USB2 (DUAL ROLE DEVICE) PHY
+
+Required properties:
+ - compatible: brcm,ns2-drd-phy
+ - reg: offset and length of the NS2 PHY related registers.
+ - reg-names
+ The below registers must be provided.
+ icfg - for DRD ICFG configurations
+ rst-ctrl - for DRD IDM reset
+ crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset
+ usb2-strap - for port over current polarity reversal
+ - #phy-cells: Must be 0. No args required.
+ - vbus-gpios: vbus gpio binding
+ - id-gpios: id gpio binding
+
+Refer to phy/phy-bindings.txt for the generic PHY binding properties
+
+Example:
+ usbdrd_phy: phy@66000960 {
+ #phy-cells = <0>;
+ compatible = "brcm,ns2-drd-phy";
+ reg = <0x66000960 0x24>,
+ <0x67012800 0x4>,
+ <0x6501d148 0x4>,
+ <0x664d0700 0x4>;
+ reg-names = "icfg", "rst-ctrl",
+ "crmu-ctrl", "usb2-strap";
+ id-gpios = <&gpio_g 30 0>;
+ vbus-gpios = <&gpio_g 31 0>;
+ };
--
2.1.0
^ permalink raw reply related
* [PATCH v2 2/3] Broadcom USB DRD Phy driver for Northstar2
From: Raviteja Garimella @ 2017-01-18 12:20 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kishon Vijay Abraham I, Ray Jui,
Scott Branden, Jon Mason, Catalin Marinas, Will Deacon
Cc: devicetree, linux-kernel, bcm-kernel-feedback-list,
linux-arm-kernel
In-Reply-To: <1484742004-6792-1-git-send-email-raviteja.garimella@broadcom.com>
This is driver for USB DRD Phy used in Broadcom's Northstar2
SoC. The phy can be configured to be in Device mode or Host
mode based on the type of cable connected to the port. The
driver registers to extcon framework to get appropriate
connect events for Host/Device cables connect/disconnect
states based on VBUS and ID interrupts.
Signed-off-by: Raviteja Garimella <raviteja.garimella@broadcom.com>
---
drivers/phy/Kconfig | 13 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-bcm-ns2-usbdrd.c | 588 +++++++++++++++++++++++++++++++++++++++
3 files changed, 602 insertions(+)
create mode 100644 drivers/phy/phy-bcm-ns2-usbdrd.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index e8eb7f2..1b3de42 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -463,6 +463,19 @@ config PHY_CYGNUS_PCIE
Enable this to support the Broadcom Cygnus PCIe PHY.
If unsure, say N.
+config PHY_NS2_USB_DRD
+ tristate "Broadcom Northstar2 USB DRD PHY support"
+ depends on OF && (ARCH_BCM_IPROC || COMPILE_TEST)
+ select GENERIC_PHY
+ select EXTCON
+ default ARCH_BCM_IPROC
+ help
+ Enable this to support the Broadcom Northstar2 USB DRD PHY.
+ This driver initializes the PHY in either HOST or DEVICE mode.
+ The host or device configuration is read from device tree.
+
+ If unsure, say N.
+
source "drivers/phy/tegra/Kconfig"
config PHY_NS2_PCIE
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 65eb2f4..cfbdd9a 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
obj-$(CONFIG_PHY_BRCM_SATA) += phy-brcm-sata.o
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
+obj-$(CONFIG_PHY_NS2_USB_DRD) += phy-bcm-ns2-usbdrd.o
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o
obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
diff --git a/drivers/phy/phy-bcm-ns2-usbdrd.c b/drivers/phy/phy-bcm-ns2-usbdrd.c
new file mode 100644
index 0000000..e9478d1
--- /dev/null
+++ b/drivers/phy/phy-bcm-ns2-usbdrd.c
@@ -0,0 +1,588 @@
+/*
+ * Copyright (C) 2016 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/extcon.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+
+#define ICFG_DRD_AFE 0x0
+#define ICFG_MISC_STAT 0x18
+#define ICFG_DRD_P0CTL 0x1C
+#define ICFG_STRAP_CTRL 0x20
+#define ICFG_FSM_CTRL 0x24
+
+#define IDM_RST_BIT BIT(0)
+#define AFE_CORERDY_VDDC BIT(18)
+#define PHY_PLL_RESETB BIT(15)
+#define PHY_RESETB BIT(14)
+#define PHY_PLL_LOCK BIT(0)
+
+#define DRD_DEV_MODE BIT(20)
+#define OHCI_OVRCUR_POL BIT(11)
+#define ICFG_OFF_MODE BIT(6)
+#define PLL_LOCK_RETRY 1000
+
+#define EVT_DEVICE 0
+#define EVT_HOST 1
+#define EVT_IDLE 2
+
+#define DRD_HOST_MODE (BIT(2) | BIT(3))
+#define DRD_DEVICE_MODE (BIT(4) | BIT(5))
+#define DRD_HOST_VAL 0x803
+#define DRD_DEV_VAL 0x807
+#define GPIO_DELAY 20
+#define PHY_WQ_DELAY msecs_to_jiffies(600)
+
+struct ns2_phy_data;
+struct ns2_phy_driver {
+ void __iomem *icfgdrd_regs;
+ void __iomem *idmdrd_rst_ctrl;
+ void __iomem *crmu_usb2_ctrl;
+ void __iomem *usb2h_strap_reg;
+ spinlock_t lock; /* spin lock for phy driver */
+ bool host_mode;
+ struct ns2_phy_data *data;
+ struct extcon_specific_cable_nb extcon_dev;
+ struct extcon_specific_cable_nb extcon_host;
+ struct notifier_block host_nb;
+ struct notifier_block dev_nb;
+ struct delayed_work conn_work;
+ struct extcon_dev *edev;
+ struct gpio_desc *vbus_gpiod;
+ struct gpio_desc *id_gpiod;
+ int id_irq;
+ int vbus_irq;
+ unsigned long debounce_jiffies;
+ struct delayed_work wq_extcon;
+};
+
+struct ns2_phy_data {
+ struct ns2_phy_driver *driver;
+ struct phy *phy;
+ int new_state;
+ bool poweron;
+};
+
+static const unsigned int usb_extcon_cable[] = {
+ EXTCON_USB,
+ EXTCON_USB_HOST,
+ EXTCON_NONE,
+};
+
+static inline int pll_lock_stat(u32 usb_reg, int reg_mask,
+ struct ns2_phy_driver *driver)
+{
+ int retry = PLL_LOCK_RETRY;
+ u32 val;
+
+ do {
+ udelay(1);
+ val = readl(driver->icfgdrd_regs + usb_reg);
+ if (val & reg_mask)
+ return 0;
+ } while (--retry > 0);
+
+ return -EBUSY;
+}
+
+static int ns2_drd_phy_init(struct phy *phy)
+{
+ struct ns2_phy_data *data = phy_get_drvdata(phy);
+ struct ns2_phy_driver *driver = data->driver;
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&driver->lock, flags);
+
+ val = readl(driver->icfgdrd_regs + ICFG_FSM_CTRL);
+
+ if (data->new_state == EVT_HOST) {
+ val &= ~DRD_DEVICE_MODE;
+ val |= DRD_HOST_MODE;
+ } else {
+ val &= ~DRD_HOST_MODE;
+ val |= DRD_DEVICE_MODE;
+ }
+ writel(val, driver->icfgdrd_regs + ICFG_FSM_CTRL);
+
+ spin_unlock_irqrestore(&driver->lock, flags);
+ return 0;
+}
+
+static int ns2_drd_phy_shutdown(struct phy *phy)
+{
+ struct ns2_phy_data *data = phy_get_drvdata(phy);
+ struct ns2_phy_driver *driver = data->driver;
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&driver->lock, flags);
+ if (!data->poweron)
+ goto exit;
+
+ val = readl(driver->crmu_usb2_ctrl);
+ val &= ~AFE_CORERDY_VDDC;
+ writel(val, driver->crmu_usb2_ctrl);
+
+ driver->host_mode = 0;
+ val = readl(driver->crmu_usb2_ctrl);
+ val &= ~DRD_DEV_MODE;
+ writel(val, driver->crmu_usb2_ctrl);
+
+ /* Disable Host and Device Mode */
+ val = readl(driver->icfgdrd_regs + ICFG_FSM_CTRL);
+ val &= ~(DRD_HOST_MODE | DRD_DEVICE_MODE | ICFG_OFF_MODE);
+ writel(val, driver->icfgdrd_regs + ICFG_FSM_CTRL);
+
+ data->poweron = 0;
+exit:
+ spin_unlock_irqrestore(&driver->lock, flags);
+ return 0;
+}
+
+static int ns2_drd_phy_poweron(struct phy *phy)
+{
+ struct ns2_phy_data *data = phy_get_drvdata(phy);
+ struct ns2_phy_driver *driver = data->driver;
+ u32 extcon_event = data->new_state;
+ unsigned long flags;
+ int ret;
+ u32 val;
+
+ spin_lock_irqsave(&driver->lock, flags);
+ if (extcon_event == EVT_DEVICE) {
+ if (data->poweron)
+ goto exit;
+
+ writel(DRD_DEV_VAL, driver->icfgdrd_regs + ICFG_DRD_P0CTL);
+
+ val = readl(driver->icfgdrd_regs + ICFG_FSM_CTRL);
+ val &= ~(DRD_HOST_MODE | ICFG_OFF_MODE);
+ val |= DRD_DEVICE_MODE;
+ writel(val, driver->icfgdrd_regs + ICFG_FSM_CTRL);
+
+ val = readl(driver->idmdrd_rst_ctrl);
+ val &= ~IDM_RST_BIT;
+ writel(val, driver->idmdrd_rst_ctrl);
+
+ val = readl(driver->crmu_usb2_ctrl);
+ val |= (AFE_CORERDY_VDDC | DRD_DEV_MODE);
+ writel(val, driver->crmu_usb2_ctrl);
+
+ /* Bring PHY and PHY_PLL out of Reset */
+ val = readl(driver->crmu_usb2_ctrl);
+ val |= (PHY_PLL_RESETB | PHY_RESETB);
+ writel(val, driver->crmu_usb2_ctrl);
+
+ ret = pll_lock_stat(ICFG_MISC_STAT, PHY_PLL_LOCK, driver);
+ if (ret < 0) {
+ dev_err(&phy->dev, "Phy PLL lock failed\n");
+ goto err_shutdown;
+ }
+ } else {
+ if (data->poweron && driver->host_mode)
+ goto exit;
+
+ writel(DRD_HOST_VAL, driver->icfgdrd_regs + ICFG_DRD_P0CTL);
+
+ val = readl(driver->icfgdrd_regs + ICFG_FSM_CTRL);
+ val &= ~(DRD_DEVICE_MODE | ICFG_OFF_MODE);
+ val |= DRD_HOST_MODE;
+ writel(val, driver->icfgdrd_regs + ICFG_FSM_CTRL);
+
+ val = readl(driver->crmu_usb2_ctrl);
+ val |= AFE_CORERDY_VDDC;
+ writel(val, driver->crmu_usb2_ctrl);
+
+ ret = pll_lock_stat(ICFG_MISC_STAT, PHY_PLL_LOCK, driver);
+ if (ret < 0) {
+ dev_err(&phy->dev, "Phy PLL lock failed\n");
+ goto err_shutdown;
+ }
+
+ val = readl(driver->idmdrd_rst_ctrl);
+ val &= ~IDM_RST_BIT;
+ writel(val, driver->idmdrd_rst_ctrl);
+
+ /* port over current Polarity */
+ val = readl(driver->usb2h_strap_reg);
+ val |= OHCI_OVRCUR_POL;
+ writel(val, driver->usb2h_strap_reg);
+
+ driver->host_mode = 1;
+ }
+
+ data->poweron = 1;
+exit:
+ spin_unlock_irqrestore(&driver->lock, flags);
+ return 0;
+
+err_shutdown:
+ data->poweron = 1;
+ spin_unlock_irqrestore(&driver->lock, flags);
+ ns2_drd_phy_shutdown(phy);
+ return ret;
+}
+
+static void connect_work(struct work_struct *work)
+{
+ struct ns2_phy_driver *driver;
+ struct ns2_phy_data *data;
+ u32 extcon_event;
+
+ driver = container_of(to_delayed_work(work),
+ struct ns2_phy_driver, conn_work);
+ data = driver->data;
+ extcon_event = data->new_state;
+
+ if (extcon_event == EVT_DEVICE || extcon_event == EVT_HOST) {
+ ns2_drd_phy_init(data->phy);
+ ns2_drd_phy_poweron(data->phy);
+ } else if (extcon_event == EVT_IDLE) {
+ ns2_drd_phy_shutdown(data->phy);
+ }
+}
+
+static int drd_device_notify(struct notifier_block *self,
+ unsigned long event, void *ptr)
+{
+ struct ns2_phy_driver *driver = container_of(self,
+ struct ns2_phy_driver, dev_nb);
+
+ if (event) {
+ pr_debug("Device connected\n");
+ driver->data->new_state = EVT_DEVICE;
+ schedule_delayed_work(&driver->conn_work, 0);
+ } else {
+ pr_debug("Device disconnected\n");
+ driver->data->new_state = EVT_IDLE;
+ schedule_delayed_work(&driver->conn_work, PHY_WQ_DELAY);
+ }
+
+ return NOTIFY_DONE;
+}
+
+static int drd_host_notify(struct notifier_block *self,
+ unsigned long event, void *ptr)
+{
+ struct ns2_phy_driver *driver = container_of(self,
+ struct ns2_phy_driver, host_nb);
+
+ if (event) {
+ pr_debug("Host connected\n");
+ driver->data->new_state = EVT_HOST;
+ schedule_delayed_work(&driver->conn_work, 0);
+ } else {
+ pr_debug("Host disconnected\n");
+ driver->data->new_state = EVT_IDLE;
+ schedule_delayed_work(&driver->conn_work, PHY_WQ_DELAY);
+ }
+
+ return NOTIFY_DONE;
+}
+
+static void extcon_work(struct work_struct *work)
+{
+ struct ns2_phy_driver *driver;
+ int vbus;
+ int id;
+
+ driver = container_of(to_delayed_work(work),
+ struct ns2_phy_driver, wq_extcon);
+
+ id = gpiod_get_value_cansleep(driver->id_gpiod);
+ vbus = gpiod_get_value_cansleep(driver->vbus_gpiod);
+
+ if (!id && vbus) {
+ extcon_set_cable_state_(driver->edev, EXTCON_USB_HOST, true);
+ } else if (id && !vbus) {
+ extcon_set_cable_state_(driver->edev, EXTCON_USB_HOST, false);
+ extcon_set_cable_state_(driver->edev, EXTCON_USB, false);
+ } else if (id && vbus) {
+ extcon_set_cable_state_(driver->edev, EXTCON_USB, true);
+ }
+}
+
+static irqreturn_t gpio_irq_handler(int irq, void *dev_id)
+{
+ struct ns2_phy_driver *driver = dev_id;
+
+ queue_delayed_work(system_power_efficient_wq, &driver->wq_extcon,
+ driver->debounce_jiffies);
+
+ return IRQ_HANDLED;
+}
+
+static int register_extcon_notifier(struct ns2_phy_driver *phy_driver,
+ struct device *dev)
+{
+ struct extcon_dev *edev;
+ int ret;
+
+ phy_driver->host_nb.notifier_call = drd_host_notify;
+ phy_driver->dev_nb.notifier_call = drd_device_notify;
+
+ edev = phy_driver->edev;
+
+ /* Register for device change notification */
+ ret = extcon_register_notifier(edev, EXTCON_USB,
+ &phy_driver->dev_nb);
+ if (ret < 0) {
+ dev_err(dev, "can't register extcon_dev for %s\n", edev->name);
+ return ret;
+ }
+
+ /* Register for host change notification */
+ ret = extcon_register_notifier(edev, EXTCON_USB_HOST,
+ &phy_driver->host_nb);
+ if (ret < 0) {
+ dev_err(dev, "can't register extcon_dev for %s\n", edev->name);
+ goto err_dev;
+ }
+
+ /* Check the device cable connect state */
+ ret = extcon_get_cable_state_(edev, EXTCON_USB);
+ if (ret < 0) {
+ dev_err(dev, "can't get extcon_dev state for %s\n", edev->name);
+ goto err_host;
+ } else if (ret) {
+ phy_driver->data->new_state = EVT_DEVICE;
+ }
+
+ /* Check the host cable connect state */
+ ret = extcon_get_cable_state_(edev, EXTCON_USB_HOST);
+ if (ret < 0) {
+ dev_err(dev, "can't get extcon_dev state for %s\n", edev->name);
+ goto err_host;
+ } else if (ret) {
+ phy_driver->data->new_state = EVT_HOST;
+ }
+
+ return 0;
+
+err_host:
+ ret = extcon_unregister_notifier(edev, EXTCON_USB_HOST,
+ &phy_driver->host_nb);
+err_dev:
+ ret = extcon_unregister_notifier(edev, EXTCON_USB,
+ &phy_driver->dev_nb);
+ return ret;
+}
+
+static struct phy_ops ops = {
+ .init = ns2_drd_phy_init,
+ .power_on = ns2_drd_phy_poweron,
+ .power_off = ns2_drd_phy_shutdown,
+ .owner = THIS_MODULE,
+};
+
+static const struct of_device_id ns2_drd_phy_dt_ids[] = {
+ { .compatible = "brcm,ns2-drd-phy", },
+ { }
+};
+
+static int ns2_drd_phy_remove(struct platform_device *pdev)
+{
+ struct ns2_phy_driver *driver = dev_get_drvdata(&pdev->dev);
+
+ if (driver->edev) {
+ extcon_unregister_notifier(driver->edev, EXTCON_USB_HOST,
+ &driver->host_nb);
+ extcon_unregister_notifier(driver->edev, EXTCON_USB,
+ &driver->dev_nb);
+ }
+
+ return 0;
+}
+static int ns2_drd_phy_probe(struct platform_device *pdev)
+{
+ struct phy_provider *phy_provider;
+ struct device *dev = &pdev->dev;
+ struct ns2_phy_driver *driver;
+ struct ns2_phy_data *data;
+ struct resource *res;
+ int ret;
+ u32 val;
+
+ driver = devm_kzalloc(dev, sizeof(struct ns2_phy_driver),
+ GFP_KERNEL);
+ if (!driver)
+ return -ENOMEM;
+
+ driver->data = devm_kzalloc(dev, sizeof(struct ns2_phy_data),
+ GFP_KERNEL);
+ if (!driver->data)
+ return -ENOMEM;
+
+ spin_lock_init(&driver->lock);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "icfg");
+ driver->icfgdrd_regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(driver->icfgdrd_regs))
+ return PTR_ERR(driver->icfgdrd_regs);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rst-ctrl");
+ driver->idmdrd_rst_ctrl = devm_ioremap_resource(dev, res);
+ if (IS_ERR(driver->idmdrd_rst_ctrl))
+ return PTR_ERR(driver->idmdrd_rst_ctrl);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crmu-ctrl");
+ driver->crmu_usb2_ctrl = devm_ioremap_resource(dev, res);
+ if (IS_ERR(driver->crmu_usb2_ctrl))
+ return PTR_ERR(driver->crmu_usb2_ctrl);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "usb2-strap");
+ driver->usb2h_strap_reg = devm_ioremap_resource(dev, res);
+ if (IS_ERR(driver->usb2h_strap_reg))
+ return PTR_ERR(driver->usb2h_strap_reg);
+
+ /* create extcon */
+ driver->id_gpiod = devm_gpiod_get(&pdev->dev, "id", GPIOD_IN);
+ if (IS_ERR(driver->id_gpiod)) {
+ dev_err(dev, "failed to get ID GPIO\n");
+ return PTR_ERR(driver->id_gpiod);
+ }
+ driver->vbus_gpiod = devm_gpiod_get(&pdev->dev, "vbus", GPIOD_IN);
+ if (IS_ERR(driver->vbus_gpiod)) {
+ dev_err(dev, "failed to get VBUS GPIO\n");
+ return PTR_ERR(driver->vbus_gpiod);
+ }
+
+ driver->edev = devm_extcon_dev_allocate(dev, usb_extcon_cable);
+ if (IS_ERR(driver->edev)) {
+ dev_err(dev, "failed to allocate extcon device\n");
+ return -ENOMEM;
+ }
+
+ ret = devm_extcon_dev_register(dev, driver->edev);
+ if (ret < 0) {
+ dev_err(dev, "failed to register extcon device\n");
+ goto extcon_free;
+ }
+
+ ret = gpiod_set_debounce(driver->id_gpiod, GPIO_DELAY * 1000);
+ if (ret < 0)
+ driver->debounce_jiffies = msecs_to_jiffies(GPIO_DELAY);
+
+ INIT_DELAYED_WORK(&driver->wq_extcon, extcon_work);
+
+ driver->id_irq = gpiod_to_irq(driver->id_gpiod);
+ if (driver->id_irq < 0) {
+ dev_err(dev, "failed to get ID IRQ\n");
+ ret = driver->id_irq;
+ goto extcon_unregister;
+ }
+ driver->vbus_irq = gpiod_to_irq(driver->vbus_gpiod);
+ if (driver->vbus_irq < 0) {
+ dev_err(dev, "failed to get ID IRQ\n");
+ ret = driver->vbus_irq;
+ goto extcon_unregister;
+ }
+
+ ret = devm_request_threaded_irq(dev, driver->id_irq, NULL,
+ gpio_irq_handler,
+ IRQF_TRIGGER_RISING |
+ IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
+ "usb_id", driver);
+ if (ret < 0) {
+ dev_err(dev, "failed to request handler for ID IRQ\n");
+ goto extcon_unregister;
+ }
+ ret = devm_request_threaded_irq(dev, driver->vbus_irq, NULL,
+ gpio_irq_handler,
+ IRQF_TRIGGER_RISING |
+ IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
+ "usb_vbus", driver);
+ if (ret < 0) {
+ dev_err(dev, "failed to request handler for VBUS IRQ\n");
+ goto extcon_unregister;
+ }
+
+ dev_set_drvdata(dev, driver);
+ driver->host_mode = 0;
+
+ /* Shutdown all ports. They can be powered up as required */
+ val = readl(driver->crmu_usb2_ctrl);
+ val &= ~(AFE_CORERDY_VDDC | PHY_RESETB);
+ writel(val, driver->crmu_usb2_ctrl);
+
+ data = driver->data;
+ data->phy = devm_phy_create(dev, dev->of_node, &ops);
+ if (IS_ERR(data->phy)) {
+ dev_err(dev, "Failed to create usb drd phy\n");
+ ret = PTR_ERR(data->phy);
+ goto extcon_unregister;
+ }
+
+ data->driver = driver;
+ data->poweron = 0;
+ phy_set_drvdata(data->phy, data);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(phy_provider)) {
+ dev_err(dev, "Failed to register as phy provider\n");
+ ret = PTR_ERR(phy_provider);
+ goto extcon_unregister;
+ }
+
+ INIT_DELAYED_WORK(&driver->conn_work, connect_work);
+ platform_set_drvdata(pdev, driver);
+
+ ret = register_extcon_notifier(driver, dev);
+ if (ret < 0) {
+ dev_err(dev, "register extcon notifier failed (%d)\n", ret);
+ goto extcon_unregister;
+ }
+ dev_info(dev, "Registered %s\n", driver->edev->name);
+ queue_delayed_work(system_power_efficient_wq, &driver->wq_extcon,
+ driver->debounce_jiffies);
+
+ return 0;
+
+extcon_unregister:
+ devm_extcon_dev_unregister(dev, driver->edev);
+extcon_free:
+ devm_extcon_dev_free(dev, driver->edev);
+ return ret;
+}
+
+MODULE_DEVICE_TABLE(of, ns2_drd_phy_dt_ids);
+
+static struct platform_driver ns2_drd_phy_driver = {
+ .probe = ns2_drd_phy_probe,
+ .remove = ns2_drd_phy_remove,
+ .driver = {
+ .name = "bcm-ns2-usbphy",
+ .of_match_table = of_match_ptr(ns2_drd_phy_dt_ids),
+ },
+};
+module_platform_driver(ns2_drd_phy_driver);
+
+MODULE_ALIAS("platform:bcm-ns2-drd-phy");
+MODULE_AUTHOR("Broadcom");
+MODULE_DESCRIPTION("Broadcom NS2 USB2 PHY driver");
+MODULE_LICENSE("GPL v2");
--
2.1.0
^ permalink raw reply related
* [PATCH v2 3/3] DT nodes for Broadcom Northstar2 USB DRD Phy
From: Raviteja Garimella @ 2017-01-18 12:20 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kishon Vijay Abraham I, Ray Jui,
Scott Branden, Jon Mason, Catalin Marinas, Will Deacon
Cc: devicetree, bcm-kernel-feedback-list, linux-kernel,
linux-arm-kernel
In-Reply-To: <1484742004-6792-1-git-send-email-raviteja.garimella@broadcom.com>
This patch adds device tree nodes for USB Dual Role Device Phy for
Broadcom's Northstar2 SoC.
Signed-off-by: Raviteja Garimella <raviteja.garimella@broadcom.com>
---
arch/arm64/boot/dts/broadcom/ns2.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index 4fcdeca..d9f701c 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -353,6 +353,20 @@
};
};
+ usbdrd_phy: phy@66000960 {
+ #phy-cells = <0>;
+ compatible = "brcm,ns2-drd-phy";
+ reg = <0x66000960 0x24>,
+ <0x67012800 0x4>,
+ <0x6501d148 0x4>,
+ <0x664d0700 0x4>;
+ reg-names = "icfg", "rst-ctrl",
+ "crmu-ctrl", "usb2-strap";
+ id-gpios = <&gpio_g 30 0>;
+ vbus-gpios = <&gpio_g 31 0>;
+ status = "disabled";
+ };
+
pwm: pwm@66010000 {
compatible = "brcm,iproc-pwm";
reg = <0x66010000 0x28>;
--
2.1.0
^ permalink raw reply related
* Re: [PATCH v2 05/12] Document: dt: binding: imx: update pinctrl doc for imx6sll
From: Linus Walleij @ 2017-01-18 12:24 UTC (permalink / raw)
To: Jacky Bai
Cc: Mark Rutland, devicetree@vger.kernel.org, Philipp Zabel,
Michael Turquette, Daniel Lezcano, Stephen Boyd,
linux-gpio@vger.kernel.org, Rob Herring, Sascha Hauer,
jacky.baip@gmail.com, Fabio Estevam, Thomas Gleixner, Shawn Guo,
linux-clk, linux-arm-kernel@lists.infradead.org
In-Reply-To: <AM3PR04MB530F532D867C08824DADDC9877C0@AM3PR04MB530.eurprd04.prod.outlook.com>
On Tue, Jan 17, 2017 at 7:35 AM, Jacky Bai <ping.bai@nxp.com> wrote:
>> Subject: Re: [PATCH v2 05/12] Document: dt: binding: imx: update pinctrl doc
>> On Thu, Jan 12, 2017 at 3:57 AM, Jacky Bai <ping.bai@nxp.com> wrote:
>>
>> > Another thing is that we can use a pins-tool program developed by NXP
>> > to generate the pinctrl configuration code that can be used directly
>> > in dts. This tiny program can avoid pin function conflict. As on i.MX,
>> > there are so may pins, each pin can be used for up 8 function.
>> > Configuring the pins is a time-consuming work. This tools is very useful for
>> customer to generate the dts code.
>>
>> I understand, but every silicon vendor has such a tool, all are different,
>> proprietary and unfriendly to programmers and open source developers, who
>> need to understand how the hardware is working without magic tools and
>> secret data sheets to fix bugs.
>>
>> For the people working with maintaining the code it is paramount that DTS files
>> are self-descriptive.
>
> OK. Thanks for your comments. Adding generic-pinconf in imx pinctrl needs some time
> to finish and the legacy method still need be here even if generic-pinconf is added.
> Do you plan to pick this legacy binding patch for now?
As I said earlier:
> atleast I need an indication from one of the i.MX maintainers how they
> want to proceed.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 1/2] pinctrl: meson: Add HDMI HPD/DDC pins functions
From: Linus Walleij @ 2017-01-18 12:27 UTC (permalink / raw)
To: Neil Armstrong
Cc: Kevin Hilman, Carlo Caione, open list:ARM/Amlogic Meson...,
linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <1484654738-5496-2-git-send-email-narmstrong@baylibre.com>
On Tue, Jan 17, 2017 at 1:05 PM, Neil Armstrong <narmstrong@baylibre.com> wrote:
> Add pinctrl functions for HDMI HPD pin and DDC pins on Amlogic Meson
> GXL and GXBB SoCs.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 2/2] ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes
From: Linus Walleij @ 2017-01-18 12:28 UTC (permalink / raw)
To: Neil Armstrong
Cc: Kevin Hilman, Carlo Caione, open list:ARM/Amlogic Meson...,
linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <1484654738-5496-3-git-send-email-narmstrong@baylibre.com>
On Tue, Jan 17, 2017 at 1:05 PM, Neil Armstrong <narmstrong@baylibre.com> wrote:
> Add pinctrl nodes for HDMI HPD and DDC pins modes for Amlogic Meson GXL
> and GXBB SoCs.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Please merge this through ARM SoC.
Yours,
Linus Walleij
^ permalink raw reply
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