* [PATCH v3 1/7] NFC: trf7970a: Don't de-assert EN2 unless it was asserted
From: Mark Greer @ 2017-01-20 19:17 UTC (permalink / raw)
To: Samuel Ortiz, Lauro Ramos Venancio, Aloisio Almeida Jr
Cc: linux-nfc-hn68Rpc1hR1g9hUCZPvPmw,
devicetree-u79uwXL29TY76Z2rM5mHXA, Mark Greer
In-Reply-To: <20170120191745.29255-1-mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
When the trf7970a part has the bug related to 'en2-rf-quirk',
the GPIO connected to the EN2 pin will not be asserted by the
driver when powering up so it shouldn't be de-asserted when
powering down.
Signed-off-by: Mark Greer <mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
---
drivers/nfc/trf7970a.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/nfc/trf7970a.c b/drivers/nfc/trf7970a.c
index 26c9dbbccb0c..92f3cf3e012a 100644
--- a/drivers/nfc/trf7970a.c
+++ b/drivers/nfc/trf7970a.c
@@ -1914,7 +1914,9 @@ static int trf7970a_power_down(struct trf7970a *trf)
}
gpio_set_value(trf->en_gpio, 0);
- gpio_set_value(trf->en2_gpio, 0);
+
+ if (!(trf->quirks & TRF7970A_QUIRK_EN2_MUST_STAY_LOW))
+ gpio_set_value(trf->en2_gpio, 0);
ret = regulator_disable(trf->regulator);
if (ret)
--
2.11.0
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^ permalink raw reply related
* [PATCH v3 2/7] NFC: trf7970a: Don't manage EN2 when not specified in DT
From: Mark Greer @ 2017-01-20 19:17 UTC (permalink / raw)
To: Samuel Ortiz, Lauro Ramos Venancio, Aloisio Almeida Jr
Cc: linux-nfc-hn68Rpc1hR1g9hUCZPvPmw,
devicetree-u79uwXL29TY76Z2rM5mHXA, Mark Greer
In-Reply-To: <20170120191745.29255-1-mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
Currently, the trf7970a driver assumes that there is a GPIO
connected to the EN2 pin of the trf7970a part; however, that
may not always be the case. Some boards may tie EN2 low and
not connect it to a GPIO. Support these configurations by making
the driver ignore EN2 when the second entry in the 'ti,enable-gpios'
DT property is missing (i.e., the one that specifies the GPIO for
EN2).
Signed-off-by: Mark Greer <mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
---
drivers/nfc/trf7970a.c | 32 +++++++++++++++++---------------
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/nfc/trf7970a.c b/drivers/nfc/trf7970a.c
index 92f3cf3e012a..0c0567adefcb 100644
--- a/drivers/nfc/trf7970a.c
+++ b/drivers/nfc/trf7970a.c
@@ -1884,7 +1884,8 @@ static int trf7970a_power_up(struct trf7970a *trf)
usleep_range(5000, 6000);
- if (!(trf->quirks & TRF7970A_QUIRK_EN2_MUST_STAY_LOW)) {
+ if (gpio_is_valid(trf->en2_gpio) &&
+ !(trf->quirks & TRF7970A_QUIRK_EN2_MUST_STAY_LOW)) {
gpio_set_value(trf->en2_gpio, 1);
usleep_range(1000, 2000);
}
@@ -1915,7 +1916,8 @@ static int trf7970a_power_down(struct trf7970a *trf)
gpio_set_value(trf->en_gpio, 0);
- if (!(trf->quirks & TRF7970A_QUIRK_EN2_MUST_STAY_LOW))
+ if (gpio_is_valid(trf->en2_gpio) &&
+ !(trf->quirks & TRF7970A_QUIRK_EN2_MUST_STAY_LOW))
gpio_set_value(trf->en2_gpio, 0);
ret = regulator_disable(trf->regulator);
@@ -2018,7 +2020,7 @@ static int trf7970a_probe(struct spi_device *spi)
if (of_property_read_bool(np, "irq-status-read-quirk"))
trf->quirks |= TRF7970A_QUIRK_IRQ_STATUS_READ;
- /* There are two enable pins - both must be present */
+ /* There are two enable pins - only EN must be present in DT */
trf->en_gpio = of_get_named_gpio(np, "ti,enable-gpios", 0);
if (!gpio_is_valid(trf->en_gpio)) {
dev_err(trf->dev, "No EN GPIO property\n");
@@ -2033,21 +2035,21 @@ static int trf7970a_probe(struct spi_device *spi)
}
trf->en2_gpio = of_get_named_gpio(np, "ti,enable-gpios", 1);
- if (!gpio_is_valid(trf->en2_gpio)) {
- dev_err(trf->dev, "No EN2 GPIO property\n");
- return trf->en2_gpio;
- }
+ if (gpio_is_valid(trf->en2_gpio)) {
+ ret = devm_gpio_request_one(trf->dev, trf->en2_gpio,
+ GPIOF_DIR_OUT | GPIOF_INIT_LOW,
+ "trf7970a EN2");
+ if (ret) {
+ dev_err(trf->dev, "Can't request EN2 GPIO: %d\n", ret);
+ return ret;
+ }
- ret = devm_gpio_request_one(trf->dev, trf->en2_gpio,
- GPIOF_DIR_OUT | GPIOF_INIT_LOW, "trf7970a EN2");
- if (ret) {
- dev_err(trf->dev, "Can't request EN2 GPIO: %d\n", ret);
- return ret;
+ if (of_property_read_bool(np, "en2-rf-quirk"))
+ trf->quirks |= TRF7970A_QUIRK_EN2_MUST_STAY_LOW;
+ } else {
+ dev_err(trf->dev, "No EN2 GPIO property - ignoring EN2\n");
}
- if (of_property_read_bool(np, "en2-rf-quirk"))
- trf->quirks |= TRF7970A_QUIRK_EN2_MUST_STAY_LOW;
-
ret = devm_request_threaded_irq(trf->dev, spi->irq, NULL,
trf7970a_irq, IRQF_TRIGGER_RISING | IRQF_ONESHOT,
"trf7970a", trf);
--
2.11.0
--
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* [PATCH v3 3/7] NFC: trf7970a: Convert to descriptor based GPIO interface
From: Mark Greer @ 2017-01-20 19:17 UTC (permalink / raw)
To: Samuel Ortiz, Lauro Ramos Venancio, Aloisio Almeida Jr
Cc: linux-nfc-hn68Rpc1hR1g9hUCZPvPmw,
devicetree-u79uwXL29TY76Z2rM5mHXA, Mark Greer
In-Reply-To: <20170120191745.29255-1-mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
The trf7970a driver uses the deprecated integer-based GPIO consumer
interface so convert it to use the new descriptor-based GPIO
consumer interface.
Signed-off-by: Mark Greer <mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
---
drivers/nfc/Kconfig | 2 +-
drivers/nfc/trf7970a.c | 54 ++++++++++++++++++++------------------------------
2 files changed, 23 insertions(+), 33 deletions(-)
diff --git a/drivers/nfc/Kconfig b/drivers/nfc/Kconfig
index 9d2369269abf..4deacbada74d 100644
--- a/drivers/nfc/Kconfig
+++ b/drivers/nfc/Kconfig
@@ -18,7 +18,7 @@ config NFC_WILINK
config NFC_TRF7970A
tristate "Texas Instruments TRF7970a NFC driver"
- depends on SPI && NFC_DIGITAL
+ depends on SPI && NFC_DIGITAL && GPIOLIB
help
This option enables the NFC driver for Texas Instruments' TRF7970a
device. Such device supports 5 different protocols: ISO14443A,
diff --git a/drivers/nfc/trf7970a.c b/drivers/nfc/trf7970a.c
index 0c0567adefcb..bd3d9a09da0d 100644
--- a/drivers/nfc/trf7970a.c
+++ b/drivers/nfc/trf7970a.c
@@ -20,9 +20,8 @@
#include <linux/nfc.h>
#include <linux/skbuff.h>
#include <linux/delay.h>
-#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
#include <linux/of.h>
-#include <linux/of_gpio.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
@@ -448,8 +447,8 @@ struct trf7970a {
u8 tx_cmd;
bool issue_eof;
bool adjust_resp_len;
- int en2_gpio;
- int en_gpio;
+ struct gpio_desc *en_gpiod;
+ struct gpio_desc *en2_gpiod;
struct mutex lock;
unsigned int timeout;
bool ignore_timeout;
@@ -1884,13 +1883,13 @@ static int trf7970a_power_up(struct trf7970a *trf)
usleep_range(5000, 6000);
- if (gpio_is_valid(trf->en2_gpio) &&
+ if (trf->en2_gpiod &&
!(trf->quirks & TRF7970A_QUIRK_EN2_MUST_STAY_LOW)) {
- gpio_set_value(trf->en2_gpio, 1);
+ gpiod_set_value_cansleep(trf->en2_gpiod, 1);
usleep_range(1000, 2000);
}
- gpio_set_value(trf->en_gpio, 1);
+ gpiod_set_value_cansleep(trf->en_gpiod, 1);
usleep_range(20000, 21000);
@@ -1914,11 +1913,11 @@ static int trf7970a_power_down(struct trf7970a *trf)
return -EBUSY;
}
- gpio_set_value(trf->en_gpio, 0);
+ gpiod_set_value_cansleep(trf->en_gpiod, 0);
- if (gpio_is_valid(trf->en2_gpio) &&
+ if (trf->en2_gpiod &&
!(trf->quirks & TRF7970A_QUIRK_EN2_MUST_STAY_LOW))
- gpio_set_value(trf->en2_gpio, 0);
+ gpiod_set_value_cansleep(trf->en2_gpiod, 0);
ret = regulator_disable(trf->regulator);
if (ret)
@@ -2021,33 +2020,24 @@ static int trf7970a_probe(struct spi_device *spi)
trf->quirks |= TRF7970A_QUIRK_IRQ_STATUS_READ;
/* There are two enable pins - only EN must be present in DT */
- trf->en_gpio = of_get_named_gpio(np, "ti,enable-gpios", 0);
- if (!gpio_is_valid(trf->en_gpio)) {
+ trf->en_gpiod = devm_gpiod_get_index(trf->dev, "ti,enable", 0,
+ GPIOD_OUT_LOW);
+ if (IS_ERR(trf->en_gpiod)) {
dev_err(trf->dev, "No EN GPIO property\n");
- return trf->en_gpio;
+ return PTR_ERR(trf->en_gpiod);
}
- ret = devm_gpio_request_one(trf->dev, trf->en_gpio,
- GPIOF_DIR_OUT | GPIOF_INIT_LOW, "trf7970a EN");
- if (ret) {
- dev_err(trf->dev, "Can't request EN GPIO: %d\n", ret);
- return ret;
- }
-
- trf->en2_gpio = of_get_named_gpio(np, "ti,enable-gpios", 1);
- if (gpio_is_valid(trf->en2_gpio)) {
- ret = devm_gpio_request_one(trf->dev, trf->en2_gpio,
- GPIOF_DIR_OUT | GPIOF_INIT_LOW,
- "trf7970a EN2");
- if (ret) {
- dev_err(trf->dev, "Can't request EN2 GPIO: %d\n", ret);
- return ret;
- }
-
+ trf->en2_gpiod = devm_gpiod_get_index_optional(trf->dev, "ti,enable", 1,
+ GPIOD_OUT_LOW);
+ if (!trf->en2_gpiod) {
+ dev_err(trf->dev, "No EN2 GPIO property - ignoring EN2\n");
+ } else if (IS_ERR(trf->en2_gpiod)) {
+ dev_err(trf->dev, "Error getting EN2 GPIO property: %ld\n",
+ PTR_ERR(trf->en2_gpiod));
+ return PTR_ERR(trf->en2_gpiod);
+ } else {
if (of_property_read_bool(np, "en2-rf-quirk"))
trf->quirks |= TRF7970A_QUIRK_EN2_MUST_STAY_LOW;
- } else {
- dev_err(trf->dev, "No EN2 GPIO property - ignoring EN2\n");
}
ret = devm_request_threaded_irq(trf->dev, spi->irq, NULL,
--
2.11.0
--
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^ permalink raw reply related
* [PATCH v3 4/7] NFC: trf7970a: Remove useless comment
From: Mark Greer @ 2017-01-20 19:17 UTC (permalink / raw)
To: Samuel Ortiz, Lauro Ramos Venancio, Aloisio Almeida Jr
Cc: linux-nfc-hn68Rpc1hR1g9hUCZPvPmw,
devicetree-u79uwXL29TY76Z2rM5mHXA, Mark Greer
In-Reply-To: <20170120191745.29255-1-mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
The last entry in the trf7970a_of_match[] table must be an empty
entry to demarcate the end of the table. Currently, there is a
comment indicating this but it is obvious so remove the comment.
Signed-off-by: Mark Greer <mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
---
drivers/nfc/trf7970a.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/nfc/trf7970a.c b/drivers/nfc/trf7970a.c
index bd3d9a09da0d..6fd85be49365 100644
--- a/drivers/nfc/trf7970a.c
+++ b/drivers/nfc/trf7970a.c
@@ -2211,7 +2211,7 @@ static const struct dev_pm_ops trf7970a_pm_ops = {
static const struct of_device_id trf7970a_of_match[] = {
{ .compatible = "ti,trf7970a", },
- { /* sentinel */ },
+ {},
};
MODULE_DEVICE_TABLE(of, trf7970a_of_match);
--
2.11.0
--
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^ permalink raw reply related
* [PATCH v3 5/7] NFC: trf7970a: Remove support for 'vin-voltage-override' DT property
From: Mark Greer @ 2017-01-20 19:17 UTC (permalink / raw)
To: Samuel Ortiz, Lauro Ramos Venancio, Aloisio Almeida Jr
Cc: linux-nfc-hn68Rpc1hR1g9hUCZPvPmw,
devicetree-u79uwXL29TY76Z2rM5mHXA, Mark Greer
In-Reply-To: <20170120191745.29255-1-mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
The 'vin-voltage-override' DT property is used by the trf7970a
driver to override the voltage presented to the driver by the
regulator subsystem. This is unnecessary as properly specifying
the regulator chain via DT properties will accomplish the same
thing. Therefore, remove support for 'vin-voltage-override'.
Signed-off-by: Mark Greer <mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
---
Documentation/devicetree/bindings/net/nfc/trf7970a.txt | 2 --
drivers/nfc/trf7970a.c | 11 +----------
2 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt
index 32b35a07abe4..07008d334536 100644
--- a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt
+++ b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt
@@ -13,7 +13,6 @@ Optional SoC Specific Properties:
- pinctrl-names: Contains only one value - "default".
- pintctrl-0: Specifies the pin control groups used for this controller.
- autosuspend-delay: Specify autosuspend delay in milliseconds.
-- vin-voltage-override: Specify voltage of VIN pin in microvolts.
- irq-status-read-quirk: Specify that the trf7970a being used has the
"IRQ Status Read" erratum.
- en2-rf-quirk: Specify that the trf7970a being used has the "EN2 RF"
@@ -38,7 +37,6 @@ Example (for ARM-based BeagleBone with TRF7970A on SPI1):
ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>,
<&gpio2 5 GPIO_ACTIVE_LOW>;
vin-supply = <&ldo3_reg>;
- vin-voltage-override = <5000000>;
autosuspend-delay = <30000>;
irq-status-read-quirk;
en2-rf-quirk;
diff --git a/drivers/nfc/trf7970a.c b/drivers/nfc/trf7970a.c
index 6fd85be49365..bc3c71daaea5 100644
--- a/drivers/nfc/trf7970a.c
+++ b/drivers/nfc/trf7970a.c
@@ -1979,12 +1979,6 @@ static int trf7970a_get_autosuspend_delay(struct device_node *np)
return autosuspend_delay;
}
-static int trf7970a_get_vin_voltage_override(struct device_node *np,
- u32 *vin_uvolts)
-{
- return of_property_read_u32(np, "vin-voltage-override", vin_uvolts);
-}
-
static int trf7970a_probe(struct spi_device *spi)
{
struct device_node *np = spi->dev.of_node;
@@ -2064,10 +2058,7 @@ static int trf7970a_probe(struct spi_device *spi)
goto err_destroy_lock;
}
- ret = trf7970a_get_vin_voltage_override(np, &uvolts);
- if (ret)
- uvolts = regulator_get_voltage(trf->regulator);
-
+ uvolts = regulator_get_voltage(trf->regulator);
if (uvolts > 4000000)
trf->chip_status_ctrl = TRF7970A_CHIP_STATUS_VRS5_3;
--
2.11.0
--
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^ permalink raw reply related
* [PATCH v3 6/7] NFC: trf7970a: Enable pins are active high not active low
From: Mark Greer @ 2017-01-20 19:17 UTC (permalink / raw)
To: Samuel Ortiz, Lauro Ramos Venancio, Aloisio Almeida Jr
Cc: linux-nfc-hn68Rpc1hR1g9hUCZPvPmw,
devicetree-u79uwXL29TY76Z2rM5mHXA, Mark Greer
In-Reply-To: <20170120191745.29255-1-mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
The example DTS code for the trf7970a sets the GPIOs for the EN
and EN2 pins to active low when they are really active high so
correct the error.
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Mark Greer <mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
---
Documentation/devicetree/bindings/net/nfc/trf7970a.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt
index 07008d334536..28e9247d8a97 100644
--- a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt
+++ b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt
@@ -34,8 +34,8 @@ Example (for ARM-based BeagleBone with TRF7970A on SPI1):
spi-max-frequency = <2000000>;
interrupt-parent = <&gpio2>;
interrupts = <14 0>;
- ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>,
- <&gpio2 5 GPIO_ACTIVE_LOW>;
+ ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>,
+ <&gpio2 5 GPIO_ACTIVE_HIGH>;
vin-supply = <&ldo3_reg>;
autosuspend-delay = <30000>;
irq-status-read-quirk;
--
2.11.0
--
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^ permalink raw reply related
* [PATCH v3 7/7] MAINTAINERS: NFC: trf7970a: Add Mark Greer as maintainer
From: Mark Greer @ 2017-01-20 19:17 UTC (permalink / raw)
To: Samuel Ortiz, Lauro Ramos Venancio, Aloisio Almeida Jr
Cc: linux-nfc-hn68Rpc1hR1g9hUCZPvPmw,
devicetree-u79uwXL29TY76Z2rM5mHXA, Mark Greer
In-Reply-To: <20170120191745.29255-1-mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
Add Mark Greer as the maintainer of the trf7970a NFC driver.
Signed-off-by: Mark Greer <mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 26edd832c64e..5622d190ae1d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10902,6 +10902,13 @@ F: include/linux/power/bq27xxx_battery.h
F: drivers/power/supply/bq27xxx_battery.c
F: drivers/power/supply/bq27xxx_battery_i2c.c
+TI TRF7970A NFC DRIVER
+M: Mark Greer <mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
+L: linux-nfc-hn68Rpc1hR1g9hUCZPvPmw@public.gmane.org (moderated for non-subscribers)
+S: Supported
+F: drivers/nfc/trf7970a.c
+F: Documentation/devicetree/bindings/net/nfc/trf7970a.txt
+
TIMEKEEPING, CLOCKSOURCE CORE, NTP, ALARMTIMER
M: John Stultz <john.stultz-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
M: Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
--
2.11.0
--
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^ permalink raw reply related
* [PATCH v4 0/3] mmc: sh_mobile_sdhi: fix missing r7s72100 clocks
From: Chris Brandt @ 2017-01-20 19:43 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Mark Rutland, Simon Horman,
Wolfram Sang, Geert Uytterhoeven
Cc: devicetree, linux-mmc, linux-renesas-soc, Chris Brandt
At first this started out as a simple typo fix, until I realized
that the SDHI in the RZ/A1 has 2 clocks per channel and both need
to be turned on/off.
This patch series adds the ability to specify 2 clocks instead of
just 1, and does so for the RZ/A1 r7s72100.
This patch has been tested on an RZ/A1 RSK board. Card detect works
fine as well as bind/unbind.
v4:
* No code changes, only text udpates to explain why there are 2 clocks
and why we need to treat them as 1 clock.
Chris Brandt (3):
mmc: sh_mobile_sdhi: add support for 2 clocks
mmc: sh_mobile_sdhi: explain clock bindings
ARM: dts: r7s72100: update sdhi clock bindings
Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 28 ++++++++++++++++++++++
arch/arm/boot/dts/r7s72100.dtsi | 17 +++++++++----
drivers/mmc/host/sh_mobile_sdhi.c | 13 ++++++++++
include/dt-bindings/clock/r7s72100-clock.h | 6 +++--
4 files changed, 57 insertions(+), 7 deletions(-)
--
2.10.1
^ permalink raw reply
* [PATCH v4 1/3] mmc: sh_mobile_sdhi: add support for 2 clocks
From: Chris Brandt @ 2017-01-20 19:43 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Mark Rutland, Simon Horman,
Wolfram Sang, Geert Uytterhoeven
Cc: devicetree, linux-mmc, linux-renesas-soc, Chris Brandt
In-Reply-To: <20170120194332.1683-1-chris.brandt@renesas.com>
Some controllers have 2 clock sources instead of 1. The 2nd clock
is for the internal card detect logic and must be enabled/disabled
along with the main core clock for proper operation.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
v3:
* add more clarification to the commit log
v2:
* changed clk2 to clk_cd
* disable clk if clk_cd enable fails
* changed clock name from "carddetect" to "cd"
---
drivers/mmc/host/sh_mobile_sdhi.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c
index 59db14b..a3f995e 100644
--- a/drivers/mmc/host/sh_mobile_sdhi.c
+++ b/drivers/mmc/host/sh_mobile_sdhi.c
@@ -143,6 +143,7 @@ MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_of_match);
struct sh_mobile_sdhi {
struct clk *clk;
+ struct clk *clk_cd;
struct tmio_mmc_data mmc_data;
struct tmio_mmc_dma dma_priv;
struct pinctrl *pinctrl;
@@ -190,6 +191,12 @@ static int sh_mobile_sdhi_clk_enable(struct tmio_mmc_host *host)
if (ret < 0)
return ret;
+ ret = clk_prepare_enable(priv->clk_cd);
+ if (ret < 0) {
+ clk_disable_unprepare(priv->clk);
+ return ret;
+ }
+
/*
* The clock driver may not know what maximum frequency
* actually works, so it should be set with the max-frequency
@@ -255,6 +262,8 @@ static void sh_mobile_sdhi_clk_disable(struct tmio_mmc_host *host)
struct sh_mobile_sdhi *priv = host_to_priv(host);
clk_disable_unprepare(priv->clk);
+ if (priv->clk_cd)
+ clk_disable_unprepare(priv->clk_cd);
}
static int sh_mobile_sdhi_card_busy(struct mmc_host *mmc)
@@ -572,6 +581,10 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev)
goto eprobe;
}
+ priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
+ if (IS_ERR(priv->clk_cd))
+ priv->clk_cd = NULL;
+
priv->pinctrl = devm_pinctrl_get(&pdev->dev);
if (!IS_ERR(priv->pinctrl)) {
priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
--
2.10.1
^ permalink raw reply related
* [PATCH v4 2/3] mmc: sh_mobile_sdhi: explain clock bindings
From: Chris Brandt @ 2017-01-20 19:43 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Mark Rutland, Simon Horman,
Wolfram Sang, Geert Uytterhoeven
Cc: devicetree, linux-mmc, linux-renesas-soc, Chris Brandt
In-Reply-To: <20170120194332.1683-1-chris.brandt@renesas.com>
In the case of a single clock source, you don't need names. However,
if the controller has 2 clock sources, you need to name them correctly
so the driver can find the 2nd one. The 2nd clock is for the internal
card detect logic and must be enabled/disabled along with the main
core clock.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
v3:
* add more clarification about why there are sometimes 2 clocks
and what you should do with them.
* remove 'status = "disabled"' from example
v2:
* fix spelling and change wording
* changed clock name from "carddetect" to "cd"
---
Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
index a1650ed..9033c6a 100644
--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
@@ -25,8 +25,36 @@ Required properties:
"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
+- clocks: Most controllers only have 1 clock source per channel. However, on
+ some variations of this controller, the internal card detection
+ logic that exists in this controller is sectioned off to be run by a
+ separate second clock source to allow the main core clock to be turned
+ off to save power. Unfortunately, the existing driver architecture
+ does not support such a separation of clocks.
+ Additionally, it is prohibited to supply a clock to the core but not
+ to the card detect circuit. That leaves you with if separate clocks
+ are presented, you must treat them both as 1.
+ If 2 clocks are specified by the hardware, you must name them as
+ "core" and "cd".
+ If the controller only has 1 clock, naming is not required.
+
Optional properties:
- toshiba,mmc-wrprotect-disable: write-protect detection is unavailable
- pinctrl-names: should be "default", "state_uhs"
- pinctrl-0: should contain default/high speed pin ctrl
- pinctrl-1: should contain uhs mode pin ctrl
+
+Example showing 2 clocks:
+ sdhi0: sd@e804e000 {
+ compatible = "renesas,sdhi-r7s72100";
+ reg = <0xe804e000 0x100>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
+ <&mstp12_clks R7S72100_CLK_SDHI01>;
+ clock-names = "core", "cd";
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ };
--
2.10.1
^ permalink raw reply related
* [PATCH v4 3/3] ARM: dts: r7s72100: update sdhi clock bindings
From: Chris Brandt @ 2017-01-20 19:43 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Mark Rutland, Simon Horman,
Wolfram Sang, Geert Uytterhoeven
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Chris Brandt
In-Reply-To: <20170120194332.1683-1-chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
The SDHI controller in the RZ/A1 has 2 clock sources per channel and both
need to be enabled/disabled for proper operation. This fixes the fact that
the define for R7S72100_CLK_SDHI1 was not correct to begin with (typo), and
that all 4 clock sources need to be defined an used.
Signed-off-by: Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
v2:
* add missing clock sources instead of just fixing typo
* changed clock name from "carddetect" to "cd"
---
arch/arm/boot/dts/r7s72100.dtsi | 17 ++++++++++++-----
include/dt-bindings/clock/r7s72100-clock.h | 6 ++++--
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 3dd427d..9d0b8d0 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -153,9 +153,12 @@
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0444 4>;
- clocks = <&p1_clk>, <&p1_clk>;
- clock-indices = <R7S72100_CLK_SDHI1 R7S72100_CLK_SDHI0>;
- clock-output-names = "sdhi1", "sdhi0";
+ clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
+ clock-indices = <
+ R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
+ R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
+ >;
+ clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
};
};
@@ -478,7 +481,9 @@
GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp12_clks R7S72100_CLK_SDHI0>;
+ clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
+ <&mstp12_clks R7S72100_CLK_SDHI01>;
+ clock-names = "core", "cd";
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
@@ -491,7 +496,9 @@
GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp12_clks R7S72100_CLK_SDHI1>;
+ clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
+ <&mstp12_clks R7S72100_CLK_SDHI11>;
+ clock-names = "core", "cd";
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h
index 29e01ed..f2d8428 100644
--- a/include/dt-bindings/clock/r7s72100-clock.h
+++ b/include/dt-bindings/clock/r7s72100-clock.h
@@ -45,7 +45,9 @@
#define R7S72100_CLK_SPI4 3
/* MSTP12 */
-#define R7S72100_CLK_SDHI0 3
-#define R7S72100_CLK_SDHI1 2
+#define R7S72100_CLK_SDHI00 3
+#define R7S72100_CLK_SDHI01 2
+#define R7S72100_CLK_SDHI10 1
+#define R7S72100_CLK_SDHI11 0
#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
--
2.10.1
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^ permalink raw reply related
* Re: [PATCH v3 0/9] meson-gx: reset RGMII PHYs and configure TX delay
From: Kevin Hilman @ 2017-01-20 19:46 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
carlo-KA+7E9HrN00dnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, will.deacon-5wv7dgnIgG8,
catalin.marinas-5wv7dgnIgG8, mark.rutland-5wv7dgnIgG8,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, narmstrong-rdvid1DuHRBWk0Htik3J/w,
jbrunet-rdvid1DuHRBWk0Htik3J/w
In-Reply-To: <CAFBinCBQ8S7-tCnkY+Vabs3etSv-gJCsK=tE+RNJZS8+uFfB=Q@mail.gmail.com>
Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> writes:
> On Fri, Jan 20, 2017 at 4:22 PM, Martin Blumenstingl
> <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> wrote:
>> This series adds the reset GPIOs for the (external) ethernet PHYs on all
>> GXBB boards.
>> Additionally it provides a ethernet PHY node which can be used to specify
>> PHY-specific properties (this may be required if more boards require the
>> "eee-broken-1000t" for the RTL8211F ethernet PHY). To make all board .dts
>> consistent I chose to add the PHY node also for boards which don't have a
>> RTL8211F PHY.
>>
>> Patch #7 from this series also removes ethernet support for the P200
>> board because it was broken anyways and nobody seems to have a board
>> available for testing. This was the outcome of the discussion from [0]
>>
>> Patch #8 was taken from (older versions of) my other series (see [1]):
>> "[PATCH net-next v3 0/2] stmmac: dwmac-meson8b: configurable
>> RGMII TX delay".
>> The binding changes for amlogic,tx-delay-ns were ACK'ed already.
>>
>> Changes since v2:
>> - fixed patch #2 to really update the P200 board (as it's the P200 which
>> actually uses a Micrel KSZ9031 RGMII PHY). Thanks to Neil Armstrong for
>> spotting this huge mistake!
>> - instead of dropping ethernet support for P201 we simply re-configure it
>> to RMII mode (replaces patch #7) without a MDIO node (which keeps PHY
>> auto-scanning enabled). This got Neil Armstrong's ACK off-list already
>>
>> Changes since v1:
>> - do not move the MDIO bus to meson-gx as this disables PHY auto-scanning
>> in the stmmac driver (this drops patch #1 from v1)
>> - add the ethernet PHY reset GPIO for nexbox a95x which was forgotten in
>> v1
>> - add the ethernet PHY reset GPIO for boards which were added since v1
>> (wetek hub and wetek play2)
>> - rebased to apply against the current v4.11/dt64 branch
>> - new in v2 (patch #7): disabled ethernet support for the P200 board (see
>> the commit description for more information). this patch is optional
>> - new in v2 (patch #9): removed the phy-mode property from meson-gx (see
>> the commit description for more information). this patch is optional
>>
>>
>> [0] http://lists.infradead.org/pipermail/linux-amlogic/2017-January/002053.html
>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2016-December/001834.html
>>
>> Martin Blumenstingl (9):
>> ARM64: dts: meson-gxbb-odroidc2: add the ethernet PHY's reset GPIO
>> ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO
>> ARM64: dts: meson-gxbb-vega-s95: add the ethernet PHY's reset GPIO
>> ARM64: dts: meson-gxbb-nexbox-a95x: add the ethernet PHY's reset GPIO
>> ARM64: dts: meson-gxbb-wetek-hub: add the ethernet PHY's reset GPIO
>> ARM64: dts: meson-gxbb-wetek-play2: add the ethernet PHY's reset GPIO
>> ARM64: dts: meson-gxbb-p201: fix ethernet support
>> ARM64: dts: amlogic: add the ethernet TX delay configuration
>> ARM64: dts: meson-gx: remove the phy-mode property from meson-gx
>>
>> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 -
>> .../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 17 ++++++++++++++
>> .../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 7 ++++++
>> arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 26 ++++++++++++++++++++++
>> arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts | 11 +++++++++
>> arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 6 -----
>> .../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 20 +++++++++++++++++
>> .../boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 26 ++++++++++++++++++++++
>> .../boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 26 ++++++++++++++++++++++
>> .../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++
>> .../arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 ++
>> arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 2 ++
>> 12 files changed, 139 insertions(+), 7 deletions(-)
> I totally forgot to mention:
> this applies to Kevin's v4.11/dt64 branch with Jerome's Odroid-C2
> ethernet fix [0] applied on top of it
So when Jerome's fix lands in mainline (probably by -rc5, maybe -rc6)
I'll rebase the dt64 branch on that and apply this series.
Kevin
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^ permalink raw reply
* Re: [PATCH v3 1/6] dt-bindings: add device tree binding for Allwinner V3s pinctrl
From: Maxime Ripard @ 2017-01-20 20:24 UTC (permalink / raw)
To: Icenowy Zheng
Cc: devicetree, linux-doc, linux-kernel, linux-gpio, Chen-Yu Tsai,
Rob Herring, linux-clk, linux-arm-kernel
In-Reply-To: <20170119175448.11445-1-icenowy@aosc.xyz>
[-- Attachment #1.1: Type: text/plain, Size: 467 bytes --]
On Fri, Jan 20, 2017 at 01:54:43AM +0800, Icenowy Zheng wrote:
> Allwinner V3s SoC has a pin controller like other Allwinner SoCs and got
> supported by the sunxi-pinctrl driver now.
>
> Add a device tree binding for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH v3 2/6] arm: sunxi: add support for V3s SoC
From: Maxime Ripard @ 2017-01-20 20:29 UTC (permalink / raw)
To: Icenowy Zheng
Cc: devicetree, linux-doc, linux-kernel, linux-gpio, Chen-Yu Tsai,
Rob Herring, linux-clk, linux-arm-kernel
In-Reply-To: <20170119175448.11445-2-icenowy@aosc.xyz>
[-- Attachment #1.1: Type: text/plain, Size: 465 bytes --]
On Fri, Jan 20, 2017 at 01:54:44AM +0800, Icenowy Zheng wrote:
> Allwinner V3s is a low-end single-core Cortex-A7 SoC, with 64MB
> integrated DRAM, and several peripherals.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
This didn't apply. Please make sure to send patches based on my
current branch.
Fixed the conflicts and applied.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH v3 4/6] dt-bindings: add device binding for the CCU of Allwinner V3s
From: Maxime Ripard @ 2017-01-20 20:32 UTC (permalink / raw)
To: Icenowy Zheng
Cc: devicetree, linux-doc, linux-kernel, linux-gpio, Chen-Yu Tsai,
Rob Herring, linux-clk, linux-arm-kernel
In-Reply-To: <20170119175448.11445-4-icenowy@aosc.xyz>
[-- Attachment #1.1: Type: text/plain, Size: 344 bytes --]
On Fri, Jan 20, 2017 at 01:54:46AM +0800, Icenowy Zheng wrote:
> Allwinner V3s is now driven by sunxi-ng CCU driver.
>
> Add devicetree binding for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Applied. Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH v3 3/6] clk: sunxi-ng: add support for V3s CCU
From: Maxime Ripard @ 2017-01-20 20:38 UTC (permalink / raw)
To: Icenowy Zheng
Cc: devicetree, linux-doc, linux-kernel, linux-gpio, Chen-Yu Tsai,
Rob Herring, linux-clk, linux-arm-kernel
In-Reply-To: <20170119175448.11445-3-icenowy@aosc.xyz>
[-- Attachment #1.1: Type: text/plain, Size: 699 bytes --]
On Fri, Jan 20, 2017 at 01:54:45AM +0800, Icenowy Zheng wrote:
> V3s has a similar but cut-down CCU to H3. Some muxes, especially clocks
> about CSI, are different, which makes it to need a new CCU driver.
>
> Add such a new driver for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
Having a changelog somewhere would help. Why did you drop your cover
letter?
> +static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", "pll-ddr" };
This is more that 80 characters and triggers a warning in
checkpatch...
Anyway, fixed and applied.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH v3 00/24] i.MX Media Driver
From: Hans Verkuil @ 2017-01-20 20:39 UTC (permalink / raw)
To: Steve Longerbeam, Philipp Zabel
Cc: mark.rutland, andrew-ct.chen, minghsiu.tsai, nick, songjun.wu,
Steve Longerbeam, robert.jarzmik, devel, markus.heiser,
laurent.pinchart+renesas, linux, geert, linux-media, devicetree,
arnd, mchehab, bparrot, robh+dt, horms+renesas, tiffany.lin,
linux-arm-kernel, niklas.soderlund+renesas, gregkh, linux-kernel,
jean-christophe.trotin, kernel, fabio.estevam, shawnguo,
sudipm.mukherjee
In-Reply-To: <3fb68686-9447-2d8a-e2d2-005e4138cd43@gmail.com>
On 01/20/2017 07:40 PM, Steve Longerbeam wrote:
> Hi Hans, Philipp,
>
>
> On 01/20/2017 08:31 AM, Philipp Zabel wrote:
>> Hi Hans,
>>
>> On Fri, 2017-01-20 at 14:52 +0100, Hans Verkuil wrote:
>>> Hi Steve, Philipp,
>>>
>>> On 01/07/2017 03:11 AM, Steve Longerbeam wrote:
>>>> In version 3:
>>>>
>>>> Changes suggested by Rob Herring <robh@kernel.org>:
>>>>
>>>> - prepended FIM node properties with vendor prefix "fsl,".
>>>>
>>>> - make mipi csi-2 receiver compatible string SoC specific:
>>>> "fsl,imx6-mipi-csi2" instead of "fsl,imx-mipi-csi2".
>>>>
>>>> - redundant "_clk" removed from mipi csi-2 receiver clock-names property.
>>>>
>>>> - removed board-specific info from the media driver binding doc. These
>>>> were all related to sensor bindings, which already are (adv7180)
>>>> or will be (ov564x) covered in separate binding docs. All reference
>>>> board info not related to DT bindings has been moved to
>>>> Documentation/media/v4l-drivers/imx.rst.
>>>>
>>>> - removed "_mipi" from the OV5640 compatible string.
>>>>
>>>> Changes suggested by Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>:
>>>>
>>>> Mostly cosmetic/non-functional changes which I won't list here, except
>>>> for the following:
>>>>
>>>> - spin_lock_irqsave() changed to spin_lock() in a couple interrupt handlers.
>>>>
>>>> - fixed some unnecessary of_node_put()'s in for_each_child_of_node() loops.
>>>>
>>>> - check/handle return code from required reg property of CSI port nodes.
>>>>
>>>> - check/handle return code from clk_prepare_enable().
>>>>
>>>> Changes suggested by Fabio Estevam <festevam@gmail.com>:
>>>>
>>>> - switch to VGEN3 Analog Vdd supply assuming rev. C SabreSD boards.
>>>>
>>>> - finally got around to passing valid IOMUX pin config values to the
>>>> pin groups.
>>>>
>>>> Other changes:
>>>>
>>>> - removed the FIM properties that overrided the v4l2 FIM control defaults
>>>> values. This was left-over from a requirement of a customer and is not
>>>> necessary here.
>>>>
>>>> - The FIM must be explicitly enabled in the fim child node under the CSI
>>>> port nodes, using the status property. If not enabled, FIM v4l2 controls
>>>> will not appear in the video capture driver.
>>>>
>>>> - brought in additional media types patch from Philipp Zabel. Use new
>>>> MEDIA_ENT_F_VID_IF_BRIDGE in mipi csi-2 receiver subdev.
>>>>
>>>> - brought in latest platform generic video multiplexer subdevice driver
>>>> from Philipp Zabel (squashed with patch that uses new MEDIA_ENT_F_MUX).
>>>>
>>>> - removed imx-media-of.h, moved those prototypes into imx-media.h.
>>> Based on the discussion on the mailinglist it seems everyone agrees that this
>>> is the preferred driver, correct?
>> No. I have some major reservations against the custom mem2mem framework
>> embedded in Steve's driver.
>> I think it is a misuse of the media entity links (which should describe
>> hardware connections) for something that should be done at the vb2 level
>> (letting one device's capture EOF interrupt trigger the next device's
>> m2m device_run without going through userspace).
>> Steve and I disagree on that point, so we'd appreciate if we could get
>> some more eyes on the above issue.
>
> This needs some background first, so let me first describe one example
> pipeline in this driver.
>
> There is a VDIC entity in the i.MX IPU that performs de-interlacing with
> hardware filters for motion compensation. Some of the motion compensation
> modes ("low" and "medium" motion) require that the VDIC receive video
> frame fields from memory buffers (dedicated dma channels in the
> IPU are used to transfer those buffers into the VDIC).
>
> So one option to support those modes would be to pass the raw buffers
> from a camera sensor up to userspace to a capture device, and then pass
> them back to the VDIC for de-interlacing using a mem2mem device.
>
> Philipp and I are both in agreement that, since userland is not interested
> in the intermediate interlaced buffers in this case, but only the final
> result (motion compensated, de-interlaced frames), it is more efficient
> to provide a media link that allows passing those intermediate frames
> directly from a camera source pad to VDIC sink pad, without having
> to route them through userspace.
>
> So in order to support that, I've implemented a simple FIFO dma buffer
> queue in the driver to allow passing video buffers directly from a source
> to a sink. It is modeled loosely off the vb2 state machine and API, but
> simpler (for instance it only allows contiguous, cache-coherent buffers).
>
> This is where Philipp has an argument, that this should be done with a
> new API in videobuf2.
>
> And I'm actually in total agreement with that. I definitely agree that there
> should be a mechanism in the media framework that allows passing video
> buffers from a source pad to a sink pad using a software queue, with no
> involvement from userland.
>
> My only disagreement is when this should be implemented. I think it is
> fine to keep my custom implementation of this in the driver for now. Once
> an extension of vb2 is ready to support this feature, it would be fairly
> straightforward to strip out my custom implementation and go with the
> new API.
For a staging driver this isn't necessary, as long as it is documented in
the TODO file that this needs to be fixed before it can be moved out of
staging. The whole point of staging is that there is still work to be
done in the driver, after all :-)
BTW, did you look at the vb2_thread_* functions in videobuf2-core.c? A lot
of what you need is already there. Making a new version that has producer
and consumer queues shouldn't be hard given that code.
Regards,
Hans
^ permalink raw reply
* [PATCH 0/3] arm64: Add ARCH_THUNDER2
From: Jayachandran C @ 2017-01-20 20:46 UTC (permalink / raw)
To: linux-arm-kernel
Cc: devicetree, Arnd Bergmann, david.daney, Catalin Marinas,
Will Deacon, linux-kernel, Rob Herring, Jayachandran C
This patchset adds support for the new ThunderX2 CN99XX processor
family.
Changes are to add the config option, the required device tree files,
the device tree bindings documentation and the defconfig entry.
JC.
Jayachandran C (3):
arm64: add THUNDER2 processor family
dt-bindings: arm64 ARCH_THUNDER2 platform documentation
arm64: add ARCH_THUNDER2 to defconfig
.../devicetree/bindings/arm/cavium-thunder2.txt | 5 +
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
arch/arm64/Kconfig.platforms | 7 +
arch/arm64/boot/dts/cavium/Makefile | 1 +
arch/arm64/boot/dts/cavium/thunder-99xx.dts | 34 +++++
arch/arm64/boot/dts/cavium/thunder-99xx.dtsi | 147 +++++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
7 files changed, 196 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder2.txt
create mode 100644 arch/arm64/boot/dts/cavium/thunder-99xx.dts
create mode 100644 arch/arm64/boot/dts/cavium/thunder-99xx.dtsi
--
2.7.4
^ permalink raw reply
* [PATCH 1/3] arm64: add THUNDER2 processor family
From: Jayachandran C @ 2017-01-20 20:46 UTC (permalink / raw)
To: linux-arm-kernel
Cc: devicetree, Arnd Bergmann, david.daney, Catalin Marinas,
Will Deacon, linux-kernel, Rob Herring, Jayachandran C
In-Reply-To: <1484945201-17248-1-git-send-email-jnair@caviumnetworks.com>
Add support for ThunderX2 CN99XX arm64 server processors.
Introduce a new arm64 platform config option ARCH_THUNDER2 for these
processors. Add device tree files boot/dts/cavium/thunder-99xx.dtsi for
on-chip devices and boot/dts/cavium/thunder-99xx.dts for the evaluation
board.
Signed-off-by: Jayachandran C <jnair@caviumnetworks.com>
---
arch/arm64/Kconfig.platforms | 7 ++
arch/arm64/boot/dts/cavium/Makefile | 1 +
arch/arm64/boot/dts/cavium/thunder-99xx.dts | 34 +++++++
arch/arm64/boot/dts/cavium/thunder-99xx.dtsi | 147 +++++++++++++++++++++++++++
4 files changed, 189 insertions(+)
create mode 100644 arch/arm64/boot/dts/cavium/thunder-99xx.dts
create mode 100644 arch/arm64/boot/dts/cavium/thunder-99xx.dtsi
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 715ef12..129cc5a 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -190,6 +190,13 @@ config ARCH_THUNDER
help
This enables support for Cavium's Thunder Family of SoCs.
+config ARCH_THUNDER2
+ bool "Cavium ThunderX2 Server Processors"
+ select GPIOLIB
+ help
+ This enables support for Cavium's ThunderX2 CN99XX family of
+ server processors.
+
config ARCH_UNIPHIER
bool "Socionext UniPhier SoC Family"
select ARCH_HAS_RESET_CONTROLLER
diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile
index e34f89d..557c8be 100644
--- a/arch/arm64/boot/dts/cavium/Makefile
+++ b/arch/arm64/boot/dts/cavium/Makefile
@@ -1,4 +1,5 @@
dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb
+dtb-$(CONFIG_ARCH_THUNDER2) += thunder-99xx.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/cavium/thunder-99xx.dts b/arch/arm64/boot/dts/cavium/thunder-99xx.dts
new file mode 100644
index 0000000..ed6715a
--- /dev/null
+++ b/arch/arm64/boot/dts/cavium/thunder-99xx.dts
@@ -0,0 +1,34 @@
+/*
+ * dts file for Cavium ThunderX2 CN99XX based Evaluation Boards
+ *
+ * Copyright (c) 2017 Cavium Inc.
+ * Copyright (c) 2013-2016 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+#include "thunder-99xx.dtsi"
+
+/ {
+ model = "Cavium ThunderX2 CN99XX";
+ compatible = "cavium,thunder-99xx";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
+ <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
diff --git a/arch/arm64/boot/dts/cavium/thunder-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-99xx.dtsi
new file mode 100644
index 0000000..1c07732
--- /dev/null
+++ b/arch/arm64/boot/dts/cavium/thunder-99xx.dtsi
@@ -0,0 +1,147 @@
+/*
+ * dtsi file for Cavium ThunderX2 CN99XX processor
+ *
+ * Copyright (c) 2017 Cavium Inc.
+ * Copyright (c) 2013-2016 Broadcom
+ * Author: Zi Shen Lim <zlim@broadcom.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "Cavium ThunderX2 CN99xx";
+ compatible = "cavium,thunder-99xx";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* just 4 cpus now, 128 needed in full config */
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "cavium,thunder2", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "cavium,thunder2", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "cavium,thunder2", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "cavium,thunder2", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ gic: interrupt-controller@400080000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */
+ <0x04 0x01000000 0x0 0x1000000>; /* GICR */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gicits: gic-its@40010000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */
+ };
+
+ clk125mhz: uart_clk125mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ clock-output-names = "clk125mhz";
+ };
+
+ pci {
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ /* ECAM at 0x3000_0000 - 0x4000_0000 */
+ reg = <0x0 0x30000000 0x0 0x10000000>;
+ reg-names = "PCI ECAM";
+
+ /*
+ * PCI ranges:
+ * IO no supported
+ * MEM 0x4000_0000 - 0x6000_0000
+ * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000
+ */
+ ranges =
+ <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000
+ 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map =
+ /* addr pin ic icaddr icintr */
+ <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ msi-parent = <&gicits>;
+ dma-coherent;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ uart0: serial@402020000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x04 0x02020000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk125mhz>;
+ clock-names = "apb_pclk";
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 2/3] dt-bindings: arm64 ARCH_THUNDER2 platform documentation
From: Jayachandran C @ 2017-01-20 20:46 UTC (permalink / raw)
To: linux-arm-kernel
Cc: devicetree, Arnd Bergmann, david.daney, Catalin Marinas,
Will Deacon, linux-kernel, Rob Herring, Jayachandran C
In-Reply-To: <1484945201-17248-1-git-send-email-jnair@caviumnetworks.com>
Add documentation for Cavium ThunderX2 CN99XX ARM64 processor family.
The processor core will use cavium,thunder2 as ID and the SoC will use
cavium,thunder-99xx
Signed-off-by: Jayachandran C <jnair@caviumnetworks.com>
---
Documentation/devicetree/bindings/arm/cavium-thunder2.txt | 5 +++++
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
2 files changed, 6 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder2.txt
diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder2.txt b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt
new file mode 100644
index 0000000..82276a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt
@@ -0,0 +1,5 @@
+Cavium Thunder2 Family device tree bindings
+-------------------------------------------
+
+Boards with Cavium ThunderX2 CN99XX shall have the root property:
+ compatible = "cavium,thunder-99xx";
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index a1bcfee..74f0b23 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -169,6 +169,7 @@ nodes to be present and contain the properties described below.
"brcm,brahma-b15"
"brcm,vulcan"
"cavium,thunder"
+ "cavium,thunder2"
"faraday,fa526"
"intel,sa110"
"intel,sa1100"
--
2.7.4
^ permalink raw reply related
* [PATCH 3/3] arm64: add ARCH_THUNDER2 to defconfig
From: Jayachandran C @ 2017-01-20 20:46 UTC (permalink / raw)
To: linux-arm-kernel
Cc: devicetree, Arnd Bergmann, david.daney, Catalin Marinas,
Will Deacon, linux-kernel, Rob Herring, Jayachandran C
In-Reply-To: <1484945201-17248-1-git-send-email-jnair@caviumnetworks.com>
This will allow the default kernel build to boot on Cavium ThunderX2
CN99XX processors.
Signed-off-by: Jayachandran C <jnair@caviumnetworks.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 33b744d..7a9c262 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -53,6 +53,7 @@ CONFIG_ARCH_STRATIX10=y
CONFIG_ARCH_TEGRA=y
CONFIG_ARCH_SPRD=y
CONFIG_ARCH_THUNDER=y
+CONFIG_ARCH_THUNDER2=y
CONFIG_ARCH_UNIPHIER=y
CONFIG_ARCH_VEXPRESS=y
CONFIG_ARCH_VULCAN=y
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v3 5/6] ARM: dts: sunxi: add dtsi file for V3s SoC
From: Maxime Ripard @ 2017-01-20 20:48 UTC (permalink / raw)
To: Icenowy Zheng
Cc: devicetree, linux-doc, linux-kernel, linux-gpio, Chen-Yu Tsai,
Rob Herring, linux-clk, linux-arm-kernel
In-Reply-To: <20170119175448.11445-5-icenowy@aosc.xyz>
[-- Attachment #1.1: Type: text/plain, Size: 849 bytes --]
On Fri, Jan 20, 2017 at 01:54:47AM +0800, Icenowy Zheng wrote:
> As we have the pinctrl and clock support for the V3s SoC, it's now to
> run a mainline Linux on it.
>
> So add a .dtsi file for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Next time, please provide a description of what that SoC in your
commit log.
> + rtc: rtc@01c20400 {
> + compatible = "allwinner,sun6i-a31-rtc";
> + reg = <0x01c20400 0x54>;
> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> + };
Did you have the chance to actually test how the RTC was behaving?
Other RTC have been pretty bad at keeping time, this is probably
something you want to check.
Applied,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v3 6/6] ARM: dts: sunxi: add support for Lichee Pi Zero board
From: Maxime Ripard @ 2017-01-20 20:48 UTC (permalink / raw)
To: Icenowy Zheng
Cc: devicetree, linux-doc, linux-kernel, linux-gpio, Chen-Yu Tsai,
Rob Herring, linux-clk, linux-arm-kernel
In-Reply-To: <20170119175448.11445-6-icenowy@aosc.xyz>
[-- Attachment #1.1: Type: text/plain, Size: 402 bytes --]
On Fri, Jan 20, 2017 at 01:54:48AM +0800, Icenowy Zheng wrote:
> Lichee Pi Zero is a small-sized V3s board, which is
> breadboard-compatible, and with a MicroUSB port with both OTG function
> and power function.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Applied, thanks
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 0/2] Ensure that platform buses from overlays are functional
From: Alexander Sverdlin @ 2017-01-20 20:57 UTC (permalink / raw)
Cc: Alexander Sverdlin, Rob Herring, Frank Rowand,
devicetree-u79uwXL29TY76Z2rM5mHXA, Grant Likely,
Pantelis Antoniou
In-Reply-To: <CAL_JsqJZ__mUwRT14BmNQKaa_mAPsJm0iWP8sb6Oqs+_-Gu5hw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
This series addresses an issue, which prevents one to add child devices to
a platform bus from an overlay if such a bus was in turn also created from
an overlay.
The root cause is missing OF_POPULATED_BUS flag for such buses and the
difference, in the way, how static and dynamic platform devices are
populated.
Second patch adds a couple of test cases which demonstrate the problem.
This series relies on the correct functioning of
of_unittest_apply_overlay() (previously sent "of/unittest: Swap arguments
of of_unittest_apply_overlay()").
Alexander Sverdlin (2):
of/platform: dynamic: Use of_platform_bus_create() to create devices
of/unittest: Test platform bus added from overlay
drivers/of/platform.c | 11 ++++----
drivers/of/unittest-data/tests-overlay.dtsi | 41 +++++++++++++++++++++++++++++
drivers/of/unittest.c | 31 ++++++++++++++++++++++
3 files changed, 78 insertions(+), 5 deletions(-)
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Frank Rowand <frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: Grant Likely <grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: Pantelis Antoniou <pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w@public.gmane.org>
--
2.11.0
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 1/2] of/platform: dynamic: Use of_platform_bus_create() to create devices
From: Alexander Sverdlin @ 2017-01-20 21:02 UTC (permalink / raw)
Cc: Alexander Sverdlin, Rob Herring, Frank Rowand,
devicetree-u79uwXL29TY76Z2rM5mHXA, Grant Likely,
Pantelis Antoniou
In-Reply-To: <20170120205745.11851-1-alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
of_platform_notify() requires parents to have OF_POPULATED_BUS to be set
(which is correct way to verify healthy platform bus), but uses
of_platform_device_create() to create devices, which never sets the above
flag. Therefore it's not possible to add platform buses via overlays.
Use of_platform_bus_create(), which is used in non-overlay case to populate
both buses and devices.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Frank Rowand <frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: Grant Likely <grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: Pantelis Antoniou <pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w@public.gmane.org>
---
drivers/of/platform.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index b8064bc2b6eb..35de1fc59fa6 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -578,6 +578,7 @@ static int of_platform_notify(struct notifier_block *nb,
struct of_reconfig_data *rd = arg;
struct platform_device *pdev_parent, *pdev;
bool children_left;
+ int ret;
switch (of_reconfig_get_state_change(action, rd)) {
case OF_RECONFIG_CHANGE_ADD:
@@ -591,15 +592,15 @@ static int of_platform_notify(struct notifier_block *nb,
/* pdev_parent may be NULL when no bus platform device */
pdev_parent = of_find_device_by_node(rd->dn->parent);
- pdev = of_platform_device_create(rd->dn, NULL,
- pdev_parent ? &pdev_parent->dev : NULL);
+ ret = of_platform_bus_create(rd->dn, of_default_bus_match_table,
+ NULL, pdev_parent ?
+ &pdev_parent->dev : NULL, true);
of_dev_put(pdev_parent);
- if (pdev == NULL) {
+ if (ret) {
pr_err("%s: failed to create for '%s'\n",
__func__, rd->dn->full_name);
- /* of_platform_device_create tosses the error code */
- return notifier_from_errno(-EINVAL);
+ return notifier_from_errno(ret);
}
break;
--
2.11.0
--
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