* [PATCH 1/2] of/platform: dynamic: Use of_platform_bus_create() to create devices
From: Alexander Sverdlin @ 2017-01-20 21:02 UTC (permalink / raw)
Cc: Alexander Sverdlin, Rob Herring, Frank Rowand,
devicetree-u79uwXL29TY76Z2rM5mHXA, Grant Likely,
Pantelis Antoniou
In-Reply-To: <20170120205745.11851-1-alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
of_platform_notify() requires parents to have OF_POPULATED_BUS to be set
(which is correct way to verify healthy platform bus), but uses
of_platform_device_create() to create devices, which never sets the above
flag. Therefore it's not possible to add platform buses via overlays.
Use of_platform_bus_create(), which is used in non-overlay case to populate
both buses and devices.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Frank Rowand <frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: Grant Likely <grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: Pantelis Antoniou <pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w@public.gmane.org>
---
drivers/of/platform.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index b8064bc2b6eb..35de1fc59fa6 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -578,6 +578,7 @@ static int of_platform_notify(struct notifier_block *nb,
struct of_reconfig_data *rd = arg;
struct platform_device *pdev_parent, *pdev;
bool children_left;
+ int ret;
switch (of_reconfig_get_state_change(action, rd)) {
case OF_RECONFIG_CHANGE_ADD:
@@ -591,15 +592,15 @@ static int of_platform_notify(struct notifier_block *nb,
/* pdev_parent may be NULL when no bus platform device */
pdev_parent = of_find_device_by_node(rd->dn->parent);
- pdev = of_platform_device_create(rd->dn, NULL,
- pdev_parent ? &pdev_parent->dev : NULL);
+ ret = of_platform_bus_create(rd->dn, of_default_bus_match_table,
+ NULL, pdev_parent ?
+ &pdev_parent->dev : NULL, true);
of_dev_put(pdev_parent);
- if (pdev == NULL) {
+ if (ret) {
pr_err("%s: failed to create for '%s'\n",
__func__, rd->dn->full_name);
- /* of_platform_device_create tosses the error code */
- return notifier_from_errno(-EINVAL);
+ return notifier_from_errno(ret);
}
break;
--
2.11.0
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 2/2] of/unittest: Test platform bus added from overlay
From: Alexander Sverdlin @ 2017-01-20 21:02 UTC (permalink / raw)
Cc: Alexander Sverdlin, Rob Herring, Frank Rowand,
devicetree-u79uwXL29TY76Z2rM5mHXA, Grant Likely,
Pantelis Antoniou
In-Reply-To: <20170120210234.11924-1-alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
Check that it's possible to:
- add children to platform buses originating from overlays
- use overlay to enable a platform bus originating from overlay
Explicitly avoid unittest_probe(), because this test case checks the correct
creation of the devices only. Driver probing might be delayed (say, modules)
and correct device creation must not depend on it.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Frank Rowand <frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: Grant Likely <grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: Pantelis Antoniou <pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w@public.gmane.org>
---
drivers/of/unittest-data/tests-overlay.dtsi | 83 +++++++++++++++++++++++++++++
drivers/of/unittest.c | 60 +++++++++++++++++++++
2 files changed, 143 insertions(+)
diff --git a/drivers/of/unittest-data/tests-overlay.dtsi b/drivers/of/unittest-data/tests-overlay.dtsi
index 02ba56c20fe1..6925a992f9e2 100644
--- a/drivers/of/unittest-data/tests-overlay.dtsi
+++ b/drivers/of/unittest-data/tests-overlay.dtsi
@@ -325,5 +325,88 @@
};
};
+ /* test that platform buses from overlays are functional */
+ overlay16 {
+ fragment@0 {
+ target-path = "/testcase-data/overlay-node/test-bus";
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ test-unittest16 {
+ /*
+ * testing just device creation,
+ * no unittest_probe() should
+ * be called
+ */
+ compatible = "simple-bus";
+ reg = <16>;
+ };
+ };
+ };
+ };
+
+ overlay17 {
+ fragment@0 {
+ target-path = "/testcase-data/overlay-node/test-bus";
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ test-unittest16 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ test-unittest161 {
+ compatible = "unittest";
+ reg = <1>;
+ };
+ };
+ };
+ };
+ };
+
+ overlay18 {
+ fragment@0 {
+ target-path = "/testcase-data/overlay-node/test-bus";
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ test-unittest18 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /*
+ * testing just device creation,
+ * no unittest_probe() should
+ * be called
+ */
+ compatible = "simple-bus";
+ reg = <18>;
+ status = "disabled";
+
+ test-unittest181 {
+ compatible = "unittest";
+ reg = <1>;
+ };
+ };
+ };
+ };
+ };
+
+ overlay19 {
+ fragment@0 {
+ target-path = "/testcase-data/overlay-node/test-bus";
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ test-unittest18 {
+ status = "okay";
+ };
+ };
+ };
+ };
+
};
};
diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c
index 66bfa8d674ce..2c533709bb0e 100644
--- a/drivers/of/unittest.c
+++ b/drivers/of/unittest.c
@@ -1854,6 +1854,63 @@ static inline void of_unittest_overlay_i2c_15(void) { }
#endif
+/* test that platform buses populated by overlays are functional */
+static void of_unittest_overlay_16(void)
+{
+ int ret;
+ char *child_path;
+
+ /* add an empty bus */
+ ret = of_unittest_apply_overlay_check(16, 16, 0, 1, PDEV_OVERLAY);
+ if (unittest(ret == 0,
+ "overlay test %d failed; overlay application\n", 16))
+ return;
+
+ /* add a device to the bus */
+ ret = of_unittest_apply_overlay(17, 16, PDEV_OVERLAY);
+ if (unittest(ret == 0,
+ "overlay test %d failed; overlay application\n", 16))
+ return;
+
+ child_path = kasprintf(GFP_KERNEL, "%s/test-unittest161",
+ unittest_path(16, PDEV_OVERLAY));
+ if (unittest(child_path, "overlay test %d failed; kasprintf\n", 16))
+ return;
+
+ ret = of_path_device_type_exists(child_path, PDEV_OVERLAY);
+ kfree(child_path);
+ if (unittest(ret, "overlay test %d failed; no child device\n", 16))
+ return;
+}
+
+static void of_unittest_overlay_18(void)
+{
+ int ret;
+ char *child_path;
+
+ /* add a disabled bus */
+ ret = of_unittest_apply_overlay_check(18, 18, 0, 0, PDEV_OVERLAY);
+ if (unittest(ret == 0,
+ "overlay test %d failed; overlay application\n", 18))
+ return;
+
+ /* enable the bus */
+ ret = of_unittest_apply_overlay_check(19, 18, 0, 1, PDEV_OVERLAY);
+ if (unittest(ret == 0,
+ "overlay test %d failed; overlay application\n", 18))
+ return;
+
+ child_path = kasprintf(GFP_KERNEL, "%s/test-unittest181",
+ unittest_path(18, PDEV_OVERLAY));
+ if (unittest(child_path, "overlay test %d failed; kasprintf\n", 18))
+ return;
+
+ ret = of_path_device_type_exists(child_path, PDEV_OVERLAY);
+ kfree(child_path);
+ if (unittest(ret, "overlay test %d failed; no child device\n", 18))
+ return;
+}
+
static void __init of_unittest_overlay(void)
{
struct device_node *bus_np = NULL;
@@ -1916,6 +1973,9 @@ static void __init of_unittest_overlay(void)
of_unittest_overlay_i2c_cleanup();
#endif
+ of_unittest_overlay_16();
+ of_unittest_overlay_18();
+
of_unittest_destroy_tracked_overlays();
out:
--
2.11.0
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH v3 5/6] ARM: dts: sunxi: add dtsi file for V3s SoC
From: Icenowy Zheng @ 2017-01-20 21:03 UTC (permalink / raw)
To: Maxime Ripard
Cc: Rob Herring, linux-clk, linux-kernel, linux-gpio, devicetree,
linux-doc, linux-arm-kernel, Chen-Yu Tsai
2017年1月21日 04:48于 Maxime Ripard <maxime.ripard@free-electrons.com>写道：
>
> On Fri, Jan 20, 2017 at 01:54:47AM +0800, Icenowy Zheng wrote:
> > As we have the pinctrl and clock support for the V3s SoC, it's now to
> > run a mainline Linux on it.
> >
> > So add a .dtsi file for it.
> >
> > Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>
> Next time, please provide a description of what that SoC in your
> commit log.
>
> > + rtc: rtc@01c20400 {
> > + compatible = "allwinner,sun6i-a31-rtc";
> > + reg = <0x01c20400 0x54>;
> > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> > + };
>
> Did you have the chance to actually test how the RTC was behaving?
>
> Other RTC have been pretty bad at keeping time, this is probably
> something you want to check.
Currently no...
>
> Applied,
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
^ permalink raw reply
* [PATCH v2 0/2] clocksource: Add renesas-ostm timer driver
From: Chris Brandt @ 2017-01-20 21:20 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Russell King, Daniel Lezcano, Thomas Gleixner, Geert Uytterhoeven
Cc: devicetree, linux-renesas-soc, Chris Brandt
This patch set adds a new clocksource driver that uses the OS Timer
(OSTM) that exists in the R7S72100 (RZ/A1) SoC.
The operation of the driver was tested with a simple user application
that does multiple calls to nanosleep() and gettimeofday().
The purpose of adding this driver is to get better time keeping
accuracy over the default MTU2 clocksource timer.
v2:
* The biggest change was now the channels are independent of each
other and have separate nodes in the DT. The first probed will
be set up as a clock source, and any additional channels probed
will become a clock event.
Chris Brandt (2):
dt-bindings: document renesas-ostm timer
clocksource: Add renesas-ostm timer driver
.../devicetree/bindings/timer/renesas,ostm.txt | 29 ++
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/clocksource/Kconfig | 12 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/renesas-ostm.c | 349 +++++++++++++++++++++
5 files changed, 392 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/renesas,ostm.txt
create mode 100644 drivers/clocksource/renesas-ostm.c
--
2.10.1
^ permalink raw reply
* [PATCH v2 1/2] dt-bindings: document renesas-ostm timer
From: Chris Brandt @ 2017-01-20 21:20 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Russell King, Daniel Lezcano, Thomas Gleixner, Geert Uytterhoeven
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Chris Brandt
In-Reply-To: <20170120212003.4103-1-chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
---
v2:
* remove sw implementation specific portions
---
.../devicetree/bindings/timer/renesas,ostm.txt | 29 ++++++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/renesas,ostm.txt
diff --git a/Documentation/devicetree/bindings/timer/renesas,ostm.txt b/Documentation/devicetree/bindings/timer/renesas,ostm.txt
new file mode 100644
index 0000000..06d7d71
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/renesas,ostm.txt
@@ -0,0 +1,29 @@
+* Renesas OS Timer (OSTM)
+
+The OSTM is a multi-channel 32-bit timer/counter with fixed clock
+source that can operate in either interval count down timer or free-running
+compare match mode.
+
+Channels are independent from each other.
+
+Required Properties:
+
+ - compatible: must be one or more of the following:
+ - "renesas,r7s72100-ostm" for the r7s72100 OSTM
+ - "renesas,ostm" for any OSTM
+ This is a fallback for the above renesas,*-ostm entries
+
+ - reg: base address and length of the register block for a timer channel.
+
+ - interrupts: interrupt specifier for the timer channel.
+
+ - clocks: clock specifier for the timer channel.
+
+Example: R7S72100 (RZ/A1H) OSTM node
+
+ ostm0: ostm@fcfec000 {
+ compatible = "renesas,r7s72100-ostm", "renesas,ostm";
+ reg = <0xfcfec000 0x30>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
+ };
--
2.10.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v2 2/2] clocksource: Add renesas-ostm timer driver
From: Chris Brandt @ 2017-01-20 21:20 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Russell King, Daniel Lezcano, Thomas Gleixner, Geert Uytterhoeven
Cc: devicetree, linux-renesas-soc, Chris Brandt
In-Reply-To: <20170120212003.4103-1-chris.brandt@renesas.com>
This patch adds a OSTM driver for the Renesas architecture.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
v2:
* changed implementation to be independent channel nodes
---
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/clocksource/Kconfig | 12 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/renesas-ostm.c | 349 +++++++++++++++++++++++++++++++++++++
4 files changed, 363 insertions(+)
create mode 100644 drivers/clocksource/renesas-ostm.c
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 2bb4b09..b928634 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -57,6 +57,7 @@ config ARCH_R7S72100
select PM
select PM_GENERIC_DOMAINS
select SYS_SUPPORTS_SH_MTU2
+ select SYS_SUPPORTS_RENESAS_OSTM
config ARCH_R8A73A4
bool "R-Mobile APE6 (R8A73A40)"
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 4866f7a..95c8d56 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -431,6 +431,9 @@ config MTK_TIMER
config SYS_SUPPORTS_SH_MTU2
bool
+config SYS_SUPPORTS_RENESAS_OSTM
+ bool
+
config SYS_SUPPORTS_SH_TMU
bool
@@ -467,6 +470,15 @@ config SH_TIMER_MTU2
Timer Pulse Unit 2 (MTU2) hardware available on SoCs from Renesas.
This hardware comes with 16 bit-timer registers.
+config RENESAS_OSTM
+ bool "Renesas OSTM timer driver" if COMPILE_TEST
+ depends on GENERIC_CLOCKEVENTS
+ select CLKSRC_MMIO
+ default SYS_SUPPORTS_RENESAS_OSTM
+ help
+ This enables the build of the OSTM timer driver.
+ It creates a clock source and clock event device.
+
config SH_TIMER_TMU
bool "Renesas TMU timer driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index a14111e..bbd163b 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += cs5535-clockevt.o
obj-$(CONFIG_CLKSRC_JCORE_PIT) += jcore-pit.o
obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o
obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o
+obj-$(CONFIG_RENESAS_OSTM) += renesas-ostm.o
obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
obj-$(CONFIG_EM_TIMER_STI) += em_sti.o
obj-$(CONFIG_CLKBLD_I8253) += i8253.o
diff --git a/drivers/clocksource/renesas-ostm.c b/drivers/clocksource/renesas-ostm.c
new file mode 100644
index 0000000..37f2461
--- /dev/null
+++ b/drivers/clocksource/renesas-ostm.c
@@ -0,0 +1,349 @@
+/*
+ * Renesas Timer Support - OSTM
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/sched_clock.h>
+
+/*
+ * The OSTM contains independent channels.
+ * The first OSTM channel probed will be set up as a free running
+ * clocksource. Additionally we will use this clocksource for the system
+ * schedule timer sched_clock().
+ *
+ * The second (or more) channel probed will be set up as an interrupt
+ * driven clock event.
+ */
+
+struct ostm_device {
+ struct platform_device *pdev;
+
+ int irq;
+ struct clk *clk;
+ unsigned long rate;
+ void __iomem *base;
+ unsigned long ticks_per_jiffy;
+ struct clock_event_device ced;
+};
+
+static void __iomem *system_clock; /* For sched_clock() */
+
+/* OSTM REGISTERS */
+#define OSTM_CMP 0x000 /* RW,32 */
+#define OSTM_CNT 0x004 /* R,32 */
+#define OSTM_TE 0x010 /* R,8 */
+#define OSTM_TS 0x014 /* W,8 */
+#define OSTM_TT 0x018 /* W,8 */
+#define OSTM_CTL 0x020 /* RW,8 */
+
+#define TE 0x01
+#define TS 0x01
+#define TT 0x01
+#define CTL_PERIODIC 0x00
+#define CTL_ONESHOT 0x02
+#define CTL_FREERUN 0x02
+
+static struct ostm_device *ced_to_ostm(struct clock_event_device *ced)
+{
+ return container_of(ced, struct ostm_device, ced);
+}
+
+static int __init ostm_init_clksrc(struct ostm_device *ostm)
+{
+ int ret;
+
+ /* irq not used (clock sources don't use interrupts) */
+
+ /* stop counter */
+ iowrite8(TT, ostm->base + OSTM_TT);
+ while (ioread8(ostm->base + OSTM_TE) & TE)
+ ;
+
+ /* setup as freerun */
+ iowrite32(0, ostm->base + OSTM_CMP);
+ iowrite8(CTL_FREERUN, ostm->base + OSTM_CTL);
+ iowrite8(TS, ostm->base + OSTM_TS);
+
+ /* register */
+ ret = clocksource_mmio_init(ostm->base + OSTM_CNT,
+ "ostm", ostm->rate,
+ 300, 32, clocksource_mmio_readl_up);
+
+ return ret;
+}
+
+static u64 notrace ostm_read_sched_clock(void)
+{
+ return ioread32(system_clock);
+}
+
+static int __init ostm_init_sched_clock(struct ostm_device *ostm)
+{
+ unsigned long flags;
+
+ system_clock = ostm->base + OSTM_CNT;
+ local_irq_save(flags);
+ local_irq_disable();
+ sched_clock_register(ostm_read_sched_clock, 32, ostm->rate);
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static void ostm_clkevt_timer_stop(struct ostm_device *ostm)
+{
+ if (ioread8(ostm->base + OSTM_TE) & TE) {
+ iowrite8(TT, ostm->base + OSTM_TT);
+ while (ioread8(ostm->base + OSTM_TE) & TE)
+ ;
+ }
+}
+
+static int ostm_clock_event_next(unsigned long delta,
+ struct clock_event_device *ced)
+{
+ struct ostm_device *ostm = ced_to_ostm(ced);
+
+ WARN_ON(!clockevent_state_oneshot(ced));
+
+ ostm_clkevt_timer_stop(ostm);
+
+ iowrite32(delta, ostm->base + OSTM_CMP);
+ iowrite8(CTL_ONESHOT, ostm->base + OSTM_CTL);
+ iowrite8(TS, ostm->base + OSTM_TS);
+
+ return 0;
+}
+
+static int ostm_shutdown(struct clock_event_device *ced)
+{
+ struct ostm_device *ostm = ced_to_ostm(ced);
+
+ ostm_clkevt_timer_stop(ostm);
+
+ return 0;
+}
+static int ostm_set_periodic(struct clock_event_device *ced)
+{
+ struct ostm_device *ostm = ced_to_ostm(ced);
+
+ if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
+ ostm_clkevt_timer_stop(ostm);
+
+ iowrite32(ostm->ticks_per_jiffy - 1, ostm->base + OSTM_CMP);
+ iowrite8(CTL_PERIODIC, ostm->base + OSTM_CTL);
+ iowrite8(TS, ostm->base + OSTM_TS);
+
+ return 0;
+}
+
+static int ostm_set_oneshot(struct clock_event_device *ced)
+{
+ struct ostm_device *ostm = ced_to_ostm(ced);
+
+ ostm_clkevt_timer_stop(ostm);
+
+ return 0;
+}
+
+static irqreturn_t ostm_timer_interrupt(int irq, void *dev_id)
+{
+ struct ostm_device *ostm = dev_id;
+
+ if (clockevent_state_oneshot(&ostm->ced))
+ ostm_clkevt_timer_stop(ostm);
+
+ /* notify clockevent layer */
+ if (ostm->ced.event_handler)
+ ostm->ced.event_handler(&ostm->ced);
+
+ return IRQ_HANDLED;
+}
+
+static int __init ostm_init_clkevt(struct ostm_device *ostm)
+{
+ struct clock_event_device *ced = &ostm->ced;
+ int ret = -ENXIO;
+
+ ret = request_irq(ostm->irq, ostm_timer_interrupt,
+ IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
+ dev_name(&ostm->pdev->dev), ostm);
+ if (ret) {
+ dev_err(&ostm->pdev->dev, "failed to request irq\n");
+ return ret;
+ }
+
+ ced->name = "ostm";
+ ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;
+ ced->set_state_shutdown = ostm_shutdown;
+ ced->set_state_periodic = ostm_set_periodic;
+ ced->set_state_oneshot = ostm_set_oneshot;
+ ced->set_next_event = ostm_clock_event_next;
+ ced->shift = 32;
+ ced->rating = 300;
+ ced->cpumask = cpumask_of(0);
+ clockevents_config_and_register(ced, ostm->rate, 0xf, 0xffffffff);
+
+ return 0;
+}
+
+static int __init ostm_probe(struct platform_device *pdev)
+{
+ struct ostm_device *ostm;
+ struct resource *res;
+ int ret = -EFAULT;
+
+ if (!is_early_platform_device(pdev)) {
+ pm_runtime_set_active(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
+ }
+
+ ostm = platform_get_drvdata(pdev);
+ if (ostm) {
+ dev_info(&pdev->dev, "kept as earlytimer\n");
+ ret = 0;
+ goto out;
+ }
+
+ ostm = kzalloc(sizeof(*ostm), GFP_KERNEL);
+ if (!ostm) {
+ dev_err(&pdev->dev, "failed to allocate memory\n");
+ return -ENOMEM;
+ }
+
+ ostm->pdev = pdev;
+ platform_set_drvdata(ostm->pdev, ostm);
+
+ res = platform_get_resource(ostm->pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&ostm->pdev->dev, "failed to get I/O memory\n");
+ goto err;
+ }
+
+ ostm->base = ioremap_nocache(res->start, resource_size(res));
+ if (!ostm->base) {
+ dev_err(&ostm->pdev->dev, "failed to remap I/O memory\n");
+ goto err;
+ }
+
+ ostm->irq = platform_get_irq(ostm->pdev, 0);
+ if (ostm->irq < 0) {
+ dev_err(&ostm->pdev->dev, "failed to get irq\n");
+ goto err;
+ }
+
+ ostm->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(ostm->clk)) {
+ dev_err(&ostm->pdev->dev, "failed to get clock\n");
+ ostm->clk = NULL;
+ goto err;
+ }
+
+ ret = clk_prepare_enable(ostm->clk);
+ if (ret) {
+ dev_err(&ostm->pdev->dev, "failed to enable clock\n");
+ goto err;
+ }
+
+ ostm->rate = clk_get_rate(ostm->clk);
+ ostm->ticks_per_jiffy = (ostm->rate + HZ / 2) / HZ;
+
+ /* First probed device will be used as system clocksource */
+ if (!system_clock) {
+ /* use as clocksource */
+ ret = ostm_init_clksrc(ostm);
+
+ /* use as system scheduling clock */
+ if (!ret)
+ ret = ostm_init_sched_clock(ostm);
+
+ if (ret) {
+ dev_err(&pdev->dev, "failed to use as sched_clock\n");
+ system_clock = (void *)-1; /* prevent future attempts */
+ ret = 0; /* still works as clocksource */
+ }
+
+ if (!ret)
+ dev_info(&pdev->dev, "used for clocksource\n");
+ } else {
+ /* use as clock event */
+ ret = ostm_init_clkevt(ostm);
+
+ if (!ret)
+ dev_info(&pdev->dev, "used for clock events\n");
+ }
+
+err:
+ if (ret) {
+ if (ostm->clk)
+ clk_disable_unprepare(ostm->clk);
+ if (ostm->base)
+ iounmap(ostm->base);
+ kfree(ostm);
+ platform_set_drvdata(pdev, NULL);
+ pm_runtime_idle(&pdev->dev);
+ return ret;
+ }
+
+ if (is_early_platform_device(pdev))
+ return ret;
+
+out:
+ pm_runtime_irq_safe(&pdev->dev);
+
+ return ret;
+}
+
+static int ostm_remove(struct platform_device *pdev)
+{
+ return -EBUSY; /* cannot unregister clockevent */
+}
+
+static const struct of_device_id ostm_of_table[] __maybe_unused = {
+ { .compatible = "renesas,ostm" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, ostm_of_table);
+
+static struct platform_driver ostm_timer = {
+ .probe = ostm_probe,
+ .remove = ostm_remove,
+ .driver = {
+ .name = "ostm",
+ .of_match_table = of_match_ptr(ostm_of_table),
+ },
+};
+
+static int __init ostm_init(void)
+{
+ return platform_driver_register(&ostm_timer);
+}
+
+static void __exit ostm_exit(void)
+{
+ platform_driver_unregister(&ostm_timer);
+}
+
+early_platform_init("earlytimer", &ostm_timer);
+subsys_initcall(ostm_init);
+module_exit(ostm_exit);
+
+MODULE_AUTHOR("Chris Brandt");
+MODULE_DESCRIPTION("Renesas OSTM Timer Driver");
+MODULE_LICENSE("GPL v2");
--
2.10.1
^ permalink raw reply related
* [PATCH v2 0/3] ARM: dts: add ostm support for r7s72100
From: Chris Brandt @ 2017-01-20 21:20 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland,
Russell King, Thomas Gleixner, Geert Uytterhoeven
Cc: devicetree, linux-renesas-soc, Chris Brandt
This patch set enables the use of the newly created driver
renesas-ostm.c for the r7s72100 SoC.
v2:
* The biggest change was now the channels are independent of each
other and have separate nodes in the DT. The first probed will
be set up as a clock source, and any additional channels probed
will become a clock event.
Chris Brandt (3):
ARM: dts: r7s72100: add ostm clock to device tree
ARM: dts: r7s72100: add ostm to device tree
ARM: dts: rskrza1: add ostm DT support
arch/arm/boot/dts/r7s72100-rskrza1.dts | 8 ++++++++
arch/arm/boot/dts/r7s72100.dtsi | 25 +++++++++++++++++++++++++
include/dt-bindings/clock/r7s72100-clock.h | 4 ++++
3 files changed, 37 insertions(+)
--
2.10.1
^ permalink raw reply
* [PATCH v2 1/3] ARM: dts: r7s72100: add ostm clock to device tree
From: Chris Brandt @ 2017-01-20 21:20 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland,
Russell King, Thomas Gleixner, Geert Uytterhoeven
Cc: devicetree, linux-renesas-soc, Chris Brandt
In-Reply-To: <20170120212055.4157-1-chris.brandt@renesas.com>
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r7s72100.dtsi | 9 +++++++++
include/dt-bindings/clock/r7s72100-clock.h | 4 ++++
2 files changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 3dd427d..d5946df 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -108,6 +108,15 @@
clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
};
+ mstp5_clks: mstp5_clks@fcfe0428 {
+ #clock-cells = <1>;
+ compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xfcfe0428 4>;
+ clocks = <&p0_clk>, <&p0_clk>;
+ clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
+ clock-output-names = "ostm0", "ostm1";
+ };
+
mstp7_clks: mstp7_clks@fcfe0430 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h
index 29e01ed..ce09915 100644
--- a/include/dt-bindings/clock/r7s72100-clock.h
+++ b/include/dt-bindings/clock/r7s72100-clock.h
@@ -25,6 +25,10 @@
#define R7S72100_CLK_SCIF6 1
#define R7S72100_CLK_SCIF7 0
+/* MSTP5 */
+#define R7S72100_CLK_OSTM0 1
+#define R7S72100_CLK_OSTM1 0
+
/* MSTP7 */
#define R7S72100_CLK_ETHER 4
--
2.10.1
^ permalink raw reply related
* [PATCH v2 2/3] ARM: dts: r7s72100: add ostm to device tree
From: Chris Brandt @ 2017-01-20 21:20 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland,
Russell King, Thomas Gleixner, Geert Uytterhoeven
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Chris Brandt
In-Reply-To: <20170120212055.4157-1-chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
---
v2:
* wrap clock lines to avoid 80 char max
* split into 2 separate channel nodes
---
arch/arm/boot/dts/r7s72100.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index d5946df..47b2165 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -505,4 +505,20 @@
cap-sdio-irq;
status = "disabled";
};
+
+ ostm0: ostm@fcfec000 {
+ compatible = "renesas,r7s72100-ostm", "renesas,ostm";
+ reg = <0xfcfec000 0x30>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
+ status = "disabled";
+ };
+
+ ostm1: ostm@fcfec400 {
+ compatible = "renesas,r7s72100-ostm", "renesas,ostm";
+ reg = <0xfcfec400 0x30>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
+ status = "disabled";
+ };
};
--
2.10.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v2 3/3] ARM: dts: rskrza1: add ostm DT support
From: Chris Brandt @ 2017-01-20 21:20 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland,
Russell King, Thomas Gleixner, Geert Uytterhoeven
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Chris Brandt
In-Reply-To: <20170120212055.4157-1-chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
---
v2:
* remove part that was supposed to go in dsti
* now there is a node for each channel
---
arch/arm/boot/dts/r7s72100-rskrza1.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts
index dd44181..02b59c5 100644
--- a/arch/arm/boot/dts/r7s72100-rskrza1.dts
+++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts
@@ -61,6 +61,14 @@
status = "okay";
};
+&ostm0 {
+ status = "okay";
+};
+
+&ostm1 {
+ status = "okay";
+};
+
&scif2 {
status = "okay";
};
--
2.10.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH v3 1/3] mmc: sh_mobile_sdhi: add support for 2 clocks
From: Wolfram Sang @ 2017-01-20 21:32 UTC (permalink / raw)
To: Chris Brandt
Cc: Ulf Hansson, Rob Herring, Mark Rutland, Simon Horman,
Wolfram Sang, Geert Uytterhoeven,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Linux-Renesas
In-Reply-To: <SG2PR06MB1165089B50C28BFD333299CB8A710-ESzmfEwOt/xoAsOJh7vwSm0DtJ1/0DrXvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 640 bytes --]
> > Is this clock solely about card detection? So in cases when you have a
> > GPIO card detect, the clock isn't needed?
> >
> > Just trying to understand things a bit better...
>
> According to the hardware manual, enabling the "core" clock but not the
> "cd" clock is not a valid setting. So in our case, it's always all or
> nothing.
It was my suggestion to either handle both clocks as "virtually" one
clock so it simulates how other SDHI instances behave, or to implement
proper and intended handling of the cd clock to save some power. Chris
chose the first option and I have full understanding for that decision.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply
* Re: [PATCH v4 2/3] mmc: sh_mobile_sdhi: explain clock bindings
From: Wolfram Sang @ 2017-01-20 21:39 UTC (permalink / raw)
To: Chris Brandt
Cc: Ulf Hansson, Rob Herring, Mark Rutland, Simon Horman,
Wolfram Sang, Geert Uytterhoeven, devicetree, linux-mmc,
linux-renesas-soc
In-Reply-To: <20170120194332.1683-3-chris.brandt@renesas.com>
[-- Attachment #1: Type: text/plain, Size: 1073 bytes --]
> +- clocks: Most controllers only have 1 clock source per channel. However, on
> + some variations of this controller, the internal card detection
> + logic that exists in this controller is sectioned off to be run by a
> + separate second clock source to allow the main core clock to be turned
> + off to save power. Unfortunately, the existing driver architecture
> + does not support such a separation of clocks.
> + Additionally, it is prohibited to supply a clock to the core but not
> + to the card detect circuit. That leaves you with if separate clocks
> + are presented, you must treat them both as 1.
> + If 2 clocks are specified by the hardware, you must name them as
> + "core" and "cd".
> + If the controller only has 1 clock, naming is not required.
I know we are not perfect in this area, but DT binding should be OS
agnostic and should refrain from specifying Linux internals.
So, I'd think the comments about driver architecture should be put into
the driver, not into the bindings.
It is ultimately Ulf's decision, of course.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply
* Re: [PATCH v1 3/3] i2c: zx2967: add i2c controller driver for ZTE's zx2967 family
From: Andy Shevchenko @ 2017-01-20 21:45 UTC (permalink / raw)
To: Baoyou Xie
Cc: jun.nie, Wolfram Sang, Rob Herring, Mark Rutland,
linux-arm Mailing List, linux-i2c, devicetree,
linux-kernel@vger.kernel.org, shawnguo, xie.baoyou, chen.chaokai,
wang.qiang01
In-Reply-To: <1484901827-16369-3-git-send-email-baoyou.xie@linaro.org>
On Fri, Jan 20, 2017 at 10:43 AM, Baoyou Xie <baoyou.xie@linaro.org> wrote:
> This patch adds i2c controller driver for ZTE's zx2967 family.
>
> +config I2C_ZX2967
> + bool "ZTE zx2967 I2C support"
No module?
> + depends on ARCH_ZX
> + default y
Would architecture selects it instead?
> + help
> + Selecting this option will add ZX I2C driver.
> + If unsure, say y.
Two sentences about the same in spite 'default y'.
> +#define BW1 (u32)1
Do you really need casting?
> +#define I2C_STOP 0
> +#define I2C_MASTER (1 << 0)
BIT(0) ?
And so further.
> +#define I2C_INT_MASK 0x3f
GENMASK(6, 0) ?
> +#define I2C_ERROR_MASK (I2C_ERROR_DATA | I2C_ERROR_DEVICE)
Ditto.
GENMASK() with explicit numbers.
> +static int zx2967_i2c_flush_fifos(struct zx2967_i2c_info *zx_i2c)
> +{
> + u32 val = 0;
> + u32 offset = 0;
Useless assignments.
> +
> + if (zx_i2c->msg_rd) {
> + offset = REG_RDCONF;
> + val = I2C_RFIFO_RESET;
> + } else {
> + offset = REG_WRCONF;
> + val = I2C_WFIFO_RESET;
> + }
> +static int zx2967_i2c_empty_rx_fifo(struct zx2967_i2c_info *zx_i2c, u32 size)
> +{
> + u8 val[I2C_FIFO_MAX] = {0};
> + int i = 0;
Ditto.
> +
> + if (size == 0) {
Would it be the case?
> + dev_err(zx_i2c->dev, "size is invalid\n");
> + return -EINVAL;
> + }
And what happens even in that case if you just remove this check?
> +
> + zx2967_i2c_readsb(zx_i2c, val, REG_DATA, size);
> + for (i = 0; i < size; i++) {
> + *(zx_i2c->buf++) = val[i];
> + zx_i2c->residue--;
> + if (zx_i2c->residue <= 0)
> + break;
> +static int zx2967_i2c_fill_tx_fifo(struct zx2967_i2c_info *zx_i2c)
> +{
> + u8 *buf = zx_i2c->buf;
> + size_t residue = zx_i2c->residue;
> +
> + if (residue == 0) {
> + dev_err(zx_i2c->dev, "residue is %d\n", (int)residue);
> + return -EINVAL;
> + }
Ditto.
> +static void zx2967_enable_tenbit(struct zx2967_i2c_info *zx_i2c, __u16 addr)
> +{
> + u16 val = ((addr >> 7) & 0x7);
Redundant parens.
> + if (val > 0) {
if (!val)
return;
> +static int zx2967_i2c_xfer_msg(struct zx2967_i2c_info *zx_i2c,
> + struct i2c_msg *msg
> +{
> + unsigned long time_left = 0;
> + unsigned int i = 0;
Redundant assignment.
> +
> + if (msg->len == 0)
if (!msg...)
> + return -EINVAL;
> +static int zx2967_i2c_xfer(struct i2c_adapter *adap,
> + struct i2c_msg *msgs, int num)
> +{
> + int i;
> + int ret = 0;
Redundant. See below.
> + struct zx2967_i2c_info *zx_i2c = i2c_get_adapdata(adap);
Reverse tree, please.
> +
> + if (zx_i2c->is_suspended)
> + return -EBUSY;
> +
> + zx2967_i2c_writel(zx_i2c, (msgs->addr & 0x7f), REG_DEVADDR_L);
> + zx2967_i2c_writel(zx_i2c, (msgs->addr >> 7) & 0x7, REG_DEVADDR_H);
> + if (zx2967_i2c_readl(zx_i2c, REG_DEVADDR_H) > 0)
> + zx2967_enable_tenbit(zx_i2c, msgs->addr);
> +
> + for (i = 0; i < num; i++) {
int ret;
> + ret = zx2967_i2c_xfer_msg(zx_i2c, &msgs[i]);
> + if (num > 1)
> + usleep_range(1000, 2000);
> + if (ret)
> + break;
return ret;
> + }
> +
> + return ret ?: i;
return i;
And looking now, how i can't be num here?
> +}
> +{
> + struct zx2967_i2c_info *zx_i2c = i2c_get_adapdata(adap);
> + u32 val;
> + u8 buf[2];
> + unsigned long time_left;
Reverse tree.
> + usleep_range(1000, 2000);
> + switch (size) {
> + case I2C_SMBUS_BYTE:
> + case I2C_SMBUS_BYTE_DATA:
> + val = zx2967_i2c_readl(zx_i2c, REG_DATA);
> + data->byte = val;
> + break;
> + case I2C_SMBUS_WORD_DATA:
> + case I2C_SMBUS_PROC_CALL:
> + buf[0] = zx2967_i2c_readl(zx_i2c, REG_DATA);
> + buf[1] = zx2967_i2c_readl(zx_i2c, REG_DATA);
> + data->word = (buf[0] << 8) | buf[1];
> + break;
> + default:
> + dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
> + return -EOPNOTSUPP;
> + }
> +
> + return 0;
> +}
I would revisit those several loooong functions for splitting/refactoring.
> +
> +static u32 zx2967_i2c_func(struct i2c_adapter *adap)
> +{
> + return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
> + I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
> + I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
> + I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
> +}
It's just
#define XXX YY1 | YY2 | ...
> +#ifdef CONFIG_PM
> +static int zx2967_i2c_suspend(struct device *dev)
Switch to __maybe_unuse.
> +static int zx2967_i2c_probe(struct platform_device *pdev)
> +{
> + struct resource *res;
> + struct zx2967_i2c_info *zx_i2c = NULL;
Redundant assignment.
> + struct clk *clk;
> + void __iomem *reg_base;
Reverse tree for all above until top of this function.
> + int ret = 0;
Redundant assignment.
> +
> + zx_i2c = devm_kzalloc(&pdev->dev, sizeof(*zx_i2c), GFP_KERNEL);
> + if (!zx_i2c)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(&pdev->dev, "missing io resource\n");
> + return -EINVAL;
> + }
> +
Completely redundant lines of code.
> + reg_base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(reg_base))
> + return PTR_ERR(reg_base);
> +
> + clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(clk)) {
> + dev_err(&pdev->dev, "missing controller clock");
> + return PTR_ERR(clk);
> + }
> +
> + ret = clk_prepare_enable(clk);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to enable i2c_clk\n");
> + return ret;
> + }
> +
> + of_property_read_u32(pdev->dev.of_node,
> + "clock-frequency", &zx_i2c->clk_freq);
devce_property_read_uXX();
> + zx_i2c->reg_base = reg_base;
> + zx_i2c->clk = clk;
> + zx_i2c->irq = platform_get_irq(pdev, 0);
Is this optional?
Otherwise has to be checked.
> + zx_i2c->id = pdev->id;
> + zx_i2c->dev = &pdev->dev;
> +
> + zx_i2c->pin_scl = devm_pinctrl_get_select(&pdev->dev, "scl");
> + if (IS_ERR(zx_i2c->pin_scl))
> + dev_info(&pdev->dev, "scl pin is not specified in dts\n");
> +
> + zx_i2c->pin_sda = devm_pinctrl_get_select(&pdev->dev, "sda");
> + if (IS_ERR(zx_i2c->pin_sda))
> + dev_info(&pdev->dev, "sda pin is not specified in dts\n");
> +
> + spin_lock_init(&zx_i2c->lock);
> + init_completion(&zx_i2c->complete);
> + platform_set_drvdata(pdev, zx_i2c);
> +
> + ret = zx2967_i2c_reset_hardware(zx_i2c);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to initialize i2c controller\n");
> + goto unprepare_clk;
> + }
> +
> + ret = devm_request_irq(&pdev->dev, zx_i2c->irq,
> + zx2967_i2c_isr, 0, dev_name(&pdev->dev), zx_i2c);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to request irq %i\n", zx_i2c->irq);
> + goto unprepare_clk;
> + }
> +
> + i2c_set_adapdata(&zx_i2c->adap, zx_i2c);
> + zx_i2c->adap.owner = THIS_MODULE;
Do you need this?
> + zx_i2c->adap.class = I2C_CLASS_DEPRECATED;
> + strlcpy(zx_i2c->adap.name, "zx2967 i2c adapter",
> + sizeof(zx_i2c->adap.name));
> + zx_i2c->adap.algo = &zx2967_i2c_algo;
> + zx_i2c->adap.dev.parent = &pdev->dev;
> + zx_i2c->adap.nr = pdev->id;
> + zx_i2c->adap.dev.of_node = pdev->dev.of_node;
> +
> + ret = i2c_add_numbered_adapter(&zx_i2c->adap);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to add zx2967 i2c adapter\n");
> + goto unprepare_clk;
> + }
> +
> + return 0;
> +
> +unprepare_clk:
err_clk_unprepare:
> + clk_unprepare(zx_i2c->clk);
Perhaps clk_disable_unprepare();
> + return ret;
> +}
> +
> +static int zx2967_i2c_remove(struct platform_device *pdev)
> +{
> + struct zx2967_i2c_info *zx_i2c = platform_get_drvdata(pdev);
> +
> + i2c_del_adapter(&zx_i2c->adap);
> + clk_unprepare(zx_i2c->clk);
Ditto.
> +
> + return 0;
> +}
> +MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
> +MODULE_DESCRIPTION("ZTE zx2967 I2C Bus Controller driver");
> +MODULE_LICENSE("GPL v2");
When bool in Kconfig this all redundant.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* [PATCH V2 1/2] dt-bindings: leds: document new led-triggers property
From: Rafał Miłecki @ 2017-01-20 21:56 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: linux-usb-u79uwXL29TY76Z2rM5mHXA,
linux-leds-u79uwXL29TY76Z2rM5mHXA, Richard Purdie,
Jacek Anaszewski, Pavel Machek, devicetree-u79uwXL29TY76Z2rM5mHXA,
Rob Herring, Mark Rutland, Rafał Miłecki
From: Rafał Miłecki <rafal-g1n6cQUeyibVItvQsEIGlw@public.gmane.org>
Some LEDs can be related to particular devices described in DT. This
property allows specifying such relations. E.g. USB LED should usually
be used to indicate some USB port(s) state.
Signed-off-by: Rafał Miłecki <rafal-g1n6cQUeyibVItvQsEIGlw@public.gmane.org>
---
V2: Replace "usb-ports" with "led-triggers" property which is more generic and
allows specifying other devices as well.
When bindings patch is related to some followup implementation, they usually go
through the same tree.
Greg: this patch is based on top of e64b8cc72bf9 ("DT: leds: Improve examples by
adding some context") from kernel/git/j.anaszewski/linux-leds.git . Is there any
way to solve this dependency issue? Or should this patch wait until 3.11 is
released?
---
Documentation/devicetree/bindings/leds/common.txt | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/leds/common.txt b/Documentation/devicetree/bindings/leds/common.txt
index 24b656014089..17632a041196 100644
--- a/Documentation/devicetree/bindings/leds/common.txt
+++ b/Documentation/devicetree/bindings/leds/common.txt
@@ -49,6 +49,17 @@ Optional properties for child nodes:
- panic-indicator : This property specifies that the LED should be used,
if at all possible, as a panic indicator.
+- led-triggers : List of devices that should trigger this LED activity. Some
+ LEDs can be related to a specific device and should somehow
+ indicate its state. E.g. USB 2.0 LED may react to device(s) in
+ a USB 2.0 port(s). Another common example is switch or router
+ with multiple Ethernet ports each of them having its own LED
+ assigned (assuming they are not hardwired).
+ In such cases this property should contain phandle(s) of
+ related device(s). In many cases LED can be related to more
+ than one device (e.g. one USB LED vs. multiple USB ports) so a
+ list of entries can be specified.
+
Required properties for flash LED child nodes:
- flash-max-microamp : Maximum flash LED supply current in microamperes.
- flash-max-timeout-us : Maximum timeout in microseconds after which the flash
@@ -69,6 +80,11 @@ gpio-leds {
linux,default-trigger = "heartbeat";
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
};
+
+ usb {
+ gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+ led-triggers = <&ohci_port1>, <&ehci_port1>;
+ };
};
max77693-led {
--
2.11.0
--
To unsubscribe from this list: send the line "unsubscribe linux-usb" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH V2 2/2] usb: core: read USB ports from DT in the usbport LED trigger driver
From: Rafał Miłecki @ 2017-01-20 21:56 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: linux-usb, linux-leds, Richard Purdie, Jacek Anaszewski,
Pavel Machek, devicetree, Rob Herring, Mark Rutland,
Rafał Miłecki
In-Reply-To: <20170120215605.15728-1-zajec5@gmail.com>
From: Rafał Miłecki <rafal@milecki.pl>
This adds support for using description of relation between LEDs and USB
ports from device tree. If DT has properly described LEDs, trigger will
know when to turn them on.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
V2: Update to use "led-triggers"
---
drivers/usb/core/ledtrig-usbport.c | 54 ++++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/drivers/usb/core/ledtrig-usbport.c b/drivers/usb/core/ledtrig-usbport.c
index 1713248ab15a..aee80748eb7a 100644
--- a/drivers/usb/core/ledtrig-usbport.c
+++ b/drivers/usb/core/ledtrig-usbport.c
@@ -11,8 +11,10 @@
#include <linux/device.h>
#include <linux/leds.h>
#include <linux/module.h>
+#include <linux/of.h>
#include <linux/slab.h>
#include <linux/usb.h>
+#include <linux/usb/of.h>
struct usbport_trig_data {
struct led_classdev *led_cdev;
@@ -123,6 +125,55 @@ static const struct attribute_group ports_group = {
* Adding & removing ports
***************************************/
+/**
+ * usbport_trig_port_observed - Check if port should be observed
+ */
+static bool usbport_trig_port_observed(struct usbport_trig_data *usbport_data,
+ struct usb_device *usb_dev, int port1)
+{
+ struct device *dev = usbport_data->led_cdev->dev;
+ struct device_node *led_np = dev->of_node;
+ struct of_phandle_args args;
+ struct device_node *port_np;
+ int count, i;
+
+ if (!led_np)
+ return false;
+
+ /* Get node of port being added */
+ port_np = usb_of_get_child_node(usb_dev->dev.of_node, port1);
+ if (!port_np)
+ return false;
+
+ /* Amount of ports this LED references */
+ count = of_count_phandle_with_args(led_np, "led-triggers", NULL);
+ if (count < 0) {
+ dev_warn(dev, "Failed to get USB ports for %s\n",
+ led_np->full_name);
+ return false;
+ }
+
+ /* Check if port is on this LED's list */
+ for (i = 0; i < count; i++) {
+ int err;
+
+ err = of_parse_phandle_with_args(led_np, "led-triggers", NULL,
+ i, &args);
+ if (err) {
+ dev_err(dev, "Failed to get USB port phandle at index %d: %d\n",
+ i, err);
+ continue;
+ }
+
+ of_node_put(args.np);
+
+ if (args.np == port_np)
+ return true;
+ }
+
+ return false;
+}
+
static int usbport_trig_add_port(struct usbport_trig_data *usbport_data,
struct usb_device *usb_dev,
const char *hub_name, int portnum)
@@ -141,6 +192,8 @@ static int usbport_trig_add_port(struct usbport_trig_data *usbport_data,
port->data = usbport_data;
port->hub = usb_dev;
port->portnum = portnum;
+ port->observed = usbport_trig_port_observed(usbport_data, usb_dev,
+ portnum);
len = strlen(hub_name) + 8;
port->port_name = kzalloc(len, GFP_KERNEL);
@@ -255,6 +308,7 @@ static void usbport_trig_activate(struct led_classdev *led_cdev)
if (err)
goto err_free;
usb_for_each_dev(usbport_data, usbport_trig_add_usb_dev_ports);
+ usbport_trig_update_count(usbport_data);
/* Notifications */
usbport_data->nb.notifier_call = usbport_trig_notify,
--
2.11.0
^ permalink raw reply related
* [EXAMPLE V2 3/2] ARM: BCM53573: Specify ports for USB LED for Tenda AC9
From: Rafał Miłecki @ 2017-01-20 21:56 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: linux-usb, linux-leds, Richard Purdie, Jacek Anaszewski,
Pavel Machek, devicetree, Rob Herring, Mark Rutland,
Rafał Miłecki
In-Reply-To: <20170120215605.15728-1-zajec5@gmail.com>
From: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
This patch *should not* be applied. It's only an EXAMPLE and that's why it uses
weird 3/2 number.
It's a proof of concept, it was tested & will be submitted through ARM tree if
previous patches get accepted.
---
arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
index 4403ae8790c2..f484d17a2270 100644
--- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
+++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
@@ -24,6 +24,7 @@
compatible = "gpio-leds";
usb {
+ led-triggers = <&ohci_port1>, <&ehci_port1>;
label = "bcm53xx:blue:usb";
gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-off";
--
2.11.0
^ permalink raw reply related
* Re: [PATCH 4/8] clk: renesas: cpg-mssr: Add support for reset control
From: Niklas Söderlund @ 2017-01-20 22:03 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Mark Rutland, devicetree, Magnus Damm, Michael Turquette,
Stephen Boyd, linux-kernel, Rob Herring, linux-renesas-soc,
Simon Horman, Philipp Zabel, linux-clk, linux-arm-kernel
In-Reply-To: <1484921306-9967-5-git-send-email-geert+renesas@glider.be>
Hi Geert,
Nice patch! It took me a while to understand why you didn't need to read
the register before writing to it in cpg_mssr_deassert() :-)
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
On 2017-01-20 15:08:22 +0100, Geert Uytterhoeven wrote:
> Add optional support for the Reset Control feature of the Renesas Clock
> Pulse Generator / Module Standby and Software Reset module on R-Car
> Gen2, R-Car Gen3, and RZ/G1 SoCs.
>
> This allows to reset SoC devices using the Reset Controller API.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> drivers/clk/renesas/renesas-cpg-mssr.c | 122 +++++++++++++++++++++++++++++++++
> 1 file changed, 122 insertions(+)
>
> diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
> index f1161a585c57e433..ea4af714ac14603a 100644
> --- a/drivers/clk/renesas/renesas-cpg-mssr.c
> +++ b/drivers/clk/renesas/renesas-cpg-mssr.c
> @@ -16,6 +16,7 @@
> #include <linux/clk.h>
> #include <linux/clk-provider.h>
> #include <linux/clk/renesas.h>
> +#include <linux/delay.h>
> #include <linux/device.h>
> #include <linux/init.h>
> #include <linux/mod_devicetable.h>
> @@ -25,6 +26,7 @@
> #include <linux/platform_device.h>
> #include <linux/pm_clock.h>
> #include <linux/pm_domain.h>
> +#include <linux/reset-controller.h>
> #include <linux/slab.h>
>
> #include <dt-bindings/clock/renesas-cpg-mssr.h>
> @@ -96,6 +98,7 @@
> /**
> * Clock Pulse Generator / Module Standby and Software Reset Private Data
> *
> + * @rcdev: Optional reset controller entity
> * @dev: CPG/MSSR device
> * @base: CPG/MSSR register block base address
> * @rmw_lock: protects RMW register accesses
> @@ -105,6 +108,9 @@
> * @last_dt_core_clk: ID of the last Core Clock exported to DT
> */
> struct cpg_mssr_priv {
> +#ifdef CONFIG_RESET_CONTROLLER
> + struct reset_controller_dev rcdev;
> +#endif
> struct device *dev;
> void __iomem *base;
> spinlock_t rmw_lock;
> @@ -494,6 +500,118 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev,
> return 0;
> }
>
> +#ifdef CONFIG_RESET_CONTROLLER
> +
> +#define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev)
> +
> +static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
> + unsigned int reg = id / 32;
> + unsigned int bit = id % 32;
> + u32 bitmask = BIT(bit);
> + unsigned long flags;
> + u32 value;
> +
> + dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
> +
> + /* Reset module */
> + spin_lock_irqsave(&priv->rmw_lock, flags);
> + value = readl(priv->base + SRCR(reg));
> + value |= bitmask;
> + writel(value, priv->base + SRCR(reg));
> + spin_unlock_irqrestore(&priv->rmw_lock, flags);
> +
> + /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
> + udelay(35);
> +
> + /* Release module from reset state */
> + writel(bitmask, priv->base + SRSTCLR(reg));
> +
> + return 0;
> +}
> +
> +static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> + struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
> + unsigned int reg = id / 32;
> + unsigned int bit = id % 32;
> + unsigned long flags;
> + u32 value;
> +
> + dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
> +
> + spin_lock_irqsave(&priv->rmw_lock, flags);
> + value = readl(priv->base + SRCR(reg));
> + writel(value | BIT(bit), priv->base + SRCR(reg));
> + spin_unlock_irqrestore(&priv->rmw_lock, flags);
> + return 0;
> +}
> +
> +static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
> + unsigned int reg = id / 32;
> + unsigned int bit = id % 32;
> +
> + dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
> +
> + writel(BIT(bit), priv->base + SRSTCLR(reg));
> + return 0;
> +}
> +
> +static int cpg_mssr_status(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
> + unsigned int reg = id / 32;
> + unsigned int bit = id % 32;
> +
> + return !!(readl(priv->base + SRCR(reg)) & BIT(bit));
> +}
> +
> +static const struct reset_control_ops cpg_mssr_reset_ops = {
> + .reset = cpg_mssr_reset,
> + .assert = cpg_mssr_assert,
> + .deassert = cpg_mssr_deassert,
> + .status = cpg_mssr_status,
> +};
> +
> +static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev,
> + const struct of_phandle_args *reset_spec)
> +{
> + struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
> + unsigned int unpacked = reset_spec->args[0];
> + unsigned int idx = MOD_CLK_PACK(unpacked);
> +
> + if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {
> + dev_err(priv->dev, "Invalid reset index %u\n", unpacked);
> + return -EINVAL;
> + }
> +
> + return idx;
> +}
> +
> +static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
> +{
> + priv->rcdev.ops = &cpg_mssr_reset_ops;
> + priv->rcdev.of_node = priv->dev->of_node;
> + priv->rcdev.of_reset_n_cells = 1;
> + priv->rcdev.of_xlate = cpg_mssr_reset_xlate;
> + priv->rcdev.nr_resets = priv->num_mod_clks;
> + return devm_reset_controller_register(priv->dev, &priv->rcdev);
> +}
> +
> +#else /* !CONFIG_RESET_CONTROLLER */
> +static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
> +{
> + return 0;
> +}
> +#endif /* !CONFIG_RESET_CONTROLLER */
> +
> +
> static const struct of_device_id cpg_mssr_match[] = {
> #ifdef CONFIG_ARCH_R8A7743
> {
> @@ -591,6 +709,10 @@ static int __init cpg_mssr_probe(struct platform_device *pdev)
> if (error)
> return error;
>
> + error = cpg_mssr_reset_controller_register(priv);
> + if (error)
> + return error;
> +
> return 0;
> }
>
> --
> 1.9.1
>
--
Regards,
Niklas Söderlund
^ permalink raw reply
* [PATCH 00/18] ARM64: meson: DT cleanups
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Carlo Caione, Kevin Hilman,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andreas Färber,
devicetree-u79uwXL29TY76Z2rM5mHXA
Hello,
This series fixes several cosmetic issues, on top of v4.11/dt64 branch.
Patches 3-5 rename a node, the rest should all be non-functional changes.
Patches 10-18 could be squashed if desired.
Regards,
Andreas
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Andreas Färber (18):
Documentation: devicetree: amlogic: Reorder boards
ARM64: dts: amlogic: Sort Makefile
ARM64: dts: meson-gxbb-vega-s95: Fix Wifi node name
ARM64: dts: meson-gxbb-p20x: Fix Wifi node name
ARM64: dts: meson-gx-p23x-q20x: Fix Wifi node name
ARM64: dts: meson-gxm-nexbox-a1: Drop UART comment
ARM64: dts: meson-gxl-s905x: Comment typo fix
ARM64: dts: meson-gxm: Drop trailing white line
ARM64: dts: meson-gxbb-wetek-hub: Reference CVBS node by label
ARM64: dts: meson-gxbb: Reorder nodes
ARM64: dts: meson-gxbb-odroidc2: Reorder nodes
ARM64: dts: meson-gxbb-vega-s95: Reorder nodes
ARM64: dts: meson-gxbb-nexbox-a95x: Reorder nodes
ARM64: dts: meson-gxbb-p20x: Reorder nodes
ARM64: dts: meson-gxl: Reorder nodes
ARM64: dts: meson-gxl-s905x-nexbox-a95x: Reorder nodes
ARM64: dts: meson-gxm-nexbox-a1: Reorder nodes
ARM64: dts: meson-gx-p23x-q20x: Reorder nodes
Documentation/devicetree/bindings/arm/amlogic.txt | 19 ++++--
arch/arm64/boot/dts/amlogic/Makefile | 4 +-
.../arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 26 ++++----
.../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 28 ++++----
.../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 52 +++++++--------
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 58 ++++++++---------
.../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 53 ++++++++-------
.../boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 6 +-
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 76 +++++++++++-----------
.../dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts | 28 ++++----
arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi | 2 +-
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 40 ++++++------
.../arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 59 +++++++++--------
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 1 -
14 files changed, 228 insertions(+), 224 deletions(-)
--
2.10.2
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 01/18] Documentation: devicetree: amlogic: Reorder boards
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic
Cc: Carlo Caione, Kevin Hilman, linux-arm-kernel, linux-kernel,
Andreas Färber, Rob Herring, Mark Rutland, devicetree
In-Reply-To: <20170120222118.21476-1-afaerber@suse.de>
Enforce groupment by SoCs and order alphabetically within the group
(with some exceptions). This should facilitate adding new boards.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
Documentation/devicetree/bindings/arm/amlogic.txt | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
index c246cd2730d9..b03d23c9ea78 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.txt
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -29,23 +29,30 @@ Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s912", "amlogic,meson-gxm";
-Board compatible values:
+Board compatible values (grouped by SoC):
+
- "geniatech,atv1200" (Meson6)
+
- "minix,neo-x8" (Meson8)
- - "tronfy,mxq" (Meson8b)
+
- "hardkernel,odroid-c1" (Meson8b)
+ - "tronfy,mxq" (Meson8b)
+
+ - "amlogic,p200" (Meson gxbb)
+ - "amlogic,p201" (Meson gxbb)
+ - "hardkernel,odroid-c2" (Meson gxbb)
+ - "nexbox,a95x" (Meson gxbb or Meson gxl s905x)
- "tronsmart,vega-s95-pro", "tronsmart,vega-s95" (Meson gxbb)
- "tronsmart,vega-s95-meta", "tronsmart,vega-s95" (Meson gxbb)
- "tronsmart,vega-s95-telos", "tronsmart,vega-s95" (Meson gxbb)
- - "hardkernel,odroid-c2" (Meson gxbb)
- - "amlogic,p200" (Meson gxbb)
- - "amlogic,p201" (Meson gxbb)
- "wetek,hub" (Meson gxbb)
- "wetek,play2" (Meson gxbb)
+
- "amlogic,p212" (Meson gxl s905x)
+
- "amlogic,p230" (Meson gxl s905d)
- "amlogic,p231" (Meson gxl s905d)
+
- "amlogic,q200" (Meson gxm s912)
- "amlogic,q201" (Meson gxm s912)
- - "nexbox,a95x" (Meson gxbb or Meson gxl s905x)
- "nexbox,a1" (Meson gxm s912)
--
2.10.2
^ permalink raw reply related
* [PATCH 02/18] ARM64: dts: amlogic: Sort Makefile
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic
Cc: Mark Rutland, devicetree, Kevin Hilman, Will Deacon, linux-kernel,
Rob Herring, Catalin Marinas, Carlo Caione, Andreas Färber,
linux-arm-kernel
In-Reply-To: <20170120222118.21476-1-afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
arch/arm64/boot/dts/amlogic/Makefile | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index 3f94bce33b7f..efcd1763a82d 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -7,13 +7,13 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-hub.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-play2.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
-dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb
-dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
--
2.10.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 03/18] ARM64: dts: meson-gxbb-vega-s95: Fix Wifi node name
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic
Cc: Mark Rutland, devicetree, Martin Blumenstingl, Kevin Hilman,
Will Deacon, linux-kernel, Rob Herring, Catalin Marinas,
Carlo Caione, Andreas Färber, linux-arm-kernel
In-Reply-To: <20170120222118.21476-1-afaerber@suse.de>
bcrmf -> brcmf
Fixes: ab5b24fdd2d5 ("ARM64: dts: meson-gxbb-vega-s95: Add SD/SDIO/MMC and PWM nodes")
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
index 86709929fd20..e688e8971a95 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
@@ -167,7 +167,7 @@
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
- brcmf: bcrmf@1 {
+ brcmf: brcmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
--
2.10.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 04/18] ARM64: dts: meson-gxbb-p20x: Fix Wifi node name
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic
Cc: Mark Rutland, devicetree, Neil Armstrong, Kevin Hilman,
Will Deacon, linux-kernel, Rob Herring, Catalin Marinas,
Carlo Caione, Andreas Färber, linux-arm-kernel
In-Reply-To: <20170120222118.21476-1-afaerber@suse.de>
bcrmf -> brcmf
Fixes: ab3943fe57a2 ("ARM64: dts: meson-gxbb: Add P20x Wifi SDIO support")
Cc: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
index 4a96e0f6f926..5183c5ce90c6 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
@@ -193,7 +193,7 @@
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
- brcmf: bcrmf@1 {
+ brcmf: brcmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
--
2.10.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 05/18] ARM64: dts: meson-gx-p23x-q20x: Fix Wifi node name
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic
Cc: Carlo Caione, Kevin Hilman, linux-arm-kernel, linux-kernel,
Andreas Färber, Neil Armstrong, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, devicetree
In-Reply-To: <20170120222118.21476-1-afaerber@suse.de>
bcrmf -> brcmf
Fixes: bb51b5350d2f ("ARM64: dts: Add support for Meson GXM")
Cc: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
index 7a078bef04cd..419c46cc64e4 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
@@ -133,7 +133,7 @@
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
- brcmf: bcrmf@1 {
+ brcmf: brcmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
--
2.10.2
^ permalink raw reply related
* [PATCH 06/18] ARM64: dts: meson-gxm-nexbox-a1: Drop UART comment
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic
Cc: Carlo Caione, Kevin Hilman, linux-arm-kernel, linux-kernel,
Andreas Färber, Neil Armstrong, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, devicetree
In-Reply-To: <20170120222118.21476-1-afaerber@suse.de>
Product pictures show no DB9 connector, so this seems copy&paste.
Cc: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
index 5a337d339df1..439060652689 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
@@ -102,7 +102,6 @@
};
};
-/* This UART is brought out to the DB9 connector */
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
--
2.10.2
^ permalink raw reply related
* [PATCH 07/18] ARM64: dts: meson-gxl-s905x: Comment typo fix
From: Andreas Färber @ 2017-01-20 22:21 UTC (permalink / raw)
To: linux-amlogic
Cc: Carlo Caione, Kevin Hilman, linux-arm-kernel, linux-kernel,
Andreas Färber, Neil Armstrong, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, devicetree
In-Reply-To: <20170120222118.21476-1-afaerber@suse.de>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
index 08237ee1e362..d49ee3c04dd7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
@@ -47,7 +47,7 @@
compatible = "amlogic,s905x", "amlogic,meson-gxl";
};
-/* S905X Only has access to its internal PHY */
+/* S905X only has access to its internal PHY */
ðmac {
phy-mode = "rmii";
phy-handle = <&internal_phy>;
--
2.10.2
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox