* Re: [PATCH] of/platform: dynamic: Use of_platform_bus_create() to create devices
From: Alexander Sverdlin @ 2017-01-23 15:07 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Frank Rowand,
Pantelis Antoniou, Grant Likely
In-Reply-To: <CAL_JsqKb8KUgit-q_cOON8VgZBsrXEQd2EcC0iF=ou_271Vg_w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hi Rob,
On 21/01/17 20:51, Rob Herring wrote:
> On Fri, Jan 20, 2017 at 11:38 AM, Alexander Sverdlin
> <alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org> wrote:
>> Hello Rob,
>>
>> On 27/10/16 15:00, Rob Herring wrote:
>>>> @@ -534,15 +535,15 @@ static int of_platform_notify(struct notifier_block *nb,
>>>>
>>>> /* pdev_parent may be NULL when no bus platform device */
>>>> pdev_parent = of_find_device_by_node(rd->dn->parent);
>>>> - pdev = of_platform_device_create(rd->dn, NULL,
>>>> - pdev_parent ? &pdev_parent->dev : NULL);
>>>> + ret = of_platform_bus_create(rd->dn, of_default_bus_match_table,
>>>> + NULL, pdev_parent ?
>>>> + &pdev_parent->dev : NULL, true);
>>> I think this should be of_platform_default_populate() instead.
>> I've just tested: it cannot be. It calls of_platform_populate(), which ignores "status" property.
>> This not only brakes half of the unit tests, but also would change the existing behavior of
>> overlays (they will completely ignore "status" too).
> That's a bug. I assume that's only at the 1st level or things would be
> completely broken.
well, after two unsuccessful attempts to use of_platform_default_populate() in of_platform_notify()
I see what the actual problem is: of_platform_*populate() do not populate the root node itself,
therefore they are not suitable for of_platform_notify().
--
Best regards,
Alexander Sverdlin.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 3/3] PCI: imx6: Add code to support i.MX7D
From: Andrey Smirnov @ 2017-01-23 15:02 UTC (permalink / raw)
To: Rob Herring
Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA, Andrey Yurovsky, Richard Zhu,
Lucas Stach, Bjorn Helgaas, Fabio Estevam, Shawn Guo,
Mark Rutland, Lee Jones,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel
In-Reply-To: <20170123145204.5lablvhf7m2hf3na@rob-hp-laptop>
On Mon, Jan 23, 2017 at 6:52 AM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Thu, Jan 19, 2017 at 08:36:31AM -0800, Andrey Smirnov wrote:
>> Add various bits of code needed to support i.MX7D variant of the IP.
>>
>> Cc: yurovsky-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
>> Cc: Richard Zhu <hongxing.zhu-3arQi8VN3Tc@public.gmane.org>
>> Cc: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
>> Cc: Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
>> Cc: Fabio Estevam <festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
>> Cc: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> Signed-off-by: Andrey Smirnov <andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>> .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 6 +-
>> drivers/pci/host/pci-imx6.c | 188 ++++++++++++++++++---
>> include/linux/mfd/syscon/imx7-gpc.h | 18 ++
>> include/linux/mfd/syscon/imx7-iomuxc-gpr.h | 4 +
>> include/linux/mfd/syscon/imx7-src.h | 18 ++
>> 5 files changed, 208 insertions(+), 26 deletions(-)
>> create mode 100644 include/linux/mfd/syscon/imx7-gpc.h
>> create mode 100644 include/linux/mfd/syscon/imx7-src.h
>>
>> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
>> index 83aeb1f..20b9382 100644
>> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
>> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
>> @@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
>> and thus inherits all the common properties defined in designware-pcie.txt.
>>
>> Required properties:
>> -- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie"
>> +- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie",
>> + "fsl,imx6qp-pcie", "fsl,imx7d-pcie"
>
> Please reformat to one valid combination per line.
Noted for v2, thanks.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 3/3] PCI: imx6: Add code to support i.MX7D
From: Rob Herring @ 2017-01-23 14:52 UTC (permalink / raw)
To: Andrey Smirnov
Cc: linux-pci, yurovsky, Richard Zhu, Lucas Stach, Bjorn Helgaas,
Fabio Estevam, Shawn Guo, Mark Rutland, Lee Jones,
linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20170119163631.10668-4-andrew.smirnov@gmail.com>
On Thu, Jan 19, 2017 at 08:36:31AM -0800, Andrey Smirnov wrote:
> Add various bits of code needed to support i.MX7D variant of the IP.
>
> Cc: yurovsky@gmail.com
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Lee Jones <lee.jones@linaro.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
> .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 6 +-
> drivers/pci/host/pci-imx6.c | 188 ++++++++++++++++++---
> include/linux/mfd/syscon/imx7-gpc.h | 18 ++
> include/linux/mfd/syscon/imx7-iomuxc-gpr.h | 4 +
> include/linux/mfd/syscon/imx7-src.h | 18 ++
> 5 files changed, 208 insertions(+), 26 deletions(-)
> create mode 100644 include/linux/mfd/syscon/imx7-gpc.h
> create mode 100644 include/linux/mfd/syscon/imx7-src.h
>
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> index 83aeb1f..20b9382 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> @@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
> and thus inherits all the common properties defined in designware-pcie.txt.
>
> Required properties:
> -- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie"
> +- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie",
> + "fsl,imx6qp-pcie", "fsl,imx7d-pcie"
Please reformat to one valid combination per line.
> - reg: base address and length of the PCIe controller
> - interrupts: A list of interrupt outputs of the controller. Must contain an
> entry for each entry in the interrupt-names property.
> @@ -34,6 +35,9 @@ Additional required properties for imx6sx-pcie:
> - clock names: Must include the following additional entries:
> - "pcie_inbound_axi"
>
> +Additional required properties for imx7d-pcie:
> +- pcie-phy-supply: Should specify the regulator supplying PCIe PHY
> +
> Example:
>
> pcie@0x01000000 {
^ permalink raw reply
* RE: [PATCH v5 1/3] mmc: sh_mobile_sdhi: add support for 2 clocks
From: Chris Brandt @ 2017-01-23 14:48 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Ulf Hansson, Rob Herring, Mark Rutland, Simon Horman,
Wolfram Sang, devicetree@vger.kernel.org, Linux MMC List,
Linux-Renesas
In-Reply-To: <CAMuHMdWwqa7CbNCRr8q60hDVsj243-ZjHCPp+o9R2a6Dg7YNWQ@mail.gmail.com>
Hi Geert,
On Monday, January 23, 2017, Geert Uytterhoeven:
> > @@ -190,6 +191,12 @@ static int sh_mobile_sdhi_clk_enable(struct
> tmio_mmc_host *host)
> > if (ret < 0)
> > return ret;
> >
> > + ret = clk_prepare_enable(priv->clk_cd);
> > + if (ret < 0) {
> > + clk_disable_unprepare(priv->clk);
> > + return ret;
> > + }
> > +
>
> As enabling the "core" clock but not the "cd" clock is not a valid setting,
> shouldn't the cd clock be enabled first?
I'm pretty sure the chip designers just didn't want you to 'use' the
peripheral with that clock configuration, and we are not using it in
between those 2 lines so I personally think it's fine.
If I need to change it to get it approved, let me know and I'll change
the code around.
(In reality, I checked and the SDHI does work with the cd clock off,
but I don't know if the restriction in the spec was because they never
fully tested the use of it that way because it wasn't a design goal for
them.)
> > /*
> > * The clock driver may not know what maximum frequency
> > * actually works, so it should be set with the max-frequency
> > @@ -255,6 +262,8 @@ static void sh_mobile_sdhi_clk_disable(struct
> tmio_mmc_host *host)
> > struct sh_mobile_sdhi *priv = host_to_priv(host);
> >
> > clk_disable_unprepare(priv->clk);
> > + if (priv->clk_cd)
>
> No need to check for a NULL pointer first.
OK, I see that IS_ERR_OR_NULL(clk) is done for clk_disable_unprepare so
I'll take the check out.
Thank you.
> > + clk_disable_unprepare(priv->clk_cd);
>
> Disabling is already done in the correct order ;-)
I guess you could get into some theoretical technical discussion around
if it is OK to enable/disable the clocks in any order (as long as you
don't use the SDHI in between), then you would want to enable the cd
circuit last, and disable it first so you would ensure that no cd
interrupts are being registered when the core clock is off?
In that case, the current enable order should remain but the disable
order should change.
Opinions???
Thank you,
Chris
^ permalink raw reply
* Re: [PATCH v4 0/9] Implement clocksource for rockchip SoC using rockchip timer
From: Daniel Lezcano @ 2017-01-23 14:47 UTC (permalink / raw)
To: Alexander Kochetkov
Cc: LKML, devicetree-u79uwXL29TY76Z2rM5mHXA, LAK,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Heiko Stuebner,
Thomas Gleixner, Mark Rutland, Rob Herring, Russell King,
Caesar Wang, Huang Tao
In-Reply-To: <E6DD9335-0D2D-47CB-8098-5F96C2E08139-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Wed, Dec 21, 2016 at 05:21:05PM +0300, Alexander Kochetkov wrote:
> Hello Heiko, Daniel!
>
> Are there any reasons why the patches [1][2] are not applied yet into kernel?
> How can I help in applying patches?
Hi Alexander,
sorry for the delay. Let me review them before taking the patchset.
Heiko, can you have a look to them also ?
Thanks.
-- Daniel
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 4/5] dt: add bindings for ZTE tvenc device
From: Rob Herring @ 2017-01-23 14:46 UTC (permalink / raw)
To: Shawn Guo
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA, Daniel Vetter, Sean Paul,
David Airlie, Mark Rutland, Baoyou Xie, Jun Nie, Shawn Guo
In-Reply-To: <1484843100-16284-5-git-send-email-shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
On Fri, Jan 20, 2017 at 12:24:59AM +0800, Shawn Guo wrote:
> From: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>
> It adds bindings doc for ZTE VOU TV Encoder device.
>
> Signed-off-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> Documentation/devicetree/bindings/display/zte,vou.txt | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCHv2] Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks
From: Tero Kristo @ 2017-01-23 14:43 UTC (permalink / raw)
To: Tony Lindgren, Michael Turquette, Stephen Boyd
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-omap-u79uwXL29TY76Z2rM5mHXA, Paul Walmsley, Rob Herring
In-Reply-To: <20170117225302.10844-1-tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
On 18/01/17 00:53, Tony Lindgren wrote:
> Texas Instruments omap variant SoCs starting with omap4 have a clkctrl
> clock controller instance for each interconnect target module. The clkctrl
> controls functional and interface clocks for the module.
>
> The clkctrl clocks are currently handled by arch/arm/mach-omap2 hwmod code.
> With this binding and a related clock device driver we can start moving the
> clkctrl clock handling to live in drivers/clk/ti.
>
> Note that this binding allows keeping the clockdomain related parts out of
> drivers/clock. The CLKCTCTRL and DYNAMICDEP registers can be handled by
> a separate driver in drivers/soc/ti and genpd. If the clockdomain driver
> needs to know it's clocks, we can just set the the clkctrl device
> instances to be children of the related clockdomain device.
>
> Each clkctrl clock can have multiple optional gate clocks, and multiple
> optional mux clocks. To represent this in device tree, it seems that
> it is best done using four clock cells #clock-cells = <4> property.
>
> The reasons for using #clock-cells = <4> are:
>
> 1. We need to specify the clkctrl offset from the instance base. Otherwise
> we end up with a large number of device tree nodes that need to be
> patched when new clocks are discovered in a clkctrl clock with minor
> hardware revision changes for example
>
> 2. On omap5 CM_L3INIT_USB_HOST_HS_CLKCTRL has ten OPTFCLKEN bits. So we
> need to use a separate cell for optional gate clocks to avoid address
> space conflicts
>
> 3. Some clkctrl instances can also also optional mux clocks. To address
> them properly we need also a separate cell for the optional mux
> clock index
>
> 4. The modulemode clock needs a flag passed to it for hardware or
> software controlled mode
Hi Tony,
I think #clock-cells = <4> is too much. I believe we only need 2:
- one entry for clkctrl offset
- one entry for clock offset within the clkctrl entry (0 = module clock,
8+ = opt-clocks / mux clocks / dividers)
Fields 2 / 3 in your proposal are mutually exclusive, if either field is
non-zero, the other one must be zero. And, the opt clocks / mux / divs
always have different values for these.
Field 4 is kind of redundant also, as the module clock must be
registered at the clkctrl probe time, it is too late for the clock
consumer to provide the proper setting for the clock during its own
probe. It seems I need to add static data to driver which basically has
this information in place already.
-Tero
>
> There is probably no need to list input clocks for each clkctrl clock
> instance in the binding. If we want to add them, the standard clocks
> binding can be used for that.
>
> For hardware reference, see omap4430 TRM "Table 3-1312. L4PER_CM2 Registers
> Mapping Summary" for example. It shows one instance of a clkctrl clock
> controller with multiple clkctrl registers.
>
> Cc: Paul Walmsley <paul-DWxLp4Yu+b8AvxtiuMwx3w@public.gmane.org>
> Cc: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> ---
>
> Changes from v1:
>
> - Use #clock-cells to avoid address space conflicts
>
> - Consider also optional mux clocks as pointed out by Tero
>
> ---
> .../devicetree/bindings/clock/ti-clkctrl.txt | 57 ++++++++++++++++++++++
> 1 file changed, 57 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/ti-clkctrl.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt
> new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt
> @@ -0,0 +1,57 @@
> +Texas Instruments clkctrl clock binding
> +
> +Texas Instruments SoCs can have a clkctrl clock controller for each
> +interconnect target module. The clkctrl clock controller manages functional
> +and interface clocks for each module. Each clkctrl controller can also
> +gate one or more optional functional clocks for a module, and can have one
> +or more clock muxes. There is a clkctrl clock controller typically for each
> +interconnect target module on omap4 and later variants.
> +
> +The clock consumers can specify the index of the clkctrl clock using
> +the hardware offset from the clkctrl instance register space. The optional
> +clocks can be specified by clkctrl hardware offset and the index of the
> +optional clock.
> +
> +For more information, please see the Linux clock framework binding at
> +Documentation/devicetree/bindings/clock/clock-bindings.txt.
> +
> +Required properties :
> +- compatible : shall be "ti,clkctrl"
> +- #clock-cells : shall contain 4 with the first entry being the instance
> + offset from the clock domain base, the second being the
> + clock index, the third being the optional clock mux index,
> + and fourth being the clock flags
> +
> +Example: Clock controller node on omap 4430:
> +
> +&cm2 {
> + l4per: cm@1400 {
> + cm_l4per@0 {
> + cm_l4per_clkctrl: clk@20 {
> + compatible = "ti,clkctrl";
> + reg = <0x20 0x1b0>;
> + #clock-cells = <4>;
> + };
> + };
> + };
> +};
> +
> +Example: Preprocessor helper macros in dt-bindings/clock/ti-clkctrl.h
> +
> +#define OMAP4_CLKCTRL_OFFSET 0x20
> +#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET)
> +#define MODULEMODE_HWCTRL 1
> +#define MODULEMODE_SWCTRL 2
> +
> +#define OMAP4_GPTIMER10_CLKTRL OMAP4_CLKCTRL_INDEX(0x28)
> +#define OMAP4_GPTIMER11_CLKTRL OMAP4_CLKCTRL_INDEX(0x30)
> +#define OMAP4_GPTIMER2_CLKTRL OMAP4_CLKCTRL_INDEX(0x38)
> +...
> +#define OMAP4_GPIO2_CLKCTRL OMAP_CLKCTRL_INDEX(0x60)
> +
> +Example: Clock consumer node for GPIO2:
> +
> +&gpio2 {
> + clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0 0 MODULEMODE_HWCTRL
> + &cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 8 0 0>;
> +};
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v3 2/3] input: pwm-beeper: add documentation for volume devicetree bindings
From: Rob Herring @ 2017-01-23 14:40 UTC (permalink / raw)
To: Frieder Schrempf
Cc: dmitry.torokhov-Re5JQEeQqe8AvxtiuMwx3w, pawel.moll-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ,
luis-HiykPkW1eAzzDCI4PIEvbQC/G2K4zDHf,
linux-input-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <48a18fbdabcce57ee8efa57b9b6033d1462ab492.1484838551.git.frieder.schrempf-wPoT/lNZgHizQB+pC5nmwQ@public.gmane.org>
On Thu, Jan 19, 2017 at 04:24:09PM +0100, Frieder Schrempf wrote:
> This patch adds the documentation for the devicetree bindings to set
> the volume levels.
>
> Signed-off-by: Frieder Schrempf <frieder.schrempf-wPoT/lNZgHizQB+pC5nmwQ@public.gmane.org>
> ---
> Changes in v3:
> - change description of volume-levels to be used for linear levels
>
> .../devicetree/bindings/input/pwm-beeper.txt | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [alsa-devel] [PATCH v3 1/2] ASoC: cs35l35: Add support for Cirrus CS35L35 Amplifier
From: Charles Keepax @ 2017-01-23 14:38 UTC (permalink / raw)
To: Brian Austin
Cc: Li Xu, alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
tiwai-IBi9RG/b67k, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, broonie-DgEjT+Ai2ygdnm+yROfE0A,
Handrigan, Paul
In-Reply-To: <alpine.DEB.2.10.1701230754300.32562@heelroid>
On Mon, Jan 23, 2017 at 08:02:34AM -0600, Brian Austin wrote:
> On Wed, 21 Dec 2016, Charles Keepax wrote:
> > > + break;
> > > + case SND_SOC_DAIFMT_PDM:
> > > + cs35l35->pdm_mode = true;
> > > + cs35l35->i2s_mode = false;
> >
> > Feels a bit redundant to have both of these if they are only ever
> > a logical inversion of each other.
> Certain features are only available in these modes and once TDM is added
> will make it easier to adjust settings based on mode
<snip>
> > > + };
> > > + } else {
> > > + /* Only certain ratios supported in I2S MASTER Mode */
> > > + switch (sp_sclks) {
> > > + case CS35L35_SP_SCLKS_32FS:
> > > + case CS35L35_SP_SCLKS_64FS:
> > > + break;
> > > + default:
> > > + dev_err(codec->dev, "ratio not supported\n");
> > > + return -EINVAL;
> > > + };
> > > + }
> > > + ret = regmap_update_bits(cs35l35->regmap,
> > > + CS35L35_CLK_CTL3, CS35L35_SP_SCLKS_MASK,
> > > + sp_sclks << CS35L35_SP_SCLKS_SHIFT);
> > > + if (ret != 0) {
> > > + dev_err(codec->dev, "Failed to set fsclk %d\n", ret);
> > > + return ret;
> > > + }
> > > + }
> > > + if (cs35l35->pdm_mode) {
> > > + regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
> > > + CS35L35_PDM_MODE_MASK, 1 << CS35L35_PDM_MODE_SHIFT);
> > > + } else {
> > > + regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
> > > + CS35L35_PDM_MODE_MASK, 0 << CS35L35_PDM_MODE_SHIFT);
> > > + }
> >
> > This if could be combined with the one above since pdm_mode ==
> > !i2s_mode.
>
> Got it thanks
Probably best to ignore that comment given you mention the
addition of more flags and the potential for these to no longer
just be an inversion of each other in the future.
> > > +
> > > + if (cs35l35->pdata.bst_ipk)
> > > + regmap_update_bits(cs35l35->regmap, CS35L35_BST_PEAK_I,
> > > + CS35L35_BST_IPK_MASK,
> > > + cs35l35->pdata.bst_ipk << CS35L35_BST_IPK_SHIFT);
> >
> > I believe zero is a valid value for this field, but not the
> > default. Are we happy that the user can never set this value?
> >
> So here I can just AND in a set high bit that way the check will show true
> even if 0. Isn't that what we thought would be the easiest?
Yeah seems easiest to me.
> > > + if (classh->classh_algo_enable) {
> > > + if (classh->classh_bst_override)
> > > + regmap_update_bits(cs35l35->regmap,
> > > + CS35L35_CLASS_H_CTL, CS35L35_CH_BST_OVR_MASK,
> > > + classh->classh_bst_override << CS35L35_CH_BST_OVR_SHIFT);
> > > + if (classh->classh_bst_max_limit)
> > > + regmap_update_bits(cs35l35->regmap,
> > > + CS35L35_CLASS_H_CTL, CS35L35_CH_BST_LIM_MASK,
> > > + classh->classh_bst_max_limit << CS35L35_CH_BST_LIM_SHIFT);
> >
> > This is a single bit, but the default bit is 1, so this code can
> > never change the value of the field.
> This one and the rest apply to previous statement correct?
>
Yeah would cover this one too.
Thanks,
Charles
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v2] of/platform: Ignore disabled devices in of_platform_populate()
From: Alexander Sverdlin @ 2017-01-23 14:33 UTC (permalink / raw)
Cc: Rob Herring, Frank Rowand, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170123125204.22233-1-alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
Hello all,
On 23/01/17 13:52, Alexander Sverdlin wrote:
> Check the status property and give up early enough. Otherwise
> OF_POPULATED_BUS might be set for disabled bus which will prevent
> it from being populated later (if enabled).
>
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Frank Rowand <frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
> drivers/of/platform.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/of/platform.c b/drivers/of/platform.c
> index 35de1fc59fa6..060621d94f1a 100644
> --- a/drivers/of/platform.c
> +++ b/drivers/of/platform.c
> @@ -476,6 +476,10 @@ int of_platform_populate(struct device_node *root,
> root = root ? of_node_get(root) : of_find_node_by_path("/");
> if (!root)
> return -EINVAL;
> + if (!of_device_is_available(root)) {
> + of_node_put(root);
> + return 0;
> + }
>
> pr_debug("%s()\n", __func__);
> pr_debug(" starting at: %s\n", root->full_name);
no, this one also doesn't allow to switch to of_platform_default_populate(),
please ignore the patch.
--
Best regards,
Alexander Sverdlin.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH] net: ethernet: mvneta: add support for 2.5G DRSGMII mode
From: Jan Luebbe @ 2017-01-23 14:22 UTC (permalink / raw)
To: netdev, devicetree, davem
Cc: Rob Herring, Mark Rutland, Thomas Petazzoni, Florian Fainelli,
Jan Luebbe
The Marvell MVNETA Ethernet controller supports a 2.5 Gbps SGMII mode
called DRSGMII.
This patch adds a corresponding phy-mode string 'drsgmii' and parses it
from DT. The MVNETA then configures the SERDES protocol value
accordingly.
It was successfully tested on a MV78460 connected to a FPGA.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
---
Documentation/devicetree/bindings/net/ethernet.txt | 1 +
drivers/net/ethernet/marvell/mvneta.c | 5 +++++
include/linux/phy.h | 3 +++
3 files changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/ethernet.txt b/Documentation/devicetree/bindings/net/ethernet.txt
index 05150957ecfd..de40c5977d8f 100644
--- a/Documentation/devicetree/bindings/net/ethernet.txt
+++ b/Documentation/devicetree/bindings/net/ethernet.txt
@@ -29,6 +29,7 @@ The following properties are common to the Ethernet controllers:
* "smii"
* "xgmii"
* "trgmii"
+ * "drsgmii"
- phy-connection-type: the same as "phy-mode" property but described in ePAPR;
- phy-handle: phandle, specifies a reference to a node representing a PHY
device; this property is described in ePAPR and so preferred;
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index e05e22705cf7..8cb43e0d9d0e 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -105,6 +105,7 @@
#define MVNETA_SERDES_CFG 0x24A0
#define MVNETA_SGMII_SERDES_PROTO 0x0cc7
#define MVNETA_QSGMII_SERDES_PROTO 0x0667
+#define MVNETA_DRSGMII_SERDES_PROTO 0x1107
#define MVNETA_TYPE_PRIO 0x24bc
#define MVNETA_FORCE_UNI BIT(21)
#define MVNETA_TXQ_CMD_1 0x24e4
@@ -4047,6 +4048,10 @@ static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
* SGMII or QSGMII mode, the RGMII bit needs to be set.
*/
switch(phy_mode) {
+ case PHY_INTERFACE_MODE_DRSGMII:
+ mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_DRSGMII_SERDES_PROTO);
+ ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
+ break;
case PHY_INTERFACE_MODE_QSGMII:
mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
diff --git a/include/linux/phy.h b/include/linux/phy.h
index f7d95f644eed..a3d83bc96035 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -82,6 +82,7 @@ typedef enum {
PHY_INTERFACE_MODE_MOCA,
PHY_INTERFACE_MODE_QSGMII,
PHY_INTERFACE_MODE_TRGMII,
+ PHY_INTERFACE_MODE_DRSGMII,
PHY_INTERFACE_MODE_MAX,
} phy_interface_t;
@@ -142,6 +143,8 @@ static inline const char *phy_modes(phy_interface_t interface)
return "qsgmii";
case PHY_INTERFACE_MODE_TRGMII:
return "trgmii";
+ case PHY_INTERFACE_MODE_DRSGMII:
+ return "drsgmii";
default:
return "unknown";
}
--
2.11.0
^ permalink raw reply related
* [PATCH] ARM: dts: r7s72100: add power-domains to mmcif
From: Chris Brandt @ 2017-01-23 14:13 UTC (permalink / raw)
To: Geert Uytterhoeven, Simon Horman, Magnus Damm, Rob Herring,
Mark Rutland
Cc: devicetree, linux-renesas-soc, Chris Brandt
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
arch/arm/boot/dts/r7s72100.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 3dd427d..354f4b6 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -466,6 +466,7 @@
GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
+ power-domains = <&cpg_clocks>;
reg-io-width = <4>;
bus-width = <8>;
status = "disabled";
--
2.10.1
^ permalink raw reply related
* Re: [V2 2/2] arm64: dts: Add dts files for Hisilicon Hi3660 SoC
From: Sudeep Holla @ 2017-01-23 14:13 UTC (permalink / raw)
To: Chen Feng, xuwei5-C8/M+/jPZTeaMJb+Lgu22Q,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: Sudeep Holla, puck.chen-H32Fclmsjq1BDgjK7y7TUQ,
dan.zhao-C8/M+/jPZTeaMJb+Lgu22Q,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q,
saberlily.xia-C8/M+/jPZTeaMJb+Lgu22Q,
xuyiping-C8/M+/jPZTeaMJb+Lgu22Q, qijiwen-C8/M+/jPZTeaMJb+Lgu22Q
In-Reply-To: <1484034915-48879-2-git-send-email-puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
On 10/01/17 07:55, Chen Feng wrote:
> Add initial dtsi file to support Hisilicon Hi3660 SoC with
> support of Octal core CPUs in two clusters(4 * A53 & 4 * A73).
>
> Also add dts file to support HiKey960 development board which
> based on Hi3660 SoC.
> The output console is earlycon "earlycon=pl011,0xfdf05000".
> And the con_init uart5 with a fixed clock, which already
> configured at bootloader.
>
> When clock is available, the uart5 will be modified.
>
> Tested on HiKey960 Board.
>
> Signed-off-by: Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
> ---
> arch/arm64/boot/dts/hisilicon/Makefile | 1 +
> arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 34 +++++
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 156 ++++++++++++++++++++++
> 3 files changed, 191 insertions(+)
> create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> new file mode 100644
> index 0000000..7f9805c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -0,0 +1,156 @@
> +/*
> + * dts file for Hisilicon Hi3660 SoC
> + *
> + * Copyright (C) 2016, Hisilicon Ltd.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + compatible = "hisilicon,hi3660";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
[...]
> +
> + cpu0: cpu@0 {
> + compatible = "arm,armv8";
You can add more specific compatibles as you mentioned this SoC contains
Cortex A53 & A73.
--
Regards,
Sudeep
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [RESEND PATCH 6/6] dt-bindings: phy-mt65xx-usb: add support for mt2712 platform
From: Rob Herring @ 2017-01-23 14:04 UTC (permalink / raw)
To: Chunfeng Yun
Cc: Kishon Vijay Abraham I, Matthias Brugger, Felipe Balbi,
Mark Rutland, Ian Campbell,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Linux USB List, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1485053419.10292.88.camel@mhfsdcap03>
On Sat, Jan 21, 2017 at 8:50 PM, Chunfeng Yun <chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> On Sat, 2017-01-21 at 14:08 -0600, Rob Herring wrote:
>> On Wed, Jan 18, 2017 at 02:00:14PM +0800, Chunfeng Yun wrote:
>> > add a new compatible string for "mt2712", and a new reference clock
>> > for SuperSpeed analog phy;
>> >
>> > Signed-off-by: Chunfeng Yun <chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>> > ---
>> > .../devicetree/bindings/phy/phy-mt65xx-usb.txt | 81 +++++++++++++++++---
>> > 1 file changed, 70 insertions(+), 11 deletions(-)
[...]
>> > @@ -31,21 +37,27 @@ Example:
>> > u3phy: usb-phy@11290000 {
>> > compatible = "mediatek,mt8173-u3phy";
>> > reg = <0 0x11290000 0 0x800>;
>> > - clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
>> > - clock-names = "u3phya_ref";
>> > + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk26m>;
>> > + clock-names = "u2ref_clk", "u3ref_clk";
>> > #address-cells = <2>;
>> > #size-cells = <2>;
>> > ranges;
>> > status = "okay";
>> >
>> > - phy_port0: port@11290800 {
>> > - reg = <0 0x11290800 0 0x800>;
>> > + u2port0: port@11290800 {
>>
>> port is for OF graph. This should be usb-phy@... instead.
> Is there any problems if u2port0's name@addr is the same as its parent's
> (u3phy)? as following:
> u3phy: usb-phy@11290000 {
> compatible = ...;
> // no reg property
> clocks = ...;
> u2port0: usb-phy@11290000 {
> reg = ...;
> }
No problem, that is fine.
Rob
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [V2 2/2] arm64: dts: Add dts files for Hisilicon Hi3660 SoC
From: Wei Xu @ 2017-01-23 14:03 UTC (permalink / raw)
To: Mark Rutland, Chen Feng
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
puck.chen-H32Fclmsjq1BDgjK7y7TUQ, dan.zhao-C8/M+/jPZTeaMJb+Lgu22Q,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q,
saberlily.xia-C8/M+/jPZTeaMJb+Lgu22Q,
xuyiping-C8/M+/jPZTeaMJb+Lgu22Q, qijiwen-C8/M+/jPZTeaMJb+Lgu22Q,
Linuxarm
In-Reply-To: <20170123134656.GC16286@leverpostej>
Hi Mark,
On 2017/1/23 13:46, Mark Rutland wrote:
> On Tue, Jan 10, 2017 at 03:55:15PM +0800, Chen Feng wrote:
>> + memory@0 {
>> + device_type = "memory";
>> + reg = <0x0 0x00400000 0x0 0xbfe00000>;
>> + };
>
> The unit-address here is incorrect. The base address of this memory is
> not zero.
>
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupt-parent = <&gic>;
>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>> + clock-frequency = <1920000>;
>> + };
>
> This clock-frequency property should not be required; please remove it.
>
> Your FW should program CNTFRQ_EL0 with the timer frequency.
Thanks!
Hi Chen Feng,
Can you send out the v3 to address above comments?
And I will pick up it soon.
Best Regards,
Wei
>
> Thanks,
> Mark.
>
> .
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 6/6] dt-bindings: mt8173-mtu3: add reference clock
From: Rob Herring @ 2017-01-23 14:02 UTC (permalink / raw)
To: Chunfeng Yun
Cc: Mathias Nyman, Felipe Balbi, Greg Kroah-Hartman, Matthias Brugger,
Mark Rutland, Ian Campbell,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Linux USB List, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1485049780.10292.78.camel@mhfsdcap03>
On Sat, Jan 21, 2017 at 7:49 PM, Chunfeng Yun <chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> Hi,
>
> On Sat, 2017-01-21 at 14:11 -0600, Rob Herring wrote:
>> On Wed, Jan 18, 2017 at 02:08:27PM +0800, Chunfeng Yun wrote:
>> > add a reference clock for compatibility
>>
>> Why? This block suddenly has 2 clocks instead of 1?
> In fact, there is a reference clock which comes from 26M oscillator
> directly. I ignore it because it is a fixed-clock in DTS, and always
> turned on for mt8173. But later, I find that I made a mistake before
> when I bring up it on a new platform whose reference clock comes from
> PLL, and need control it. So here add it, no matter it is a fixed-clock
> or not.
Add this explanation to the changelog.
Rob
--
To unsubscribe from this list: send the line "unsubscribe linux-usb" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [alsa-devel] [PATCH v3 1/2] ASoC: cs35l35: Add support for Cirrus CS35L35 Amplifier
From: Brian Austin @ 2017-01-23 14:02 UTC (permalink / raw)
To: Charles Keepax
Cc: Li Xu, alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
brian.austin-jGc1dHjMKG3QT0dZR+AlfA, tiwai-IBi9RG/b67k,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, lgirdwood-Re5JQEeQqe8AvxtiuMwx3w,
broonie-DgEjT+Ai2ygdnm+yROfE0A, Handrigan, Paul
In-Reply-To: <20161221105350.GR1867-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
On Wed, 21 Dec 2016, Charles Keepax wrote:
>
> Feels redundant to have this extra comment after the large comment
> before it.
I'll remove it
>
> > +
> > +#include <linux/module.h>
> > +#include <linux/moduleparam.h>
> > +#include <linux/version.h>
> > +#include <linux/kernel.h>
> > +#include <linux/init.h>
> > +#include <linux/delay.h>
> > +#include <linux/i2c.h>
> > +#include <linux/slab.h>
> > +#include <linux/workqueue.h>
>
> Do we need the workqueue header we don't seem to use any
> workqueues?
Nope
>
> > +static int cs35l35_sdin_event(struct snd_soc_dapm_widget *w,
> > + struct snd_kcontrol *kcontrol, int event)
> > +{
> > + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
> > + struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
> > + int ret = 0;
> > +
> > + switch (event) {
> > + case SND_SOC_DAPM_PRE_PMU:
> > + regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
> > + CS35L35_MCLK_DIS_MASK, 0 << CS35L35_MCLK_DIS_SHIFT);
> > + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
> > + CS35L35_DISCHG_FILT_MASK, 0 << CS35L35_DISCHG_FILT_SHIFT);
> > + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
> > + CS35L35_PDN_ALL_MASK, 0);
> > + break;
>
> Break should be indented for kernel coding style.
>
> > + case SND_SOC_DAPM_POST_PMD: + regmap_update_bits(cs35l35->regmap,
> > CS35L35_PWRCTL1, + CS35L35_PDN_ALL_MASK, 1); +
> > regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1, +
> > CS35L35_DISCHG_FILT_MASK, 1 << CS35L35_DISCHG_FILT_SHIFT); + + ret =
> > wait_for_completion_timeout(&cs35l35->pdn_done, +
> > msecs_to_jiffies(100)); + if (ret == 0) { + dev_err(codec->dev,
> > "TIMEOUT PDN_DONE did not complete in 100ms\n"); + ret = -ETIMEDOUT; +
> > } + + regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1, +
> > CS35L35_MCLK_DIS_MASK, 1 << CS35L35_MCLK_DIS_SHIFT); + break;
>
> Ditto.
Thanks
> > + usleep_range(5000, 5100);
> > + /* If PDM mode we must use VP
> > + * for Voltage control
> > + */
>
> Does this comment need to split across multiple lines?
Nope
> > + break;
> > + case SND_SOC_DAIFMT_PDM:
> > + cs35l35->pdm_mode = true;
> > + cs35l35->i2s_mode = false;
>
> Feels a bit redundant to have both of these if they are only ever
> a logical inversion of each other.
Certain features are only available in these modes and once TDM is added
will make it easier to adjust settings based on mode
>
> > +static int cs35l35_get_clk_config(int sysclk, int srate)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(cs35l35_clk_ctl); i++) {
> > + if (cs35l35_clk_ctl[i].sysclk == sysclk &&
> > + cs35l35_clk_ctl[i].srate == srate)
> > + return cs35l35_clk_ctl[i].clk_cfg;
> > + }
> > + return -EINVAL;
> > +}
> > +
> > +static int cs35l35_pcm_hw_params(struct snd_pcm_substream *substream,
> > + struct snd_pcm_hw_params *params,
> > + struct snd_soc_dai *dai)
> > +{
> > + struct snd_soc_codec *codec = dai->codec;
> > + struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
> > + struct classh_cfg *classh = &cs35l35->pdata.classh_algo;
> > + int srate = params_rate(params);
> > + int ret = 0;
> > + u8 sp_sclks;
> > + int audin_format;
> > + int errata_chk;
> > +
> > + int clk_ctl = cs35l35_get_clk_config(cs35l35->sysclk, srate);
> > +
> > + if (clk_ctl < 0) {
> > + dev_err(codec->dev, "Invalid CLK:Rate %d:%d\n",
> > + cs35l35->sysclk, srate);
> > + return -EINVAL;
> > + }
>
> It would normally be slightly better to set constraints in
> startup based on the SYSCLK rather than returning an error in
> hw_params. This allows user-space to negotiate a rate that is
> actually supported and do any sample rate conversion required.
>
We talked about this and it made sense up to the point where I have to
know the actual sample rate in order to determine if the sysclk is valid.
Also there are several clocks that are common to several sample rates so
I'm not sure if I will be able to take advantage of this idea to the
extent I/we would like.
> > + };
> > + } else {
> > + /* Only certain ratios supported in I2S MASTER Mode */
> > + switch (sp_sclks) {
> > + case CS35L35_SP_SCLKS_32FS:
> > + case CS35L35_SP_SCLKS_64FS:
> > + break;
> > + default:
> > + dev_err(codec->dev, "ratio not supported\n");
> > + return -EINVAL;
> > + };
> > + }
> > + ret = regmap_update_bits(cs35l35->regmap,
> > + CS35L35_CLK_CTL3, CS35L35_SP_SCLKS_MASK,
> > + sp_sclks << CS35L35_SP_SCLKS_SHIFT);
> > + if (ret != 0) {
> > + dev_err(codec->dev, "Failed to set fsclk %d\n", ret);
> > + return ret;
> > + }
> > + }
> > + if (cs35l35->pdm_mode) {
> > + regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
> > + CS35L35_PDM_MODE_MASK, 1 << CS35L35_PDM_MODE_SHIFT);
> > + } else {
> > + regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
> > + CS35L35_PDM_MODE_MASK, 0 << CS35L35_PDM_MODE_SHIFT);
> > + }
>
> This if could be combined with the one above since pdm_mode ==
> !i2s_mode.
Got it thanks
>
> > + return ret;
> > +}
> > +
> > +
> > +static const struct snd_soc_dai_ops cs35l35_ops = {
> > + .startup = cs35l35_pcm_startup,
> > + .set_fmt = cs35l35_set_dai_fmt,
> > + .hw_params = cs35l35_pcm_hw_params,
> > + .set_sysclk = cs35l35_dai_set_sysclk,
> > +};
> > +
> > +static const struct snd_soc_dai_ops cs35l35_pdm_ops = {
> > + .startup = cs35l35_pdm_startup,
> > + .set_fmt = cs35l35_set_dai_fmt,
> > + .hw_params = cs35l35_pcm_hw_params,
>
> I would be tempted to rename the function to just
> cs35l35_hw_params if it is shared between both PCM and PDM.
>
Done. Thanks
> > + .set_sysclk = cs35l35_dai_set_sysclk,
Since it's only 1 stream at a time I am removing the dia_set_sysclk
> > +
> > + if (cs35l35->pdata.bst_ipk)
> > + regmap_update_bits(cs35l35->regmap, CS35L35_BST_PEAK_I,
> > + CS35L35_BST_IPK_MASK,
> > + cs35l35->pdata.bst_ipk << CS35L35_BST_IPK_SHIFT);
>
> I believe zero is a valid value for this field, but not the
> default. Are we happy that the user can never set this value?
>
So here I can just AND in a set high bit that way the check will show true
even if 0. Isn't that what we thought would be the easiest?
> > +
> > + if (cs35l35->pdata.gain_zc)
> > + regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
> > + CS35L35_AMP_GAIN_ZC_MASK,
> > + cs35l35->pdata.gain_zc << CS35L35_AMP_GAIN_ZC_SHIFT);
> > +
> > + if (cs35l35->pdata.aud_channel)
> > + regmap_update_bits(cs35l35->regmap,
> > + CS35L35_AUDIN_RXLOC_CTL,
> > + CS35L35_AUD_IN_LR_MASK,
> > + cs35l35->pdata.aud_channel << CS35L35_AUD_IN_LR_SHIFT);
> > +
> > + if (cs35l35->pdata.stereo) {
> > + regmap_update_bits(cs35l35->regmap,
> > + CS35L35_ADVIN_RXLOC_CTL, CS35L35_ADV_IN_LR_MASK,
> > + cs35l35->pdata.adv_channel << CS35L35_ADV_IN_LR_SHIFT);
> > + if (cs35l35->pdata.shared_bst)
> > + regmap_update_bits(cs35l35->regmap, CS35L35_CLASS_H_CTL,
> > + CS35L35_CH_STEREO_MASK, 1 << CS35L35_CH_STEREO_SHIFT);
> > + ret = snd_soc_add_codec_controls(codec, cs35l35_adv_controls,
> > + ARRAY_SIZE(cs35l35_adv_controls));
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + if (cs35l35->pdata.sp_drv_str)
> > + regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
> > + CS35L35_SP_DRV_MASK,
> > + cs35l35->pdata.sp_drv_str << CS35L35_SP_DRV_SHIFT);
> > +
> > + if (classh->classh_algo_enable) {
> > + if (classh->classh_bst_override)
> > + regmap_update_bits(cs35l35->regmap,
> > + CS35L35_CLASS_H_CTL, CS35L35_CH_BST_OVR_MASK,
> > + classh->classh_bst_override << CS35L35_CH_BST_OVR_SHIFT);
> > + if (classh->classh_bst_max_limit)
> > + regmap_update_bits(cs35l35->regmap,
> > + CS35L35_CLASS_H_CTL, CS35L35_CH_BST_LIM_MASK,
> > + classh->classh_bst_max_limit << CS35L35_CH_BST_LIM_SHIFT);
>
> This is a single bit, but the default bit is 1, so this code can
> never change the value of the field.
This one and the rest apply to previous statement correct?
> > +
> > + /* returning NULL can be an option if in stereo mode */
> > + cs35l35->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
> > + "reset", GPIOD_OUT_LOW);
> > + if (IS_ERR(cs35l35->reset_gpio))
> > + return PTR_ERR(cs35l35->reset_gpio);
>
> This should be a goto err;
>
OK
> > +
> > + if (cs35l35->reset_gpio)
> > + gpiod_set_value_cansleep(cs35l35->reset_gpio, 1);
>
> gpiod_set_value_can_sleep does an internal NULL check on the GPIO
> desc I would be tempted to just rely on that one.
>
That works for me
> > +
> > + init_completion(&cs35l35->pdn_done);
> > +
> > + ret = regmap_register_patch(cs35l35->regmap, cs35l35_errata_patch,
> > + ARRAY_SIZE(cs35l35_errata_patch));
> > + if (ret < 0) {
> > + dev_err(&i2c_client->dev, "Failed to apply errata patch\n");
> > + return ret;
>
> This should be a goto err;
>
OK
> clientdata was allocated with devm this kfree will cause a double
> free.
got it thanks
>
> > + return 0;
> > +}
>
> Thanks,
> Charles
>
Thanks,
Brian
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 1/3] ARM: dts: Add support for phyCORE-AM335x PCM-953 carrier board
From: Rob Herring @ 2017-01-23 14:01 UTC (permalink / raw)
To: Teresa Remmet
Cc: linux-omap, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Benoît Cousson, Tony Lindgren, Mark Rutland, Wadim Egorov
In-Reply-To: <1485167232.3082.9.camel-guT5V/WYfQezQB+pC5nmwQ@public.gmane.org>
On Mon, Jan 23, 2017 at 4:27 AM, Teresa Remmet <t.remmet-guT5V/WYfQezQB+pC5nmwQ@public.gmane.org> wrote:
> Hello Rob,
>
> Am Samstag, den 21.01.2017, 14:53 -0600 schrieb Rob Herring:
>> On Thu, Jan 19, 2017 at 02:07:48PM +0100, Teresa Remmet wrote:
>> >
>> > The phyCORE-AM335x development kit is a combination of the
>> > phyCORE-AM335x SoM and a PCM-953 carrier board. The features
>> > of the PCM-953 are:
>> > * ETH phy on carrier board: 1x RGMII
>> > * 1x CAN
>> > * Up to 4x UART
>> > * USB0 (otg)
>> > * USB1 (host)
>> > * SD slot
>> > * User gpio-keys
>> > * User LEDs
>> >
>> > Signed-off-by: Teresa Remmet <t.remmet-guT5V/WYfQezQB+pC5nmwQ@public.gmane.org>
>> > Reviewed-by: Wadim Egorov <w.egorov-guT5V/WYfQezQB+pC5nmwQ@public.gmane.org>
>> > ---
>> > .../devicetree/bindings/arm/omap/omap.txt | 3 +
>> > arch/arm/boot/dts/Makefile | 1 +
>> > arch/arm/boot/dts/am335x-pcm-953.dtsi | 303
>> > +++++++++++++++++++++
>> > arch/arm/boot/dts/am335x-phycore-rdk.dts | 27 ++
>> > 4 files changed, 334 insertions(+)
>> > create mode 100644 arch/arm/boot/dts/am335x-pcm-953.dtsi
>> > create mode 100644 arch/arm/boot/dts/am335x-phycore-rdk.dts
>> [...]
>>
>> >
>> > + user_leds: user_leds {
>> > + compatible = "gpio-leds";
>> > + };
>> > +
>> > + user_buttons: user_buttons {
>> > + compatible = "gpio-keys";
>> > + };
>> With only a compatible, I don't think there's much gain to split
>> these 2
>> nodes. Otherwse,
>
> whould it be ok to open up the root node again below? Or should I
> better move the nodes up? Which does mess up the order then. We
> orinented here on the am335x-pepper.dts. They also only keep the
> compatibles in the root node.
The order is not important. It is silly to have the same node twice in
the same file. Someone should fix am335x-pepper.dts, too.
The split is generally what is chip specific and board specific, but
this is all board specific.
Rob
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH v2 2/2] ARM: sun8i: dt: Add mali node
From: Maxime Ripard @ 2017-01-23 14:00 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Chen-Yu Tsai, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Carlo Caione, Kevin Hilman,
Heiko Stuebner, Matthias Brugger, Kukjin Kim, Krzysztof Kozlowski,
Javier Martinez Canillas, Linus Walleij, Alexandre Belloni,
Thomas Petazzoni, Boris Brezillon, Maxime Ripard
In-Reply-To: <a4d90de597cfcfab5fddeeb538505774a980818b.1485180017.git-series.maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
The A23 and A33 have an ARM Mali 400 GPU. Now that we have a binding, add
it to our DT.
Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index e4991a78ad73..982705719ef2 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -486,6 +486,32 @@
#size-cells = <0>;
};
+ mali: gpu@01c40000 {
+ compatible = "allwinner,sun8i-a23-mali",
+ "allwinner,sun7i-a20-mali", "arm,mali-400";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pmu";
+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_BUS_GPU>;
+
+ assigned-clocks = <&ccu CLK_GPU>;
+ assigned-clock-rates = <408000000>;
+ };
+
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
--
git-series 0.8.11
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v2 1/2] dt-bindings: gpu: Add Mali Utgard bindings
From: Maxime Ripard @ 2017-01-23 14:00 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Chen-Yu Tsai, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Carlo Caione, Kevin Hilman,
Heiko Stuebner, Matthias Brugger, Kukjin Kim, Krzysztof Kozlowski,
Javier Martinez Canillas, Linus Walleij, Alexandre Belloni,
Thomas Petazzoni, Boris Brezillon, Maxime Ripard
The ARM Mali Utgard GPU family is embedded into a number of SoCs from
Allwinner, Amlogic, Mediatek or Rockchip.
Add a binding for the GPU of that family.
Reviewed-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
Changes from v1:
- Dropped the arm,mali-utgard compatible
- Made the clocks mandatory
- Added Linus Walleij Reviewed-by, and the ST compatible for the Mali
---
Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 79 ++++++++-
1 file changed, 79 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
new file mode 100644
index 000000000000..ba0edcdd1b00
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
@@ -0,0 +1,79 @@
+ARM Mali Utgard GPU
+===================
+
+Required properties:
+ - compatible
+ * Must be one of the following:
+ + "arm,mali-300"
+ + "arm,mali-400"
+ + "arm,mali-450"
+ * And, optionally, one of the vendor specific compatible:
+ + allwinner,sun4i-a10-mali
+ + allwinner,sun7i-a20-mali
+
+ - reg: Physical base address and length of the GPU registers
+
+ - interrupts: an entry for each entry in interrupt-names.
+ See ../interrupt-controller/interrupts.txt for details.
+
+ - interrupt-names:
+ * ppX: Pixel Processor X interrupt (X from 0 to 7)
+ * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7)
+ * pp: Pixel Processor broadcast interrupt (mali-450 only)
+ * gp: Geometry Processor interrupt
+ * gpmmu: Geometry Processor MMU interrupt
+
+ - clocks: an entry for each entry in clock-names
+ - clock-names:
+ * bus: bus clock for the GPU
+ * core: clock driving the GPU itself
+
+Optional properties:
+ - interrupt-names and interrupts:
+ * pmu: Power Management Unit interrupt, if implemented in hardware
+
+Vendor-specific bindings
+------------------------
+
+The Mali GPU is integrated very differently from one SoC to
+another. In order to accomodate those differences, you have the option
+to specify one more vendor-specific compatible, among:
+
+ - allwinner,sun4i-a10-mali
+ Required properties:
+ * resets: phandle to the reset line for the GPU
+
+ - allwinner,sun7i-a20-mali
+ Required properties:
+ * resets: phandle to the reset line for the GPU
+
+ - stericsson,db8500-mali
+ Required properties:
+ * interrupt-names and interrupts:
+ + combined: combined interrupt of all of the above lines
+
+Example:
+
+mali: gpu@01c40000 {
+ compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pmu";
+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_BUS_GPU>;
+};
+
+
base-commit: 49def1853334396f948dcb4cedb9347abb318df5
--
git-series 0.8.11
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v3 3/3] ARM: dts: rskrza1: add ostm DT support
From: Chris Brandt @ 2017-01-23 13:55 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland,
Russell King, Thomas Gleixner, Geert Uytterhoeven
Cc: devicetree, linux-renesas-soc, Chris Brandt
In-Reply-To: <20170123135520.28834-1-chris.brandt@renesas.com>
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
v2:
* remove part that was supposed to go in dsti
* now there is a node for each channel
---
arch/arm/boot/dts/r7s72100-rskrza1.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts
index dd44181..02b59c5 100644
--- a/arch/arm/boot/dts/r7s72100-rskrza1.dts
+++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts
@@ -61,6 +61,14 @@
status = "okay";
};
+&ostm0 {
+ status = "okay";
+};
+
+&ostm1 {
+ status = "okay";
+};
+
&scif2 {
status = "okay";
};
--
2.10.1
^ permalink raw reply related
* [PATCH v3 2/3] ARM: dts: r7s72100: add ostm to device tree
From: Chris Brandt @ 2017-01-23 13:55 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland,
Russell King, Thomas Gleixner, Geert Uytterhoeven
Cc: devicetree, linux-renesas-soc, Chris Brandt
In-Reply-To: <20170123135520.28834-1-chris.brandt@renesas.com>
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
v3:
* changed ostm@xxx to timer@xxx
* added power-domains to nodes
v2:
* wrap clock lines to avoid 80 char max
* split into 2 separate channel nodes
---
arch/arm/boot/dts/r7s72100.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index d5946df..74e684f 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -505,4 +505,22 @@
cap-sdio-irq;
status = "disabled";
};
+
+ ostm0: timer@fcfec000 {
+ compatible = "renesas,r7s72100-ostm", "renesas,ostm";
+ reg = <0xfcfec000 0x30>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ ostm1: timer@fcfec400 {
+ compatible = "renesas,r7s72100-ostm", "renesas,ostm";
+ reg = <0xfcfec400 0x30>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
};
--
2.10.1
^ permalink raw reply related
* [PATCH v3 1/3] ARM: dts: r7s72100: add ostm clock to device tree
From: Chris Brandt @ 2017-01-23 13:55 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland,
Russell King, Thomas Gleixner, Geert Uytterhoeven
Cc: devicetree, linux-renesas-soc, Chris Brandt
In-Reply-To: <20170123135520.28834-1-chris.brandt@renesas.com>
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r7s72100.dtsi | 9 +++++++++
include/dt-bindings/clock/r7s72100-clock.h | 4 ++++
2 files changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 3dd427d..d5946df 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -108,6 +108,15 @@
clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
};
+ mstp5_clks: mstp5_clks@fcfe0428 {
+ #clock-cells = <1>;
+ compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xfcfe0428 4>;
+ clocks = <&p0_clk>, <&p0_clk>;
+ clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
+ clock-output-names = "ostm0", "ostm1";
+ };
+
mstp7_clks: mstp7_clks@fcfe0430 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h
index 29e01ed..ce09915 100644
--- a/include/dt-bindings/clock/r7s72100-clock.h
+++ b/include/dt-bindings/clock/r7s72100-clock.h
@@ -25,6 +25,10 @@
#define R7S72100_CLK_SCIF6 1
#define R7S72100_CLK_SCIF7 0
+/* MSTP5 */
+#define R7S72100_CLK_OSTM0 1
+#define R7S72100_CLK_OSTM1 0
+
/* MSTP7 */
#define R7S72100_CLK_ETHER 4
--
2.10.1
^ permalink raw reply related
* [PATCH v3 0/3] ARM: dts: add ostm support for r7s72100
From: Chris Brandt @ 2017-01-23 13:55 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland,
Russell King, Thomas Gleixner, Geert Uytterhoeven
Cc: devicetree, linux-renesas-soc, Chris Brandt
This patch set enables the use of the newly created driver
renesas-ostm.c for the r7s72100 SoC.
v3:
* Changed ostm@fcfec000 to timer@fcfec000
* Added power-domains to nodes
v2:
* The biggest change was now the channels are independent of each
other and have separate nodes in the DT. The first probed will
be set up as a clock source, and any additional channels probed
will become a clock event.
Chris Brandt (3):
ARM: dts: r7s72100: add ostm clock to device tree
ARM: dts: r7s72100: add ostm to device tree
ARM: dts: rskrza1: add ostm DT support
arch/arm/boot/dts/r7s72100-rskrza1.dts | 8 ++++++++
arch/arm/boot/dts/r7s72100.dtsi | 27 +++++++++++++++++++++++++++
include/dt-bindings/clock/r7s72100-clock.h | 4 ++++
3 files changed, 39 insertions(+)
--
2.10.1
^ permalink raw reply
* [PATCH v3 2/2] clocksource: Add renesas-ostm timer driver
From: Chris Brandt @ 2017-01-23 13:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Russell King, Daniel Lezcano, Thomas Gleixner, Geert Uytterhoeven
Cc: devicetree, linux-renesas-soc, Chris Brandt
In-Reply-To: <20170123135423.28780-1-chris.brandt@renesas.com>
This patch adds a OSTM driver for the Renesas architecture.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
v2:
* changed implementation to be independent channel nodes
---
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/clocksource/Kconfig | 12 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/renesas-ostm.c | 349 +++++++++++++++++++++++++++++++++++++
4 files changed, 363 insertions(+)
create mode 100644 drivers/clocksource/renesas-ostm.c
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 2bb4b09..b928634 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -57,6 +57,7 @@ config ARCH_R7S72100
select PM
select PM_GENERIC_DOMAINS
select SYS_SUPPORTS_SH_MTU2
+ select SYS_SUPPORTS_RENESAS_OSTM
config ARCH_R8A73A4
bool "R-Mobile APE6 (R8A73A40)"
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 4866f7a..95c8d56 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -431,6 +431,9 @@ config MTK_TIMER
config SYS_SUPPORTS_SH_MTU2
bool
+config SYS_SUPPORTS_RENESAS_OSTM
+ bool
+
config SYS_SUPPORTS_SH_TMU
bool
@@ -467,6 +470,15 @@ config SH_TIMER_MTU2
Timer Pulse Unit 2 (MTU2) hardware available on SoCs from Renesas.
This hardware comes with 16 bit-timer registers.
+config RENESAS_OSTM
+ bool "Renesas OSTM timer driver" if COMPILE_TEST
+ depends on GENERIC_CLOCKEVENTS
+ select CLKSRC_MMIO
+ default SYS_SUPPORTS_RENESAS_OSTM
+ help
+ This enables the build of the OSTM timer driver.
+ It creates a clock source and clock event device.
+
config SH_TIMER_TMU
bool "Renesas TMU timer driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index a14111e..bbd163b 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += cs5535-clockevt.o
obj-$(CONFIG_CLKSRC_JCORE_PIT) += jcore-pit.o
obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o
obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o
+obj-$(CONFIG_RENESAS_OSTM) += renesas-ostm.o
obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
obj-$(CONFIG_EM_TIMER_STI) += em_sti.o
obj-$(CONFIG_CLKBLD_I8253) += i8253.o
diff --git a/drivers/clocksource/renesas-ostm.c b/drivers/clocksource/renesas-ostm.c
new file mode 100644
index 0000000..37f2461
--- /dev/null
+++ b/drivers/clocksource/renesas-ostm.c
@@ -0,0 +1,349 @@
+/*
+ * Renesas Timer Support - OSTM
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/sched_clock.h>
+
+/*
+ * The OSTM contains independent channels.
+ * The first OSTM channel probed will be set up as a free running
+ * clocksource. Additionally we will use this clocksource for the system
+ * schedule timer sched_clock().
+ *
+ * The second (or more) channel probed will be set up as an interrupt
+ * driven clock event.
+ */
+
+struct ostm_device {
+ struct platform_device *pdev;
+
+ int irq;
+ struct clk *clk;
+ unsigned long rate;
+ void __iomem *base;
+ unsigned long ticks_per_jiffy;
+ struct clock_event_device ced;
+};
+
+static void __iomem *system_clock; /* For sched_clock() */
+
+/* OSTM REGISTERS */
+#define OSTM_CMP 0x000 /* RW,32 */
+#define OSTM_CNT 0x004 /* R,32 */
+#define OSTM_TE 0x010 /* R,8 */
+#define OSTM_TS 0x014 /* W,8 */
+#define OSTM_TT 0x018 /* W,8 */
+#define OSTM_CTL 0x020 /* RW,8 */
+
+#define TE 0x01
+#define TS 0x01
+#define TT 0x01
+#define CTL_PERIODIC 0x00
+#define CTL_ONESHOT 0x02
+#define CTL_FREERUN 0x02
+
+static struct ostm_device *ced_to_ostm(struct clock_event_device *ced)
+{
+ return container_of(ced, struct ostm_device, ced);
+}
+
+static int __init ostm_init_clksrc(struct ostm_device *ostm)
+{
+ int ret;
+
+ /* irq not used (clock sources don't use interrupts) */
+
+ /* stop counter */
+ iowrite8(TT, ostm->base + OSTM_TT);
+ while (ioread8(ostm->base + OSTM_TE) & TE)
+ ;
+
+ /* setup as freerun */
+ iowrite32(0, ostm->base + OSTM_CMP);
+ iowrite8(CTL_FREERUN, ostm->base + OSTM_CTL);
+ iowrite8(TS, ostm->base + OSTM_TS);
+
+ /* register */
+ ret = clocksource_mmio_init(ostm->base + OSTM_CNT,
+ "ostm", ostm->rate,
+ 300, 32, clocksource_mmio_readl_up);
+
+ return ret;
+}
+
+static u64 notrace ostm_read_sched_clock(void)
+{
+ return ioread32(system_clock);
+}
+
+static int __init ostm_init_sched_clock(struct ostm_device *ostm)
+{
+ unsigned long flags;
+
+ system_clock = ostm->base + OSTM_CNT;
+ local_irq_save(flags);
+ local_irq_disable();
+ sched_clock_register(ostm_read_sched_clock, 32, ostm->rate);
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static void ostm_clkevt_timer_stop(struct ostm_device *ostm)
+{
+ if (ioread8(ostm->base + OSTM_TE) & TE) {
+ iowrite8(TT, ostm->base + OSTM_TT);
+ while (ioread8(ostm->base + OSTM_TE) & TE)
+ ;
+ }
+}
+
+static int ostm_clock_event_next(unsigned long delta,
+ struct clock_event_device *ced)
+{
+ struct ostm_device *ostm = ced_to_ostm(ced);
+
+ WARN_ON(!clockevent_state_oneshot(ced));
+
+ ostm_clkevt_timer_stop(ostm);
+
+ iowrite32(delta, ostm->base + OSTM_CMP);
+ iowrite8(CTL_ONESHOT, ostm->base + OSTM_CTL);
+ iowrite8(TS, ostm->base + OSTM_TS);
+
+ return 0;
+}
+
+static int ostm_shutdown(struct clock_event_device *ced)
+{
+ struct ostm_device *ostm = ced_to_ostm(ced);
+
+ ostm_clkevt_timer_stop(ostm);
+
+ return 0;
+}
+static int ostm_set_periodic(struct clock_event_device *ced)
+{
+ struct ostm_device *ostm = ced_to_ostm(ced);
+
+ if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
+ ostm_clkevt_timer_stop(ostm);
+
+ iowrite32(ostm->ticks_per_jiffy - 1, ostm->base + OSTM_CMP);
+ iowrite8(CTL_PERIODIC, ostm->base + OSTM_CTL);
+ iowrite8(TS, ostm->base + OSTM_TS);
+
+ return 0;
+}
+
+static int ostm_set_oneshot(struct clock_event_device *ced)
+{
+ struct ostm_device *ostm = ced_to_ostm(ced);
+
+ ostm_clkevt_timer_stop(ostm);
+
+ return 0;
+}
+
+static irqreturn_t ostm_timer_interrupt(int irq, void *dev_id)
+{
+ struct ostm_device *ostm = dev_id;
+
+ if (clockevent_state_oneshot(&ostm->ced))
+ ostm_clkevt_timer_stop(ostm);
+
+ /* notify clockevent layer */
+ if (ostm->ced.event_handler)
+ ostm->ced.event_handler(&ostm->ced);
+
+ return IRQ_HANDLED;
+}
+
+static int __init ostm_init_clkevt(struct ostm_device *ostm)
+{
+ struct clock_event_device *ced = &ostm->ced;
+ int ret = -ENXIO;
+
+ ret = request_irq(ostm->irq, ostm_timer_interrupt,
+ IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
+ dev_name(&ostm->pdev->dev), ostm);
+ if (ret) {
+ dev_err(&ostm->pdev->dev, "failed to request irq\n");
+ return ret;
+ }
+
+ ced->name = "ostm";
+ ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;
+ ced->set_state_shutdown = ostm_shutdown;
+ ced->set_state_periodic = ostm_set_periodic;
+ ced->set_state_oneshot = ostm_set_oneshot;
+ ced->set_next_event = ostm_clock_event_next;
+ ced->shift = 32;
+ ced->rating = 300;
+ ced->cpumask = cpumask_of(0);
+ clockevents_config_and_register(ced, ostm->rate, 0xf, 0xffffffff);
+
+ return 0;
+}
+
+static int __init ostm_probe(struct platform_device *pdev)
+{
+ struct ostm_device *ostm;
+ struct resource *res;
+ int ret = -EFAULT;
+
+ if (!is_early_platform_device(pdev)) {
+ pm_runtime_set_active(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
+ }
+
+ ostm = platform_get_drvdata(pdev);
+ if (ostm) {
+ dev_info(&pdev->dev, "kept as earlytimer\n");
+ ret = 0;
+ goto out;
+ }
+
+ ostm = kzalloc(sizeof(*ostm), GFP_KERNEL);
+ if (!ostm) {
+ dev_err(&pdev->dev, "failed to allocate memory\n");
+ return -ENOMEM;
+ }
+
+ ostm->pdev = pdev;
+ platform_set_drvdata(ostm->pdev, ostm);
+
+ res = platform_get_resource(ostm->pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&ostm->pdev->dev, "failed to get I/O memory\n");
+ goto err;
+ }
+
+ ostm->base = ioremap_nocache(res->start, resource_size(res));
+ if (!ostm->base) {
+ dev_err(&ostm->pdev->dev, "failed to remap I/O memory\n");
+ goto err;
+ }
+
+ ostm->irq = platform_get_irq(ostm->pdev, 0);
+ if (ostm->irq < 0) {
+ dev_err(&ostm->pdev->dev, "failed to get irq\n");
+ goto err;
+ }
+
+ ostm->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(ostm->clk)) {
+ dev_err(&ostm->pdev->dev, "failed to get clock\n");
+ ostm->clk = NULL;
+ goto err;
+ }
+
+ ret = clk_prepare_enable(ostm->clk);
+ if (ret) {
+ dev_err(&ostm->pdev->dev, "failed to enable clock\n");
+ goto err;
+ }
+
+ ostm->rate = clk_get_rate(ostm->clk);
+ ostm->ticks_per_jiffy = (ostm->rate + HZ / 2) / HZ;
+
+ /* First probed device will be used as system clocksource */
+ if (!system_clock) {
+ /* use as clocksource */
+ ret = ostm_init_clksrc(ostm);
+
+ /* use as system scheduling clock */
+ if (!ret)
+ ret = ostm_init_sched_clock(ostm);
+
+ if (ret) {
+ dev_err(&pdev->dev, "failed to use as sched_clock\n");
+ system_clock = (void *)-1; /* prevent future attempts */
+ ret = 0; /* still works as clocksource */
+ }
+
+ if (!ret)
+ dev_info(&pdev->dev, "used for clocksource\n");
+ } else {
+ /* use as clock event */
+ ret = ostm_init_clkevt(ostm);
+
+ if (!ret)
+ dev_info(&pdev->dev, "used for clock events\n");
+ }
+
+err:
+ if (ret) {
+ if (ostm->clk)
+ clk_disable_unprepare(ostm->clk);
+ if (ostm->base)
+ iounmap(ostm->base);
+ kfree(ostm);
+ platform_set_drvdata(pdev, NULL);
+ pm_runtime_idle(&pdev->dev);
+ return ret;
+ }
+
+ if (is_early_platform_device(pdev))
+ return ret;
+
+out:
+ pm_runtime_irq_safe(&pdev->dev);
+
+ return ret;
+}
+
+static int ostm_remove(struct platform_device *pdev)
+{
+ return -EBUSY; /* cannot unregister clockevent */
+}
+
+static const struct of_device_id ostm_of_table[] __maybe_unused = {
+ { .compatible = "renesas,ostm" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, ostm_of_table);
+
+static struct platform_driver ostm_timer = {
+ .probe = ostm_probe,
+ .remove = ostm_remove,
+ .driver = {
+ .name = "ostm",
+ .of_match_table = of_match_ptr(ostm_of_table),
+ },
+};
+
+static int __init ostm_init(void)
+{
+ return platform_driver_register(&ostm_timer);
+}
+
+static void __exit ostm_exit(void)
+{
+ platform_driver_unregister(&ostm_timer);
+}
+
+early_platform_init("earlytimer", &ostm_timer);
+subsys_initcall(ostm_init);
+module_exit(ostm_exit);
+
+MODULE_AUTHOR("Chris Brandt");
+MODULE_DESCRIPTION("Renesas OSTM Timer Driver");
+MODULE_LICENSE("GPL v2");
--
2.10.1
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox