* Re: [PATCH] of/platform: dynamic: Use of_platform_bus_create() to create devices
From: Alexander Sverdlin @ 2017-01-23 15:07 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Frank Rowand,
Pantelis Antoniou, Grant Likely
In-Reply-To: <CAL_JsqKb8KUgit-q_cOON8VgZBsrXEQd2EcC0iF=ou_271Vg_w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hi Rob,
On 21/01/17 20:51, Rob Herring wrote:
> On Fri, Jan 20, 2017 at 11:38 AM, Alexander Sverdlin
> <alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org> wrote:
>> Hello Rob,
>>
>> On 27/10/16 15:00, Rob Herring wrote:
>>>> @@ -534,15 +535,15 @@ static int of_platform_notify(struct notifier_block *nb,
>>>>
>>>> /* pdev_parent may be NULL when no bus platform device */
>>>> pdev_parent = of_find_device_by_node(rd->dn->parent);
>>>> - pdev = of_platform_device_create(rd->dn, NULL,
>>>> - pdev_parent ? &pdev_parent->dev : NULL);
>>>> + ret = of_platform_bus_create(rd->dn, of_default_bus_match_table,
>>>> + NULL, pdev_parent ?
>>>> + &pdev_parent->dev : NULL, true);
>>> I think this should be of_platform_default_populate() instead.
>> I've just tested: it cannot be. It calls of_platform_populate(), which ignores "status" property.
>> This not only brakes half of the unit tests, but also would change the existing behavior of
>> overlays (they will completely ignore "status" too).
> That's a bug. I assume that's only at the 1st level or things would be
> completely broken.
well, after two unsuccessful attempts to use of_platform_default_populate() in of_platform_notify()
I see what the actual problem is: of_platform_*populate() do not populate the root node itself,
therefore they are not suitable for of_platform_notify().
--
Best regards,
Alexander Sverdlin.
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* Re: [PATCH v2] of/platform: Ignore disabled devices in of_platform_populate()
From: Alexander Sverdlin @ 2017-01-23 15:09 UTC (permalink / raw)
Cc: Rob Herring, Frank Rowand, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <711e6067-ab41-8217-b947-2b4c356aaaba-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
On 23/01/17 15:33, Alexander Sverdlin wrote:
>> Check the status property and give up early enough. Otherwise
>> OF_POPULATED_BUS might be set for disabled bus which will prevent
>> it from being populated later (if enabled).
>>
>> Signed-off-by: Alexander Sverdlin <alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
>> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Cc: Frank Rowand <frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> ---
>> drivers/of/platform.c | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/of/platform.c b/drivers/of/platform.c
>> index 35de1fc59fa6..060621d94f1a 100644
>> --- a/drivers/of/platform.c
>> +++ b/drivers/of/platform.c
>> @@ -476,6 +476,10 @@ int of_platform_populate(struct device_node *root,
>> root = root ? of_node_get(root) : of_find_node_by_path("/");
>> if (!root)
>> return -EINVAL;
>> + if (!of_device_is_available(root)) {
>> + of_node_put(root);
>> + return 0;
>> + }
>>
>> pr_debug("%s()\n", __func__);
>> pr_debug(" starting at: %s\n", root->full_name);
> no, this one also doesn't allow to switch to of_platform_default_populate(),
> please ignore the patch.
Well, the patch seems to fix a real problem because OF_POPULATED_BUS would be
set for disabled buses, which will prevent their enabling later. Even if there
is no in-tree call site stumbles upon this issue.
--
Best regards,
Alexander Sverdlin.
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* Re: [PATCH] ARM: dts: r7s72100: add power-domains to mmcif
From: Geert Uytterhoeven @ 2017-01-23 15:12 UTC (permalink / raw)
To: Chris Brandt
Cc: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland,
devicetree@vger.kernel.org, Linux-Renesas
In-Reply-To: <20170123141349.29844-1-chris.brandt@renesas.com>
On Mon, Jan 23, 2017 at 3:13 PM, Chris Brandt <chris.brandt@renesas.com> wrote:
> Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v3 2/3] ARM: dts: r7s72100: add ostm to device tree
From: Geert Uytterhoeven @ 2017-01-23 15:12 UTC (permalink / raw)
To: Chris Brandt
Cc: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland,
Russell King, Thomas Gleixner, Geert Uytterhoeven,
devicetree@vger.kernel.org, Linux-Renesas
In-Reply-To: <20170123135520.28834-3-chris.brandt@renesas.com>
On Mon, Jan 23, 2017 at 2:55 PM, Chris Brandt <chris.brandt@renesas.com> wrote:
> Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v3 3/3] ARM: dts: rskrza1: add ostm DT support
From: Geert Uytterhoeven @ 2017-01-23 15:13 UTC (permalink / raw)
To: Chris Brandt
Cc: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland,
Russell King, Thomas Gleixner, Geert Uytterhoeven,
devicetree@vger.kernel.org, Linux-Renesas
In-Reply-To: <20170123135520.28834-4-chris.brandt@renesas.com>
On Mon, Jan 23, 2017 at 2:55 PM, Chris Brandt <chris.brandt@renesas.com> wrote:
> Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [RFC] ARM: dts: imx53-qsb-common: fix FEC pinmux config
From: linux-kernel-dev @ 2017-01-23 15:14 UTC (permalink / raw)
To: shawnguo, kernel
Cc: fabio.estevam, robh+dt, mark.rutland, linux, linux-arm-kernel,
devicetree, linux-kernel, Patrick Bruenn
From: Patrick Bruenn <p.bruenn@beckhoff.com>
The pinmux configuration in device tree is different from manual
muxing in <u-boot>/board/freescale/mx53loco/mx53loco.c
It seems the device tree configuration is never used by any kernel
driver and the correct setting, preconfigured by u-boot, was never
overwritten. So this issue never showed up anywhere.
---
I stumbled upon this difference, while adding the imx53 based CX9020
Embedded PC to u-boot bootloader. "New" boards are encouraged to use
device tree for pinmuxing in u-boot, so I tried to reuse
imx53-qsb-common.dtsi for that. That failed with a high packet loss on
the fec_mxc device. With the attached patch that device tree based
pinmuxing seems successful in u-boot. My suggestion is to apply it to
imx53-qsb-common.dtsi, too. That will help other "late adopters" and
prevent similar issues, in case any kernel driver starts using this
pinmux configurations.
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
---
arch/arm/boot/dts/imx53-qsb-common.dtsi | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi
index c05e7cfd0cbc..40b3e31935d0 100644
--- a/arch/arm/boot/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
@@ -215,16 +215,16 @@
pinctrl_fec: fecgrp {
fsl,pins = <
- MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
- MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
- MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
- MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
- MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
- MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
- MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
- MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
- MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
- MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
+ MX53_PAD_FEC_MDC__FEC_MDC 0x4
+ MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
>;
};
--
2.11.0
^ permalink raw reply related
* Re: [PATCH 1/5] drm: zte: add interlace mode support
From: Sean Paul @ 2017-01-23 15:19 UTC (permalink / raw)
To: Shawn Guo
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA, Daniel Vetter, Baoyou Xie,
Rob Herring, Jun Nie
In-Reply-To: <1484843100-16284-2-git-send-email-shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
On Fri, Jan 20, 2017 at 12:24:56AM +0800, Shawn Guo wrote:
> From: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>
> It adds interlace mode support in VOU TIMING_CTRL and channel control
> block, so that VOU driver gets ready to support output device in
> interlace mode like TV Encoder.
>
> Signed-off-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> drivers/gpu/drm/zte/zx_vou.c | 53 +++++++++++++++++++++++++++++++++++++--
> drivers/gpu/drm/zte/zx_vou_regs.h | 15 +++++++++++
> 2 files changed, 66 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/zte/zx_vou.c b/drivers/gpu/drm/zte/zx_vou.c
> index 3056b41df518..8c4f0e2885f3 100644
> --- a/drivers/gpu/drm/zte/zx_vou.c
> +++ b/drivers/gpu/drm/zte/zx_vou.c
<snip>
> @@ -196,19 +211,26 @@ static inline void vou_chn_set_update(struct zx_crtc *zcrtc)
> static void zx_crtc_enable(struct drm_crtc *crtc)
> {
> struct drm_display_mode *mode = &crtc->state->adjusted_mode;
> + bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
> struct zx_crtc *zcrtc = to_zx_crtc(crtc);
> struct zx_vou_hw *vou = zcrtc->vou;
> const struct zx_crtc_regs *regs = zcrtc->regs;
> const struct zx_crtc_bits *bits = zcrtc->bits;
> struct videomode vm;
> + u32 vactive;
> u32 pol = 0;
> u32 val;
> + u32 mask;
> int ret;
>
> drm_display_mode_to_videomode(mode, &vm);
>
> /* Set up timing parameters */
> - val = V_ACTIVE(vm.vactive - 1);
> + vactive = vm.vactive;
> + if (interlaced)
> + vactive /= 2;
> +
> + val = V_ACTIVE(vactive - 1);
Instead of introducing a new var, I think you can get away with:
if (interlaced)
val = V_ACTIVE(vm.vactive / 2);
else
val = V_ACTIVE(vm.vactive - 1);
> val |= H_ACTIVE(vm.hactive - 1);
> zx_writel(vou->timing + regs->fir_active, val);
>
> @@ -222,6 +244,22 @@ static void zx_crtc_enable(struct drm_crtc *crtc)
> val |= FRONT_PORCH(vm.vfront_porch - 1);
> zx_writel(vou->timing + regs->fir_vtiming, val);
>
> + if (interlaced) {
> + u32 shift = bits->sec_vactive_shift;
> + u32 mask = bits->sec_vactive_mask;
mask is already defined at the function scope
> +
> + val = zx_readl(vou->timing + SEC_V_ACTIVE);
> + val &= ~mask;
> + val |= ((vactive - 1) << shift) & mask;
> + zx_writel(vou->timing + SEC_V_ACTIVE, val);
> +
> + val = SYNC_WIDE(vm.vsync_len - 1);
> + /* sec_vbp = fir_vbp + 1 */
Looks like leftover kruft here.
> + val |= BACK_PORCH(vm.vback_porch);
> + val |= FRONT_PORCH(vm.vfront_porch - 1);
> + zx_writel(vou->timing + regs->sec_vtiming, val);
> + }
> +
> /* Set up polarities */
> if (vm.flags & DISPLAY_FLAGS_VSYNC_LOW)
> pol |= 1 << POL_VSYNC_SHIFT;
> @@ -232,9 +270,16 @@ static void zx_crtc_enable(struct drm_crtc *crtc)
> pol << bits->polarity_shift);
>
> /* Setup SHIFT register by following what ZTE BSP does */
> - zx_writel(vou->timing + regs->timing_shift, H_SHIFT_VAL);
> + val = H_SHIFT_VAL;
> + if (interlaced)
> + val |= V_SHIFT_VAL << 16;
> + zx_writel(vou->timing + regs->timing_shift, val);
> zx_writel(vou->timing + regs->timing_pi_shift, H_PI_SHIFT_VAL);
>
> + /* Progressive or interlace scan select */
> + mask = bits->interlace_select | bits->pi_enable;
> + zx_writel_mask(vou->timing + SCAN_CTRL, mask, interlaced ? mask : 0);
> +
> /* Enable TIMING_CTRL */
> zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable,
> bits->tc_enable);
> @@ -245,6 +290,10 @@ static void zx_crtc_enable(struct drm_crtc *crtc)
> zx_writel_mask(zcrtc->chnreg + CHN_CTRL1, CHN_SCREEN_H_MASK,
> vm.vactive << CHN_SCREEN_H_SHIFT);
>
> + /* Configure channel interlace buffer control */
> + zx_writel_mask(zcrtc->chnreg + CHN_INTERLACE_BUF_CTRL, CHN_INTERLACE_EN,
> + interlaced ? CHN_INTERLACE_EN : 0);
> +
> /* Update channel */
> vou_chn_set_update(zcrtc);
>
> diff --git a/drivers/gpu/drm/zte/zx_vou_regs.h b/drivers/gpu/drm/zte/zx_vou_regs.h
> index 193c1ce01fe7..e6ed844e068a 100644
> --- a/drivers/gpu/drm/zte/zx_vou_regs.h
> +++ b/drivers/gpu/drm/zte/zx_vou_regs.h
> @@ -75,6 +75,8 @@
> #define CHN_SCREEN_H_SHIFT 5
> #define CHN_SCREEN_H_MASK (0x1fff << CHN_SCREEN_H_SHIFT)
> #define CHN_UPDATE 0x08
> +#define CHN_INTERLACE_BUF_CTRL 0x24
Maybe it's my email reader, but it seems like there's an alignment issue here.
> +#define CHN_INTERLACE_EN BIT(2)
>
> /* TIMING_CTRL registers */
> #define TIMING_TC_ENABLE 0x04
> @@ -117,6 +119,19 @@
> #define TIMING_MAIN_SHIFT 0x2c
> #define TIMING_AUX_SHIFT 0x30
> #define H_SHIFT_VAL 0x0048
> +#define V_SHIFT_VAL 0x0001
> +#define SCAN_CTRL 0x34
> +#define AUX_PI_EN BIT(19)
> +#define MAIN_PI_EN BIT(18)
> +#define AUX_INTERLACE_SEL BIT(1)
> +#define MAIN_INTERLACE_SEL BIT(0)
> +#define SEC_V_ACTIVE 0x38
> +#define SEC_VACT_MAIN_SHIFT 0
> +#define SEC_VACT_MAIN_MASK (0xffff << SEC_VACT_MAIN_SHIFT)
> +#define SEC_VACT_AUX_SHIFT 16
> +#define SEC_VACT_AUX_MASK (0xffff << SEC_VACT_AUX_SHIFT)
> +#define SEC_MAIN_V_TIMING 0x3c
> +#define SEC_AUX_V_TIMING 0x40
> #define TIMING_MAIN_PI_SHIFT 0x68
> #define TIMING_AUX_PI_SHIFT 0x6c
> #define H_PI_SHIFT_VAL 0x000f
> --
> 1.9.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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^ permalink raw reply
* Re: [alsa-devel] [PATCH v4 3/4] ASoC: rockchip: Add machine driver for RK3288 boards that use analog/HDMI
From: kbuild test robot @ 2017-01-23 15:24 UTC (permalink / raw)
Cc: kbuild-all-JC7UmRfGjtg, Liam Girdwood, Mark Brown,
Jaroslav Kysela, Takashi Iwai, alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
Heiko Stuebner, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
Pawel Moll, Ian Campbell,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Sjoerd Simons,
Rob Herring, Kumar Gala, Romain Perier
In-Reply-To: <20170123104149.2508-4-romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Hi Romain,
[auto build test WARNING on rockchip/for-next]
[also build test WARNING on v4.10-rc5 next-20170123]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Romain-Perier/Add-support-for-es8388-and-hdmi-audio-on-the-rock2/20170123-220028
base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
coccinelle warnings: (new ones prefixed by >>)
>> sound/soc/rockchip/rk3288_hdmi_analog.c:288:3-8: No need to set .owner here. The core will do it.
Please review and possibly fold the followup patch.
---
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https://lists.01.org/pipermail/kbuild-all Intel Corporation
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* [PATCH] ASoC: rockchip: fix platform_no_drv_owner.cocci warnings
From: kbuild test robot @ 2017-01-23 15:24 UTC (permalink / raw)
Cc: kbuild-all-JC7UmRfGjtg, Liam Girdwood, Mark Brown,
Jaroslav Kysela, Takashi Iwai, alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
Heiko Stuebner, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
Pawel Moll, Ian Campbell,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Sjoerd Simons,
Rob Herring, Kumar Gala, Romain Perier
In-Reply-To: <20170123104149.2508-4-romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
sound/soc/rockchip/rk3288_hdmi_analog.c:288:3-8: No need to set .owner here. The core will do it.
Remove .owner field if calls are used which set it automatically
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
CC: Romain Perier <romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Signed-off-by: Fengguang Wu <fengguang.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
---
rk3288_hdmi_analog.c | 1 -
1 file changed, 1 deletion(-)
--- a/sound/soc/rockchip/rk3288_hdmi_analog.c
+++ b/sound/soc/rockchip/rk3288_hdmi_analog.c
@@ -285,7 +285,6 @@ static struct platform_driver rockchip_s
.probe = snd_rk_mc_probe,
.driver = {
.name = DRV_NAME,
- .owner = THIS_MODULE,
.pm = &snd_soc_pm_ops,
.of_match_table = rockchip_sound_of_match,
},
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^ permalink raw reply
* Re: [PATCH 2/5] drm: zte: move struct vou_inf into zx_vou driver
From: Sean Paul @ 2017-01-23 15:30 UTC (permalink / raw)
To: Shawn Guo
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA, Daniel Vetter, Baoyou Xie,
Rob Herring, Jun Nie
In-Reply-To: <1484843100-16284-3-git-send-email-shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
On Fri, Jan 20, 2017 at 12:24:57AM +0800, Shawn Guo wrote:
> From: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>
> Although data in struct vou_inf is defined per output device, it doesn't
> belong to the device itself but VOU control module. All these data can
> just be defined in VOU driver, and output device driver only needs to
> invoke VOU driver function with device ID to enable/disable specific
> output device.
>
Reviewed-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> Signed-off-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> drivers/gpu/drm/zte/zx_hdmi.c | 12 ++----------
> drivers/gpu/drm/zte/zx_vou.c | 31 ++++++++++++++++++++++++-------
> drivers/gpu/drm/zte/zx_vou.h | 11 ++---------
> 3 files changed, 28 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/zte/zx_hdmi.c b/drivers/gpu/drm/zte/zx_hdmi.c
> index 6bf6c364811e..2f1e278ab50e 100644
> --- a/drivers/gpu/drm/zte/zx_hdmi.c
> +++ b/drivers/gpu/drm/zte/zx_hdmi.c
> @@ -53,13 +53,6 @@ struct zx_hdmi {
>
> #define to_zx_hdmi(x) container_of(x, struct zx_hdmi, x)
>
> -static const struct vou_inf vou_inf_hdmi = {
> - .id = VOU_HDMI,
> - .data_sel = VOU_YUV444,
> - .clocks_en_bits = BIT(24) | BIT(18) | BIT(6),
> - .clocks_sel_bits = BIT(13) | BIT(2),
> -};
> -
> static inline u8 hdmi_readb(struct zx_hdmi *hdmi, u16 offset)
> {
> return readl_relaxed(hdmi->mmio + offset * 4);
> @@ -238,14 +231,14 @@ static void zx_hdmi_encoder_enable(struct drm_encoder *encoder)
>
> zx_hdmi_hw_enable(hdmi);
>
> - vou_inf_enable(hdmi->inf, encoder->crtc);
> + vou_inf_enable(VOU_HDMI, encoder->crtc);
> }
>
> static void zx_hdmi_encoder_disable(struct drm_encoder *encoder)
> {
> struct zx_hdmi *hdmi = to_zx_hdmi(encoder);
>
> - vou_inf_disable(hdmi->inf, encoder->crtc);
> + vou_inf_disable(VOU_HDMI, encoder->crtc);
>
> zx_hdmi_hw_disable(hdmi);
>
> @@ -523,7 +516,6 @@ static int zx_hdmi_bind(struct device *dev, struct device *master, void *data)
>
> hdmi->dev = dev;
> hdmi->drm = drm;
> - hdmi->inf = &vou_inf_hdmi;
>
> dev_set_drvdata(dev, hdmi);
>
> diff --git a/drivers/gpu/drm/zte/zx_vou.c b/drivers/gpu/drm/zte/zx_vou.c
> index 8c4f0e2885f3..c48704b4425a 100644
> --- a/drivers/gpu/drm/zte/zx_vou.c
> +++ b/drivers/gpu/drm/zte/zx_vou.c
> @@ -158,6 +158,21 @@ struct zx_vou_hw {
> struct zx_crtc *aux_crtc;
> };
>
> +struct vou_inf {
> + enum vou_inf_id id;
> + enum vou_inf_data_sel data_sel;
> + u32 clocks_en_bits;
> + u32 clocks_sel_bits;
> +};
> +
> +static struct vou_inf vou_infs[] = {
> + [VOU_HDMI] = {
> + .data_sel = VOU_YUV444,
> + .clocks_en_bits = BIT(24) | BIT(18) | BIT(6),
> + .clocks_sel_bits = BIT(13) | BIT(2),
> + },
> +};
> +
> static inline struct zx_vou_hw *crtc_to_vou(struct drm_crtc *crtc)
> {
> struct zx_crtc *zcrtc = to_zx_crtc(crtc);
> @@ -165,20 +180,21 @@ static inline struct zx_vou_hw *crtc_to_vou(struct drm_crtc *crtc)
> return zcrtc->vou;
> }
>
> -void vou_inf_enable(const struct vou_inf *inf, struct drm_crtc *crtc)
> +void vou_inf_enable(enum vou_inf_id id, struct drm_crtc *crtc)
> {
> struct zx_crtc *zcrtc = to_zx_crtc(crtc);
> struct zx_vou_hw *vou = zcrtc->vou;
> + struct vou_inf *inf = &vou_infs[id];
> bool is_main = zcrtc->chn_type == VOU_CHN_MAIN;
> - u32 data_sel_shift = inf->id << 1;
> + u32 data_sel_shift = id << 1;
>
> /* Select data format */
> zx_writel_mask(vou->vouctl + VOU_INF_DATA_SEL, 0x3 << data_sel_shift,
> inf->data_sel << data_sel_shift);
>
> /* Select channel */
> - zx_writel_mask(vou->vouctl + VOU_INF_CH_SEL, 0x1 << inf->id,
> - zcrtc->chn_type << inf->id);
> + zx_writel_mask(vou->vouctl + VOU_INF_CH_SEL, 0x1 << id,
> + zcrtc->chn_type << id);
>
> /* Select interface clocks */
> zx_writel_mask(vou->vouctl + VOU_CLK_SEL, inf->clocks_sel_bits,
> @@ -189,15 +205,16 @@ void vou_inf_enable(const struct vou_inf *inf, struct drm_crtc *crtc)
> inf->clocks_en_bits);
>
> /* Enable the device */
> - zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << inf->id, 1 << inf->id);
> + zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << id, 1 << id);
> }
>
> -void vou_inf_disable(const struct vou_inf *inf, struct drm_crtc *crtc)
> +void vou_inf_disable(enum vou_inf_id id, struct drm_crtc *crtc)
> {
> struct zx_vou_hw *vou = crtc_to_vou(crtc);
> + struct vou_inf *inf = &vou_infs[id];
>
> /* Disable the device */
> - zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << inf->id, 0);
> + zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << id, 0);
>
> /* Disable interface clocks */
> zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits, 0);
> diff --git a/drivers/gpu/drm/zte/zx_vou.h b/drivers/gpu/drm/zte/zx_vou.h
> index 4b4339be641b..a41a0ad49857 100644
> --- a/drivers/gpu/drm/zte/zx_vou.h
> +++ b/drivers/gpu/drm/zte/zx_vou.h
> @@ -30,15 +30,8 @@ enum vou_inf_data_sel {
> VOU_RGB_666 = 3,
> };
>
> -struct vou_inf {
> - enum vou_inf_id id;
> - enum vou_inf_data_sel data_sel;
> - u32 clocks_en_bits;
> - u32 clocks_sel_bits;
> -};
> -
> -void vou_inf_enable(const struct vou_inf *inf, struct drm_crtc *crtc);
> -void vou_inf_disable(const struct vou_inf *inf, struct drm_crtc *crtc);
> +void vou_inf_enable(enum vou_inf_id id, struct drm_crtc *crtc);
> +void vou_inf_disable(enum vou_inf_id id, struct drm_crtc *crtc);
>
> int zx_vou_enable_vblank(struct drm_device *drm, unsigned int pipe);
> void zx_vou_disable_vblank(struct drm_device *drm, unsigned int pipe);
> --
> 1.9.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Sean Paul, Software Engineer, Google / Chromium OS
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^ permalink raw reply
* Re: [PATCH] usb: dwc3: add quirk to handle DWC_USB3_NUM == DWC_USB3_NUM_IN_EPS
From: Rob Herring @ 2017-01-23 15:38 UTC (permalink / raw)
To: Bryan O'Donoghue
Cc: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, mark.rutland-5wv7dgnIgG8,
balbi-DgEjT+Ai2ygdnm+yROfE0A, linux-usb-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1484855882-4936-1-git-send-email-pure.logic-SyKdqv6vbfZdzvEItQ6vdLNAH6kLmebB@public.gmane.org>
On Thu, Jan 19, 2017 at 07:58:02PM +0000, Bryan O'Donoghue wrote:
> - DWC_USB3_NUM indicates the number of Device mode single directional
> endpoints, including OUT and IN endpoint 0.
>
> - DWC_USB3_NUM_IN_EPS indicates the maximum number of Device mode IN
> endpoints active at any time, including control endpoint 0.
>
> It's possible to configure RTL such that DWC_USB3_NUM_EPS is equal to
> DWC_USB3_NUM_IN_EPS.
>
> dwc3-core calculates the number of OUT endpoints as DWC_USB3_NUM minus
> DWC_USB3_NUM_IN_EPS. If RTL has been configured with DWC_USB3_NUM_IN_EPS
> equal to DWC_USB3_NUM then dwc3-core will calculate the number of OUT
> endpoints as zero.
>
> For example a from dwc3_core_num_eps() shows:
> [ 1.565000] /usb0@f01d0000: found 8 IN and 0 OUT endpoints
>
> This patch fixes this case by adding a snps,num_in_eps quirk and an
> over-ride value for DWC_USB3_NUM_IN_EPS snps,num_in_eps_override. When the
> quirk is declared then snps,num_in_eps_override will be used instead of
> DWC_USB3_NUM_IN_EPS as the value of the number active IN endpoints.
>
> The minimum value specified for DWC_USB3_NUM_IN_EPS in the Designware
> data-book is two, if snps,num_in_eps_quirk is declared but
> snps,num_in_eps_override is omitted, then the minimum value will be used as
> the default.
>
> Signed-off-by: Bryan O'Donoghue <pure.logic-SyKdqv6vbfZdzvEItQ6vdLNAH6kLmebB@public.gmane.org>
> ---
> Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++
> drivers/usb/dwc3/core.c | 11 +++++++++++
> drivers/usb/dwc3/core.h | 6 ++++++
> 3 files changed, 20 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
> index e3e6983..bb383bf 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> @@ -55,6 +55,9 @@ Optional properties:
> fladj_30mhz_sdbnd signal is invalid or incorrect.
>
> - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
> + - snps,num_in_eps_quirk: when set core will over-ride the num_in_eps value.
> + - snps,num_in_eps_override: the value that will be used for num_in_eps when
> + num_in_eps_quirk is true
Why do you need 2 properties? Presence of the prop eanbles the override
and the value of the prop provides the value.
Use '-' rather than '_'.
>
> This is usually a subnode to DWC3 glue to which it is connected.
>
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^ permalink raw reply
* Re: [PATCH v7 1/3] doc: dt: add cyclone-ps-spi binding document
From: Rob Herring @ 2017-01-23 15:39 UTC (permalink / raw)
To: Joshua Clayton
Cc: Alan Tull, Moritz Fischer, Russell King, Shawn Guo, Sascha Hauer,
Fabio Estevam, Mark Rutland, Anatolij Gustschin, devicetree,
linux-kernel, linux-arm-kernel, linux-fpga
In-Reply-To: <6b7883678d1e343d103302c77863bf69ca836637.1484869881.git.stillcompiling@gmail.com>
On Thu, Jan 19, 2017 at 04:12:27PM -0800, Joshua Clayton wrote:
> Describe a cyclone-ps-spi devicetree entry, required features
>
> Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
> ---
> .../bindings/fpga/altera-passive-serial.txt | 25 ++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v4 2/9] ARM: dts: rockchip: update compatible property for rk3228 timer
From: Daniel Lezcano @ 2017-01-23 15:40 UTC (permalink / raw)
To: Alexander Kochetkov
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Thomas Gleixner,
Heiko Stuebner, Mark Rutland, Rob Herring, Russell King,
Caesar Wang, Huang Tao
In-Reply-To: <1480436092-10728-3-git-send-email-al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Tue, Nov 29, 2016 at 07:14:45PM +0300, Alexander Kochetkov wrote:
> Property set to '"rockchip,rk3228-timer", "rockchip,rk3288-timer"'
> to match devicetree bindings.
>
> Signed-off-by: Alexander Kochetkov <al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> arch/arm/boot/dts/rk3228-evb.dts | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts
> index 904668e..38eab87 100644
> --- a/arch/arm/boot/dts/rk3228-evb.dts
> +++ b/arch/arm/boot/dts/rk3228-evb.dts
> @@ -70,3 +70,7 @@
> &uart2 {
> status = "okay";
> };
> +
> +&timer {
> + compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
> +};
I'm not sure this is correct, to which timer &timer will refer ?
timer {
compatible = "arm,armv7-timer";
...
}
timer: timer@110c0000 {
compatible = "rockchip,rk3288-timer";
...
}
Why not change the compatible string in the timer definition in rk322x.dtsi ?
Same comment for the other patches doing these changes.
-- Daniel
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
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^ permalink raw reply
* Re: [PATCH 3/5] drm: zte: add function to configure vou_ctrl dividers
From: Sean Paul @ 2017-01-23 15:47 UTC (permalink / raw)
To: Shawn Guo
Cc: Mark Rutland, devicetree, Daniel Vetter, Baoyou Xie, dri-devel,
Rob Herring, Jun Nie
In-Reply-To: <1484843100-16284-4-git-send-email-shawnguo@kernel.org>
On Fri, Jan 20, 2017 at 12:24:58AM +0800, Shawn Guo wrote:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> The clock control module (CRM) cannot always provide desired frequency
> for all VOU output devices. That's why VOU integrates a few dividers
> to further divide the clocks from CRM. Let's add an interface for
> configuring these dividers.
>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> drivers/gpu/drm/zte/zx_vou.c | 79 +++++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/zte/zx_vou.h | 25 +++++++++++++
> drivers/gpu/drm/zte/zx_vou_regs.h | 16 ++++++++
> 3 files changed, 120 insertions(+)
>
> diff --git a/drivers/gpu/drm/zte/zx_vou.c b/drivers/gpu/drm/zte/zx_vou.c
> index c48704b4425a..98f0f51f9748 100644
> --- a/drivers/gpu/drm/zte/zx_vou.c
> +++ b/drivers/gpu/drm/zte/zx_vou.c
> @@ -72,6 +72,13 @@ struct zx_crtc_bits {
> u32 sec_vactive_mask;
> u32 interlace_select;
> u32 pi_enable;
> + u32 div_vga_shift;
> + u32 div_pic_shift;
> + u32 div_tvenc_shift;
> + u32 div_hdmi_pnx_shift;
> + u32 div_hdmi_shift;
> + u32 div_inf_shift;
> + u32 div_layer_shift;
> };
>
> static const struct zx_crtc_bits main_crtc_bits = {
> @@ -83,6 +90,13 @@ struct zx_crtc_bits {
> .sec_vactive_mask = SEC_VACT_MAIN_MASK,
> .interlace_select = MAIN_INTERLACE_SEL,
> .pi_enable = MAIN_PI_EN,
> + .div_vga_shift = VGA_MAIN_DIV_SHIFT,
> + .div_pic_shift = PIC_MAIN_DIV_SHIFT,
> + .div_tvenc_shift = TVENC_MAIN_DIV_SHIFT,
> + .div_hdmi_pnx_shift = HDMI_MAIN_PNX_DIV_SHIFT,
> + .div_hdmi_shift = HDMI_MAIN_DIV_SHIFT,
> + .div_inf_shift = INF_MAIN_DIV_SHIFT,
> + .div_layer_shift = LAYER_MAIN_DIV_SHIFT,
> };
>
> static const struct zx_crtc_bits aux_crtc_bits = {
> @@ -94,6 +108,13 @@ struct zx_crtc_bits {
> .sec_vactive_mask = SEC_VACT_AUX_MASK,
> .interlace_select = AUX_INTERLACE_SEL,
> .pi_enable = AUX_PI_EN,
> + .div_vga_shift = VGA_AUX_DIV_SHIFT,
> + .div_pic_shift = PIC_AUX_DIV_SHIFT,
> + .div_tvenc_shift = TVENC_AUX_DIV_SHIFT,
> + .div_hdmi_pnx_shift = HDMI_AUX_PNX_DIV_SHIFT,
> + .div_hdmi_shift = HDMI_AUX_DIV_SHIFT,
> + .div_inf_shift = INF_AUX_DIV_SHIFT,
> + .div_layer_shift = LAYER_AUX_DIV_SHIFT,
> };
>
> struct zx_crtc {
> @@ -220,6 +241,64 @@ void vou_inf_disable(enum vou_inf_id id, struct drm_crtc *crtc)
> zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits, 0);
> }
>
> +void zx_vou_config_dividers(struct drm_crtc *crtc,
> + struct vou_div_config *configs, int num)
> +{
> + struct zx_crtc *zcrtc = to_zx_crtc(crtc);
> + struct zx_vou_hw *vou = zcrtc->vou;
> + const struct zx_crtc_bits *bits = zcrtc->bits;
> + int i;
> +
> + /* Clear update flag bit */
> + zx_writel_mask(vou->vouctl + VOU_DIV_PARA, DIV_PARA_UPDATE, 0);
> +
> + for (i = 0; i < num; i++) {
> + struct vou_div_config *cfg = configs + i;
> + u32 reg, shift;
> +
> + switch (cfg->id) {
> + case VOU_DIV_VGA:
> + reg = VOU_CLK_SEL;
> + shift = bits->div_vga_shift;
> + break;
> + case VOU_DIV_PIC:
> + reg = VOU_CLK_SEL;
> + shift = bits->div_pic_shift;
> + break;
> + case VOU_DIV_TVENC:
> + reg = VOU_DIV_PARA;
> + shift = bits->div_tvenc_shift;
> + break;
> + case VOU_DIV_HDMI_PNX:
> + reg = VOU_DIV_PARA;
> + shift = bits->div_hdmi_pnx_shift;
> + break;
> + case VOU_DIV_HDMI:
> + reg = VOU_DIV_PARA;
> + shift = bits->div_hdmi_shift;
> + break;
> + case VOU_DIV_INF:
> + reg = VOU_DIV_PARA;
> + shift = bits->div_inf_shift;
> + break;
> + case VOU_DIV_LAYER:
> + reg = VOU_DIV_PARA;
> + shift = bits->div_layer_shift;
> + break;
> + default:
> + continue;
> + }
> +
> + /* Each divider occupies 3 bits */
> + zx_writel_mask(vou->vouctl + reg, 0x7 << shift,
> + cfg->val << shift);
> + }
> +
> + /* Set update flag bit to get dividers effected */
> + zx_writel_mask(vou->vouctl + VOU_DIV_PARA, DIV_PARA_UPDATE,
> + DIV_PARA_UPDATE);
> +}
> +
> static inline void vou_chn_set_update(struct zx_crtc *zcrtc)
> {
> zx_writel(zcrtc->chnreg + CHN_UPDATE, 1);
> diff --git a/drivers/gpu/drm/zte/zx_vou.h b/drivers/gpu/drm/zte/zx_vou.h
> index a41a0ad49857..0dae4faefac4 100644
> --- a/drivers/gpu/drm/zte/zx_vou.h
> +++ b/drivers/gpu/drm/zte/zx_vou.h
> @@ -33,6 +33,31 @@ enum vou_inf_data_sel {
> void vou_inf_enable(enum vou_inf_id id, struct drm_crtc *crtc);
> void vou_inf_disable(enum vou_inf_id id, struct drm_crtc *crtc);
>
> +enum vou_div_id {
> + VOU_DIV_VGA,
> + VOU_DIV_PIC,
> + VOU_DIV_TVENC,
> + VOU_DIV_HDMI_PNX,
> + VOU_DIV_HDMI,
> + VOU_DIV_INF,
> + VOU_DIV_LAYER,
> +};
> +
> +enum vou_div_val {
> + VOU_DIV_1 = 0,
> + VOU_DIV_2 = 1,
> + VOU_DIV_4 = 3,
> + VOU_DIV_8 = 7,
> +};
> +
> +struct vou_div_config {
> + enum vou_div_id id;
> + enum vou_div_val val;
> +};
> +
> +void zx_vou_config_dividers(struct drm_crtc *crtc,
> + struct vou_div_config *configs, int num);
> +
> int zx_vou_enable_vblank(struct drm_device *drm, unsigned int pipe);
> void zx_vou_disable_vblank(struct drm_device *drm, unsigned int pipe);
>
> diff --git a/drivers/gpu/drm/zte/zx_vou_regs.h b/drivers/gpu/drm/zte/zx_vou_regs.h
> index e6ed844e068a..552772137cf0 100644
> --- a/drivers/gpu/drm/zte/zx_vou_regs.h
> +++ b/drivers/gpu/drm/zte/zx_vou_regs.h
> @@ -176,11 +176,27 @@
> #define VOU_INF_DATA_SEL 0x08
> #define VOU_SOFT_RST 0x14
> #define VOU_CLK_SEL 0x18
> +#define VGA_AUX_DIV_SHIFT 29
> +#define VGA_MAIN_DIV_SHIFT 26
> +#define PIC_MAIN_DIV_SHIFT 23
> +#define PIC_AUX_DIV_SHIFT 20
> #define VOU_CLK_VL2_SEL BIT(8)
> #define VOU_CLK_VL1_SEL BIT(7)
> #define VOU_CLK_VL0_SEL BIT(6)
> #define VOU_CLK_GL1_SEL BIT(5)
> #define VOU_CLK_GL0_SEL BIT(4)
> +#define VOU_DIV_PARA 0x1c
> +#define DIV_PARA_UPDATE BIT(31)
> +#define TVENC_AUX_DIV_SHIFT 28
> +#define HDMI_AUX_PNX_DIV_SHIFT 25
> +#define HDMI_MAIN_PNX_DIV_SHIFT 22
> +#define HDMI_AUX_DIV_SHIFT 19
> +#define HDMI_MAIN_DIV_SHIFT 16
> +#define TVENC_MAIN_DIV_SHIFT 13
> +#define INF_AUX_DIV_SHIFT 9
> +#define INF_MAIN_DIV_SHIFT 6
> +#define LAYER_AUX_DIV_SHIFT 3
> +#define LAYER_MAIN_DIV_SHIFT 0
> #define VOU_CLK_REQEN 0x20
> #define VOU_CLK_EN 0x24
>
> --
> 1.9.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH v5 01/14] devicetree: bindings: add bindings for ahci-da850
From: Rob Herring @ 2017-01-23 15:49 UTC (permalink / raw)
To: Sekhar Nori
Cc: Bartosz Golaszewski, Kevin Hilman, Patrick Titiano,
Michael Turquette, Tejun Heo, Mark Rutland, Russell King,
David Lechner, linux-ide, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <5615fb6b-af26-c2fb-1f97-416548a9faaf@ti.com>
On Fri, Jan 20, 2017 at 07:02:08PM +0530, Sekhar Nori wrote:
> Hi Rob,
>
> On Friday 20 January 2017 04:51 PM, Bartosz Golaszewski wrote:
> > Add DT bindings for the TI DA850 AHCI SATA controller.
> >
> > Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>
> Could you ack this binding?
First I'm seeing it that I recall and v5? That either means the DT list
wasn't copied or new versions are being sent out faster than can be
reviewed. Sending new versions puts you at the back of the queue.
>
> Thanks,
> Sekhar
>
> > ---
> > Documentation/devicetree/bindings/ata/ahci-da850.txt | 15 +++++++++++++++
> > 1 file changed, 15 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/ata/ahci-da850.txt
> >
> > diff --git a/Documentation/devicetree/bindings/ata/ahci-da850.txt b/Documentation/devicetree/bindings/ata/ahci-da850.txt
> > new file mode 100644
> > index 0000000..268fe87
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/ata/ahci-da850.txt
> > @@ -0,0 +1,15 @@
> > +Device tree binding for the TI DA850 AHCI SATA Controller
> > +---------------------------------------------------------
> > +
> > +Required properties:
> > + - compatible: must be "ti,da850-ahci"
> > + - reg: physical base addresses and sizes of the controller's register areas
Need to state how many and what the regions are.
> > + - interrupts: interrupt specifier (refer to the interrupt binding)
> > +
> > +Example:
> > +
> > + sata: sata@218000 {
> > + compatible = "ti,da850-ahci";
> > + reg = <0x218000 0x2000>, <0x22c018 0x4>;
> > + interrupts = <67>;
> > + };
> >
>
^ permalink raw reply
* Re: [PATCH] usb: dwc3: add quirk to handle DWC_USB3_NUM == DWC_USB3_NUM_IN_EPS
From: Bryan O'Donoghue @ 2017-01-23 15:49 UTC (permalink / raw)
To: Rob Herring
Cc: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, mark.rutland-5wv7dgnIgG8,
balbi-DgEjT+Ai2ygdnm+yROfE0A, linux-usb-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170123153815.qxridbif7dg4k23z@rob-hp-laptop>
On 23/01/17 15:38, Rob Herring wrote:
>> - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
>> + - snps,num_in_eps_quirk: when set core will over-ride the num_in_eps value.
>> + - snps,num_in_eps_override: the value that will be used for num_in_eps when
>> + num_in_eps_quirk is true
>
> Why do you need 2 properties? Presence of the prop eanbles the override
> and the value of the prop provides the value.
We don't, sorry Rob I didn't CC you on the follow up patch, we've
decided to do everything in-code minus any DT bindings.
---
bod
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH v2 0/2] ARM: DTS: Fix broken GICv2 register maps
From: Marc Zyngier @ 2017-01-23 15:56 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: Thomas Gleixner, Jason Cooper, Rob Herring, Mark Rutland,
Tsahee Zidenberg, Antoine Tenart, Russell King,
Benoît Cousson, Tony Lindgren, Kukjin Kim,
Krzysztof Kozlowski, Javier Martinez Canillas, Shawn Guo,
Sascha Hauer, Fabio Estevam, Santosh Shilimkar, Matthias Brugger,
Simon Horman, Magnus Damm
For a GICv2 (which happens to be virtualization capable), the
architecture mandates the following regions:
GICD: 4kB
GICC: 8kB
GICH: 8kB
GICV: 8kB
Unfortunately, I made a mistake in one of the examples contained in
the DT binding document, and everyone duplicated that same mistake all
over the map.
This small series fixes the DT binding, and hopefully updates all the
offending DTs to be compliant with the architecture. Unless someone
suddenly wakes up and spots something wrong, I'll send a pull-request
to the arm-soc team by the end of tomorrow.
* From v1:
- Added a few GIC-400 compatibility strings where reported by people
having TRMs at hand
- Fixed the commit messages
- Added Acks and RBs
Marc Zyngier (2):
dt-bindings: arm,gic: Fix binding example for a virt-capable GIC
ARM: DTS: Fix register map for virt-capable GIC
Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt | 4 ++--
arch/arm/boot/dts/alpine.dtsi | 2 +-
arch/arm/boot/dts/axm55xx.dtsi | 2 +-
arch/arm/boot/dts/dra7.dtsi | 2 +-
arch/arm/boot/dts/ecx-2000.dts | 2 +-
arch/arm/boot/dts/exynos3250.dtsi | 2 +-
arch/arm/boot/dts/exynos5.dtsi | 4 ++--
arch/arm/boot/dts/exynos5260.dtsi | 2 +-
arch/arm/boot/dts/exynos5440.dtsi | 2 +-
arch/arm/boot/dts/imx6ul.dtsi | 4 ++--
arch/arm/boot/dts/keystone-k2g.dtsi | 4 ++--
arch/arm/boot/dts/keystone.dtsi | 4 ++--
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
arch/arm/boot/dts/mt2701.dtsi | 2 +-
arch/arm/boot/dts/mt6580.dtsi | 2 +-
arch/arm/boot/dts/mt6589.dtsi | 2 +-
arch/arm/boot/dts/mt7623.dtsi | 2 +-
arch/arm/boot/dts/mt8127.dtsi | 2 +-
arch/arm/boot/dts/mt8135.dtsi | 2 +-
arch/arm/boot/dts/omap5.dtsi | 2 +-
arch/arm/boot/dts/r8a73a4.dtsi | 2 +-
arch/arm/boot/dts/r8a7743.dtsi | 2 +-
arch/arm/boot/dts/r8a7745.dtsi | 2 +-
arch/arm/boot/dts/r8a7790.dtsi | 2 +-
arch/arm/boot/dts/r8a7791.dtsi | 2 +-
arch/arm/boot/dts/r8a7792.dtsi | 2 +-
arch/arm/boot/dts/r8a7793.dtsi | 2 +-
arch/arm/boot/dts/r8a7794.dtsi | 2 +-
arch/arm/boot/dts/rk1108.dtsi | 2 +-
arch/arm/boot/dts/rk3036.dtsi | 2 +-
arch/arm/boot/dts/rk322x.dtsi | 2 +-
arch/arm/boot/dts/rk3288.dtsi | 2 +-
arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
arch/arm/boot/dts/sun7i-a20.dtsi | 4 ++--
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
38 files changed, 45 insertions(+), 45 deletions(-)
--
2.1.4
^ permalink raw reply
* [PATCH v2 1/2] dt-bindings: arm,gic: Fix binding example for a virt-capable GIC
From: Marc Zyngier @ 2017-01-23 15:56 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: Thomas Gleixner, Jason Cooper, Rob Herring, Mark Rutland,
Tsahee Zidenberg, Antoine Tenart, Russell King,
Benoît Cousson, Tony Lindgren, Kukjin Kim,
Krzysztof Kozlowski, Javier Martinez Canillas, Shawn Guo,
Sascha Hauer, Fabio Estevam, Santosh Shilimkar, Matthias Brugger,
Simon Horman, Magnus Damm
In-Reply-To: <1485186974-13678-1-git-send-email-marc.zyngier@arm.com>
The joys of copy/paste: the example of a virtualization capable GIC
in the DT binding was wrong, and propagated to dozens of platforms.
By having a GICC region that is only 4kB (instead of 8kB), we
end-up not being able to access the GICC_DIR register which is on
the second page.
Oh well. Let's fix the source of the crap before tackling individual
offenders. While we're at it, also fix the compatibility string to
mention "arm,gic-400", which is the name of the actual implementation
of the GICv2 spec.
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
index 5393e2a..a3d51ed 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
@@ -107,11 +107,11 @@ Required properties:
Example:
interrupt-controller@2c001000 {
- compatible = "arm,cortex-a15-gic";
+ compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x2c001000 0x1000>,
- <0x2c002000 0x1000>,
+ <0x2c002000 0x2000>,
<0x2c004000 0x2000>,
<0x2c006000 0x2000>;
interrupts = <1 9 0xf04>;
--
2.1.4
^ permalink raw reply related
* [PATCH v2 2/2] ARM: DTS: Fix register map for virt-capable GIC
From: Marc Zyngier @ 2017-01-23 15:56 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Thomas Gleixner, Jason Cooper, Rob Herring, Mark Rutland,
Tsahee Zidenberg, Antoine Tenart, Russell King,
Benoît Cousson, Tony Lindgren, Kukjin Kim,
Krzysztof Kozlowski, Javier Martinez Canillas, Shawn Guo,
Sascha Hauer, Fabio Estevam, Santosh Shilimkar, Matthias Brugger,
Simon Horman, Magnus Damm
In-Reply-To: <1485186974-13678-1-git-send-email-marc.zyngier-5wv7dgnIgG8@public.gmane.org>
Since everybody copied my own mistake from the DT binding example,
let's address all the offenders in one swift go.
Most of them got the CPU interface size wrong (4kB, while it should
be 8kB), except for both keystone platforms which got the control
interface wrong (4kB instead of 8kB).
In a few cases where I knew for sure what implementation was used,
I've added the "arm,gic-400" compatible string. I'm 99% sure that
this is what everyone is using, but short of having the TRM for
all the other SoCs, I've left them alone.
Acked-by: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Acked-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
Acked-by: Santosh Shilimkar <ssantosh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Acked-by: Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Acked-by: Antoine Tenart <antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Acked-by: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
Acked-by: Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
Reviewed-by: Javier Martinez Canillas <javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
Signed-off-by: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
---
arch/arm/boot/dts/alpine.dtsi | 2 +-
arch/arm/boot/dts/axm55xx.dtsi | 2 +-
arch/arm/boot/dts/dra7.dtsi | 2 +-
arch/arm/boot/dts/ecx-2000.dts | 2 +-
arch/arm/boot/dts/exynos3250.dtsi | 2 +-
arch/arm/boot/dts/exynos5.dtsi | 4 ++--
arch/arm/boot/dts/exynos5260.dtsi | 2 +-
arch/arm/boot/dts/exynos5440.dtsi | 2 +-
arch/arm/boot/dts/imx6ul.dtsi | 4 ++--
arch/arm/boot/dts/keystone-k2g.dtsi | 4 ++--
arch/arm/boot/dts/keystone.dtsi | 4 ++--
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
arch/arm/boot/dts/mt2701.dtsi | 2 +-
arch/arm/boot/dts/mt6580.dtsi | 2 +-
arch/arm/boot/dts/mt6589.dtsi | 2 +-
arch/arm/boot/dts/mt7623.dtsi | 2 +-
arch/arm/boot/dts/mt8127.dtsi | 2 +-
arch/arm/boot/dts/mt8135.dtsi | 2 +-
arch/arm/boot/dts/omap5.dtsi | 2 +-
arch/arm/boot/dts/r8a73a4.dtsi | 2 +-
arch/arm/boot/dts/r8a7743.dtsi | 2 +-
arch/arm/boot/dts/r8a7745.dtsi | 2 +-
arch/arm/boot/dts/r8a7790.dtsi | 2 +-
arch/arm/boot/dts/r8a7791.dtsi | 2 +-
arch/arm/boot/dts/r8a7792.dtsi | 2 +-
arch/arm/boot/dts/r8a7793.dtsi | 2 +-
arch/arm/boot/dts/r8a7794.dtsi | 2 +-
arch/arm/boot/dts/rk1108.dtsi | 2 +-
arch/arm/boot/dts/rk3036.dtsi | 2 +-
arch/arm/boot/dts/rk322x.dtsi | 2 +-
arch/arm/boot/dts/rk3288.dtsi | 2 +-
arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
arch/arm/boot/dts/sun7i-a20.dtsi | 4 ++--
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
37 files changed, 43 insertions(+), 43 deletions(-)
diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
index db8752f..d0eefc3 100644
--- a/arch/arm/boot/dts/alpine.dtsi
+++ b/arch/arm/boot/dts/alpine.dtsi
@@ -93,7 +93,7 @@
interrupt-controller;
reg = <0x0 0xfb001000 0x0 0x1000>,
<0x0 0xfb002000 0x0 0x2000>,
- <0x0 0xfb004000 0x0 0x1000>,
+ <0x0 0xfb004000 0x0 0x2000>,
<0x0 0xfb006000 0x0 0x2000>;
interrupts =
<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi
index a9d6d59..47799f5 100644
--- a/arch/arm/boot/dts/axm55xx.dtsi
+++ b/arch/arm/boot/dts/axm55xx.dtsi
@@ -62,7 +62,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0x20 0x01001000 0 0x1000>,
- <0x20 0x01002000 0 0x1000>,
+ <0x20 0x01002000 0 0x2000>,
<0x20 0x01004000 0 0x2000>,
<0x20 0x01006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 1faf24a..a9ffa49 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -57,7 +57,7 @@
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x0 0x48211000 0x0 0x1000>,
- <0x0 0x48212000 0x0 0x1000>,
+ <0x0 0x48212000 0x0 0x2000>,
<0x0 0x48214000 0x0 0x2000>,
<0x0 0x48216000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
index 2ccbb57f..c15e7e0 100644
--- a/arch/arm/boot/dts/ecx-2000.dts
+++ b/arch/arm/boot/dts/ecx-2000.dts
@@ -99,7 +99,7 @@
interrupt-controller;
interrupts = <1 9 0xf04>;
reg = <0xfff11000 0x1000>,
- <0xfff12000 0x1000>,
+ <0xfff12000 0x2000>,
<0xfff14000 0x2000>,
<0xfff16000 0x2000>;
};
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index ba17ee1..9c28ef4 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -234,7 +234,7 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10481000 0x1000>,
- <0x10482000 0x1000>,
+ <0x10482000 0x2000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
interrupts = <GIC_PPI 9
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 7fd870e..b74c537 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -90,11 +90,11 @@
};
gic: interrupt-controller@10481000 {
- compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ compatible = "arm,gic-400", "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10481000 0x1000>,
- <0x10482000 0x1000>,
+ <0x10482000 0x2000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
interrupts = <GIC_PPI 9
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index 5818718..5e88c96 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -167,7 +167,7 @@
#size-cells = <0>;
interrupt-controller;
reg = <0x10481000 0x1000>,
- <0x10482000 0x1000>,
+ <0x10482000 0x2000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
interrupts = <GIC_PPI 9
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 2a2e570..77d35bb 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -40,7 +40,7 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x2E1000 0x1000>,
- <0x2E2000 0x1000>,
+ <0x2E2000 0x2000>,
<0x2E4000 0x2000>,
<0x2E6000 0x2000>;
interrupts = <GIC_PPI 9
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 39845a7..ac5371a 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -91,11 +91,11 @@
};
intc: interrupt-controller@00a01000 {
- compatible = "arm,cortex-a7-gic";
+ compatible = "arm,gic-400", "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
- <0x00a02000 0x1000>,
+ <0x00a02000 0x2000>,
<0x00a04000 0x2000>,
<0x00a06000 0x2000>;
};
diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
index 63c7cf0..1631f20 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -40,12 +40,12 @@
};
gic: interrupt-controller@02561000 {
- compatible = "arm,cortex-a15-gic";
+ compatible = "arm,gic-400", "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x02561000 0x0 0x1000>,
<0x0 0x02562000 0x0 0x2000>,
- <0x0 0x02564000 0x0 0x1000>,
+ <0x0 0x02564000 0x0 0x2000>,
<0x0 0x02566000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index 02708ba..e30c83f 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -30,12 +30,12 @@
};
gic: interrupt-controller {
- compatible = "arm,cortex-a15-gic";
+ compatible = "arm,gic-400", "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x02561000 0x0 0x1000>,
<0x0 0x02562000 0x0 0x2000>,
- <0x0 0x02564000 0x0 0x1000>,
+ <0x0 0x02564000 0x0 0x2000>,
<0x0 0x02566000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 282d854..45ea57f 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -110,11 +110,11 @@
ranges;
gic: interrupt-controller@1400000 {
- compatible = "arm,cortex-a7-gic";
+ compatible = "arm,gic-400", "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x1401000 0x0 0x1000>,
- <0x0 0x1402000 0x0 0x1000>,
+ <0x0 0x1402000 0x0 0x2000>,
<0x0 0x1404000 0x0 0x2000>,
<0x0 0x1406000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 7eab6f4..454d099 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -170,7 +170,7 @@
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10211000 0 0x1000>,
- <0 0x10212000 0 0x1000>,
+ <0 0x10212000 0 0x2000>,
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi
index 06fdf6c..a349dba 100644
--- a/arch/arm/boot/dts/mt6580.dtsi
+++ b/arch/arm/boot/dts/mt6580.dtsi
@@ -91,7 +91,7 @@
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0x10211000 0x1000>,
- <0x10212000 0x1000>,
+ <0x10212000 0x2000>,
<0x10214000 0x2000>,
<0x10216000 0x2000>;
};
diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
index 88b3cb1..0d6f60a 100644
--- a/arch/arm/boot/dts/mt6589.dtsi
+++ b/arch/arm/boot/dts/mt6589.dtsi
@@ -102,7 +102,7 @@
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0x10211000 0x1000>,
- <0x10212000 0x1000>,
+ <0x10212000 0x2000>,
<0x10214000 0x2000>,
<0x10216000 0x2000>;
};
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index fd2b614..19a54a3 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -104,7 +104,7 @@
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10211000 0 0x1000>,
- <0 0x10212000 0 0x1000>,
+ <0 0x10212000 0 0x2000>,
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
index 52086c8..916c095 100644
--- a/arch/arm/boot/dts/mt8127.dtsi
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -129,7 +129,7 @@
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10211000 0 0x1000>,
- <0 0x10212000 0 0x1000>,
+ <0 0x10212000 0 0x2000>,
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 1d7f92b..a97b4ee 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -221,7 +221,7 @@
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10211000 0 0x1000>,
- <0 0x10212000 0 0x1000>,
+ <0 0x10212000 0 0x2000>,
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 7cd92ba..71b4809 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -92,7 +92,7 @@
interrupt-controller;
#interrupt-cells = <3>;
reg = <0 0x48211000 0 0x1000>,
- <0 0x48212000 0 0x1000>,
+ <0 0x48212000 0 0x2000>,
<0 0x48214000 0 0x2000>,
<0 0x48216000 0 0x2000>;
interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 53183ff..14a66ca 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -465,7 +465,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 216cb1f..172a944 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -55,7 +55,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 0b2e2f3..7390ec0 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -55,7 +55,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 0c8900d..ac38764 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -183,7 +183,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 8721466..28039db 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -114,7 +114,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 6ced3c1..1ed5c88 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -88,7 +88,7 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 2fb527c..934c097 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -105,7 +105,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index fb576db..09f7823 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -71,7 +71,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi
index d770023..d6194bf 100644
--- a/arch/arm/boot/dts/rk1108.dtsi
+++ b/arch/arm/boot/dts/rk1108.dtsi
@@ -215,7 +215,7 @@
#address-cells = <0>;
reg = <0x32011000 0x1000>,
- <0x32012000 0x1000>,
+ <0x32012000 0x2000>,
<0x32014000 0x2000>,
<0x32016000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 4ed49a2..ff9b90b 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -189,7 +189,7 @@
#address-cells = <0>;
reg = <0x10139000 0x1000>,
- <0x1013a000 0x1000>,
+ <0x1013a000 0x2000>,
<0x1013c000 0x2000>,
<0x1013e000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 9d3aee5..9dff822 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -443,7 +443,7 @@
#address-cells = <0>;
reg = <0x32011000 0x1000>,
- <0x32012000 0x1000>,
+ <0x32012000 0x2000>,
<0x32014000 0x2000>,
<0x32016000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 4fad133..af46cba 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1110,7 +1110,7 @@
#address-cells = <0>;
reg = <0xffc01000 0x1000>,
- <0xffc02000 0x1000>,
+ <0xffc02000 0x2000>,
<0xffc04000 0x2000>,
<0xffc06000 0x2000>;
interrupts = <GIC_PPI 9 0xf04>;
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 2b26175..6ed505a 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -861,7 +861,7 @@
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
+ <0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index f7db067..3c24832 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -1686,9 +1686,9 @@
};
gic: interrupt-controller@01c81000 {
- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
+ <0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index e4991a7..49dfe86 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -489,7 +489,7 @@
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
+ <0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index d3473f8..04c3fdd 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -217,7 +217,7 @@
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
+ <0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 6c14a6f..292abd0 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -580,7 +580,7 @@
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
+ <0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 979ad1a..b7b5831 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -613,7 +613,7 @@
gic: interrupt-controller@01c41000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c41000 0x1000>,
- <0x01c42000 0x1000>,
+ <0x01c42000 0x2000>,
<0x01c44000 0x2000>,
<0x01c46000 0x2000>;
interrupt-controller;
--
2.1.4
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^ permalink raw reply related
* Re: [PATCH 2/3 v2] clk: ux500: Add device tree bindings for ABx500 clocks
From: Rob Herring @ 2017-01-23 16:01 UTC (permalink / raw)
To: Linus Walleij
Cc: Michael Turquette, Stephen Boyd, linux-clk, devicetree,
Ulf Hansson
In-Reply-To: <20170120132539.3013-1-linus.walleij@linaro.org>
On Fri, Jan 20, 2017 at 02:25:39PM +0100, Linus Walleij wrote:
> This adds device tree bindings for the ABx500 clocks on the
> ST-Ericsson platforms.
>
> Cc: devicetree@vger.kernel.org
> Cc: Ulf Hansson <ulf.hansson@linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> ChangeLog v1->v2:
> - Indicate that the abx500 clocks need to be in a device tree
> node under an ABx500 MFD device.
> - Rename the example node to clock-controller.
> ---
> .../devicetree/bindings/clock/stericsson,abx500.txt | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/stericsson,abx500.txt
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Hallo,
From: Anna Blanchard @ 2017-01-23 16:06 UTC (permalink / raw)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="_iso-2022-jp$ESC", Size: 1198 bytes --]
Hallo,
Es ist gut, euch heute zu schreiben, obwohl wir uns noch nicht kennen oder kennen gelernt haben. Mein Name ist Frau Anna Blanchard. Ich war verheiratet mit dem späten Mr. William Blanchard, der in der Elfenbeinküste als Investor für einen Zeitraum von 19 Jahren. Er verließ einen Betrag von $ 4.500.000,00 mit einem Finanzinstitut in Cote D'Ivoire. Vor kurzem hat mein Arzt mir gesagt, dass ich nicht mehr als acht Monate von jetzt wegen meiner Krebserkrankung leben.
Nachdem ich meinen Zustand erkannt hatte, entschied ich mich, diesen Fonds einer Organisation oder einer guten Person zu spenden, die sie für den Vorteil der weniger Privilegierten nutzen wird. Mit einem Teil davon zu etablieren Unternehmen, die Arbeitsplätze für die arbeitslose Bevölkerung zu schaffen ist auch eine gute Idee. Jede Verzögerung in Ihrer Antwort kann mir Raum geben, nach einer anderen guten Person für diesen gleichen Zweck zu suchen. Möge Gott dich segnen.
Dein,
Frau Anna Blanchard
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^ permalink raw reply
* Re: [PATCH 5/5] drm: zte: add tvenc driver support
From: Sean Paul @ 2017-01-23 16:10 UTC (permalink / raw)
To: Shawn Guo
Cc: Mark Rutland, devicetree, Daniel Vetter, Baoyou Xie, dri-devel,
Rob Herring, Jun Nie
In-Reply-To: <1484843100-16284-6-git-send-email-shawnguo@kernel.org>
On Fri, Jan 20, 2017 at 12:25:00AM +0800, Shawn Guo wrote:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> It adds the TV Encoder driver to support video output in PAL and NTSC
> format. The driver uses syscon/regmap interface to configure register
> bit sitting in SYSCTRL module for DAC power control.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> drivers/gpu/drm/zte/Makefile | 1 +
> drivers/gpu/drm/zte/zx_drm_drv.c | 1 +
> drivers/gpu/drm/zte/zx_drm_drv.h | 1 +
> drivers/gpu/drm/zte/zx_tvenc.c | 416 ++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/zte/zx_tvenc_regs.h | 31 +++
> drivers/gpu/drm/zte/zx_vou.c | 5 +
> 6 files changed, 455 insertions(+)
> create mode 100644 drivers/gpu/drm/zte/zx_tvenc.c
> create mode 100644 drivers/gpu/drm/zte/zx_tvenc_regs.h
>
> diff --git a/drivers/gpu/drm/zte/Makefile b/drivers/gpu/drm/zte/Makefile
> index 699180bfd57c..01352b56c418 100644
> --- a/drivers/gpu/drm/zte/Makefile
> +++ b/drivers/gpu/drm/zte/Makefile
> @@ -2,6 +2,7 @@ zxdrm-y := \
> zx_drm_drv.o \
> zx_hdmi.o \
> zx_plane.o \
> + zx_tvenc.o \
> zx_vou.o
>
> obj-$(CONFIG_DRM_ZTE) += zxdrm.o
> diff --git a/drivers/gpu/drm/zte/zx_drm_drv.c b/drivers/gpu/drm/zte/zx_drm_drv.c
> index 3e76f72c92ff..13081fed902d 100644
> --- a/drivers/gpu/drm/zte/zx_drm_drv.c
> +++ b/drivers/gpu/drm/zte/zx_drm_drv.c
> @@ -247,6 +247,7 @@ static int zx_drm_remove(struct platform_device *pdev)
> static struct platform_driver *drivers[] = {
> &zx_crtc_driver,
> &zx_hdmi_driver,
> + &zx_tvenc_driver,
> &zx_drm_platform_driver,
> };
>
> diff --git a/drivers/gpu/drm/zte/zx_drm_drv.h b/drivers/gpu/drm/zte/zx_drm_drv.h
> index e65cd18a6cba..5ca035b079c7 100644
> --- a/drivers/gpu/drm/zte/zx_drm_drv.h
> +++ b/drivers/gpu/drm/zte/zx_drm_drv.h
> @@ -13,6 +13,7 @@
>
> extern struct platform_driver zx_crtc_driver;
> extern struct platform_driver zx_hdmi_driver;
> +extern struct platform_driver zx_tvenc_driver;
>
> static inline u32 zx_readl(void __iomem *reg)
> {
> diff --git a/drivers/gpu/drm/zte/zx_tvenc.c b/drivers/gpu/drm/zte/zx_tvenc.c
> new file mode 100644
> index 000000000000..5a6cff1ff8a8
> --- /dev/null
> +++ b/drivers/gpu/drm/zte/zx_tvenc.c
> @@ -0,0 +1,416 @@
> +/*
> + * Copyright 2017 Linaro Ltd.
> + * Copyright 2017 ZTE Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/regmap.h>
> +
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drmP.h>
> +
> +#include "zx_drm_drv.h"
> +#include "zx_tvenc_regs.h"
> +#include "zx_vou.h"
> +
> +struct zx_tvenc_pwrctrl {
> + struct regmap *regmap;
> + u32 reg;
> + u32 mask;
> +};
> +
> +struct zx_tvenc {
> + struct drm_connector connector;
> + struct drm_encoder encoder;
> + struct device *dev;
> + void __iomem *mmio;
> + const struct vou_inf *inf;
> + struct zx_tvenc_pwrctrl pwrctrl;
> +};
> +
> +#define to_zx_tvenc(x) container_of(x, struct zx_tvenc, x)
> +
> +struct zx_tvenc_mode {
> + char *name;
> + u32 hdisplay;
> + u32 vdisplay;
> + u32 hfp;
> + u32 hbp;
> + u32 hsw;
> + u32 vfp;
> + u32 vbp;
> + u32 vsw;
Let's not duplicate these fields and do conversions. I think you should embed a
drm_display_mode struct here instead and just return it in get_modes. Check out
panel_desc in drivers/gpu/drm/panel/panel-simple.c, I think you can do something
similar here.
> + u32 video_info;
> + u32 video_res;
> + u32 field1_param;
> + u32 field2_param;
> + u32 burst_line_odd1;
> + u32 burst_line_even1;
> + u32 burst_line_odd2;
> + u32 burst_line_even2;
> + u32 line_timing_param;
> + u32 weight_value;
> + u32 blank_black_level;
> + u32 burst_level;
> + u32 control_param;
> + u32 sub_carrier_phase1;
> + u32 phase_line_incr_cvbs;
> +};
> +
> +static const struct zx_tvenc_mode tvenc_modes[] = {
> + {
> + .name = "PAL",
> + .hdisplay = 720,
> + .vdisplay = 576,
> + .hfp = 12,
> + .hbp = 130,
> + .hsw = 2,
> + .vfp = 2,
> + .vbp = 20,
> + .vsw = 2,
> + .video_info = 0x00040040,
> + .video_res = 0x05a9c760,
> + .field1_param = 0x0004d416,
> + .field2_param = 0x0009b94f,
> + .burst_line_odd1 = 0x0004d406,
> + .burst_line_even1 = 0x0009b53e,
> + .burst_line_odd2 = 0x0004d805,
> + .burst_line_even2 = 0x0009b93f,
> + .line_timing_param = 0x06a96fdf,
> + .weight_value = 0x00c188a0,
> + .blank_black_level = 0x0000fcfc,
> + .burst_level = 0x00001595,
> + .control_param = 0x00000001,
> + .sub_carrier_phase1 = 0x1504c566,
> + .phase_line_incr_cvbs = 0xc068db8c,
I don't suppose you can derive these magic values from the mode?
> + }, {
> + .name = "NTSC",
> + .hdisplay = 720,
> + .vdisplay = 480,
> + .hfp = 16,
> + .hbp = 120,
> + .hsw = 2,
> + .vfp = 3,
> + .vbp = 17,
> + .vsw = 2,
> + .video_info = 0x00040080,
> + .video_res = 0x05a8375a,
> + .field1_param = 0x00041817,
> + .field2_param = 0x0008351e,
> + .burst_line_odd1 = 0x00041006,
> + .burst_line_even1 = 0x0008290d,
> + .burst_line_odd2 = 0x00000000,
> + .burst_line_even2 = 0x00000000,
> + .line_timing_param = 0x06a8ef9e,
> + .weight_value = 0x00b68197,
> + .blank_black_level = 0x0000f0f0,
> + .burst_level = 0x0000009c,
> + .control_param = 0x00000001,
> + .sub_carrier_phase1 = 0x10f83e10,
> + .phase_line_incr_cvbs = 0x80000000,
> + },
> +};
> +
> +static const struct zx_tvenc_mode *
> +zx_tvenc_find_zmode(struct drm_display_mode *mode)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(tvenc_modes); i++) {
> + const struct zx_tvenc_mode *zmode = &tvenc_modes[i];
> +
> + if (!strcmp(mode->name, zmode->name))
drm_mode_equal() is your friend
> + return zmode;
> + }
> +
> + return NULL;
> +}
> +
> +static void zx_tvenc_encoder_mode_set(struct drm_encoder *encoder,
> + struct drm_display_mode *mode,
> + struct drm_display_mode *adj_mode)
> +{
> + struct zx_tvenc *tvenc = to_zx_tvenc(encoder);
> + const struct zx_tvenc_mode *zmode;
> + struct vou_div_config configs[] = {
> + { VOU_DIV_INF, VOU_DIV_4 },
> + { VOU_DIV_TVENC, VOU_DIV_1 },
> + { VOU_DIV_LAYER, VOU_DIV_2 },
> + };
> +
> + zx_vou_config_dividers(encoder->crtc, configs, ARRAY_SIZE(configs));
> +
> + zmode = zx_tvenc_find_zmode(mode);
> + if (!zmode) {
> + DRM_DEV_ERROR(tvenc->dev, "failed to find zmode\n");
> + return;
> + }
> +
> + zx_writel(tvenc->mmio + VENC_VIDEO_INFO, zmode->video_info);
> + zx_writel(tvenc->mmio + VENC_VIDEO_RES, zmode->video_res);
> + zx_writel(tvenc->mmio + VENC_FIELD1_PARAM, zmode->field1_param);
> + zx_writel(tvenc->mmio + VENC_FIELD2_PARAM, zmode->field2_param);
> + zx_writel(tvenc->mmio + VENC_LINE_O_1, zmode->burst_line_odd1);
> + zx_writel(tvenc->mmio + VENC_LINE_E_1, zmode->burst_line_even1);
> + zx_writel(tvenc->mmio + VENC_LINE_O_2, zmode->burst_line_odd2);
> + zx_writel(tvenc->mmio + VENC_LINE_E_2, zmode->burst_line_even2);
> + zx_writel(tvenc->mmio + VENC_LINE_TIMING_PARAM,
> + zmode->line_timing_param);
> + zx_writel(tvenc->mmio + VENC_WEIGHT_VALUE, zmode->weight_value);
> + zx_writel(tvenc->mmio + VENC_BLANK_BLACK_LEVEL,
> + zmode->blank_black_level);
> + zx_writel(tvenc->mmio + VENC_BURST_LEVEL, zmode->burst_level);
> + zx_writel(tvenc->mmio + VENC_CONTROL_PARAM, zmode->control_param);
> + zx_writel(tvenc->mmio + VENC_SUB_CARRIER_PHASE1,
> + zmode->sub_carrier_phase1);
> + zx_writel(tvenc->mmio + VENC_PHASE_LINE_INCR_CVBS,
> + zmode->phase_line_incr_cvbs);
> +}
> +
> +static void zx_tvenc_encoder_enable(struct drm_encoder *encoder)
> +{
> + struct zx_tvenc *tvenc = to_zx_tvenc(encoder);
> + struct zx_tvenc_pwrctrl *pwrctrl = &tvenc->pwrctrl;
> +
> + /* Set bit to power up TVENC DAC */
> + regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask,
> + pwrctrl->mask);
> +
> + vou_inf_enable(VOU_TV_ENC, encoder->crtc);
> +
> + zx_writel(tvenc->mmio + VENC_ENABLE, 1);
> +}
> +
> +static void zx_tvenc_encoder_disable(struct drm_encoder *encoder)
> +{
> + struct zx_tvenc *tvenc = to_zx_tvenc(encoder);
> + struct zx_tvenc_pwrctrl *pwrctrl = &tvenc->pwrctrl;
> +
> + zx_writel(tvenc->mmio + VENC_ENABLE, 0);
> +
> + vou_inf_disable(VOU_TV_ENC, encoder->crtc);
> +
> + /* Clear bit to power down TVENC DAC */
> + regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask, 0);
> +}
> +
> +static const struct drm_encoder_helper_funcs zx_tvenc_encoder_helper_funcs = {
> + .enable = zx_tvenc_encoder_enable,
> + .disable = zx_tvenc_encoder_disable,
> + .mode_set = zx_tvenc_encoder_mode_set,
> +};
> +
> +static const struct drm_encoder_funcs zx_tvenc_encoder_funcs = {
> + .destroy = drm_encoder_cleanup,
> +};
> +
> +static void zx_tvenc_mode_to_drm_mode(const struct zx_tvenc_mode *zmode,
> + struct drm_display_mode *mode)
> +{
> + strcpy(mode->name, zmode->name);
Consider drm_mode_set_name() instead of rolling your own names
> +
> + mode->type = DRM_MODE_TYPE_DRIVER;
> + mode->flags = DRM_MODE_FLAG_INTERLACE;
> + mode->flags |= DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC;
> +
> + /*
> + * The CRM cannot directly provide such a low rate, and we have to
> + * ask a multiflied rate from CRM and use the divider in VOU to get
s/multified/multiplied/
> + * the disired one.
s/disired/desired/
> + */
> + mode->clock = 13500 * 4;
I don't think this should be hardcoded at runtime, stick it in the modes above
> +
> + mode->hdisplay = zmode->hdisplay;
> + mode->hsync_start = mode->hdisplay + zmode->hfp;
> + mode->hsync_end = mode->hsync_start + zmode->hsw;
> + mode->htotal = mode->hsync_end + zmode->hbp;
> +
> + mode->vdisplay = zmode->vdisplay;
> + mode->vsync_start = mode->vdisplay + zmode->vfp;
> + mode->vsync_end = mode->vsync_start + zmode->vsw;
> + mode->vtotal = mode->vsync_end + zmode->vbp;
> +}
> +
> +static int zx_tvenc_connector_get_modes(struct drm_connector *connector)
> +{
> + struct zx_tvenc *tvenc = to_zx_tvenc(connector);
> + struct device *dev = tvenc->dev;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(tvenc_modes); i++) {
> + struct drm_display_mode *mode;
> + const struct zx_tvenc_mode *zmode = &tvenc_modes[i];
> +
> + mode = drm_mode_create(connector->dev);
> + if (!mode) {
> + DRM_DEV_ERROR(dev, "failed to create drm mode\n");
> + return 0;
> + }
> +
> + zx_tvenc_mode_to_drm_mode(zmode, mode);
> + drm_mode_probed_add(connector, mode);
> + }
> +
> + return i;
> +}
> +
> +static enum drm_mode_status
> +zx_tvenc_connector_mode_valid(struct drm_connector *connector,
> + struct drm_display_mode *mode)
> +{
You probably want to do a sanity check to ensure the mode is in your list above
(and not user-submitted).
> + return MODE_OK;
> +}
> +
> +static struct drm_connector_helper_funcs zx_tvenc_connector_helper_funcs = {
> + .get_modes = zx_tvenc_connector_get_modes,
> + .mode_valid = zx_tvenc_connector_mode_valid,
> +};
> +
> +static const struct drm_connector_funcs zx_tvenc_connector_funcs = {
> + .dpms = drm_atomic_helper_connector_dpms,
> + .fill_modes = drm_helper_probe_single_connector_modes,
> + .destroy = drm_connector_cleanup,
> + .reset = drm_atomic_helper_connector_reset,
> + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> +};
> +
> +static int zx_tvenc_register(struct drm_device *drm, struct zx_tvenc *tvenc)
> +{
> + struct drm_encoder *encoder = &tvenc->encoder;
> + struct drm_connector *connector = &tvenc->connector;
> +
> + /*
> + * The tvenc is designed to use aux channel, as there is a deflicker
> + * block for the channel.
> + */
> + encoder->possible_crtcs = BIT(1);
> +
> + drm_encoder_init(drm, encoder, &zx_tvenc_encoder_funcs,
> + DRM_MODE_ENCODER_TVDAC, NULL);
> + drm_encoder_helper_add(encoder, &zx_tvenc_encoder_helper_funcs);
> +
> + connector->interlace_allowed = true;
> +
> + drm_connector_init(drm, connector, &zx_tvenc_connector_funcs,
> + DRM_MODE_CONNECTOR_Composite);
> + drm_connector_helper_add(connector, &zx_tvenc_connector_helper_funcs);
> +
> + drm_mode_connector_attach_encoder(connector, encoder);
> +
> + return 0;
> +}
> +
> +static int zx_tvenc_pwrctrl_init(struct zx_tvenc *tvenc)
> +{
> + struct zx_tvenc_pwrctrl *pwrctrl = &tvenc->pwrctrl;
> + struct device *dev = tvenc->dev;
> + struct of_phandle_args out_args;
> + struct regmap *regmap;
> + int ret;
> +
> + ret = of_parse_phandle_with_fixed_args(dev->of_node,
> + "zte,tvenc-power-control", 2, 0, &out_args);
> + if (ret)
> + return ret;
> +
> + regmap = syscon_node_to_regmap(out_args.np);
> + if (IS_ERR(regmap)) {
> + ret = PTR_ERR(regmap);
> + goto out;
> + }
> +
> + pwrctrl->regmap = regmap;
> + pwrctrl->reg = out_args.args[0];
> + pwrctrl->mask = out_args.args[1];
> +
> +out:
> + of_node_put(out_args.np);
> + return ret;
> +}
> +
> +static int zx_tvenc_bind(struct device *dev, struct device *master, void *data)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct drm_device *drm = data;
> + struct resource *res;
> + struct zx_tvenc *tvenc;
> + int ret;
> +
> + tvenc = devm_kzalloc(dev, sizeof(*tvenc), GFP_KERNEL);
> + if (!tvenc)
> + return -ENOMEM;
> +
> + tvenc->dev = dev;
> + dev_set_drvdata(dev, tvenc);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + tvenc->mmio = devm_ioremap_resource(dev, res);
> + if (IS_ERR(tvenc->mmio)) {
> + ret = PTR_ERR(tvenc->mmio);
> + DRM_DEV_ERROR(dev, "failed to remap tvenc region: %d\n", ret);
> + return ret;
> + }
> +
> + ret = zx_tvenc_pwrctrl_init(tvenc);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "failed to init power control: %d\n", ret);
> + return ret;
> + }
> +
> + ret = zx_tvenc_register(drm, tvenc);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "failed to register tvenc: %d\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static void zx_tvenc_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct zx_tvenc *tvenc = dev_get_drvdata(dev);
> +
> + tvenc->connector.funcs->destroy(&tvenc->connector);
> + tvenc->encoder.funcs->destroy(&tvenc->encoder);
I think drm_mode_config_cleanup() should take care of calling these
> +}
> +
> +static const struct component_ops zx_tvenc_component_ops = {
> + .bind = zx_tvenc_bind,
> + .unbind = zx_tvenc_unbind,
> +};
> +
> +static int zx_tvenc_probe(struct platform_device *pdev)
> +{
> + return component_add(&pdev->dev, &zx_tvenc_component_ops);
> +}
> +
> +static int zx_tvenc_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &zx_tvenc_component_ops);
> + return 0;
> +}
> +
> +static const struct of_device_id zx_tvenc_of_match[] = {
> + { .compatible = "zte,zx296718-tvenc", },
> + { /* end */ },
> +};
> +MODULE_DEVICE_TABLE(of, zx_tvenc_of_match);
> +
> +struct platform_driver zx_tvenc_driver = {
> + .probe = zx_tvenc_probe,
> + .remove = zx_tvenc_remove,
> + .driver = {
> + .name = "zx-tvenc",
> + .of_match_table = zx_tvenc_of_match,
> + },
> +};
> diff --git a/drivers/gpu/drm/zte/zx_tvenc_regs.h b/drivers/gpu/drm/zte/zx_tvenc_regs.h
> new file mode 100644
> index 000000000000..bd91f5dcc1f3
> --- /dev/null
> +++ b/drivers/gpu/drm/zte/zx_tvenc_regs.h
> @@ -0,0 +1,31 @@
> +/*
> + * Copyright 2017 Linaro Ltd.
> + * Copyright 2017 ZTE Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#ifndef __ZX_TVENC_REGS_H__
> +#define __ZX_TVENC_REGS_H__
> +
> +#define VENC_VIDEO_INFO 0x04
> +#define VENC_VIDEO_RES 0x08
> +#define VENC_FIELD1_PARAM 0x10
> +#define VENC_FIELD2_PARAM 0x14
> +#define VENC_LINE_O_1 0x18
> +#define VENC_LINE_E_1 0x1c
> +#define VENC_LINE_O_2 0x20
> +#define VENC_LINE_E_2 0x24
> +#define VENC_LINE_TIMING_PARAM 0x28
> +#define VENC_WEIGHT_VALUE 0x2c
> +#define VENC_BLANK_BLACK_LEVEL 0x30
> +#define VENC_BURST_LEVEL 0x34
> +#define VENC_CONTROL_PARAM 0x3c
> +#define VENC_SUB_CARRIER_PHASE1 0x40
> +#define VENC_PHASE_LINE_INCR_CVBS 0x48
> +#define VENC_ENABLE 0xa8
> +
> +#endif /* __ZX_TVENC_REGS_H__ */
> diff --git a/drivers/gpu/drm/zte/zx_vou.c b/drivers/gpu/drm/zte/zx_vou.c
> index 98f0f51f9748..61d4ff709d83 100644
> --- a/drivers/gpu/drm/zte/zx_vou.c
> +++ b/drivers/gpu/drm/zte/zx_vou.c
> @@ -192,6 +192,11 @@ struct vou_inf {
> .clocks_en_bits = BIT(24) | BIT(18) | BIT(6),
> .clocks_sel_bits = BIT(13) | BIT(2),
> },
> + [VOU_TV_ENC] = {
> + .data_sel = VOU_YUV444,
> + .clocks_en_bits = BIT(15),
> + .clocks_sel_bits = BIT(11) | BIT(0),
> + },
> };
>
> static inline struct zx_vou_hw *crtc_to_vou(struct drm_crtc *crtc)
> --
> 1.9.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH v4 2/9] ARM: dts: rockchip: update compatible property for rk3228 timer
From: Heiko Stübner @ 2017-01-23 16:12 UTC (permalink / raw)
To: Daniel Lezcano
Cc: Alexander Kochetkov, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Thomas Gleixner,
Mark Rutland, Rob Herring, Russell King, Caesar Wang, Huang Tao
In-Reply-To: <20170123154046.GF2166@mai>
Am Montag, 23. Januar 2017, 16:40:46 CET schrieb Daniel Lezcano:
> On Tue, Nov 29, 2016 at 07:14:45PM +0300, Alexander Kochetkov wrote:
> > Property set to '"rockchip,rk3228-timer", "rockchip,rk3288-timer"'
> > to match devicetree bindings.
> >
> > Signed-off-by: Alexander Kochetkov <al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > ---
> >
> > arch/arm/boot/dts/rk3228-evb.dts | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/rk3228-evb.dts
> > b/arch/arm/boot/dts/rk3228-evb.dts index 904668e..38eab87 100644
> > --- a/arch/arm/boot/dts/rk3228-evb.dts
> > +++ b/arch/arm/boot/dts/rk3228-evb.dts
> > @@ -70,3 +70,7 @@
> >
> > &uart2 {
> >
> > status = "okay";
> >
> > };
> >
> > +
> > +&timer {
> > + compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
> > +};
>
> I'm not sure this is correct, to which timer &timer will refer ?
>
> timer {
> compatible = "arm,armv7-timer";
> ...
> }
>
> timer: timer@110c0000 {
> compatible = "rockchip,rk3288-timer";
> ...
> }
>
> Why not change the compatible string in the timer definition in rk322x.dtsi
> ?
>
> Same comment for the other patches doing these changes.
I think Alexander didn't know which timer name to use.
Both the rk3228 and rk3229 are so similar that so far no-one has seen any
difference and thus they really share the whole rk322x.dtsi file.
On the other hand compatibles are supposed to be explicit, so a rk322x-timer
compatible is not allowed.
But as the socs are soooo similar, I'd suggest just using the rk3228-timer
compatible in the rk322x.dtsi and not changing individual board files.
Similar to what Daniel suggested.
Heiko
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^ permalink raw reply
* Re: [PATCH v4 2/9] ARM: dts: rockchip: update compatible property for rk3228 timer
From: Alexander Kochetkov @ 2017-01-23 16:13 UTC (permalink / raw)
To: Daniel Lezcano
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Thomas Gleixner,
Heiko Stuebner, Mark Rutland, Rob Herring, Russell King,
Caesar Wang, Huang Tao
In-Reply-To: <20170123154046.GF2166@mai>
Hello Daniel!
:
> +
> +&timer {
> + compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
> +};
> 23 янв. 2017 г., в 18:40, Daniel Lezcano <daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> написал(а):
>
> I'm not sure this is correct, to which timer &timer will refer ?
>
> timer {
> compatible = "arm,armv7-timer";
> ...
> }
>
> timer: timer@110c0000 {
> compatible = "rockchip,rk3288-timer";
> ...
> }
The block '&timer { …}' change compatible string for 'timer: timer@110c0000’ timer'. It refers to it using ’timer:’ label.
'arm,armv7-timer’ has ’timer’ node name without label and cannot be addressed in underline dts files.
> Why not change the compatible string in the timer definition in rk322x.dtsi ?
Initially my patch series was for rk3188 only. I declared rk3188 timer using rk3228 compatible string[1].
Heiko reviewed the series and suggest[2] to use another ‘compatible=‘ binding for rk3188. And
suggest[3] to update rockchip,rk-timer.txt bindings, like mmc/rockchip-dw-mshc.txt does.
So I updated rockchip,rk-timer.txt. rk322x family has has two parts rk3228 and rk3229. So I replaced
rk322x to rk3228 and rk3229 and updated dts file to match bindings.
[1] http://lists.infradead.org/pipermail/linux-rockchip/2016-November/013152.html
[2] http://lists.infradead.org/pipermail/linux-rockchip/2016-November/013174.html
[3] http://lists.infradead.org/pipermail/linux-rockchip/2016-November/013174.html
> Same comment for the other patches doing these changes.
>
> -- Daniel
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^ permalink raw reply
* Re: [PATCH v4 5/9] ARM: dts: rockchip: disable arm-global-timer for rk3188
From: Heiko Stübner @ 2017-01-23 16:14 UTC (permalink / raw)
To: Alexander Kochetkov
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-rockchip,
Thomas Gleixner, Mark Rutland, Rob Herring, Russell King,
Caesar Wang, Huang Tao, Daniel Lezcano
In-Reply-To: <1480436092-10728-6-git-send-email-al.kochet@gmail.com>
Am Dienstag, 29. November 2016, 19:14:48 CET schrieb Alexander Kochetkov:
> arm-global-timer can provide clockevents, clocksource and shed_clock. But
> on rk3188 platform it provide only clocksource and shed_clock. clockevents
> from arm-global-timer is not used by kernel because there is another
> clockevent provider with higher rating (smp-twd).
>
> My commit from the series implement clocksource and shed_clock using
> rockchip_timer. But sched clock from rk_timer is not selected by kernel
> due to lower frequency than arm-global-timer, and clocksource from
> rk_timer is not selected by kernel due to lower rating than
> arm-global-timer. And I don't want to increase clocksource rating
> because ratings greater 300 used for high frequency clocksources.
>
> clocksource and shed_clock is quite unstable, because their rate depends
> on cpu frequency. So disable arm-global-timer and use clocksource and
> sched_clock from rockchip_timer.
That commit message is hard to understand in its entirety, but this last
paragraph is essentially enough to describe the problem. So maybe you could
shorten that somehow.
Heiko
> Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
> ---
> arch/arm/boot/dts/rk3188.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
> index 0dc52fe..44da3d42 100644
> --- a/arch/arm/boot/dts/rk3188.dtsi
> +++ b/arch/arm/boot/dts/rk3188.dtsi
> @@ -546,6 +546,7 @@
>
> &global_timer {
> interrupts = <GIC_PPI 11 0xf04>;
> + status = "disabled";
> };
>
> &local_timer {
^ permalink raw reply
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