* Re: [RFC 3/8] cpufreq: imx6q: Set max suspend_freq to avoid changes during suspend
From: Rafael J. Wysocki @ 2017-03-28 20:50 UTC (permalink / raw)
To: Leonard Crestez
Cc: Mark Rutland, devicetree, Anson Huang, Irina Tirdea, Viresh Kumar,
linux-pm, Liam Girdwood, Rob Herring, linux-kernel, Mark Brown,
Octavian Purdila, Sascha Hauer, Fabio Estevam, Robin Gong,
Shawn Guo, linux-arm-kernel
In-Reply-To: <1490731431.15830.9.camel@nxp.com>
On Tuesday, March 28, 2017 11:03:51 PM Leonard Crestez wrote:
> On Thu, 2017-03-23 at 10:04 +0530, Viresh Kumar wrote:
> > On 22-03-17, 18:53, Leonard Crestez wrote:
> > > If the cpufreq driver tries to modify voltage/freq during suspend/resume
> > > it might need to control an external PMIC via I2C or SPI but those
> > > devices might be already suspended.
> > >
> > > To avoid this scenario we just increase cpufreq to highest setpoint
> > > before suspend. This issue can easily be triggered by ldo-bypass but in
> > > theory any regulator set_voltage call can end up having to modify
> > > external supply voltages.
> > >
> > > Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
> > > ---
> > > drivers/cpufreq/imx6q-cpufreq.c | 2 ++
> > > 1 file changed, 2 insertions(+)
> >
> > Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
>
> The first couple of patches are obvious fixes despite being marked as
> RFC. It would be great if you could apply them to your tree separately
Why?
> from the rest of the series but I'm not sure what the process is here.
Well, you have to talk to me.
Thanks,
Rafael
^ permalink raw reply
* Re: [PATCH v6 2/5] irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed
From: Benjamin Herrenschmidt @ 2017-03-28 20:50 UTC (permalink / raw)
To: Marc Zyngier, Brendan Higgins, wsa-z923LK4zBo2bacvFa/9K2g,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
tglx-hfZtesqFncYOwBW4kG4KsQ, jason-NLaQJdtUoK4Be96aLqz0jA,
joel-U3u1mxZcP9KHXe+LvDLADg, vz-ChpfBGZJDbMAvxtiuMwx3w,
mouse-Pma6HLj0uuo, clg-Bxea+6Xhats
Cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
openbmc-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <91936f1a-0a0d-4091-b981-976503a6f7cd-5wv7dgnIgG8@public.gmane.org>
On Tue, 2017-03-28 at 10:40 +0100, Marc Zyngier wrote:
> On 28/03/17 10:12, Benjamin Herrenschmidt wrote:
> > On Tue, 2017-03-28 at 09:32 +0100, Marc Zyngier wrote:
> > > I'm a bit concerned by this. It means that you can't even mask an
> > > interrupt. Is that really what you intend to do? Or all that the HW can
> > > do? If you cannot mask an interrupt, you're at the mercy of a screaming
> > > device...
> >
> > This is not really an interrupt controller. It's a "summary" register
> > that reflects the state of the 14 i2c controller interrupts.
> >
> > This approach does have the advantage of providing separate counters in
> > /proc/interrupts which is rather nice, but it does have overhead. On
> > those shittly little ARMv9 400Mhz cores it can be significant.
>
> <pedantic>
> s/ARMv9/ARM9/, as we're still on variations of the ARMv8 architecture ;-)
> </pedantic>
It was a typo, I meant ARM9/ARMv5 :-)
The 2 SOC families we are talking about (Aspeed 24xx and 25xx) are
based on a ARM926EJ at 400Mhz and an ARM1176JZFS at 800Mhz
respectively, so cycles do count :-)
> A 400MHz ARM9 (which is either ARMv4 or ARMv5) is not too bad (hey, we
> still have a couple of Versatile-ABs here...). Caches are pretty small
> though.
16K/16K, no L2 :)
> > I would personally have some kind of trick to register a single
> > interrupt handler that calls directly the handlers of the respective
> > i2c busses via a simple indirection for speed, maybe adding my custom
> > sysfs or debugfs statistics. But that's just me trying to suck the last
> > cycle out of the bloody thing ;-)
>
> I'd hope the irqdomain itself to be pretty light (the revmap should help
> here), but of course you're going to do more work. Counters also come at
> a cost. It'd be interesting to see if Brendan has any overhead data
> about this.
Thankfully, the HW supports buffered sends/receive or even DMA. The
current patch doesn't yet support these but they would be a good way to
alleviate the cost of the interrupts if it becomes a problem.
Cheers,
Ben.
> Cheers,
>
> M.
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^ permalink raw reply
* Re: [PATCH] ARM: dts: rockchip: Enable sata support on rock2 square
From: Heiko Stuebner @ 2017-03-28 20:22 UTC (permalink / raw)
To: Sjoerd Simons
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring,
Mark Rutland, Russell King,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170317135118.17333-1-sjoerd.simons-ZGY8ohtN/8pPYcu2f3hruQ@public.gmane.org>
Am Freitag, 17. März 2017, 14:51:17 CEST schrieb Sjoerd Simons:
> The Rock 2 square board has a USB -> SATA converter hooked up to its usb
> host1 connection. Enable the usb controller and always turn on the power
> on the 5V sata power connector (controlled by gpio).
>
> Signed-off-by: Sjoerd Simons <sjoerd.simons-ZGY8ohtN/8pPYcu2f3hruQ@public.gmane.org>
applied for 4.12
Thanks
Heiko
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^ permalink raw reply
* Re: [RFC PATCH 1/2] dt-bindings: mtd: Add Cavium SOCs NAND bindings
From: Boris Brezillon @ 2017-03-28 20:20 UTC (permalink / raw)
To: Jan Glauber
Cc: Richard Weinberger, David Woodhouse, Brian Norris, Marek Vasut,
Cyrille Pitchen, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
Rob Herring, linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170327160524.29019-2-jglauber-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
Hi Jan,
On Mon, 27 Mar 2017 18:05:23 +0200
Jan Glauber <jglauber-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> wrote:
> Add device tree binding description for Cavium SOC nand flash controller.
>
> CC: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> CC: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> CC: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>
> Signed-off-by: Jan Glauber <jglauber-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
> ---
> .../devicetree/bindings/mtd/cavium_nand.txt | 32 ++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/cavium_nand.txt
>
> diff --git a/Documentation/devicetree/bindings/mtd/cavium_nand.txt b/Documentation/devicetree/bindings/mtd/cavium_nand.txt
> new file mode 100644
> index 0000000..4698d1f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/cavium_nand.txt
> @@ -0,0 +1,32 @@
> +* Cavium NAND controller
> +
> +Required properties:
> +
> +- compatible: should be "cavium,cn8xxx-nand"
> +- reg: PCI devfn
> +- clocks: must contain system clock
> +- #address-cells: <1>
> +- #size-cells: <0>
> +
> +The nand flash controller may contain up to 8 subnodes representing
> +NAND flash chips. Their properties are as follows.
> +
> +Required properties:
> +- compatible: should be "cavium,nandcs"
Why do you need a compatible here? All sub-nodes should be representing
NAND devices connected to the NAND controller. If you need an extra
subnode to represent something that is not a NAND device, then it should
not have a reg property, so testing if reg is present to detect if the
subnode is reprensenting a NAND device should be enough.
Am I missing something?
> +- reg: a single integer representing the chip-select number
> +- nand-ecc-mode: see nand.txt
> +
> +Example:
> +
> +nfc: nand@b,0 {
^ nand-controller@xxx
> + compatible = "cavium,cn8xxx-nand";
> + reg = <0x5800 0 0 0 0>;
> + clocks = <&sclk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + nand@1 {
> + compatible = "cavium,nandcs";
> + reg = <1>;
> + nand-ecc-mode = "on-die";
> +};
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^ permalink raw reply
* Re: [RESEND PATCH v2 00/53] mtd: nand: denali: 2nd round of Denali NAND IP patch bomb
From: Boris Brezillon @ 2017-03-28 20:14 UTC (permalink / raw)
To: Masahiro Yamada
Cc: linux-mtd, Laurent Monat, thorsten.christiansson, Enrico Jorns,
Artem Bityutskiy, Dinh Nguyen, Marek Vasut, Graham Moore,
David Woodhouse, Masami Hiramatsu, Chuanxiao Dong, Jassi Brar,
devicetree, Linux Kernel Mailing List, Brian Norris,
Richard Weinberger, Cyrille Pitchen, Rob Herring,
Mark Rutland <mark.>
In-Reply-To: <CAK7LNARNUhyFpVRKYwmadkTGpR-aAjUNs2WgwYn3ao5Y+zTH1w@mail.gmail.com>
On Sat, 25 Mar 2017 23:40:38 +0900
Masahiro Yamada <yamada.masahiro@socionext.com> wrote:
> Hi Boris,
>
>
>
> 2017-03-25 5:13 GMT+09:00 Boris Brezillon <boris.brezillon@free-electrons.com>:
>
> >>
> >> Masahiro Yamada (53):
> >> mtd: nand: allow to set only one of ECC size and ECC strength from DT
> >> mtd: nand: use read_oob() instead of cmdfunc() for bad block check
> >> mtd: nand: denali: remove unused CONFIG option and macros
> >> mtd: nand: denali: remove redundant define of BANK(x)
> >> mtd: nand: denali: remove more unused struct members
> >> mtd: nand: denali: fix comment of denali_nand_info::flash_mem
> >> mtd: nand: denali: consolidate INTR_STATUS__* and INTR_EN__* macros
> >> mtd: nand: denali: introduce capability flag
> >> mtd: nand: denali: use int where no reason to use fixed width variable
> >> mtd: nand: denali: fix erased page checking
> >> mtd: nand: denali: fix bitflips calculation in handle_ecc()
> >> mtd: nand: denali: support HW_ECC_FIXUP capability
> >> mtd: nand: denali_dt: enable HW_ECC_FIXUP for Altera SOCFPGA variant
> >> mtd: nand: denali: support 64bit capable DMA engine
> >> mtd: nand: denali_dt: remove dma-mask DT property
> >> mtd: nand: denali_dt: use pdev instead of ofdev for platform_device
> >> mtd: nand: denali: allow to override revision number
> >> mtd: nand: denali: use nand_chip to hold frequently accessed data
> >> mtd: nand: denali: call nand_set_flash_node() to set DT node
> >> mtd: nand: denali: do not set mtd->name
> >> mtd: nand: denali: move multi device fixup code to a helper function
> >> mtd: nand: denali: simplify multi device fixup code
> >> mtd: nand: denali: set DEVICES_CONNECTED 1 if not set
> >> mtd: nand: denali: remove meaningless writes to read-only registers
> >> mtd: nand: denali: remove unnecessary writes to ECC_CORRECTION
> >> mtd: nand: denali: support 1024 byte ECC step size
> >> mtd: nand: denali: avoid hard-coding ecc.strength and ecc.bytes
> >> mtd: nand: denali: support "nand-ecc-strength" DT property
> >> mtd: nand: denali: remove Toshiba and Hynix specific fixup code
> >> mtd: nand: denali_dt: add compatible strings for UniPhier SoC variants
> >> mtd: nand: denali: set NAND_ECC_CUSTOM_PAGE_ACCESS
> >> mtd: nand: denali: do not propagate NAND_STATUS_FAIL to waitfunc()
> >> mtd: nand: denali: use BIT() and GENMASK() for register macros
> >> mtd: nand: denali: remove unneeded find_valid_banks()
> >> mtd: nand: denali: handle timing parameters by setup_data_interface()
> >> mtd: nand: denali: remove meaningless pipeline read-ahead operation
> >> mtd: nand: denali: rework interrupt handling
> >> mtd: nand: denali: fix NAND_CMD_STATUS handling
> >> mtd: nand: denali: fix NAND_CMD_PARAM handling
> >> mtd: nand: do not check R/B# for CMD_READID in nand_command(_lp)
> >> mtd: nand: do not check R/B# for CMD_SET_FEATURES in nand_command(_lp)
> >> mtd: nand: denali: switch over to cmd_ctrl instead of cmdfunc
> >> mtd: nand: denali: fix bank reset function
> >> mtd: nand: denali: use interrupt instead of polling for bank reset
> >> mtd: nand: denali: propagate page to helpers via function argument
> >> mtd: nand: denali: merge struct nand_buf into struct denali_nand_info
> >> mtd: nand: denali: use flag instead of register macro for direction
> >> mtd: nand: denali: fix raw and oob accessors for syndrome page layout
> >> mtd: nand: denali: support hardware-assisted erased page detection
> >> mtd: nand: allocate aligned buffers if NAND_OWN_BUFFERS is unset
> >> mtd: nand: denali: skip driver internal bounce buffer when possible
> >> mtd: nand: denali: use non-managed kmalloc() for DMA buffer
> >> mtd: nand: denali: enable bad block table scan
> >
> > Applied patch 1 to 9, 40 and 41. I'll see what else I can apply so that
> > you don't have to re-post the remaining 42 patches, but I fear some of
> > them won't apply correctly without patch 10 on which I had comments.
>
> Thanks!
>
> This will be very helpful when sending the next version.
>
> If you like, you can also apply the following 9 patches cleanly in this order.
>
> 18/53 mtd: nand: denali: use nand_chip to hold frequently accessed data
> 19/53 mtd: nand: denali: call nand_set_flash_node() to set DT node
> 20/53 mtd: nand: denali: do not set mtd->name
> 21/53 mtd: nand: denali: move multi device fixup code to a helper function
> 22/53 mtd: nand: denali: simplify multi device fixup code
> 23/53 mtd: nand: denali: set DEVICES_CONNECTED 1 if not set
> 24/53 mtd: nand: denali: remove meaningless writes to read-only registers
> 25/53 mtd: nand: denali: remove unnecessary writes to ECC_CORRECTION
Applied all the above patches.
> 36/53 mtd: nand: denali: remove meaningless pipeline read-ahead operation
Still need to review this one.
>
> These are less controversial, and have no dependency on 10/53-17/53.
>
>
>
>
> 50/53 "mtd: nand: allocate aligned buffers if NAND_OWN_BUFFERS is unset"
> is a change to the NAND framework. (used as a pre-requisite for 51/53)
Had a comment on the commit message (not the patch content). I find it
too alarmist: you seem to imply that all controller drivers doing DMA
on nand buffers allocated by the core are broken, which I think is not
the case.
I don't deny the theoretical risk of using non-cache aligned buffers,
but in practice, given the workflow we have in the NAND framework, I
don't think cache management operations can trigger data corruptions (I
might be wrong, though).
^ permalink raw reply
* Re: [PATCH] ARM: dts: vf610-zii-dev-rev-b: change switch2 label
From: Vivien Didelot @ 2017-03-28 20:04 UTC (permalink / raw)
To: Andrew Lunn
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
kernel-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/, Shawn Guo,
Florian Fainelli
In-Reply-To: <20170328193318.GG2268-g2DYL2Zd6BY@public.gmane.org>
Hi Andrew,
Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org> writes:
> You might need to rebase this onto
>
> git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
>
> There have been a few other changes to the ZII dts files this cycle.
This patch applies correctly on shawnguo/for-next. Is it the correct
branch to rebase onto?
Thanks,
Vivien
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^ permalink raw reply
* Re: [RFC 3/8] cpufreq: imx6q: Set max suspend_freq to avoid changes during suspend
From: Leonard Crestez @ 2017-03-28 20:03 UTC (permalink / raw)
To: Viresh Kumar
Cc: Mark Brown, Liam Girdwood, Rafael J. Wysocki, Shawn Guo,
Sascha Hauer, Robin Gong, Anson Huang, Irina Tirdea, Rob Herring,
Mark Rutland, Fabio Estevam, Octavian Purdila,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170323043427.GE12094@vireshk-i7>
On Thu, 2017-03-23 at 10:04 +0530, Viresh Kumar wrote:
> On 22-03-17, 18:53, Leonard Crestez wrote:
> > If the cpufreq driver tries to modify voltage/freq during suspend/resume
> > it might need to control an external PMIC via I2C or SPI but those
> > devices might be already suspended.
> >
> > To avoid this scenario we just increase cpufreq to highest setpoint
> > before suspend. This issue can easily be triggered by ldo-bypass but in
> > theory any regulator set_voltage call can end up having to modify
> > external supply voltages.
> >
> > Signed-off-by: Leonard Crestez <leonard.crestez-3arQi8VN3Tc@public.gmane.org>
> > ---
> > drivers/cpufreq/imx6q-cpufreq.c | 2 ++
> > 1 file changed, 2 insertions(+)
>
> Acked-by: Viresh Kumar <viresh.kumar-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
The first couple of patches are obvious fixes despite being marked as
RFC. It would be great if you could apply them to your tree separately
from the rest of the series but I'm not sure what the process is here.
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^ permalink raw reply
* Re: [RFC 4/8] regulator: core: Check enabling bypass respects constraints
From: Leonard Crestez @ 2017-03-28 19:49 UTC (permalink / raw)
To: Mark Brown
Cc: Sascha Hauer, Liam Girdwood, Viresh Kumar, Rafael J. Wysocki,
Shawn Guo, Robin Gong, Anson Huang, Irina Tirdea, Rob Herring,
Mark Rutland, Fabio Estevam, Octavian Purdila, linux-pm,
linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20170328164754.z2c2ttovs3sxbcos@sirena.org.uk>
On Tue, 2017-03-28 at 17:47 +0100, Mark Brown wrote:
> On Tue, Mar 28, 2017 at 03:39:41PM +0300, Leonard Crestez wrote:
> > On Fri, 2017-03-24 at 12:52 +0000, Mark Brown wrote:
> Please fix your mail client to word wrap within paragraphs at something
> substantially less than 80 columns. Doing this makes your messages much
> easier to read and reply to.
Sorry, still messing around with Evolution and Exchange.
> > > to the supply. Usually bypass is used for low power retention modes
> > > with different settings to those used in normal operation that wouldn't
> > > be desired in normal operation, if we were going to have constraints for
> > > this I'd expect a separate set used during bypass.
> >
> > In this particular case it's not possible to set constraints on the parent
> > regulator so that both ldo-enable and ldo-bypass modes work. The maximum allowed
> > voltage for ldo-bypass is lower than the minimum required to support the chip at
> > max frequency wit ldo-enable.
>
> If things are really so sensitive that you can't bypass without lowering
> the voltage then it's hard to see how you can safely transition into and
> out of bypass mode.
The CPU frequency is set to the minimum value so that when bypass mode
is entered and voltage rises (because the dropout goes away) it is
still low enough. Transitioning out of bypass mode is not implemented
but you would presumably have to go to the minimum frequency again,
raise the voltage above what is required and the flip the switch.
> > I'm not sure I understand why you are against applying constraints to the parent
> > when in bypass mode, it seems like the obvious thing to do if you want to
> > support flexible configuration. The check I introduced is probably not enough to
> > cover all cases, for example it would still be possible to explicitly change
> > parent voltage afterwards.
>
> To repeat what I said previously the whole point of bypassing is to not
> do regulation and generally the constraints in the unregulated idle case
> are substantially more relaxed. This would break use cases relying on
> the existing behaviour which wouldn't expect to affect the parent
> voltage at all, either stopping things working or making them less
> efficient by needlessly regulating the voltage down which defeats the
> main point of bypassing.
So what you want is to prevent voltage changes unless strictly
required, even lowering? What I want is to get the minimum voltage in
the SOC because that's where power is being consumed.
It's not at all obvious that in bypass mode the output constraints of a
regulator need not be respected by the core. I expected the opposite,
this is something that should be documented.
But if the bypassed regulator has a downstream consumer then it's
requirements should definitely still be met in bypass mode, right? I
could set my maximum voltage directly from cpufreq in that case.
Or should a bypassed regulator ignore all other requests? One of the
behaviors that this patch series relies on is that calling set_voltage
on a bypassed regulator propagates this request to the supply and picks
the minimum voltage there. An alternative implementation would be to
call set_voltage directly on the supply regulator by changing the
"{arm,soc,pu}-supply" references in DT to point to the PMIC instead.
Would that be better?
Both approaches work. Relying on propagation feels like it is the
"right way" to handle this, even if it's harder to get right and the
regulator core does not entirely support it. But it's possible that
this is based on a misunderstanding of what "bypass" is actually
supposed to do.
--
Regards,
Leonard
^ permalink raw reply
* Re: [GIT PULL] Immutable branch between MFD and LEDS due for the v4.12 merge window
From: Jacek Anaszewski @ 2017-03-28 19:37 UTC (permalink / raw)
To: Lee Jones, Sebastian Reichel
Cc: Richard Purdie, Pavel Machek, Tony Lindgren, Rob Herring,
Mark Rutland, linux-leds-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170328081342.5iobnc55sq3zucgt@dell>
On 03/28/2017 10:13 AM, Lee Jones wrote:
> Enjoy!
>
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git ib-mfd-leds-v4.12
>
> for you to fetch changes up to 4f9ab0c1570800002e77515888600ca2e3dce4a9:
>
> mfd: cpcap: Add missing include dependencies (2017-03-28 09:09:50 +0100)
>
> ----------------------------------------------------------------
> Immutable branch between MFD and LEDS due for the v4.12 merge window
>
> ----------------------------------------------------------------
> Sebastian Reichel (1):
> mfd: cpcap: Add missing include dependencies
>
> include/linux/mfd/motorola-cpcap.h | 3 +++
> 1 file changed, 3 insertions(+)
>
Pulled, thanks.
--
Best regards,
Jacek Anaszewski
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^ permalink raw reply
* Re: [PATCH v2 0/8] pinctrl: meson: add audio output pins
From: Kevin Hilman @ 2017-03-28 19:33 UTC (permalink / raw)
To: Jerome Brunet
Cc: Linus Walleij, Carlo Caione, linux-gpio, linux-arm-kernel,
linux-amlogic, devicetree, linux-kernel
In-Reply-To: <20170326171923.19269-1-jbrunet@baylibre.com>
Jerome Brunet <jbrunet@baylibre.com> writes:
> This patchset adds the pinctrl definition and the related device-tree
> bindings of the i2s output and spdif output pins on the meson gxbb and
> gxl SoCs.
>
> This is part of the ongoing work to bring audio output support on the
> meson family. It was tested on the gxbb p200 and gxl p230.
>
> Changes since v1: [0]
> * add a few comments in the changelog
> * patched rebased on pinctrl/for-next + Neil patch on missing pins [1]
>
> [0]: https://marc.info/?i=20170323165101.29262-1-jbrunet%40baylibre.com
> [1]: https://marc.info/?i=20170323104112.16558-2-narmstrong%40baylibre.com
>
> Jerome Brunet (8):
> pinctrl: meson: gxbb: add i2s output pins
> pinctrl: meson: gxbb: add spdif output pins
> pinctrl: meson: gxl: add i2s output pins
> pinctrl: meson: gxl: add spdif output pins
> ARM64: dts: meson-gxbb: add i2s output pins
> ARM64: dts: meson-gxbb: add spdif output pins
> ARM64: dts: meson-gxl: add i2s output pins
> ARM64: dts: meson-gxl: add spdif output pins
DT patches applied to amlogic v4.12/dt64 branch,
Thanks for the respin,
Kevin
^ permalink raw reply
* Re: [PATCH] ARM: dts: vf610-zii-dev-rev-b: change switch2 label
From: Andrew Lunn @ 2017-03-28 19:33 UTC (permalink / raw)
To: Vivien Didelot
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
kernel-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/, Shawn Guo,
Florian Fainelli
In-Reply-To: <20170328192426.13798-1-vivien.didelot-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/@public.gmane.org>
On Tue, Mar 28, 2017 at 03:24:26PM -0400, Vivien Didelot wrote:
> Rename the switch2@0 label of the switch2 node to switch@0 to respect
> the general unit@address DTS rule, and be consistent with the other
> switch nodes of the DTS file.
>
> Signed-off-by: Vivien Didelot <vivien.didelot-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/@public.gmane.org>
Hi Vivien
You might need to rebase this onto
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
There have been a few other changes to the ZII dts files this cycle.
Reviewed-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
Andrew
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^ permalink raw reply
* [PATCH] ARM: dts: vf610-zii-dev-rev-b: change switch2 label
From: Vivien Didelot @ 2017-03-28 19:24 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
kernel-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/, Shawn Guo,
Florian Fainelli, Andrew Lunn, Vivien Didelot
Rename the switch2@0 label of the switch2 node to switch@0 to respect
the general unit@address DTS rule, and be consistent with the other
switch nodes of the DTS file.
Signed-off-by: Vivien Didelot <vivien.didelot-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/@public.gmane.org>
---
arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
index 7940408838df..5a93f2d875b1 100644
--- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
+++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
@@ -239,7 +239,7 @@
#size-cells = <0>;
reg = <4>;
- switch2: switch2@0 {
+ switch2: switch@0 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
--
2.12.1
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^ permalink raw reply related
* Re: [RESEND PATCH v3 1/2] dt-bindings: i2c: Add Mediatek MT2701 i2c binding
From: Wolfram Sang @ 2017-03-28 19:22 UTC (permalink / raw)
To: Jun Gao
Cc: Matthias Brugger, robh-DgEjT+Ai2ygdnm+yROfE0A,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w
In-Reply-To: <1490694612.18582.11.camel@mhfsdcap03>
[-- Attachment #1: Type: text/plain, Size: 2709 bytes --]
On Tue, Mar 28, 2017 at 05:50:12PM +0800, Jun Gao wrote:
> On Wed, 2017-03-22 at 10:05 +0100, Wolfram Sang wrote:
> > On Thu, Mar 09, 2017 at 11:13:04AM +0800, Jun Gao wrote:
> > > From: Jun Gao <jun.gao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > >
> > > Add MT2701 i2c binding to i2c-mt6577.txt and there is no need to
> > > modify i2c driver.
> > >
> > > Signed-off-by: Jun Gao <jun.gao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> >
> > There is still the issue which Matthias Brugger pointed out on January,
> > 24th: you need to describe the fallback compatibles.
> >
>
> IMHO the value under compatible are just inputs which can be accepted.
> It's little strange to add fallback information in binding. Some other
> bindings do not describe so detailedly.
> Is it OK to make binding as minimum standard?
> If we describe it very detailedly, we will have to modify binding if
> there are some changes for mt2701.
My reading of the below is that I could simply use "mediatek,mt2701-i2c"
as compatible and things will work. But it won't, we don't have that in
the driver IIRC. So, we need a fallback for that to work.
> Rob, could you give some suggestions? Thanks!
Would be welcome, yes. I lost track what the preferred solution is.
>
> > > ---
> > > .../devicetree/bindings/i2c/i2c-mt6577.txt | 11 ++++++-----
> > > 1 file changed, 6 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
> > > index 0ce6fa3..27dbbf9 100644
> > > --- a/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
> > > +++ b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
> > > @@ -4,11 +4,12 @@ The Mediatek's I2C controller is used to interface with I2C devices.
> > >
> > > Required properties:
> > > - compatible: value should be either of the following.
> > > - (a) "mediatek,mt6577-i2c", for i2c compatible with mt6577 i2c.
> > > - (b) "mediatek,mt6589-i2c", for i2c compatible with mt6589 i2c.
> > > - (c) "mediatek,mt8127-i2c", for i2c compatible with mt8127 i2c.
> > > - (d) "mediatek,mt8135-i2c", for i2c compatible with mt8135 i2c.
> > > - (e) "mediatek,mt8173-i2c", for i2c compatible with mt8173 i2c.
> > > + "mediatek,mt2701-i2c"
> > > + "mediatek,mt6577-i2c"
> > > + "mediatek,mt6589-i2c"
> > > + "mediatek,mt8127-i2c"
> > > + "mediatek,mt8135-i2c"
> > > + "mediatek,mt8173-i2c"
> > > - reg: physical base address of the controller and dma base, length of memory
> > > mapped region.
> > > - interrupts: interrupt number to the cpu.
> > > --
> > > 1.7.9.5
> > >
>
>
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^ permalink raw reply
* Re: [PATCH v2,1/3] meson_uart: expose CLKID_UARTx
From: Jerome Brunet @ 2017-03-28 19:14 UTC (permalink / raw)
To: Helmut Klein, mturquette, sboyd
Cc: devicetree, linux-kernel, linux-amlogic, linux-clk,
linux-arm-kernel
In-Reply-To: <71489b62-78c8-7082-587e-8598dc43ca59@gmail.com>
On Tue, 2017-03-28 at 20:18 +0200, Helmut Klein wrote:
> i know for sure that the bluetooth chip of my system is connected to
> uart_A. so this clock must be exposed.
>
> i don't know if the other 2 uarts are used on other hardware. so i will
> remove them from my patch.
What I meant is device trees "upstream".
I would expect such patch as part of a series to add support for your board in
device-tree, with its bluetooth chipset.
I think it would better to drop this patch from the series.
You can either keep it for your personal work, or send it again when upstreaming
the support for your board and/or add the support for the bluetooth chip.
Cheers
Jerome
>
> Helmut
>
> On 28.03.2017 17:51, Jerome Brunet wrote:
> > On Tue, 2017-03-28 at 11:25 +0200, Helmut Klein wrote:
> > > Expose the clock ids for the three none AO uarts to the dt-bindings
> >
> > Are they all used in the device tree ?
> > We try to only expose what we need in the DT
> > The recent discussion over CLKID_CPUCLK proved it was a sane thing to do.
> >
> > >
> > > Signed-off-by: Helmut Klein <hgkr.klein@gmail.com>
> > > ---
> > > drivers/clk/meson/gxbb.h | 6 +++---
> > > include/dt-bindings/clock/gxbb-clkc.h | 3 +++
> > > 2 files changed, 6 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
> > > index 8ee2022ce5d5..1edfaa5fe307 100644
> > > --- a/drivers/clk/meson/gxbb.h
> > > +++ b/drivers/clk/meson/gxbb.h
> > > @@ -194,7 +194,7 @@
> > > /* #define CLKID_SAR_ADC */
> > > #define CLKID_SMART_CARD 24
> > > #define CLKID_RNG0 25
> > > -#define CLKID_UART0 26
> > > +/* CLKID_UART0 */
> > > #define CLKID_SDHC 27
> > > #define CLKID_STREAM 28
> > > #define CLKID_ASYNC_FIFO 29
> > > @@ -216,7 +216,7 @@
> > > #define CLKID_ADC 45
> > > #define CLKID_BLKMV 46
> > > #define CLKID_AIU 47
> > > -#define CLKID_UART1 48
> > > +/* CLKID_UART1 */
> > > #define CLKID_G2D 49
> > > /* CLKID_USB0 */
> > > /* CLKID_USB1 */
> > > @@ -236,7 +236,7 @@
> > > /* CLKID_USB0_DDR_BRIDGE */
> > > #define CLKID_MMC_PCLK 66
> > > #define CLKID_DVIN 67
> > > -#define CLKID_UART2 68
> > > +/* CLKID_UART2 */
> > > /* #define CLKID_SANA */
> > > #define CLKID_VPU_INTR 70
> > > #define CLKID_SEC_AHB_AHB3_BRIDGE 71
> > > diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-
> > > bindings/clock/gxbb-clkc.h
> > > index 692846c7941b..7b329df47752 100644
> > > --- a/include/dt-bindings/clock/gxbb-clkc.h
> > > +++ b/include/dt-bindings/clock/gxbb-clkc.h
> > > @@ -15,13 +15,16 @@
> > > #define CLKID_SPI 34
> > > #define CLKID_I2C 22
> > > #define CLKID_SAR_ADC 23
> > > +#define CLKID_UART0 26
> > > #define CLKID_ETH 36
> > > +#define CLKID_UART1 48
> > > #define CLKID_USB0 50
> > > #define CLKID_USB1 51
> > > #define CLKID_USB 55
> > > #define CLKID_HDMI_PCLK 63
> > > #define CLKID_USB1_DDR_BRIDGE 64
> > > #define CLKID_USB0_DDR_BRIDGE 65
> > > +#define CLKID_UART2 68
> > > #define CLKID_SANA 69
> > > #define CLKID_GCLK_VENCI_INT0 77
> > > #define CLKID_AO_I2C 93
> > > --
> > > 2.11.0
> > >
> > >
> > > _______________________________________________
> > > linux-amlogic mailing list
> > > linux-amlogic@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply
* [RFC PATCH] of: Fix DMA configuration for non-DT masters
From: Robin Murphy @ 2017-03-28 18:57 UTC (permalink / raw)
To: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
For PCI masters not represented in DT, we pass the OF node of their
associated host bridge to of_dma_configure(), such that they can inherit
the appropriate DMA configuration from whatever is described there.
Unfortunately, whilst this has worked for the "dma-coherent" property,
it turns out to miss the case where the host bridge node has a non-empty
"dma-ranges", since nobody is expecting the 'device' to be a bus itself.
It transpires, though, that the de-facto interface since the prototype
change in 1f5c69aa51f9 ("of: Move of_dma_configure() to device.c to help
re-use") is very clear-cut: either the master_np argument is redundant
with dev->of_node, or dev->of_node is NULL and master_np is the relevant
parent bus. Let's ratify that behaviour, then teach the whole
of_dma_configure() pipeline to cope with both cases properly.
Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
---
This is what I'd consider the better fix - rather than adding yet more
special cases - which will also make it simple to handle multiple
"dma-ranges" entries with minimal further disruption. The callers now
left passing dev->of_node as 'parent' are harmless, but look a bit silly
and clearly want cleaning up - I'd be partial to renaming the existing
function and having a single-argument wrapper for the 'normal' case, e.g.:
static inline int of_dma_configure(struct device_node *dev)
{
return of_dma_configure_parent(dev, NULL);
}
Thoughts?
Robin.
drivers/iommu/of_iommu.c | 7 ++++---
drivers/of/address.c | 37 +++++++++++++++++++++++++------------
drivers/of/device.c | 12 +++++++-----
include/linux/of_address.h | 7 ++++---
include/linux/of_device.h | 4 ++--
include/linux/of_iommu.h | 4 ++--
6 files changed, 44 insertions(+), 27 deletions(-)
diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c
index 2683e9fc0dcf..35aff07bb5eb 100644
--- a/drivers/iommu/of_iommu.c
+++ b/drivers/iommu/of_iommu.c
@@ -138,21 +138,22 @@ static const struct iommu_ops
}
const struct iommu_ops *of_iommu_configure(struct device *dev,
- struct device_node *master_np)
+ struct device_node *parent)
{
struct of_phandle_args iommu_spec;
- struct device_node *np;
+ struct device_node *np, *master_np;
const struct iommu_ops *ops = NULL;
int idx = 0;
if (dev_is_pci(dev))
- return of_pci_iommu_configure(to_pci_dev(dev), master_np);
+ return of_pci_iommu_configure(to_pci_dev(dev), parent);
/*
* We don't currently walk up the tree looking for a parent IOMMU.
* See the `Notes:' section of
* Documentation/devicetree/bindings/iommu/iommu.txt
*/
+ master_np = dev->of_node ? dev->of_node : parent;
while (!of_parse_phandle_with_args(master_np, "iommus",
"#iommu-cells", idx,
&iommu_spec)) {
diff --git a/drivers/of/address.c b/drivers/of/address.c
index 02b2903fe9d2..833bc17f5e55 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -808,6 +808,7 @@ EXPORT_SYMBOL(of_io_request_and_map);
/**
* of_dma_get_range - Get DMA range info
* @np: device node to get DMA range info
+ * @parent: node of device's parent bus, if @np is NULL
* @dma_addr: pointer to store initial DMA address of DMA range
* @paddr: pointer to store initial CPU address of DMA range
* @size: pointer to store size of DMA range
@@ -822,36 +823,48 @@ EXPORT_SYMBOL(of_io_request_and_map);
* It returns -ENODEV if "dma-ranges" property was not found
* for this device in DT.
*/
-int of_dma_get_range(struct device_node *np, u64 *dma_addr, u64 *paddr, u64 *size)
+int of_dma_get_range(struct device_node *np, struct device_node *parent,
+ u64 *dma_addr, u64 *paddr, u64 *size)
{
- struct device_node *node = of_node_get(np);
+ struct device_node *node;
const __be32 *ranges = NULL;
int len, naddr, nsize, pna;
int ret = 0;
u64 dmaaddr;
- if (!node)
- return -EINVAL;
-
- while (1) {
+ if (np) {
+ node = of_node_get(np);
naddr = of_n_addr_cells(node);
nsize = of_n_size_cells(node);
node = of_get_next_parent(node);
- if (!node)
- break;
+ } else if (parent) {
+ node = of_node_get(parent);
+ np = parent;
+ if (of_property_read_u32(node, "#address-cells", &naddr))
+ naddr = of_n_addr_cells(node);
+ if (of_property_read_u32(node, "#size-cells", &nsize))
+ nsize = of_n_size_cells(node);
+ } else {
+ return -EINVAL;
+ }
+ while (node) {
ranges = of_get_property(node, "dma-ranges", &len);
- /* Ignore empty ranges, they imply no translation required */
- if (ranges && len > 0)
- break;
-
/*
* At least empty ranges has to be defined for parent node if
* DMA is supported
*/
if (!ranges)
break;
+
+ /* Ignore empty ranges, they imply no translation required */
+ if (len > 0)
+ break;
+
+ naddr = of_n_addr_cells(node);
+ nsize = of_n_size_cells(node);
+ node = of_get_next_parent(node);
}
if (!ranges) {
diff --git a/drivers/of/device.c b/drivers/of/device.c
index 9bb8518b28f2..57ec5324ed6c 100644
--- a/drivers/of/device.c
+++ b/drivers/of/device.c
@@ -73,7 +73,8 @@ int of_device_add(struct platform_device *ofdev)
/**
* of_dma_configure - Setup DMA configuration
* @dev: Device to apply DMA configuration
- * @np: Pointer to OF node having DMA configuration
+ * @parent: OF node of device's parent bus, if @dev is not
+ * represented in DT (i.e. @dev->of_node is NULL)
*
* Try to get devices's DMA configuration from DT and update it
* accordingly.
@@ -82,13 +83,14 @@ int of_device_add(struct platform_device *ofdev)
* can use a platform bus notifier and handle BUS_NOTIFY_ADD_DEVICE events
* to fix up DMA configuration.
*/
-void of_dma_configure(struct device *dev, struct device_node *np)
+void of_dma_configure(struct device *dev, struct device_node *parent)
{
u64 dma_addr, paddr, size;
int ret;
bool coherent;
unsigned long offset;
const struct iommu_ops *iommu;
+ struct device_node *np = dev->of_node;
/*
* Set default coherent_dma_mask to 32 bit. Drivers are expected to
@@ -104,7 +106,7 @@ void of_dma_configure(struct device *dev, struct device_node *np)
if (!dev->dma_mask)
dev->dma_mask = &dev->coherent_dma_mask;
- ret = of_dma_get_range(np, &dma_addr, &paddr, &size);
+ ret = of_dma_get_range(np, parent, &dma_addr, &paddr, &size);
if (ret < 0) {
dma_addr = offset = 0;
size = dev->coherent_dma_mask + 1;
@@ -132,11 +134,11 @@ void of_dma_configure(struct device *dev, struct device_node *np)
dev->coherent_dma_mask = DMA_BIT_MASK(ilog2(dma_addr + size));
*dev->dma_mask = dev->coherent_dma_mask;
- coherent = of_dma_is_coherent(np);
+ coherent = of_dma_is_coherent(np ? np : parent);
dev_dbg(dev, "device is%sdma coherent\n",
coherent ? " " : " not ");
- iommu = of_iommu_configure(dev, np);
+ iommu = of_iommu_configure(dev, parent);
dev_dbg(dev, "device is%sbehind an iommu\n",
iommu ? " " : " not ");
diff --git a/include/linux/of_address.h b/include/linux/of_address.h
index 37864734ca50..f1a507f3ae57 100644
--- a/include/linux/of_address.h
+++ b/include/linux/of_address.h
@@ -52,8 +52,8 @@ extern int of_pci_range_parser_init(struct of_pci_range_parser *parser,
extern struct of_pci_range *of_pci_range_parser_one(
struct of_pci_range_parser *parser,
struct of_pci_range *range);
-extern int of_dma_get_range(struct device_node *np, u64 *dma_addr,
- u64 *paddr, u64 *size);
+extern int of_dma_get_range(struct device_node *np, struct device_node *parent,
+ u64 *dma_addr, u64 *paddr, u64 *size);
extern bool of_dma_is_coherent(struct device_node *np);
#else /* CONFIG_OF_ADDRESS */
static inline void __iomem *of_io_request_and_map(struct device_node *device,
@@ -95,7 +95,8 @@ static inline struct of_pci_range *of_pci_range_parser_one(
return NULL;
}
-static inline int of_dma_get_range(struct device_node *np, u64 *dma_addr,
+static inline int of_dma_get_range(struct device_node *np,
+ struct device_node *parent, u64 *dma_addr,
u64 *paddr, u64 *size)
{
return -ENODEV;
diff --git a/include/linux/of_device.h b/include/linux/of_device.h
index c12dace043f3..bcd2b6fbeef3 100644
--- a/include/linux/of_device.h
+++ b/include/linux/of_device.h
@@ -55,7 +55,7 @@ static inline struct device_node *of_cpu_device_node_get(int cpu)
return of_node_get(cpu_dev->of_node);
}
-void of_dma_configure(struct device *dev, struct device_node *np);
+void of_dma_configure(struct device *dev, struct device_node *parent);
#else /* CONFIG_OF */
static inline int of_driver_match_device(struct device *dev,
@@ -103,7 +103,7 @@ static inline struct device_node *of_cpu_device_node_get(int cpu)
{
return NULL;
}
-static inline void of_dma_configure(struct device *dev, struct device_node *np)
+static inline void of_dma_configure(struct device *dev, struct device_node *parent)
{}
#endif /* CONFIG_OF */
diff --git a/include/linux/of_iommu.h b/include/linux/of_iommu.h
index 13394ac83c66..c02b62e8e6ed 100644
--- a/include/linux/of_iommu.h
+++ b/include/linux/of_iommu.h
@@ -12,7 +12,7 @@ extern int of_get_dma_window(struct device_node *dn, const char *prefix,
size_t *size);
extern const struct iommu_ops *of_iommu_configure(struct device *dev,
- struct device_node *master_np);
+ struct device_node *parent);
#else
@@ -24,7 +24,7 @@ static inline int of_get_dma_window(struct device_node *dn, const char *prefix,
}
static inline const struct iommu_ops *of_iommu_configure(struct device *dev,
- struct device_node *master_np)
+ struct device_node *parent)
{
return NULL;
}
--
2.11.0.dirty
^ permalink raw reply related
* Re: [PATCH] arm64: tegra: Add CPU and PSCI nodes for NVIDIA Tegra210 platforms
From: Mark Rutland @ 2017-03-28 18:54 UTC (permalink / raw)
To: Jon Hunter
Cc: Stephen Warren, devicetree-u79uwXL29TY76Z2rM5mHXA, Stephen Warren,
Vagrant Cascadian, Thierry Reding,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Martin Michlmayr,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <f9c59c65-de48-108d-73df-c659cc3300e6-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On Tue, Mar 28, 2017 at 05:49:41PM +0100, Jon Hunter wrote:
>
> On 28/03/17 17:23, Stephen Warren wrote:
> > On 03/28/2017 05:48 AM, Jon Hunter wrote:
> >> Add the CPU and PSCI nodes for the NVIDIA Tegra210 platforms so that
> >> all CPUs can be enabled on boot. This assumes that the PSCI firmware
> >> has been loaded during the initial bootstrap on the device before the
> >> kernel starts (which is typically the case for these platforms). The
> >> PSCI firmware version is set to v0.2 which aligns with the current
> >> shipping version for Tegra.
> >
> > This seems fine, although I'd expect PSCI to be used everywhere on
> > Tegra, so putting this in tegra210.dtsi would make more sense.
>
> It's fine with me. Although technically, tegra210-smaug ships with
> psci-v1.0 and tegra210-jetson-tx1 currently have psci-v0.2. However, I
> did test both with the psci version set to v1.0 and the jetson-tx1, did
> detect the version automatically and reverted to v0.2 (which is a
> feature of psci >= v0.2).
Please don't rely upon that.
If the DT lists 0.2 and the FW reports 1.0 we deliberately upgrade and
treat it as 1.0, but the other way around was not a deliberate decision.
If the FW is not necessarily 1.0, please do not list 1.0 in the DT.
Thanks,
Mark.
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^ permalink raw reply
* Re: [PATCH v2, 2/3] tty/serial: meson_uart: add documentation for the dt-bindings
From: Helmut Klein @ 2017-03-28 18:20 UTC (permalink / raw)
To: Mark Rutland
Cc: devicetree, robh+dt, linux-kernel, linux-arm-kernel,
linux-amlogic
In-Reply-To: <20170328100551.GA24221@leverpostej>
Hallo Mark,
i will add your text to the patch.
Helmut
On 28.03.2017 12:05, Mark Rutland wrote:
> On Tue, Mar 28, 2017 at 11:25:44AM +0200, Helmut Klein wrote:
>> Add the documentation for the device tree binding of meson_uart
>>
>> Signed-off-by: Helmut Klein <hgkr.klein@gmail.com>
>> ---
>> .../bindings/serial/amlogic,meson_uart.txt | 25 ++++++++++++++++++++++
>> 1 file changed, 25 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/serial/amlogic,meson_uart.txt
>>
>> diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson_uart.txt b/Documentation/devicetree/bindings/serial/amlogic,meson_uart.txt
>> new file mode 100644
>> index 000000000000..6f94ba25760d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/serial/amlogic,meson_uart.txt
>> @@ -0,0 +1,25 @@
>> +* Amlogic Meson UART, used in multiple SoCs (e.g. S905, s905X, ...)
>> +
>> +Required properties:
>> +- compatible : "amlogic,meson-uart"
>> +- reg : offset and length of the register set for the device.
>> +- interrupts : device interrupt
>> +- clocks : the baud rate clock for the UART and optionally the core clock for the none AO uarts
>> +e.g.
>> +uart_A: serial@84c0 {
>> + compatible = "amlogic,meson-uart";
>> + reg = <0x0 0x84c0 0x0 0x14>;
>> + pinctrl-0 = <&uart_a_pins &uart_a_cts_rts_pins>;
>> + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>> + clocks = <&xtal>, <&clkc CLKID_UART0>;
>> + clock-names = "xtal", "core";
>
> Please define these explicitly above, e.g.
>
> - clocks: a list of phandle + clock-specifier pairs, one for each entry
> in clock names.
> - clock-names: contains:
> * "xtal" for the baud rate clock
> * "core" for the non-AO UARTs (optional)
>
> Thanks,
> Mark.
>
^ permalink raw reply
* Re: [PATCH v2,1/3] meson_uart: expose CLKID_UARTx
From: Helmut Klein @ 2017-03-28 18:18 UTC (permalink / raw)
To: Jerome Brunet, mturquette, sboyd
Cc: devicetree, linux-clk, linux-kernel, linux-arm-kernel,
linux-amlogic
In-Reply-To: <1490716277.20764.6.camel@baylibre.com>
i know for sure that the bluetooth chip of my system is connected to
uart_A. so this clock must be exposed.
i don't know if the other 2 uarts are used on other hardware. so i will
remove them from my patch.
Helmut
On 28.03.2017 17:51, Jerome Brunet wrote:
> On Tue, 2017-03-28 at 11:25 +0200, Helmut Klein wrote:
>> Expose the clock ids for the three none AO uarts to the dt-bindings
>
> Are they all used in the device tree ?
> We try to only expose what we need in the DT
> The recent discussion over CLKID_CPUCLK proved it was a sane thing to do.
>
>>
>> Signed-off-by: Helmut Klein <hgkr.klein@gmail.com>
>> ---
>> drivers/clk/meson/gxbb.h | 6 +++---
>> include/dt-bindings/clock/gxbb-clkc.h | 3 +++
>> 2 files changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
>> index 8ee2022ce5d5..1edfaa5fe307 100644
>> --- a/drivers/clk/meson/gxbb.h
>> +++ b/drivers/clk/meson/gxbb.h
>> @@ -194,7 +194,7 @@
>> /* #define CLKID_SAR_ADC */
>> #define CLKID_SMART_CARD 24
>> #define CLKID_RNG0 25
>> -#define CLKID_UART0 26
>> +/* CLKID_UART0 */
>> #define CLKID_SDHC 27
>> #define CLKID_STREAM 28
>> #define CLKID_ASYNC_FIFO 29
>> @@ -216,7 +216,7 @@
>> #define CLKID_ADC 45
>> #define CLKID_BLKMV 46
>> #define CLKID_AIU 47
>> -#define CLKID_UART1 48
>> +/* CLKID_UART1 */
>> #define CLKID_G2D 49
>> /* CLKID_USB0 */
>> /* CLKID_USB1 */
>> @@ -236,7 +236,7 @@
>> /* CLKID_USB0_DDR_BRIDGE */
>> #define CLKID_MMC_PCLK 66
>> #define CLKID_DVIN 67
>> -#define CLKID_UART2 68
>> +/* CLKID_UART2 */
>> /* #define CLKID_SANA */
>> #define CLKID_VPU_INTR 70
>> #define CLKID_SEC_AHB_AHB3_BRIDGE 71
>> diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-
>> bindings/clock/gxbb-clkc.h
>> index 692846c7941b..7b329df47752 100644
>> --- a/include/dt-bindings/clock/gxbb-clkc.h
>> +++ b/include/dt-bindings/clock/gxbb-clkc.h
>> @@ -15,13 +15,16 @@
>> #define CLKID_SPI 34
>> #define CLKID_I2C 22
>> #define CLKID_SAR_ADC 23
>> +#define CLKID_UART0 26
>> #define CLKID_ETH 36
>> +#define CLKID_UART1 48
>> #define CLKID_USB0 50
>> #define CLKID_USB1 51
>> #define CLKID_USB 55
>> #define CLKID_HDMI_PCLK 63
>> #define CLKID_USB1_DDR_BRIDGE 64
>> #define CLKID_USB0_DDR_BRIDGE 65
>> +#define CLKID_UART2 68
>> #define CLKID_SANA 69
>> #define CLKID_GCLK_VENCI_INT0 77
>> #define CLKID_AO_I2C 93
>> --
>> 2.11.0
>>
>>
>> _______________________________________________
>> linux-amlogic mailing list
>> linux-amlogic@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-amlogic
>
^ permalink raw reply
* Re: [PATCH v4 2/3] mailbox: Add iProc mailbox controller driver
From: Jonathan Richardson @ 2017-03-28 17:30 UTC (permalink / raw)
To: Jassi Brar
Cc: Rob Herring, Mark Rutland, Ray Jui, Scott Branden, Jon Mason,
Russell King, Vikram Prakash, Devicetree List,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
BCM Kernel Feedback
In-Reply-To: <CABb+yY1kbFOKJPO95SRw995zt=fCoA+SkXgECOj774i_hJUCNg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 17-03-15 10:30 AM, Jassi Brar wrote:
> On Fri, Mar 3, 2017 at 2:33 AM, Jonathan Richardson
> <jonathan.richardson-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote:
>>
>> On 17-02-23 09:00 PM, Jassi Brar wrote:
>>> On Fri, Feb 24, 2017 at 12:29 AM, Jonathan Richardson
>>> <jonathan.richardson-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote:
>>>> On 17-02-16 10:20 PM, Jassi Brar wrote:
>>>>> On Fri, Jan 27, 2017 at 2:08 AM, Jonathan Richardson
>>>>> <jonathan.richardson-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote:
>>>>>
>>>>>> +static int iproc_mbox_send_data_m0(struct mbox_chan *chan, void *data)
>>>>>> +{
>>>>>> + struct iproc_mbox *mbox = dev_get_drvdata(chan->mbox->dev);
>>>>>> + struct iproc_mbox_msg *msg = (struct iproc_mbox_msg *)data;
>>>>>> + unsigned long flags;
>>>>>> + int err = 0;
>>>>>> + const int poll_period_us = 5;
>>>>>> + const int max_retries = (MAX_M0_TIMEOUT_MS * 1000) / poll_period_us;
>>>>>> +
>>>>>> + if (!msg)
>>>>>> + return -EINVAL;
>>>>>> +
>>>>>> + spin_lock_irqsave(&mbox->lock, flags);
>>>>>> +
>>>>>> + dev_dbg(mbox->dev, "Send msg to M0: cmd=0x%x, param=0x%x, wait_ack=%d\n",
>>>>>> + msg->cmd, msg->param, msg->wait_ack);
>>>>>> +
>>>>> prints should be outside the spinlocks.
>>>>>
>>>>>> + writel(msg->cmd, mbox->base + IPROC_CRMU_MAILBOX0_OFFSET);
>>>>>> + writel(msg->param, mbox->base + IPROC_CRMU_MAILBOX1_OFFSET);
>>>>>> +
>>>>>> + if (msg->wait_ack) {
>>>>>> + int retries;
>>>>>> +
>>>>> move poll_period_us and max_retries in here or just define' them
>>>>>
>>>>>> + err = msg->reply_code = -ETIMEDOUT;
>>>>>> + for (retries = 0; retries < max_retries; retries++) {
>>>>>> + u32 val = readl(
>>>>>> + mbox->base + IPROC_CRMU_MAILBOX0_OFFSET);
>>>>>> + if (val & M0_IPC_CMD_DONE_MASK) {
>>>>>> + /*
>>>>>> + * M0 replied - save reply code and
>>>>>> + * clear error.
>>>>>> + */
>>>>>> + msg->reply_code = (val &
>>>>>> + M0_IPC_CMD_REPLY_MASK) >>
>>>>>> + M0_IPC_CMD_REPLY_SHIFT;
>>>>>> + err = 0;
>>>>>> + break;
>>>>>> + }
>>>>>> + udelay(poll_period_us);
>>>>>>
>>>>> potentially 2ms inside spin_lock_irqsave. Alternative is to implement
>>>>> a simple 'peek_data' and call it for requests with 'wait_ack'
>>>> Hi Jassi. The M0 response is normally 25-30 us.
>>>>
>>> You hardcode the behaviour of your protocol in the controller driver.
>>> What if your next platform/protocol has commands that the remote/M0
>>> takes upto 10ms to respond (because they are not critical/trivial)?
>>>
> You overlooked this concern?
>
>>> If you don't have some h/w indicator (like irq or bit-flag) for
>>> tx-done and data-rx , you have to use ack-by-client and peek method.
>> There isn't any functionality not in the driver. We write the message to two registers and poll another to know when it's complete. Nothing can touch the registers again until the operation is complete. We can't even pass data back to the controller. We pass pointers to the M0 and it can write to the memory. The only data we sent back to the client is that status code from the polled register. When complete, data will already be written into the clients memory from the M0.
>>> Commands that don't get a response will be immediately followed by
>>> mbox_client_txdone(), while others would need to call peek_data() to
>>> poll for data-rx. Please note, if you implement the tx_prepare
>>> callback, you will know when to start peeking for incoming data.
>> The driver will need to block access to the registers if we remove the spinlock.
>> If a client sends a message that doesn't get a response and another client has
>> already sent a message that does which is pending, it still needs to be blocked.
>>
>> The framework queues messages on a per channel basis. We have several clients for
>> various drivers each with their own mbox channel. send_data in the controller could
>> return EBUSY if the channel is being used by another channel (ie- transaction pending).
>> If channel A sends a message, then client B sends one before A is complete, the
>> controller's send_data must return an error.
>>
> Many platforms have clients sharing channels.
Hi Jassi. Could you point me to one? I've looked at all of them and don't see any of them sharing channels.
> The right way to do is have a 'server/owner' client that accepts
> requests from various clients and serially queue them to mailbox. That
> way you can keep the controller driver free from quirks (like max wait
> time of 30us) of your present platform.
Do you mean 1 mailbox client with one mailbox channel that all the mbox client drivers share? I thought this would work when I suggested it previously but the client callbacks are necessary in all txdone modes. Client drivers that send the messages need the callbacks and this is only possible with multiple mbox clients. And a channel can only have 1 mbox client. Clients in multiple drivers need the callbacks to either know when to start polling, or be notified when the transaction is complete. It would be nice if multiple clients could use the same channel.
Thanks.
> thanks
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^ permalink raw reply
* [RFC PATCH 3/3] ARM: sun8i: h3: add support for the thermal sensor in H3
From: Icenowy Zheng @ 2017-03-28 17:30 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Jonathan Cameron, Zhang Rui, Quentin Schulz
Cc: devicetree, linux-pm, linux-iio, linux-kernel, linux-arm-kernel,
Icenowy Zheng
In-Reply-To: <20170328173013.16539-1-icenowy@aosc.io>
As we have gained the support for the thermal sensor in H3, we can now
add its device nodes to the device tree.
Add them to the H3 device tree.
The H5 thermal sensor has some differences, and will be added furtherly.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index b36f9f423c39..552217bb9266 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -72,6 +72,32 @@
};
};
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&ths>;
+ };
+
+ soc {
+ ths: ths@01c25000 {
+ compatible = "allwinner,sun8i-h3-ths";
+ reg = <0x01c25000 0x100>;
+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+ clock-names = "bus", "ths";
+ resets = <&ccu RST_BUS_THS>;
+ #thermal-sensor-cells = <0>;
+ #io-channel-cells = <0>;
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal {
+ /* milliseconds */
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&ths>;
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
--
2.12.0
^ permalink raw reply related
* [RFC PATCH 2/3] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor
From: Icenowy Zheng @ 2017-03-28 17:30 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Jonathan Cameron, Zhang Rui, Quentin Schulz
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-iio, linux-pm,
Icenowy Zheng
In-Reply-To: <20170328173013.16539-1-icenowy@aosc.io>
This adds support for the Allwinner H3 thermal sensor.
Allwinner H3 has a thermal sensor like the one in A33, but have its
registers nearly all re-arranged, sample clock moved to CCU and a pair
of bus clock and reset added. It's also the base of newer SoCs' thermal
sensors.
An option is added to gpadc_data struct, to indicate whether this device
is a new-generation Allwinner thermal sensor.
The thermal sensors on A64 and H5 is like the one on H3, but with of
course different formula factors.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/iio/adc/sun4i-gpadc-iio.c | 130 ++++++++++++++++++++++++++++++++------
include/linux/mfd/sun4i-gpadc.h | 33 +++++++++-
2 files changed, 141 insertions(+), 22 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c
index 74705aa37982..7512b1cae877 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -22,6 +22,7 @@
* shutdown for not being used.
*/
+#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/io.h>
@@ -31,6 +32,7 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
+#include <linux/reset.h>
#include <linux/thermal.h>
#include <linux/delay.h>
@@ -56,6 +58,7 @@ struct gpadc_data {
unsigned int tp_adc_select;
unsigned int (*adc_chan_select)(unsigned int chan);
unsigned int adc_chan_mask;
+ bool gen2_ths;
};
static const struct gpadc_data sun4i_gpadc_data = {
@@ -88,7 +91,20 @@ static const struct gpadc_data sun6i_gpadc_data = {
static const struct gpadc_data sun8i_a33_gpadc_data = {
.temp_offset = -1662,
.temp_scale = 162,
- .tp_mode_en = SUN8I_GPADC_CTRL1_CHOP_TEMP_EN,
+ .tp_mode_en = SUN8I_A23_GPADC_CTRL1_CHOP_TEMP_EN,
+};
+
+static const struct gpadc_data sun8i_h3_gpadc_data = {
+ /*
+ * The original formula on the datasheet seems to be wrong.
+ * These factors are calculated based on the formula in the BSP
+ * kernel, which is originally Tem = 217 - (T / 8.253), in which Tem
+ * is the temperature in Celsius degree and T is the raw value
+ * from the sensor.
+ */
+ .temp_offset = -1791,
+ .temp_scale = -121,
+ .gen2_ths = true,
};
struct sun4i_gpadc_iio {
@@ -103,6 +119,9 @@ struct sun4i_gpadc_iio {
atomic_t ignore_temp_data_irq;
const struct gpadc_data *data;
bool no_irq;
+ struct clk *ths_bus_clk;
+ struct clk *ths_clk;
+ struct reset_control *reset;
/* prevents concurrent reads of temperature and ADC */
struct mutex mutex;
};
@@ -274,7 +293,11 @@ static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val)
if (info->no_irq) {
pm_runtime_get_sync(indio_dev->dev.parent);
- regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, val);
+ if (info->data->gen2_ths)
+ regmap_read(info->regmap, SUN8I_H3_GPADC_TEMP_DATA,
+ val);
+ else
+ regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, val);
pm_runtime_mark_last_busy(indio_dev->dev.parent);
pm_runtime_put_autosuspend(indio_dev->dev.parent);
@@ -386,10 +409,15 @@ static int sun4i_gpadc_runtime_suspend(struct device *dev)
{
struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
- /* Disable the ADC on IP */
- regmap_write(info->regmap, SUN4I_GPADC_CTRL1, 0);
- /* Disable temperature sensor on IP */
- regmap_write(info->regmap, SUN4I_GPADC_TPR, 0);
+ if (info->data->gen2_ths) {
+ /* Disable temperature sensor */
+ regmap_write(info->regmap, SUN8I_H3_GPADC_CTRL2, 0);
+ } else {
+ /* Disable the ADC on IP */
+ regmap_write(info->regmap, SUN4I_GPADC_CTRL1, 0);
+ /* Disable temperature sensor on IP */
+ regmap_write(info->regmap, SUN4I_GPADC_TPR, 0);
+ }
return 0;
}
@@ -398,19 +426,36 @@ static int sun4i_gpadc_runtime_resume(struct device *dev)
{
struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
- /* clkin = 6MHz */
- regmap_write(info->regmap, SUN4I_GPADC_CTRL0,
- SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(2) |
- SUN4I_GPADC_CTRL0_FS_DIV(7) |
- SUN4I_GPADC_CTRL0_T_ACQ(63));
- regmap_write(info->regmap, SUN4I_GPADC_CTRL1, info->data->tp_mode_en);
- regmap_write(info->regmap, SUN4I_GPADC_CTRL3,
- SUN4I_GPADC_CTRL3_FILTER_EN |
- SUN4I_GPADC_CTRL3_FILTER_TYPE(1));
- /* period = SUN4I_GPADC_TPR_TEMP_PERIOD * 256 * 16 / clkin; ~0.6s */
- regmap_write(info->regmap, SUN4I_GPADC_TPR,
- SUN4I_GPADC_TPR_TEMP_ENABLE |
- SUN4I_GPADC_TPR_TEMP_PERIOD(800));
+ if (info->data->gen2_ths) {
+ regmap_write(info->regmap, SUN8I_H3_GPADC_CTRL2,
+ SUN8I_H3_GPADC_CTRL2_TEMP_SENSE_EN |
+ SUN8I_H3_GPADC_CTRL2_T_ACQ1(31));
+ regmap_write(info->regmap, SUN4I_GPADC_CTRL0,
+ SUN4I_GPADC_CTRL0_T_ACQ(31));
+ regmap_write(info->regmap, SUN8I_H3_GPADC_CTRL3,
+ SUN4I_GPADC_CTRL3_FILTER_EN |
+ SUN4I_GPADC_CTRL3_FILTER_TYPE(1));
+ regmap_write(info->regmap, SUN8I_H3_GPADC_INTC,
+ SUN8I_H3_GPADC_INTC_TEMP_PERIOD(800));
+ } else {
+ /* clkin = 6MHz */
+ regmap_write(info->regmap, SUN4I_GPADC_CTRL0,
+ SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(2) |
+ SUN4I_GPADC_CTRL0_FS_DIV(7) |
+ SUN4I_GPADC_CTRL0_T_ACQ(63));
+ regmap_write(info->regmap, SUN4I_GPADC_CTRL1,
+ info->data->tp_mode_en);
+ regmap_write(info->regmap, SUN4I_GPADC_CTRL3,
+ SUN4I_GPADC_CTRL3_FILTER_EN |
+ SUN4I_GPADC_CTRL3_FILTER_TYPE(1));
+ /*
+ * period = SUN4I_GPADC_TPR_TEMP_PERIOD * 256 * 16 / clkin;
+ * ~0.6s
+ */
+ regmap_write(info->regmap, SUN4I_GPADC_TPR,
+ SUN4I_GPADC_TPR_TEMP_ENABLE |
+ SUN4I_GPADC_TPR_TEMP_PERIOD(800));
+ }
return 0;
}
@@ -494,6 +539,10 @@ static const struct of_device_id sun4i_gpadc_of_id[] = {
.compatible = "allwinner,sun8i-a33-ths",
.data = &sun8i_a33_gpadc_data,
},
+ {
+ .compatible = "allwinner,sun8i-h3-ths",
+ .data = &sun8i_h3_gpadc_data,
+ },
{ /* sentinel */ }
};
@@ -529,6 +578,43 @@ static int sun4i_gpadc_probe_dt(struct platform_device *pdev,
return ret;
}
+ if (info->data->gen2_ths) {
+ info->reset = devm_reset_control_get(&pdev->dev, NULL);
+ if (IS_ERR(info->reset)) {
+ ret = PTR_ERR(info->reset);
+ return ret;
+ }
+
+ ret = reset_control_deassert(info->reset);
+ if (ret)
+ return ret;
+
+ info->ths_bus_clk = devm_clk_get(&pdev->dev, "bus");
+ if (IS_ERR(info->ths_bus_clk)) {
+ ret = PTR_ERR(info->ths_bus_clk);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(info->ths_bus_clk);
+ if (ret)
+ return ret;
+
+ info->ths_clk = devm_clk_get(&pdev->dev, "ths");
+ if (IS_ERR(info->ths_clk)) {
+ ret = PTR_ERR(info->ths_clk);
+ return ret;
+ }
+
+ /* Running at 6MHz */
+ ret = clk_set_rate(info->ths_clk, 6000000);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(info->ths_clk);
+ if (ret)
+ return ret;
+ }
+
if (!IS_ENABLED(CONFIG_THERMAL_OF))
return 0;
@@ -691,6 +777,12 @@ static int sun4i_gpadc_remove(struct platform_device *pdev)
if (!info->no_irq && IS_ENABLED(CONFIG_THERMAL_OF))
iio_map_array_unregister(indio_dev);
+ if (info->data->gen2_ths) {
+ clk_disable_unprepare(info->ths_clk);
+ clk_disable_unprepare(info->ths_bus_clk);
+ reset_control_deassert(info->reset);
+ }
+
return 0;
}
diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h
index 139872c2e0fe..f794a2988a93 100644
--- a/include/linux/mfd/sun4i-gpadc.h
+++ b/include/linux/mfd/sun4i-gpadc.h
@@ -38,9 +38,12 @@
#define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(3, 0) & BIT(x))
#define SUN6I_GPADC_CTRL1_ADC_CHAN_MASK GENMASK(3, 0)
-/* TP_CTRL1 bits for sun8i SoCs */
-#define SUN8I_GPADC_CTRL1_CHOP_TEMP_EN BIT(8)
-#define SUN8I_GPADC_CTRL1_GPADC_CALI_EN BIT(7)
+/* TP_CTRL1 bits for sun8i A23/A33 SoCs */
+#define SUN8I_A23_GPADC_CTRL1_CHOP_TEMP_EN BIT(8)
+#define SUN8I_A23_GPADC_CTRL1_GPADC_CALI_EN BIT(7)
+
+/* TP_CTRL1 bits for SoCs after H3 */
+#define SUN8I_H3_GPADC_CTRL1_GPADC_CALI_EN BIT(17)
#define SUN4I_GPADC_CTRL2 0x08
@@ -49,7 +52,17 @@
#define SUN4I_GPADC_CTRL2_PRE_MEA_EN BIT(24)
#define SUN4I_GPADC_CTRL2_PRE_MEA_THRE_CNT(x) (GENMASK(23, 0) & (x))
+#define SUN8I_H3_GPADC_CTRL2 0x40
+
+#define SUN8I_H3_GPADC_CTRL2_TEMP_SENSE_EN BIT(0)
+#define SUN8I_H3_GPADC_CTRL2_T_ACQ1(x) ((GENMASK(15, 0) * (x)) << 16)
+
#define SUN4I_GPADC_CTRL3 0x0c
+/*
+ * This register is named "Average filter Control Register" in H3 Datasheet,
+ * but the register's definition is the same as the old CTRL3 register.
+ */
+#define SUN8I_H3_GPADC_CTRL3 0x70
#define SUN4I_GPADC_CTRL3_FILTER_EN BIT(2)
#define SUN4I_GPADC_CTRL3_FILTER_TYPE(x) (GENMASK(1, 0) & (x))
@@ -71,6 +84,13 @@
#define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN BIT(1)
#define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN BIT(0)
+#define SUN8I_H3_GPADC_INTC 0x44
+
+#define SUN8I_H3_GPADC_INTC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12)
+#define SUN8I_H3_GPADC_INTC_TEMP_DATA BIT(8)
+#define SUN8I_H3_GPADC_INTC_TEMP_SHUT BIT(4)
+#define SUN8I_H3_GPADC_INTC_TEMP_ALARM BIT(0)
+
#define SUN4I_GPADC_INT_FIFOS 0x14
#define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING BIT(18)
@@ -80,9 +100,16 @@
#define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING BIT(1)
#define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING BIT(0)
+#define SUN8I_H3_GPADC_INTS 0x44
+
+#define SUN8I_H3_GPADC_INTS_TEMP_DATA BIT(8)
+#define SUN8I_H3_GPADC_INTS_TEMP_SHUT BIT(4)
+#define SUN8I_H3_GPADC_INTS_TEMP_ALARM BIT(0)
+
#define SUN4I_GPADC_CDAT 0x1c
#define SUN4I_GPADC_TEMP_DATA 0x20
#define SUN4I_GPADC_DATA 0x24
+#define SUN8I_H3_GPADC_TEMP_DATA 0x80
#define SUN4I_GPADC_IRQ_FIFO_DATA 0
#define SUN4I_GPADC_IRQ_TEMP_DATA 1
--
2.12.0
^ permalink raw reply related
* [RFC PATCH 1/3] dt-bindings: update the Allwinner GPADC device tree binding for H3
From: Icenowy Zheng @ 2017-03-28 17:30 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Jonathan Cameron, Zhang Rui, Quentin Schulz
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-iio-u79uwXL29TY76Z2rM5mHXA, linux-pm-u79uwXL29TY76Z2rM5mHXA,
Icenowy Zheng
In-Reply-To: <20170328173013.16539-1-icenowy-h8G6r0blFSE@public.gmane.org>
Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC) and added a pair of bus clock and reset.
Update the binding document to cover H3.
Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
.../devicetree/bindings/mfd/sun4i-gpadc.txt | 23 ++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
index badff3611a98..7753133ca0ff 100644
--- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
+++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
@@ -4,12 +4,20 @@ The Allwinner SoCs all have an ADC that can also act as a thermal sensor
and sometimes as a touchscreen controller.
Required properties:
- - compatible: "allwinner,sun8i-a33-ths",
+ - compatible: must contain one of the following compatibles:
+ - "allwinner,sun8i-a33-ths"
+ - "allwinner,sun8i-h3-ths"
- reg: mmio address range of the chip,
- #thermal-sensor-cells: shall be 0,
- #io-channel-cells: shall be 0,
-Example:
+Required properties for the following compatibles:
+ - "allwinner,sun8i-h3-ths"
+ - clocks: the bus clock and the input clock of the ADC,
+ - clock-names: should be "bus" and "ths",
+ - resets: the bus reset of the ADC,
+
+Example for A33:
ths: ths@01c25000 {
compatible = "allwinner,sun8i-a33-ths";
reg = <0x01c25000 0x100>;
@@ -17,6 +25,17 @@ Example:
#io-channel-cells = <0>;
};
+Example for H3:
+ ths: ths@01c25000 {
+ compatible = "allwinner,sun8i-h3-ths";
+ reg = <0x01c25000 0x100>;
+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+ clock-names = "bus", "ths";
+ resets = <&ccu RST_BUS_THS>;
+ #thermal-sensor-cells = <0>;
+ #io-channel-cells = <0>;
+ };
+
sun4i, sun5i and sun6i SoCs are also supported via the older binding:
sun4i resistive touchscreen controller
--
2.12.0
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^ permalink raw reply related
* [RFC PATCH 0/3] IIO-based thermal sensor driver for Allwinner H3 SoC
From: Icenowy Zheng @ 2017-03-28 17:30 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Jonathan Cameron, Zhang Rui, Quentin Schulz
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-iio-u79uwXL29TY76Z2rM5mHXA, linux-pm-u79uwXL29TY76Z2rM5mHXA,
Icenowy Zheng
Allwiner H3 SoC has a thermal sensor, which is a large refactored version of
the old Allwinner "GPADC" (although it have already only thermal part left
in A33).
This patch tried to add support for the sensor in H3 based on the A33
thermal sensor patchset by Quentin Schulz at [1].
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2017-March/495505.html
Icenowy Zheng (3):
dt-bindings: update the Allwinner GPADC device tree binding for H3
iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor
ARM: sun8i: h3: add support for the thermal sensor in H3
.../devicetree/bindings/mfd/sun4i-gpadc.txt | 23 +++-
arch/arm/boot/dts/sun8i-h3.dtsi | 26 +++++
drivers/iio/adc/sun4i-gpadc-iio.c | 130 ++++++++++++++++++---
include/linux/mfd/sun4i-gpadc.h | 33 +++++-
4 files changed, 188 insertions(+), 24 deletions(-)
--
2.12.0
--
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^ permalink raw reply
* Re: [PATCH 0/2] [kernel] ARM: lpc32xx: migrate CLCD config to device tree
From: Sylvain Lemieux @ 2017-03-28 17:28 UTC (permalink / raw)
To: vz-ChpfBGZJDbMAvxtiuMwx3w
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170308174638.25578-1-slemieux.tyco-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hi Vladimir,
On Wed, 2017-03-08 at 12:46 -0500, Sylvain Lemieux wrote:
> From: Sylvain Lemieux <slemieux-1xCVI8+nB4ZBDgjK7y7TUQ@public.gmane.org>
>
> Migrate the CLCD configurations to the device tree and
> remove custom functions from board files.
>
> This change depends on the following change:
> "video: ARM CLCD: fix dma allocation size"
> https://www.spinics.net/lists/arm-kernel/msg567178.html
>
> Note:
> * We tested a similar change on a custom LPC32xx board with a 480x272 LCD.
> * We did not test this change on hardware;
> we do not have access to a PHY3250 board with the 240x320 LCD.
>
> Liam Beguin (2):
> ARM: dts: lpc32xx: phy3250: add clcd configuration
> ARM: lpc32xx: drop CLCD configuration
>
> arch/arm/boot/dts/lpc3250-phy3250.dts | 35 ++++++++++++++++++
> arch/arm/mach-lpc32xx/phy3250.c | 70 -----------------------------------
> 2 files changed, 35 insertions(+), 70 deletions(-)
>
do you think you can look at this patchset?
Regards,
Sylvain
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^ permalink raw reply
* Re: [RESEND PATCH 1/3] dt: pwm: lpc32xx: add description of clocks and #pwm-cells properties
From: Sylvain Lemieux @ 2017-03-28 17:24 UTC (permalink / raw)
To: thierry.reding; +Cc: linux-pwm, devicetree, robh+dt, linux-arm-kernel, vz
In-Reply-To: <20170216202749.20653-2-slemieux.tyco@gmail.com>
ping
On Thu, 2017-02-16 at 15:27 -0500, slemieux.tyco@gmail.com wrote:
> From: Vladimir Zapolskiy <vz@mleia.com>
>
> NXP LPC32xx SoCs have two simple independent PWM controllers with a single
> output each, in this case there is no need to specify PWM channel argument
> on client side, one cell for setting PWM output frequency is sufficient.
>
> Another added to the description property 'clocks' has a standard meaning
> of a controller supply clock, in the LPC32xx User's Manual the clock is
> denoted as PWM1_CLK or PWM2_CLK clock.
>
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> Reviewed-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt b/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt
> index 74b5bc5dd19a..523d79662861 100644
> --- a/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt
> @@ -3,15 +3,22 @@ LPC32XX PWM controller
> Required properties:
> - compatible: should be "nxp,lpc3220-pwm"
> - reg: physical base address and length of the controller's registers
> +- clocks: clock phandle and clock specifier pair
> +- #pwm-cells: should be 1, the cell is used to specify the period in
> + nanoseconds.
>
> Examples:
>
> pwm@4005c000 {
> compatible = "nxp,lpc3220-pwm";
> reg = <0x4005c000 0x4>;
> + clocks = <&clk LPC32XX_CLK_PWM1>;
> + #pwm-cells = <1>;
> };
>
> pwm@4005c004 {
> compatible = "nxp,lpc3220-pwm";
> reg = <0x4005c004 0x4>;
> + clocks = <&clk LPC32XX_CLK_PWM2>;
> + #pwm-cells = <1>;
> };
^ permalink raw reply
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