* Re: [PATCH V3 0/5] iommu/arm-smmu: Add runtime pm/sleep support
From: Will Deacon @ 2017-04-03 17:23 UTC (permalink / raw)
To: Rob Clark
Cc: Sricharan R, Mark Rutland, devicetree@vger.kernel.org,
Mathieu Poirier, linux-arm-msm, Stephen Boyd,
iommu@lists.linux-foundation.org, Rob Herring, linux-clk,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <CAF6AEGv_1pNvhCc-mVP5S28Yt5kTJmTRfe8tKSJpEmxfOKM7Jg@mail.gmail.com>
On Fri, Mar 31, 2017 at 10:58:16PM -0400, Rob Clark wrote:
> On Fri, Mar 31, 2017 at 1:54 PM, Will Deacon <will.deacon@arm.com> wrote:
> > On Thu, Mar 09, 2017 at 09:05:43PM +0530, Sricharan R wrote:
> >> This series provides the support for turning on the arm-smmu's
> >> clocks/power domains using runtime pm. This is done using the
> >> recently introduced device links patches, which lets the symmu's
> >> runtime to follow the master's runtime pm, so the smmu remains
> >> powered only when the masters use it.
> >
> > Do you have any numbers for the power savings you achieve with this?
> > How often do we actually manage to stop the SMMU clocks on an SoC with
> > a handful of masters?
> >
> > In other words, is this too coarse-grained to be useful, or is it common
> > that all the devices upstream of the SMMU are suspended?
>
> well, if you think about a phone/tablet with a command mode panel,
> pretty much all devices will be suspended most of the time ;-)
Well, that's really what I was asking about. I assumed that periodic
modem/radio transactions would keep the SMMU clocked, so would like to get a
rough idea of the power savings achieved with this coarse-grained approach.
Will
^ permalink raw reply
* Re: [PATCH v5 1/2] Documentation: dt-bindings: Document bindings for Aspeed ADC
From: Rick Altherr @ 2017-04-03 17:17 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Joel Stanley, OpenBMC Maillist, Linux Kernel Mailing List,
devicetree, linux-iio, Hartmut Knaack, Rob Herring,
Lars-Peter Clausen, Mark Rutland, Peter Meerwald-Stadler
In-Reply-To: <968a3a78-49d3-138b-ef6e-7cee3c133471@kernel.org>
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On Sat, Apr 1, 2017 at 3:51 AM, Jonathan Cameron <jic23@kernel.org> wrote:
> On 29/03/17 03:33, Joel Stanley wrote:
> > On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr <raltherr@google.com>
> wrote:
> >> Signed-off-by: Rick Altherr <raltherr@google.com>
> >> ---
> >
> > Acked-by: Joel Stanley <joel@jms.id.au>
> I can't see why Rob would mind any of the changes made since he
> Acked this (and having acked it I doubt he is looking at newer versions!)
> so I'm going to take the view his Ack still applies.
>
> Applied to the togreg branch of iio.git which will get pushed out first
> as testing for the autobuilders to have a chance to play with it.
>
> Thanks,
>
> Jonathan
>
Thanks! I realized I forgot to include Acks when I sent out later
versions. I'll be more careful on that for future patches.
> >
> >>
> >> Changes in v5: None
> >> Changes in v4: None
> >> Changes in v3:
> >> - Consistently write hex contstants with lowercase letters
> >> - Drop model numbers from description as same IP is used in every
> generation
> >>
> >> Changes in v2:
> >> - Rewritten as an IIO ADC device
> >>
> >> .../devicetree/bindings/iio/adc/aspeed_adc.txt | 20
> ++++++++++++++++++++
> >> 1 file changed, 20 insertions(+)
> >> create mode 100644 Documentation/devicetree/
> bindings/iio/adc/aspeed_adc.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt
> b/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt
> >> new file mode 100644
> >> index 000000000000..674e133b7cd7
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt
> >> @@ -0,0 +1,20 @@
> >> +Aspeed ADC
> >> +
> >> +This device is a 10-bit converter for 16 voltage channels. All inputs
> are
> >> +single ended.
> >> +
> >> +Required properties:
> >> +- compatible: Should be "aspeed,ast2400-adc" or "aspeed,ast2500-adc"
> >> +- reg: memory window mapping address and length
> >> +- clocks: Input clock used to derive the sample clock. Expected to be
> the
> >> + SoC's APB clock.
> >> +- #io-channel-cells: Must be set to <1> to indicate channels are
> selected
> >> + by index.
> >> +
> >> +Example:
> >> + adc@1e6e9000 {
> >> + compatible = "aspeed,ast2400-adc";
> >> + reg = <0x1e6e9000 0xb0>;
> >> + clocks = <&clk_apb>;
> >> + #io-channel-cells = <1>;
> >> + };
> >> --
> >> 2.12.2.564.g063fe858b8-goog
> >>
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
> >
>
>
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^ permalink raw reply
* Re: [PATCH v7 06/13] dt: bindings: Add bindings for Marvell Xenon SD Host Controller
From: Hu Ziji @ 2017-04-03 17:07 UTC (permalink / raw)
To: Rob Herring, Gregory CLEMENT
Cc: Jimmy Xu, Andrew Lunn, Ulf Hansson, linux-mmc, Mike Turquette,
linux-kernel, Nadav Haklai, Victor Gu, Doug Jones, linux-clk,
Jisheng Zhang, Yehuda Yitschak, Marcin Wojtas, Kostya Porotchkin,
Hanna Hawa, Sebastian Hesselbarth, devicetree, Jason Cooper,
Ryan Gao, Wei(SOCP) Liu, linux-arm-kernel, Thomas Petazzoni,
Stephen Boyd, Adrian Hunter, Wilson Ding <dingwe>
In-Reply-To: <20170403161926.wfj7foddu33gxuae@rob-hp-laptop>
Hi Rob,
On 2017/4/4 0:19, Rob Herring wrote:
> ----------------------------------------------------------------------
> On Thu, Mar 30, 2017 at 05:22:58PM +0200, Gregory CLEMENT wrote:
>> From: Hu Ziji <huziji@marvell.com>
>>
>> Marvell Xenon SDHC can support eMMC/SD/SDIO.
>> Add Xenon-specific properties.
>> Also add properties for Xenon PHY setting.
>>
>> Signed-off-by: Hu Ziji <huziji@marvell.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>> ---
>> Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt | 170 +++++++-
>> 1 file changed, 170 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
>
> I acked v6 and it seems like a minor change, though I had to search for
> both because there is no revision history nor explanation why you didn't
> add my ack.
>
Sorry for missing your ACK.
I add a few but important comments on common Xenon power implementations
in the examples. It is recorded in the cover letter.
v6->v7:
- Add comments on vqmmc and vmmc in examples in dt binding doc.
I was a little unsure if we can still add your ACK after adding the comment.
We will add your ACK back if we have to release another version later.
Thank you.
Best regards,
Hu Ziji
> Acked-by: Rob Herring <robh@kernel.org>
>
^ permalink raw reply
* [PATCH v3 4/4] ARM: dts: sun7i: Add can0_pins_a pinctrl settings
From: Patrick Menschel @ 2017-04-03 17:00 UTC (permalink / raw)
To: robh+dt, mark.rutland, linux, maxime.ripard, wens, devicetree,
linux-arm-kernel, linux-kernel, linux-can
Cc: Patrick Menschel
In-Reply-To: <1491238814-4888-1-git-send-email-menschel.p@posteo.de>
The A20 SoC has an on-board CAN controller. This patch adds
the pinctrl settings for pins PH20 and PH21.
This patch is adapted from the description in
Documentation/devicetree/bindings/net/can/sun4i_can.txt
Signed-off-by: Patrick Menschel <menschel.p@posteo.de>
---
arch/arm/boot/dts/sun7i-a20.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index c637e10..8536caf 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -1096,6 +1096,11 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ can0_pins_a: can0@0 {
+ pins = "PH20","PH21";
+ function = "can";
+ };
+
clk_out_a_pins_a: clk_out_a@0 {
pins = "PI12";
function = "clk_out_a";
--
1.9.1
^ permalink raw reply related
* [PATCH v3 3/4] ARM: dts: sun7i: Add CAN node
From: Patrick Menschel @ 2017-04-03 17:00 UTC (permalink / raw)
To: robh+dt, mark.rutland, linux, maxime.ripard, wens, devicetree,
linux-arm-kernel, linux-kernel, linux-can
Cc: Patrick Menschel
In-Reply-To: <1491238814-4888-1-git-send-email-menschel.p@posteo.de>
The A20 SoC has an on-board CAN controller.
This patch adds the device node.
The CAN controller is inherited from the A10 SoC and uses the same driver.
This patch is adapted from the description in
Documentation/devicetree/bindings/net/can/sun4i_can.txt
Signed-off-by: Patrick Menschel <menschel.p@posteo.de>
---
arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 2db97fc..c637e10 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -1582,6 +1582,15 @@
#size-cells = <0>;
};
+ can0: can@01c2bc00 {
+ compatible = "allwinner,sun7i-a20-can",
+ "allwinner,sun4i-a10-can";
+ reg = <0x01c2bc00 0x400>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb1_gates 4>;
+ status = "disabled";
+ };
+
i2c4: i2c@01c2c000 {
compatible = "allwinner,sun7i-a20-i2c",
"allwinner,sun4i-a10-i2c";
--
1.9.1
^ permalink raw reply related
* [PATCH v3 2/4] ARM: dts: sun4i: Add can0_pins_a pinctrl settings
From: Patrick Menschel @ 2017-04-03 17:00 UTC (permalink / raw)
To: robh+dt, mark.rutland, linux, maxime.ripard, wens, devicetree,
linux-arm-kernel, linux-kernel, linux-can
Cc: Patrick Menschel
In-Reply-To: <1491238814-4888-1-git-send-email-menschel.p@posteo.de>
The A10 SoC has an on-board CAN controller. This patch adds the
pinctrl settings for pins PH20 and PH21.
This patch is adapted from the description in
Documentation/devicetree/bindings/net/can/sun4i_can.txt
Signed-off-by: Patrick Menschel <menschel.p@posteo.de>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 7c559e7..f7dced4 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -974,6 +974,11 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ can0_pins_a: can0@0 {
+ pins = "PH20","PH21";
+ function = "can";
+ };
+
emac_pins_a: emac0@0 {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
--
1.9.1
^ permalink raw reply related
* [PATCH v3 1/4] ARM: dts: sun4i: Add CAN node
From: Patrick Menschel @ 2017-04-03 17:00 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-I+IVW8TIWO2tmTQ+vhA3Yw,
maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, wens-jdAy2FN1RRM,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-can-u79uwXL29TY76Z2rM5mHXA
Cc: Patrick Menschel
In-Reply-To: <1491238814-4888-1-git-send-email-menschel.p-1KBjaw7Xf1+zQB+pC5nmwQ@public.gmane.org>
The A10 SoC has an on-board CAN controller.
This patch adds the device node.
This patch is adapted from the description in
Documentation/devicetree/bindings/net/can/sun4i_can.txt
Signed-off-by: Patrick Menschel <menschel.p-1KBjaw7Xf1+zQB+pC5nmwQ@public.gmane.org>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index ba20b48..7c559e7 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -1313,6 +1313,14 @@
#size-cells = <0>;
};
+ can0: can@01c2bc00 {
+ compatible = "allwinner,sun4i-a10-can";
+ reg = <0x01c2bc00 0x400>;
+ interrupts = <26>;
+ clocks = <&apb1_gates 4>;
+ status = "disabled";
+ };
+
ps20: ps2@01c2a000 {
compatible = "allwinner,sun4i-a10-ps2";
reg = <0x01c2a000 0x400>;
--
1.9.1
--
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^ permalink raw reply related
* [PATCH v3 0/4] ARM: dts: sunxi: Add CAN node and can0_pins_a pinctrl settings
From: Patrick Menschel @ 2017-04-03 17:00 UTC (permalink / raw)
To: robh+dt, mark.rutland, linux, maxime.ripard, wens, devicetree,
linux-arm-kernel, linux-kernel, linux-can
Cc: Patrick Menschel
The Allwinner A10/A20 SoCs have an on-board CAN (Controller Area Network)
controller. This patch adds the CAN core to the SoC's include files,
sun4i-a10.dtsi and sun7i-a20.dtsi.
On linux-can mailing list was a discussion about updating the device tree bindings
https://lkml.org/lkml/2015/9/17/220
but it did not progress past writing the documentation file.
Documentation/devicetree/bindings/net/can/sun4i_can.txt
The CAN controller can be enabled in a board specific dts file as
described in the documentation file or by using a device tree overlay.
I have tested the patch on a Banana Pi (A20 SoC) with mainline kernel 4.10.5.
History:
v3: added "allwinner,sun7i-a20-can" compatible to can0 device node contents,
make separate patches for device nodes and pinctrl settings
v2: changed can0_pins_a node contents to new generic binding method,
changed can0_pins_a node position by alphabetical order,
changed can0 device node position by rising physical address order
v1: initial
Patrick Menschel (4):
ARM: dts: sun4i: Add CAN node
ARM: dts: sun4i: Add can0_pins_a pinctrl settings
ARM: dts: sun7i: Add CAN node
ARM: dts: sun7i: Add can0_pins_a pinctrl settings
arch/arm/boot/dts/sun4i-a10.dtsi | 13 +++++++++++++
arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++
2 files changed, 27 insertions(+)
--
1.9.1
^ permalink raw reply
* Re: [PATCH v3] regulator: Add driver for voltage controlled regulators
From: Rob Herring @ 2017-04-03 16:59 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: Liam Girdwood, Mark Brown, Mark Rutland,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Douglas Anderson, Brian Norris
In-Reply-To: <20170331205035.126001-1-mka-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
On Fri, Mar 31, 2017 at 01:50:35PM -0700, Matthias Kaehlcke wrote:
> The output voltage of a voltage controlled regulator can be controlled
> through the voltage of another regulator. The current version of this
> driver assumes that the output voltage is a linear function of the control
> voltage.
>
> Signed-off-by: Matthias Kaehlcke <mka-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> ---
> Changes in v3:
> - Pre-calculate limits for OVP-safe downward transitions with a discrete
> control regulator
> - Use regulator_get_linear_step() and regulator_count_voltages() to
> determine if the control regulator is continuous or discrete
> - Changed some log messages to start with lowercase character for
> consistency
> - Misc formatting fixes
>
> Changes in v2:
> - Don't configure control regulator as supply
> - Added enable/disable ops to turn control regulator on/off
> - Use regulator_has_continuous_voltage_range() to determine if control
> regulator is continuous or discrete
> - Use regulator-min/max-microvolt as output voltage range
> - Updated and fixed example in DT bindings
> - Updated commit message
>
> .../devicetree/bindings/regulator/vctrl.txt | 50 ++
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> drivers/regulator/Kconfig | 7 +
> drivers/regulator/Makefile | 1 +
> drivers/regulator/vctrl-regulator.c | 553 +++++++++++++++++++++
> 4 files changed, 611 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/regulator/vctrl.txt
> create mode 100644 drivers/regulator/vctrl-regulator.c
--
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^ permalink raw reply
* Re: [PATCH v4 0/5] ARM: K2G: Add support for TI-SCI Generic PM Domains
From: santosh.shilimkar @ 2017-04-03 16:58 UTC (permalink / raw)
To: Dave Gerlach, Arnd Bergmann, Olof Johansson
Cc: Nishanth Menon, devicetree, Ulf Hansson, Sudeep Holla,
Kevin Hilman, Keerthy, linux-pm, Rafael J. Wysocki, linux-kernel,
Tero Kristo, Russell King, Rob Herring, Santosh Shilimkar,
linux-arm-kernel
In-Reply-To: <58CAD9F5.7030904@ti.com>
Hi Dave,
On 3/16/17 11:31 AM, Dave Gerlach wrote:
> Santosh,
> On 03/12/2017 12:02 PM, Rafael J. Wysocki wrote:
[...]
>>> I did not update the "power-domain" binding document because in regards to
>>> #power-domain-cells it already states "can be any value as specified by device
>>> tree binding documentation of particular provider" which I think already
>>> describes the change in patch 2.
>>
>> I'm assuming that this will go in through the arm-soc tree.
>
> Assuming that Rob is OK with the v5 of patch 3 that I just sent in response to
> the v4 patch email, can this series go through you? We should be good to go with
> v4 of the series + the small v5 update to patch 3 if Rob is ok with it.
>
Yes I can queue this up for arm-soc. Please repost the v5 with all the
patches and acks.
Hi Arnd, Olof,
Is it ok to send this as a single pull request ? Am asking since it
is touching few topics which goes via different heads.
------------------------
Dave Gerlach (5):
PM / Domains: Add generic data pointer to genpd data struct
PM / Domains: Do not check if simple providers have phandle cells
dt-bindings: Add TI SCI PM Domains
soc: ti: Add ti_sci_pm_domains driver
ARM: keystone: Drop PM domain support for k2g
.../devicetree/bindings/soc/ti/sci-pm-domain.txt | 59 ++++++
MAINTAINERS | 3 +
arch/arm/mach-keystone/Kconfig | 1 +
arch/arm/mach-keystone/pm_domain.c | 4 +-
drivers/base/power/domain.c | 2 -
drivers/soc/ti/Kconfig | 12 ++
drivers/soc/ti/Makefile | 1 +
drivers/soc/ti/ti_sci_pm_domains.c | 202
+++++++++++++++++++++
include/dt-bindings/genpd/k2g.h | 90 +++++++++
include/linux/pm_domain.h | 1 +
10 files changed, 372 insertions(+), 3 deletions(-)
create mode 100644
Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
create mode 100644 drivers/soc/ti/ti_sci_pm_domains.c
create mode 100644 include/dt-bindings/genpd/k2g.h
regards,
Santosh
^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: Document the STM32 QSPI bindings
From: Rob Herring @ 2017-04-03 16:57 UTC (permalink / raw)
To: Ludovic Barre
Cc: Cyrille Pitchen, Marek Vasut, David Woodhouse, Brian Norris,
Boris Brezillon, Richard Weinberger, Alexandre Torgue, linux-mtd,
linux-kernel, devicetree
In-Reply-To: <1490979724-10905-2-git-send-email-ludovic.Barre@st.com>
On Fri, Mar 31, 2017 at 07:02:03PM +0200, Ludovic Barre wrote:
> From: Ludovic Barre <ludovic.barre@st.com>
>
> This patch adds documentation of device tree bindings for the STM32
> QSPI controller.
>
> Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
> ---
> .../devicetree/bindings/mtd/stm32-quadspi.txt | 45 ++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/stm32-quadspi.txt
>
> diff --git a/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt
> new file mode 100644
> index 0000000..95a8ebd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt
> @@ -0,0 +1,45 @@
> +* STMicroelectronics Quad Serial Peripheral Interface(QuadSPI)
> +
> +Required properties:
> +- compatible: should be "st,stm32f469-qspi"
> +- reg: contains the register location and length.
> + (optional) the memory mapping address and length
Why optional? Either the h/w has it or doesn't. If some chips don't,
they should have a different compatible string.
> +- reg-names: list of the names corresponding to the previous register
> + Should contain "qspi" to register location
> + (optional) "qspi_mm" if read in memory map mode (improve read throughput)
> +- interrupts: should contain the interrupt for the device
> +- clocks: the phandle of the clock needed by the QSPI controller
> +- A pinctrl must be defined to set pins in mode of operation for QSPI transfer
> +
> +Optional properties:
> +- resets: must contain the phandle to the reset controller.
> +
> +A spi flash must be a child of the nor_flash node and could have some
> +properties. Also see jedec,spi-nor.txt.
> +
> +Required properties:
> +- reg: chip-Select number (QSPI controller may connect 2 nor flashes)
> +- spi-max-frequency: max frequency of spi bus
> +
> +Optional property:
> +- spi-rx-bus-width: the bus width (number of data wires)
Just "see ../spi/spi-bus.txt" for the description
> +
> +Example:
> +
> +qspi: qspi@a0001000 {
spi@...
> + compatible = "st,stm32f469-qspi";
> + reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
> + reg-names = "qspi", "qspi_mm";
> + interrupts = <91>;
> + resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
> + clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_qspi0>;
> +
> + flash@0 {
> + reg = <0>;
> + spi-rx-bus-width = <4>;
> + spi-max-frequency = <108000000>;
> + ...
> + };
> +};
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH v3 2/4] dt-binding: meson_uart: add documentation for the UARTs of amlogic
From: Rob Herring @ 2017-04-03 16:52 UTC (permalink / raw)
To: Helmut Klein
Cc: mark.rutland, devicetree, linux-amlogic, linux-arm-kernel,
linux-kernel
In-Reply-To: <20170331165437.26227-3-hgkr.klein@gmail.com>
On Fri, Mar 31, 2017 at 06:54:35PM +0200, Helmut Klein wrote:
> Add the documentation for the device tree binding of meson_uart
>
> Signed-off-by: Helmut Klein <hgkr.klein@gmail.com>
> ---
> .../bindings/serial/amlogic,meson_uart.txt | 30 ++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/serial/amlogic,meson_uart.txt
>
> diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson_uart.txt b/Documentation/devicetree/bindings/serial/amlogic,meson_uart.txt
> new file mode 100644
> index 000000000000..8250a191c2fc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/amlogic,meson_uart.txt
> @@ -0,0 +1,30 @@
> +* Amlogic Meson UART, used in multiple SoCs (e.g. S905, s905X, ...)
> +
> +Required properties:
> +- compatible : "amlogic,meson-uart"
Should have SoC specific compatible strings in addition.
> +- reg : offset and length of the register set for the device.
> +- interrupts : device interrupt
> +- clocks : a list of phandle + clock-specifier pairs, one for each
> + entry in clock names.
> +- clocks-names : contains:
> + * "xtal" for the baud rate clock
> + * "core" for the core clock of none AO UARTs (optional)
> +
> +e.g.
> +uart_A: serial@84c0 {
> + compatible = "amlogic,meson-uart";
> + reg = <0x0 0x84c0 0x0 0x14>;
> + pinctrl-0 = <&uart_a_pins &uart_a_cts_rts_pins>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&xtal>, <&clkc CLKID_UART0>;
> + clock-names = "xtal", "core";
> + status = "ok";
Drop status from examples.
> +};
> +
> +Note: Each port should have an alias correctly numbered in "aliases" node.
True for pretty much any uart, so you can drop this.
> +
> +e.g.
> +aliases {
> + serial0 = &uart_AO;
> + serial1 = &uart_A;
> +};
> --
> 2.11.0
>
^ permalink raw reply
* Re: [PATCH 4/4] dt-bindings: input: Add Atmel PTC subsystem bindings
From: Rob Herring @ 2017-04-03 16:50 UTC (permalink / raw)
To: Ludovic Desroches
Cc: linux-input-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
dmitry.torokhov-Re5JQEeQqe8AvxtiuMwx3w,
nicolas.ferre-UWL1GkI3JZL3oGB3hsPCZA,
alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170331152250.12758-5-ludovic.desroches-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
On Fri, Mar 31, 2017 at 05:22:50PM +0200, Ludovic Desroches wrote:
> Add description of the Atmel PTC subsystem bindings.
>
> Signed-off-by: Ludovic Desroches <ludovic.desroches-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
> ---
> .../devicetree/bindings/input/atmel,ptc.txt | 67 ++++++++++++++++++++++
> 1 file changed, 67 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/input/atmel,ptc.txt
Other than the patch order,
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [RESEND PATCH v3 6/7] DT bindings documentation for Broadcom IPROC USB Device controller.
From: Rob Herring @ 2017-04-03 16:47 UTC (permalink / raw)
To: Raviteja Garimella
Cc: Mark Rutland, Greg Kroah-Hartman, Felipe Balbi, devicetree,
linux-kernel, bcm-kernel-feedback-list, linux-usb
In-Reply-To: <1490965753-3511-6-git-send-email-raviteja.garimella@broadcom.com>
On Fri, Mar 31, 2017 at 06:39:12PM +0530, Raviteja Garimella wrote:
> The device node is used for UDCs integrated into Broadcom's
> iProc family of SoCs'. The UDC is based on Synopsys Designware
> Cores AHB Subsystem USB Device Controller IP.
>
> Signed-off-by: Raviteja Garimella <raviteja.garimella@broadcom.com>
> ---
> Documentation/devicetree/bindings/usb/iproc-udc.txt | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/iproc-udc.txt
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: iio: stm32-adc: add option to set resolution
From: Rob Herring @ 2017-04-03 16:46 UTC (permalink / raw)
To: Fabrice Gasnier
Cc: jic23-DgEjT+Ai2ygdnm+yROfE0A, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-iio-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w,
alexandre.torgue-qxv4g6HH51o, lars-Qo5EllUWu/uELgA04lAiVw,
knaack.h-Mmb7MZpHnFY, pmeerw-jW+XmwGofnusTnJN9+BGXg,
benjamin.gaignard-QSEj5FYQhm4dnm+yROfE0A,
benjamin.gaignard-qxv4g6HH51o,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <1490963559-32159-2-git-send-email-fabrice.gasnier-qxv4g6HH51o@public.gmane.org>
On Fri, Mar 31, 2017 at 02:32:37PM +0200, Fabrice Gasnier wrote:
> Add documentation for 'assigned-resolution-bits' dt optional property.
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier-qxv4g6HH51o@public.gmane.org>
> ---
> Changes in v2:
> - rename property from 'st,adc-res' to 'assigned-resolution-bits' so it
> is more common.
> ---
> Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt | 4 ++++
> 1 file changed, 4 insertions(+)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply
* Re: [PATCH 0/2] ARM: dts: keystone: Add support for new K2G evm
From: santosh.shilimkar-QHcLZuEGTsvQT0dZR+AlfA @ 2017-04-03 16:44 UTC (permalink / raw)
To: Franklin S Cooper Jr, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, ssantosh-DgEjT+Ai2ygdnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170330152907.12595-1-fcooper-l0cyMroinI0@public.gmane.org>
Hi Franklin,
On 3/30/17 8:29 AM, Franklin S Cooper Jr wrote:
> This patchset adds support for new K2G Industrial Communication Engine
> evm. For now only a bare minimal dts which will allow ram boot. Additional
> peripherals will be added when base K2G SoC patches are upstreamed allowing
> peripherals to be enabled.
>
> ARM: keystone: Create new binding for K2G ICE evm
> ARM: dts: keystone: Add minimum support for K2G ICE evm
>
Can you clarify Rob's comment on second patch and re-post the updated
patch with his ack if you agree ? Will apply the series.
Regards,
Santosh
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^ permalink raw reply
* [PATCH 2/2] power: tps65217_charger: Add properties like voltage and current charge
From: Enric Balletbo i Serra @ 2017-04-03 16:44 UTC (permalink / raw)
To: Sebastian Reichel, Rob Herring, Lee Jones
Cc: linux-pm, devicetree, linux-kernel
In-Reply-To: <20170403164446.28076-1-enric.balletbo@collabora.com>
Allow the possibility to configure the charge and the current voltage of
the charger and also the NTC type for battery temperature measurement.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
.../bindings/power/supply/tps65217_charger.txt | 15 ++
drivers/power/supply/tps65217_charger.c | 187 +++++++++++++++++++--
include/linux/mfd/tps65217.h | 2 +
3 files changed, 192 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/power/supply/tps65217_charger.txt b/Documentation/devicetree/bindings/power/supply/tps65217_charger.txt
index a11072c..600da6e 100644
--- a/Documentation/devicetree/bindings/power/supply/tps65217_charger.txt
+++ b/Documentation/devicetree/bindings/power/supply/tps65217_charger.txt
@@ -6,6 +6,18 @@ Required Properties:
Should be <0> for the USB charger and <1> for the AC adapter.
-interrupt-names: Should be "USB" and "AC"
+Optional properties:
+-ti,charge-voltage-uvolt: set the charge voltage. The value can be: 4100000,
+ 4150000, 4200000, 4250000; default: 4100000
+
+-ti,charge-current-uamp: set the charging current. The value can be: 300000,
+ 400000, 500000, 700000; default: 500000
+
+-ti,ntc-type: set the NTC type for battery temperature measurement. The value
+ must be 0 or 1, where:
+ 0 – 100k (curve 1, B = 3960)
+ 1 – 10k (curve 2, B = 3480) (default)
+
This node is a subnode of the tps65217 PMIC.
Example:
@@ -14,4 +26,7 @@ Example:
compatible = "ti,tps65217-charger";
interrupts = <0>, <1>;
interrupt-names = "USB", "AC";
+ ti,charge-voltage-uvolt = <4100000>;
+ ti,charge-current-uamp = <500000>;
+ ti,ntc-type = <1>;
};
diff --git a/drivers/power/supply/tps65217_charger.c b/drivers/power/supply/tps65217_charger.c
index 1f52340..1d7055d 100644
--- a/drivers/power/supply/tps65217_charger.c
+++ b/drivers/power/supply/tps65217_charger.c
@@ -39,6 +39,12 @@
#define NUM_CHARGER_IRQS 2
#define POLL_INTERVAL (HZ * 2)
+struct tps65217_charger_platform_data {
+ u32 charge_current_uamp;
+ u32 charge_voltage_uvolt;
+ int ntc_type;
+};
+
struct tps65217_charger {
struct tps65217 *tps;
struct device *dev;
@@ -48,16 +54,82 @@ struct tps65217_charger {
int prev_online;
struct task_struct *poll_task;
+ struct tps65217_charger_platform_data *pdata;
};
static enum power_supply_property tps65217_charger_props[] = {
POWER_SUPPLY_PROP_ONLINE,
};
-static int tps65217_config_charger(struct tps65217_charger *charger)
+static int tps65217_set_charge_current(struct tps65217_charger *charger,
+ unsigned int uamp)
+{
+ int ret, val;
+
+ dev_dbg(charger->dev, "setting charge current to %d uA\n", uamp);
+
+ if (uamp == 300000)
+ val = 0x00;
+ else if (uamp == 400000)
+ val = 0x01;
+ else if (uamp == 500000)
+ val = 0x02;
+ else if (uamp == 700000)
+ val = 0x03;
+ else
+ return -EINVAL;
+
+ ret = tps65217_set_bits(charger->tps, TPS65217_REG_CHGCONFIG3,
+ TPS65217_CHGCONFIG3_ICHRG_MASK,
+ val << TPS65217_CHGCONFIG3_ICHRG_SHIFT,
+ TPS65217_PROTECT_NONE);
+ if (ret) {
+ dev_err(charger->dev,
+ "failed to set ICHRG setting to 0x%02x (err: %d)\n",
+ val, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int tps65217_set_charge_voltage(struct tps65217_charger *charger,
+ unsigned int uvolt)
+{
+ int ret, val;
+
+ dev_dbg(charger->dev, "setting charge voltage to %d uV\n", uvolt);
+
+ if (uvolt != 4100000 && uvolt != 4150000 &&
+ uvolt != 4200000 && uvolt != 4250000)
+ return -EINVAL;
+
+ val = (uvolt - 4100000) / 50000;
+
+ ret = tps65217_set_bits(charger->tps, TPS65217_REG_CHGCONFIG2,
+ TPS65217_CHGCONFIG2_VOREG_MASK,
+ val << TPS65217_CHGCONFIG2_VOREG_SHIFT,
+ TPS65217_PROTECT_NONE);
+ if (ret) {
+ dev_err(charger->dev,
+ "failed to set VOCHG setting to 0x%02x (err: %d)\n",
+ val, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int tps65217_set_ntc_type(struct tps65217_charger *charger,
+ unsigned int ntc)
{
int ret;
+ dev_dbg(charger->dev, "setting NTC type to %d\n", ntc);
+
+ if (ntc != 0 && ntc != 1)
+ return -EINVAL;
+
/*
* tps65217 rev. G, p. 31 (see p. 32 for NTC schematic)
*
@@ -74,14 +146,57 @@ static int tps65217_config_charger(struct tps65217_charger *charger)
* NTC TYPE (for battery temperature measurement)
* 0 – 100k (curve 1, B = 3960)
* 1 – 10k (curve 2, B = 3480) (default on reset)
- *
*/
- ret = tps65217_clear_bits(charger->tps, TPS65217_REG_CHGCONFIG1,
- TPS65217_CHGCONFIG1_NTC_TYPE,
- TPS65217_PROTECT_NONE);
+ if (ntc) {
+ ret = tps65217_set_bits(charger->tps, TPS65217_REG_CHGCONFIG1,
+ TPS65217_CHGCONFIG1_NTC_TYPE,
+ TPS65217_CHGCONFIG1_NTC_TYPE,
+ TPS65217_PROTECT_NONE);
+ if (ret) {
+ dev_err(charger->dev,
+ "failed to set NTC type to 10K: %d\n", ret);
+ return ret;
+ }
+ } else {
+ ret = tps65217_clear_bits(charger->tps, TPS65217_REG_CHGCONFIG1,
+ TPS65217_CHGCONFIG1_NTC_TYPE,
+ TPS65217_PROTECT_NONE);
+ if (ret) {
+ dev_err(charger->dev,
+ "failed to set NTC type to 100K: %d\n", ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int tps65217_config_charger(struct tps65217_charger *charger)
+{
+ int ret;
+ struct tps65217_charger_platform_data *pdata = charger->pdata;
+
+ if (!charger->pdata)
+ return -EINVAL;
+
+ ret = tps65217_set_charge_voltage(charger, pdata->charge_voltage_uvolt);
if (ret) {
dev_err(charger->dev,
- "failed to set 100k NTC setting: %d\n", ret);
+ "failed to set charge voltage setting: %d\n", ret);
+ return ret;
+ }
+
+ ret = tps65217_set_charge_current(charger, pdata->charge_current_uamp);
+ if (ret) {
+ dev_err(charger->dev,
+ "failed to set charge current setting: %d\n", ret);
+ return ret;
+ }
+
+ ret = tps65217_set_ntc_type(charger, pdata->ntc_type);
+ if (ret) {
+ dev_err(charger->dev,
+ "failed to set NTC type setting: %d\n", ret);
return ret;
}
@@ -185,6 +300,48 @@ static int tps65217_charger_poll_task(void *data)
return 0;
}
+#ifdef CONFIG_OF
+static struct tps65217_charger_platform_data *tps65217_charger_pdata_init(
+ struct platform_device *pdev)
+{
+ struct tps65217_charger_platform_data *pdata;
+ struct device_node *np = pdev->dev.of_node;
+ int ret;
+
+ if (!np) {
+ dev_err(&pdev->dev, "No charger OF node\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return ERR_PTR(-ENOMEM);
+
+ ret = of_property_read_u32(np, "ti,charge-voltage-uvolt",
+ &pdata->charge_voltage_uvolt);
+ if (ret)
+ pdata->charge_voltage_uvolt = 4100000;
+
+ ret = of_property_read_u32(np, "ti,charge-current-uamp",
+ &pdata->charge_current_uamp);
+ if (ret)
+ pdata->charge_current_uamp = 500000;
+
+ ret = of_property_read_u32(np, "ti,ntc-type",
+ &pdata->ntc_type);
+ if (ret)
+ pdata->ntc_type = 1; /* 10k (curve 2, B = 3480) */
+
+ return pdata;
+}
+#else /* CONFIG_OF */
+static struct tps65217_charger_platform_data *tps65217_charger_pdata_init(
+ struct platform_device *pdev)
+{
+ return NULL;
+}
+#endif /* CONFIG_OF */
+
static const struct power_supply_desc tps65217_charger_desc = {
.name = "tps65217-charger",
.type = POWER_SUPPLY_TYPE_MAINS,
@@ -214,6 +371,18 @@ static int tps65217_charger_probe(struct platform_device *pdev)
cfg.of_node = pdev->dev.of_node;
cfg.drv_data = charger;
+ charger->pdata = tps65217_charger_pdata_init(pdev);
+ if (IS_ERR(charger->pdata)) {
+ dev_err(charger->dev, "failed: getting platform data\n");
+ return PTR_ERR(charger->pdata);
+ }
+
+ ret = tps65217_config_charger(charger);
+ if (ret < 0) {
+ dev_err(charger->dev, "charger config failed, err %d\n", ret);
+ return ret;
+ }
+
charger->psy = devm_power_supply_register(&pdev->dev,
&tps65217_charger_desc,
&cfg);
@@ -225,12 +394,6 @@ static int tps65217_charger_probe(struct platform_device *pdev)
irq[0] = platform_get_irq_byname(pdev, "USB");
irq[1] = platform_get_irq_byname(pdev, "AC");
- ret = tps65217_config_charger(charger);
- if (ret < 0) {
- dev_err(charger->dev, "charger config failed, err %d\n", ret);
- return ret;
- }
-
/* Create a polling thread if an interrupt is invalid */
if (irq[0] < 0 || irq[1] < 0) {
poll_task = kthread_run(tps65217_charger_poll_task,
diff --git a/include/linux/mfd/tps65217.h b/include/linux/mfd/tps65217.h
index eac2857..d040062 100644
--- a/include/linux/mfd/tps65217.h
+++ b/include/linux/mfd/tps65217.h
@@ -103,8 +103,10 @@
#define TPS65217_CHGCONFIG2_DYNTMR BIT(7)
#define TPS65217_CHGCONFIG2_VPREGHG BIT(6)
#define TPS65217_CHGCONFIG2_VOREG_MASK 0x30
+#define TPS65217_CHGCONFIG2_VOREG_SHIFT 4
#define TPS65217_CHGCONFIG3_ICHRG_MASK 0xC0
+#define TPS65217_CHGCONFIG3_ICHRG_SHIFT 6
#define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30
#define TPS65217_CHGCONFIG2_PCHRGT BIT(3)
#define TPS65217_CHGCONFIG2_TERMIF 0x06
--
2.9.3
^ permalink raw reply related
* [PATCH 1/2] power: supply: tps65217: remove debug messages for function calls
From: Enric Balletbo i Serra @ 2017-04-03 16:44 UTC (permalink / raw)
To: Sebastian Reichel, Rob Herring, Lee Jones
Cc: linux-pm, devicetree, linux-kernel
Equivalent information can be nowadays obtained using function tracer.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
drivers/power/supply/tps65217_charger.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/power/supply/tps65217_charger.c b/drivers/power/supply/tps65217_charger.c
index 29b61e8..1f52340 100644
--- a/drivers/power/supply/tps65217_charger.c
+++ b/drivers/power/supply/tps65217_charger.c
@@ -58,8 +58,6 @@ static int tps65217_config_charger(struct tps65217_charger *charger)
{
int ret;
- dev_dbg(charger->dev, "%s\n", __func__);
-
/*
* tps65217 rev. G, p. 31 (see p. 32 for NTC schematic)
*
@@ -205,8 +203,6 @@ static int tps65217_charger_probe(struct platform_device *pdev)
int ret;
int i;
- dev_dbg(&pdev->dev, "%s\n", __func__);
-
charger = devm_kzalloc(&pdev->dev, sizeof(*charger), GFP_KERNEL);
if (!charger)
return -ENOMEM;
--
2.9.3
^ permalink raw reply related
* Re: [PATCHv6 05/10] s5p-cec.txt: document the HDMI controller phandle
From: Rob Herring @ 2017-04-03 16:43 UTC (permalink / raw)
To: Hans Verkuil
Cc: devicetree, linux-samsung-soc, Patrice.chotard,
Krzysztof Kozlowski, Russell King, Javier Martinez Canillas,
Hans Verkuil, dri-devel, Daniel Vetter, Marek Szyprowski,
linux-media
In-Reply-To: <20170331122036.55706-6-hverkuil@xs4all.nl>
On Fri, Mar 31, 2017 at 02:20:31PM +0200, Hans Verkuil wrote:
> From: Hans Verkuil <hans.verkuil@cisco.com>
>
> Update the bindings documenting the new hdmi phandle.
>
> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> CC: linux-samsung-soc@vger.kernel.org
> CC: devicetree@vger.kernel.org
> ---
> Documentation/devicetree/bindings/media/s5p-cec.txt | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
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* Re: [PATCH 1/4] dt-bindings: iio: stm32-dac: Add support for STM32 DAC
From: Rob Herring @ 2017-04-03 16:42 UTC (permalink / raw)
To: Fabrice Gasnier
Cc: jic23-DgEjT+Ai2ygdnm+yROfE0A, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-iio-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w,
alexandre.torgue-qxv4g6HH51o, lars-Qo5EllUWu/uELgA04lAiVw,
knaack.h-Mmb7MZpHnFY, pmeerw-jW+XmwGofnusTnJN9+BGXg,
benjamin.gaignard-QSEj5FYQhm4dnm+yROfE0A,
benjamin.gaignard-qxv4g6HH51o,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A, amelie.delaunay-qxv4g6HH51o
In-Reply-To: <1490960707-22422-2-git-send-email-fabrice.gasnier-qxv4g6HH51o@public.gmane.org>
On Fri, Mar 31, 2017 at 01:45:04PM +0200, Fabrice Gasnier wrote:
> Document STMicroelectronics STM32 DAC (digital-to-analog converter).
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier-qxv4g6HH51o@public.gmane.org>
> ---
> .../devicetree/bindings/iio/dac/st,stm32-dac.txt | 56 ++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/dac/st,stm32-dac.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.txt b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.txt
> new file mode 100644
> index 0000000..1981983
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.txt
> @@ -0,0 +1,56 @@
> +STMicroelectronics STM32 DAC
> +
> +The STM32 DAC is a 12-bit voltage output digital-to-analog converter. The DAC
> +can be configured in 8- or 12-bit mode. In 12-bit mode, the data could be
> +left- or right-aligned. It has two output channels, each with its own converter.
> +It has built-in noise and triangle waveform generator and supports external
> +triggers for conversions. The DAC's output buffer allows a high drive output
> +current.
> +
> +Contents of a stm32 dac root node:
> +-----------------------------------
> +Required properties:
> +- compatible: Must be "st,stm32h7-dac-core".
> +- reg: Offset and length of the device's register set.
> +- clocks: Must contain an entry for pclk (which feeds the peripheral bus
> + interface)
> +- clock-names: Must be "pclk".
> +- vref-supply: Phandle to the vref+ input analog reference supply.
> +
> +Optional properties:
> +- resets: Must contain the phandle to the reset controller.
> +- A pinctrl state named "default" for each DAC channel may be defined to set
> + DAC_OUTx pin in mode of operation for analog output on external pin.
> +
> +Contents of a stm32 dac child node:
> +-----------------------------------
> +DAC core node should contain at least one subnode, representing a
> +DAC instance/channel available on the machine.
> +
> +Required properties:
> +- compatible: Must be "st,stm32-dac".
> +- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in
> + Documentation/devicetree/bindings/iio/iio-bindings.txt
> +- st,dac-channel: Must be either 1 or 2, to define channel in use (e.g.
> + single channels: 1 or 2)
Use "reg" instead.
> +
> +Example:
> + dac: dac@40007400 {
> + compatible = "st,stm32h7-dac-core";
> + reg = <0x40007400 0x400>;
> + clocks = <&clk>;
> + clock-names = "pclk";
> + vref-supply = <®_vref>;
> +
> + dac1: dac@1 {
> + compatible = "st,stm32-dac";
> + #io-channels-cells = <1>;
> + st,dac-channel = <1>;
> + };
> +
> + dac2: dac@2 {
> + compatible = "st,stm32-dac";
> + #io-channels-cells = <1>;
> + st,dac-channel = <2>;
> + };
> + };
> --
> 1.9.1
>
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* Re: [PATCH V3 1/3] dt-bindings: mtd: document linux,part-probe property
From: Rob Herring @ 2017-04-03 16:40 UTC (permalink / raw)
To: Rafał Miłecki
Cc: David Woodhouse, Brian Norris, Boris Brezillon, Marek Vasut,
Richard Weinberger, Cyrille Pitchen, Mark Rutland, Frank Rowand,
Linus Walleij, linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rafał Miłecki
In-Reply-To: <20170331114016.26858-1-zajec5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Fri, Mar 31, 2017 at 01:40:14PM +0200, Rafał Miłecki wrote:
> From: Rafał Miłecki <rafal-g1n6cQUeyibVItvQsEIGlw@public.gmane.org>
>
> Support for this property has been introduced in 2010 with commit
> 9d5da3a9b849 ("mtd: extend physmap_of to let the device tree specify the
> parition probe") but it was never documented. Fix this by adding a
> proper description and example.
>
> Signed-off-by: Rafał Miłecki <rafal-g1n6cQUeyibVItvQsEIGlw@public.gmane.org>
> ---
> Documentation/devicetree/bindings/mtd/common.txt | 7 +++++++
> 1 file changed, 7 insertions(+)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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* Re: [PATCH 2/3] dt-bindings: arm: amlogic: Add SoC information bindings
From: Rob Herring @ 2017-04-03 16:34 UTC (permalink / raw)
To: Neil Armstrong
Cc: Arnd Bergmann, Kevin Hilman, carlo-KA+7E9HrN00dnm+yROfE0A,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Linux ARM,
Linux Kernel Mailing List, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <4ab7d4ee-e805-69f1-b76b-b827b46285bd-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
On Fri, Mar 31, 2017 at 04:10:30PM +0200, Neil Armstrong wrote:
> On 03/31/2017 03:44 PM, Arnd Bergmann wrote:
> > On Fri, Mar 31, 2017 at 10:47 AM, Neil Armstrong
> > <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> wrote:
> >> Add bindings for the SoC information register of the Amlogic SoCs.
> >>
> >> Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> >> ---
> >> Documentation/devicetree/bindings/arm/amlogic.txt | 20 ++++++++++++++++++++
> >> 1 file changed, 20 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
> >> index bfd5b55..b850985 100644
> >> --- a/Documentation/devicetree/bindings/arm/amlogic.txt
> >> +++ b/Documentation/devicetree/bindings/arm/amlogic.txt
> >> @@ -52,3 +52,23 @@ Board compatible values:
> >> - "amlogic,q201" (Meson gxm s912)
> >> - "nexbox,a95x" (Meson gxbb or Meson gxl s905x)
> >> - "nexbox,a1" (Meson gxm s912)
> >> +
> >> +Amlogic Meson GX SoCs Information
> >> +----------------------------------
> >> +
> >> +The Meson SoCs have a Product Register that allows to retrieve SoC type,
> >> +package and revision information. If present, a device node for this register
> >> +should be added.
> >> +
> >> +Required properties:
> >> + - compatible: For Meson GX SoCs, must be "amlogic,meson-gx-socinfo".
> >> + - reg: Base address and length of the register block.
> >> +
> >> +Examples
> >> +--------
> >> +
> >> + chipid@220 {
> >> + compatible = "amlogic,meson-gx-socinfo";
> >> + reg = <0x0 0x00220 0x0 0x4>;
> >> + };
> >> +
> >
> > The register location would hint that this is in the middle of some block of
> > random registers, i.e. a syscon or some unrelated device.
> >
> > Are you sure that "socinfo" is the actual name of the IP block and that
> > it only has a single 32-bit register?
> >
> > Arnd
> >
>
> Hi Arnd,
>
> I'm sorry I did not find any relevant registers in the docs or source code describing
> it in a specific block of registers, and no close enough register definitions either.
> They may be used by the secure firmware I imagine.
>
> For the register name, Amlogic refers it to "cpu_version" in their code, but it really
> gives some details on the whole SoC and package, and socinfo seems better.
A register at address 0x220 seems a bit strange (unless there's ranges
you're not showing), but ROM code at this address would be fairly
typical. And putting version information into the ROM is also common.
Rob
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^ permalink raw reply
* Re: [PATCH v4] ASoC: Add support for Maxim Integrated MAX98927 Amplifier
From: Rob Herring @ 2017-04-03 16:30 UTC (permalink / raw)
To: Ryan Lee
Cc: lgirdwood, broonie, mark.rutland, perex, tiwai,
kuninori.morimoto.gx, arnd, ckeepax, lars, bardliao, nh6z, KCHSU0,
axel.lin, romain.perier, srinivas.kandagatla, oder_chiou,
Paul.Handrigan, alsa-devel, devicetree, linux-kernel, dgreid,
ryan.lee.maxim
In-Reply-To: <1490922994-19294-1-git-send-email-ryans.lee@maximintegrated.com>
On Fri, Mar 31, 2017 at 10:16:34AM +0900, Ryan Lee wrote:
> Signed-off-by: Ryan Lee <ryans.lee@maximintegrated.com>
> ---
>
> Changes since v4:
> * Removed support for SND_SOC_DAIFMT_CBS_CFM.
> * Fixed coding style for indention.
> * Removed variables if it has only one user.
> * Assigned ch_size directly.
> * Removed oring.
> * Put the return false in the switch statement.
> * Removed 'Monomix Output' and 'Speaker Source' controls.
> * Modified control names per control-names.rst.
> * Moved Revision ID check code to i2c_probe function.
> * Added 'Current Limit' control.
> * Removed 'devm__kfree' function.
>
> Changes since v3:
> * Combined MAX98926 and MAX98927 binding. Kept existing property name.
This looks fine, but:
> Changes since v2:
> * Removed local register read/write function to avoid duplication of ASoC core function.
>
> .../devicetree/bindings/sound/max98925.txt | 22 -
> .../devicetree/bindings/sound/max98926.txt | 32 -
> .../devicetree/bindings/sound/max9892x.txt | 41 +
> sound/soc/codecs/Kconfig | 5 +
> sound/soc/codecs/Makefile | 2 +
> sound/soc/codecs/max98927.c | 841 +++++++++++++++++++++
> sound/soc/codecs/max98927.h | 272 +++++++
> 7 files changed, 1161 insertions(+), 54 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/sound/max98925.txt
> delete mode 100644 Documentation/devicetree/bindings/sound/max98926.txt
> create mode 100755 Documentation/devicetree/bindings/sound/max9892x.txt
> mode change 100644 => 100755 sound/soc/codecs/Kconfig
> mode change 100644 => 100755 sound/soc/codecs/Makefile
> create mode 100755 sound/soc/codecs/max98927.c
> create mode 100755 sound/soc/codecs/max98927.h
These should all be 644 mode.
Rob
^ permalink raw reply
* Re: [PATCH] of: irq: Export of_irq_count()
From: Thierry Reding @ 2017-04-03 16:29 UTC (permalink / raw)
To: Rob Herring
Cc: Frank Rowand, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CAL_JsqLGUuJZ6E3W+DXumtAfxtVPG8myqkZs7YL_KFc+RLgGGw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
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On Mon, Apr 03, 2017 at 11:13:43AM -0500, Rob Herring wrote:
> On Mon, Apr 3, 2017 at 10:55 AM, Thierry Reding
> <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> > From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> >
> > of_irq_count() is handy for obtaining the number of interrupts assigned
> > to a device tree node. It is reasonable to want to access this function
> > from loadable modules, so export the symbol to allow that.
> >
> > Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> > ---
> > Hi Rob, Frank,
> >
> > This patch is required for the new Tegra186 GPIO driver I'm trying to
> > get merged for v4.12. It'd be great if I could get an Acked-by from you
> > so that the patch can be merged through the GPIO tree along with a few
> > other prerequisites for the new driver.
>
> Use platform_irq_count instead.
Nice, that's much better.
Thanks,
Thierry
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^ permalink raw reply
* Re: [PATCH 2/2] ARM: dts: keystone: Add minimum support for K2G ICE evm
From: Rob Herring @ 2017-04-03 16:27 UTC (permalink / raw)
To: Franklin S Cooper Jr
Cc: linux-I+IVW8TIWO2tmTQ+vhA3Yw, ssantosh-DgEjT+Ai2ygdnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170330152907.12595-3-fcooper-l0cyMroinI0@public.gmane.org>
On Thu, Mar 30, 2017 at 10:29:07AM -0500, Franklin S Cooper Jr wrote:
> Add barebones dts support for TI's K2G Industrial Communication Engine evm.
> This dts allows the board to boot using a ram based filesystem.
>
> Signed-off-by: Franklin S Cooper Jr <fcooper-l0cyMroinI0@public.gmane.org>
> ---
> arch/arm/boot/dts/Makefile | 3 ++-
> arch/arm/boot/dts/keystone-k2g-ice.dts | 42 ++++++++++++++++++++++++++++++++++
> 2 files changed, 44 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/keystone-k2g-ice.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 0118084..01a98f1 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -193,7 +193,8 @@ dtb-$(CONFIG_ARCH_KEYSTONE) += \
> keystone-k2hk-evm.dtb \
> keystone-k2l-evm.dtb \
> keystone-k2e-evm.dtb \
> - keystone-k2g-evm.dtb
> + keystone-k2g-evm.dtb \
> + keystone-k2g-ice.dtb
> dtb-$(CONFIG_MACH_KIRKWOOD) += \
> kirkwood-b3.dtb \
> kirkwood-blackarmor-nas220.dtb \
> diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/keystone-k2g-ice.dts
> new file mode 100644
> index 0000000..9ab5f42
> --- /dev/null
> +++ b/arch/arm/boot/dts/keystone-k2g-ice.dts
> @@ -0,0 +1,42 @@
> +/*
> + * Device Tree Source for K2G Industrial Communication Engine EVM
> + *
> + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
You can Use SPDX tags here.
> + */
> +/dts-v1/;
> +
> +#include "keystone-k2g.dtsi"
> +
> +/ {
> + compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
> + model = "Texas Instruments K2G Industrial Communication EVM";
> +
> + memory {
memory@800000000
unless that gives you bootloader(s) problems.
> + device_type = "memory";
> + reg = <0x00000008 0x00000000 0x00000000 0x20000000>;
> + };
> +};
> +
> +&k2g_pinctrl {
> + uart0_pins: pinmux_uart0_pins {
> + pinctrl-single,pins = <
> + K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
> + K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
> + >;
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> + status = "okay";
> +};
> --
> 2.10.0
>
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