* [PATCH v2 1/2] dt-binding: regulator: anatop: make regulator name property required
From: Dong Aisheng @ 2017-04-14 14:30 UTC (permalink / raw)
To: linux-kernel; +Cc: Dong Aisheng, Rob Herring, Mark Rutland, devicetree
We actually can't allow the missing of the regualor name, thus update
the binding doc to make regulator-name property to be required.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
Documentation/devicetree/bindings/regulator/anatop-regulator.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
index 1d58c8c..a3106c7 100644
--- a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
@@ -2,6 +2,7 @@ Anatop Voltage regulators
Required properties:
- compatible: Must be "fsl,anatop-regulator"
+- regulator-name: A string used as a descriptive name for regulator outputs
- anatop-reg-offset: Anatop MFD register offset
- anatop-vol-bit-shift: Bit shift for the register
- anatop-vol-bit-width: Number of bits used in the register
--
2.7.4
^ permalink raw reply related
* Re: [GIT PULL] Immutable branch between MFD and IIO due for the v4.12 merge window
From: Jonathan Cameron @ 2017-04-14 14:30 UTC (permalink / raw)
To: Lee Jones, Quentin Schulz
Cc: mark.rutland, thomas.petazzoni, lars, linux-pm, liam,
linux-kernel, linux-sunxi, sre, linux, linux-iio, wens, robh+dt,
icenowy, pmeerw, knaack.h, maxime.ripard, devicetree,
linux-arm-kernel
In-Reply-To: <20170411100528.2zif3fyi7uoyw33n@dell>
On 11/04/17 11:05, Lee Jones wrote:
> Enjoy!
>
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git ib-mfd-iio-v4.12
>
> for you to fetch changes up to f2499ab450d3052097ba53a7d763f767935c0c59:
>
> iio: adc: add support for X-Powers AXP20X and AXP22X PMICs ADCs (2017-04-11 11:02:33 +0100)
>
> ----------------------------------------------------------------
> Immutable branch between MFD and IIO due for the v4.12 merge window
>
> ----------------------------------------------------------------
> Quentin Schulz (1):
> iio: adc: add support for X-Powers AXP20X and AXP22X PMICs ADCs
>
> drivers/iio/adc/Kconfig | 10 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/axp20x_adc.c | 617 +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 628 insertions(+)
> create mode 100644 drivers/iio/adc/axp20x_adc.c
>
Hi Lee,
Thanks for doing this, but the reason it was going to go through your
tree in the first place was a dependency on
commit 4707274714ef ("mfd: axp20x: Correct name of temperature data ADC registers")
Not present in the immutable branch.
There isn't much time for anything else going on around this driver though
so other than a possible merge conflict on the Kconfig and Makefile shouldn't
matter if this just goes through mfd. (famous last words ;)
Jonathan
^ permalink raw reply
* Re: [PATCH] ARM: dts: dra7: Add power hold and power controller properties to palmas
From: Tony Lindgren @ 2017-04-14 14:21 UTC (permalink / raw)
To: Keerthy
Cc: robh+dt, mark.rutland, devicetree, linux-kernel, linux-omap,
t-kristo
In-Reply-To: <1492059081-20124-1-git-send-email-j-keerthy@ti.com>
* Keerthy <j-keerthy@ti.com> [170412 21:55]:
> Add power hold and power controller properties to palmas node.
> This is needed to shutdown pmic correctly on boards with
> powerhold set.
Is this OK to wait for v4.12 or is this needed as a fix for
the -rc series?
Regards,
Tony
> Signed-off-by: Keerthy <j-keerthy@ti.com>
> ---
> arch/arm/boot/dts/dra7-evm.dts | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
> index 4bc4b57..31a9e06 100644
> --- a/arch/arm/boot/dts/dra7-evm.dts
> +++ b/arch/arm/boot/dts/dra7-evm.dts
> @@ -204,6 +204,8 @@
> tps659038: tps659038@58 {
> compatible = "ti,tps659038";
> reg = <0x58>;
> + ti,palmas-override-powerhold;
> + ti,system-power-controller;
>
> tps659038_pmic {
> compatible = "ti,tps659038-pmic";
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH V2] PM / OPP: Use - instead of @ for DT entries
From: Tony Lindgren @ 2017-04-14 14:20 UTC (permalink / raw)
To: Viresh Kumar
Cc: Rafael Wysocki, Chanwoo Choi, MyungJoo Ham, Kyungmin Park,
Kukjin Kim, Krzysztof Kozlowski, Javier Martinez Canillas,
Viresh Kumar, Nishanth Menon, Stephen Boyd, Benoît Cousson,
Rob Herring, Mark Rutland, Daniel Mack, Haojian Zhuang,
Robert Jarzmik, Maxime Ripard, Chen-Yu Tsai, Masahiro Yamada
In-Reply-To: <70e7c7ee13722ab9c73cb073f88502eaf1ada5f5.1491816050.git.viresh.kumar@linaro.org>
* Viresh Kumar <viresh.kumar@linaro.org> [170410 02:24]:
> Compiling the DT file with W=1, DTC warns like follows:
>
> Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
> unit name, but no reg property
>
> Fix this by replacing '@' with '-' as the OPP nodes will never have a
> "reg" property.
>
> Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> Suggested-by: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> (sunxi)
> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Looks good to me too:
Acked-by: Tony Lindgren <tony@atomide.com>
^ permalink raw reply
* Re: [PATCH v3 03/21] ARM: dts: omap: Add generic compatible string for I2C EEPROM
From: Tony Lindgren @ 2017-04-14 14:17 UTC (permalink / raw)
To: Javier Martinez Canillas
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Wolfram Sang,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Benoît Cousson, devicetree-u79uwXL29TY76Z2rM5mHXA,
Rob Herring, Mark Rutland, linux-omap-u79uwXL29TY76Z2rM5mHXA,
Russell King, Mark Jackson
In-Reply-To: <20170414010445.21727-4-javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
* Javier Martinez Canillas <javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org> [170413 18:08]:
> The at24 driver allows to register I2C EEPROM chips using different vendor
> and devices, but the I2C subsystem does not take the vendor into account
> when matching using the I2C table since it only has device entries.
>
> But when matching using an OF table, both the vendor and device has to be
> taken into account so the driver defines only a set of compatible strings
> using the "atmel" vendor as a generic fallback for compatible I2C devices.
>
> So add this generic fallback to the device node compatible string to make
> the device to match the driver using the OF device ID table.
>
> Signed-off-by: Javier Martinez Canillas <javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
Looks good to me assuming this will get merged in a single series:
Acked-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
Or if you want me to pick this patch separately, let me know.
Regards,
Tony
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^ permalink raw reply
* Re: [PATCH 2/3] Documentation: dt: i2c: Add Altera I2C Controller
From: Thor Thayer @ 2017-04-14 13:46 UTC (permalink / raw)
To: Rob Herring
Cc: wsa-z923LK4zBo2bacvFa/9K2g, linux-i2c-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170413212240.uxwh5525baqmgny4@rob-hp-laptop>
Hi Rob,
On 04/13/2017 04:22 PM, Rob Herring wrote:
> On Tue, Apr 11, 2017 at 11:02:26AM -0500, thor.thayer-VuQAYsv1563Yd54FQh9/CA@public.gmane.org wrote:
>> From: Thor Thayer <thor.thayer-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
>>
>> Add the documentation to support the Altera I2C Controller.
>
> "dt-bindings: i2c: ..." for the subject.
>
Got it. Thanks.
>>
>> Signed-off-by: Thor Thayer <thor.thayer-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
>> ---
>> .../devicetree/bindings/i2c/i2c-altera.txt | 37 ++++++++++++++++++++++
>> 1 file changed, 37 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/i2c/i2c-altera.txt
>>
>> diff --git a/Documentation/devicetree/bindings/i2c/i2c-altera.txt b/Documentation/devicetree/bindings/i2c/i2c-altera.txt
>> new file mode 100644
>> index 0000000..a67241c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/i2c/i2c-altera.txt
>> @@ -0,0 +1,37 @@
>> +* Altera I2C Controller
>
> This is the only one? For synthesizable logic or a hard block in
> socfpga?
>
This is synthesizable logic in an FPGA.
>> +
>> +Required properties :
>> + - compatible : should be "altr,sip-i2c"
>
> Seems kind of generic.
>
I'm using sip for soft IP - right now we only offer 1 flavor.
>> + - reg : Offset and length of the register set for the device
>> + - interrupts : <IRQ> where IRQ is the interrupt number.
>> + - clocks : phandles to input clocks.
>
> Need to specify how many clocks.
>
OK. There is only 1 so I'll change to singular. phandle to input clock.
>> + - #address-cells = <1>;
>> + - #size-cells = <0>;
>> +
>> +Recommended properties :
>> + - clock-frequency : desired I2C bus clock frequency in Hz.
>> +
>> +Optional properties :
>> + - altr,fifo-size : Size of the RX and TX FIFOs.
>
> in bytes?
>
> Just "fifo-size" is already fairly common, so drop the vendor prefix.
>
Yes, it is in bytes. I'll make the change.
Thanks for reviewing!
>> + - Child nodes conforming to i2c bus binding
>> +
>> +Example :
>> +
>> + i2c@100080000 {
>> + compatible = "altr,sip-i2c";
>> + reg = <0x00000001 0x00080000 0x00000040>;
>> + interrupt-parent = <&intc>;
>> + interrupts = <0 43 4>;
>> + clocks = <&clk_0>;
>> + clock-frequency = <100000>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + altr,fifo-size = <4>;
>> +
>> + eeprom@51 {
>> + compatible = "atmel,24c32";
>> + reg = <0x51>;
>> + pagesize = <32>;
>> + };
>> + };
>> +
>> --
>> 1.9.1
>>
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^ permalink raw reply
* [PATCH 2/2] arm64: allwinner: a64: enable EHCI0/OHCI0 for Pine64
From: Icenowy Zheng @ 2017-04-14 13:15 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
In-Reply-To: <20170414131555.9431-1-icenowy-h8G6r0blFSE@public.gmane.org>
As we have USB0 controller switch available on A64, we should now enable
the EHCI0/OHCI0 controllers for Pine64.
Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index c680ed385da3..4782add50b94 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -66,6 +66,10 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -91,6 +95,10 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
--
2.12.2
^ permalink raw reply related
* [PATCH 1/2] arm64: allwinner: a64: add EHCI0/OHCI0 nodes to A64 DTSI
From: Icenowy Zheng @ 2017-04-14 13:15 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
Allwinner A64 SoC features a pair of EHCI/OHCI controllers that can be
set to wire to USB0 port (the OTG-capable one), which can be used to
provide a better performance in host mode.
Add their device tree nodes.
Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index c7f669f5884f..65a344d9cea4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -204,6 +204,28 @@
#phy-cells = <1>;
};
+ ehci0: usb@01c1a000 {
+ compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ status = "disabled";
+ };
+
+ ohci0: usb@01c1a400 {
+ compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
ehci1: usb@01c1b000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;
--
2.12.2
^ permalink raw reply related
* Re: [PATCH v7 5/9] MAINTAINERS: add maintainers for DRM STM driver
From: Neil Armstrong @ 2017-04-14 12:59 UTC (permalink / raw)
To: Yannick Fertre, Alexandre TORGUE, Thierry Reding, David Airlie,
Maxime Coquelin, Russell King, Mark Rutland, Rob Herring,
Arnd Bergmann, Benjamin Gaignard
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, kernel-F5mvAk5X5gdBDgjK7y7TUQ,
Philippe Cornu, Fabien Dessenne,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Mickael Reulier,
Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1492164819-10513-6-git-send-email-yannick.fertre-qxv4g6HH51o@public.gmane.org>
On 04/14/2017 12:13 PM, Yannick Fertre wrote:
> Add Philippe Cornu and myself as maintainers.
>
> Signed-off-by: Yannick Fertre <yannick.fertre-qxv4g6HH51o@public.gmane.org>
> ---
> MAINTAINERS | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index c36dfae..84cf73f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -4424,6 +4424,15 @@ S: Maintained
> F: drivers/gpu/drm/sti
> F: Documentation/devicetree/bindings/display/st,stih4xx.txt
>
> +DRM DRIVERS FOR STM
> +M: Yannick Fertre <yannick.fertre-qxv4g6HH51o@public.gmane.org>
> +M: Philippe Cornu <philippe.cornu-qxv4g6HH51o@public.gmane.org>
> +L: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> +T: git git://anongit.freedesktop.org/drm/drm-misc
> +S: Maintained
> +F: drivers/gpu/drm/stm
> +F: Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
> +
> DRM DRIVER FOR TDFX VIDEO CARDS
> S: Orphan / Obsolete
> F: drivers/gpu/drm/tdfx/
>
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH v7 4/9] drm/stm: Add STM32 LTDC driver
From: Neil Armstrong @ 2017-04-14 12:59 UTC (permalink / raw)
To: Yannick Fertre, Alexandre TORGUE, Thierry Reding, David Airlie,
Maxime Coquelin, Russell King, Mark Rutland, Rob Herring,
Arnd Bergmann, Benjamin Gaignard
Cc: devicetree, kernel, Philippe Cornu, dri-devel, Fabien Dessenne,
Mickael Reulier, Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel
In-Reply-To: <1492164819-10513-5-git-send-email-yannick.fertre@st.com>
On 04/14/2017 12:13 PM, Yannick Fertre wrote:
> This controller provides output signals to interface directly a variety
> of LCD and TFT panels. These output signals are: RGB signals
> (up to 24bpp), vertical & horizontal synchronisations, data enable and
> the pixel clock.
>
> Reviewed-by: Eric Anholt <eric@anholt.net>
> Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
> ---
> drivers/gpu/drm/Kconfig | 2 +
> drivers/gpu/drm/Makefile | 1 +
> drivers/gpu/drm/stm/Kconfig | 16 +
> drivers/gpu/drm/stm/Makefile | 7 +
> drivers/gpu/drm/stm/drv.c | 221 ++++++++
> drivers/gpu/drm/stm/ltdc.c | 1161 ++++++++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/stm/ltdc.h | 40 ++
> 7 files changed, 1448 insertions(+)
> create mode 100644 drivers/gpu/drm/stm/Kconfig
> create mode 100644 drivers/gpu/drm/stm/Makefile
> create mode 100644 drivers/gpu/drm/stm/drv.c
> create mode 100644 drivers/gpu/drm/stm/ltdc.c
> create mode 100644 drivers/gpu/drm/stm/ltdc.h
>
> diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
> index 78d7fc0..f57540d 100644
> --- a/drivers/gpu/drm/Kconfig
> +++ b/drivers/gpu/drm/Kconfig
> @@ -246,6 +246,8 @@ source "drivers/gpu/drm/fsl-dcu/Kconfig"
>
> source "drivers/gpu/drm/tegra/Kconfig"
>
> +source "drivers/gpu/drm/stm/Kconfig"
> +
> source "drivers/gpu/drm/panel/Kconfig"
>
> source "drivers/gpu/drm/bridge/Kconfig"
> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> index 59f0f9b..aa62ded 100644
> --- a/drivers/gpu/drm/Makefile
> +++ b/drivers/gpu/drm/Makefile
> @@ -82,6 +82,7 @@ obj-$(CONFIG_DRM_BOCHS) += bochs/
> obj-$(CONFIG_DRM_VIRTIO_GPU) += virtio/
> obj-$(CONFIG_DRM_MSM) += msm/
> obj-$(CONFIG_DRM_TEGRA) += tegra/
> +obj-$(CONFIG_DRM_STM) += stm/
> obj-$(CONFIG_DRM_STI) += sti/
> obj-$(CONFIG_DRM_IMX) += imx/
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek/
> diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig
> new file mode 100644
> index 0000000..2c4817f
> --- /dev/null
> +++ b/drivers/gpu/drm/stm/Kconfig
> @@ -0,0 +1,16 @@
> +config DRM_STM
> + tristate "DRM Support for STMicroelectronics SoC Series"
> + depends on DRM && (ARCH_STM32 || ARCH_MULTIPLATFORM)
> + select DRM_KMS_HELPER
> + select DRM_GEM_CMA_HELPER
> + select DRM_KMS_CMA_HELPER
> + select DRM_PANEL
> + select VIDEOMODE_HELPERS
> + select FB_PROVIDE_GET_FB_UNMAPPED_AREA
> + default y
> +
> + help
> + Enable support for the on-chip display controller on
> + STMicroelectronics STM32 MCUs.
> + To compile this driver as a module, choose M here: the module
> + will be called stm-drm.
> diff --git a/drivers/gpu/drm/stm/Makefile b/drivers/gpu/drm/stm/Makefile
> new file mode 100644
> index 0000000..e114d45
> --- /dev/null
> +++ b/drivers/gpu/drm/stm/Makefile
> @@ -0,0 +1,7 @@
> +ccflags-y := -Iinclude/drm
> +
> +stm-drm-y := \
> + drv.o \
> + ltdc.o
> +
> +obj-$(CONFIG_DRM_STM) += stm-drm.o
> diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c
> new file mode 100644
> index 0000000..83ab48f
> --- /dev/null
> +++ b/drivers/gpu/drm/stm/drv.c
> @@ -0,0 +1,221 @@
> +/*
> + * Copyright (C) STMicroelectronics SA 2017
> + *
> + * Authors: Philippe Cornu <philippe.cornu@st.com>
> + * Yannick Fertre <yannick.fertre@st.com>
> + * Fabien Dessenne <fabien.dessenne@st.com>
> + * Mickael Reulier <mickael.reulier@st.com>
> + *
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#include <linux/component.h>
> +#include <linux/of_platform.h>
> +
> +#include <drm/drm_atomic.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_fb_cma_helper.h>
> +#include <drm/drm_gem_cma_helper.h>
> +
> +#include "ltdc.h"
> +
> +#define DRIVER_NAME "stm"
> +#define DRIVER_DESC "STMicroelectronics SoC DRM"
> +#define DRIVER_DATE "20170330"
> +#define DRIVER_MAJOR 1
> +#define DRIVER_MINOR 0
> +#define DRIVER_PATCH_LEVEL 0
> +
> +#define STM_MAX_FB_WIDTH 2048
> +#define STM_MAX_FB_HEIGHT 2048 /* same as width to handle orientation */
> +
> +static void drv_output_poll_changed(struct drm_device *ddev)
> +{
> + struct ltdc_device *ldev = ddev->dev_private;
> +
> + drm_fbdev_cma_hotplug_event(ldev->fbdev);
> +}
> +
> +static const struct drm_mode_config_funcs drv_mode_config_funcs = {
> + .fb_create = drm_fb_cma_create,
> + .output_poll_changed = drv_output_poll_changed,
> + .atomic_check = drm_atomic_helper_check,
> + .atomic_commit = drm_atomic_helper_commit,
> +};
> +
> +static void drv_lastclose(struct drm_device *ddev)
> +{
> + struct ltdc_device *ldev = ddev->dev_private;
> +
> + DRM_DEBUG("%s\n", __func__);
> +
> + drm_fbdev_cma_restore_mode(ldev->fbdev);
> +}
> +
> +DEFINE_DRM_GEM_CMA_FOPS(drv_driver_fops);
> +
> +static struct drm_driver drv_driver = {
> + .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
> + DRIVER_ATOMIC,
> + .lastclose = drv_lastclose,
> + .name = DRIVER_NAME,
> + .desc = DRIVER_DESC,
> + .date = DRIVER_DATE,
> + .major = DRIVER_MAJOR,
> + .minor = DRIVER_MINOR,
> + .patchlevel = DRIVER_PATCH_LEVEL,
> + .fops = &drv_driver_fops,
> + .dumb_create = drm_gem_cma_dumb_create,
> + .dumb_map_offset = drm_gem_cma_dumb_map_offset,
> + .dumb_destroy = drm_gem_dumb_destroy,
> + .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> + .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> + .gem_free_object_unlocked = drm_gem_cma_free_object,
> + .gem_vm_ops = &drm_gem_cma_vm_ops,
> + .gem_prime_export = drm_gem_prime_export,
> + .gem_prime_import = drm_gem_prime_import,
> + .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
> + .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> + .gem_prime_vmap = drm_gem_cma_prime_vmap,
> + .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
> + .gem_prime_mmap = drm_gem_cma_prime_mmap,
> + .enable_vblank = ltdc_crtc_enable_vblank,
> + .disable_vblank = ltdc_crtc_disable_vblank,
> +};
> +
> +static int drv_load(struct drm_device *ddev)
> +{
> + struct platform_device *pdev = to_platform_device(ddev->dev);
> + struct drm_fbdev_cma *fbdev;
> + struct ltdc_device *ldev;
> + int ret;
> +
> + DRM_DEBUG("%s\n", __func__);
> +
> + ldev = devm_kzalloc(ddev->dev, sizeof(*ldev), GFP_KERNEL);
> + if (!ldev)
> + return -ENOMEM;
> +
> + ddev->dev_private = (void *)ldev;
> +
> + drm_mode_config_init(ddev);
> +
> + /*
> + * set max width and height as default value.
> + * this value would be used to check framebuffer size limitation
> + * at drm_mode_addfb().
> + */
> + ddev->mode_config.min_width = 0;
> + ddev->mode_config.min_height = 0;
> + ddev->mode_config.max_width = STM_MAX_FB_WIDTH;
> + ddev->mode_config.max_height = STM_MAX_FB_HEIGHT;
> + ddev->mode_config.funcs = &drv_mode_config_funcs;
> +
> + ret = ltdc_load(ddev);
> + if (ret)
> + goto err;
> +
> + drm_mode_config_reset(ddev);
> + drm_kms_helper_poll_init(ddev);
> +
> + if (ddev->mode_config.num_connector) {
> + ldev = ddev->dev_private;
> + fbdev = drm_fbdev_cma_init(ddev, 16,
> + ddev->mode_config.num_connector);
> + if (IS_ERR(fbdev)) {
> + DRM_DEBUG("Warning: fails to create fbdev\n");
> + fbdev = NULL;
> + }
> + ldev->fbdev = fbdev;
> + }
> +
> + platform_set_drvdata(pdev, ddev);
> +
> + return 0;
> +err:
> + drm_mode_config_cleanup(ddev);
> + return ret;
> +}
> +
> +static void drv_unload(struct drm_device *ddev)
> +{
> + struct ltdc_device *ldev = ddev->dev_private;
> +
> + DRM_DEBUG("%s\n", __func__);
> +
> + if (ldev->fbdev) {
> + drm_fbdev_cma_fini(ldev->fbdev);
> + ldev->fbdev = NULL;
> + }
> + drm_kms_helper_poll_fini(ddev);
> + ltdc_unload(ddev);
> + drm_mode_config_cleanup(ddev);
> +}
> +
> +static int stm_drm_platform_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct drm_device *ddev;
> + int ret;
> +
> + DRM_DEBUG("%s\n", __func__);
> +
> + dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
> +
> + ddev = drm_dev_alloc(&drv_driver, dev);
> + if (IS_ERR(ddev))
> + return PTR_ERR(ddev);
> +
> + ret = drv_load(ddev);
> + if (ret)
> + goto err_unref;
> +
> + ret = drm_dev_register(ddev, 0);
> + if (ret)
> + goto err_unref;
> +
> + return 0;
> +
> +err_unref:
> + drm_dev_unref(ddev);
> +
> + return ret;
> +}
> +
> +static int stm_drm_platform_remove(struct platform_device *pdev)
> +{
> + struct drm_device *ddev = platform_get_drvdata(pdev);
> +
> + DRM_DEBUG("%s\n", __func__);
> +
> + drm_dev_unregister(ddev);
> + drv_unload(ddev);
> + drm_dev_unref(ddev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id drv_dt_ids[] = {
> + { .compatible = "st,stm32-ltdc"},
> + { /* end node */ },
> +};
> +MODULE_DEVICE_TABLE(of, drv_dt_ids);
> +
> +static struct platform_driver stm_drm_platform_driver = {
> + .probe = stm_drm_platform_probe,
> + .remove = stm_drm_platform_remove,
> + .driver = {
> + .name = DRIVER_NAME,
> + .of_match_table = drv_dt_ids,
> + },
> +};
> +
> +module_platform_driver(stm_drm_platform_driver);
> +
> +MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
> +MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
> +MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
> +MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
> +MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> new file mode 100644
> index 0000000..a373178
> --- /dev/null
> +++ b/drivers/gpu/drm/stm/ltdc.c
> @@ -0,0 +1,1161 @@
> +/*
> + * Copyright (C) STMicroelectronics SA 2017
> + *
> + * Authors: Philippe Cornu <philippe.cornu@st.com>
> + * Yannick Fertre <yannick.fertre@st.com>
> + * Fabien Dessenne <fabien.dessenne@st.com>
> + * Mickael Reulier <mickael.reulier@st.com>
> + *
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_address.h>
> +#include <linux/of_graph.h>
> +#include <linux/reset.h>
> +
> +#include <drm/drm_atomic.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_fb_cma_helper.h>
> +#include <drm/drm_gem_cma_helper.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_plane_helper.h>
> +
> +#include <video/videomode.h>
> +
> +#include "ltdc.h"
> +
> +#define NB_CRTC 1
> +#define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
> +
> +#define MAX_IRQ 4
> +
> +#define HWVER_10200 0x010200
> +#define HWVER_10300 0x010300
> +#define HWVER_20101 0x020101
> +
> +/*
> + * The address of some registers depends on the HW version: such registers have
> + * an extra offset specified with reg_ofs.
> + */
> +#define REG_OFS_NONE 0
> +#define REG_OFS_4 4 /* Insertion of "Layer Configuration 2" reg */
> +#define REG_OFS (ldev->caps.reg_ofs)
> +#define LAY_OFS 0x80 /* Register Offset between 2 layers */
> +
> +/* Global register offsets */
> +#define LTDC_IDR 0x0000 /* IDentification */
> +#define LTDC_LCR 0x0004 /* Layer Count */
> +#define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */
> +#define LTDC_BPCR 0x000C /* Back Porch Configuration */
> +#define LTDC_AWCR 0x0010 /* Active Width Configuration */
> +#define LTDC_TWCR 0x0014 /* Total Width Configuration */
> +#define LTDC_GCR 0x0018 /* Global Control */
> +#define LTDC_GC1R 0x001C /* Global Configuration 1 */
> +#define LTDC_GC2R 0x0020 /* Global Configuration 2 */
> +#define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */
> +#define LTDC_GACR 0x0028 /* GAmma Correction */
> +#define LTDC_BCCR 0x002C /* Background Color Configuration */
> +#define LTDC_IER 0x0034 /* Interrupt Enable */
> +#define LTDC_ISR 0x0038 /* Interrupt Status */
> +#define LTDC_ICR 0x003C /* Interrupt Clear */
> +#define LTDC_LIPCR 0x0040 /* Line Interrupt Position Configuration */
> +#define LTDC_CPSR 0x0044 /* Current Position Status */
> +#define LTDC_CDSR 0x0048 /* Current Display Status */
> +
> +/* Layer register offsets */
> +#define LTDC_L1LC1R (0x0080) /* L1 Layer Configuration 1 */
> +#define LTDC_L1LC2R (0x0084) /* L1 Layer Configuration 2 */
> +#define LTDC_L1CR (0x0084 + REG_OFS) /* L1 Control */
> +#define LTDC_L1WHPCR (0x0088 + REG_OFS) /* L1 Window Hor Position Config */
> +#define LTDC_L1WVPCR (0x008C + REG_OFS) /* L1 Window Vert Position Config */
> +#define LTDC_L1CKCR (0x0090 + REG_OFS) /* L1 Color Keying Configuration */
> +#define LTDC_L1PFCR (0x0094 + REG_OFS) /* L1 Pixel Format Configuration */
> +#define LTDC_L1CACR (0x0098 + REG_OFS) /* L1 Constant Alpha Config */
> +#define LTDC_L1DCCR (0x009C + REG_OFS) /* L1 Default Color Configuration */
> +#define LTDC_L1BFCR (0x00A0 + REG_OFS) /* L1 Blend Factors Configuration */
> +#define LTDC_L1FBBCR (0x00A4 + REG_OFS) /* L1 FrameBuffer Bus Control */
> +#define LTDC_L1AFBCR (0x00A8 + REG_OFS) /* L1 AuxFB Control */
> +#define LTDC_L1CFBAR (0x00AC + REG_OFS) /* L1 Color FrameBuffer Address */
> +#define LTDC_L1CFBLR (0x00B0 + REG_OFS) /* L1 Color FrameBuffer Length */
> +#define LTDC_L1CFBLNR (0x00B4 + REG_OFS) /* L1 Color FrameBuffer Line Nb */
> +#define LTDC_L1AFBAR (0x00B8 + REG_OFS) /* L1 AuxFB Address */
> +#define LTDC_L1AFBLR (0x00BC + REG_OFS) /* L1 AuxFB Length */
> +#define LTDC_L1AFBLNR (0x00C0 + REG_OFS) /* L1 AuxFB Line Number */
> +#define LTDC_L1CLUTWR (0x00C4 + REG_OFS) /* L1 CLUT Write */
> +#define LTDC_L1YS1R (0x00E0 + REG_OFS) /* L1 YCbCr Scale 1 */
> +#define LTDC_L1YS2R (0x00E4 + REG_OFS) /* L1 YCbCr Scale 2 */
> +
> +/* Bit definitions */
> +#define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
> +#define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
> +
> +#define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
> +#define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
> +
> +#define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
> +#define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
> +
> +#define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
> +#define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
> +
> +#define GCR_LTDCEN BIT(0) /* LTDC ENable */
> +#define GCR_DEN BIT(16) /* Dither ENable */
> +#define GCR_PCPOL BIT(28) /* Pixel Clock POLarity */
> +#define GCR_DEPOL BIT(29) /* Data Enable POLarity */
> +#define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity */
> +#define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity */
> +
> +#define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
> +#define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
> +#define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
> +#define GC1R_PBEN BIT(12) /* Precise Blending ENable */
> +#define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
> +#define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
> +#define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
> +#define GC1R_BCP BIT(22) /* Background Colour Programmable */
> +#define GC1R_BBEN BIT(23) /* Background Blending ENabled */
> +#define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
> +#define GC1R_TP BIT(25) /* Timing Programmable */
> +#define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
> +#define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
> +#define GC1R_DWP BIT(28) /* Dither Width Programmable */
> +#define GC1R_STREN BIT(29) /* STatus Registers ENabled */
> +#define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
> +
> +#define GC2R_EDCA BIT(0) /* External Display Control Ability */
> +#define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
> +#define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
> +#define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
> +#define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
> +#define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
> +
> +#define SRCR_IMR BIT(0) /* IMmediate Reload */
> +#define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
> +
> +#define BCCR_BCBLACK 0x00 /* Background Color BLACK */
> +#define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */
> +#define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */
> +#define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */
> +#define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */
> +
> +#define IER_LIE BIT(0) /* Line Interrupt Enable */
> +#define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */
> +#define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */
> +#define IER_RRIE BIT(3) /* Register Reload Interrupt enable */
> +
> +#define ISR_LIF BIT(0) /* Line Interrupt Flag */
> +#define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */
> +#define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */
> +#define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */
> +
> +#define LXCR_LEN BIT(0) /* Layer ENable */
> +#define LXCR_COLKEN BIT(1) /* Color Keying Enable */
> +#define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
> +
> +#define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
> +#define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
> +
> +#define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
> +#define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
> +
> +#define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
> +
> +#define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
> +
> +#define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
> +#define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
> +
> +#define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
> +#define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
> +
> +#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
> +
> +#define HSPOL_AL 0 /* Horizontal Sync POLarity Active Low */
> +#define VSPOL_AL 0 /* Vertical Sync POLarity Active Low */
> +#define DEPOL_AL 0 /* Data Enable POLarity Active Low */
> +#define PCPOL_IPC 0 /* Input Pixel Clock */
> +#define HSPOL_AH GCR_HSPOL /* Horizontal Sync POLarity Active High */
> +#define VSPOL_AH GCR_VSPOL /* Vertical Sync POLarity Active High */
> +#define DEPOL_AH GCR_DEPOL /* Data Enable POLarity Active High */
> +#define PCPOL_IIPC GCR_PCPOL /* Inverted Input Pixel Clock */
> +#define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */
> +#define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
> +#define BF1_CA 0x400 /* Constant Alpha */
> +#define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
> +#define BF2_1CA 0x005 /* 1 - Constant Alpha */
> +
> +#define NB_PF 8 /* Max nb of HW pixel format */
> +
> +enum ltdc_pix_fmt {
> + PF_NONE,
> + /* RGB formats */
> + PF_ARGB8888, /* ARGB [32 bits] */
> + PF_RGBA8888, /* RGBA [32 bits] */
> + PF_RGB888, /* RGB [24 bits] */
> + PF_RGB565, /* RGB [16 bits] */
> + PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */
> + PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
> + /* Indexed formats */
> + PF_L8, /* Indexed 8 bits [8 bits] */
> + PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */
> + PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */
> +};
> +
> +/* The index gives the encoding of the pixel format for an HW version */
> +static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = {
> + PF_ARGB8888, /* 0x00 */
> + PF_RGB888, /* 0x01 */
> + PF_RGB565, /* 0x02 */
> + PF_ARGB1555, /* 0x03 */
> + PF_ARGB4444, /* 0x04 */
> + PF_L8, /* 0x05 */
> + PF_AL44, /* 0x06 */
> + PF_AL88 /* 0x07 */
> +};
> +
> +static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
> + PF_ARGB8888, /* 0x00 */
> + PF_RGB888, /* 0x01 */
> + PF_RGB565, /* 0x02 */
> + PF_RGBA8888, /* 0x03 */
> + PF_AL44, /* 0x04 */
> + PF_L8, /* 0x05 */
> + PF_ARGB1555, /* 0x06 */
> + PF_ARGB4444 /* 0x07 */
> +};
> +
> +static inline u32 reg_read(void __iomem *base, u32 reg)
> +{
> + return readl_relaxed(base + reg);
> +}
> +
> +static inline void reg_write(void __iomem *base, u32 reg, u32 val)
> +{
> + writel_relaxed(val, base + reg);
> +}
> +
> +static inline void reg_set(void __iomem *base, u32 reg, u32 mask)
> +{
> + reg_write(base, reg, reg_read(base, reg) | mask);
> +}
> +
> +static inline void reg_clear(void __iomem *base, u32 reg, u32 mask)
> +{
> + reg_write(base, reg, reg_read(base, reg) & ~mask);
> +}
> +
> +static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask,
> + u32 val)
> +{
> + reg_write(base, reg, (reg_read(base, reg) & ~mask) | val);
> +}
> +
> +static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc)
> +{
> + return (struct ltdc_device *)crtc->dev->dev_private;
> +}
> +
> +static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane)
> +{
> + return (struct ltdc_device *)plane->dev->dev_private;
> +}
> +
> +static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc)
> +{
> + return (struct ltdc_device *)enc->dev->dev_private;
> +}
> +
> +static inline struct ltdc_device *connector_to_ltdc(struct drm_connector *con)
> +{
> + return (struct ltdc_device *)con->dev->dev_private;
> +}
> +
> +static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
> +{
> + enum ltdc_pix_fmt pf;
> +
> + switch (drm_fmt) {
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_XRGB8888:
> + pf = PF_ARGB8888;
> + break;
> + case DRM_FORMAT_RGBA8888:
> + case DRM_FORMAT_RGBX8888:
> + pf = PF_RGBA8888;
> + break;
> + case DRM_FORMAT_RGB888:
> + pf = PF_RGB888;
> + break;
> + case DRM_FORMAT_RGB565:
> + pf = PF_RGB565;
> + break;
> + case DRM_FORMAT_ARGB1555:
> + case DRM_FORMAT_XRGB1555:
> + pf = PF_ARGB1555;
> + break;
> + case DRM_FORMAT_ARGB4444:
> + case DRM_FORMAT_XRGB4444:
> + pf = PF_ARGB4444;
> + break;
> + case DRM_FORMAT_C8:
> + pf = PF_L8;
> + break;
> + default:
> + pf = PF_NONE;
> + break;
> + /* Note: There are no DRM_FORMAT for AL44 and AL88 */
> + }
> +
> + return pf;
> +}
> +
> +static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf)
> +{
> + switch (pf) {
> + case PF_ARGB8888:
> + return DRM_FORMAT_ARGB8888;
> + case PF_RGBA8888:
> + return DRM_FORMAT_RGBA8888;
> + case PF_RGB888:
> + return DRM_FORMAT_RGB888;
> + case PF_RGB565:
> + return DRM_FORMAT_RGB565;
> + case PF_ARGB1555:
> + return DRM_FORMAT_ARGB1555;
> + case PF_ARGB4444:
> + return DRM_FORMAT_ARGB4444;
> + case PF_L8:
> + return DRM_FORMAT_C8;
> + case PF_AL44: /* No DRM support */
> + case PF_AL88: /* No DRM support */
> + case PF_NONE:
> + default:
> + return 0;
> + }
> +}
> +
> +static irqreturn_t ltdc_irq_thread(int irq, void *arg)
> +{
> + struct drm_device *ddev = arg;
> + struct ltdc_device *ldev = ddev->dev_private;
> + struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0);
> +
> + /* Line IRQ : trigger the vblank event */
> + if (ldev->irq_status & ISR_LIF)
> + drm_crtc_handle_vblank(crtc);
> +
> + /* Save FIFO Underrun & Transfer Error status */
> + mutex_lock(&ldev->err_lock);
> + if (ldev->irq_status & ISR_FUIF)
> + ldev->error_status |= ISR_FUIF;
> + if (ldev->irq_status & ISR_TERRIF)
> + ldev->error_status |= ISR_TERRIF;
> + mutex_unlock(&ldev->err_lock);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t ltdc_irq(int irq, void *arg)
> +{
> + struct drm_device *ddev = arg;
> + struct ltdc_device *ldev = ddev->dev_private;
> +
> + /* Read & Clear the interrupt status */
> + ldev->irq_status = reg_read(ldev->regs, LTDC_ISR);
> + reg_write(ldev->regs, LTDC_ICR, ldev->irq_status);
> +
> + return IRQ_WAKE_THREAD;
> +}
> +
> +/*
> + * DRM_CRTC
> + */
> +
> +static void ltdc_crtc_load_lut(struct drm_crtc *crtc)
> +{
> + struct ltdc_device *ldev = crtc_to_ltdc(crtc);
> + unsigned int i, lay;
> +
> + for (lay = 0; lay < ldev->caps.nb_layers; lay++)
> + for (i = 0; i < 256; i++)
> + reg_write(ldev->regs, LTDC_L1CLUTWR + lay * LAY_OFS,
> + ldev->clut[i]);
> +}
> +
> +static void ltdc_crtc_enable(struct drm_crtc *crtc)
> +{
> + struct ltdc_device *ldev = crtc_to_ltdc(crtc);
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + /* Sets the background color value */
> + reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK);
> +
> + /* Enable IRQ */
> + reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
> +
> + /* Immediately commit the planes */
> + reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
> +
> + /* Enable LTDC */
> + reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN);
> +
> + drm_crtc_vblank_on(crtc);
> +}
> +
> +static void ltdc_crtc_disable(struct drm_crtc *crtc)
> +{
> + struct ltdc_device *ldev = crtc_to_ltdc(crtc);
> + struct drm_pending_vblank_event *event = crtc->state->event;
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + drm_crtc_vblank_off(crtc);
> +
> + /* disable LTDC */
> + reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN);
> +
> + /* disable IRQ */
> + reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
> +
> + /* immediately commit disable of layers before switching off LTDC */
> + reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
> +}
> +
> +static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
> +{
> + struct ltdc_device *ldev = crtc_to_ltdc(crtc);
> + struct drm_display_mode *mode = &crtc->state->adjusted_mode;
> + struct videomode vm;
> + int rate = mode->clock * 1000;
> + u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
> + u32 total_width, total_height;
> + u32 val;
> +
> + drm_display_mode_to_videomode(mode, &vm);
> +
> + DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name);
> + DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive);
> + DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
> + vm.hfront_porch, vm.hback_porch, vm.hsync_len,
> + vm.vfront_porch, vm.vback_porch, vm.vsync_len);
> +
> + /* Convert video timings to ltdc timings */
> + hsync = vm.hsync_len - 1;
> + vsync = vm.vsync_len - 1;
> + accum_hbp = hsync + vm.hback_porch;
> + accum_vbp = vsync + vm.vback_porch;
> + accum_act_w = accum_hbp + vm.hactive;
> + accum_act_h = accum_vbp + vm.vactive;
> + total_width = accum_act_w + vm.hfront_porch;
> + total_height = accum_act_h + vm.vfront_porch;
> +
> + clk_disable(ldev->pixel_clk);
> +
> + if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
> + DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
> + return;
> + }
> +
> + clk_enable(ldev->pixel_clk);
> +
> + /* Configures the HS, VS, DE and PC polarities. */
> + val = HSPOL_AL | HSPOL_AL | DEPOL_AL | PCPOL_IPC;
> +
> + if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
> + val |= HSPOL_AH;
> +
> + if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
> + val |= VSPOL_AH;
> +
> + if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
> + val |= DEPOL_AH;
> +
> + if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
> + val |= PCPOL_IIPC;
> +
> + reg_update_bits(ldev->regs, LTDC_GCR,
> + GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
> +
> + /* Set Synchronization size */
> + val = (hsync << 16) | vsync;
> + reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
> +
> + /* Set Accumulated Back porch */
> + val = (accum_hbp << 16) | accum_vbp;
> + reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
> +
> + /* Set Accumulated Active Width */
> + val = (accum_act_w << 16) | accum_act_h;
> + reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
> +
> + /* Set total width & height */
> + val = (total_width << 16) | total_height;
> + reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
> +
> + reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1));
> +}
> +
> +static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
> + struct drm_crtc_state *old_crtc_state)
> +{
> + struct ltdc_device *ldev = crtc_to_ltdc(crtc);
> + struct drm_pending_vblank_event *event = crtc->state->event;
> +
> + DRM_DEBUG_ATOMIC("\n");
> +
> + /* Commit shadow registers = update planes at next vblank */
> + reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
> +
> + if (event) {
> + crtc->state->event = NULL;
> +
> + spin_lock_irq(&crtc->dev->event_lock);
> + if (drm_crtc_vblank_get(crtc) == 0)
> + drm_crtc_arm_vblank_event(crtc, event);
> + else
> + drm_crtc_send_vblank_event(crtc, event);
> + spin_unlock_irq(&crtc->dev->event_lock);
> + }
> +}
> +
> +static struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
> + .load_lut = ltdc_crtc_load_lut,
> + .enable = ltdc_crtc_enable,
> + .disable = ltdc_crtc_disable,
> + .mode_set_nofb = ltdc_crtc_mode_set_nofb,
> + .atomic_flush = ltdc_crtc_atomic_flush,
> +};
> +
> +int ltdc_crtc_enable_vblank(struct drm_device *ddev, unsigned int pipe)
> +{
> + struct ltdc_device *ldev = ddev->dev_private;
> +
> + DRM_DEBUG_DRIVER("\n");
> + reg_set(ldev->regs, LTDC_IER, IER_LIE);
> +
> + return 0;
> +}
> +
> +void ltdc_crtc_disable_vblank(struct drm_device *ddev, unsigned int pipe)
> +{
> + struct ltdc_device *ldev = ddev->dev_private;
> +
> + DRM_DEBUG_DRIVER("\n");
> + reg_clear(ldev->regs, LTDC_IER, IER_LIE);
> +}
> +
> +static struct drm_crtc_funcs ltdc_crtc_funcs = {
> + .destroy = drm_crtc_cleanup,
> + .set_config = drm_atomic_helper_set_config,
> + .page_flip = drm_atomic_helper_page_flip,
> + .reset = drm_atomic_helper_crtc_reset,
> + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
> +};
> +
> +/*
> + * DRM_PLANE
> + */
> +
> +static int ltdc_plane_atomic_check(struct drm_plane *plane,
> + struct drm_plane_state *state)
> +{
> + struct drm_framebuffer *fb = state->fb;
> + u32 src_x, src_y, src_w, src_h;
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + if (!fb)
> + return 0;
> +
> + /* convert src_ from 16:16 format */
> + src_x = state->src_x >> 16;
> + src_y = state->src_y >> 16;
> + src_w = state->src_w >> 16;
> + src_h = state->src_h >> 16;
> +
> + /* Reject scaling */
> + if ((src_w != state->crtc_w) || (src_h != state->crtc_h)) {
> + DRM_ERROR("Scaling is not supported");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static void ltdc_plane_atomic_update(struct drm_plane *plane,
> + struct drm_plane_state *oldstate)
> +{
> + struct ltdc_device *ldev = plane_to_ltdc(plane);
> + struct drm_plane_state *state = plane->state;
> + struct drm_framebuffer *fb = state->fb;
> + u32 lofs = plane->index * LAY_OFS;
> + u32 x0 = state->crtc_x;
> + u32 x1 = state->crtc_x + state->crtc_w - 1;
> + u32 y0 = state->crtc_y;
> + u32 y1 = state->crtc_y + state->crtc_h - 1;
> + u32 src_x, src_y, src_w, src_h;
> + u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr;
> + enum ltdc_pix_fmt pf;
> +
> + if (!state->crtc || !fb) {
> + DRM_DEBUG_DRIVER("fb or crtc NULL");
> + return;
> + }
> +
> + /* convert src_ from 16:16 format */
> + src_x = state->src_x >> 16;
> + src_y = state->src_y >> 16;
> + src_w = state->src_w >> 16;
> + src_h = state->src_h >> 16;
> +
> + DRM_DEBUG_DRIVER(
> + "plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
> + plane->base.id, fb->base.id,
> + src_w, src_h, src_x, src_y,
> + state->crtc_w, state->crtc_h, state->crtc_x, state->crtc_y);
> +
> + bpcr = reg_read(ldev->regs, LTDC_BPCR);
> + ahbp = (bpcr & BPCR_AHBP) >> 16;
> + avbp = bpcr & BPCR_AVBP;
> +
> + /* Configures the horizontal start and stop position */
> + val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp);
> + reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs,
> + LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
> +
> + /* Configures the vertical start and stop position */
> + val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp);
> + reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs,
> + LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
> +
> + /* Specifies the pixel format */
> + pf = to_ltdc_pixelformat(fb->format->format);
> + for (val = 0; val < NB_PF; val++)
> + if (ldev->caps.pix_fmt_hw[val] == pf)
> + break;
> +
> + if (val == NB_PF) {
> + DRM_ERROR("Pixel format %.4s not supported\n",
> + (char *)&fb->format->format);
> + val = 0; /* set by default ARGB 32 bits */
> + }
> + reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
> +
> + /* Configures the color frame buffer pitch in bytes & line length */
> + pitch_in_bytes = fb->pitches[0];
> + line_length = drm_format_plane_cpp(fb->format->format, 0) *
> + (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
> + val = ((pitch_in_bytes << 16) | line_length);
> + reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs,
> + LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
> +
> + /* Specifies the constant alpha value */
> + val = CONSTA_MAX;
> + reg_update_bits(ldev->regs, LTDC_L1CACR + lofs,
> + LXCACR_CONSTA, val);
> +
> + /* Specifies the blending factors */
> + val = BF1_PAXCA | BF2_1PAXCA;
> + reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs,
> + LXBFCR_BF2 | LXBFCR_BF1, val);
> +
> + /* Configures the frame buffer line number */
> + val = y1 - y0 + 1;
> + reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs,
> + LXCFBLNR_CFBLN, val);
> +
> + /* Sets the FB address */
> + paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0);
> +
> + DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr);
> + reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr);
> +
> + /* Enable layer and CLUT if needed */
> + val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0;
> + val |= LXCR_LEN;
> + reg_update_bits(ldev->regs, LTDC_L1CR + lofs,
> + LXCR_LEN | LXCR_CLUTEN, val);
> +
> + mutex_lock(&ldev->err_lock);
> + if (ldev->error_status & ISR_FUIF) {
> + DRM_DEBUG_DRIVER("Fifo underrun\n");
> + ldev->error_status &= ~ISR_FUIF;
> + }
> + if (ldev->error_status & ISR_TERRIF) {
> + DRM_DEBUG_DRIVER("Transfer error\n");
> + ldev->error_status &= ~ISR_TERRIF;
> + }
> + mutex_unlock(&ldev->err_lock);
> +}
> +
> +static void ltdc_plane_atomic_disable(struct drm_plane *plane,
> + struct drm_plane_state *oldstate)
> +{
> + struct ltdc_device *ldev = plane_to_ltdc(plane);
> + u32 lofs = plane->index * LAY_OFS;
> +
> + /* disable layer */
> + reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN);
> +
> + DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
> + oldstate->crtc->base.id, plane->base.id);
> +}
> +
> +static struct drm_plane_funcs ltdc_plane_funcs = {
> + .update_plane = drm_atomic_helper_update_plane,
> + .disable_plane = drm_atomic_helper_disable_plane,
> + .destroy = drm_plane_cleanup,
> + .set_property = drm_atomic_helper_plane_set_property,
> + .reset = drm_atomic_helper_plane_reset,
> + .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
> +};
> +
> +static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
> + .atomic_check = ltdc_plane_atomic_check,
> + .atomic_update = ltdc_plane_atomic_update,
> + .atomic_disable = ltdc_plane_atomic_disable,
> +};
> +
> +static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
> + enum drm_plane_type type)
> +{
> + unsigned long possible_crtcs = CRTC_MASK;
> + struct ltdc_device *ldev = ddev->dev_private;
> + struct device *dev = ddev->dev;
> + struct drm_plane *plane;
> + unsigned int i, nb_fmt = 0;
> + u32 formats[NB_PF];
> + u32 drm_fmt;
> + int ret;
> +
> + /* Get supported pixel formats */
> + for (i = 0; i < NB_PF; i++) {
> + drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]);
> + if (!drm_fmt)
> + continue;
> + formats[nb_fmt++] = drm_fmt;
> + }
> +
> + plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
> + if (!plane)
> + return 0;
> +
> + ret = drm_universal_plane_init(ddev, plane, possible_crtcs,
> + <dc_plane_funcs, formats, nb_fmt,
> + type, NULL);
> + if (ret < 0)
> + return 0;
> +
> + drm_plane_helper_add(plane, <dc_plane_helper_funcs);
> +
> + DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
> +
> + return plane;
> +}
> +
> +static void ltdc_plane_destroy_all(struct drm_device *ddev)
> +{
> + struct drm_plane *plane, *plane_temp;
> +
> + list_for_each_entry_safe(plane, plane_temp,
> + &ddev->mode_config.plane_list, head)
> + drm_plane_cleanup(plane);
> +}
> +
> +static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
> +{
> + struct ltdc_device *ldev = ddev->dev_private;
> + struct drm_plane *primary, *overlay;
> + unsigned int i;
> + int res;
> +
> + primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY);
> + if (!primary) {
> + DRM_ERROR("Can not create primary plane\n");
> + return -EINVAL;
> + }
> +
> + res = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
> + <dc_crtc_funcs, NULL);
> + if (res) {
> + DRM_ERROR("Can not initialize CRTC\n");
> + goto cleanup;
> + }
> +
> + drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs);
> +
> + DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
> +
> + /* Add planes. Note : the first layer is used by primary plane */
> + for (i = 1; i < ldev->caps.nb_layers; i++) {
> + overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY);
> + if (!overlay) {
> + res = -ENOMEM;
> + DRM_ERROR("Can not create overlay plane %d\n", i);
> + goto cleanup;
> + }
> + }
> +
> + return 0;
> +
> +cleanup:
> + ltdc_plane_destroy_all(ddev);
> + return res;
> +}
> +
> +/*
> + * DRM_ENCODER
> + */
> +
> +static void ltdc_rgb_encoder_enable(struct drm_encoder *encoder)
> +{
> + struct ltdc_device *ldev = encoder_to_ltdc(encoder);
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + drm_panel_prepare(ldev->panel);
> + drm_panel_enable(ldev->panel);
> +}
> +
> +static void ltdc_rgb_encoder_disable(struct drm_encoder *encoder)
> +{
> + struct ltdc_device *ldev = encoder_to_ltdc(encoder);
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + drm_panel_disable(ldev->panel);
> + drm_panel_unprepare(ldev->panel);
> +}
> +
> +static const struct drm_encoder_helper_funcs ltdc_rgb_encoder_helper_funcs = {
> + .enable = ltdc_rgb_encoder_enable,
> + .disable = ltdc_rgb_encoder_disable,
> +};
> +
> +static const struct drm_encoder_funcs ltdc_rgb_encoder_funcs = {
> + .destroy = drm_encoder_cleanup,
> +};
> +
> +static struct drm_encoder *ltdc_rgb_encoder_create(struct drm_device *ddev)
> +{
> + struct drm_encoder *encoder;
> +
> + encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
> + if (!encoder)
> + return NULL;
> +
> + encoder->possible_crtcs = CRTC_MASK;
> + encoder->possible_clones = 0; /* No cloning support */
> +
> + drm_encoder_init(ddev, encoder, <dc_rgb_encoder_funcs,
> + DRM_MODE_ENCODER_DPI, NULL);
> +
> + drm_encoder_helper_add(encoder, <dc_rgb_encoder_helper_funcs);
> +
> + DRM_DEBUG_DRIVER("RGB encoder:%d created\n", encoder->base.id);
> +
> + return encoder;
> +}
> +
> +/*
> + * DRM_CONNECTOR
> + */
> +
> +static int ltdc_rgb_connector_get_modes(struct drm_connector *connector)
> +{
> + struct drm_device *ddev = connector->dev;
> + struct ltdc_device *ldev = ddev->dev_private;
> + int ret = 0;
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + if (ldev->panel)
> + ret = drm_panel_get_modes(ldev->panel);
> +
> + return ret < 0 ? 0 : ret;
> +}
> +
> +static struct drm_connector_helper_funcs ltdc_rgb_connector_helper_funcs = {
> + .get_modes = ltdc_rgb_connector_get_modes,
> +};
> +
> +static enum drm_connector_status
> +ltdc_rgb_connector_detect(struct drm_connector *connector, bool force)
> +{
> + struct ltdc_device *ldev = connector_to_ltdc(connector);
> +
> + return ldev->panel ? connector_status_connected :
> + connector_status_disconnected;
> +}
> +
> +static void ltdc_rgb_connector_destroy(struct drm_connector *connector)
> +{
> + DRM_DEBUG_DRIVER("\n");
> +
> + drm_connector_unregister(connector);
> + drm_connector_cleanup(connector);
> +}
> +
> +static const struct drm_connector_funcs ltdc_rgb_connector_funcs = {
> + .dpms = drm_atomic_helper_connector_dpms,
> + .fill_modes = drm_helper_probe_single_connector_modes,
> + .detect = ltdc_rgb_connector_detect,
> + .destroy = ltdc_rgb_connector_destroy,
> + .reset = drm_atomic_helper_connector_reset,
> + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> +};
> +
> +struct drm_connector *ltdc_rgb_connector_create(struct drm_device *ddev)
> +{
> + struct drm_connector *connector;
> + int err;
> +
> + connector = devm_kzalloc(ddev->dev, sizeof(*connector), GFP_KERNEL);
> + if (!connector) {
> + DRM_ERROR("Failed to allocate connector\n");
> + return NULL;
> + }
> +
> + connector->polled = DRM_CONNECTOR_POLL_HPD;
> +
> + err = drm_connector_init(ddev, connector, <dc_rgb_connector_funcs,
> + DRM_MODE_CONNECTOR_DPI);
> + if (err) {
> + DRM_ERROR("Failed to initialize connector\n");
> + return NULL;
> + }
> +
> + drm_connector_helper_add(connector, <dc_rgb_connector_helper_funcs);
> +
> + DRM_DEBUG_DRIVER("RGB connector:%d created\n", connector->base.id);
> +
> + return connector;
> +}
> +
> +static int ltdc_get_caps(struct drm_device *ddev)
> +{
> + struct ltdc_device *ldev = ddev->dev_private;
> + u32 bus_width_log2, lcr, gc2r;
> +
> + /* at least 1 layer must be managed */
> + lcr = reg_read(ldev->regs, LTDC_LCR);
> +
> + ldev->caps.nb_layers = max_t(int, lcr, 1);
> +
> + /* set data bus width */
> + gc2r = reg_read(ldev->regs, LTDC_GC2R);
> + bus_width_log2 = (gc2r & GC2R_BW) >> 4;
> + ldev->caps.bus_width = 8 << bus_width_log2;
> + ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR);
> +
> + switch (ldev->caps.hw_version) {
> + case HWVER_10200:
> + case HWVER_10300:
> + ldev->caps.reg_ofs = REG_OFS_NONE;
> + ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
> + break;
> + case HWVER_20101:
> + ldev->caps.reg_ofs = REG_OFS_4;
> + ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
> + break;
> + default:
> + return -ENODEV;
> + }
> +
> + return 0;
> +}
> +
> +static struct drm_panel *ltdc_get_panel(struct drm_device *ddev)
> +{
> + struct device *dev = ddev->dev;
> + struct device_node *np = dev->of_node;
> + struct device_node *entity, *port = NULL;
> + struct drm_panel *panel = NULL;
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + /*
> + * Parse ltdc node to get remote port and find RGB panel / HDMI slave
> + * If a dsi or a bridge (hdmi, lvds...) is connected to ltdc,
> + * a remote port & RGB panel will not be found.
> + */
> + for_each_endpoint_of_node(np, entity) {
> + if (!of_device_is_available(entity))
> + continue;
> +
> + port = of_graph_get_remote_port_parent(entity);
> + if (port) {
> + panel = of_drm_find_panel(port);
> + of_node_put(port);
> + if (panel) {
> + DRM_DEBUG_DRIVER("remote panel %s\n",
> + port->full_name);
> + } else {
> + DRM_DEBUG_DRIVER("panel missing\n");
> + of_node_put(entity);
> + }
> + }
> + }
> +
> + return panel;
> +}
> +
> +int ltdc_load(struct drm_device *ddev)
> +{
> + struct platform_device *pdev = to_platform_device(ddev->dev);
> + struct ltdc_device *ldev = ddev->dev_private;
> + struct device *dev = ddev->dev;
> + struct device_node *np = dev->of_node;
> + struct drm_encoder *encoder;
> + struct drm_connector *connector = NULL;
> + struct drm_crtc *crtc;
> + struct reset_control *rstc;
> + struct resource res;
> + int irq, ret, i;
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + ldev->panel = ltdc_get_panel(ddev);
> + if (!ldev->panel)
> + return -EPROBE_DEFER;
> +
> + rstc = of_reset_control_get(np, NULL);
> +
> + mutex_init(&ldev->err_lock);
> +
> + ldev->pixel_clk = devm_clk_get(dev, "lcd");
> + if (IS_ERR(ldev->pixel_clk)) {
> + DRM_ERROR("Unable to get lcd clock\n");
> + return -ENODEV;
> + }
> +
> + if (clk_prepare_enable(ldev->pixel_clk)) {
> + DRM_ERROR("Unable to prepare pixel clock\n");
> + return -ENODEV;
> + }
> +
> + if (of_address_to_resource(np, 0, &res)) {
> + DRM_ERROR("Unable to get resource\n");
> + return -ENODEV;
> + }
> +
> + ldev->regs = devm_ioremap_resource(dev, &res);
> + if (IS_ERR(ldev->regs)) {
> + DRM_ERROR("Unable to get ltdc registers\n");
> + return PTR_ERR(ldev->regs);
> + }
> +
> + for (i = 0; i < MAX_IRQ; i++) {
> + irq = platform_get_irq(pdev, i);
> + if (irq < 0)
> + continue;
> +
> + ret = devm_request_threaded_irq(dev, irq, ltdc_irq,
> + ltdc_irq_thread, IRQF_ONESHOT,
> + dev_name(dev), ddev);
> + if (ret) {
> + DRM_ERROR("Failed to register LTDC interrupt\n");
> + return ret;
> + }
> + }
> +
> + if (!IS_ERR(rstc))
> + reset_control_deassert(rstc);
> +
> + /* Disable interrupts */
> + reg_clear(ldev->regs, LTDC_IER,
> + IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE);
> +
> + ret = ltdc_get_caps(ddev);
> + if (ret) {
> + DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
> + ldev->caps.hw_version);
> + return ret;
> + }
> +
> + DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version);
> +
> + if (ldev->panel) {
> + encoder = ltdc_rgb_encoder_create(ddev);
> + if (!encoder) {
> + DRM_ERROR("Failed to create RGB encoder\n");
> + ret = -EINVAL;
> + goto err;
> + }
> +
> + connector = ltdc_rgb_connector_create(ddev);
> + if (!connector) {
> + DRM_ERROR("Failed to create RGB connector\n");
> + ret = -EINVAL;
> + goto err;
> + }
> +
> + ret = drm_mode_connector_attach_encoder(connector, encoder);
> + if (ret) {
> + DRM_ERROR("Failed to attach connector to encoder\n");
> + goto err;
> + }
> +
> + drm_panel_attach(ldev->panel, connector);
> + }
> +
> + crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
> + if (!crtc) {
> + DRM_ERROR("Failed to allocate crtc\n");
> + ret = -ENOMEM;
> + goto err;
> + }
> +
> + ret = ltdc_crtc_init(ddev, crtc);
> + if (ret) {
> + DRM_ERROR("Failed to init crtc\n");
> + goto err;
> + }
> +
> + ret = drm_vblank_init(ddev, NB_CRTC);
> + if (ret) {
> + DRM_ERROR("Failed calling drm_vblank_init()\n");
> + goto err;
> + }
> +
> + /* Allow usage of vblank without having to call drm_irq_install */
> + ddev->irq_enabled = 1;
> +
> + return 0;
> +err:
> + if (ldev->panel)
> + drm_panel_detach(ldev->panel);
> +
> + clk_disable_unprepare(ldev->pixel_clk);
> +
> + return ret;
> +}
> +
> +void ltdc_unload(struct drm_device *ddev)
> +{
> + struct ltdc_device *ldev = ddev->dev_private;
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + drm_vblank_cleanup(ddev);
> +
> + if (ldev->panel)
> + drm_panel_detach(ldev->panel);
> +
> + clk_disable_unprepare(ldev->pixel_clk);
> +}
> +
> +MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
> +MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
> +MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
> +MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
> +MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
> new file mode 100644
> index 0000000..d7a9c73
> --- /dev/null
> +++ b/drivers/gpu/drm/stm/ltdc.h
> @@ -0,0 +1,40 @@
> +/*
> + * Copyright (C) STMicroelectronics SA 2017
> + *
> + * Authors: Philippe Cornu <philippe.cornu@st.com>
> + * Yannick Fertre <yannick.fertre@st.com>
> + * Fabien Dessenne <fabien.dessenne@st.com>
> + * Mickael Reulier <mickael.reulier@st.com>
> + *
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#ifndef _LTDC_H_
> +#define _LTDC_H_
> +
> +struct ltdc_caps {
> + u32 hw_version; /* hardware version */
> + u32 nb_layers; /* number of supported layers */
> + u32 reg_ofs; /* register offset for applicable regs */
> + u32 bus_width; /* bus width (32 or 64 bits) */
> + const u32 *pix_fmt_hw; /* supported pixel formats */
> +};
> +
> +struct ltdc_device {
> + struct drm_fbdev_cma *fbdev;
> + void __iomem *regs;
> + struct clk *pixel_clk; /* lcd pixel clock */
> + struct drm_panel *panel;
> + struct mutex err_lock; /* protecting error_status */
> + struct ltdc_caps caps;
> + u32 clut[256]; /* color look up table */
> + u32 error_status;
> + u32 irq_status;
> +};
> +
> +int ltdc_crtc_enable_vblank(struct drm_device *dev, unsigned int pipe);
> +void ltdc_crtc_disable_vblank(struct drm_device *dev, unsigned int pipe);
> +int ltdc_load(struct drm_device *ddev);
> +void ltdc_unload(struct drm_device *ddev);
> +
> +#endif
>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH v7 2/9] drm/fb-cma-helper: Add drm_fb_cma_get_gem_addr()
From: Neil Armstrong @ 2017-04-14 12:54 UTC (permalink / raw)
To: Yannick Fertre, Alexandre TORGUE, Thierry Reding, David Airlie,
Maxime Coquelin, Russell King, Mark Rutland, Rob Herring,
Arnd Bergmann, Benjamin Gaignard
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, kernel-F5mvAk5X5gdBDgjK7y7TUQ,
Philippe Cornu, Fabien Dessenne,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Mickael Reulier,
Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1492164819-10513-3-git-send-email-yannick.fertre-qxv4g6HH51o@public.gmane.org>
On 04/14/2017 12:13 PM, Yannick Fertre wrote:
> Add function drm_fb_cma_get_gem_addr() which return the physical address
> of framebuffer (1st pixel). This function will usually be called by plane
> callback (atomic_update).
>
> Signed-off-by: Yannick Fertre <yannick.fertre-qxv4g6HH51o@public.gmane.org>
> ---
> drivers/gpu/drm/drm_fb_cma_helper.c | 27 +++++++++++++++++++++++++++
> include/drm/drm_fb_cma_helper.h | 4 ++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c b/drivers/gpu/drm/drm_fb_cma_helper.c
> index 50abd1f..d2b77b0 100644
> --- a/drivers/gpu/drm/drm_fb_cma_helper.c
> +++ b/drivers/gpu/drm/drm_fb_cma_helper.c
> @@ -260,6 +260,33 @@ struct drm_gem_cma_object *drm_fb_cma_get_gem_obj(struct drm_framebuffer *fb,
> EXPORT_SYMBOL_GPL(drm_fb_cma_get_gem_obj);
>
> /**
> + * drm_fb_cma_get_gem_addr() - Get physical address for framebuffer
> + * @fb: The framebuffer
> + * @state: Which state of drm plane
> + * @plane: Which plane
> + * Return the CMA GEM address for given framebuffer.
> + *
> + * This function will usually be called from the PLANE callback functions.
> + */
> +dma_addr_t drm_fb_cma_get_gem_addr(struct drm_framebuffer *fb,
> + struct drm_plane_state *state,
> + unsigned int plane)
> +{
> + struct drm_fb_cma *fb_cma = to_fb_cma(fb);
> + dma_addr_t paddr;
> +
> + if (plane >= 4)
> + return 0;
Nitpick, but why not using drm_fb_cma_get_gem_obj(fb, plane) here ?
=====
struct drm_gem_cma_object *gem = drm_fb_cma_get_gem_obj(fb, plane);
if (!gem)
return 0;
paddr = gem->paddr + fb->offsets[plane];
======
> +
> + paddr = fb_cma->obj[plane]->paddr + fb->offsets[plane];
> + paddr += fb->format->cpp[plane] * (state->src_x >> 16);
> + paddr += fb->pitches[plane] * (state->src_y >> 16);
> +
> + return paddr;
> +}
> +EXPORT_SYMBOL_GPL(drm_fb_cma_get_gem_addr);
> +
> +/**
> * drm_fb_cma_prepare_fb() - Prepare CMA framebuffer
> * @plane: Which plane
> * @state: Plane state attach fence to
> diff --git a/include/drm/drm_fb_cma_helper.h b/include/drm/drm_fb_cma_helper.h
> index a5ecc0a..199a63f 100644
> --- a/include/drm/drm_fb_cma_helper.h
> +++ b/include/drm/drm_fb_cma_helper.h
> @@ -41,6 +41,10 @@ struct drm_framebuffer *drm_fb_cma_create(struct drm_device *dev,
> struct drm_gem_cma_object *drm_fb_cma_get_gem_obj(struct drm_framebuffer *fb,
> unsigned int plane);
>
> +dma_addr_t drm_fb_cma_get_gem_addr(struct drm_framebuffer *fb,
> + struct drm_plane_state *state,
> + unsigned int plane);
> +
> int drm_fb_cma_prepare_fb(struct drm_plane *plane,
> struct drm_plane_state *state);
>
>
Anyway it's still ok,
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH v7 1/9] drm/cma: Update DEFINE_DRM_GEM_CMA_FOPS to add get_unmapped_area
From: Neil Armstrong @ 2017-04-14 12:49 UTC (permalink / raw)
To: Yannick Fertre, Alexandre TORGUE, Thierry Reding, David Airlie,
Maxime Coquelin, Russell King, Mark Rutland, Rob Herring,
Arnd Bergmann, Benjamin Gaignard
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, kernel-F5mvAk5X5gdBDgjK7y7TUQ,
Philippe Cornu, Fabien Dessenne,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Mickael Reulier,
Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1492164819-10513-2-git-send-email-yannick.fertre-qxv4g6HH51o@public.gmane.org>
On 04/14/2017 12:13 PM, Yannick Fertre wrote:
> Missing field get_unmapped_area which is necessary with device without MMU
>
> Signed-off-by: Yannick Fertre <yannick.fertre-qxv4g6HH51o@public.gmane.org>
> ---
> include/drm/drm_gem_cma_helper.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/drm/drm_gem_cma_helper.h b/include/drm/drm_gem_cma_helper.h
> index f962d33..7320b14 100644
> --- a/include/drm/drm_gem_cma_helper.h
> +++ b/include/drm/drm_gem_cma_helper.h
> @@ -50,6 +50,7 @@ struct drm_gem_cma_object {
> .read = drm_read,\
> .llseek = noop_llseek,\
> .mmap = drm_gem_cma_mmap,\
> + .get_unmapped_area = drm_gem_cma_get_unmapped_area,\
> }
>
> /* free GEM object */
>
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH 2/3] dt-bindings: hwmon: Add bindings for Google Chromium EC HWMON
From: Rob Herring @ 2017-04-14 12:48 UTC (permalink / raw)
To: Guenter Roeck
Cc: Moritz Fischer, linux-hwmon-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Lee Jones,
Olof Johansson, Jean Delvare, Mark Rutland, Moritz Fischer
In-Reply-To: <20170413210707.GA16304-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>
On Thu, Apr 13, 2017 at 4:07 PM, Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org> wrote:
> On Thu, Apr 13, 2017 at 03:01:40PM -0500, Rob Herring wrote:
>> On Fri, Apr 07, 2017 at 03:00:09PM -0700, Moritz Fischer wrote:
>> > From: Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> >
>> > Add bindings for the Chromium EC HWMON. The Chromium EC HWMON
>> > allows monitoring of temperature sensors and fans attached to the
>> > EC.
>> >
>> > Signed-off-by: Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> > ---
>> > .../devicetree/bindings/hwmon/cros-ec-hwmon.txt | 25 ++++++++++++++++++++++
>> > 1 file changed, 25 insertions(+)
>> > create mode 100644 Documentation/devicetree/bindings/hwmon/cros-ec-hwmon.txt
>> >
>> > diff --git a/Documentation/devicetree/bindings/hwmon/cros-ec-hwmon.txt b/Documentation/devicetree/bindings/hwmon/cros-ec-hwmon.txt
>> > new file mode 100644
>> > index 0000000..4c94869
>> > --- /dev/null
>> > +++ b/Documentation/devicetree/bindings/hwmon/cros-ec-hwmon.txt
>> > @@ -0,0 +1,25 @@
>> > +Chromium Embedded Controller EC temperature and fan control
>> > +-----------------------------------------------------------
>> > +
>> > +Google's Chromium EC HWMON is a hwmon implemented byimplemented by the Chromium EC
>> > +firmware attached to the Embedded Controller (EC) and controlled via a host-command
>> > +interface.
>> > +
>> > +An EC HWMON node should be only found as a sub-node of the EC node (see
>> > +Documentation/devicetree/bindings/mfd/cros-ec.txt).
>> > +
>> > +Required properties:
>> > +- compatible: Must contain "google,cros-ec-hwmon"
>> > +
>> > +Example:
>> > + embedded-controller@1e {
>> > + reg = <0x1e>;
>> > + compatible = "google,cros-ec-i2c";
>> > + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
>> > + interrupt-parent = <&gpio0>;
>> > +
>> > + hwmon {
>> > + compatible = "google,cros-ec-hwmon";
>>
>> This is sufficient for all devices? I don't see that DT provides
>> anything here other than instantiating a device, but the parent device
>> can just as easily do that.
>>
> The parent driver (drivers/mfd/cros_ec_i2c.c) calls cros_ec_register(),
> which uses uses of_platform_populate() to populate all sub-devices.
> There are various examples in the dts files (look for "google,cros-ec").
> Does it really make sense to start a second method for instantiating
> sub-devices ?
Okay, I suppose not. That wasn't clear from the example.
Rob
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^ permalink raw reply
* Re: [PATCH V5 2/2] thermal: broadcom: add Northstar thermal driver
From: Rafał Miłecki @ 2017-04-14 12:16 UTC (permalink / raw)
To: Eduardo Valentin, Rafał Miłecki
Cc: Mark Rutland, devicetree, Florian Fainelli, Scott Branden,
Stephen Warren, Ray Jui, linux-pm, Lee Jones, Jon Mason,
Eric Anholt, Rob Herring, bcm-kernel-feedback-list,
linux-rpi-kernel, Zhang Rui, linux-arm-kernel
In-Reply-To: <20170407044218.GA12447@localhost.localdomain>
On 04/07/2017 06:42 AM, Eduardo Valentin wrote:
> On Mon, Apr 03, 2017 at 05:48:29PM +0200, Rafał Miłecki wrote:
>> From: Rafał Miłecki <rafal@milecki.pl>
>>
>> Northstar is a SoC family commonly used in home routers. This commit
>> adds a driver for checking CPU temperature. As Northstar Plus seems to
>> also have this IP block this new symbol gets ARCH_BCM_IPROC dependency.
>>
>> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
>> Signed-off-by: Jon Mason <jon.mason@broadcom.com>
>
> If no objection, I am applying this series.
Cool, hopefully there aren't any more objections :) Once applied should I
expect this in
https://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git/log/?h=next
?
That would allow me to move bcm2835_thermal.c to the broadcom subdir.
>> +const struct thermal_zone_of_device_ops ns_thermal_ops = {
>
> minor correction here:
>
> -const struct thermal_zone_of_device_ops ns_thermal_ops = {
> +static const struct thermal_zone_of_device_ops ns_thermal_ops = {
>
> but I am applying this already in my tree.
>
>> + .get_temp = ns_thermal_get_temp,
>> +};
Thank you!
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH] ARM: dts: at91: use correct compatible for the gpio mux controller
From: Peter Rosin @ 2017-04-14 10:50 UTC (permalink / raw)
To: Alexandre Belloni
Cc: linux-kernel, Nicolas Ferre, Rob Herring, Mark Rutland,
Russell King, linux-arm-kernel, devicetree
In-Reply-To: <20170414100705.tiltc433lidqzcr2@piout.net>
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On April 14, 2017 12:07:05 PM GMT+02:00, Alexandre Belloni <alexandre.belloni@free-electrons.com> wrote:
>On 13/04/2017 at 23:22:58 +0200, Peter Rosin wrote:
>> The compatible string for a gpio based mux controller is "gpio-mux",
>> and nothing else.
>>
>> Fixes: 29dd89418007 ("ARM: dts: at91: add envelope detector mux to
>the Axentia TSE-850")
>> Signed-off-by: Peter Rosin <peda@axentia.se>
>> ---
>> arch/arm/boot/dts/at91-tse850-3.dts | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> Hi!
>>
>> The compatible string for the gpio based mux changed along the way
>(on
>> request from Rob) but I failed to update the implementation in the
>> gpio-mux driver when I made that change. Consequently, I didn't
>notice
>> that I didn't update the compatible string here either, since it all
>> continued to work in my tests...
>>
>> The compatible string in the gpio-mux driver is being fixed to match
>> documentation, so this of course needs fixing too. No TSE-850 devices
>> are affected, except for the one on my desk.
>>
>> Sorry for the churn.
>>
>
>So, I folded that one in the previous one and updated my pull request.
>Hopefully this will be OK.
>
>--
>Alexandre Belloni, Free Electrons
>Embedded Linux and Kernel engineering
>http://free-electrons.com
From my POV, excellent!
Cheers,
peda
--
Sent from my Android device with K-9 Mail. Please excuse my brevity.
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^ permalink raw reply
* [PATCH v7 9/9] ARM: configs: stm32: Add simple panel support in STM32 defconfig
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
Benjamin Gaignard, Yannick Fertre
Cc: devicetree, kernel, Philippe Cornu, Fabien Dessenne, dri-devel,
Mickael Reulier, Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
This patch adds simple panel support in stm32_defconfig file
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
arch/arm/configs/stm32_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index c2ff2e7..0d38263 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -49,6 +49,8 @@ CONFIG_SERIAL_STM32_CONSOLE=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_DRM=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_USB_SUPPORT is not set
--
1.9.1
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* [PATCH v7 8/9] ARM: configs: stm32: Add DRM support in STM32 defconfig
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
Benjamin Gaignard, Yannick Fertre
Cc: devicetree, kernel, Philippe Cornu, Fabien Dessenne, dri-devel,
Mickael Reulier, Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
This patch adds DRM (Direct Rendering Manager) support
in stm32_defconfig file
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
arch/arm/configs/stm32_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index a9d8e3c..c2ff2e7 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -48,6 +48,7 @@ CONFIG_SERIAL_STM32=y
CONFIG_SERIAL_STM32_CONSOLE=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
+CONFIG_DRM=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_USB_SUPPORT is not set
--
1.9.1
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* [PATCH v7 7/9] ARM: dts: stm32: Enable ltdc & simple panel on stm32f429-Eval board
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
Benjamin Gaignard, Yannick Fertre
Cc: devicetree, kernel, Philippe Cornu, Fabien Dessenne, dri-devel,
Mickael Reulier, Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
Enable ltdc & enable am-480272h3tmqw-t01h panel.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
arch/arm/boot/dts/stm32429i-eval.dts | 59 ++++++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 3c99466..631f08a 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -124,6 +124,65 @@
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>;
clock-names = "main_clk";
};
+
+ panel_rgb: panel-rgb {
+ compatible = "ampire,am-480272h3tmqw-t01h";
+ status = "okay";
+ port {
+ panel_in_rgb: endpoint {
+ remote-endpoint = <<dc_out_rgb>;
+ };
+ };
+ };
+};
+
+&pinctrl {
+ pinctrl_ltdc: ltdc@0 {
+ pins {
+ pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>,
+ <STM32F429_PI13_FUNC_LCD_VSYNC>,
+ <STM32F429_PI14_FUNC_LCD_CLK>,
+ <STM32F429_PI15_FUNC_LCD_R0>,
+ <STM32F429_PJ0_FUNC_LCD_R1>,
+ <STM32F429_PJ1_FUNC_LCD_R2>,
+ <STM32F429_PJ2_FUNC_LCD_R3>,
+ <STM32F429_PJ3_FUNC_LCD_R4>,
+ <STM32F429_PJ4_FUNC_LCD_R5>,
+ <STM32F429_PJ5_FUNC_LCD_R6>,
+ <STM32F429_PJ6_FUNC_LCD_R7>,
+ <STM32F429_PJ7_FUNC_LCD_G0>,
+ <STM32F429_PJ8_FUNC_LCD_G1>,
+ <STM32F429_PJ9_FUNC_LCD_G2>,
+ <STM32F429_PJ10_FUNC_LCD_G3>,
+ <STM32F429_PJ11_FUNC_LCD_G4>,
+ <STM32F429_PJ12_FUNC_LCD_B0>,
+ <STM32F429_PJ13_FUNC_LCD_B1>,
+ <STM32F429_PJ14_FUNC_LCD_B2>,
+ <STM32F429_PJ15_FUNC_LCD_B3>,
+ <STM32F429_PK0_FUNC_LCD_G5>,
+ <STM32F429_PK1_FUNC_LCD_G6>,
+ <STM32F429_PK2_FUNC_LCD_G7>,
+ <STM32F429_PK3_FUNC_LCD_B4>,
+ <STM32F429_PK4_FUNC_LCD_B5>,
+ <STM32F429_PK5_FUNC_LCD_B6>,
+ <STM32F429_PK6_FUNC_LCD_B7>,
+ <STM32F429_PK7_FUNC_LCD_DE>;
+ slew-rate = <2>;
+ };
+ };
+};
+
+<dc {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_ltdc>;
+ pinctrl-names = "default";
+ dma-ranges;
+
+ port {
+ ltdc_out_rgb: endpoint {
+ remote-endpoint = <&panel_in_rgb>;
+ };
+ };
};
&adc {
--
1.9.1
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* [PATCH v7 6/9] ARM: dts: stm32: Add ltdc support on stm32f429 MCU
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
Benjamin Gaignard, Yannick Fertre
Cc: devicetree, kernel, Philippe Cornu, Fabien Dessenne, dri-devel,
Mickael Reulier, Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
Add LTDC (Lcd-tft Display Controller) support.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index ee0da97..23debd9 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -543,7 +543,17 @@
reg = <0x40007000 0x400>;
};
- pin-controller {
+ ltdc: display-controller@40016800 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x40016800 0x200>;
+ interrupts = <88>, <89>;
+ resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
+ clocks = <&rcc 1 CLK_LCD>;
+ clock-names = "lcd";
+ status = "disabled";
+ };
+
+ pinctrl: pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32f429-pinctrl";
--
1.9.1
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* [PATCH v7 5/9] MAINTAINERS: add maintainers for DRM STM driver
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
Benjamin Gaignard, Yannick Fertre
Cc: devicetree, kernel, Philippe Cornu, Fabien Dessenne, dri-devel,
Mickael Reulier, Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
Add Philippe Cornu and myself as maintainers.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c36dfae..84cf73f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4424,6 +4424,15 @@ S: Maintained
F: drivers/gpu/drm/sti
F: Documentation/devicetree/bindings/display/st,stih4xx.txt
+DRM DRIVERS FOR STM
+M: Yannick Fertre <yannick.fertre@st.com>
+M: Philippe Cornu <philippe.cornu@st.com>
+L: dri-devel@lists.freedesktop.org
+T: git git://anongit.freedesktop.org/drm/drm-misc
+S: Maintained
+F: drivers/gpu/drm/stm
+F: Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
+
DRM DRIVER FOR TDFX VIDEO CARDS
S: Orphan / Obsolete
F: drivers/gpu/drm/tdfx/
--
1.9.1
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* [PATCH v7 4/9] drm/stm: Add STM32 LTDC driver
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
Benjamin Gaignard, Yannick Fertre
Cc: devicetree, kernel, Philippe Cornu, Fabien Dessenne, dri-devel,
Mickael Reulier, Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
This controller provides output signals to interface directly a variety
of LCD and TFT panels. These output signals are: RGB signals
(up to 24bpp), vertical & horizontal synchronisations, data enable and
the pixel clock.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/stm/Kconfig | 16 +
drivers/gpu/drm/stm/Makefile | 7 +
drivers/gpu/drm/stm/drv.c | 221 ++++++++
drivers/gpu/drm/stm/ltdc.c | 1161 ++++++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/stm/ltdc.h | 40 ++
7 files changed, 1448 insertions(+)
create mode 100644 drivers/gpu/drm/stm/Kconfig
create mode 100644 drivers/gpu/drm/stm/Makefile
create mode 100644 drivers/gpu/drm/stm/drv.c
create mode 100644 drivers/gpu/drm/stm/ltdc.c
create mode 100644 drivers/gpu/drm/stm/ltdc.h
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 78d7fc0..f57540d 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -246,6 +246,8 @@ source "drivers/gpu/drm/fsl-dcu/Kconfig"
source "drivers/gpu/drm/tegra/Kconfig"
+source "drivers/gpu/drm/stm/Kconfig"
+
source "drivers/gpu/drm/panel/Kconfig"
source "drivers/gpu/drm/bridge/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 59f0f9b..aa62ded 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -82,6 +82,7 @@ obj-$(CONFIG_DRM_BOCHS) += bochs/
obj-$(CONFIG_DRM_VIRTIO_GPU) += virtio/
obj-$(CONFIG_DRM_MSM) += msm/
obj-$(CONFIG_DRM_TEGRA) += tegra/
+obj-$(CONFIG_DRM_STM) += stm/
obj-$(CONFIG_DRM_STI) += sti/
obj-$(CONFIG_DRM_IMX) += imx/
obj-$(CONFIG_DRM_MEDIATEK) += mediatek/
diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig
new file mode 100644
index 0000000..2c4817f
--- /dev/null
+++ b/drivers/gpu/drm/stm/Kconfig
@@ -0,0 +1,16 @@
+config DRM_STM
+ tristate "DRM Support for STMicroelectronics SoC Series"
+ depends on DRM && (ARCH_STM32 || ARCH_MULTIPLATFORM)
+ select DRM_KMS_HELPER
+ select DRM_GEM_CMA_HELPER
+ select DRM_KMS_CMA_HELPER
+ select DRM_PANEL
+ select VIDEOMODE_HELPERS
+ select FB_PROVIDE_GET_FB_UNMAPPED_AREA
+ default y
+
+ help
+ Enable support for the on-chip display controller on
+ STMicroelectronics STM32 MCUs.
+ To compile this driver as a module, choose M here: the module
+ will be called stm-drm.
diff --git a/drivers/gpu/drm/stm/Makefile b/drivers/gpu/drm/stm/Makefile
new file mode 100644
index 0000000..e114d45
--- /dev/null
+++ b/drivers/gpu/drm/stm/Makefile
@@ -0,0 +1,7 @@
+ccflags-y := -Iinclude/drm
+
+stm-drm-y := \
+ drv.o \
+ ltdc.o
+
+obj-$(CONFIG_DRM_STM) += stm-drm.o
diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c
new file mode 100644
index 0000000..83ab48f
--- /dev/null
+++ b/drivers/gpu/drm/stm/drv.c
@@ -0,0 +1,221 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * Authors: Philippe Cornu <philippe.cornu@st.com>
+ * Yannick Fertre <yannick.fertre@st.com>
+ * Fabien Dessenne <fabien.dessenne@st.com>
+ * Mickael Reulier <mickael.reulier@st.com>
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/component.h>
+#include <linux/of_platform.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+
+#include "ltdc.h"
+
+#define DRIVER_NAME "stm"
+#define DRIVER_DESC "STMicroelectronics SoC DRM"
+#define DRIVER_DATE "20170330"
+#define DRIVER_MAJOR 1
+#define DRIVER_MINOR 0
+#define DRIVER_PATCH_LEVEL 0
+
+#define STM_MAX_FB_WIDTH 2048
+#define STM_MAX_FB_HEIGHT 2048 /* same as width to handle orientation */
+
+static void drv_output_poll_changed(struct drm_device *ddev)
+{
+ struct ltdc_device *ldev = ddev->dev_private;
+
+ drm_fbdev_cma_hotplug_event(ldev->fbdev);
+}
+
+static const struct drm_mode_config_funcs drv_mode_config_funcs = {
+ .fb_create = drm_fb_cma_create,
+ .output_poll_changed = drv_output_poll_changed,
+ .atomic_check = drm_atomic_helper_check,
+ .atomic_commit = drm_atomic_helper_commit,
+};
+
+static void drv_lastclose(struct drm_device *ddev)
+{
+ struct ltdc_device *ldev = ddev->dev_private;
+
+ DRM_DEBUG("%s\n", __func__);
+
+ drm_fbdev_cma_restore_mode(ldev->fbdev);
+}
+
+DEFINE_DRM_GEM_CMA_FOPS(drv_driver_fops);
+
+static struct drm_driver drv_driver = {
+ .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
+ DRIVER_ATOMIC,
+ .lastclose = drv_lastclose,
+ .name = DRIVER_NAME,
+ .desc = DRIVER_DESC,
+ .date = DRIVER_DATE,
+ .major = DRIVER_MAJOR,
+ .minor = DRIVER_MINOR,
+ .patchlevel = DRIVER_PATCH_LEVEL,
+ .fops = &drv_driver_fops,
+ .dumb_create = drm_gem_cma_dumb_create,
+ .dumb_map_offset = drm_gem_cma_dumb_map_offset,
+ .dumb_destroy = drm_gem_dumb_destroy,
+ .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
+ .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
+ .gem_free_object_unlocked = drm_gem_cma_free_object,
+ .gem_vm_ops = &drm_gem_cma_vm_ops,
+ .gem_prime_export = drm_gem_prime_export,
+ .gem_prime_import = drm_gem_prime_import,
+ .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
+ .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
+ .gem_prime_vmap = drm_gem_cma_prime_vmap,
+ .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
+ .gem_prime_mmap = drm_gem_cma_prime_mmap,
+ .enable_vblank = ltdc_crtc_enable_vblank,
+ .disable_vblank = ltdc_crtc_disable_vblank,
+};
+
+static int drv_load(struct drm_device *ddev)
+{
+ struct platform_device *pdev = to_platform_device(ddev->dev);
+ struct drm_fbdev_cma *fbdev;
+ struct ltdc_device *ldev;
+ int ret;
+
+ DRM_DEBUG("%s\n", __func__);
+
+ ldev = devm_kzalloc(ddev->dev, sizeof(*ldev), GFP_KERNEL);
+ if (!ldev)
+ return -ENOMEM;
+
+ ddev->dev_private = (void *)ldev;
+
+ drm_mode_config_init(ddev);
+
+ /*
+ * set max width and height as default value.
+ * this value would be used to check framebuffer size limitation
+ * at drm_mode_addfb().
+ */
+ ddev->mode_config.min_width = 0;
+ ddev->mode_config.min_height = 0;
+ ddev->mode_config.max_width = STM_MAX_FB_WIDTH;
+ ddev->mode_config.max_height = STM_MAX_FB_HEIGHT;
+ ddev->mode_config.funcs = &drv_mode_config_funcs;
+
+ ret = ltdc_load(ddev);
+ if (ret)
+ goto err;
+
+ drm_mode_config_reset(ddev);
+ drm_kms_helper_poll_init(ddev);
+
+ if (ddev->mode_config.num_connector) {
+ ldev = ddev->dev_private;
+ fbdev = drm_fbdev_cma_init(ddev, 16,
+ ddev->mode_config.num_connector);
+ if (IS_ERR(fbdev)) {
+ DRM_DEBUG("Warning: fails to create fbdev\n");
+ fbdev = NULL;
+ }
+ ldev->fbdev = fbdev;
+ }
+
+ platform_set_drvdata(pdev, ddev);
+
+ return 0;
+err:
+ drm_mode_config_cleanup(ddev);
+ return ret;
+}
+
+static void drv_unload(struct drm_device *ddev)
+{
+ struct ltdc_device *ldev = ddev->dev_private;
+
+ DRM_DEBUG("%s\n", __func__);
+
+ if (ldev->fbdev) {
+ drm_fbdev_cma_fini(ldev->fbdev);
+ ldev->fbdev = NULL;
+ }
+ drm_kms_helper_poll_fini(ddev);
+ ltdc_unload(ddev);
+ drm_mode_config_cleanup(ddev);
+}
+
+static int stm_drm_platform_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct drm_device *ddev;
+ int ret;
+
+ DRM_DEBUG("%s\n", __func__);
+
+ dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
+
+ ddev = drm_dev_alloc(&drv_driver, dev);
+ if (IS_ERR(ddev))
+ return PTR_ERR(ddev);
+
+ ret = drv_load(ddev);
+ if (ret)
+ goto err_unref;
+
+ ret = drm_dev_register(ddev, 0);
+ if (ret)
+ goto err_unref;
+
+ return 0;
+
+err_unref:
+ drm_dev_unref(ddev);
+
+ return ret;
+}
+
+static int stm_drm_platform_remove(struct platform_device *pdev)
+{
+ struct drm_device *ddev = platform_get_drvdata(pdev);
+
+ DRM_DEBUG("%s\n", __func__);
+
+ drm_dev_unregister(ddev);
+ drv_unload(ddev);
+ drm_dev_unref(ddev);
+
+ return 0;
+}
+
+static const struct of_device_id drv_dt_ids[] = {
+ { .compatible = "st,stm32-ltdc"},
+ { /* end node */ },
+};
+MODULE_DEVICE_TABLE(of, drv_dt_ids);
+
+static struct platform_driver stm_drm_platform_driver = {
+ .probe = stm_drm_platform_probe,
+ .remove = stm_drm_platform_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = drv_dt_ids,
+ },
+};
+
+module_platform_driver(stm_drm_platform_driver);
+
+MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
+MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
+MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
+MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
+MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
new file mode 100644
index 0000000..a373178
--- /dev/null
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -0,0 +1,1161 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * Authors: Philippe Cornu <philippe.cornu@st.com>
+ * Yannick Fertre <yannick.fertre@st.com>
+ * Fabien Dessenne <fabien.dessenne@st.com>
+ * Mickael Reulier <mickael.reulier@st.com>
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_address.h>
+#include <linux/of_graph.h>
+#include <linux/reset.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_plane_helper.h>
+
+#include <video/videomode.h>
+
+#include "ltdc.h"
+
+#define NB_CRTC 1
+#define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
+
+#define MAX_IRQ 4
+
+#define HWVER_10200 0x010200
+#define HWVER_10300 0x010300
+#define HWVER_20101 0x020101
+
+/*
+ * The address of some registers depends on the HW version: such registers have
+ * an extra offset specified with reg_ofs.
+ */
+#define REG_OFS_NONE 0
+#define REG_OFS_4 4 /* Insertion of "Layer Configuration 2" reg */
+#define REG_OFS (ldev->caps.reg_ofs)
+#define LAY_OFS 0x80 /* Register Offset between 2 layers */
+
+/* Global register offsets */
+#define LTDC_IDR 0x0000 /* IDentification */
+#define LTDC_LCR 0x0004 /* Layer Count */
+#define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */
+#define LTDC_BPCR 0x000C /* Back Porch Configuration */
+#define LTDC_AWCR 0x0010 /* Active Width Configuration */
+#define LTDC_TWCR 0x0014 /* Total Width Configuration */
+#define LTDC_GCR 0x0018 /* Global Control */
+#define LTDC_GC1R 0x001C /* Global Configuration 1 */
+#define LTDC_GC2R 0x0020 /* Global Configuration 2 */
+#define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */
+#define LTDC_GACR 0x0028 /* GAmma Correction */
+#define LTDC_BCCR 0x002C /* Background Color Configuration */
+#define LTDC_IER 0x0034 /* Interrupt Enable */
+#define LTDC_ISR 0x0038 /* Interrupt Status */
+#define LTDC_ICR 0x003C /* Interrupt Clear */
+#define LTDC_LIPCR 0x0040 /* Line Interrupt Position Configuration */
+#define LTDC_CPSR 0x0044 /* Current Position Status */
+#define LTDC_CDSR 0x0048 /* Current Display Status */
+
+/* Layer register offsets */
+#define LTDC_L1LC1R (0x0080) /* L1 Layer Configuration 1 */
+#define LTDC_L1LC2R (0x0084) /* L1 Layer Configuration 2 */
+#define LTDC_L1CR (0x0084 + REG_OFS) /* L1 Control */
+#define LTDC_L1WHPCR (0x0088 + REG_OFS) /* L1 Window Hor Position Config */
+#define LTDC_L1WVPCR (0x008C + REG_OFS) /* L1 Window Vert Position Config */
+#define LTDC_L1CKCR (0x0090 + REG_OFS) /* L1 Color Keying Configuration */
+#define LTDC_L1PFCR (0x0094 + REG_OFS) /* L1 Pixel Format Configuration */
+#define LTDC_L1CACR (0x0098 + REG_OFS) /* L1 Constant Alpha Config */
+#define LTDC_L1DCCR (0x009C + REG_OFS) /* L1 Default Color Configuration */
+#define LTDC_L1BFCR (0x00A0 + REG_OFS) /* L1 Blend Factors Configuration */
+#define LTDC_L1FBBCR (0x00A4 + REG_OFS) /* L1 FrameBuffer Bus Control */
+#define LTDC_L1AFBCR (0x00A8 + REG_OFS) /* L1 AuxFB Control */
+#define LTDC_L1CFBAR (0x00AC + REG_OFS) /* L1 Color FrameBuffer Address */
+#define LTDC_L1CFBLR (0x00B0 + REG_OFS) /* L1 Color FrameBuffer Length */
+#define LTDC_L1CFBLNR (0x00B4 + REG_OFS) /* L1 Color FrameBuffer Line Nb */
+#define LTDC_L1AFBAR (0x00B8 + REG_OFS) /* L1 AuxFB Address */
+#define LTDC_L1AFBLR (0x00BC + REG_OFS) /* L1 AuxFB Length */
+#define LTDC_L1AFBLNR (0x00C0 + REG_OFS) /* L1 AuxFB Line Number */
+#define LTDC_L1CLUTWR (0x00C4 + REG_OFS) /* L1 CLUT Write */
+#define LTDC_L1YS1R (0x00E0 + REG_OFS) /* L1 YCbCr Scale 1 */
+#define LTDC_L1YS2R (0x00E4 + REG_OFS) /* L1 YCbCr Scale 2 */
+
+/* Bit definitions */
+#define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
+#define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
+
+#define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
+#define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
+
+#define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
+#define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
+
+#define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
+#define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
+
+#define GCR_LTDCEN BIT(0) /* LTDC ENable */
+#define GCR_DEN BIT(16) /* Dither ENable */
+#define GCR_PCPOL BIT(28) /* Pixel Clock POLarity */
+#define GCR_DEPOL BIT(29) /* Data Enable POLarity */
+#define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity */
+#define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity */
+
+#define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
+#define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
+#define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
+#define GC1R_PBEN BIT(12) /* Precise Blending ENable */
+#define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
+#define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
+#define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
+#define GC1R_BCP BIT(22) /* Background Colour Programmable */
+#define GC1R_BBEN BIT(23) /* Background Blending ENabled */
+#define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
+#define GC1R_TP BIT(25) /* Timing Programmable */
+#define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
+#define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
+#define GC1R_DWP BIT(28) /* Dither Width Programmable */
+#define GC1R_STREN BIT(29) /* STatus Registers ENabled */
+#define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
+
+#define GC2R_EDCA BIT(0) /* External Display Control Ability */
+#define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
+#define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
+#define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
+#define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
+#define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
+
+#define SRCR_IMR BIT(0) /* IMmediate Reload */
+#define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
+
+#define BCCR_BCBLACK 0x00 /* Background Color BLACK */
+#define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */
+#define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */
+#define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */
+#define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */
+
+#define IER_LIE BIT(0) /* Line Interrupt Enable */
+#define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */
+#define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */
+#define IER_RRIE BIT(3) /* Register Reload Interrupt enable */
+
+#define ISR_LIF BIT(0) /* Line Interrupt Flag */
+#define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */
+#define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */
+#define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */
+
+#define LXCR_LEN BIT(0) /* Layer ENable */
+#define LXCR_COLKEN BIT(1) /* Color Keying Enable */
+#define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
+
+#define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
+#define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
+
+#define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
+#define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
+
+#define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
+
+#define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
+
+#define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
+#define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
+
+#define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
+#define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
+
+#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
+
+#define HSPOL_AL 0 /* Horizontal Sync POLarity Active Low */
+#define VSPOL_AL 0 /* Vertical Sync POLarity Active Low */
+#define DEPOL_AL 0 /* Data Enable POLarity Active Low */
+#define PCPOL_IPC 0 /* Input Pixel Clock */
+#define HSPOL_AH GCR_HSPOL /* Horizontal Sync POLarity Active High */
+#define VSPOL_AH GCR_VSPOL /* Vertical Sync POLarity Active High */
+#define DEPOL_AH GCR_DEPOL /* Data Enable POLarity Active High */
+#define PCPOL_IIPC GCR_PCPOL /* Inverted Input Pixel Clock */
+#define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */
+#define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
+#define BF1_CA 0x400 /* Constant Alpha */
+#define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
+#define BF2_1CA 0x005 /* 1 - Constant Alpha */
+
+#define NB_PF 8 /* Max nb of HW pixel format */
+
+enum ltdc_pix_fmt {
+ PF_NONE,
+ /* RGB formats */
+ PF_ARGB8888, /* ARGB [32 bits] */
+ PF_RGBA8888, /* RGBA [32 bits] */
+ PF_RGB888, /* RGB [24 bits] */
+ PF_RGB565, /* RGB [16 bits] */
+ PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */
+ PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
+ /* Indexed formats */
+ PF_L8, /* Indexed 8 bits [8 bits] */
+ PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */
+ PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */
+};
+
+/* The index gives the encoding of the pixel format for an HW version */
+static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = {
+ PF_ARGB8888, /* 0x00 */
+ PF_RGB888, /* 0x01 */
+ PF_RGB565, /* 0x02 */
+ PF_ARGB1555, /* 0x03 */
+ PF_ARGB4444, /* 0x04 */
+ PF_L8, /* 0x05 */
+ PF_AL44, /* 0x06 */
+ PF_AL88 /* 0x07 */
+};
+
+static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
+ PF_ARGB8888, /* 0x00 */
+ PF_RGB888, /* 0x01 */
+ PF_RGB565, /* 0x02 */
+ PF_RGBA8888, /* 0x03 */
+ PF_AL44, /* 0x04 */
+ PF_L8, /* 0x05 */
+ PF_ARGB1555, /* 0x06 */
+ PF_ARGB4444 /* 0x07 */
+};
+
+static inline u32 reg_read(void __iomem *base, u32 reg)
+{
+ return readl_relaxed(base + reg);
+}
+
+static inline void reg_write(void __iomem *base, u32 reg, u32 val)
+{
+ writel_relaxed(val, base + reg);
+}
+
+static inline void reg_set(void __iomem *base, u32 reg, u32 mask)
+{
+ reg_write(base, reg, reg_read(base, reg) | mask);
+}
+
+static inline void reg_clear(void __iomem *base, u32 reg, u32 mask)
+{
+ reg_write(base, reg, reg_read(base, reg) & ~mask);
+}
+
+static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask,
+ u32 val)
+{
+ reg_write(base, reg, (reg_read(base, reg) & ~mask) | val);
+}
+
+static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc)
+{
+ return (struct ltdc_device *)crtc->dev->dev_private;
+}
+
+static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane)
+{
+ return (struct ltdc_device *)plane->dev->dev_private;
+}
+
+static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc)
+{
+ return (struct ltdc_device *)enc->dev->dev_private;
+}
+
+static inline struct ltdc_device *connector_to_ltdc(struct drm_connector *con)
+{
+ return (struct ltdc_device *)con->dev->dev_private;
+}
+
+static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
+{
+ enum ltdc_pix_fmt pf;
+
+ switch (drm_fmt) {
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XRGB8888:
+ pf = PF_ARGB8888;
+ break;
+ case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_RGBX8888:
+ pf = PF_RGBA8888;
+ break;
+ case DRM_FORMAT_RGB888:
+ pf = PF_RGB888;
+ break;
+ case DRM_FORMAT_RGB565:
+ pf = PF_RGB565;
+ break;
+ case DRM_FORMAT_ARGB1555:
+ case DRM_FORMAT_XRGB1555:
+ pf = PF_ARGB1555;
+ break;
+ case DRM_FORMAT_ARGB4444:
+ case DRM_FORMAT_XRGB4444:
+ pf = PF_ARGB4444;
+ break;
+ case DRM_FORMAT_C8:
+ pf = PF_L8;
+ break;
+ default:
+ pf = PF_NONE;
+ break;
+ /* Note: There are no DRM_FORMAT for AL44 and AL88 */
+ }
+
+ return pf;
+}
+
+static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf)
+{
+ switch (pf) {
+ case PF_ARGB8888:
+ return DRM_FORMAT_ARGB8888;
+ case PF_RGBA8888:
+ return DRM_FORMAT_RGBA8888;
+ case PF_RGB888:
+ return DRM_FORMAT_RGB888;
+ case PF_RGB565:
+ return DRM_FORMAT_RGB565;
+ case PF_ARGB1555:
+ return DRM_FORMAT_ARGB1555;
+ case PF_ARGB4444:
+ return DRM_FORMAT_ARGB4444;
+ case PF_L8:
+ return DRM_FORMAT_C8;
+ case PF_AL44: /* No DRM support */
+ case PF_AL88: /* No DRM support */
+ case PF_NONE:
+ default:
+ return 0;
+ }
+}
+
+static irqreturn_t ltdc_irq_thread(int irq, void *arg)
+{
+ struct drm_device *ddev = arg;
+ struct ltdc_device *ldev = ddev->dev_private;
+ struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0);
+
+ /* Line IRQ : trigger the vblank event */
+ if (ldev->irq_status & ISR_LIF)
+ drm_crtc_handle_vblank(crtc);
+
+ /* Save FIFO Underrun & Transfer Error status */
+ mutex_lock(&ldev->err_lock);
+ if (ldev->irq_status & ISR_FUIF)
+ ldev->error_status |= ISR_FUIF;
+ if (ldev->irq_status & ISR_TERRIF)
+ ldev->error_status |= ISR_TERRIF;
+ mutex_unlock(&ldev->err_lock);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t ltdc_irq(int irq, void *arg)
+{
+ struct drm_device *ddev = arg;
+ struct ltdc_device *ldev = ddev->dev_private;
+
+ /* Read & Clear the interrupt status */
+ ldev->irq_status = reg_read(ldev->regs, LTDC_ISR);
+ reg_write(ldev->regs, LTDC_ICR, ldev->irq_status);
+
+ return IRQ_WAKE_THREAD;
+}
+
+/*
+ * DRM_CRTC
+ */
+
+static void ltdc_crtc_load_lut(struct drm_crtc *crtc)
+{
+ struct ltdc_device *ldev = crtc_to_ltdc(crtc);
+ unsigned int i, lay;
+
+ for (lay = 0; lay < ldev->caps.nb_layers; lay++)
+ for (i = 0; i < 256; i++)
+ reg_write(ldev->regs, LTDC_L1CLUTWR + lay * LAY_OFS,
+ ldev->clut[i]);
+}
+
+static void ltdc_crtc_enable(struct drm_crtc *crtc)
+{
+ struct ltdc_device *ldev = crtc_to_ltdc(crtc);
+
+ DRM_DEBUG_DRIVER("\n");
+
+ /* Sets the background color value */
+ reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK);
+
+ /* Enable IRQ */
+ reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
+
+ /* Immediately commit the planes */
+ reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
+
+ /* Enable LTDC */
+ reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN);
+
+ drm_crtc_vblank_on(crtc);
+}
+
+static void ltdc_crtc_disable(struct drm_crtc *crtc)
+{
+ struct ltdc_device *ldev = crtc_to_ltdc(crtc);
+ struct drm_pending_vblank_event *event = crtc->state->event;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ drm_crtc_vblank_off(crtc);
+
+ /* disable LTDC */
+ reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN);
+
+ /* disable IRQ */
+ reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
+
+ /* immediately commit disable of layers before switching off LTDC */
+ reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
+}
+
+static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
+{
+ struct ltdc_device *ldev = crtc_to_ltdc(crtc);
+ struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+ struct videomode vm;
+ int rate = mode->clock * 1000;
+ u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
+ u32 total_width, total_height;
+ u32 val;
+
+ drm_display_mode_to_videomode(mode, &vm);
+
+ DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name);
+ DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive);
+ DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
+ vm.hfront_porch, vm.hback_porch, vm.hsync_len,
+ vm.vfront_porch, vm.vback_porch, vm.vsync_len);
+
+ /* Convert video timings to ltdc timings */
+ hsync = vm.hsync_len - 1;
+ vsync = vm.vsync_len - 1;
+ accum_hbp = hsync + vm.hback_porch;
+ accum_vbp = vsync + vm.vback_porch;
+ accum_act_w = accum_hbp + vm.hactive;
+ accum_act_h = accum_vbp + vm.vactive;
+ total_width = accum_act_w + vm.hfront_porch;
+ total_height = accum_act_h + vm.vfront_porch;
+
+ clk_disable(ldev->pixel_clk);
+
+ if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
+ DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
+ return;
+ }
+
+ clk_enable(ldev->pixel_clk);
+
+ /* Configures the HS, VS, DE and PC polarities. */
+ val = HSPOL_AL | HSPOL_AL | DEPOL_AL | PCPOL_IPC;
+
+ if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
+ val |= HSPOL_AH;
+
+ if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
+ val |= VSPOL_AH;
+
+ if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
+ val |= DEPOL_AH;
+
+ if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+ val |= PCPOL_IIPC;
+
+ reg_update_bits(ldev->regs, LTDC_GCR,
+ GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
+
+ /* Set Synchronization size */
+ val = (hsync << 16) | vsync;
+ reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
+
+ /* Set Accumulated Back porch */
+ val = (accum_hbp << 16) | accum_vbp;
+ reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
+
+ /* Set Accumulated Active Width */
+ val = (accum_act_w << 16) | accum_act_h;
+ reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
+
+ /* Set total width & height */
+ val = (total_width << 16) | total_height;
+ reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
+
+ reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1));
+}
+
+static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
+ struct drm_crtc_state *old_crtc_state)
+{
+ struct ltdc_device *ldev = crtc_to_ltdc(crtc);
+ struct drm_pending_vblank_event *event = crtc->state->event;
+
+ DRM_DEBUG_ATOMIC("\n");
+
+ /* Commit shadow registers = update planes at next vblank */
+ reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
+
+ if (event) {
+ crtc->state->event = NULL;
+
+ spin_lock_irq(&crtc->dev->event_lock);
+ if (drm_crtc_vblank_get(crtc) == 0)
+ drm_crtc_arm_vblank_event(crtc, event);
+ else
+ drm_crtc_send_vblank_event(crtc, event);
+ spin_unlock_irq(&crtc->dev->event_lock);
+ }
+}
+
+static struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
+ .load_lut = ltdc_crtc_load_lut,
+ .enable = ltdc_crtc_enable,
+ .disable = ltdc_crtc_disable,
+ .mode_set_nofb = ltdc_crtc_mode_set_nofb,
+ .atomic_flush = ltdc_crtc_atomic_flush,
+};
+
+int ltdc_crtc_enable_vblank(struct drm_device *ddev, unsigned int pipe)
+{
+ struct ltdc_device *ldev = ddev->dev_private;
+
+ DRM_DEBUG_DRIVER("\n");
+ reg_set(ldev->regs, LTDC_IER, IER_LIE);
+
+ return 0;
+}
+
+void ltdc_crtc_disable_vblank(struct drm_device *ddev, unsigned int pipe)
+{
+ struct ltdc_device *ldev = ddev->dev_private;
+
+ DRM_DEBUG_DRIVER("\n");
+ reg_clear(ldev->regs, LTDC_IER, IER_LIE);
+}
+
+static struct drm_crtc_funcs ltdc_crtc_funcs = {
+ .destroy = drm_crtc_cleanup,
+ .set_config = drm_atomic_helper_set_config,
+ .page_flip = drm_atomic_helper_page_flip,
+ .reset = drm_atomic_helper_crtc_reset,
+ .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
+};
+
+/*
+ * DRM_PLANE
+ */
+
+static int ltdc_plane_atomic_check(struct drm_plane *plane,
+ struct drm_plane_state *state)
+{
+ struct drm_framebuffer *fb = state->fb;
+ u32 src_x, src_y, src_w, src_h;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ if (!fb)
+ return 0;
+
+ /* convert src_ from 16:16 format */
+ src_x = state->src_x >> 16;
+ src_y = state->src_y >> 16;
+ src_w = state->src_w >> 16;
+ src_h = state->src_h >> 16;
+
+ /* Reject scaling */
+ if ((src_w != state->crtc_w) || (src_h != state->crtc_h)) {
+ DRM_ERROR("Scaling is not supported");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void ltdc_plane_atomic_update(struct drm_plane *plane,
+ struct drm_plane_state *oldstate)
+{
+ struct ltdc_device *ldev = plane_to_ltdc(plane);
+ struct drm_plane_state *state = plane->state;
+ struct drm_framebuffer *fb = state->fb;
+ u32 lofs = plane->index * LAY_OFS;
+ u32 x0 = state->crtc_x;
+ u32 x1 = state->crtc_x + state->crtc_w - 1;
+ u32 y0 = state->crtc_y;
+ u32 y1 = state->crtc_y + state->crtc_h - 1;
+ u32 src_x, src_y, src_w, src_h;
+ u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr;
+ enum ltdc_pix_fmt pf;
+
+ if (!state->crtc || !fb) {
+ DRM_DEBUG_DRIVER("fb or crtc NULL");
+ return;
+ }
+
+ /* convert src_ from 16:16 format */
+ src_x = state->src_x >> 16;
+ src_y = state->src_y >> 16;
+ src_w = state->src_w >> 16;
+ src_h = state->src_h >> 16;
+
+ DRM_DEBUG_DRIVER(
+ "plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
+ plane->base.id, fb->base.id,
+ src_w, src_h, src_x, src_y,
+ state->crtc_w, state->crtc_h, state->crtc_x, state->crtc_y);
+
+ bpcr = reg_read(ldev->regs, LTDC_BPCR);
+ ahbp = (bpcr & BPCR_AHBP) >> 16;
+ avbp = bpcr & BPCR_AVBP;
+
+ /* Configures the horizontal start and stop position */
+ val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp);
+ reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs,
+ LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
+
+ /* Configures the vertical start and stop position */
+ val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp);
+ reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs,
+ LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
+
+ /* Specifies the pixel format */
+ pf = to_ltdc_pixelformat(fb->format->format);
+ for (val = 0; val < NB_PF; val++)
+ if (ldev->caps.pix_fmt_hw[val] == pf)
+ break;
+
+ if (val == NB_PF) {
+ DRM_ERROR("Pixel format %.4s not supported\n",
+ (char *)&fb->format->format);
+ val = 0; /* set by default ARGB 32 bits */
+ }
+ reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
+
+ /* Configures the color frame buffer pitch in bytes & line length */
+ pitch_in_bytes = fb->pitches[0];
+ line_length = drm_format_plane_cpp(fb->format->format, 0) *
+ (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
+ val = ((pitch_in_bytes << 16) | line_length);
+ reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs,
+ LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
+
+ /* Specifies the constant alpha value */
+ val = CONSTA_MAX;
+ reg_update_bits(ldev->regs, LTDC_L1CACR + lofs,
+ LXCACR_CONSTA, val);
+
+ /* Specifies the blending factors */
+ val = BF1_PAXCA | BF2_1PAXCA;
+ reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs,
+ LXBFCR_BF2 | LXBFCR_BF1, val);
+
+ /* Configures the frame buffer line number */
+ val = y1 - y0 + 1;
+ reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs,
+ LXCFBLNR_CFBLN, val);
+
+ /* Sets the FB address */
+ paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0);
+
+ DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr);
+ reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr);
+
+ /* Enable layer and CLUT if needed */
+ val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0;
+ val |= LXCR_LEN;
+ reg_update_bits(ldev->regs, LTDC_L1CR + lofs,
+ LXCR_LEN | LXCR_CLUTEN, val);
+
+ mutex_lock(&ldev->err_lock);
+ if (ldev->error_status & ISR_FUIF) {
+ DRM_DEBUG_DRIVER("Fifo underrun\n");
+ ldev->error_status &= ~ISR_FUIF;
+ }
+ if (ldev->error_status & ISR_TERRIF) {
+ DRM_DEBUG_DRIVER("Transfer error\n");
+ ldev->error_status &= ~ISR_TERRIF;
+ }
+ mutex_unlock(&ldev->err_lock);
+}
+
+static void ltdc_plane_atomic_disable(struct drm_plane *plane,
+ struct drm_plane_state *oldstate)
+{
+ struct ltdc_device *ldev = plane_to_ltdc(plane);
+ u32 lofs = plane->index * LAY_OFS;
+
+ /* disable layer */
+ reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN);
+
+ DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
+ oldstate->crtc->base.id, plane->base.id);
+}
+
+static struct drm_plane_funcs ltdc_plane_funcs = {
+ .update_plane = drm_atomic_helper_update_plane,
+ .disable_plane = drm_atomic_helper_disable_plane,
+ .destroy = drm_plane_cleanup,
+ .set_property = drm_atomic_helper_plane_set_property,
+ .reset = drm_atomic_helper_plane_reset,
+ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
+};
+
+static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
+ .atomic_check = ltdc_plane_atomic_check,
+ .atomic_update = ltdc_plane_atomic_update,
+ .atomic_disable = ltdc_plane_atomic_disable,
+};
+
+static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
+ enum drm_plane_type type)
+{
+ unsigned long possible_crtcs = CRTC_MASK;
+ struct ltdc_device *ldev = ddev->dev_private;
+ struct device *dev = ddev->dev;
+ struct drm_plane *plane;
+ unsigned int i, nb_fmt = 0;
+ u32 formats[NB_PF];
+ u32 drm_fmt;
+ int ret;
+
+ /* Get supported pixel formats */
+ for (i = 0; i < NB_PF; i++) {
+ drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]);
+ if (!drm_fmt)
+ continue;
+ formats[nb_fmt++] = drm_fmt;
+ }
+
+ plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
+ if (!plane)
+ return 0;
+
+ ret = drm_universal_plane_init(ddev, plane, possible_crtcs,
+ <dc_plane_funcs, formats, nb_fmt,
+ type, NULL);
+ if (ret < 0)
+ return 0;
+
+ drm_plane_helper_add(plane, <dc_plane_helper_funcs);
+
+ DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
+
+ return plane;
+}
+
+static void ltdc_plane_destroy_all(struct drm_device *ddev)
+{
+ struct drm_plane *plane, *plane_temp;
+
+ list_for_each_entry_safe(plane, plane_temp,
+ &ddev->mode_config.plane_list, head)
+ drm_plane_cleanup(plane);
+}
+
+static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
+{
+ struct ltdc_device *ldev = ddev->dev_private;
+ struct drm_plane *primary, *overlay;
+ unsigned int i;
+ int res;
+
+ primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY);
+ if (!primary) {
+ DRM_ERROR("Can not create primary plane\n");
+ return -EINVAL;
+ }
+
+ res = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
+ <dc_crtc_funcs, NULL);
+ if (res) {
+ DRM_ERROR("Can not initialize CRTC\n");
+ goto cleanup;
+ }
+
+ drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs);
+
+ DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
+
+ /* Add planes. Note : the first layer is used by primary plane */
+ for (i = 1; i < ldev->caps.nb_layers; i++) {
+ overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY);
+ if (!overlay) {
+ res = -ENOMEM;
+ DRM_ERROR("Can not create overlay plane %d\n", i);
+ goto cleanup;
+ }
+ }
+
+ return 0;
+
+cleanup:
+ ltdc_plane_destroy_all(ddev);
+ return res;
+}
+
+/*
+ * DRM_ENCODER
+ */
+
+static void ltdc_rgb_encoder_enable(struct drm_encoder *encoder)
+{
+ struct ltdc_device *ldev = encoder_to_ltdc(encoder);
+
+ DRM_DEBUG_DRIVER("\n");
+
+ drm_panel_prepare(ldev->panel);
+ drm_panel_enable(ldev->panel);
+}
+
+static void ltdc_rgb_encoder_disable(struct drm_encoder *encoder)
+{
+ struct ltdc_device *ldev = encoder_to_ltdc(encoder);
+
+ DRM_DEBUG_DRIVER("\n");
+
+ drm_panel_disable(ldev->panel);
+ drm_panel_unprepare(ldev->panel);
+}
+
+static const struct drm_encoder_helper_funcs ltdc_rgb_encoder_helper_funcs = {
+ .enable = ltdc_rgb_encoder_enable,
+ .disable = ltdc_rgb_encoder_disable,
+};
+
+static const struct drm_encoder_funcs ltdc_rgb_encoder_funcs = {
+ .destroy = drm_encoder_cleanup,
+};
+
+static struct drm_encoder *ltdc_rgb_encoder_create(struct drm_device *ddev)
+{
+ struct drm_encoder *encoder;
+
+ encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
+ if (!encoder)
+ return NULL;
+
+ encoder->possible_crtcs = CRTC_MASK;
+ encoder->possible_clones = 0; /* No cloning support */
+
+ drm_encoder_init(ddev, encoder, <dc_rgb_encoder_funcs,
+ DRM_MODE_ENCODER_DPI, NULL);
+
+ drm_encoder_helper_add(encoder, <dc_rgb_encoder_helper_funcs);
+
+ DRM_DEBUG_DRIVER("RGB encoder:%d created\n", encoder->base.id);
+
+ return encoder;
+}
+
+/*
+ * DRM_CONNECTOR
+ */
+
+static int ltdc_rgb_connector_get_modes(struct drm_connector *connector)
+{
+ struct drm_device *ddev = connector->dev;
+ struct ltdc_device *ldev = ddev->dev_private;
+ int ret = 0;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ if (ldev->panel)
+ ret = drm_panel_get_modes(ldev->panel);
+
+ return ret < 0 ? 0 : ret;
+}
+
+static struct drm_connector_helper_funcs ltdc_rgb_connector_helper_funcs = {
+ .get_modes = ltdc_rgb_connector_get_modes,
+};
+
+static enum drm_connector_status
+ltdc_rgb_connector_detect(struct drm_connector *connector, bool force)
+{
+ struct ltdc_device *ldev = connector_to_ltdc(connector);
+
+ return ldev->panel ? connector_status_connected :
+ connector_status_disconnected;
+}
+
+static void ltdc_rgb_connector_destroy(struct drm_connector *connector)
+{
+ DRM_DEBUG_DRIVER("\n");
+
+ drm_connector_unregister(connector);
+ drm_connector_cleanup(connector);
+}
+
+static const struct drm_connector_funcs ltdc_rgb_connector_funcs = {
+ .dpms = drm_atomic_helper_connector_dpms,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .detect = ltdc_rgb_connector_detect,
+ .destroy = ltdc_rgb_connector_destroy,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+struct drm_connector *ltdc_rgb_connector_create(struct drm_device *ddev)
+{
+ struct drm_connector *connector;
+ int err;
+
+ connector = devm_kzalloc(ddev->dev, sizeof(*connector), GFP_KERNEL);
+ if (!connector) {
+ DRM_ERROR("Failed to allocate connector\n");
+ return NULL;
+ }
+
+ connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+ err = drm_connector_init(ddev, connector, <dc_rgb_connector_funcs,
+ DRM_MODE_CONNECTOR_DPI);
+ if (err) {
+ DRM_ERROR("Failed to initialize connector\n");
+ return NULL;
+ }
+
+ drm_connector_helper_add(connector, <dc_rgb_connector_helper_funcs);
+
+ DRM_DEBUG_DRIVER("RGB connector:%d created\n", connector->base.id);
+
+ return connector;
+}
+
+static int ltdc_get_caps(struct drm_device *ddev)
+{
+ struct ltdc_device *ldev = ddev->dev_private;
+ u32 bus_width_log2, lcr, gc2r;
+
+ /* at least 1 layer must be managed */
+ lcr = reg_read(ldev->regs, LTDC_LCR);
+
+ ldev->caps.nb_layers = max_t(int, lcr, 1);
+
+ /* set data bus width */
+ gc2r = reg_read(ldev->regs, LTDC_GC2R);
+ bus_width_log2 = (gc2r & GC2R_BW) >> 4;
+ ldev->caps.bus_width = 8 << bus_width_log2;
+ ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR);
+
+ switch (ldev->caps.hw_version) {
+ case HWVER_10200:
+ case HWVER_10300:
+ ldev->caps.reg_ofs = REG_OFS_NONE;
+ ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
+ break;
+ case HWVER_20101:
+ ldev->caps.reg_ofs = REG_OFS_4;
+ ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
+ break;
+ default:
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static struct drm_panel *ltdc_get_panel(struct drm_device *ddev)
+{
+ struct device *dev = ddev->dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *entity, *port = NULL;
+ struct drm_panel *panel = NULL;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ /*
+ * Parse ltdc node to get remote port and find RGB panel / HDMI slave
+ * If a dsi or a bridge (hdmi, lvds...) is connected to ltdc,
+ * a remote port & RGB panel will not be found.
+ */
+ for_each_endpoint_of_node(np, entity) {
+ if (!of_device_is_available(entity))
+ continue;
+
+ port = of_graph_get_remote_port_parent(entity);
+ if (port) {
+ panel = of_drm_find_panel(port);
+ of_node_put(port);
+ if (panel) {
+ DRM_DEBUG_DRIVER("remote panel %s\n",
+ port->full_name);
+ } else {
+ DRM_DEBUG_DRIVER("panel missing\n");
+ of_node_put(entity);
+ }
+ }
+ }
+
+ return panel;
+}
+
+int ltdc_load(struct drm_device *ddev)
+{
+ struct platform_device *pdev = to_platform_device(ddev->dev);
+ struct ltdc_device *ldev = ddev->dev_private;
+ struct device *dev = ddev->dev;
+ struct device_node *np = dev->of_node;
+ struct drm_encoder *encoder;
+ struct drm_connector *connector = NULL;
+ struct drm_crtc *crtc;
+ struct reset_control *rstc;
+ struct resource res;
+ int irq, ret, i;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ ldev->panel = ltdc_get_panel(ddev);
+ if (!ldev->panel)
+ return -EPROBE_DEFER;
+
+ rstc = of_reset_control_get(np, NULL);
+
+ mutex_init(&ldev->err_lock);
+
+ ldev->pixel_clk = devm_clk_get(dev, "lcd");
+ if (IS_ERR(ldev->pixel_clk)) {
+ DRM_ERROR("Unable to get lcd clock\n");
+ return -ENODEV;
+ }
+
+ if (clk_prepare_enable(ldev->pixel_clk)) {
+ DRM_ERROR("Unable to prepare pixel clock\n");
+ return -ENODEV;
+ }
+
+ if (of_address_to_resource(np, 0, &res)) {
+ DRM_ERROR("Unable to get resource\n");
+ return -ENODEV;
+ }
+
+ ldev->regs = devm_ioremap_resource(dev, &res);
+ if (IS_ERR(ldev->regs)) {
+ DRM_ERROR("Unable to get ltdc registers\n");
+ return PTR_ERR(ldev->regs);
+ }
+
+ for (i = 0; i < MAX_IRQ; i++) {
+ irq = platform_get_irq(pdev, i);
+ if (irq < 0)
+ continue;
+
+ ret = devm_request_threaded_irq(dev, irq, ltdc_irq,
+ ltdc_irq_thread, IRQF_ONESHOT,
+ dev_name(dev), ddev);
+ if (ret) {
+ DRM_ERROR("Failed to register LTDC interrupt\n");
+ return ret;
+ }
+ }
+
+ if (!IS_ERR(rstc))
+ reset_control_deassert(rstc);
+
+ /* Disable interrupts */
+ reg_clear(ldev->regs, LTDC_IER,
+ IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE);
+
+ ret = ltdc_get_caps(ddev);
+ if (ret) {
+ DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
+ ldev->caps.hw_version);
+ return ret;
+ }
+
+ DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version);
+
+ if (ldev->panel) {
+ encoder = ltdc_rgb_encoder_create(ddev);
+ if (!encoder) {
+ DRM_ERROR("Failed to create RGB encoder\n");
+ ret = -EINVAL;
+ goto err;
+ }
+
+ connector = ltdc_rgb_connector_create(ddev);
+ if (!connector) {
+ DRM_ERROR("Failed to create RGB connector\n");
+ ret = -EINVAL;
+ goto err;
+ }
+
+ ret = drm_mode_connector_attach_encoder(connector, encoder);
+ if (ret) {
+ DRM_ERROR("Failed to attach connector to encoder\n");
+ goto err;
+ }
+
+ drm_panel_attach(ldev->panel, connector);
+ }
+
+ crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
+ if (!crtc) {
+ DRM_ERROR("Failed to allocate crtc\n");
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ ret = ltdc_crtc_init(ddev, crtc);
+ if (ret) {
+ DRM_ERROR("Failed to init crtc\n");
+ goto err;
+ }
+
+ ret = drm_vblank_init(ddev, NB_CRTC);
+ if (ret) {
+ DRM_ERROR("Failed calling drm_vblank_init()\n");
+ goto err;
+ }
+
+ /* Allow usage of vblank without having to call drm_irq_install */
+ ddev->irq_enabled = 1;
+
+ return 0;
+err:
+ if (ldev->panel)
+ drm_panel_detach(ldev->panel);
+
+ clk_disable_unprepare(ldev->pixel_clk);
+
+ return ret;
+}
+
+void ltdc_unload(struct drm_device *ddev)
+{
+ struct ltdc_device *ldev = ddev->dev_private;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ drm_vblank_cleanup(ddev);
+
+ if (ldev->panel)
+ drm_panel_detach(ldev->panel);
+
+ clk_disable_unprepare(ldev->pixel_clk);
+}
+
+MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
+MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
+MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
+MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
+MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
new file mode 100644
index 0000000..d7a9c73
--- /dev/null
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * Authors: Philippe Cornu <philippe.cornu@st.com>
+ * Yannick Fertre <yannick.fertre@st.com>
+ * Fabien Dessenne <fabien.dessenne@st.com>
+ * Mickael Reulier <mickael.reulier@st.com>
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#ifndef _LTDC_H_
+#define _LTDC_H_
+
+struct ltdc_caps {
+ u32 hw_version; /* hardware version */
+ u32 nb_layers; /* number of supported layers */
+ u32 reg_ofs; /* register offset for applicable regs */
+ u32 bus_width; /* bus width (32 or 64 bits) */
+ const u32 *pix_fmt_hw; /* supported pixel formats */
+};
+
+struct ltdc_device {
+ struct drm_fbdev_cma *fbdev;
+ void __iomem *regs;
+ struct clk *pixel_clk; /* lcd pixel clock */
+ struct drm_panel *panel;
+ struct mutex err_lock; /* protecting error_status */
+ struct ltdc_caps caps;
+ u32 clut[256]; /* color look up table */
+ u32 error_status;
+ u32 irq_status;
+};
+
+int ltdc_crtc_enable_vblank(struct drm_device *dev, unsigned int pipe);
+void ltdc_crtc_disable_vblank(struct drm_device *dev, unsigned int pipe);
+int ltdc_load(struct drm_device *ddev);
+void ltdc_unload(struct drm_device *ddev);
+
+#endif
--
1.9.1
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^ permalink raw reply related
* [PATCH v7 3/9] dt-bindings: display: Add STM32 LTDC driver
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
Benjamin Gaignard, Yannick Fertre
Cc: devicetree, kernel, Philippe Cornu, Fabien Dessenne, dri-devel,
Mickael Reulier, Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
This patch adds documentation of device tree bindings for the STM32 LTDC
(Lcd-Tft Display Controller).
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
.../devicetree/bindings/display/st,stm32-ltdc.txt | 36 ++++++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
new file mode 100644
index 0000000..8e14769
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
@@ -0,0 +1,36 @@
+* STMicroelectronics STM32 lcd-tft display controller
+
+- ltdc: lcd-tft display controller host
+ must be a sub-node of st-display-subsystem
+ Required properties:
+ - compatible: "st,stm32-ltdc"
+ - reg: Physical base address of the IP registers and length of memory mapped region.
+ - clocks: A list of phandle + clock-specifier pairs, one for each
+ entry in 'clock-names'.
+ - clock-names: A list of clock names. For ltdc it should contain:
+ - "lcd" for the clock feeding the output pixel clock & IP clock.
+ - resets: reset to be used by the device (defined by use of RCC macro).
+ Required nodes:
+ - Video port for RGB output.
+
+Example:
+
+/ {
+ ...
+ soc {
+ ...
+ ltdc: display-controller@40016800 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x40016800 0x200>;
+ interrupts = <88>, <89>;
+ resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
+ clocks = <&rcc 1 CLK_LCD>;
+ clock-names = "lcd";
+
+ port {
+ ltdc_out_rgb: endpoint {
+ };
+ };
+ };
+ };
+};
--
1.9.1
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* [PATCH v7 2/9] drm/fb-cma-helper: Add drm_fb_cma_get_gem_addr()
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
Benjamin Gaignard, Yannick Fertre
Cc: devicetree, kernel, Philippe Cornu, Fabien Dessenne, dri-devel,
Mickael Reulier, Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
Add function drm_fb_cma_get_gem_addr() which return the physical address
of framebuffer (1st pixel). This function will usually be called by plane
callback (atomic_update).
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
drivers/gpu/drm/drm_fb_cma_helper.c | 27 +++++++++++++++++++++++++++
include/drm/drm_fb_cma_helper.h | 4 ++++
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c b/drivers/gpu/drm/drm_fb_cma_helper.c
index 50abd1f..d2b77b0 100644
--- a/drivers/gpu/drm/drm_fb_cma_helper.c
+++ b/drivers/gpu/drm/drm_fb_cma_helper.c
@@ -260,6 +260,33 @@ struct drm_gem_cma_object *drm_fb_cma_get_gem_obj(struct drm_framebuffer *fb,
EXPORT_SYMBOL_GPL(drm_fb_cma_get_gem_obj);
/**
+ * drm_fb_cma_get_gem_addr() - Get physical address for framebuffer
+ * @fb: The framebuffer
+ * @state: Which state of drm plane
+ * @plane: Which plane
+ * Return the CMA GEM address for given framebuffer.
+ *
+ * This function will usually be called from the PLANE callback functions.
+ */
+dma_addr_t drm_fb_cma_get_gem_addr(struct drm_framebuffer *fb,
+ struct drm_plane_state *state,
+ unsigned int plane)
+{
+ struct drm_fb_cma *fb_cma = to_fb_cma(fb);
+ dma_addr_t paddr;
+
+ if (plane >= 4)
+ return 0;
+
+ paddr = fb_cma->obj[plane]->paddr + fb->offsets[plane];
+ paddr += fb->format->cpp[plane] * (state->src_x >> 16);
+ paddr += fb->pitches[plane] * (state->src_y >> 16);
+
+ return paddr;
+}
+EXPORT_SYMBOL_GPL(drm_fb_cma_get_gem_addr);
+
+/**
* drm_fb_cma_prepare_fb() - Prepare CMA framebuffer
* @plane: Which plane
* @state: Plane state attach fence to
diff --git a/include/drm/drm_fb_cma_helper.h b/include/drm/drm_fb_cma_helper.h
index a5ecc0a..199a63f 100644
--- a/include/drm/drm_fb_cma_helper.h
+++ b/include/drm/drm_fb_cma_helper.h
@@ -41,6 +41,10 @@ struct drm_framebuffer *drm_fb_cma_create(struct drm_device *dev,
struct drm_gem_cma_object *drm_fb_cma_get_gem_obj(struct drm_framebuffer *fb,
unsigned int plane);
+dma_addr_t drm_fb_cma_get_gem_addr(struct drm_framebuffer *fb,
+ struct drm_plane_state *state,
+ unsigned int plane);
+
int drm_fb_cma_prepare_fb(struct drm_plane *plane,
struct drm_plane_state *state);
--
1.9.1
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* [PATCH v7 1/9] drm/cma: Update DEFINE_DRM_GEM_CMA_FOPS to add get_unmapped_area
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
Benjamin Gaignard, Yannick Fertre
Cc: devicetree, kernel, Philippe Cornu, Fabien Dessenne, dri-devel,
Mickael Reulier, Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
Missing field get_unmapped_area which is necessary with device without MMU
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
include/drm/drm_gem_cma_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_gem_cma_helper.h b/include/drm/drm_gem_cma_helper.h
index f962d33..7320b14 100644
--- a/include/drm/drm_gem_cma_helper.h
+++ b/include/drm/drm_gem_cma_helper.h
@@ -50,6 +50,7 @@ struct drm_gem_cma_object {
.read = drm_read,\
.llseek = noop_llseek,\
.mmap = drm_gem_cma_mmap,\
+ .get_unmapped_area = drm_gem_cma_get_unmapped_area,\
}
/* free GEM object */
--
1.9.1
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* [PATCH v7 0/9] STM32 LCD-TFT display controller
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: Alexandre TORGUE, Thierry Reding, David Airlie, Maxime Coquelin,
Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
Benjamin Gaignard, Yannick Fertre
Cc: devicetree, kernel, Philippe Cornu, Fabien Dessenne, dri-devel,
Mickael Reulier, Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel
Version 7:
- rework heading of MAINTAINERS patch
Version 6:
- Add patch on MAINTAINERS file to add Philippe Cornu & myself.
- Update driver stm to remove uneccessary functions called.
Version 5:
- Add patch on drm_gem_cma_helper.h to udapte DEFINE_DRM_GEM_CMA_FOPS.
- Add patch on drm_fb_cma_helper to add new function to get physical address.
- Solve some typos & update ltdc driver including last remarks of Eric Anholt
- Update commits of config patches.
Version 4:
- Update "ampire,am-480272h3tmqw-t01h.txt" binding with more details on gpios.
- Update ltdc.c. Remove regmap, solve some typo & warnings.
Version 3:
- Update "st,stm32-ltdc.txt" binding.
- Add a commit to "ARM: configs: stm32: ADD LDTC support" patch.
Version 2:
- Rename driver directory from st to stm.
- Rename compatiblity from st,ltdc to st,stm32-ltdc.
- Remove compatibility st,display-subsystem.
- Rename driver from st-drm to stm-drm.
- Rework probe sequence & remove display-subsystem part.
- I keep clock name which is necessary for devm_regmap_init_mmio_clk call.
Version 1:
- Initial commit
The purpose of this set of patches is to add a new driver for stm32f429.
This driver was developed and tested on evaluation board stm32429i.
Stm32f4 is a MCU platform which don't have MMU so the last patches developed
by Benjamin Gaignard regarding "DRM: allow to use mmuless devices"
are necessary.
The board stm429i embeds a Ampire AM-480272H3TMQW-T01H screen.
A new simple panel am-480272h3tmqw-t01h have been added to support it.
Yannick Fertre (9):
drm/cma: Update DEFINE_DRM_GEM_CMA_FOPS to add get_unmapped_area
drm/fb-cma-helper: Add drm_fb_cma_get_gem_addr()
dt-bindings: display: Add STM32 LTDC driver
drm/stm: Add STM32 LTDC driver
MAINTAINERS: add maintainers for DRM STM driver
ARM: dts: stm32: Add ltdc support on stm32f429 MCU
ARM: dts: stm32: Enable ltdc & simple panel on stm32f429-Eval board
ARM: configs: stm32: Add DRM support in STM32 defconfig
ARM: configs: stm32: Add simple panel support in STM32 defconfig
.../devicetree/bindings/display/st,stm32-ltdc.txt | 36 +
MAINTAINERS | 9 +
arch/arm/boot/dts/stm32429i-eval.dts | 59 +
arch/arm/boot/dts/stm32f429.dtsi | 12 +-
arch/arm/configs/stm32_defconfig | 3 +
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/drm_fb_cma_helper.c | 27 +
drivers/gpu/drm/stm/Kconfig | 16 +
drivers/gpu/drm/stm/Makefile | 7 +
drivers/gpu/drm/stm/drv.c | 221 ++++
drivers/gpu/drm/stm/ltdc.c | 1161 ++++++++++++++++++++
drivers/gpu/drm/stm/ltdc.h | 40 +
include/drm/drm_fb_cma_helper.h | 4 +
include/drm/drm_gem_cma_helper.h | 1 +
15 files changed, 1598 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
create mode 100644 drivers/gpu/drm/stm/Kconfig
create mode 100644 drivers/gpu/drm/stm/Makefile
create mode 100644 drivers/gpu/drm/stm/drv.c
create mode 100644 drivers/gpu/drm/stm/ltdc.c
create mode 100644 drivers/gpu/drm/stm/ltdc.h
--
1.9.1
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