* [PATCH v6 3/4] ARM: mvebu: Enable SENSORS_PWM_FAN in defconfig
From: Ralph Sennhauser @ 2017-04-14 15:40 UTC (permalink / raw)
To: linux-gpio
Cc: Andrew Lunn, Ralph Sennhauser, Thierry Reding, Linus Walleij,
Alexandre Courbot, Rob Herring, Mark Rutland, Jason Cooper,
Gregory Clement, Sebastian Hesselbarth, Russell King, linux-pwm,
devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20170414154056.32055-1-ralph.sennhauser@gmail.com>
From: Andrew Lunn <andrew@lunn.ch>
Now that the GPIO driver also supports PWM operation, enable the PWM
framework and fan driver in mvebu_v7_defconfig.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
URL: https://patchwork.ozlabs.org/patch/427297/
[Ralph Sennhauser: add fan driver to defconfig]
Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
---
arch/arm/configs/mvebu_v7_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
index f1a0e25..6955370 100644
--- a/arch/arm/configs/mvebu_v7_defconfig
+++ b/arch/arm/configs/mvebu_v7_defconfig
@@ -135,6 +135,8 @@ CONFIG_DMADEVICES=y
CONFIG_MV_XOR=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_MEMORY=y
+CONFIG_PWM=y
+CONFIG_SENSORS_PWM_FAN=y
CONFIG_EXT4_FS=y
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
--
2.10.2
^ permalink raw reply related
* [PATCH v6 2/4] ARM: dts: mvebu: Add PWM properties to .dtsi files
From: Ralph Sennhauser @ 2017-04-14 15:40 UTC (permalink / raw)
To: linux-gpio
Cc: Andrew Lunn, Ralph Sennhauser, Thierry Reding, Linus Walleij,
Alexandre Courbot, Rob Herring, Mark Rutland, Jason Cooper,
Gregory Clement, Sebastian Hesselbarth, Russell King, linux-pwm,
devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20170414154056.32055-1-ralph.sennhauser@gmail.com>
From: Andrew Lunn <andrew@lunn.ch>
Add properties to the GPIO nodes to allow them to be also used as PWM
lines.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
URL: https://patchwork.ozlabs.org/patch/427294/
[Ralph Sennhauser: Add new compatible string marvell,armada-370-xp-gpio]
Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
---
arch/arm/boot/dts/armada-370.dtsi | 19 ++++++++++++++-----
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 16 ++++++++++++----
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 19 ++++++++++++++-----
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 19 ++++++++++++++-----
4 files changed, 54 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index cc011c8..5e815cc 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -137,29 +137,38 @@
};
gpio0: gpio@18100 {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
+ compatible = "marvell,armada-370-xp-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18100 0x40>, <0x181c0 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
+ clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
+ compatible = "marvell,armada-370-xp-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18140 0x40>, <0x181c8 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
+ clocks = <&coreclk 0>;
};
gpio2: gpio@18180 {
- compatible = "marvell,orion-gpio";
+ compatible = "marvell,armada-370-xp-gpio",
+ "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <2>;
gpio-controller;
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 07c5090..f77168c9 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -202,25 +202,33 @@
internal-regs {
gpio0: gpio@18100 {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
+ compatible = "marvell,armada-370-xp-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18100 0x40>, <0x181c0 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
+ clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
+ compatible = "marvell,armada-370-xp-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18140 0x40>, <0x181c8 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <17>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>;
+ clocks = <&coreclk 0>;
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 64e936a..0ecfaf4 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -285,29 +285,38 @@
internal-regs {
gpio0: gpio@18100 {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
+ compatible = "marvell,armada-370-xp-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18100 0x40>, <0x181c0 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
+ clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
+ compatible = "marvell,armada-370-xp-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18140 0x40>, <0x181c8 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
+ clocks = <&coreclk 0>;
};
gpio2: gpio@18180 {
- compatible = "marvell,orion-gpio";
+ compatible = "marvell,armada-370-xp-gpio",
+ "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <3>;
gpio-controller;
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index d1383dd..670ece4c 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -323,29 +323,38 @@
internal-regs {
gpio0: gpio@18100 {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
+ compatible = "marvell,armada-370-xp-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18100 0x40>, <0x181c0 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
+ clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
+ compatible = "marvell,armada-370-xp-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18140 0x40>, <0x181c8 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
+ clocks = <&coreclk 0>;
};
gpio2: gpio@18180 {
- compatible = "marvell,orion-gpio";
+ compatible = "marvell,armada-370-xp-gpio",
+ "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <3>;
gpio-controller;
--
2.10.2
^ permalink raw reply related
* [PATCH v6 1/4] gpio: mvebu: Add limited PWM support
From: Ralph Sennhauser @ 2017-04-14 15:40 UTC (permalink / raw)
To: linux-gpio
Cc: Andrew Lunn, Ralph Sennhauser, Thierry Reding, Linus Walleij,
Alexandre Courbot, Rob Herring, Mark Rutland, Jason Cooper,
Gregory Clement, Sebastian Hesselbarth, Russell King, linux-pwm,
devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20170414154056.32055-1-ralph.sennhauser@gmail.com>
From: Andrew Lunn <andrew@lunn.ch>
Armada 370/XP devices can 'blink' GPIO lines with a configurable on
and off period. This can be modelled as a PWM.
However, there are only two sets of PWM configuration registers for
all the GPIO lines. This driver simply allows a single GPIO line per
GPIO chip of 32 lines to be used as a PWM. Attempts to use more return
EBUSY.
Due to the interleaving of registers it is not simple to separate the
PWM driver from the GPIO driver. Thus the GPIO driver has been
extended with a PWM driver.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
URL: https://patchwork.ozlabs.org/patch/427287/
URL: https://patchwork.ozlabs.org/patch/427295/
[Ralph Sennhauser:
* Port forward
* Merge PWM portion into gpio-mvebu.c
* Switch to atomic PWM API
* Add new compatible string marvell,armada-370-xp-gpio
* Update and merge documentation patch
* Update MAINTAINERS]
Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/gpio/gpio-mvebu.txt | 32 ++
MAINTAINERS | 2 +
drivers/gpio/gpio-mvebu.c | 327 ++++++++++++++++++++-
3 files changed, 349 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
index a6f3bec..42c3bb2 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
@@ -38,6 +38,24 @@ Required properties:
- #gpio-cells: Should be two. The first cell is the pin number. The
second cell is reserved for flags, unused at the moment.
+Optional properties:
+
+In order to use the GPIO lines in PWM mode, some additional optional
+properties are required. Only Armada 370 and XP support these properties.
+
+- compatible: Must contain "marvell,armada-370-xp-gpio"
+
+- reg: an additional register set is needed, for the GPIO Blink
+ Counter on/off registers.
+
+- reg-names: Must contain an entry "pwm" corresponding to the
+ additional register range needed for PWM operation.
+
+- #pwm-cells: Should be two. The first cell is the GPIO line number. The
+ second cell is the period in nanoseconds.
+
+- clocks: Must be a phandle to the clock for the GPIO controller.
+
Example:
gpio0: gpio@d0018100 {
@@ -51,3 +69,17 @@ Example:
#interrupt-cells = <2>;
interrupts = <16>, <17>, <18>, <19>;
};
+
+ gpio1: gpio@18140 {
+ compatible = "marvell,armada-370-xp-gpio";
+ reg = <0x18140 0x40>, <0x181c8 0x08>;
+ reg-names = "gpio", "pwm";
+ ngpios = <17>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #pwm-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <87>, <88>, <89>;
+ clocks = <&coreclk 0>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 58b3a22..19382f5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10295,6 +10295,8 @@ F: include/linux/pwm.h
F: drivers/pwm/
F: drivers/video/backlight/pwm_bl.c
F: include/linux/pwm_backlight.h
+F: drivers/gpio/gpio-mvebu.c
+F: Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
PXA2xx/PXA3xx SUPPORT
M: Daniel Mack <daniel@zonque.org>
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index fae4db6..19a92ef 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -42,22 +42,34 @@
#include <linux/io.h>
#include <linux/of_irq.h>
#include <linux/of_device.h>
+#include <linux/pwm.h>
#include <linux/clk.h>
#include <linux/pinctrl/consumer.h>
#include <linux/irqchip/chained_irq.h>
+#include <linux/platform_device.h>
#include <linux/bitops.h>
+#include "gpiolib.h"
+
/*
* GPIO unit register offsets.
*/
-#define GPIO_OUT_OFF 0x0000
-#define GPIO_IO_CONF_OFF 0x0004
-#define GPIO_BLINK_EN_OFF 0x0008
-#define GPIO_IN_POL_OFF 0x000c
-#define GPIO_DATA_IN_OFF 0x0010
-#define GPIO_EDGE_CAUSE_OFF 0x0014
-#define GPIO_EDGE_MASK_OFF 0x0018
-#define GPIO_LEVEL_MASK_OFF 0x001c
+#define GPIO_OUT_OFF 0x0000
+#define GPIO_IO_CONF_OFF 0x0004
+#define GPIO_BLINK_EN_OFF 0x0008
+#define GPIO_IN_POL_OFF 0x000c
+#define GPIO_DATA_IN_OFF 0x0010
+#define GPIO_EDGE_CAUSE_OFF 0x0014
+#define GPIO_EDGE_MASK_OFF 0x0018
+#define GPIO_LEVEL_MASK_OFF 0x001c
+#define GPIO_BLINK_CNT_SELECT_OFF 0x0020
+
+/*
+ * PWM register offsets.
+ */
+#define PWM_BLINK_ON_DURATION_OFF 0x0
+#define PWM_BLINK_OFF_DURATION_OFF 0x4
+
/* The MV78200 has per-CPU registers for edge mask and level mask */
#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
@@ -78,6 +90,20 @@
#define MVEBU_MAX_GPIO_PER_BANK 32
+struct mvebu_pwm {
+ void __iomem *membase;
+ unsigned long clk_rate;
+ struct gpio_desc *gpiod;
+ struct pwm_chip chip;
+ spinlock_t lock;
+ struct mvebu_gpio_chip *mvchip;
+
+ /* Used to preserve GPIO/PWM registers across suspend/resume */
+ u32 blink_select;
+ u32 blink_on_duration;
+ u32 blink_off_duration;
+};
+
struct mvebu_gpio_chip {
struct gpio_chip chip;
spinlock_t lock;
@@ -87,6 +113,10 @@ struct mvebu_gpio_chip {
struct irq_domain *domain;
int soc_variant;
+ /* Used for PWM support */
+ struct clk *clk;
+ struct mvebu_pwm *mvpwm;
+
/* Used to preserve GPIO registers across suspend/resume */
u32 out_reg;
u32 io_conf_reg;
@@ -110,6 +140,12 @@ static void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip)
return mvchip->membase + GPIO_BLINK_EN_OFF;
}
+static void __iomem *mvebu_gpioreg_blink_counter_select(struct mvebu_gpio_chip
+ *mvchip)
+{
+ return mvchip->membase + GPIO_BLINK_CNT_SELECT_OFF;
+}
+
static void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
{
return mvchip->membase + GPIO_IO_CONF_OFF;
@@ -181,6 +217,20 @@ static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip)
}
/*
+ * Functions returning addresses of individual registers for a given
+ * PWM controller.
+ */
+static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
+{
+ return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF;
+}
+
+static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
+{
+ return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF;
+}
+
+/*
* Functions implementing the gpio_chip methods
*/
static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
@@ -484,6 +534,246 @@ static void mvebu_gpio_irq_handler(struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
+/*
+ * Functions implementing the pwm_chip methods
+ */
+static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
+{
+ return container_of(chip, struct mvebu_pwm, chip);
+}
+
+static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
+ struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
+ struct gpio_desc *desc;
+ unsigned long flags;
+ int ret = 0;
+
+ spin_lock_irqsave(&mvpwm->lock, flags);
+
+ if (mvpwm->gpiod) {
+ ret = -EBUSY;
+ } else {
+ desc = gpio_to_desc(mvchip->chip.base + pwm->hwpwm);
+ if (!desc) {
+ ret = -ENODEV;
+ goto out;
+ }
+
+ ret = gpiod_request(desc, "mvebu-pwm");
+ if (ret)
+ goto out;
+
+ ret = gpiod_direction_output(desc, 0);
+ if (ret) {
+ gpiod_free(desc);
+ goto out;
+ }
+
+ mvpwm->gpiod = desc;
+ }
+out:
+ spin_unlock_irqrestore(&mvpwm->lock, flags);
+ return ret;
+}
+
+static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
+ unsigned long flags;
+
+ spin_lock_irqsave(&mvpwm->lock, flags);
+ gpiod_free(mvpwm->gpiod);
+ mvpwm->gpiod = NULL;
+ spin_unlock_irqrestore(&mvpwm->lock, flags);
+}
+
+static void mvebu_pwm_get_state(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ struct pwm_state *state) {
+
+ struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
+ struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
+ unsigned long long val;
+ unsigned long flags;
+ u32 u;
+
+ spin_lock_irqsave(&mvpwm->lock, flags);
+
+ val = (unsigned long long)
+ readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
+ val *= NSEC_PER_SEC;
+ do_div(val, mvpwm->clk_rate);
+ if (val > UINT_MAX)
+ state->duty_cycle = UINT_MAX;
+ else if (val)
+ state->duty_cycle = val;
+ else
+ state->duty_cycle = 1;
+
+ val = (unsigned long long)
+ readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
+ val *= NSEC_PER_SEC;
+ do_div(val, mvpwm->clk_rate);
+ if (val < state->duty_cycle) {
+ state->period = 1;
+ } else {
+ val -= state->duty_cycle;
+ if (val > UINT_MAX)
+ state->period = UINT_MAX;
+ else if (val)
+ state->period = val;
+ else
+ state->period = 1;
+ }
+
+ u = readl_relaxed(mvebu_gpioreg_blink(mvchip));
+ if (u)
+ state->enabled = true;
+ else
+ state->enabled = false;
+
+ spin_unlock_irqrestore(&mvpwm->lock, flags);
+}
+
+static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
+ struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
+ unsigned long long val;
+ unsigned long flags;
+ unsigned int on, off;
+
+ val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
+ do_div(val, NSEC_PER_SEC);
+ if (val > UINT_MAX)
+ return -EINVAL;
+ if (val)
+ on = val;
+ else
+ on = 1;
+
+ val = (unsigned long long) mvpwm->clk_rate *
+ (state->period - state->duty_cycle);
+ do_div(val, NSEC_PER_SEC);
+ if (val > UINT_MAX)
+ return -EINVAL;
+ if (val)
+ off = val;
+ else
+ off = 1;
+
+ spin_lock_irqsave(&mvpwm->lock, flags);
+
+ writel_relaxed(on, mvebu_pwmreg_blink_on_duration(mvpwm));
+ writel_relaxed(off, mvebu_pwmreg_blink_off_duration(mvpwm));
+ if (state->enabled)
+ mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
+ else
+ mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
+
+ spin_unlock_irqrestore(&mvpwm->lock, flags);
+
+ return 0;
+}
+
+static const struct pwm_ops mvebu_pwm_ops = {
+ .request = mvebu_pwm_request,
+ .free = mvebu_pwm_free,
+ .get_state = mvebu_pwm_get_state,
+ .apply = mvebu_pwm_apply,
+ .owner = THIS_MODULE,
+};
+
+static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
+{
+ struct mvebu_pwm *mvpwm = mvchip->mvpwm;
+
+ mvpwm->blink_select =
+ readl_relaxed(mvebu_gpioreg_blink_counter_select(mvchip));
+ mvpwm->blink_on_duration =
+ readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
+ mvpwm->blink_off_duration =
+ readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
+}
+
+static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
+{
+ struct mvebu_pwm *mvpwm = mvchip->mvpwm;
+
+ writel_relaxed(mvpwm->blink_select,
+ mvebu_gpioreg_blink_counter_select(mvchip));
+ writel_relaxed(mvpwm->blink_on_duration,
+ mvebu_pwmreg_blink_on_duration(mvpwm));
+ writel_relaxed(mvpwm->blink_off_duration,
+ mvebu_pwmreg_blink_off_duration(mvpwm));
+}
+
+static int mvebu_pwm_probe(struct platform_device *pdev,
+ struct mvebu_gpio_chip *mvchip,
+ int id)
+{
+ struct device *dev = &pdev->dev;
+ struct mvebu_pwm *mvpwm;
+ struct resource *res;
+ u32 set;
+
+ if (!of_device_is_compatible(mvchip->chip.of_node,
+ "marvell,armada-370-xp-gpio"))
+ return 0;
+
+ if (IS_ERR(mvchip->clk))
+ return PTR_ERR(mvchip->clk);
+
+ /*
+ * There are only two sets of PWM configuration registers for
+ * all the GPIO lines on those SoCs which this driver reserves
+ * for the first two GPIO chips. So if the resource is missing
+ * we can't treat it as an error.
+ */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm");
+ if (!res)
+ return 0;
+
+ /*
+ * Use set A for lines of GPIO chip with id 0, B for GPIO chip
+ * with id 1. Don't allow further GPIO chips to be used for PWM.
+ */
+ if (id == 0)
+ set = 0;
+ else if (id == 1)
+ set = U32_MAX;
+ else
+ return -EINVAL;
+ writel_relaxed(0, mvebu_gpioreg_blink_counter_select(mvchip));
+
+ mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
+ if (!mvpwm)
+ return -ENOMEM;
+ mvchip->mvpwm = mvpwm;
+ mvpwm->mvchip = mvchip;
+
+ mvpwm->membase = devm_ioremap_resource(dev, res);
+ if (IS_ERR(mvpwm->membase))
+ return PTR_ERR(mvpwm->membase);
+
+ mvpwm->clk_rate = clk_get_rate(mvchip->clk);
+ if (!mvpwm->clk_rate) {
+ dev_err(dev, "failed to get clock rate\n");
+ return -EINVAL;
+ }
+
+ mvpwm->chip.dev = dev;
+ mvpwm->chip.ops = &mvebu_pwm_ops;
+ mvpwm->chip.npwm = mvchip->chip.ngpio;
+
+ spin_lock_init(&mvpwm->lock);
+
+ return pwmchip_add(&mvpwm->chip);
+}
+
#ifdef CONFIG_DEBUG_FS
#include <linux/seq_file.h>
@@ -555,6 +845,10 @@ static const struct of_device_id mvebu_gpio_of_match[] = {
.data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
},
{
+ .compatible = "marvell,armada-370-xp-gpio",
+ .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
+ },
+ {
/* sentinel */
},
};
@@ -600,6 +894,9 @@ static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
BUG();
}
+ if (IS_ENABLED(CONFIG_PWM))
+ mvebu_pwm_suspend(mvchip);
+
return 0;
}
@@ -643,6 +940,9 @@ static int mvebu_gpio_resume(struct platform_device *pdev)
BUG();
}
+ if (IS_ENABLED(CONFIG_PWM))
+ mvebu_pwm_resume(mvchip);
+
return 0;
}
@@ -654,7 +954,6 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
struct resource *res;
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
- struct clk *clk;
unsigned int ngpios;
bool have_irqs;
int soc_variant;
@@ -688,10 +987,10 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
return id;
}
- clk = devm_clk_get(&pdev->dev, NULL);
+ mvchip->clk = devm_clk_get(&pdev->dev, NULL);
/* Not all SoCs require a clock.*/
- if (!IS_ERR(clk))
- clk_prepare_enable(clk);
+ if (!IS_ERR(mvchip->clk))
+ clk_prepare_enable(mvchip->clk);
mvchip->soc_variant = soc_variant;
mvchip->chip.label = dev_name(&pdev->dev);
@@ -822,6 +1121,10 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
mvchip);
}
+ /* Armada 370/XP has simple PWM support for GPIO lines */
+ if (IS_ENABLED(CONFIG_PWM))
+ return mvebu_pwm_probe(pdev, mvchip, id);
+
return 0;
err_domain:
--
2.10.2
^ permalink raw reply related
* [PATCH v5 0/4] gpio: mvebu: Add PWM fan support
From: Ralph Sennhauser @ 2017-04-14 15:40 UTC (permalink / raw)
To: linux-gpio
Cc: Ralph Sennhauser, Thierry Reding, Linus Walleij,
Alexandre Courbot, Rob Herring, Mark Rutland, Jason Cooper,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth, Russell King,
linux-pwm, devicetree, linux-kernel, linux-arm-kernel
Hi everyone,
With the bike shedding fixes as Thierry called them out of the way and
the ACK by Rob for the bindings this version could be merged.
The only thing still sort of open is whether to use npwm=1 and giving up
the sysfs use case. Though an ACK was given for this implementation
already I think we should give Thierry a chance to speak up once more if
he so wishes.
Thanks
Ralph
---
Notes:
About npwm = 1:
The only way I can think of to achieve that requires reading the
GPIO line from the device tree. This would prevent a user to
dynamically choose a line. Which is fine for the fan found on Mamba
but let's take some development board with freely accessible GPIOs
and suddenly we limit the use of this driver (sysfs). Given the
above, npwm = ngpio with only one usable at a time is a closer /
more appropriate description of the situation. The downside is
some "wasted" space and not meeting the expectation that all PWMs
are usable concurrently, only one per chip at any given time.
About the new compatible string:
Orion was chosen for the SoC variant for the same reason as in
commit 5f79c651e81e ("arm: mvebu: use global interrupts for GPIOs on
Armada XP").
The "pwm" property remains optional for the new compatible string so
the compatiple string "marvell,armada-370-xp-gpio" can be used by
all and not just the first two GPIO chips.
About extending the driver for use with a third GPIO chip:
It's possible to add an extra node "mvebugpiopwmctrl" to configure a
different assignment without requiring changes to the current
bindings. The current implementation doesn't prevent a fan to be
used as gpio-fan connect to the 3rd chip.
---
Changes v5->v6:
Patch 1/4 gpio: mvebu: Add limited PWM support:
* more uppercase for GPIO / PWM in prose (suggested by Thierry
Reding)
* use a variable for register set A/B selection value (suggested by
Thierry Reding)
* Don't set pwm_chip base to gpio_chip base, use hwpwm instead.
(suggested by Thierry Reding)
* use pointer to gpio_desc instead of boolen used (suggested by
Thierry Reding)
* check a bit earlier for working clock (suggested by Thierry
Reding)
* Add Acked-by: Thierry Reding <thierry.reding@gmail.com>
* Acked-by: Rob Herring <robh@kernel.org>
Changes v4->v5:
All
* add Tested-by: Andrew Lunn <andrew@lunn.ch>, thanks
Patch 2/4 mvebu: xp: Add PWM properties to .dtsi files
* keep the old compatible stings, we don't have to drop them (suggested by Gregory CLEMENT)
* subject starts with ARM: dts: mvebu: (suggested by Gregory CLEMENT)
Patch 4/4 mvebu: wrt1900ac: Use pwm-fan rather than gpio-fan
* subject starts with ARM: dts: armada-xp: (suggested by Gregory CLEMENT)
Changes v3->v4:
Patch 1/4 gpio: mvebu: Add limited PWM support:
* braces for both branches in if statement if one needs it. (suggested
by Andrew Lunn)
* introduce compatible string marvell,armada-370-xp-gpio (suggest by
Rob Herring)
* fix mvebu_pwmreg_blink_on_duration -> mvebu_pwmreg_blink_off_duration
for period callculation in mvebu_pwm_get_state()
Patch 4/4 mvebu: wrt1900ac: Use pwm-fan rather than gpio-fan
* Drop flags from pwms for Mamba, as no longer used (suggested by
Andrew Lunn)
* Use again #pwm-cell = 2, the second cell is actually the period.
Changes v2->v3:
Patch 1/4 gpio: mvebu: Add limited PWM support:
* drop pin from mvebu_pwn, can be infered (suggested by Thierry Reding)
* rename pwm to mvpwm so pwm can be used for pwm_device as in the API,
avoids some mental gymnastic.
* drop id from struct mvebu_gpio_chip, select blink counter in
mvebu_pwm_probe for all lines instead. We do not care about the
unused ones. I think a clear improvement in readability.
Makes coming up with a good comment simple as well.
* Switch to new atomic PWM API (suggested by Thierry Reding)
* rename use mvebu_gpioreg_blink_select to
mvebu_gpioreg_blink_counter_select.
* mark *_suspend() / *_resume() as __maybe_unused (suggested by Linus
Walleij)
* document #pwm-cells = 1 (suggested by Thierry Reding)
Patch 2/4 mvebu: xp: Add PWM properties to .dtsi files
* add missing reg-names / #pwm-cell properties to
armada-xp-mv78260.dtsi gpio1 node
* set pwm-cells = 1 (suggested by Thierry Reding)
All:
* always uppercase GPIO/PWM in prose (suggested by Thierry Reding)
Changes v1 -> v2:
Patch 1/4 gpio: mvebu: Add limited PWM support:
* use BIT macro (suggested by Linus Walleij)
* move id from struct mvebu_pwm to struct mvebu_gpio_chip, implement
blink select as if else and comment on the chip id for code clarity
(to accommodate Linus Walleijs request for a code clarification /
comment. If you can word it better I'm all ears.)
* Move function comment mvebu_pwm_probe into the function itself.
---
Andrew Lunn (4):
gpio: mvebu: Add limited PWM support
ARM: dts: mvebu: Add PWM properties to .dtsi files
ARM: mvebu: Enable SENSORS_PWM_FAN in defconfig
ARM: dts: armada-xp: Use pwm-fan rather than gpio-fan
.../devicetree/bindings/gpio/gpio-mvebu.txt | 32 ++
MAINTAINERS | 2 +
arch/arm/boot/dts/armada-370.dtsi | 19 +-
arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 8 +-
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 16 +-
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 19 +-
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 19 +-
arch/arm/configs/mvebu_v7_defconfig | 2 +
drivers/gpio/gpio-mvebu.c | 327 ++++++++++++++++++++-
9 files changed, 408 insertions(+), 36 deletions(-)
--
2.10.2
^ permalink raw reply
* Re: [PATCH v3 2/2] iio: dac: add support for stm32 DAC
From: Jonathan Cameron @ 2017-04-14 15:36 UTC (permalink / raw)
To: Fabrice Gasnier, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w,
alexandre.torgue-qxv4g6HH51o, lars-Qo5EllUWu/uELgA04lAiVw,
knaack.h-Mmb7MZpHnFY, pmeerw-jW+XmwGofnusTnJN9+BGXg,
benjamin.gaignard-QSEj5FYQhm4dnm+yROfE0A,
benjamin.gaignard-qxv4g6HH51o
In-Reply-To: <1491839390-2449-3-git-send-email-fabrice.gasnier-qxv4g6HH51o@public.gmane.org>
On 10/04/17 16:49, Fabrice Gasnier wrote:
> Add support for STMicroelectronics STM32 DAC. It's a 12-bit, voltage
> output digital-to-analog converter. It has two output channels, each
> with its own converter.
> It supports 8 bits or 12bits left/right aligned data format. Only
> 12bits right-aligned is used here. It has built-in noise or
> triangle waveform generator, and supports external triggers for
> conversions.
> Each channel can be used independently, with separate trigger, then
> separate IIO devices are used to handle this. Core driver is intended
> to share common resources such as clock, reset, reference voltage and
> registers.
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier-qxv4g6HH51o@public.gmane.org>
You did the constant attribute differently from how I would have done, but
it's a perfectly valid approach so that's fine with me. (I'll probably
regret that when it keeps getting copied form now on).
Looks good to me,
Applied to the togreg branch of iio.git and pushed out as testing for
the autobuilders to play with it.
Thanks,
Jonathan
> ---
> Changes in v3:
> - Fix powerdown, no need for 'enable', use 'three_state' as standard name
> for 'left floating' as per ABI documentation, instead of 'Hi-Z'.
>
> Changes in v2:
> - Define 'Hi-Z'/'enable' powerdown modes instead of using 'enable'
> attribute normally not used for DACs.
> - use 'reg' instead of 'st,dac-channel' property
> - Use macro to differentiate channels
> - Fix typos, remove leading '&' for functions
> - Add comments on single channel per device
> - Use devm_iio_device_register variant, removes need for .remove
> ---
> drivers/iio/dac/Kconfig | 15 ++
> drivers/iio/dac/Makefile | 2 +
> drivers/iio/dac/stm32-dac-core.c | 180 +++++++++++++++++++++
> drivers/iio/dac/stm32-dac-core.h | 51 ++++++
> drivers/iio/dac/stm32-dac.c | 334 +++++++++++++++++++++++++++++++++++++++
> 5 files changed, 582 insertions(+)
> create mode 100644 drivers/iio/dac/stm32-dac-core.c
> create mode 100644 drivers/iio/dac/stm32-dac-core.h
> create mode 100644 drivers/iio/dac/stm32-dac.c
>
> diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig
> index d3084028..7198648 100644
> --- a/drivers/iio/dac/Kconfig
> +++ b/drivers/iio/dac/Kconfig
> @@ -274,6 +274,21 @@ config MCP4922
> To compile this driver as a module, choose M here: the module
> will be called mcp4922.
>
> +config STM32_DAC
> + tristate "STMicroelectronics STM32 DAC"
> + depends on (ARCH_STM32 && OF) || COMPILE_TEST
> + depends on REGULATOR
> + select STM32_DAC_CORE
> + help
> + Say yes here to build support for STMicroelectronics STM32 Digital
> + to Analog Converter (DAC).
> +
> + This driver can also be built as a module. If so, the module
> + will be called stm32-dac.
> +
> +config STM32_DAC_CORE
> + tristate
> +
> config VF610_DAC
> tristate "Vybrid vf610 DAC driver"
> depends on OF
> diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile
> index f01bf4a..afe8ae7 100644
> --- a/drivers/iio/dac/Makefile
> +++ b/drivers/iio/dac/Makefile
> @@ -29,4 +29,6 @@ obj-$(CONFIG_MAX517) += max517.o
> obj-$(CONFIG_MAX5821) += max5821.o
> obj-$(CONFIG_MCP4725) += mcp4725.o
> obj-$(CONFIG_MCP4922) += mcp4922.o
> +obj-$(CONFIG_STM32_DAC_CORE) += stm32-dac-core.o
> +obj-$(CONFIG_STM32_DAC) += stm32-dac.o
> obj-$(CONFIG_VF610_DAC) += vf610_dac.o
> diff --git a/drivers/iio/dac/stm32-dac-core.c b/drivers/iio/dac/stm32-dac-core.c
> new file mode 100644
> index 0000000..75e4878
> --- /dev/null
> +++ b/drivers/iio/dac/stm32-dac-core.c
> @@ -0,0 +1,180 @@
> +/*
> + * This file is part of STM32 DAC driver
> + *
> + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
> + * Author: Fabrice Gasnier <fabrice.gasnier-qxv4g6HH51o@public.gmane.org>.
> + *
> + * License type: GPLv2
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
> + * or FITNESS FOR A PARTICULAR PURPOSE.
> + * See the GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/reset.h>
> +
> +#include "stm32-dac-core.h"
> +
> +/**
> + * struct stm32_dac_priv - stm32 DAC core private data
> + * @pclk: peripheral clock common for all DACs
> + * @rst: peripheral reset control
> + * @vref: regulator reference
> + * @common: Common data for all DAC instances
> + */
> +struct stm32_dac_priv {
> + struct clk *pclk;
> + struct reset_control *rst;
> + struct regulator *vref;
> + struct stm32_dac_common common;
> +};
> +
> +static struct stm32_dac_priv *to_stm32_dac_priv(struct stm32_dac_common *com)
> +{
> + return container_of(com, struct stm32_dac_priv, common);
> +}
> +
> +static const struct regmap_config stm32_dac_regmap_cfg = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = sizeof(u32),
> + .max_register = 0x3fc,
> +};
> +
> +static int stm32_dac_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct stm32_dac_priv *priv;
> + struct regmap *regmap;
> + struct resource *res;
> + void __iomem *mmio;
> + int ret;
> +
> + if (!dev->of_node)
> + return -ENODEV;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + mmio = devm_ioremap_resource(dev, res);
> + if (IS_ERR(mmio))
> + return PTR_ERR(mmio);
> +
> + regmap = devm_regmap_init_mmio(dev, mmio, &stm32_dac_regmap_cfg);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> + priv->common.regmap = regmap;
> +
> + priv->vref = devm_regulator_get(dev, "vref");
> + if (IS_ERR(priv->vref)) {
> + ret = PTR_ERR(priv->vref);
> + dev_err(dev, "vref get failed, %d\n", ret);
> + return ret;
> + }
> +
> + ret = regulator_enable(priv->vref);
> + if (ret < 0) {
> + dev_err(dev, "vref enable failed\n");
> + return ret;
> + }
> +
> + ret = regulator_get_voltage(priv->vref);
> + if (ret < 0) {
> + dev_err(dev, "vref get voltage failed, %d\n", ret);
> + goto err_vref;
> + }
> + priv->common.vref_mv = ret / 1000;
> + dev_dbg(dev, "vref+=%dmV\n", priv->common.vref_mv);
> +
> + priv->pclk = devm_clk_get(dev, "pclk");
> + if (IS_ERR(priv->pclk)) {
> + ret = PTR_ERR(priv->pclk);
> + dev_err(dev, "pclk get failed\n");
> + goto err_vref;
> + }
> +
> + ret = clk_prepare_enable(priv->pclk);
> + if (ret < 0) {
> + dev_err(dev, "pclk enable failed\n");
> + goto err_vref;
> + }
> +
> + priv->rst = devm_reset_control_get(dev, NULL);
> + if (!IS_ERR(priv->rst)) {
> + reset_control_assert(priv->rst);
> + udelay(2);
> + reset_control_deassert(priv->rst);
> + }
> +
> + /* When clock speed is higher than 80MHz, set HFSEL */
> + priv->common.hfsel = (clk_get_rate(priv->pclk) > 80000000UL);
> + ret = regmap_update_bits(regmap, STM32_DAC_CR, STM32H7_DAC_CR_HFSEL,
> + priv->common.hfsel ? STM32H7_DAC_CR_HFSEL : 0);
> + if (ret)
> + goto err_pclk;
> +
> + platform_set_drvdata(pdev, &priv->common);
> +
> + ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, dev);
> + if (ret < 0) {
> + dev_err(dev, "failed to populate DT children\n");
> + goto err_pclk;
> + }
> +
> + return 0;
> +
> +err_pclk:
> + clk_disable_unprepare(priv->pclk);
> +err_vref:
> + regulator_disable(priv->vref);
> +
> + return ret;
> +}
> +
> +static int stm32_dac_remove(struct platform_device *pdev)
> +{
> + struct stm32_dac_common *common = platform_get_drvdata(pdev);
> + struct stm32_dac_priv *priv = to_stm32_dac_priv(common);
> +
> + of_platform_depopulate(&pdev->dev);
> + clk_disable_unprepare(priv->pclk);
> + regulator_disable(priv->vref);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id stm32_dac_of_match[] = {
> + { .compatible = "st,stm32h7-dac-core", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, stm32_dac_of_match);
> +
> +static struct platform_driver stm32_dac_driver = {
> + .probe = stm32_dac_probe,
> + .remove = stm32_dac_remove,
> + .driver = {
> + .name = "stm32-dac-core",
> + .of_match_table = stm32_dac_of_match,
> + },
> +};
> +module_platform_driver(stm32_dac_driver);
> +
> +MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier-qxv4g6HH51o@public.gmane.org>");
> +MODULE_DESCRIPTION("STMicroelectronics STM32 DAC core driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:stm32-dac-core");
> diff --git a/drivers/iio/dac/stm32-dac-core.h b/drivers/iio/dac/stm32-dac-core.h
> new file mode 100644
> index 0000000..daf0993
> --- /dev/null
> +++ b/drivers/iio/dac/stm32-dac-core.h
> @@ -0,0 +1,51 @@
> +/*
> + * This file is part of STM32 DAC driver
> + *
> + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
> + * Author: Fabrice Gasnier <fabrice.gasnier-qxv4g6HH51o@public.gmane.org>.
> + *
> + * License type: GPLv2
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
> + * or FITNESS FOR A PARTICULAR PURPOSE.
> + * See the GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef __STM32_DAC_CORE_H
> +#define __STM32_DAC_CORE_H
> +
> +#include <linux/regmap.h>
> +
> +/* STM32 DAC registers */
> +#define STM32_DAC_CR 0x00
> +#define STM32_DAC_DHR12R1 0x08
> +#define STM32_DAC_DHR12R2 0x14
> +#define STM32_DAC_DOR1 0x2C
> +#define STM32_DAC_DOR2 0x30
> +
> +/* STM32_DAC_CR bit fields */
> +#define STM32_DAC_CR_EN1 BIT(0)
> +#define STM32H7_DAC_CR_HFSEL BIT(15)
> +#define STM32_DAC_CR_EN2 BIT(16)
> +
> +/**
> + * struct stm32_dac_common - stm32 DAC driver common data (for all instances)
> + * @regmap: DAC registers shared via regmap
> + * @vref_mv: reference voltage (mv)
> + * @hfsel: high speed bus clock selected
> + */
> +struct stm32_dac_common {
> + struct regmap *regmap;
> + int vref_mv;
> + bool hfsel;
> +};
> +
> +#endif
> diff --git a/drivers/iio/dac/stm32-dac.c b/drivers/iio/dac/stm32-dac.c
> new file mode 100644
> index 0000000..50f8ec0
> --- /dev/null
> +++ b/drivers/iio/dac/stm32-dac.c
> @@ -0,0 +1,334 @@
> +/*
> + * This file is part of STM32 DAC driver
> + *
> + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
> + * Authors: Amelie Delaunay <amelie.delaunay-qxv4g6HH51o@public.gmane.org>
> + * Fabrice Gasnier <fabrice.gasnier-qxv4g6HH51o@public.gmane.org>
> + *
> + * License type: GPLv2
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
> + * or FITNESS FOR A PARTICULAR PURPOSE.
> + * See the GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/delay.h>
> +#include <linux/iio/iio.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +
> +#include "stm32-dac-core.h"
> +
> +#define STM32_DAC_CHANNEL_1 1
> +#define STM32_DAC_CHANNEL_2 2
> +#define STM32_DAC_IS_CHAN_1(ch) ((ch) & STM32_DAC_CHANNEL_1)
> +
> +/**
> + * struct stm32_dac - private data of DAC driver
> + * @common: reference to DAC common data
> + */
> +struct stm32_dac {
> + struct stm32_dac_common *common;
> +};
> +
> +static int stm32_dac_is_enabled(struct iio_dev *indio_dev, int channel)
> +{
> + struct stm32_dac *dac = iio_priv(indio_dev);
> + u32 en, val;
> + int ret;
> +
> + ret = regmap_read(dac->common->regmap, STM32_DAC_CR, &val);
> + if (ret < 0)
> + return ret;
> + if (STM32_DAC_IS_CHAN_1(channel))
> + en = FIELD_GET(STM32_DAC_CR_EN1, val);
> + else
> + en = FIELD_GET(STM32_DAC_CR_EN2, val);
> +
> + return !!en;
> +}
> +
> +static int stm32_dac_set_enable_state(struct iio_dev *indio_dev, int ch,
> + bool enable)
> +{
> + struct stm32_dac *dac = iio_priv(indio_dev);
> + u32 msk = STM32_DAC_IS_CHAN_1(ch) ? STM32_DAC_CR_EN1 : STM32_DAC_CR_EN2;
> + u32 en = enable ? msk : 0;
> + int ret;
> +
> + ret = regmap_update_bits(dac->common->regmap, STM32_DAC_CR, msk, en);
> + if (ret < 0) {
> + dev_err(&indio_dev->dev, "%s failed\n", en ?
> + "Enable" : "Disable");
> + return ret;
> + }
> +
> + /*
> + * When HFSEL is set, it is not allowed to write the DHRx register
> + * during 8 clock cycles after the ENx bit is set. It is not allowed
> + * to make software/hardware trigger during this period either.
> + */
> + if (en && dac->common->hfsel)
> + udelay(1);
> +
> + return 0;
> +}
> +
> +static int stm32_dac_get_value(struct stm32_dac *dac, int channel, int *val)
> +{
> + int ret;
> +
> + if (STM32_DAC_IS_CHAN_1(channel))
> + ret = regmap_read(dac->common->regmap, STM32_DAC_DOR1, val);
> + else
> + ret = regmap_read(dac->common->regmap, STM32_DAC_DOR2, val);
> +
> + return ret ? ret : IIO_VAL_INT;
> +}
> +
> +static int stm32_dac_set_value(struct stm32_dac *dac, int channel, int val)
> +{
> + int ret;
> +
> + if (STM32_DAC_IS_CHAN_1(channel))
> + ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R1, val);
> + else
> + ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R2, val);
> +
> + return ret;
> +}
> +
> +static int stm32_dac_read_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + int *val, int *val2, long mask)
> +{
> + struct stm32_dac *dac = iio_priv(indio_dev);
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + return stm32_dac_get_value(dac, chan->channel, val);
> + case IIO_CHAN_INFO_SCALE:
> + *val = dac->common->vref_mv;
> + *val2 = chan->scan_type.realbits;
> + return IIO_VAL_FRACTIONAL_LOG2;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int stm32_dac_write_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + int val, int val2, long mask)
> +{
> + struct stm32_dac *dac = iio_priv(indio_dev);
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + return stm32_dac_set_value(dac, chan->channel, val);
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int stm32_dac_debugfs_reg_access(struct iio_dev *indio_dev,
> + unsigned reg, unsigned writeval,
> + unsigned *readval)
> +{
> + struct stm32_dac *dac = iio_priv(indio_dev);
> +
> + if (!readval)
> + return regmap_write(dac->common->regmap, reg, writeval);
> + else
> + return regmap_read(dac->common->regmap, reg, readval);
> +}
> +
> +static const struct iio_info stm32_dac_iio_info = {
> + .read_raw = stm32_dac_read_raw,
> + .write_raw = stm32_dac_write_raw,
> + .debugfs_reg_access = stm32_dac_debugfs_reg_access,
> + .driver_module = THIS_MODULE,
> +};
> +
> +static const char * const stm32_dac_powerdown_modes[] = {
> + "three_state",
> +};
> +
> +static int stm32_dac_get_powerdown_mode(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan)
> +{
> + return 0;
> +}
> +
> +static int stm32_dac_set_powerdown_mode(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + unsigned int type)
> +{
> + return 0;
> +}
Slightly novel usage of the enum code, but I suppose it does no harm.
I'd have gone with an IIO_CONST_ATTR but this does line up nicely
with other drivers so other than taking a few more lines, not much wrong
with it as an approach.
> +
> +static ssize_t stm32_dac_read_powerdown(struct iio_dev *indio_dev,
> + uintptr_t private,
> + const struct iio_chan_spec *chan,
> + char *buf)
> +{
> + int ret = stm32_dac_is_enabled(indio_dev, chan->channel);
> +
> + if (ret < 0)
> + return ret;
> +
> + return sprintf(buf, "%d\n", ret ? 0 : 1);
> +}
> +
> +static ssize_t stm32_dac_write_powerdown(struct iio_dev *indio_dev,
> + uintptr_t private,
> + const struct iio_chan_spec *chan,
> + const char *buf, size_t len)
> +{
> + bool powerdown;
> + int ret;
> +
> + ret = strtobool(buf, &powerdown);
> + if (ret)
> + return ret;
> +
> + ret = stm32_dac_set_enable_state(indio_dev, chan->channel, !powerdown);
> + if (ret)
> + return ret;
> +
> + return len;
> +}
> +
> +static const struct iio_enum stm32_dac_powerdown_mode_en = {
> + .items = stm32_dac_powerdown_modes,
> + .num_items = ARRAY_SIZE(stm32_dac_powerdown_modes),
> + .get = stm32_dac_get_powerdown_mode,
> + .set = stm32_dac_set_powerdown_mode,
> +};
> +
> +static const struct iio_chan_spec_ext_info stm32_dac_ext_info[] = {
> + {
> + .name = "powerdown",
> + .read = stm32_dac_read_powerdown,
> + .write = stm32_dac_write_powerdown,
> + .shared = IIO_SEPARATE,
> + },
> + IIO_ENUM("powerdown_mode", IIO_SEPARATE, &stm32_dac_powerdown_mode_en),
> + IIO_ENUM_AVAILABLE("powerdown_mode", &stm32_dac_powerdown_mode_en),
> + {},
> +};
> +
> +#define STM32_DAC_CHANNEL(chan, name) { \
> + .type = IIO_VOLTAGE, \
> + .indexed = 1, \
> + .output = 1, \
> + .channel = chan, \
> + .info_mask_separate = \
> + BIT(IIO_CHAN_INFO_RAW) | \
> + BIT(IIO_CHAN_INFO_SCALE), \
> + /* scan_index is always 0 as num_channels is 1 */ \
> + .scan_type = { \
> + .sign = 'u', \
> + .realbits = 12, \
> + .storagebits = 16, \
> + }, \
> + .datasheet_name = name, \
> + .ext_info = stm32_dac_ext_info \
> +}
> +
> +static const struct iio_chan_spec stm32_dac_channels[] = {
> + STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_1, "out1"),
> + STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_2, "out2"),
> +};
> +
> +static int stm32_dac_chan_of_init(struct iio_dev *indio_dev)
> +{
> + struct device_node *np = indio_dev->dev.of_node;
> + unsigned int i;
> + u32 channel;
> + int ret;
> +
> + ret = of_property_read_u32(np, "reg", &channel);
> + if (ret) {
> + dev_err(&indio_dev->dev, "Failed to read reg property\n");
> + return ret;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(stm32_dac_channels); i++) {
> + if (stm32_dac_channels[i].channel == channel)
> + break;
> + }
> + if (i >= ARRAY_SIZE(stm32_dac_channels)) {
> + dev_err(&indio_dev->dev, "Invalid st,dac-channel\n");
> + return -EINVAL;
> + }
> +
> + indio_dev->channels = &stm32_dac_channels[i];
> + /*
> + * Expose only one channel here, as they can be used independently,
> + * with separate trigger. Then separate IIO devices are instantiated
> + * to manage this.
> + */
> + indio_dev->num_channels = 1;
> +
> + return 0;
> +};
> +
> +static int stm32_dac_probe(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct iio_dev *indio_dev;
> + struct stm32_dac *dac;
> + int ret;
> +
> + if (!np)
> + return -ENODEV;
> +
> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*dac));
> + if (!indio_dev)
> + return -ENOMEM;
> + platform_set_drvdata(pdev, indio_dev);
> +
> + dac = iio_priv(indio_dev);
> + dac->common = dev_get_drvdata(pdev->dev.parent);
> + indio_dev->name = dev_name(&pdev->dev);
> + indio_dev->dev.parent = &pdev->dev;
> + indio_dev->dev.of_node = pdev->dev.of_node;
> + indio_dev->info = &stm32_dac_iio_info;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> +
> + ret = stm32_dac_chan_of_init(indio_dev);
> + if (ret < 0)
> + return ret;
> +
> + return devm_iio_device_register(&pdev->dev, indio_dev);
> +}
> +
> +static const struct of_device_id stm32_dac_of_match[] = {
> + { .compatible = "st,stm32-dac", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, stm32_dac_of_match);
> +
> +static struct platform_driver stm32_dac_driver = {
> + .probe = stm32_dac_probe,
> + .driver = {
> + .name = "stm32-dac",
> + .of_match_table = stm32_dac_of_match,
> + },
> +};
> +module_platform_driver(stm32_dac_driver);
> +
> +MODULE_ALIAS("platform:stm32-dac");
> +MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay-qxv4g6HH51o@public.gmane.org>");
> +MODULE_DESCRIPTION("STMicroelectronics STM32 DAC driver");
> +MODULE_LICENSE("GPL v2");
>
^ permalink raw reply
* Re: [PATCH 3/8] ARM: dts: imx7s: Adjust anatop-enable-bit for 'reg_1p0d'
From: Dong Aisheng @ 2017-04-14 15:32 UTC (permalink / raw)
To: Andrey Smirnov
Cc: Shawn Guo, yurovsky-Re5JQEeQqe8AvxtiuMwx3w, Sascha Hauer,
Fabio Estevam, Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170413133242.5068-4-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Thu, Apr 13, 2017 at 06:32:37AM -0700, Andrey Smirnov wrote:
> In PMU_REG_1P0Dn ENABLE_LINREG is bit 0. Bit 31 is called OVERRIDE and
> it serves the function of granting permission to GPC IP block to alter
> various bit-fields of the register. The reason why this property, that
> trickeld here from Freescale BSP, is set to 31 is because in the code
> it came from it is used in conjunction with a notifier handler for
> REGULATOR_EVENT_PRE_DO_ENABLE and REGULATOR_EVENT_PRE_DO_DISABLE
> events (not found in upstream kernel) that triggers GPC to start
> manipulating aforementioned other bitfields.
>
> Since:
> a) none of the aforementioned machinery is implemented by
> upstream
> b) using 'anatop-enable-bit' in that capacity is a bit of a
> semantic stretch
Yes, this does is a bit of semantic stretch.
FSL using is combined with regulator notify and that do bring a bit
of complexity.
I'm not sure if it's good to introduce another anatop-override-bit
to separate, but i'm a bit scare since there's already many....
>
> simplify the situation by setting the value of 'anatop-enable-bit' to
> point to ENABLE_LINREG (same as i.MX6).
>
> Cc: yurovsky-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
> Cc: Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Cc: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> arch/arm/boot/dts/imx7s.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
> index 22c9788..8fee299 100644
> --- a/arch/arm/boot/dts/imx7s.dtsi
> +++ b/arch/arm/boot/dts/imx7s.dtsi
> @@ -516,7 +516,7 @@
> anatop-min-bit-val = <8>;
> anatop-min-voltage = <800000>;
> anatop-max-voltage = <1200000>;
> - anatop-enable-bit = <31>;
> + anatop-enable-bit = <0>;
The change of this line seems already exist in patch 1.
Regards
Dong Aisheng
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^ permalink raw reply
* Re: [PATCH 6/8] ARM: dts: imx7d-sdb: Add GPIO expander node
From: Andrey Smirnov @ 2017-04-14 15:32 UTC (permalink / raw)
To: Shawn Guo
Cc: Andrey Yurovsky, Sascha Hauer, Fabio Estevam, Rob Herring,
Mark Rutland, Russell King, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel, linux-arm-kernel
In-Reply-To: <20170414034659.GH14915@dragon>
On Thu, Apr 13, 2017 at 8:47 PM, Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Thu, Apr 13, 2017 at 06:32:40AM -0700, Andrey Smirnov wrote:
>> Add node for U38, a 74LV595PW serial-in shift register that acts as a
>> GPIO expander on the board.
>>
>> Cc: yurovsky-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
>> Cc: Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
>> Cc: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
>> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
>> Cc: Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>
>> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>> Signed-off-by: Andrey Smirnov <andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>> arch/arm/boot/dts/imx7d-sdb.dts | 32 ++++++++++++++++++++++++++++++++
>> 1 file changed, 32 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
>> index 5be01a1..e0ff276 100644
>> --- a/arch/arm/boot/dts/imx7d-sdb.dts
>> +++ b/arch/arm/boot/dts/imx7d-sdb.dts
>> @@ -52,6 +52,30 @@
>> reg = <0x80000000 0x80000000>;
>> };
>>
>> + spi4 {
>> + compatible = "spi-gpio";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_spi1>;
>> + status = "okay";
>
> The 'status' is not needed in this case.
>
Missed that, will fix in v2.
>> + gpio-sck = <&gpio1 13 0>;
>> + gpio-mosi = <&gpio1 9 0>;
>> + cs-gpios = <&gpio1 12 0>;
>> + num-chipselects = <1>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + gpio_spi: gpio_spi@0 {
>
> gpio-expander might be a better node name?
>
Yeah, I agree. I'll change it to extended_io: gpio-expander@0
("Extended IO" is how this part is called out on the schematic)
>> + compatible = "fairchild,74hc595";
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + reg = <0>;
>> + registers-number = <1>;
>> + /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/
>> + registers-default = /bits/ 8 <0x74>;
>
> I do not see this property is documented or supported by kernel.
My bad, some downstream properties leakage. Will remove in v2.
Thanks,
Andrey Smirnov
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^ permalink raw reply
* Re: [PATCH v2 5/5] iio: dac: stm32: add support for waveform generator
From: Jonathan Cameron @ 2017-04-14 15:28 UTC (permalink / raw)
To: Fabrice Gasnier, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w,
alexandre.torgue-qxv4g6HH51o, lars-Qo5EllUWu/uELgA04lAiVw,
knaack.h-Mmb7MZpHnFY, pmeerw-jW+XmwGofnusTnJN9+BGXg,
benjamin.gaignard-QSEj5FYQhm4dnm+yROfE0A,
benjamin.gaignard-qxv4g6HH51o
In-Reply-To: <779a0082-3760-75c4-2fd3-b8a5b70dbaf8-qxv4g6HH51o@public.gmane.org>
On 10/04/17 17:43, Fabrice Gasnier wrote:
> On 04/09/2017 11:34 AM, Jonathan Cameron wrote:
>> On 06/04/17 17:11, Fabrice Gasnier wrote:
>>> STM32 DAC has built-in noise or triangle waveform generator.
>>> - "wavetype" extended attribute selects noise or triangle.
>>> - "amplitude" extended attribute selects amplitude for waveform generator
>>>
>>> A DC offset can be added to waveform generator output. This can be done
>>> using out_voltage[1/2]_offset
>>>
>>> Waveform generator requires a trigger to be configured, to increment /
>>> decrement internal counter in case of triangle generator. Noise
>>> generator is a bit different, but also requires a trigger to generate
>>> samples.
>>>
>>> Signed-off-by: Fabrice Gasnier <fabrice.gasnier-qxv4g6HH51o@public.gmane.org>
>>
>> Various bits inline. Mostly I think the blockers on this will be
>> making sure the ABI defined is generic enough to handle the more crazy
>> DDS chips out there... (basically the ones doing frequency modulation).
>>
>> Jonathan
>>> ---
>>> Changes in v2:
>>> - use _offset parameter to add DC offset to waveform generator
>> Conceptually this offset is just the normal DAC output value (particularly
> yes
>> in the flat case) I guess we can paper over this by having the _raw
>> and this always have th same value, but it's a little inelegant.
>> Still people are going to expect _raw to control it when in DAC mode but
>> that makes limited sense in DDS mode.
>>
>> Mind you nothing stops us defining all DDS channels as the sum of whatever
>> the DDS is doing and whatever is _raw is set to. Perhaps we tidy this up
>> purely through documentation. Think of the DDS as a modulation on top
>> of the DAC...
>>
>>> - Rework ABI to better fit existing DDS ABI: use out_voltageY_wavetype,
>>> out_voltage_wavetype_available, out_voltageY_amplitude,
>>> out_voltage_amplitude_available
>> Hmm. I'm thinking those amplitude values aren't nice and don't fit well
>> with the more general ABI.
>>
>> I suggested (but didn't really expand upon) having standard defined types
>> for each waveform then using scale to control the amplitude.
>
> Do you mean _scale attribute ?
Yes
>>
>> Is that something that might work here?
>
> I probably miss the point here...
>>
>> So say we have our triangle standard form having an amplitude of 1V Peak to
>> Peak. Then we can use scale to make it whatever we actually have in this
>> case? The docs for wave type will need to describe those standard forms
>> though.
> ... scale is fixed here, in line with _raw attribute. In 'amplitude'
> description for STM32 DAC here (e.g. from 1...4095), same scale is used.
> Can you elaborate ?
Good point - it is already effectively been applied to the _raw
value - I'd forgotten that.
Seems like abuse of the ABI to use calibscale, so we might need something
new here - wavescale maybe or ddsscale? Not sure.
>
>>
>> Hmm. Whether this is worth doing is unclear however as we'll still have
>> to describe the 'frequency' in terms of the clock ticks (here the triggers)
>
> Describing frequency may be an issue, not sure it makes senses in this
> case: 'clock ticks', e.g. triggers here may be timers, but also an EXTI
> (external...), or even software trig perhaps.
To describe the waveform in a remotely standard way we'll have to address
this to some degree. What's the slope?
>
>> So maybe amplitude is worth having. Again, looking for input from ADI lot
>> on this... There are some really fiddly cases to describe were we are doing
>> symbol encoding so have multiple waveforms that we are switching between based
>> on some external signal. Any ABI needs to encompass that sort of usage.
>> Parts like the AD9833 for example...
>>
>>> - Better explain trigger usage in case of waveform generator.
>>> ---
>>> Documentation/ABI/testing/sysfs-bus-iio-dac-stm32 | 16 +++
>>> drivers/iio/dac/stm32-dac-core.h | 4 +
>>> drivers/iio/dac/stm32-dac.c | 158 +++++++++++++++++++++-
>>> 3 files changed, 177 insertions(+), 1 deletion(-)
>>> create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-dac-stm32
>>>
>>> diff --git a/Documentation/ABI/testing/sysfs-bus-iio-dac-stm32 b/Documentation/ABI/testing/sysfs-bus-iio-dac-stm32
>>> new file mode 100644
>>> index 0000000..8f1fa009
>>> --- /dev/null
>>> +++ b/Documentation/ABI/testing/sysfs-bus-iio-dac-stm32
>> Fair enough to initially introduced these for this part only, but I'd very
>> much like to see us agree on these sufficiently to get them into the main
>> docs asap so we have something to work with for getting the DDS chips out
>> of staging...
>>> @@ -0,0 +1,16 @@
>>> +What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_wavetype
>>> +What: /sys/bus/iio/devices/iio:deviceX/out_voltage_wavetype_available
>>> +KernelVersion: 4.12
>>> +Contact: fabrice.gasnier-qxv4g6HH51o@public.gmane.org
>>> +Description:
>>> + List and/or select waveform generation provided by STM32 DAC:
>>> + - "flat": waveform generator disabled (default)
>>> + - "noise": select noise waveform
>>> + - "triangle": select triangle waveform
>>> +
>>> +What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_amplitude
>>> +What: /sys/bus/iio/devices/iio:deviceX/out_voltage_amplitude_available
>>> +KernelVersion: 4.12
>>> +Contact: fabrice.gasnier-qxv4g6HH51o@public.gmane.org
>>> +Description:
>>> + List and/or select amplitude used for waveform generator
>>> diff --git a/drivers/iio/dac/stm32-dac-core.h b/drivers/iio/dac/stm32-dac-core.h
>>> index e51a468..0f02975 100644
>>> --- a/drivers/iio/dac/stm32-dac-core.h
>>> +++ b/drivers/iio/dac/stm32-dac-core.h
>>> @@ -37,8 +37,12 @@
>>> #define STM32H7_DAC_CR_TEN1 BIT(1)
>>> #define STM32H7_DAC_CR_TSEL1_SHIFT 2
>>> #define STM32H7_DAC_CR_TSEL1 GENMASK(5, 2)
>>> +#define STM32_DAC_CR_WAVE1 GENMASK(7, 6)
>>> +#define STM32_DAC_CR_MAMP1 GENMASK(11, 8)
>>> #define STM32H7_DAC_CR_HFSEL BIT(15)
>>> #define STM32_DAC_CR_EN2 BIT(16)
>>> +#define STM32_DAC_CR_WAVE2 GENMASK(23, 22)
>>> +#define STM32_DAC_CR_MAMP2 GENMASK(27, 24)
>>>
>>> /* STM32_DAC_SWTRIGR bit fields */
>>> #define STM32_DAC_SWTRIGR_SWTRIG1 BIT(0)
>>> diff --git a/drivers/iio/dac/stm32-dac.c b/drivers/iio/dac/stm32-dac.c
>>> index a7a078e..2ed75db 100644
>>> --- a/drivers/iio/dac/stm32-dac.c
>>> +++ b/drivers/iio/dac/stm32-dac.c
>>> @@ -42,10 +42,12 @@
>>> /**
>>> * struct stm32_dac - private data of DAC driver
>>> * @common: reference to DAC common data
>>> + * @wavetype: waveform generator
>>> * @swtrig: Using software trigger
>>> */
>>> struct stm32_dac {
>>> struct stm32_dac_common *common;
>>> + u32 wavetype;
>>> bool swtrig;
>>> };
>>>
>>> @@ -222,6 +224,29 @@ static int stm32_dac_set_value(struct stm32_dac *dac, int channel, int val)
>>> return ret;
>>> }
>>>
>>> +static int stm32_dac_get_offset(struct stm32_dac *dac, int channel, int *val)
>>> +{
>>> + int ret;
>>> +
>>> + /* Offset is only relevant in waveform generation mode. */
>>> + if (!dac->wavetype) {
>>> + *val = 0;
>>> + return IIO_VAL_INT;
>>> + }
>>> +
>>> + /*
>>> + * In waveform generation mode, DC offset in DHR is added to waveform
>>> + * generator output, then stored to DOR (data output register).
>>> + * Read offset from DHR.
>>> + */
>> Just thinking what fun we could have if we do the fifo based output to push
>> this that I was suggesting for the previous patch ;) triangles on top
>> of fun general waveforms..
>>
>>> + if (STM32_DAC_IS_CHAN_1(channel))
>>> + ret = regmap_read(dac->common->regmap, STM32_DAC_DHR12R1, val);
>>> + else
>>> + ret = regmap_read(dac->common->regmap, STM32_DAC_DHR12R2, val);
>>> +
>>> + return ret ? ret : IIO_VAL_INT;
>>> +}
>>> +
>>> static int stm32_dac_read_raw(struct iio_dev *indio_dev,
>>> struct iio_chan_spec const *chan,
>>> int *val, int *val2, long mask)
>>> @@ -231,6 +256,8 @@ static int stm32_dac_read_raw(struct iio_dev *indio_dev,
>>> switch (mask) {
>>> case IIO_CHAN_INFO_RAW:
>>> return stm32_dac_get_value(dac, chan->channel, val);
>>> + case IIO_CHAN_INFO_OFFSET:
>>> + return stm32_dac_get_offset(dac, chan->channel, val);
>>> case IIO_CHAN_INFO_SCALE:
>>> *val = dac->common->vref_mv;
>>> *val2 = chan->scan_type.realbits;
>>> @@ -247,8 +274,16 @@ static int stm32_dac_write_raw(struct iio_dev *indio_dev,
>>> struct stm32_dac *dac = iio_priv(indio_dev);
>>>
>>> switch (mask) {
>>> + case IIO_CHAN_INFO_OFFSET:
>>> + /* Offset only makes sense in waveform generation mode */
>>> + if (dac->wavetype)
>>> + return stm32_dac_set_value(dac, chan->channel, val);
>>> + return -EBUSY;
>> Yeah, I think I sent you down a blind alley here. If people agree, lets
>> just define DDS signals as always being the sum of _raw + the dds element.
>> Then it's easy.
> Ok, I can revert back to use _raw if this is fine ;-)
>
>>> case IIO_CHAN_INFO_RAW:
>>> - return stm32_dac_set_value(dac, chan->channel, val);
>>> + if (!dac->wavetype)
>>> + return stm32_dac_set_value(dac, chan->channel, val);
>>> + /* raw value is read only in waveform generation mode */
>>> + return -EBUSY;
>>> default:
>>> return -EINVAL;
>>> }
>>> @@ -334,6 +369,122 @@ static ssize_t stm32_dac_write_powerdown(struct iio_dev *indio_dev,
>>> .set = stm32_dac_set_powerdown_mode,
>>> };
>>>
>>> +/* waveform generator wave selection */
>>> +static const char * const stm32_dac_wavetype_desc[] = {
>>> + "flat",
>>> + "noise",
>>> + "triangle",
>>> +};
>>> +
>>> +static int stm32_dac_set_wavetype(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan,
>>> + unsigned int wavetype)
>>> +{
>>> + struct stm32_dac *dac = iio_priv(indio_dev);
>>> + u32 mask, val;
>>> + int ret;
>>> +
>>> + /*
>>> + * Waveform generator requires a trigger to be configured, to increment
>>> + * or decrement internal counter in case of triangle generator. Noise
>>> + * generator is a bit different, but also requires a trigger to
>>> + * generate samples.
>>> + */
>>> + if (wavetype && !indio_dev->trig)
>>> + dev_dbg(&indio_dev->dev, "Wavegen requires a trigger\n");
>>> +
>>> + if (STM32_DAC_IS_CHAN_1(chan->channel)) {
>>> + val = FIELD_PREP(STM32_DAC_CR_WAVE1, wavetype);
>>> + mask = STM32_DAC_CR_WAVE1;
>>> + } else {
>>> + val = FIELD_PREP(STM32_DAC_CR_WAVE2, wavetype);
>>> + mask = STM32_DAC_CR_WAVE2;
>>> + }
>>> +
>>> + ret = regmap_update_bits(dac->common->regmap, STM32_DAC_CR, mask, val);
>>> + if (ret)
>>> + return ret;
>>> + dac->wavetype = wavetype;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int stm32_dac_get_wavetype(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan)
>>> +{
>>> + struct stm32_dac *dac = iio_priv(indio_dev);
>>> + u32 val;
>>> + int ret;
>>> +
>>> + ret = regmap_read(dac->common->regmap, STM32_DAC_CR, &val);
>>> + if (ret < 0)
>>> + return ret;
>>> +
>>> + if (STM32_DAC_IS_CHAN_1(chan->channel))
>>> + return FIELD_GET(STM32_DAC_CR_WAVE1, val);
>>> + else
>>> + return FIELD_GET(STM32_DAC_CR_WAVE2, val);
>>> +}
>>> +
>>> +static const struct iio_enum stm32_dac_wavetype_enum = {
>>> + .items = stm32_dac_wavetype_desc,
>>> + .num_items = ARRAY_SIZE(stm32_dac_wavetype_desc),
>>> + .get = stm32_dac_get_wavetype,
>>> + .set = stm32_dac_set_wavetype,
>>> +};
>>> +
>>> +/*
>>> + * waveform generator mamp selection: mask/amplitude
>>> + * - noise: LFSR mask (linear feedback shift register, umasks bit 0, [1:0]...)
>> This needs breaking out into two attributes - for noise it isn't amplitude in
>> any conventional sense... Keep the result device specific for now. I'm not
>> even sure what type of pseudo random source that actually is...
> Do you suggest to create specific attribute for this ? This will end-up
> to write same register/bitfield as 'amplitude' for triangle generator.
I think it should definitely be a separate attribute. Otherwise the userspace
ABI will be really confusing as this definitely isn't amplitude in any normal
sense!
>
> Thanks & Regards,
> Fabrice
>
>> If anyone wants to figure it out it would be great to document it in a general
>> form!
>>
>>> + * - triangle: amplitude (equal to 1, 3, 5, 7... 4095)
>>> + */
>>> +static const char * const stm32_dac_amplitude_desc[] = {
>>> + "1", "3", "7", "15", "31", "63", "127", "255", "511", "1023", "2047",
>>> + "4095",
>>> +};
>>> +
>>> +static int stm32_dac_set_amplitude(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan,
>>> + unsigned int amplitude)
>>> +{
>>> + struct stm32_dac *dac = iio_priv(indio_dev);
>>> + u32 mask, val;
>>> +
>>> + if (STM32_DAC_IS_CHAN_1(chan->channel)) {
>>> + val = FIELD_PREP(STM32_DAC_CR_MAMP1, amplitude);
>>> + mask = STM32_DAC_CR_MAMP1;
>>> + } else {
>>> + val = FIELD_PREP(STM32_DAC_CR_MAMP2, amplitude);
>>> + mask = STM32_DAC_CR_MAMP2;
>>> + }
>>> +
>>> + return regmap_update_bits(dac->common->regmap, STM32_DAC_CR, mask, val);
>>> +}
>>> +
>>> +static int stm32_dac_get_amplitude(struct iio_dev *indio_dev,
>>> + const struct iio_chan_spec *chan)
>>> +{
>>> + struct stm32_dac *dac = iio_priv(indio_dev);
>>> + u32 val;
>>> + int ret;
>>> +
>>> + ret = regmap_read(dac->common->regmap, STM32_DAC_CR, &val);
>>> + if (ret < 0)
>>> + return ret;
>>> +
>>> + if (STM32_DAC_IS_CHAN_1(chan->channel))
>>> + return FIELD_GET(STM32_DAC_CR_MAMP1, val);
>>> + else
>>> + return FIELD_GET(STM32_DAC_CR_MAMP2, val);
>>> +}
>>> +
>>> +static const struct iio_enum stm32_dac_amplitude_enum = {
>>> + .items = stm32_dac_amplitude_desc,
>>> + .num_items = ARRAY_SIZE(stm32_dac_amplitude_desc),
>>> + .get = stm32_dac_get_amplitude,
>>> + .set = stm32_dac_set_amplitude,
>>> +};
>>> +
>>> static const struct iio_chan_spec_ext_info stm32_dac_ext_info[] = {
>>> {
>>> .name = "powerdown",
>>> @@ -343,6 +494,10 @@ static ssize_t stm32_dac_write_powerdown(struct iio_dev *indio_dev,
>>> },
>>> IIO_ENUM("powerdown_mode", IIO_SEPARATE, &stm32_dac_powerdown_mode_en),
>>> IIO_ENUM_AVAILABLE("powerdown_mode", &stm32_dac_powerdown_mode_en),
>>> + IIO_ENUM("wavetype", IIO_SEPARATE, &stm32_dac_wavetype_enum),
>>> + IIO_ENUM_AVAILABLE("wavetype", &stm32_dac_wavetype_enum),
>>> + IIO_ENUM("amplitude", IIO_SEPARATE, &stm32_dac_amplitude_enum),
>>> + IIO_ENUM_AVAILABLE("amplitude", &stm32_dac_amplitude_enum),
>>> {},
>>> };
>>>
>>> @@ -352,6 +507,7 @@ static ssize_t stm32_dac_write_powerdown(struct iio_dev *indio_dev,
>>> .output = 1, \
>>> .channel = chan, \
>>> .info_mask_separate = \
>>> + BIT(IIO_CHAN_INFO_OFFSET) | \
>>> BIT(IIO_CHAN_INFO_RAW) | \
>>> BIT(IIO_CHAN_INFO_SCALE), \
>>> /* scan_index is always 0 as num_channels is 1 */ \
>>>
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* Re: [PATCH 6/8] ARM: dts: imx7d-sdb: Add GPIO expander node
From: Andrey Smirnov @ 2017-04-14 15:25 UTC (permalink / raw)
To: Fabio Estevam
Cc: Shawn Guo, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Russell King,
linux-kernel, Rob Herring, Sascha Hauer, Fabio Estevam,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Andrey Yurovsky
In-Reply-To: <CAOMZO5A9u9bjbFa=0LQ_gnwFry4wm2HGD8xncThb3ta1TaZ1aw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Thu, Apr 13, 2017 at 3:20 PM, Fabio Estevam <festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> Hi Andrey,
>
> On Thu, Apr 13, 2017 at 10:32 AM, Andrey Smirnov
> <andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>
>> diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
>> index 5be01a1..e0ff276 100644
>> --- a/arch/arm/boot/dts/imx7d-sdb.dts
>> +++ b/arch/arm/boot/dts/imx7d-sdb.dts
>> @@ -52,6 +52,30 @@
>> reg = <0x80000000 0x80000000>;
>> };
>>
>> + spi4 {
>
> Here you use spi4 label...
>
>> + compatible = "spi-gpio";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_spi1>;
>
> and here spi1, which is a bit confusing.
>
Agreed. It is confusing, will fix in v2.
>> + status = "okay";
>> + gpio-sck = <&gpio1 13 0>;
>> + gpio-mosi = <&gpio1 9 0>;
>> + cs-gpios = <&gpio1 12 0>;
>
> You could use GPIO_ACTIVE_HIGH flag for better readability.
Missed that, will fix in v2.
Thanks,
Andrey Smirnov
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH V5 2/2] thermal: broadcom: add Northstar thermal driver
From: Rafał Miłecki @ 2017-04-14 15:19 UTC (permalink / raw)
To: Eduardo Valentin
Cc: Rafał Miłecki, Zhang Rui, Rob Herring, Mark Rutland,
Stephen Warren, Lee Jones, Eric Anholt, Florian Fainelli, Ray Jui,
Scott Branden, bcm-kernel-feedback-list, linux-pm,
devicetree@vger.kernel.org, linux-rpi-kernel,
linux-arm-kernel@lists.infradead.org, Jon Mason
In-Reply-To: <20170414151613.GA24429@localhost.localdomain>
On 14 April 2017 at 17:16, Eduardo Valentin <edubezval@gmail.com> wrote:
> Hello Rafal,
>
> On Fri, Apr 14, 2017 at 02:16:36PM +0200, Rafał Miłecki wrote:
>> On 04/07/2017 06:42 AM, Eduardo Valentin wrote:
>> >On Mon, Apr 03, 2017 at 05:48:29PM +0200, Rafał Miłecki wrote:
>> >>From: Rafał Miłecki <rafal@milecki.pl>
>> >>
>> >>Northstar is a SoC family commonly used in home routers. This commit
>> >>adds a driver for checking CPU temperature. As Northstar Plus seems to
>> >>also have this IP block this new symbol gets ARCH_BCM_IPROC dependency.
>> >>
>> >>Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
>> >>Signed-off-by: Jon Mason <jon.mason@broadcom.com>
>> >
>> >If no objection, I am applying this series.
>>
>> Cool, hopefully there aren't any more objections :) Once applied should I
>> expect this in
>> https://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git/log/?h=next
>> ?
>
> They were already applied, but in my #linus branch. Now they are also in
> my #next branch. The #linus branch goes to the coming merge window. The
> #next branch goes to linux-next testing. Your change is now on
> linux-next test, kernelci testing, and for the coming merge windown.
I got it, thank you!
--
Rafał
^ permalink raw reply
* Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC
From: Andrey Smirnov @ 2017-04-14 15:19 UTC (permalink / raw)
To: Shawn Guo
Cc: Andrey Yurovsky, Sascha Hauer, Fabio Estevam, Rob Herring,
Mark Rutland, Russell King, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20170414034005.GG14915@dragon>
On Thu, Apr 13, 2017 at 8:40 PM, Shawn Guo <shawnguo@kernel.org> wrote:
> On Thu, Apr 13, 2017 at 06:32:38AM -0700, Andrey Smirnov wrote:
>> Add node for GPC and specify as a parent interrupt controller for SoC bus.
>>
>> Cc: yurovsky@gmail.com
>> Cc: Sascha Hauer <kernel@pengutronix.de>
>> Cc: Fabio Estevam <fabio.estevam@nxp.com>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Russell King <linux@armlinux.org.uk>
>> Cc: devicetree@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Cc: linux-arm-kernel@lists.infradead.org
>> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
>> ---
>> arch/arm/boot/dts/imx7s.dtsi | 27 ++++++++++++++++++++++++++-
>> 1 file changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
>> index 8fee299..1a7058f 100644
>> --- a/arch/arm/boot/dts/imx7s.dtsi
>> +++ b/arch/arm/boot/dts/imx7s.dtsi
>> @@ -42,6 +42,7 @@
>> */
>>
>> #include <dt-bindings/clock/imx7d-clock.h>
>> +#include <dt-bindings/power/imx7-power.h>
>> #include <dt-bindings/gpio/gpio.h>
>> #include <dt-bindings/input/input.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> @@ -119,7 +120,7 @@
>> #address-cells = <1>;
>> #size-cells = <1>;
>> compatible = "simple-bus";
>> - interrupt-parent = <&intc>;
>> + interrupt-parent = <&gpc>;
>> ranges;
>>
>> funnel@30041000 {
>> @@ -301,6 +302,7 @@
>> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> #interrupt-cells = <3>;
>> interrupt-controller;
>> + interrupt-parent = <&intc>;
>> reg = <0x31001000 0x1000>,
>> <0x31002000 0x2000>,
>> <0x31004000 0x2000>,
>> @@ -309,6 +311,7 @@
>>
>> timer {
>> compatible = "arm,armv7-timer";
>> + interrupt-parent = <&intc>;
>> interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> @@ -564,6 +567,28 @@
>> interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>> #reset-cells = <1>;
>> };
>> +
>> + gpc: gpc@303a0000 {
>> + compatible = "fsl,imx7d-gpc";
>> + reg = <0x303a0000 0x10000>;
>> + interrupt-controller;
>> + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
>> + #interrupt-cells = <3>;
>> + interrupt-parent = <&intc>;
>> + #power-domain-cells = <1>;
>> +
>> + pgc {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + pgc_pcie_phy: pgc-pcie-phy-domain {
>
> The node name should be something generic and has a unit-address when
> there is a 'reg' property in the node.
>
I'll change it to pgc-power-domain@0, let me know if you want
something different.
>> + #power-domain-cells = <0>;
>> +
>
> Drop this newline.
>
OK. Will do in v2.
^ permalink raw reply
* Re: [PATCH V5 2/2] thermal: broadcom: add Northstar thermal driver
From: Eduardo Valentin @ 2017-04-14 15:16 UTC (permalink / raw)
To: Rafał Miłecki
Cc: Rafał Miłecki, Zhang Rui, Rob Herring, Mark Rutland,
Stephen Warren, Lee Jones, Eric Anholt, Florian Fainelli, Ray Jui,
Scott Branden, bcm-kernel-feedback-list, linux-pm, devicetree,
linux-rpi-kernel, linux-arm-kernel, Jon Mason
In-Reply-To: <6dd2617d-a8a8-d7a4-53a4-7ebcb274573c@milecki.pl>
[-- Attachment #1: Type: text/plain, Size: 1607 bytes --]
Hello Rafal,
On Fri, Apr 14, 2017 at 02:16:36PM +0200, Rafał Miłecki wrote:
> On 04/07/2017 06:42 AM, Eduardo Valentin wrote:
> >On Mon, Apr 03, 2017 at 05:48:29PM +0200, Rafał Miłecki wrote:
> >>From: Rafał Miłecki <rafal@milecki.pl>
> >>
> >>Northstar is a SoC family commonly used in home routers. This commit
> >>adds a driver for checking CPU temperature. As Northstar Plus seems to
> >>also have this IP block this new symbol gets ARCH_BCM_IPROC dependency.
> >>
> >>Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
> >>Signed-off-by: Jon Mason <jon.mason@broadcom.com>
> >
> >If no objection, I am applying this series.
>
> Cool, hopefully there aren't any more objections :) Once applied should I
> expect this in
> https://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git/log/?h=next
> ?
They were already applied, but in my #linus branch. Now they are also in
my #next branch. The #linus branch goes to the coming merge window. The
#next branch goes to linux-next testing. Your change is now on
linux-next test, kernelci testing, and for the coming merge windown.
>
> That would allow me to move bcm2835_thermal.c to the broadcom subdir.
>
>
Please send the patch.
> >>+const struct thermal_zone_of_device_ops ns_thermal_ops = {
> >
> >minor correction here:
> >
> >-const struct thermal_zone_of_device_ops ns_thermal_ops = {
> >+static const struct thermal_zone_of_device_ops ns_thermal_ops = {
> >
> >but I am applying this already in my tree.
> >
> >>+ .get_temp = ns_thermal_get_temp,
> >>+};
>
> Thank you!
[-- Attachment #2: Digital signature --]
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^ permalink raw reply
* Re: [PATCH 3/8] ARM: dts: imx7s: Adjust anatop-enable-bit for 'reg_1p0d'
From: Andrey Smirnov @ 2017-04-14 14:33 UTC (permalink / raw)
To: Shawn Guo
Cc: Andrey Yurovsky, Sascha Hauer, Fabio Estevam, Rob Herring,
Mark Rutland, Russell King, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20170414032853.GF14915@dragon>
On Thu, Apr 13, 2017 at 8:28 PM, Shawn Guo <shawnguo@kernel.org> wrote:
> On Thu, Apr 13, 2017 at 06:32:37AM -0700, Andrey Smirnov wrote:
>> In PMU_REG_1P0Dn ENABLE_LINREG is bit 0. Bit 31 is called OVERRIDE and
>> it serves the function of granting permission to GPC IP block to alter
>> various bit-fields of the register. The reason why this property, that
>> trickeld here from Freescale BSP, is set to 31 is because in the code
>> it came from it is used in conjunction with a notifier handler for
>> REGULATOR_EVENT_PRE_DO_ENABLE and REGULATOR_EVENT_PRE_DO_DISABLE
>> events (not found in upstream kernel) that triggers GPC to start
>> manipulating aforementioned other bitfields.
>>
>> Since:
>> a) none of the aforementioned machinery is implemented by
>> upstream
>> b) using 'anatop-enable-bit' in that capacity is a bit of a
>> semantic stretch
>>
>> simplify the situation by setting the value of 'anatop-enable-bit' to
>> point to ENABLE_LINREG (same as i.MX6).
>>
>> Cc: yurovsky@gmail.com
>> Cc: Sascha Hauer <kernel@pengutronix.de>
>> Cc: Fabio Estevam <fabio.estevam@nxp.com>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Russell King <linux@armlinux.org.uk>
>> Cc: devicetree@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Cc: linux-arm-kernel@lists.infradead.org
>> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
>
> Since patch 1 ~ 3 are all about adding anatop-enable-bit, can we squash
> them into one patch?
OK. Will do in v2.
^ permalink raw reply
* [PATCH v2 1/2] dt-binding: regulator: anatop: make regulator name property required
From: Dong Aisheng @ 2017-04-14 14:30 UTC (permalink / raw)
To: linux-kernel; +Cc: Dong Aisheng, Rob Herring, Mark Rutland, devicetree
We actually can't allow the missing of the regualor name, thus update
the binding doc to make regulator-name property to be required.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
Documentation/devicetree/bindings/regulator/anatop-regulator.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
index 1d58c8c..a3106c7 100644
--- a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
@@ -2,6 +2,7 @@ Anatop Voltage regulators
Required properties:
- compatible: Must be "fsl,anatop-regulator"
+- regulator-name: A string used as a descriptive name for regulator outputs
- anatop-reg-offset: Anatop MFD register offset
- anatop-vol-bit-shift: Bit shift for the register
- anatop-vol-bit-width: Number of bits used in the register
--
2.7.4
^ permalink raw reply related
* Re: [GIT PULL] Immutable branch between MFD and IIO due for the v4.12 merge window
From: Jonathan Cameron @ 2017-04-14 14:30 UTC (permalink / raw)
To: Lee Jones, Quentin Schulz
Cc: mark.rutland, thomas.petazzoni, lars, linux-pm, liam,
linux-kernel, linux-sunxi, sre, linux, linux-iio, wens, robh+dt,
icenowy, pmeerw, knaack.h, maxime.ripard, devicetree,
linux-arm-kernel
In-Reply-To: <20170411100528.2zif3fyi7uoyw33n@dell>
On 11/04/17 11:05, Lee Jones wrote:
> Enjoy!
>
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git ib-mfd-iio-v4.12
>
> for you to fetch changes up to f2499ab450d3052097ba53a7d763f767935c0c59:
>
> iio: adc: add support for X-Powers AXP20X and AXP22X PMICs ADCs (2017-04-11 11:02:33 +0100)
>
> ----------------------------------------------------------------
> Immutable branch between MFD and IIO due for the v4.12 merge window
>
> ----------------------------------------------------------------
> Quentin Schulz (1):
> iio: adc: add support for X-Powers AXP20X and AXP22X PMICs ADCs
>
> drivers/iio/adc/Kconfig | 10 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/axp20x_adc.c | 617 +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 628 insertions(+)
> create mode 100644 drivers/iio/adc/axp20x_adc.c
>
Hi Lee,
Thanks for doing this, but the reason it was going to go through your
tree in the first place was a dependency on
commit 4707274714ef ("mfd: axp20x: Correct name of temperature data ADC registers")
Not present in the immutable branch.
There isn't much time for anything else going on around this driver though
so other than a possible merge conflict on the Kconfig and Makefile shouldn't
matter if this just goes through mfd. (famous last words ;)
Jonathan
^ permalink raw reply
* Re: [PATCH] ARM: dts: dra7: Add power hold and power controller properties to palmas
From: Tony Lindgren @ 2017-04-14 14:21 UTC (permalink / raw)
To: Keerthy
Cc: robh+dt, mark.rutland, devicetree, linux-kernel, linux-omap,
t-kristo
In-Reply-To: <1492059081-20124-1-git-send-email-j-keerthy@ti.com>
* Keerthy <j-keerthy@ti.com> [170412 21:55]:
> Add power hold and power controller properties to palmas node.
> This is needed to shutdown pmic correctly on boards with
> powerhold set.
Is this OK to wait for v4.12 or is this needed as a fix for
the -rc series?
Regards,
Tony
> Signed-off-by: Keerthy <j-keerthy@ti.com>
> ---
> arch/arm/boot/dts/dra7-evm.dts | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
> index 4bc4b57..31a9e06 100644
> --- a/arch/arm/boot/dts/dra7-evm.dts
> +++ b/arch/arm/boot/dts/dra7-evm.dts
> @@ -204,6 +204,8 @@
> tps659038: tps659038@58 {
> compatible = "ti,tps659038";
> reg = <0x58>;
> + ti,palmas-override-powerhold;
> + ti,system-power-controller;
>
> tps659038_pmic {
> compatible = "ti,tps659038-pmic";
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH V2] PM / OPP: Use - instead of @ for DT entries
From: Tony Lindgren @ 2017-04-14 14:20 UTC (permalink / raw)
To: Viresh Kumar
Cc: Rafael Wysocki, Chanwoo Choi, MyungJoo Ham, Kyungmin Park,
Kukjin Kim, Krzysztof Kozlowski, Javier Martinez Canillas,
Viresh Kumar, Nishanth Menon, Stephen Boyd, Benoît Cousson,
Rob Herring, Mark Rutland, Daniel Mack, Haojian Zhuang,
Robert Jarzmik, Maxime Ripard, Chen-Yu Tsai, Masahiro Yamada
In-Reply-To: <70e7c7ee13722ab9c73cb073f88502eaf1ada5f5.1491816050.git.viresh.kumar@linaro.org>
* Viresh Kumar <viresh.kumar@linaro.org> [170410 02:24]:
> Compiling the DT file with W=1, DTC warns like follows:
>
> Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
> unit name, but no reg property
>
> Fix this by replacing '@' with '-' as the OPP nodes will never have a
> "reg" property.
>
> Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> Suggested-by: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> (sunxi)
> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Looks good to me too:
Acked-by: Tony Lindgren <tony@atomide.com>
^ permalink raw reply
* Re: [PATCH v3 03/21] ARM: dts: omap: Add generic compatible string for I2C EEPROM
From: Tony Lindgren @ 2017-04-14 14:17 UTC (permalink / raw)
To: Javier Martinez Canillas
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Wolfram Sang,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Benoît Cousson, devicetree-u79uwXL29TY76Z2rM5mHXA,
Rob Herring, Mark Rutland, linux-omap-u79uwXL29TY76Z2rM5mHXA,
Russell King, Mark Jackson
In-Reply-To: <20170414010445.21727-4-javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
* Javier Martinez Canillas <javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org> [170413 18:08]:
> The at24 driver allows to register I2C EEPROM chips using different vendor
> and devices, but the I2C subsystem does not take the vendor into account
> when matching using the I2C table since it only has device entries.
>
> But when matching using an OF table, both the vendor and device has to be
> taken into account so the driver defines only a set of compatible strings
> using the "atmel" vendor as a generic fallback for compatible I2C devices.
>
> So add this generic fallback to the device node compatible string to make
> the device to match the driver using the OF device ID table.
>
> Signed-off-by: Javier Martinez Canillas <javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
Looks good to me assuming this will get merged in a single series:
Acked-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
Or if you want me to pick this patch separately, let me know.
Regards,
Tony
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^ permalink raw reply
* Re: [PATCH 2/3] Documentation: dt: i2c: Add Altera I2C Controller
From: Thor Thayer @ 2017-04-14 13:46 UTC (permalink / raw)
To: Rob Herring
Cc: wsa-z923LK4zBo2bacvFa/9K2g, linux-i2c-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170413212240.uxwh5525baqmgny4@rob-hp-laptop>
Hi Rob,
On 04/13/2017 04:22 PM, Rob Herring wrote:
> On Tue, Apr 11, 2017 at 11:02:26AM -0500, thor.thayer-VuQAYsv1563Yd54FQh9/CA@public.gmane.org wrote:
>> From: Thor Thayer <thor.thayer-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
>>
>> Add the documentation to support the Altera I2C Controller.
>
> "dt-bindings: i2c: ..." for the subject.
>
Got it. Thanks.
>>
>> Signed-off-by: Thor Thayer <thor.thayer-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
>> ---
>> .../devicetree/bindings/i2c/i2c-altera.txt | 37 ++++++++++++++++++++++
>> 1 file changed, 37 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/i2c/i2c-altera.txt
>>
>> diff --git a/Documentation/devicetree/bindings/i2c/i2c-altera.txt b/Documentation/devicetree/bindings/i2c/i2c-altera.txt
>> new file mode 100644
>> index 0000000..a67241c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/i2c/i2c-altera.txt
>> @@ -0,0 +1,37 @@
>> +* Altera I2C Controller
>
> This is the only one? For synthesizable logic or a hard block in
> socfpga?
>
This is synthesizable logic in an FPGA.
>> +
>> +Required properties :
>> + - compatible : should be "altr,sip-i2c"
>
> Seems kind of generic.
>
I'm using sip for soft IP - right now we only offer 1 flavor.
>> + - reg : Offset and length of the register set for the device
>> + - interrupts : <IRQ> where IRQ is the interrupt number.
>> + - clocks : phandles to input clocks.
>
> Need to specify how many clocks.
>
OK. There is only 1 so I'll change to singular. phandle to input clock.
>> + - #address-cells = <1>;
>> + - #size-cells = <0>;
>> +
>> +Recommended properties :
>> + - clock-frequency : desired I2C bus clock frequency in Hz.
>> +
>> +Optional properties :
>> + - altr,fifo-size : Size of the RX and TX FIFOs.
>
> in bytes?
>
> Just "fifo-size" is already fairly common, so drop the vendor prefix.
>
Yes, it is in bytes. I'll make the change.
Thanks for reviewing!
>> + - Child nodes conforming to i2c bus binding
>> +
>> +Example :
>> +
>> + i2c@100080000 {
>> + compatible = "altr,sip-i2c";
>> + reg = <0x00000001 0x00080000 0x00000040>;
>> + interrupt-parent = <&intc>;
>> + interrupts = <0 43 4>;
>> + clocks = <&clk_0>;
>> + clock-frequency = <100000>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + altr,fifo-size = <4>;
>> +
>> + eeprom@51 {
>> + compatible = "atmel,24c32";
>> + reg = <0x51>;
>> + pagesize = <32>;
>> + };
>> + };
>> +
>> --
>> 1.9.1
>>
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^ permalink raw reply
* [PATCH 2/2] arm64: allwinner: a64: enable EHCI0/OHCI0 for Pine64
From: Icenowy Zheng @ 2017-04-14 13:15 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
In-Reply-To: <20170414131555.9431-1-icenowy-h8G6r0blFSE@public.gmane.org>
As we have USB0 controller switch available on A64, we should now enable
the EHCI0/OHCI0 controllers for Pine64.
Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index c680ed385da3..4782add50b94 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -66,6 +66,10 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -91,6 +95,10 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
--
2.12.2
^ permalink raw reply related
* [PATCH 1/2] arm64: allwinner: a64: add EHCI0/OHCI0 nodes to A64 DTSI
From: Icenowy Zheng @ 2017-04-14 13:15 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
Allwinner A64 SoC features a pair of EHCI/OHCI controllers that can be
set to wire to USB0 port (the OTG-capable one), which can be used to
provide a better performance in host mode.
Add their device tree nodes.
Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index c7f669f5884f..65a344d9cea4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -204,6 +204,28 @@
#phy-cells = <1>;
};
+ ehci0: usb@01c1a000 {
+ compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ status = "disabled";
+ };
+
+ ohci0: usb@01c1a400 {
+ compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
ehci1: usb@01c1b000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;
--
2.12.2
^ permalink raw reply related
* Re: [PATCH v7 5/9] MAINTAINERS: add maintainers for DRM STM driver
From: Neil Armstrong @ 2017-04-14 12:59 UTC (permalink / raw)
To: Yannick Fertre, Alexandre TORGUE, Thierry Reding, David Airlie,
Maxime Coquelin, Russell King, Mark Rutland, Rob Herring,
Arnd Bergmann, Benjamin Gaignard
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, kernel-F5mvAk5X5gdBDgjK7y7TUQ,
Philippe Cornu, Fabien Dessenne,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Mickael Reulier,
Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1492164819-10513-6-git-send-email-yannick.fertre-qxv4g6HH51o@public.gmane.org>
On 04/14/2017 12:13 PM, Yannick Fertre wrote:
> Add Philippe Cornu and myself as maintainers.
>
> Signed-off-by: Yannick Fertre <yannick.fertre-qxv4g6HH51o@public.gmane.org>
> ---
> MAINTAINERS | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index c36dfae..84cf73f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -4424,6 +4424,15 @@ S: Maintained
> F: drivers/gpu/drm/sti
> F: Documentation/devicetree/bindings/display/st,stih4xx.txt
>
> +DRM DRIVERS FOR STM
> +M: Yannick Fertre <yannick.fertre-qxv4g6HH51o@public.gmane.org>
> +M: Philippe Cornu <philippe.cornu-qxv4g6HH51o@public.gmane.org>
> +L: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> +T: git git://anongit.freedesktop.org/drm/drm-misc
> +S: Maintained
> +F: drivers/gpu/drm/stm
> +F: Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
> +
> DRM DRIVER FOR TDFX VIDEO CARDS
> S: Orphan / Obsolete
> F: drivers/gpu/drm/tdfx/
>
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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* Re: [PATCH v7 4/9] drm/stm: Add STM32 LTDC driver
From: Neil Armstrong @ 2017-04-14 12:59 UTC (permalink / raw)
To: Yannick Fertre, Alexandre TORGUE, Thierry Reding, David Airlie,
Maxime Coquelin, Russell King, Mark Rutland, Rob Herring,
Arnd Bergmann, Benjamin Gaignard
Cc: devicetree, kernel, Philippe Cornu, dri-devel, Fabien Dessenne,
Mickael Reulier, Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel
In-Reply-To: <1492164819-10513-5-git-send-email-yannick.fertre@st.com>
On 04/14/2017 12:13 PM, Yannick Fertre wrote:
> This controller provides output signals to interface directly a variety
> of LCD and TFT panels. These output signals are: RGB signals
> (up to 24bpp), vertical & horizontal synchronisations, data enable and
> the pixel clock.
>
> Reviewed-by: Eric Anholt <eric@anholt.net>
> Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
> ---
> drivers/gpu/drm/Kconfig | 2 +
> drivers/gpu/drm/Makefile | 1 +
> drivers/gpu/drm/stm/Kconfig | 16 +
> drivers/gpu/drm/stm/Makefile | 7 +
> drivers/gpu/drm/stm/drv.c | 221 ++++++++
> drivers/gpu/drm/stm/ltdc.c | 1161 ++++++++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/stm/ltdc.h | 40 ++
> 7 files changed, 1448 insertions(+)
> create mode 100644 drivers/gpu/drm/stm/Kconfig
> create mode 100644 drivers/gpu/drm/stm/Makefile
> create mode 100644 drivers/gpu/drm/stm/drv.c
> create mode 100644 drivers/gpu/drm/stm/ltdc.c
> create mode 100644 drivers/gpu/drm/stm/ltdc.h
>
> diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
> index 78d7fc0..f57540d 100644
> --- a/drivers/gpu/drm/Kconfig
> +++ b/drivers/gpu/drm/Kconfig
> @@ -246,6 +246,8 @@ source "drivers/gpu/drm/fsl-dcu/Kconfig"
>
> source "drivers/gpu/drm/tegra/Kconfig"
>
> +source "drivers/gpu/drm/stm/Kconfig"
> +
> source "drivers/gpu/drm/panel/Kconfig"
>
> source "drivers/gpu/drm/bridge/Kconfig"
> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> index 59f0f9b..aa62ded 100644
> --- a/drivers/gpu/drm/Makefile
> +++ b/drivers/gpu/drm/Makefile
> @@ -82,6 +82,7 @@ obj-$(CONFIG_DRM_BOCHS) += bochs/
> obj-$(CONFIG_DRM_VIRTIO_GPU) += virtio/
> obj-$(CONFIG_DRM_MSM) += msm/
> obj-$(CONFIG_DRM_TEGRA) += tegra/
> +obj-$(CONFIG_DRM_STM) += stm/
> obj-$(CONFIG_DRM_STI) += sti/
> obj-$(CONFIG_DRM_IMX) += imx/
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek/
> diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig
> new file mode 100644
> index 0000000..2c4817f
> --- /dev/null
> +++ b/drivers/gpu/drm/stm/Kconfig
> @@ -0,0 +1,16 @@
> +config DRM_STM
> + tristate "DRM Support for STMicroelectronics SoC Series"
> + depends on DRM && (ARCH_STM32 || ARCH_MULTIPLATFORM)
> + select DRM_KMS_HELPER
> + select DRM_GEM_CMA_HELPER
> + select DRM_KMS_CMA_HELPER
> + select DRM_PANEL
> + select VIDEOMODE_HELPERS
> + select FB_PROVIDE_GET_FB_UNMAPPED_AREA
> + default y
> +
> + help
> + Enable support for the on-chip display controller on
> + STMicroelectronics STM32 MCUs.
> + To compile this driver as a module, choose M here: the module
> + will be called stm-drm.
> diff --git a/drivers/gpu/drm/stm/Makefile b/drivers/gpu/drm/stm/Makefile
> new file mode 100644
> index 0000000..e114d45
> --- /dev/null
> +++ b/drivers/gpu/drm/stm/Makefile
> @@ -0,0 +1,7 @@
> +ccflags-y := -Iinclude/drm
> +
> +stm-drm-y := \
> + drv.o \
> + ltdc.o
> +
> +obj-$(CONFIG_DRM_STM) += stm-drm.o
> diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c
> new file mode 100644
> index 0000000..83ab48f
> --- /dev/null
> +++ b/drivers/gpu/drm/stm/drv.c
> @@ -0,0 +1,221 @@
> +/*
> + * Copyright (C) STMicroelectronics SA 2017
> + *
> + * Authors: Philippe Cornu <philippe.cornu@st.com>
> + * Yannick Fertre <yannick.fertre@st.com>
> + * Fabien Dessenne <fabien.dessenne@st.com>
> + * Mickael Reulier <mickael.reulier@st.com>
> + *
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#include <linux/component.h>
> +#include <linux/of_platform.h>
> +
> +#include <drm/drm_atomic.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_fb_cma_helper.h>
> +#include <drm/drm_gem_cma_helper.h>
> +
> +#include "ltdc.h"
> +
> +#define DRIVER_NAME "stm"
> +#define DRIVER_DESC "STMicroelectronics SoC DRM"
> +#define DRIVER_DATE "20170330"
> +#define DRIVER_MAJOR 1
> +#define DRIVER_MINOR 0
> +#define DRIVER_PATCH_LEVEL 0
> +
> +#define STM_MAX_FB_WIDTH 2048
> +#define STM_MAX_FB_HEIGHT 2048 /* same as width to handle orientation */
> +
> +static void drv_output_poll_changed(struct drm_device *ddev)
> +{
> + struct ltdc_device *ldev = ddev->dev_private;
> +
> + drm_fbdev_cma_hotplug_event(ldev->fbdev);
> +}
> +
> +static const struct drm_mode_config_funcs drv_mode_config_funcs = {
> + .fb_create = drm_fb_cma_create,
> + .output_poll_changed = drv_output_poll_changed,
> + .atomic_check = drm_atomic_helper_check,
> + .atomic_commit = drm_atomic_helper_commit,
> +};
> +
> +static void drv_lastclose(struct drm_device *ddev)
> +{
> + struct ltdc_device *ldev = ddev->dev_private;
> +
> + DRM_DEBUG("%s\n", __func__);
> +
> + drm_fbdev_cma_restore_mode(ldev->fbdev);
> +}
> +
> +DEFINE_DRM_GEM_CMA_FOPS(drv_driver_fops);
> +
> +static struct drm_driver drv_driver = {
> + .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
> + DRIVER_ATOMIC,
> + .lastclose = drv_lastclose,
> + .name = DRIVER_NAME,
> + .desc = DRIVER_DESC,
> + .date = DRIVER_DATE,
> + .major = DRIVER_MAJOR,
> + .minor = DRIVER_MINOR,
> + .patchlevel = DRIVER_PATCH_LEVEL,
> + .fops = &drv_driver_fops,
> + .dumb_create = drm_gem_cma_dumb_create,
> + .dumb_map_offset = drm_gem_cma_dumb_map_offset,
> + .dumb_destroy = drm_gem_dumb_destroy,
> + .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> + .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> + .gem_free_object_unlocked = drm_gem_cma_free_object,
> + .gem_vm_ops = &drm_gem_cma_vm_ops,
> + .gem_prime_export = drm_gem_prime_export,
> + .gem_prime_import = drm_gem_prime_import,
> + .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
> + .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> + .gem_prime_vmap = drm_gem_cma_prime_vmap,
> + .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
> + .gem_prime_mmap = drm_gem_cma_prime_mmap,
> + .enable_vblank = ltdc_crtc_enable_vblank,
> + .disable_vblank = ltdc_crtc_disable_vblank,
> +};
> +
> +static int drv_load(struct drm_device *ddev)
> +{
> + struct platform_device *pdev = to_platform_device(ddev->dev);
> + struct drm_fbdev_cma *fbdev;
> + struct ltdc_device *ldev;
> + int ret;
> +
> + DRM_DEBUG("%s\n", __func__);
> +
> + ldev = devm_kzalloc(ddev->dev, sizeof(*ldev), GFP_KERNEL);
> + if (!ldev)
> + return -ENOMEM;
> +
> + ddev->dev_private = (void *)ldev;
> +
> + drm_mode_config_init(ddev);
> +
> + /*
> + * set max width and height as default value.
> + * this value would be used to check framebuffer size limitation
> + * at drm_mode_addfb().
> + */
> + ddev->mode_config.min_width = 0;
> + ddev->mode_config.min_height = 0;
> + ddev->mode_config.max_width = STM_MAX_FB_WIDTH;
> + ddev->mode_config.max_height = STM_MAX_FB_HEIGHT;
> + ddev->mode_config.funcs = &drv_mode_config_funcs;
> +
> + ret = ltdc_load(ddev);
> + if (ret)
> + goto err;
> +
> + drm_mode_config_reset(ddev);
> + drm_kms_helper_poll_init(ddev);
> +
> + if (ddev->mode_config.num_connector) {
> + ldev = ddev->dev_private;
> + fbdev = drm_fbdev_cma_init(ddev, 16,
> + ddev->mode_config.num_connector);
> + if (IS_ERR(fbdev)) {
> + DRM_DEBUG("Warning: fails to create fbdev\n");
> + fbdev = NULL;
> + }
> + ldev->fbdev = fbdev;
> + }
> +
> + platform_set_drvdata(pdev, ddev);
> +
> + return 0;
> +err:
> + drm_mode_config_cleanup(ddev);
> + return ret;
> +}
> +
> +static void drv_unload(struct drm_device *ddev)
> +{
> + struct ltdc_device *ldev = ddev->dev_private;
> +
> + DRM_DEBUG("%s\n", __func__);
> +
> + if (ldev->fbdev) {
> + drm_fbdev_cma_fini(ldev->fbdev);
> + ldev->fbdev = NULL;
> + }
> + drm_kms_helper_poll_fini(ddev);
> + ltdc_unload(ddev);
> + drm_mode_config_cleanup(ddev);
> +}
> +
> +static int stm_drm_platform_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct drm_device *ddev;
> + int ret;
> +
> + DRM_DEBUG("%s\n", __func__);
> +
> + dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
> +
> + ddev = drm_dev_alloc(&drv_driver, dev);
> + if (IS_ERR(ddev))
> + return PTR_ERR(ddev);
> +
> + ret = drv_load(ddev);
> + if (ret)
> + goto err_unref;
> +
> + ret = drm_dev_register(ddev, 0);
> + if (ret)
> + goto err_unref;
> +
> + return 0;
> +
> +err_unref:
> + drm_dev_unref(ddev);
> +
> + return ret;
> +}
> +
> +static int stm_drm_platform_remove(struct platform_device *pdev)
> +{
> + struct drm_device *ddev = platform_get_drvdata(pdev);
> +
> + DRM_DEBUG("%s\n", __func__);
> +
> + drm_dev_unregister(ddev);
> + drv_unload(ddev);
> + drm_dev_unref(ddev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id drv_dt_ids[] = {
> + { .compatible = "st,stm32-ltdc"},
> + { /* end node */ },
> +};
> +MODULE_DEVICE_TABLE(of, drv_dt_ids);
> +
> +static struct platform_driver stm_drm_platform_driver = {
> + .probe = stm_drm_platform_probe,
> + .remove = stm_drm_platform_remove,
> + .driver = {
> + .name = DRIVER_NAME,
> + .of_match_table = drv_dt_ids,
> + },
> +};
> +
> +module_platform_driver(stm_drm_platform_driver);
> +
> +MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
> +MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
> +MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
> +MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
> +MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> new file mode 100644
> index 0000000..a373178
> --- /dev/null
> +++ b/drivers/gpu/drm/stm/ltdc.c
> @@ -0,0 +1,1161 @@
> +/*
> + * Copyright (C) STMicroelectronics SA 2017
> + *
> + * Authors: Philippe Cornu <philippe.cornu@st.com>
> + * Yannick Fertre <yannick.fertre@st.com>
> + * Fabien Dessenne <fabien.dessenne@st.com>
> + * Mickael Reulier <mickael.reulier@st.com>
> + *
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_address.h>
> +#include <linux/of_graph.h>
> +#include <linux/reset.h>
> +
> +#include <drm/drm_atomic.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_fb_cma_helper.h>
> +#include <drm/drm_gem_cma_helper.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_plane_helper.h>
> +
> +#include <video/videomode.h>
> +
> +#include "ltdc.h"
> +
> +#define NB_CRTC 1
> +#define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
> +
> +#define MAX_IRQ 4
> +
> +#define HWVER_10200 0x010200
> +#define HWVER_10300 0x010300
> +#define HWVER_20101 0x020101
> +
> +/*
> + * The address of some registers depends on the HW version: such registers have
> + * an extra offset specified with reg_ofs.
> + */
> +#define REG_OFS_NONE 0
> +#define REG_OFS_4 4 /* Insertion of "Layer Configuration 2" reg */
> +#define REG_OFS (ldev->caps.reg_ofs)
> +#define LAY_OFS 0x80 /* Register Offset between 2 layers */
> +
> +/* Global register offsets */
> +#define LTDC_IDR 0x0000 /* IDentification */
> +#define LTDC_LCR 0x0004 /* Layer Count */
> +#define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */
> +#define LTDC_BPCR 0x000C /* Back Porch Configuration */
> +#define LTDC_AWCR 0x0010 /* Active Width Configuration */
> +#define LTDC_TWCR 0x0014 /* Total Width Configuration */
> +#define LTDC_GCR 0x0018 /* Global Control */
> +#define LTDC_GC1R 0x001C /* Global Configuration 1 */
> +#define LTDC_GC2R 0x0020 /* Global Configuration 2 */
> +#define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */
> +#define LTDC_GACR 0x0028 /* GAmma Correction */
> +#define LTDC_BCCR 0x002C /* Background Color Configuration */
> +#define LTDC_IER 0x0034 /* Interrupt Enable */
> +#define LTDC_ISR 0x0038 /* Interrupt Status */
> +#define LTDC_ICR 0x003C /* Interrupt Clear */
> +#define LTDC_LIPCR 0x0040 /* Line Interrupt Position Configuration */
> +#define LTDC_CPSR 0x0044 /* Current Position Status */
> +#define LTDC_CDSR 0x0048 /* Current Display Status */
> +
> +/* Layer register offsets */
> +#define LTDC_L1LC1R (0x0080) /* L1 Layer Configuration 1 */
> +#define LTDC_L1LC2R (0x0084) /* L1 Layer Configuration 2 */
> +#define LTDC_L1CR (0x0084 + REG_OFS) /* L1 Control */
> +#define LTDC_L1WHPCR (0x0088 + REG_OFS) /* L1 Window Hor Position Config */
> +#define LTDC_L1WVPCR (0x008C + REG_OFS) /* L1 Window Vert Position Config */
> +#define LTDC_L1CKCR (0x0090 + REG_OFS) /* L1 Color Keying Configuration */
> +#define LTDC_L1PFCR (0x0094 + REG_OFS) /* L1 Pixel Format Configuration */
> +#define LTDC_L1CACR (0x0098 + REG_OFS) /* L1 Constant Alpha Config */
> +#define LTDC_L1DCCR (0x009C + REG_OFS) /* L1 Default Color Configuration */
> +#define LTDC_L1BFCR (0x00A0 + REG_OFS) /* L1 Blend Factors Configuration */
> +#define LTDC_L1FBBCR (0x00A4 + REG_OFS) /* L1 FrameBuffer Bus Control */
> +#define LTDC_L1AFBCR (0x00A8 + REG_OFS) /* L1 AuxFB Control */
> +#define LTDC_L1CFBAR (0x00AC + REG_OFS) /* L1 Color FrameBuffer Address */
> +#define LTDC_L1CFBLR (0x00B0 + REG_OFS) /* L1 Color FrameBuffer Length */
> +#define LTDC_L1CFBLNR (0x00B4 + REG_OFS) /* L1 Color FrameBuffer Line Nb */
> +#define LTDC_L1AFBAR (0x00B8 + REG_OFS) /* L1 AuxFB Address */
> +#define LTDC_L1AFBLR (0x00BC + REG_OFS) /* L1 AuxFB Length */
> +#define LTDC_L1AFBLNR (0x00C0 + REG_OFS) /* L1 AuxFB Line Number */
> +#define LTDC_L1CLUTWR (0x00C4 + REG_OFS) /* L1 CLUT Write */
> +#define LTDC_L1YS1R (0x00E0 + REG_OFS) /* L1 YCbCr Scale 1 */
> +#define LTDC_L1YS2R (0x00E4 + REG_OFS) /* L1 YCbCr Scale 2 */
> +
> +/* Bit definitions */
> +#define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
> +#define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
> +
> +#define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
> +#define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
> +
> +#define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
> +#define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
> +
> +#define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
> +#define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
> +
> +#define GCR_LTDCEN BIT(0) /* LTDC ENable */
> +#define GCR_DEN BIT(16) /* Dither ENable */
> +#define GCR_PCPOL BIT(28) /* Pixel Clock POLarity */
> +#define GCR_DEPOL BIT(29) /* Data Enable POLarity */
> +#define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity */
> +#define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity */
> +
> +#define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
> +#define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
> +#define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
> +#define GC1R_PBEN BIT(12) /* Precise Blending ENable */
> +#define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
> +#define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
> +#define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
> +#define GC1R_BCP BIT(22) /* Background Colour Programmable */
> +#define GC1R_BBEN BIT(23) /* Background Blending ENabled */
> +#define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
> +#define GC1R_TP BIT(25) /* Timing Programmable */
> +#define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
> +#define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
> +#define GC1R_DWP BIT(28) /* Dither Width Programmable */
> +#define GC1R_STREN BIT(29) /* STatus Registers ENabled */
> +#define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
> +
> +#define GC2R_EDCA BIT(0) /* External Display Control Ability */
> +#define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
> +#define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
> +#define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
> +#define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
> +#define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
> +
> +#define SRCR_IMR BIT(0) /* IMmediate Reload */
> +#define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
> +
> +#define BCCR_BCBLACK 0x00 /* Background Color BLACK */
> +#define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */
> +#define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */
> +#define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */
> +#define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */
> +
> +#define IER_LIE BIT(0) /* Line Interrupt Enable */
> +#define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */
> +#define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */
> +#define IER_RRIE BIT(3) /* Register Reload Interrupt enable */
> +
> +#define ISR_LIF BIT(0) /* Line Interrupt Flag */
> +#define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */
> +#define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */
> +#define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */
> +
> +#define LXCR_LEN BIT(0) /* Layer ENable */
> +#define LXCR_COLKEN BIT(1) /* Color Keying Enable */
> +#define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
> +
> +#define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
> +#define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
> +
> +#define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
> +#define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
> +
> +#define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
> +
> +#define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
> +
> +#define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
> +#define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
> +
> +#define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
> +#define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
> +
> +#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
> +
> +#define HSPOL_AL 0 /* Horizontal Sync POLarity Active Low */
> +#define VSPOL_AL 0 /* Vertical Sync POLarity Active Low */
> +#define DEPOL_AL 0 /* Data Enable POLarity Active Low */
> +#define PCPOL_IPC 0 /* Input Pixel Clock */
> +#define HSPOL_AH GCR_HSPOL /* Horizontal Sync POLarity Active High */
> +#define VSPOL_AH GCR_VSPOL /* Vertical Sync POLarity Active High */
> +#define DEPOL_AH GCR_DEPOL /* Data Enable POLarity Active High */
> +#define PCPOL_IIPC GCR_PCPOL /* Inverted Input Pixel Clock */
> +#define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */
> +#define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
> +#define BF1_CA 0x400 /* Constant Alpha */
> +#define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
> +#define BF2_1CA 0x005 /* 1 - Constant Alpha */
> +
> +#define NB_PF 8 /* Max nb of HW pixel format */
> +
> +enum ltdc_pix_fmt {
> + PF_NONE,
> + /* RGB formats */
> + PF_ARGB8888, /* ARGB [32 bits] */
> + PF_RGBA8888, /* RGBA [32 bits] */
> + PF_RGB888, /* RGB [24 bits] */
> + PF_RGB565, /* RGB [16 bits] */
> + PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */
> + PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
> + /* Indexed formats */
> + PF_L8, /* Indexed 8 bits [8 bits] */
> + PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */
> + PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */
> +};
> +
> +/* The index gives the encoding of the pixel format for an HW version */
> +static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = {
> + PF_ARGB8888, /* 0x00 */
> + PF_RGB888, /* 0x01 */
> + PF_RGB565, /* 0x02 */
> + PF_ARGB1555, /* 0x03 */
> + PF_ARGB4444, /* 0x04 */
> + PF_L8, /* 0x05 */
> + PF_AL44, /* 0x06 */
> + PF_AL88 /* 0x07 */
> +};
> +
> +static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
> + PF_ARGB8888, /* 0x00 */
> + PF_RGB888, /* 0x01 */
> + PF_RGB565, /* 0x02 */
> + PF_RGBA8888, /* 0x03 */
> + PF_AL44, /* 0x04 */
> + PF_L8, /* 0x05 */
> + PF_ARGB1555, /* 0x06 */
> + PF_ARGB4444 /* 0x07 */
> +};
> +
> +static inline u32 reg_read(void __iomem *base, u32 reg)
> +{
> + return readl_relaxed(base + reg);
> +}
> +
> +static inline void reg_write(void __iomem *base, u32 reg, u32 val)
> +{
> + writel_relaxed(val, base + reg);
> +}
> +
> +static inline void reg_set(void __iomem *base, u32 reg, u32 mask)
> +{
> + reg_write(base, reg, reg_read(base, reg) | mask);
> +}
> +
> +static inline void reg_clear(void __iomem *base, u32 reg, u32 mask)
> +{
> + reg_write(base, reg, reg_read(base, reg) & ~mask);
> +}
> +
> +static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask,
> + u32 val)
> +{
> + reg_write(base, reg, (reg_read(base, reg) & ~mask) | val);
> +}
> +
> +static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc)
> +{
> + return (struct ltdc_device *)crtc->dev->dev_private;
> +}
> +
> +static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane)
> +{
> + return (struct ltdc_device *)plane->dev->dev_private;
> +}
> +
> +static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc)
> +{
> + return (struct ltdc_device *)enc->dev->dev_private;
> +}
> +
> +static inline struct ltdc_device *connector_to_ltdc(struct drm_connector *con)
> +{
> + return (struct ltdc_device *)con->dev->dev_private;
> +}
> +
> +static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
> +{
> + enum ltdc_pix_fmt pf;
> +
> + switch (drm_fmt) {
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_XRGB8888:
> + pf = PF_ARGB8888;
> + break;
> + case DRM_FORMAT_RGBA8888:
> + case DRM_FORMAT_RGBX8888:
> + pf = PF_RGBA8888;
> + break;
> + case DRM_FORMAT_RGB888:
> + pf = PF_RGB888;
> + break;
> + case DRM_FORMAT_RGB565:
> + pf = PF_RGB565;
> + break;
> + case DRM_FORMAT_ARGB1555:
> + case DRM_FORMAT_XRGB1555:
> + pf = PF_ARGB1555;
> + break;
> + case DRM_FORMAT_ARGB4444:
> + case DRM_FORMAT_XRGB4444:
> + pf = PF_ARGB4444;
> + break;
> + case DRM_FORMAT_C8:
> + pf = PF_L8;
> + break;
> + default:
> + pf = PF_NONE;
> + break;
> + /* Note: There are no DRM_FORMAT for AL44 and AL88 */
> + }
> +
> + return pf;
> +}
> +
> +static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf)
> +{
> + switch (pf) {
> + case PF_ARGB8888:
> + return DRM_FORMAT_ARGB8888;
> + case PF_RGBA8888:
> + return DRM_FORMAT_RGBA8888;
> + case PF_RGB888:
> + return DRM_FORMAT_RGB888;
> + case PF_RGB565:
> + return DRM_FORMAT_RGB565;
> + case PF_ARGB1555:
> + return DRM_FORMAT_ARGB1555;
> + case PF_ARGB4444:
> + return DRM_FORMAT_ARGB4444;
> + case PF_L8:
> + return DRM_FORMAT_C8;
> + case PF_AL44: /* No DRM support */
> + case PF_AL88: /* No DRM support */
> + case PF_NONE:
> + default:
> + return 0;
> + }
> +}
> +
> +static irqreturn_t ltdc_irq_thread(int irq, void *arg)
> +{
> + struct drm_device *ddev = arg;
> + struct ltdc_device *ldev = ddev->dev_private;
> + struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0);
> +
> + /* Line IRQ : trigger the vblank event */
> + if (ldev->irq_status & ISR_LIF)
> + drm_crtc_handle_vblank(crtc);
> +
> + /* Save FIFO Underrun & Transfer Error status */
> + mutex_lock(&ldev->err_lock);
> + if (ldev->irq_status & ISR_FUIF)
> + ldev->error_status |= ISR_FUIF;
> + if (ldev->irq_status & ISR_TERRIF)
> + ldev->error_status |= ISR_TERRIF;
> + mutex_unlock(&ldev->err_lock);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t ltdc_irq(int irq, void *arg)
> +{
> + struct drm_device *ddev = arg;
> + struct ltdc_device *ldev = ddev->dev_private;
> +
> + /* Read & Clear the interrupt status */
> + ldev->irq_status = reg_read(ldev->regs, LTDC_ISR);
> + reg_write(ldev->regs, LTDC_ICR, ldev->irq_status);
> +
> + return IRQ_WAKE_THREAD;
> +}
> +
> +/*
> + * DRM_CRTC
> + */
> +
> +static void ltdc_crtc_load_lut(struct drm_crtc *crtc)
> +{
> + struct ltdc_device *ldev = crtc_to_ltdc(crtc);
> + unsigned int i, lay;
> +
> + for (lay = 0; lay < ldev->caps.nb_layers; lay++)
> + for (i = 0; i < 256; i++)
> + reg_write(ldev->regs, LTDC_L1CLUTWR + lay * LAY_OFS,
> + ldev->clut[i]);
> +}
> +
> +static void ltdc_crtc_enable(struct drm_crtc *crtc)
> +{
> + struct ltdc_device *ldev = crtc_to_ltdc(crtc);
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + /* Sets the background color value */
> + reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK);
> +
> + /* Enable IRQ */
> + reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
> +
> + /* Immediately commit the planes */
> + reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
> +
> + /* Enable LTDC */
> + reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN);
> +
> + drm_crtc_vblank_on(crtc);
> +}
> +
> +static void ltdc_crtc_disable(struct drm_crtc *crtc)
> +{
> + struct ltdc_device *ldev = crtc_to_ltdc(crtc);
> + struct drm_pending_vblank_event *event = crtc->state->event;
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + drm_crtc_vblank_off(crtc);
> +
> + /* disable LTDC */
> + reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN);
> +
> + /* disable IRQ */
> + reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
> +
> + /* immediately commit disable of layers before switching off LTDC */
> + reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
> +}
> +
> +static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
> +{
> + struct ltdc_device *ldev = crtc_to_ltdc(crtc);
> + struct drm_display_mode *mode = &crtc->state->adjusted_mode;
> + struct videomode vm;
> + int rate = mode->clock * 1000;
> + u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
> + u32 total_width, total_height;
> + u32 val;
> +
> + drm_display_mode_to_videomode(mode, &vm);
> +
> + DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name);
> + DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive);
> + DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
> + vm.hfront_porch, vm.hback_porch, vm.hsync_len,
> + vm.vfront_porch, vm.vback_porch, vm.vsync_len);
> +
> + /* Convert video timings to ltdc timings */
> + hsync = vm.hsync_len - 1;
> + vsync = vm.vsync_len - 1;
> + accum_hbp = hsync + vm.hback_porch;
> + accum_vbp = vsync + vm.vback_porch;
> + accum_act_w = accum_hbp + vm.hactive;
> + accum_act_h = accum_vbp + vm.vactive;
> + total_width = accum_act_w + vm.hfront_porch;
> + total_height = accum_act_h + vm.vfront_porch;
> +
> + clk_disable(ldev->pixel_clk);
> +
> + if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
> + DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
> + return;
> + }
> +
> + clk_enable(ldev->pixel_clk);
> +
> + /* Configures the HS, VS, DE and PC polarities. */
> + val = HSPOL_AL | HSPOL_AL | DEPOL_AL | PCPOL_IPC;
> +
> + if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
> + val |= HSPOL_AH;
> +
> + if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
> + val |= VSPOL_AH;
> +
> + if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
> + val |= DEPOL_AH;
> +
> + if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
> + val |= PCPOL_IIPC;
> +
> + reg_update_bits(ldev->regs, LTDC_GCR,
> + GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
> +
> + /* Set Synchronization size */
> + val = (hsync << 16) | vsync;
> + reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
> +
> + /* Set Accumulated Back porch */
> + val = (accum_hbp << 16) | accum_vbp;
> + reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
> +
> + /* Set Accumulated Active Width */
> + val = (accum_act_w << 16) | accum_act_h;
> + reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
> +
> + /* Set total width & height */
> + val = (total_width << 16) | total_height;
> + reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
> +
> + reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1));
> +}
> +
> +static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
> + struct drm_crtc_state *old_crtc_state)
> +{
> + struct ltdc_device *ldev = crtc_to_ltdc(crtc);
> + struct drm_pending_vblank_event *event = crtc->state->event;
> +
> + DRM_DEBUG_ATOMIC("\n");
> +
> + /* Commit shadow registers = update planes at next vblank */
> + reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
> +
> + if (event) {
> + crtc->state->event = NULL;
> +
> + spin_lock_irq(&crtc->dev->event_lock);
> + if (drm_crtc_vblank_get(crtc) == 0)
> + drm_crtc_arm_vblank_event(crtc, event);
> + else
> + drm_crtc_send_vblank_event(crtc, event);
> + spin_unlock_irq(&crtc->dev->event_lock);
> + }
> +}
> +
> +static struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
> + .load_lut = ltdc_crtc_load_lut,
> + .enable = ltdc_crtc_enable,
> + .disable = ltdc_crtc_disable,
> + .mode_set_nofb = ltdc_crtc_mode_set_nofb,
> + .atomic_flush = ltdc_crtc_atomic_flush,
> +};
> +
> +int ltdc_crtc_enable_vblank(struct drm_device *ddev, unsigned int pipe)
> +{
> + struct ltdc_device *ldev = ddev->dev_private;
> +
> + DRM_DEBUG_DRIVER("\n");
> + reg_set(ldev->regs, LTDC_IER, IER_LIE);
> +
> + return 0;
> +}
> +
> +void ltdc_crtc_disable_vblank(struct drm_device *ddev, unsigned int pipe)
> +{
> + struct ltdc_device *ldev = ddev->dev_private;
> +
> + DRM_DEBUG_DRIVER("\n");
> + reg_clear(ldev->regs, LTDC_IER, IER_LIE);
> +}
> +
> +static struct drm_crtc_funcs ltdc_crtc_funcs = {
> + .destroy = drm_crtc_cleanup,
> + .set_config = drm_atomic_helper_set_config,
> + .page_flip = drm_atomic_helper_page_flip,
> + .reset = drm_atomic_helper_crtc_reset,
> + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
> +};
> +
> +/*
> + * DRM_PLANE
> + */
> +
> +static int ltdc_plane_atomic_check(struct drm_plane *plane,
> + struct drm_plane_state *state)
> +{
> + struct drm_framebuffer *fb = state->fb;
> + u32 src_x, src_y, src_w, src_h;
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + if (!fb)
> + return 0;
> +
> + /* convert src_ from 16:16 format */
> + src_x = state->src_x >> 16;
> + src_y = state->src_y >> 16;
> + src_w = state->src_w >> 16;
> + src_h = state->src_h >> 16;
> +
> + /* Reject scaling */
> + if ((src_w != state->crtc_w) || (src_h != state->crtc_h)) {
> + DRM_ERROR("Scaling is not supported");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static void ltdc_plane_atomic_update(struct drm_plane *plane,
> + struct drm_plane_state *oldstate)
> +{
> + struct ltdc_device *ldev = plane_to_ltdc(plane);
> + struct drm_plane_state *state = plane->state;
> + struct drm_framebuffer *fb = state->fb;
> + u32 lofs = plane->index * LAY_OFS;
> + u32 x0 = state->crtc_x;
> + u32 x1 = state->crtc_x + state->crtc_w - 1;
> + u32 y0 = state->crtc_y;
> + u32 y1 = state->crtc_y + state->crtc_h - 1;
> + u32 src_x, src_y, src_w, src_h;
> + u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr;
> + enum ltdc_pix_fmt pf;
> +
> + if (!state->crtc || !fb) {
> + DRM_DEBUG_DRIVER("fb or crtc NULL");
> + return;
> + }
> +
> + /* convert src_ from 16:16 format */
> + src_x = state->src_x >> 16;
> + src_y = state->src_y >> 16;
> + src_w = state->src_w >> 16;
> + src_h = state->src_h >> 16;
> +
> + DRM_DEBUG_DRIVER(
> + "plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
> + plane->base.id, fb->base.id,
> + src_w, src_h, src_x, src_y,
> + state->crtc_w, state->crtc_h, state->crtc_x, state->crtc_y);
> +
> + bpcr = reg_read(ldev->regs, LTDC_BPCR);
> + ahbp = (bpcr & BPCR_AHBP) >> 16;
> + avbp = bpcr & BPCR_AVBP;
> +
> + /* Configures the horizontal start and stop position */
> + val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp);
> + reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs,
> + LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
> +
> + /* Configures the vertical start and stop position */
> + val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp);
> + reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs,
> + LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
> +
> + /* Specifies the pixel format */
> + pf = to_ltdc_pixelformat(fb->format->format);
> + for (val = 0; val < NB_PF; val++)
> + if (ldev->caps.pix_fmt_hw[val] == pf)
> + break;
> +
> + if (val == NB_PF) {
> + DRM_ERROR("Pixel format %.4s not supported\n",
> + (char *)&fb->format->format);
> + val = 0; /* set by default ARGB 32 bits */
> + }
> + reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
> +
> + /* Configures the color frame buffer pitch in bytes & line length */
> + pitch_in_bytes = fb->pitches[0];
> + line_length = drm_format_plane_cpp(fb->format->format, 0) *
> + (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
> + val = ((pitch_in_bytes << 16) | line_length);
> + reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs,
> + LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
> +
> + /* Specifies the constant alpha value */
> + val = CONSTA_MAX;
> + reg_update_bits(ldev->regs, LTDC_L1CACR + lofs,
> + LXCACR_CONSTA, val);
> +
> + /* Specifies the blending factors */
> + val = BF1_PAXCA | BF2_1PAXCA;
> + reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs,
> + LXBFCR_BF2 | LXBFCR_BF1, val);
> +
> + /* Configures the frame buffer line number */
> + val = y1 - y0 + 1;
> + reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs,
> + LXCFBLNR_CFBLN, val);
> +
> + /* Sets the FB address */
> + paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0);
> +
> + DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr);
> + reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr);
> +
> + /* Enable layer and CLUT if needed */
> + val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0;
> + val |= LXCR_LEN;
> + reg_update_bits(ldev->regs, LTDC_L1CR + lofs,
> + LXCR_LEN | LXCR_CLUTEN, val);
> +
> + mutex_lock(&ldev->err_lock);
> + if (ldev->error_status & ISR_FUIF) {
> + DRM_DEBUG_DRIVER("Fifo underrun\n");
> + ldev->error_status &= ~ISR_FUIF;
> + }
> + if (ldev->error_status & ISR_TERRIF) {
> + DRM_DEBUG_DRIVER("Transfer error\n");
> + ldev->error_status &= ~ISR_TERRIF;
> + }
> + mutex_unlock(&ldev->err_lock);
> +}
> +
> +static void ltdc_plane_atomic_disable(struct drm_plane *plane,
> + struct drm_plane_state *oldstate)
> +{
> + struct ltdc_device *ldev = plane_to_ltdc(plane);
> + u32 lofs = plane->index * LAY_OFS;
> +
> + /* disable layer */
> + reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN);
> +
> + DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
> + oldstate->crtc->base.id, plane->base.id);
> +}
> +
> +static struct drm_plane_funcs ltdc_plane_funcs = {
> + .update_plane = drm_atomic_helper_update_plane,
> + .disable_plane = drm_atomic_helper_disable_plane,
> + .destroy = drm_plane_cleanup,
> + .set_property = drm_atomic_helper_plane_set_property,
> + .reset = drm_atomic_helper_plane_reset,
> + .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
> +};
> +
> +static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
> + .atomic_check = ltdc_plane_atomic_check,
> + .atomic_update = ltdc_plane_atomic_update,
> + .atomic_disable = ltdc_plane_atomic_disable,
> +};
> +
> +static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
> + enum drm_plane_type type)
> +{
> + unsigned long possible_crtcs = CRTC_MASK;
> + struct ltdc_device *ldev = ddev->dev_private;
> + struct device *dev = ddev->dev;
> + struct drm_plane *plane;
> + unsigned int i, nb_fmt = 0;
> + u32 formats[NB_PF];
> + u32 drm_fmt;
> + int ret;
> +
> + /* Get supported pixel formats */
> + for (i = 0; i < NB_PF; i++) {
> + drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]);
> + if (!drm_fmt)
> + continue;
> + formats[nb_fmt++] = drm_fmt;
> + }
> +
> + plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
> + if (!plane)
> + return 0;
> +
> + ret = drm_universal_plane_init(ddev, plane, possible_crtcs,
> + <dc_plane_funcs, formats, nb_fmt,
> + type, NULL);
> + if (ret < 0)
> + return 0;
> +
> + drm_plane_helper_add(plane, <dc_plane_helper_funcs);
> +
> + DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
> +
> + return plane;
> +}
> +
> +static void ltdc_plane_destroy_all(struct drm_device *ddev)
> +{
> + struct drm_plane *plane, *plane_temp;
> +
> + list_for_each_entry_safe(plane, plane_temp,
> + &ddev->mode_config.plane_list, head)
> + drm_plane_cleanup(plane);
> +}
> +
> +static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
> +{
> + struct ltdc_device *ldev = ddev->dev_private;
> + struct drm_plane *primary, *overlay;
> + unsigned int i;
> + int res;
> +
> + primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY);
> + if (!primary) {
> + DRM_ERROR("Can not create primary plane\n");
> + return -EINVAL;
> + }
> +
> + res = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
> + <dc_crtc_funcs, NULL);
> + if (res) {
> + DRM_ERROR("Can not initialize CRTC\n");
> + goto cleanup;
> + }
> +
> + drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs);
> +
> + DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
> +
> + /* Add planes. Note : the first layer is used by primary plane */
> + for (i = 1; i < ldev->caps.nb_layers; i++) {
> + overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY);
> + if (!overlay) {
> + res = -ENOMEM;
> + DRM_ERROR("Can not create overlay plane %d\n", i);
> + goto cleanup;
> + }
> + }
> +
> + return 0;
> +
> +cleanup:
> + ltdc_plane_destroy_all(ddev);
> + return res;
> +}
> +
> +/*
> + * DRM_ENCODER
> + */
> +
> +static void ltdc_rgb_encoder_enable(struct drm_encoder *encoder)
> +{
> + struct ltdc_device *ldev = encoder_to_ltdc(encoder);
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + drm_panel_prepare(ldev->panel);
> + drm_panel_enable(ldev->panel);
> +}
> +
> +static void ltdc_rgb_encoder_disable(struct drm_encoder *encoder)
> +{
> + struct ltdc_device *ldev = encoder_to_ltdc(encoder);
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + drm_panel_disable(ldev->panel);
> + drm_panel_unprepare(ldev->panel);
> +}
> +
> +static const struct drm_encoder_helper_funcs ltdc_rgb_encoder_helper_funcs = {
> + .enable = ltdc_rgb_encoder_enable,
> + .disable = ltdc_rgb_encoder_disable,
> +};
> +
> +static const struct drm_encoder_funcs ltdc_rgb_encoder_funcs = {
> + .destroy = drm_encoder_cleanup,
> +};
> +
> +static struct drm_encoder *ltdc_rgb_encoder_create(struct drm_device *ddev)
> +{
> + struct drm_encoder *encoder;
> +
> + encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
> + if (!encoder)
> + return NULL;
> +
> + encoder->possible_crtcs = CRTC_MASK;
> + encoder->possible_clones = 0; /* No cloning support */
> +
> + drm_encoder_init(ddev, encoder, <dc_rgb_encoder_funcs,
> + DRM_MODE_ENCODER_DPI, NULL);
> +
> + drm_encoder_helper_add(encoder, <dc_rgb_encoder_helper_funcs);
> +
> + DRM_DEBUG_DRIVER("RGB encoder:%d created\n", encoder->base.id);
> +
> + return encoder;
> +}
> +
> +/*
> + * DRM_CONNECTOR
> + */
> +
> +static int ltdc_rgb_connector_get_modes(struct drm_connector *connector)
> +{
> + struct drm_device *ddev = connector->dev;
> + struct ltdc_device *ldev = ddev->dev_private;
> + int ret = 0;
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + if (ldev->panel)
> + ret = drm_panel_get_modes(ldev->panel);
> +
> + return ret < 0 ? 0 : ret;
> +}
> +
> +static struct drm_connector_helper_funcs ltdc_rgb_connector_helper_funcs = {
> + .get_modes = ltdc_rgb_connector_get_modes,
> +};
> +
> +static enum drm_connector_status
> +ltdc_rgb_connector_detect(struct drm_connector *connector, bool force)
> +{
> + struct ltdc_device *ldev = connector_to_ltdc(connector);
> +
> + return ldev->panel ? connector_status_connected :
> + connector_status_disconnected;
> +}
> +
> +static void ltdc_rgb_connector_destroy(struct drm_connector *connector)
> +{
> + DRM_DEBUG_DRIVER("\n");
> +
> + drm_connector_unregister(connector);
> + drm_connector_cleanup(connector);
> +}
> +
> +static const struct drm_connector_funcs ltdc_rgb_connector_funcs = {
> + .dpms = drm_atomic_helper_connector_dpms,
> + .fill_modes = drm_helper_probe_single_connector_modes,
> + .detect = ltdc_rgb_connector_detect,
> + .destroy = ltdc_rgb_connector_destroy,
> + .reset = drm_atomic_helper_connector_reset,
> + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> +};
> +
> +struct drm_connector *ltdc_rgb_connector_create(struct drm_device *ddev)
> +{
> + struct drm_connector *connector;
> + int err;
> +
> + connector = devm_kzalloc(ddev->dev, sizeof(*connector), GFP_KERNEL);
> + if (!connector) {
> + DRM_ERROR("Failed to allocate connector\n");
> + return NULL;
> + }
> +
> + connector->polled = DRM_CONNECTOR_POLL_HPD;
> +
> + err = drm_connector_init(ddev, connector, <dc_rgb_connector_funcs,
> + DRM_MODE_CONNECTOR_DPI);
> + if (err) {
> + DRM_ERROR("Failed to initialize connector\n");
> + return NULL;
> + }
> +
> + drm_connector_helper_add(connector, <dc_rgb_connector_helper_funcs);
> +
> + DRM_DEBUG_DRIVER("RGB connector:%d created\n", connector->base.id);
> +
> + return connector;
> +}
> +
> +static int ltdc_get_caps(struct drm_device *ddev)
> +{
> + struct ltdc_device *ldev = ddev->dev_private;
> + u32 bus_width_log2, lcr, gc2r;
> +
> + /* at least 1 layer must be managed */
> + lcr = reg_read(ldev->regs, LTDC_LCR);
> +
> + ldev->caps.nb_layers = max_t(int, lcr, 1);
> +
> + /* set data bus width */
> + gc2r = reg_read(ldev->regs, LTDC_GC2R);
> + bus_width_log2 = (gc2r & GC2R_BW) >> 4;
> + ldev->caps.bus_width = 8 << bus_width_log2;
> + ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR);
> +
> + switch (ldev->caps.hw_version) {
> + case HWVER_10200:
> + case HWVER_10300:
> + ldev->caps.reg_ofs = REG_OFS_NONE;
> + ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
> + break;
> + case HWVER_20101:
> + ldev->caps.reg_ofs = REG_OFS_4;
> + ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
> + break;
> + default:
> + return -ENODEV;
> + }
> +
> + return 0;
> +}
> +
> +static struct drm_panel *ltdc_get_panel(struct drm_device *ddev)
> +{
> + struct device *dev = ddev->dev;
> + struct device_node *np = dev->of_node;
> + struct device_node *entity, *port = NULL;
> + struct drm_panel *panel = NULL;
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + /*
> + * Parse ltdc node to get remote port and find RGB panel / HDMI slave
> + * If a dsi or a bridge (hdmi, lvds...) is connected to ltdc,
> + * a remote port & RGB panel will not be found.
> + */
> + for_each_endpoint_of_node(np, entity) {
> + if (!of_device_is_available(entity))
> + continue;
> +
> + port = of_graph_get_remote_port_parent(entity);
> + if (port) {
> + panel = of_drm_find_panel(port);
> + of_node_put(port);
> + if (panel) {
> + DRM_DEBUG_DRIVER("remote panel %s\n",
> + port->full_name);
> + } else {
> + DRM_DEBUG_DRIVER("panel missing\n");
> + of_node_put(entity);
> + }
> + }
> + }
> +
> + return panel;
> +}
> +
> +int ltdc_load(struct drm_device *ddev)
> +{
> + struct platform_device *pdev = to_platform_device(ddev->dev);
> + struct ltdc_device *ldev = ddev->dev_private;
> + struct device *dev = ddev->dev;
> + struct device_node *np = dev->of_node;
> + struct drm_encoder *encoder;
> + struct drm_connector *connector = NULL;
> + struct drm_crtc *crtc;
> + struct reset_control *rstc;
> + struct resource res;
> + int irq, ret, i;
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + ldev->panel = ltdc_get_panel(ddev);
> + if (!ldev->panel)
> + return -EPROBE_DEFER;
> +
> + rstc = of_reset_control_get(np, NULL);
> +
> + mutex_init(&ldev->err_lock);
> +
> + ldev->pixel_clk = devm_clk_get(dev, "lcd");
> + if (IS_ERR(ldev->pixel_clk)) {
> + DRM_ERROR("Unable to get lcd clock\n");
> + return -ENODEV;
> + }
> +
> + if (clk_prepare_enable(ldev->pixel_clk)) {
> + DRM_ERROR("Unable to prepare pixel clock\n");
> + return -ENODEV;
> + }
> +
> + if (of_address_to_resource(np, 0, &res)) {
> + DRM_ERROR("Unable to get resource\n");
> + return -ENODEV;
> + }
> +
> + ldev->regs = devm_ioremap_resource(dev, &res);
> + if (IS_ERR(ldev->regs)) {
> + DRM_ERROR("Unable to get ltdc registers\n");
> + return PTR_ERR(ldev->regs);
> + }
> +
> + for (i = 0; i < MAX_IRQ; i++) {
> + irq = platform_get_irq(pdev, i);
> + if (irq < 0)
> + continue;
> +
> + ret = devm_request_threaded_irq(dev, irq, ltdc_irq,
> + ltdc_irq_thread, IRQF_ONESHOT,
> + dev_name(dev), ddev);
> + if (ret) {
> + DRM_ERROR("Failed to register LTDC interrupt\n");
> + return ret;
> + }
> + }
> +
> + if (!IS_ERR(rstc))
> + reset_control_deassert(rstc);
> +
> + /* Disable interrupts */
> + reg_clear(ldev->regs, LTDC_IER,
> + IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE);
> +
> + ret = ltdc_get_caps(ddev);
> + if (ret) {
> + DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
> + ldev->caps.hw_version);
> + return ret;
> + }
> +
> + DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version);
> +
> + if (ldev->panel) {
> + encoder = ltdc_rgb_encoder_create(ddev);
> + if (!encoder) {
> + DRM_ERROR("Failed to create RGB encoder\n");
> + ret = -EINVAL;
> + goto err;
> + }
> +
> + connector = ltdc_rgb_connector_create(ddev);
> + if (!connector) {
> + DRM_ERROR("Failed to create RGB connector\n");
> + ret = -EINVAL;
> + goto err;
> + }
> +
> + ret = drm_mode_connector_attach_encoder(connector, encoder);
> + if (ret) {
> + DRM_ERROR("Failed to attach connector to encoder\n");
> + goto err;
> + }
> +
> + drm_panel_attach(ldev->panel, connector);
> + }
> +
> + crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
> + if (!crtc) {
> + DRM_ERROR("Failed to allocate crtc\n");
> + ret = -ENOMEM;
> + goto err;
> + }
> +
> + ret = ltdc_crtc_init(ddev, crtc);
> + if (ret) {
> + DRM_ERROR("Failed to init crtc\n");
> + goto err;
> + }
> +
> + ret = drm_vblank_init(ddev, NB_CRTC);
> + if (ret) {
> + DRM_ERROR("Failed calling drm_vblank_init()\n");
> + goto err;
> + }
> +
> + /* Allow usage of vblank without having to call drm_irq_install */
> + ddev->irq_enabled = 1;
> +
> + return 0;
> +err:
> + if (ldev->panel)
> + drm_panel_detach(ldev->panel);
> +
> + clk_disable_unprepare(ldev->pixel_clk);
> +
> + return ret;
> +}
> +
> +void ltdc_unload(struct drm_device *ddev)
> +{
> + struct ltdc_device *ldev = ddev->dev_private;
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + drm_vblank_cleanup(ddev);
> +
> + if (ldev->panel)
> + drm_panel_detach(ldev->panel);
> +
> + clk_disable_unprepare(ldev->pixel_clk);
> +}
> +
> +MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
> +MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
> +MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
> +MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
> +MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
> new file mode 100644
> index 0000000..d7a9c73
> --- /dev/null
> +++ b/drivers/gpu/drm/stm/ltdc.h
> @@ -0,0 +1,40 @@
> +/*
> + * Copyright (C) STMicroelectronics SA 2017
> + *
> + * Authors: Philippe Cornu <philippe.cornu@st.com>
> + * Yannick Fertre <yannick.fertre@st.com>
> + * Fabien Dessenne <fabien.dessenne@st.com>
> + * Mickael Reulier <mickael.reulier@st.com>
> + *
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#ifndef _LTDC_H_
> +#define _LTDC_H_
> +
> +struct ltdc_caps {
> + u32 hw_version; /* hardware version */
> + u32 nb_layers; /* number of supported layers */
> + u32 reg_ofs; /* register offset for applicable regs */
> + u32 bus_width; /* bus width (32 or 64 bits) */
> + const u32 *pix_fmt_hw; /* supported pixel formats */
> +};
> +
> +struct ltdc_device {
> + struct drm_fbdev_cma *fbdev;
> + void __iomem *regs;
> + struct clk *pixel_clk; /* lcd pixel clock */
> + struct drm_panel *panel;
> + struct mutex err_lock; /* protecting error_status */
> + struct ltdc_caps caps;
> + u32 clut[256]; /* color look up table */
> + u32 error_status;
> + u32 irq_status;
> +};
> +
> +int ltdc_crtc_enable_vblank(struct drm_device *dev, unsigned int pipe);
> +void ltdc_crtc_disable_vblank(struct drm_device *dev, unsigned int pipe);
> +int ltdc_load(struct drm_device *ddev);
> +void ltdc_unload(struct drm_device *ddev);
> +
> +#endif
>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH v7 2/9] drm/fb-cma-helper: Add drm_fb_cma_get_gem_addr()
From: Neil Armstrong @ 2017-04-14 12:54 UTC (permalink / raw)
To: Yannick Fertre, Alexandre TORGUE, Thierry Reding, David Airlie,
Maxime Coquelin, Russell King, Mark Rutland, Rob Herring,
Arnd Bergmann, Benjamin Gaignard
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, kernel-F5mvAk5X5gdBDgjK7y7TUQ,
Philippe Cornu, Fabien Dessenne,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Mickael Reulier,
Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1492164819-10513-3-git-send-email-yannick.fertre-qxv4g6HH51o@public.gmane.org>
On 04/14/2017 12:13 PM, Yannick Fertre wrote:
> Add function drm_fb_cma_get_gem_addr() which return the physical address
> of framebuffer (1st pixel). This function will usually be called by plane
> callback (atomic_update).
>
> Signed-off-by: Yannick Fertre <yannick.fertre-qxv4g6HH51o@public.gmane.org>
> ---
> drivers/gpu/drm/drm_fb_cma_helper.c | 27 +++++++++++++++++++++++++++
> include/drm/drm_fb_cma_helper.h | 4 ++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c b/drivers/gpu/drm/drm_fb_cma_helper.c
> index 50abd1f..d2b77b0 100644
> --- a/drivers/gpu/drm/drm_fb_cma_helper.c
> +++ b/drivers/gpu/drm/drm_fb_cma_helper.c
> @@ -260,6 +260,33 @@ struct drm_gem_cma_object *drm_fb_cma_get_gem_obj(struct drm_framebuffer *fb,
> EXPORT_SYMBOL_GPL(drm_fb_cma_get_gem_obj);
>
> /**
> + * drm_fb_cma_get_gem_addr() - Get physical address for framebuffer
> + * @fb: The framebuffer
> + * @state: Which state of drm plane
> + * @plane: Which plane
> + * Return the CMA GEM address for given framebuffer.
> + *
> + * This function will usually be called from the PLANE callback functions.
> + */
> +dma_addr_t drm_fb_cma_get_gem_addr(struct drm_framebuffer *fb,
> + struct drm_plane_state *state,
> + unsigned int plane)
> +{
> + struct drm_fb_cma *fb_cma = to_fb_cma(fb);
> + dma_addr_t paddr;
> +
> + if (plane >= 4)
> + return 0;
Nitpick, but why not using drm_fb_cma_get_gem_obj(fb, plane) here ?
=====
struct drm_gem_cma_object *gem = drm_fb_cma_get_gem_obj(fb, plane);
if (!gem)
return 0;
paddr = gem->paddr + fb->offsets[plane];
======
> +
> + paddr = fb_cma->obj[plane]->paddr + fb->offsets[plane];
> + paddr += fb->format->cpp[plane] * (state->src_x >> 16);
> + paddr += fb->pitches[plane] * (state->src_y >> 16);
> +
> + return paddr;
> +}
> +EXPORT_SYMBOL_GPL(drm_fb_cma_get_gem_addr);
> +
> +/**
> * drm_fb_cma_prepare_fb() - Prepare CMA framebuffer
> * @plane: Which plane
> * @state: Plane state attach fence to
> diff --git a/include/drm/drm_fb_cma_helper.h b/include/drm/drm_fb_cma_helper.h
> index a5ecc0a..199a63f 100644
> --- a/include/drm/drm_fb_cma_helper.h
> +++ b/include/drm/drm_fb_cma_helper.h
> @@ -41,6 +41,10 @@ struct drm_framebuffer *drm_fb_cma_create(struct drm_device *dev,
> struct drm_gem_cma_object *drm_fb_cma_get_gem_obj(struct drm_framebuffer *fb,
> unsigned int plane);
>
> +dma_addr_t drm_fb_cma_get_gem_addr(struct drm_framebuffer *fb,
> + struct drm_plane_state *state,
> + unsigned int plane);
> +
> int drm_fb_cma_prepare_fb(struct drm_plane *plane,
> struct drm_plane_state *state);
>
>
Anyway it's still ok,
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH v7 1/9] drm/cma: Update DEFINE_DRM_GEM_CMA_FOPS to add get_unmapped_area
From: Neil Armstrong @ 2017-04-14 12:49 UTC (permalink / raw)
To: Yannick Fertre, Alexandre TORGUE, Thierry Reding, David Airlie,
Maxime Coquelin, Russell King, Mark Rutland, Rob Herring,
Arnd Bergmann, Benjamin Gaignard
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, kernel-F5mvAk5X5gdBDgjK7y7TUQ,
Philippe Cornu, Fabien Dessenne,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Mickael Reulier,
Vincent Abriou, Gabriel FERNANDEZ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1492164819-10513-2-git-send-email-yannick.fertre-qxv4g6HH51o@public.gmane.org>
On 04/14/2017 12:13 PM, Yannick Fertre wrote:
> Missing field get_unmapped_area which is necessary with device without MMU
>
> Signed-off-by: Yannick Fertre <yannick.fertre-qxv4g6HH51o@public.gmane.org>
> ---
> include/drm/drm_gem_cma_helper.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/drm/drm_gem_cma_helper.h b/include/drm/drm_gem_cma_helper.h
> index f962d33..7320b14 100644
> --- a/include/drm/drm_gem_cma_helper.h
> +++ b/include/drm/drm_gem_cma_helper.h
> @@ -50,6 +50,7 @@ struct drm_gem_cma_object {
> .read = drm_read,\
> .llseek = noop_llseek,\
> .mmap = drm_gem_cma_mmap,\
> + .get_unmapped_area = drm_gem_cma_get_unmapped_area,\
> }
>
> /* free GEM object */
>
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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