* [PATCH v2 04/35] nds32: MMU definitions
From: Greentime Hu @ 2017-11-27 12:27 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial
Cc: green.hu, Vincent Chen
In-Reply-To: <cover.1511785528.git.green.hu@gmail.com>
From: Greentime Hu <greentime@andestech.com>
This patch includes virtual memory layout, PHYS_OFFSET is defined as 0x0. It
also includes the 4KB/8KB page size configurations and pte operations.
Signed-off-by: Vincent Chen <vincentc@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
---
arch/nds32/include/asm/fixmap.h | 42 ++++
arch/nds32/include/asm/highmem.h | 78 +++++++
arch/nds32/include/asm/memory.h | 118 ++++++++++
arch/nds32/include/asm/mmu.h | 25 +++
arch/nds32/include/asm/page.h | 78 +++++++
arch/nds32/include/asm/pgalloc.h | 109 ++++++++++
arch/nds32/include/asm/pgtable.h | 426 +++++++++++++++++++++++++++++++++++++
arch/nds32/include/asm/shmparam.h | 32 +++
8 files changed, 908 insertions(+)
create mode 100644 arch/nds32/include/asm/fixmap.h
create mode 100644 arch/nds32/include/asm/highmem.h
create mode 100644 arch/nds32/include/asm/memory.h
create mode 100644 arch/nds32/include/asm/mmu.h
create mode 100644 arch/nds32/include/asm/page.h
create mode 100644 arch/nds32/include/asm/pgalloc.h
create mode 100644 arch/nds32/include/asm/pgtable.h
create mode 100644 arch/nds32/include/asm/shmparam.h
diff --git a/arch/nds32/include/asm/fixmap.h b/arch/nds32/include/asm/fixmap.h
new file mode 100644
index 0000000..daeddab
--- /dev/null
+++ b/arch/nds32/include/asm/fixmap.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ASM_NDS32_FIXMAP_H
+#define __ASM_NDS32_FIXMAP_H
+
+#ifdef CONFIG_HIGHMEM
+#include <linux/threads.h>
+#include <asm/kmap_types.h>
+#endif
+
+enum fixed_addresses {
+ FIX_HOLE,
+ FIX_KMAP_RESERVED,
+ FIX_KMAP_BEGIN,
+#ifdef CONFIG_HIGHMEM
+ FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_TYPE_NR * NR_CPUS),
+#endif
+ FIX_EARLYCON_MEM_BASE,
+ __end_of_fixed_addresses
+};
+#define FIXADDR_TOP ((unsigned long) (-(16 * PAGE_SIZE)))
+#define FIXADDR_SIZE ((__end_of_fixed_addresses) << PAGE_SHIFT)
+#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
+#define FIXMAP_PAGE_IO __pgprot(PAGE_DEVICE)
+void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot);
+
+#include <asm-generic/fixmap.h>
+#endif /* __ASM_NDS32_FIXMAP_H */
diff --git a/arch/nds32/include/asm/highmem.h b/arch/nds32/include/asm/highmem.h
new file mode 100644
index 0000000..6a569c1
--- /dev/null
+++ b/arch/nds32/include/asm/highmem.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _ASM_HIGHMEM_H
+#define _ASM_HIGHMEM_H
+
+#include <asm/proc-fns.h>
+#include <asm/kmap_types.h>
+#include <asm/fixmap.h>
+#include <asm/pgtable.h>
+
+/*
+ * Right now we initialize only a single pte table. It can be extended
+ * easily, subsequent pte tables have to be allocated in one physical
+ * chunk of RAM.
+ */
+/*
+ * Ordering is (from lower to higher memory addresses):
+ *
+ * high_memory
+ * Persistent kmap area
+ * PKMAP_BASE
+ * fixed_addresses
+ * FIXADDR_START
+ * FIXADDR_TOP
+ * Vmalloc area
+ * VMALLOC_START
+ * VMALLOC_END
+ */
+#define PKMAP_BASE ((FIXADDR_START - PGDIR_SIZE) & (PGDIR_MASK))
+#define LAST_PKMAP PTRS_PER_PTE
+#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
+#define PKMAP_NR(virt) (((virt) - (PKMAP_BASE)) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
+#define kmap_prot PAGE_KERNEL
+
+static inline void flush_cache_kmaps(void)
+{
+ cpu_dcache_wbinval_all();
+}
+
+/* declarations for highmem.c */
+extern unsigned long highstart_pfn, highend_pfn;
+
+extern pte_t *pkmap_page_table;
+
+extern void *kmap_high(struct page *page);
+extern void kunmap_high(struct page *page);
+
+extern void kmap_init(void);
+
+/*
+ * The following functions are already defined by <linux/highmem.h>
+ * when CONFIG_HIGHMEM is not set.
+ */
+#ifdef CONFIG_HIGHMEM
+extern void *kmap(struct page *page);
+extern void kunmap(struct page *page);
+extern void *kmap_atomic(struct page *page);
+extern void __kunmap_atomic(void *kvaddr);
+extern void *kmap_atomic_pfn(unsigned long pfn);
+extern struct page *kmap_atomic_to_page(void *ptr);
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/memory.h b/arch/nds32/include/asm/memory.h
new file mode 100644
index 0000000..7891654
--- /dev/null
+++ b/arch/nds32/include/asm/memory.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ASM_NDS32_MEMORY_H
+#define __ASM_NDS32_MEMORY_H
+
+#include <linux/compiler.h>
+#include <linux/sizes.h>
+
+#ifndef __ASSEMBLY__
+#include <asm/page.h>
+#endif
+
+#ifndef PHYS_OFFSET
+#define PHYS_OFFSET (0x0)
+#endif
+
+#ifndef __virt_to_bus
+#define __virt_to_bus __virt_to_phys
+#endif
+
+#ifndef __bus_to_virt
+#define __bus_to_virt __phys_to_virt
+#endif
+
+/*
+ * TASK_SIZE - the maximum size of a user space task.
+ * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
+ */
+#define TASK_SIZE ((CONFIG_PAGE_OFFSET) - (SZ_32M))
+#define TASK_UNMAPPED_BASE ALIGN(TASK_SIZE / 3, SZ_32M)
+#define PAGE_OFFSET (CONFIG_PAGE_OFFSET)
+
+/*
+ * Physical vs virtual RAM address space conversion. These are
+ * private definitions which should NOT be used outside memory.h
+ * files. Use virt_to_phys/phys_to_virt/__pa/__va instead.
+ */
+#ifndef __virt_to_phys
+#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET)
+#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET)
+#endif
+
+/*
+ * The module space lives between the addresses given by TASK_SIZE
+ * and PAGE_OFFSET - it must be within 32MB of the kernel text.
+ */
+#define MODULES_END (PAGE_OFFSET)
+#define MODULES_VADDR (MODULES_END - SZ_32M)
+
+#if TASK_SIZE > MODULES_VADDR
+#error Top of user space clashes with start of module space
+#endif
+
+#ifndef __ASSEMBLY__
+
+/*
+ * PFNs are used to describe any physical page; this means
+ * PFN 0 == physical address 0.
+ *
+ * This is the PFN of the first RAM page in the kernel
+ * direct-mapped view. We assume this is the first page
+ * of RAM in the mem_map as well.
+ */
+#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT)
+
+/*
+ * Drivers should NOT use these either.
+ */
+#define __pa(x) __virt_to_phys((unsigned long)(x))
+#define __va(x) ((void *)__phys_to_virt((unsigned long)(x)))
+
+/*
+ * Conversion between a struct page and a physical address.
+ *
+ * Note: when converting an unknown physical address to a
+ * struct page, the resulting pointer must be validated
+ * using VALID_PAGE(). It must return an invalid struct page
+ * for any physical address not corresponding to a system
+ * RAM address.
+ *
+ * pfn_valid(pfn) indicates whether a PFN number is valid
+ *
+ * virt_to_page(k) convert a _valid_ virtual address to struct page *
+ * virt_addr_valid(k) indicates whether a virtual address is valid
+ */
+#ifndef CONFIG_DISCONTIGMEM
+
+#define ARCH_PFN_OFFSET PHYS_PFN_OFFSET
+#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
+
+#define virt_to_page(kaddr) (pfn_to_page(__pa(kaddr) >> PAGE_SHIFT))
+#define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
+
+#else /* CONFIG_DISCONTIGMEM */
+#error CONFIG_DISCONTIGMEM is not supported yet.
+#endif /* !CONFIG_DISCONTIGMEM */
+
+#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
+
+#endif
+
+#include <asm-generic/memory_model.h>
+
+#endif
diff --git a/arch/nds32/include/asm/mmu.h b/arch/nds32/include/asm/mmu.h
new file mode 100644
index 0000000..147fd06
--- /dev/null
+++ b/arch/nds32/include/asm/mmu.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __NDS32_MMU_H
+#define __NDS32_MMU_H
+
+typedef struct {
+ unsigned int id;
+ void *vdso;
+} mm_context_t;
+
+#endif
diff --git a/arch/nds32/include/asm/page.h b/arch/nds32/include/asm/page.h
new file mode 100644
index 0000000..7e93d69
--- /dev/null
+++ b/arch/nds32/include/asm/page.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _ASMNDS32_PAGE_H
+#define _ASMNDS32_PAGE_H
+
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+#define PAGE_SHIFT 12
+#endif
+#ifdef CONFIG_ANDES_PAGE_SIZE_8KB
+#define PAGE_SHIFT 13
+#endif
+#include <linux/const.h>
+#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
+#define PAGE_MASK (~(PAGE_SIZE-1))
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+struct page;
+struct vm_area_struct;
+#ifndef CONFIG_CPU_CACHE_NONALIASING
+extern void copy_user_highpage(struct page *to, struct page *from,
+ unsigned long vaddr, struct vm_area_struct *vma);
+extern void clear_user_highpage(struct page *page, unsigned long vaddr);
+
+#define __HAVE_ARCH_COPY_USER_HIGHPAGE
+#define clear_user_highpage clear_user_highpage
+#else
+#define clear_user_page(page, vaddr, pg) clear_page(page)
+#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
+#endif
+
+void clear_page(void *page);
+void copy_page(void *to, void *from);
+
+typedef unsigned long pte_t;
+typedef unsigned long pmd_t;
+typedef unsigned long pgd_t;
+typedef unsigned long pgprot_t;
+
+#define pte_val(x) (x)
+#define pmd_val(x) (x)
+#define pgd_val(x) (x)
+#define pgprot_val(x) (x)
+
+#define __pte(x) (x)
+#define __pmd(x) (x)
+#define __pgd(x) (x)
+#define __pgprot(x) (x)
+
+typedef struct page *pgtable_t;
+
+#include <asm/memory.h>
+#include <asm-generic/getorder.h>
+
+#endif /* !__ASSEMBLY__ */
+
+#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
+ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/nds32/include/asm/pgalloc.h b/arch/nds32/include/asm/pgalloc.h
new file mode 100644
index 0000000..0b7530b
--- /dev/null
+++ b/arch/nds32/include/asm/pgalloc.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _ASMNDS32_PGALLOC_H
+#define _ASMNDS32_PGALLOC_H
+
+#include <asm/processor.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/proc-fns.h>
+
+/*
+ * Since we have only two-level page tables, these are trivial
+ */
+#define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *)2); })
+#define pmd_free(mm, pmd) do { } while (0)
+#define pgd_populate(mm, pmd, pte) BUG()
+#define pmd_pgtable(pmd) pmd_page(pmd)
+
+extern pgd_t *pgd_alloc(struct mm_struct *mm);
+extern void pgd_free(struct mm_struct *mm, pgd_t * pgd);
+
+#define check_pgt_cache() do { } while (0)
+
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+ unsigned long addr)
+{
+ pte_t *pte;
+
+ pte =
+ (pte_t *) __get_free_page(GFP_KERNEL | __GFP_RETRY_MAYFAIL |
+ __GFP_ZERO);
+
+ return pte;
+}
+
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+ pgtable_t pte;
+
+ pte = alloc_pages(GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_ZERO, 0);
+ if (pte)
+ cpu_dcache_wb_page((unsigned long)page_address(pte));
+
+ return pte;
+}
+
+/*
+ * Free one PTE table.
+ */
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t * pte)
+{
+ if (pte) {
+ free_page((unsigned long)pte);
+ }
+}
+
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
+{
+ __free_page(pte);
+}
+
+/*
+ * Populate the pmdp entry with a pointer to the pte. This pmd is part
+ * of the mm address space.
+ *
+ * Ensure that we always set both PMD entries.
+ */
+static inline void
+pmd_populate_kernel(struct mm_struct *mm, pmd_t * pmdp, pte_t * ptep)
+{
+ unsigned long pte_ptr = (unsigned long)ptep;
+ unsigned long pmdval;
+
+ BUG_ON(mm != &init_mm);
+
+ /*
+ * The pmd must be loaded with the physical
+ * address of the PTE table
+ */
+ pmdval = __pa(pte_ptr) | _PAGE_KERNEL_TABLE;
+ set_pmd(pmdp, __pmd(pmdval));
+}
+
+static inline void
+pmd_populate(struct mm_struct *mm, pmd_t * pmdp, pgtable_t ptep)
+{
+ unsigned long pmdval;
+
+ BUG_ON(mm == &init_mm);
+
+ pmdval = page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE;
+ set_pmd(pmdp, __pmd(pmdval));
+}
+
+#endif
diff --git a/arch/nds32/include/asm/pgtable.h b/arch/nds32/include/asm/pgtable.h
new file mode 100644
index 0000000..a09f1f8
--- /dev/null
+++ b/arch/nds32/include/asm/pgtable.h
@@ -0,0 +1,426 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _ASMNDS32_PGTABLE_H
+#define _ASMNDS32_PGTABLE_H
+
+#define __PAGETABLE_PMD_FOLDED
+#include <asm-generic/4level-fixup.h>
+#include <asm-generic/sizes.h>
+
+#include <asm/memory.h>
+#include <asm/nds32.h>
+#ifndef __ASSEMBLY__
+#include <asm/fixmap.h>
+#include <asm-generic/io.h>
+#include <nds32_intrinsic.h>
+#endif
+
+#ifdef CONFIG_CACHE_L2
+#include <asm/l2_cache.h>
+#endif
+
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+#define PGDIR_SHIFT 22
+#define PTRS_PER_PGD 1024
+#define PMD_SHIFT 22
+#define PTRS_PER_PMD 1
+#define PTRS_PER_PTE 1024
+#endif
+
+#ifdef CONFIG_ANDES_PAGE_SIZE_8KB
+#define PGDIR_SHIFT 24
+#define PTRS_PER_PGD 256
+#define PMD_SHIFT 24
+#define PTRS_PER_PMD 1
+#define PTRS_PER_PTE 2048
+#endif
+
+#ifndef __ASSEMBLY__
+extern void __pte_error(const char *file, int line, unsigned long val);
+extern void __pmd_error(const char *file, int line, unsigned long val);
+extern void __pgd_error(const char *file, int line, unsigned long val);
+
+#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
+#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
+#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
+#endif /* !__ASSEMBLY__ */
+
+#define PMD_SIZE (1UL << PMD_SHIFT)
+#define PMD_MASK (~(PMD_SIZE-1))
+#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK (~(PGDIR_SIZE-1))
+
+/*
+ * This is the lowest virtual address we can permit any user space
+ * mapping to be mapped at. This is particularly important for
+ * non-high vector CPUs.
+ */
+#define FIRST_USER_ADDRESS 0x8000
+
+#ifdef CONFIG_HIGHMEM
+#define CONSISTENT_BASE ((PKMAP_BASE) - (SZ_2M))
+#define CONSISTENT_END (PKMAP_BASE)
+#else
+#define CONSISTENT_BASE (FIXADDR_START - SZ_2M)
+#define CONSISTENT_END (FIXADDR_START)
+#endif
+#define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
+
+#ifdef CONFIG_HIGHMEM
+#ifndef __ASSEMBLY__
+#include <asm/highmem.h>
+#endif
+#endif
+
+#define VMALLOC_RESERVE SZ_128M
+#define VMALLOC_END (CONSISTENT_BASE - PAGE_SIZE)
+#define VMALLOC_START ((VMALLOC_END) - VMALLOC_RESERVE)
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define MAXMEM __pa(VMALLOC_START)
+#define MAXMEM_PFN PFN_DOWN(MAXMEM)
+
+#define FIRST_USER_PGD_NR 0
+#define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) + FIRST_USER_PGD_NR)
+
+/* L2 PTE */
+#define _PAGE_V (1UL << 0)
+
+#define _PAGE_M_XKRW (0UL << 1)
+#define _PAGE_M_UR_KR (1UL << 1)
+#define _PAGE_M_UR_KRW (2UL << 1)
+#define _PAGE_M_URW_KRW (3UL << 1)
+#define _PAGE_M_KR (5UL << 1)
+#define _PAGE_M_KRW (7UL << 1)
+
+#define _PAGE_D (1UL << 4)
+#define _PAGE_E (1UL << 5)
+#define _PAGE_A (1UL << 6)
+#define _PAGE_G (1UL << 7)
+
+#define _PAGE_C_DEV (0UL << 8)
+#define _PAGE_C_DEV_WB (1UL << 8)
+#define _PAGE_C_MEM (2UL << 8)
+#define _PAGE_C_MEM_SHRD_WB (4UL << 8)
+#define _PAGE_C_MEM_SHRD_WT (5UL << 8)
+#define _PAGE_C_MEM_WB (6UL << 8)
+#define _PAGE_C_MEM_WT (7UL << 8)
+
+#define _PAGE_L (1UL << 11)
+
+#define _HAVE_PAGE_L (_PAGE_L)
+#define _PAGE_FILE (1UL << 1)
+#define _PAGE_YOUNG 0
+#define _PAGE_M_MASK _PAGE_M_KRW
+#define _PAGE_C_MASK _PAGE_C_MEM_WT
+
+#ifdef CONFIG_SMP
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+#define _PAGE_CACHE_SHRD _PAGE_C_MEM_SHRD_WT
+#else
+#define _PAGE_CACHE_SHRD _PAGE_C_MEM_SHRD_WB
+#endif
+#else
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+#define _PAGE_CACHE_SHRD _PAGE_C_MEM_WT
+#else
+#define _PAGE_CACHE_SHRD _PAGE_C_MEM_WB
+#endif
+#endif
+
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+#define _PAGE_CACHE _PAGE_C_MEM_WT
+#else
+#define _PAGE_CACHE _PAGE_C_MEM_WB
+#endif
+
+/*
+ * + Level 1 descriptor (PMD)
+ */
+#define PMD_TYPE_TABLE 0
+
+#ifndef __ASSEMBLY__
+
+#define _PAGE_USER_TABLE PMD_TYPE_TABLE
+#define _PAGE_KERNEL_TABLE PMD_TYPE_TABLE
+
+#define PAGE_EXEC __pgprot(_PAGE_V | _PAGE_M_XKRW | _PAGE_E)
+#define PAGE_NONE __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_A)
+#define PAGE_READ __pgprot(_PAGE_V | _PAGE_M_UR_KR)
+#define PAGE_RDWR __pgprot(_PAGE_V | _PAGE_M_URW_KRW | _PAGE_D)
+#define PAGE_COPY __pgprot(_PAGE_V | _PAGE_M_UR_KR)
+
+#define PAGE_UXKRWX_V1 __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
+#define PAGE_UXKRWX_V2 __pgprot(_PAGE_V | _PAGE_M_XKRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
+#define PAGE_URXKRWX_V2 __pgprot(_PAGE_V | _PAGE_M_UR_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
+#define PAGE_CACHE_L1 __pgprot(_HAVE_PAGE_L | _PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE)
+#define PAGE_MEMORY __pgprot(_HAVE_PAGE_L | _PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
+#define PAGE_KERNEL __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
+#define PAGE_DEVICE __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_G | _PAGE_C_DEV)
+#endif /* __ASSEMBLY__ */
+
+/* xwr */
+#define __P000 (PAGE_NONE | _PAGE_CACHE_SHRD)
+#define __P001 (PAGE_READ | _PAGE_CACHE_SHRD)
+#define __P010 (PAGE_COPY | _PAGE_CACHE_SHRD)
+#define __P011 (PAGE_COPY | _PAGE_CACHE_SHRD)
+#define __P100 (PAGE_EXEC | _PAGE_CACHE_SHRD)
+#define __P101 (PAGE_READ | _PAGE_E | _PAGE_CACHE_SHRD)
+#define __P110 (PAGE_COPY | _PAGE_E | _PAGE_CACHE_SHRD)
+#define __P111 (PAGE_COPY | _PAGE_E | _PAGE_CACHE_SHRD)
+
+#define __S000 (PAGE_NONE | _PAGE_CACHE_SHRD)
+#define __S001 (PAGE_READ | _PAGE_CACHE_SHRD)
+#define __S010 (PAGE_RDWR | _PAGE_CACHE_SHRD)
+#define __S011 (PAGE_RDWR | _PAGE_CACHE_SHRD)
+#define __S100 (PAGE_EXEC | _PAGE_CACHE_SHRD)
+#define __S101 (PAGE_READ | _PAGE_E | _PAGE_CACHE_SHRD)
+#define __S110 (PAGE_RDWR | _PAGE_E | _PAGE_CACHE_SHRD)
+#define __S111 (PAGE_RDWR | _PAGE_E | _PAGE_CACHE_SHRD)
+
+#ifndef __ASSEMBLY__
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern struct page *empty_zero_page;
+extern void paging_init(void);
+#define ZERO_PAGE(vaddr) (empty_zero_page)
+
+#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
+#define pfn_pte(pfn,prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)))
+
+#define pte_none(pte) !(pte_val(pte))
+#define pte_clear(mm,addr,ptep) set_pte_at((mm),(addr),(ptep), __pte(0))
+#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
+
+#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_offset_kernel(dir, address) ((pte_t *)pmd_page_kernel(*(dir)) + pte_index(address))
+#define pte_offset_map(dir, address) ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
+#define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
+#define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
+
+#define pte_unmap(pte) do { } while (0)
+#define pte_unmap_nested(pte) do { } while (0)
+
+#define pmd_off_k(address) pmd_offset(pgd_offset_k(address), address)
+
+#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
+/*
+ * Set a level 1 translation table entry, and clean it out of
+ * any caches such that the MMUs can load it correctly.
+ */
+static inline void set_pmd(pmd_t * pmdp, pmd_t pmd)
+{
+
+ *pmdp = pmd;
+#if !defined(CONFIG_CPU_DCACHE_DISABLE) && !defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (pmdp):"memory");
+ __nds32__msync_all();
+ __nds32__dsb();
+#endif
+}
+
+/*
+ * Set a PTE and flush it out
+ */
+static inline void set_pte(pte_t * ptep, pte_t pte)
+{
+
+ *ptep = pte;
+#if !defined(CONFIG_CPU_DCACHE_DISABLE) && !defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (ptep):"memory");
+ __nds32__msync_all();
+ __nds32__dsb();
+#endif
+}
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+
+/*
+ * pte_write: this page is writeable for user mode
+ * pte_read: this page is readable for user mode
+ * pte_kernel_write: this page is writeable for kernel mode
+ *
+ * We don't have pte_kernel_read because kernel always can read.
+ *
+ * */
+
+#define pte_present(pte) (pte_val(pte) & _PAGE_V)
+#define pte_write(pte) ((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_URW_KRW)
+#define pte_read(pte) (((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_UR_KR) || \
+ ((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_UR_KRW) || \
+ ((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_URW_KRW))
+#define pte_kernel_write(pte) (((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_URW_KRW) || \
+ ((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_UR_KRW) || \
+ ((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_KRW) || \
+ (((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_XKRW) && pte_exec(pte)))
+#define pte_exec(pte) (pte_val(pte) & _PAGE_E)
+#define pte_dirty(pte) (pte_val(pte) & _PAGE_D)
+#define pte_young(pte) (pte_val(pte) & _PAGE_YOUNG)
+
+/*
+ * The following only works if pte_present() is not true.
+ */
+#define pte_file(pte) (pte_val(pte) & _PAGE_FILE)
+#define pte_to_pgoff(x) (pte_val(x) >> 2)
+#define pgoff_to_pte(x) __pte(((x) << 2) | _PAGE_FILE)
+
+#define PTE_FILE_MAX_BITS 29
+
+#define PTE_BIT_FUNC(fn,op) \
+static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
+
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+ pte_val(pte) = pte_val(pte) & ~_PAGE_M_MASK;
+ pte_val(pte) = pte_val(pte) | _PAGE_M_UR_KR;
+ return pte;
+}
+
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+ pte_val(pte) = pte_val(pte) & ~_PAGE_M_MASK;
+ pte_val(pte) = pte_val(pte) | _PAGE_M_URW_KRW;
+ return pte;
+}
+
+PTE_BIT_FUNC(exprotect, &=~_PAGE_E);
+PTE_BIT_FUNC(mkexec, |=_PAGE_E);
+PTE_BIT_FUNC(mkclean, &=~_PAGE_D);
+PTE_BIT_FUNC(mkdirty, |=_PAGE_D);
+PTE_BIT_FUNC(mkold, &=~_PAGE_YOUNG);
+PTE_BIT_FUNC(mkyoung, |=_PAGE_YOUNG);
+static inline int pte_special(pte_t pte)
+{
+ return 0;
+}
+
+static inline pte_t pte_mkspecial(pte_t pte)
+{
+ return pte;
+}
+
+/*
+ * Mark the prot value as uncacheable and unbufferable.
+ */
+#define pgprot_noncached(prot) __pgprot((pgprot_val(prot)&~_PAGE_C_MASK) | _PAGE_C_DEV)
+#define pgprot_writecombine(prot) __pgprot((pgprot_val(prot)&~_PAGE_C_MASK) | _PAGE_C_DEV_WB)
+
+#define pmd_none(pmd) (pmd_val(pmd)&0x1)
+#define pmd_present(pmd) (!pmd_none(pmd))
+#define pmd_bad(pmd) pmd_none(pmd)
+
+#define copy_pmd(pmdpd,pmdps) set_pmd((pmdpd), *(pmdps))
+#define pmd_clear(pmdp) set_pmd((pmdp), __pmd(1))
+
+static inline pmd_t __mk_pmd(pte_t * ptep, unsigned long prot)
+{
+ unsigned long ptr = (unsigned long)ptep;
+ pmd_t pmd;
+
+ /*
+ * The pmd must be loaded with the physical
+ * address of the PTE table
+ */
+
+ pmd_val(pmd) = __virt_to_phys(ptr) | prot;
+ return pmd;
+}
+
+#define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd)))
+
+/*
+ * Permanent address of a page. We never have highmem, so this is trivial.
+ */
+#define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT))
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
+
+/*
+ * The "pgd_xxx()" functions here are trivial for a folded two-level
+ * setup: the pgd is never bad, and a pmd always exists (as it's folded
+ * into the pgd entry)
+ */
+#define pgd_none(pgd) (0)
+#define pgd_bad(pgd) (0)
+#define pgd_present(pgd) (1)
+#define pgd_clear(pgdp) do { } while (0)
+
+#define page_pte_prot(page,prot) mk_pte(page, prot)
+#define page_pte(page) mk_pte(page, __pgprot(0))
+/*
+ * L1PTE = $mr1 + ((virt >> PMD_SHIFT) << 2);
+ * L2PTE = (((virt >> PAGE_SHIFT) & (PTRS_PER_PTE -1 )) << 2);
+ * PPN = (phys & 0xfffff000);
+ *
+*/
+
+/* to find an entry in a page-table-directory */
+#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
+#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
+
+/* Find an entry in the second-level page table.. */
+#define pmd_offset(dir, addr) ((pmd_t *)(dir))
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+ const unsigned long mask = 0xfff;
+ pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
+ return pte;
+}
+
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+
+/* Encode and decode a swap entry.
+ *
+ * We support up to 32GB of swap on 4k machines
+ */
+#define __swp_type(x) (((x).val >> 2) & 0x7f)
+#define __swp_offset(x) ((x).val >> 9)
+#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 9) })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
+
+/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
+#define kern_addr_valid(addr) (1)
+
+#include <asm-generic/pgtable.h>
+
+/*
+ * We provide our own arch_get_unmapped_area to cope with VIPT caches.
+ */
+#define HAVE_ARCH_UNMAPPED_AREA
+
+/*
+ * remap a physical address `phys' of size `size' with page protection `prot'
+ * into virtual address `from'
+ */
+
+#define pgtable_cache_init() do { } while (0)
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASMNDS32_PGTABLE_H */
diff --git a/arch/nds32/include/asm/shmparam.h b/arch/nds32/include/asm/shmparam.h
new file mode 100644
index 0000000..f05c539
--- /dev/null
+++ b/arch/nds32/include/asm/shmparam.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _ASMNDS32_SHMPARAM_H
+#define _ASMNDS32_SHMPARAM_H
+
+/*
+ * This should be the size of the virtually indexed cache/ways,
+ * whichever is greater since the cache aliases every size/ways
+ * bytes.
+ */
+#define SHMLBA (4 * SZ_8K) /* attach addr a multiple of this */
+
+/*
+ * Enforce SHMLBA in shmat
+ */
+#define __ARCH_FORCE_SHMLBA
+
+#endif /* _ASMNDS32_SHMPARAM_H */
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 03/35] nds32: Exception handling
From: Greentime Hu @ 2017-11-27 12:27 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial
Cc: green.hu, Vincent Chen
In-Reply-To: <cover.1511785528.git.green.hu@gmail.com>
From: Greentime Hu <greentime@andestech.com>
This patch includes the exception/interrupt entries, pt_reg structure and
related accessors.
Signed-off-by: Vincent Chen <vincentc@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
---
arch/nds32/include/asm/ptrace.h | 79 +++++
arch/nds32/kernel/ex-entry.S | 170 +++++++++++
arch/nds32/kernel/ex-exit.S | 206 +++++++++++++
arch/nds32/kernel/stacktrace.c | 60 ++++
arch/nds32/kernel/traps.c | 441 +++++++++++++++++++++++++++
arch/nds32/mm/alignment.c | 622 +++++++++++++++++++++++++++++++++++++++
6 files changed, 1578 insertions(+)
create mode 100644 arch/nds32/include/asm/ptrace.h
create mode 100644 arch/nds32/kernel/ex-entry.S
create mode 100644 arch/nds32/kernel/ex-exit.S
create mode 100644 arch/nds32/kernel/stacktrace.c
create mode 100644 arch/nds32/kernel/traps.c
create mode 100644 arch/nds32/mm/alignment.c
diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 0000000..2c9c03d
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ASM_NDS32_PTRACE_H
+#define __ASM_NDS32_PTRACE_H
+
+#define PTRACE_GETREGS 12
+#define PTRACE_SETREGS 13
+#define PTRACE_GETFPREGS 14
+#define PTRACE_SETFPREGS 15
+
+#include <uapi/asm/ptrace.h>
+
+#ifndef __ASSEMBLY__
+
+struct pt_regs {
+ union {
+ struct user_pt_regs user_regs;
+ struct {
+ long uregs[26];
+ long fp;
+ long gp;
+ long lp;
+ long sp;
+ long ipc;
+#if defined(CONFIG_HWZOL)
+ long lb;
+ long le;
+ long lc;
+#else
+ long dummy[3];
+#endif
+ long syscallno;
+ };
+ };
+ long orig_r0;
+ long ir0;
+ long ipsw;
+ long pipsw;
+ long pipc;
+ long pp0;
+ long pp1;
+ long fucop_ctl;
+ long osp;
+};
+
+#include <asm/bitfield.h>
+extern void show_regs(struct pt_regs *);
+/* Avoid circular header include via sched.h */
+struct task_struct;
+extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs,
+ int error_code, int si_code);
+
+#define arch_has_single_step() (1)
+#define user_mode(regs) (((regs)->ipsw & PSW_mskPOM) == 0)
+#define interrupts_enabled(regs) (!!((regs)->ipsw & PSW_mskGIE))
+#define valid_user_regs(regs) (user_mode(regs) && interrupts_enabled(regs))
+#define regs_return_value(regs) ((regs)->uregs[0])
+#define instruction_pointer(regs) ((regs)->ipc)
+#define user_stack_pointer(regs) ((regs)->sp)
+#define profile_pc(regs) instruction_pointer(regs)
+
+#define ARCH_HAS_USER_SINGLE_STEP_INFO
+
+#endif /* __ASSEMBLY__ */
+#endif
diff --git a/arch/nds32/kernel/ex-entry.S b/arch/nds32/kernel/ex-entry.S
new file mode 100644
index 0000000..09dc6a0
--- /dev/null
+++ b/arch/nds32/kernel/ex-entry.S
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <asm/memory.h>
+#include <asm/nds32.h>
+#include <asm/errno.h>
+#include <asm/asm-offsets.h>
+#include <asm/page.h>
+
+#ifdef CONFIG_HWZOL
+ .macro push_zol
+ mfusr $r14, $LB
+ mfusr $r15, $LE
+ mfusr $r16, $LC
+ .endm
+#endif
+
+ .macro save_user_regs
+
+ smw.adm $sp, [$sp], $sp, #0x1
+ /* move $SP to the bottom of pt_regs */
+ addi $sp, $sp, -OSP_OFFSET
+
+ /* push $r0 ~ $r25 */
+ smw.bim $r0, [$sp], $r25
+ /* push $fp, $gp, $lp */
+ smw.bim $sp, [$sp], $sp, #0xe
+
+ mfsr $r12, $SP_USR
+ mfsr $r13, $IPC
+#ifdef CONFIG_HWZOL
+ push_zol
+#endif
+ movi $r17, -1
+ move $r18, $r0
+ mfsr $r19, $PSW
+ mfsr $r20, $IPSW
+ mfsr $r21, $P_IPSW
+ mfsr $r22, $P_IPC
+ mfsr $r23, $P_P0
+ mfsr $r24, $P_P1
+ smw.bim $r12, [$sp], $r24, #0
+ addi $sp, $sp, -FUCOP_CTL_OFFSET
+
+ /* Initialize kernel space $fp */
+ andi $p0, $r20, #PSW_mskPOM
+ movi $p1, #0x0
+ cmovz $fp, $p1, $p0
+
+ andi $r16, $r19, #PSW_mskINTL
+ slti $r17, $r16, #4
+ bnez $r17, 1f
+ addi $r17, $r19, #-2
+ mtsr $r17, $PSW
+ isb
+1:
+ /* If it was superuser mode, we don't need to update $r25 */
+ bnez $p0, 2f
+ la $p0, __entry_task
+ lw $r25, [$p0]
+2:
+ .endm
+
+ .text
+
+/*
+ * Exception Vector
+ */
+exception_handlers:
+ .long unhandled_exceptions !Reset/NMI
+ .long unhandled_exceptions !TLB fill
+ .long do_page_fault !PTE not present
+ .long do_dispatch_tlb_misc !TLB misc
+ .long unhandled_exceptions !TLB VLPT
+ .long unhandled_exceptions !Machine Error
+ .long do_debug_trap !Debug related
+ .long do_dispatch_general !General exception
+ .long eh_syscall !Syscall
+ .long asm_do_IRQ !IRQ
+
+common_exception_handler:
+ save_user_regs
+ mfsr $p0, $ITYPE
+ andi $p0, $p0, #ITYPE_mskVECTOR
+ srli $p0, $p0, #ITYPE_offVECTOR
+ andi $p1, $p0, #NDS32_VECTOR_mskNONEXCEPTION
+ bnez $p1, 1f
+ sethi $lp, hi20(ret_from_exception)
+ ori $lp, $lp, lo12(ret_from_exception)
+ sethi $p1, hi20(exception_handlers)
+ ori $p1, $p1, lo12(exception_handlers)
+ lw $p1, [$p1+$p0<<2]
+ move $r0, $p0
+ mfsr $r1, $EVA
+ mfsr $r2, $ITYPE
+ move $r3, $sp
+ mfsr $r4, $OIPC
+ /* enable gie if it is enabled in IPSW. */
+ mfsr $r21, $PSW
+ andi $r20, $r20, #PSW_mskGIE /* r20 is $IPSW*/
+ or $r21, $r21, $r20
+ mtsr $r21, $PSW
+ dsb
+ jr $p1
+
+ /* syscall */
+1:
+ addi $p1, $p0, #-NDS32_VECTOR_offEXCEPTION
+ bnez $p1, 2f
+ sethi $lp, hi20(ret_from_exception)
+ ori $lp, $lp, lo12(ret_from_exception)
+ sethi $p1, hi20(exception_handlers)
+ ori $p1, $p1, lo12(exception_handlers)
+ lwi $p1, [$p1+#NDS32_VECTOR_offEXCEPTION<<2]
+ jr $p1
+
+ /* interrupt */
+2:
+#ifdef CONFIG_TRACE_IRQFLAGS
+ jal arch_trace_hardirqs_off
+#endif
+ move $r0, $sp
+ sethi $lp, hi20(ret_from_intr)
+ ori $lp, $lp, lo12(ret_from_intr)
+ sethi $p0, hi20(exception_handlers)
+ ori $p0, $p0, lo12(exception_handlers)
+ lwi $p0, [$p0+#NDS32_VECTOR_offINTERRUPT<<2]
+ jr $p0
+
+ .macro EXCEPTION_VECTOR_DEBUG
+ .align 4
+ mfsr $p0, $EDM_CTL
+ andi $p0, $p0, EDM_CTL_mskV3_EDM_MODE
+ tnez $p0, SWID_RAISE_INTERRUPT_LEVEL
+ .endm
+
+ .macro EXCEPTION_VECTOR
+ .align 4
+ sethi $p0, hi20(common_exception_handler)
+ ori $p0, $p0, lo12(common_exception_handler)
+ jral.ton $p0, $p0
+ .endm
+
+ .section ".text.init", #alloc, #execinstr
+ .global exception_vector
+exception_vector:
+.rept 5
+ EXCEPTION_VECTOR
+.endr
+ EXCEPTION_VECTOR_DEBUG
+.rept 122
+ EXCEPTION_VECTOR
+.endr
+ .align 4
+ .global exception_vector_end
+exception_vector_end:
diff --git a/arch/nds32/kernel/ex-exit.S b/arch/nds32/kernel/ex-exit.S
new file mode 100644
index 0000000..fc60e60
--- /dev/null
+++ b/arch/nds32/kernel/ex-exit.S
@@ -0,0 +1,206 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <asm/unistd.h>
+#include <asm/assembler.h>
+#include <asm/nds32.h>
+#include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
+#include <asm/current.h>
+
+
+
+#ifdef CONFIG_HWZOL
+ .macro pop_zol
+ mtusr $r14, $LB
+ mtusr $r15, $LE
+ mtusr $r16, $LC
+ .endm
+#endif
+
+ .macro restore_user_regs_first
+ setgie.d
+ isb
+
+ addi $sp, $sp, FUCOP_CTL_OFFSET
+
+ lmw.adm $r12, [$sp], $r24, #0x0
+ mtsr $r12, $SP_USR
+ mtsr $r13, $IPC
+#ifdef CONFIG_HWZOL
+ pop_zol
+#endif
+ mtsr $r19, $PSW
+ mtsr $r20, $IPSW
+ mtsr $r21, $P_IPSW
+ mtsr $r22, $P_IPC
+ mtsr $r23, $P_P0
+ mtsr $r24, $P_P1
+ lmw.adm $sp, [$sp], $sp, #0xe
+ .endm
+
+ .macro restore_user_regs_last
+ pop $p0
+ cmovn $sp, $p0, $p0
+
+ iret
+ nop
+
+ .endm
+
+ .macro restore_user_regs
+ restore_user_regs_first
+ lmw.adm $r0, [$sp], $r25, #0x0
+ addi $sp, $sp, OSP_OFFSET
+ restore_user_regs_last
+ .endm
+
+ .macro fast_restore_user_regs
+ restore_user_regs_first
+ lmw.adm $r1, [$sp], $r25, #0x0
+ addi $sp, $sp, OSP_OFFSET-4
+ restore_user_regs_last
+ .endm
+
+#ifdef CONFIG_PREEMPT
+ .macro preempt_stop
+ .endm
+#else
+ .macro preempt_stop
+ setgie.d
+ isb
+ .endm
+#define resume_kernel no_work_pending
+#endif
+
+ENTRY(ret_from_exception)
+ preempt_stop
+ENTRY(ret_from_intr)
+ move why, #0 ! not system call
+
+/*
+ * judge Kernel or user mode
+ *
+ */
+ lwi $p0, [$sp+(#IPSW_OFFSET)] ! Check if in nested interrupt
+ andi $p0, $p0, #PSW_mskINTL
+ bnez $p0, resume_kernel ! done with iret
+ j resume_userspace
+
+
+/*
+ * This is the fast syscall return path. We do as little as
+ * possible here, and this includes saving $r0 back into the SVC
+ * stack.
+ * fixed: tsk - $r25, why - $r8, $r7 - syscall #, $r8 - syscall table pointer
+ */
+ENTRY(ret_fast_syscall)
+ gie_disable
+ lwi $r1, [tsk+#TSK_TI_FLAGS]
+ andi $p1, $r1, #_TIF_WORK_MASK
+ bnez $p1, fast_work_pending
+ fast_restore_user_regs ! iret
+
+/*
+ * Ok, we need to do extra processing,
+ * enter the slow path returning from syscall, while pending work.
+ */
+fast_work_pending:
+ swi $r0, [$sp+(#R0_OFFSET)] ! what is different from ret_from_exception
+work_pending:
+ andi $p1, $r1, #_TIF_NEED_RESCHED
+ bnez $p1, work_resched
+
+ andi $p1, $r1, #_TIF_SIGPENDING|#_TIF_NOTIFY_RESUME
+ beqz $p1, no_work_pending
+
+ move $r0, $sp ! 'regs'
+ move $r2, why
+ gie_enable
+ bal do_notify_resume
+ beqz $r0, ret_slow_syscall
+ bgtz $r0, 1f
+ lmw.bi $r0, [sp], $r5
+ movi $r7, #__NR_restart_syscall
+1:
+ b eh_syscall_phase_2
+work_resched:
+ bal schedule ! path, return to user mode
+
+/*
+ * "slow" syscall return path.
+ * "why" tells us if this was a real syscall.
+ */
+ENTRY(resume_userspace)
+ENTRY(ret_slow_syscall)
+ gie_disable
+ lwi $p0, [$sp+(#IPSW_OFFSET)] ! Check if in nested interrupt
+ andi $p0, $p0, #PSW_mskINTL
+ bnez $p0, no_work_pending ! done with iret
+ lwi $r1, [tsk+#TSK_TI_FLAGS]
+ andi $p1, $r1, #_TIF_WORK_MASK
+ bnez $p1, work_pending ! handle work_resched, sig_pend
+
+no_work_pending:
+#ifdef CONFIG_TRACE_IRQFLAGS
+ lwi $p0, [$sp+(#IPSW_OFFSET)]
+ andi $p0, $p0, #0x1
+ la $r10, trace_hardirqs_off
+ la $r9, trace_hardirqs_on
+ cmovz $r9, $p0, $r10
+ jral $r9
+#endif
+ restore_user_regs ! return from iret
+
+
+/*
+ * preemptive kernel
+ */
+#ifdef CONFIG_PREEMPT
+resume_kernel:
+ gie_disable
+ lwi $t0, [tsk+#TSK_TI_PREEMPT]
+ bnez $t0, no_work_pending
+need_resched:
+ lwi $t0, [tsk+#TSK_TI_FLAGS]
+ andi $p1, $t0, #_TIF_NEED_RESCHED
+ beqz $p1, no_work_pending
+
+ lwi $t0, [$sp+(#IPSW_OFFSET)] ! Interrupts off?
+ andi $t0, $t0, #1
+ beqz $t0, no_work_pending
+
+ jal preempt_schedule_irq
+ b need_resched
+#endif
+
+/*
+ * This is how we return from a fork.
+ */
+ENTRY(ret_from_fork)
+ bal schedule_tail
+ beqz $r6, 1f ! r6 stores fn for kernel thread
+ move $r0, $r7 ! prepare kernel thread arg
+ jral $r6
+1:
+ lwi $r1, [tsk+#TSK_TI_FLAGS] ! check for syscall tracing
+ move why, #1
+ andi $p1, $r1, #_TIF_WORK_SYSCALL_LEAVE ! are we tracing syscalls?
+ beqz $p1, ret_slow_syscall
+ move $r0, $sp
+ bal syscall_trace_leave
+ b ret_slow_syscall
diff --git a/arch/nds32/kernel/stacktrace.c b/arch/nds32/kernel/stacktrace.c
new file mode 100644
index 0000000..78e816d
--- /dev/null
+++ b/arch/nds32/kernel/stacktrace.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/sched/debug.h>
+#include <linux/sched/task_stack.h>
+#include <linux/stacktrace.h>
+
+void save_stack_trace(struct stack_trace *trace)
+{
+ save_stack_trace_tsk(current, trace);
+}
+
+void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
+{
+ unsigned long *fpn;
+ int skip = trace->skip;
+ int savesched;
+
+ if (tsk == current) {
+ __asm__ __volatile__("\tori\t%0, $fp, #0\n":"=r"(fpn));
+ savesched = 1;
+ } else {
+ fpn = (unsigned long *)thread_saved_fp(tsk);
+ savesched = 0;
+ }
+
+ while (!kstack_end(fpn) && !((unsigned long)fpn & 0x3)
+ && (fpn >= (unsigned long *)TASK_SIZE)) {
+ unsigned long lpp, fpp;
+
+ lpp = fpn[-1];
+ fpp = fpn[FP_OFFSET];
+ if (!__kernel_text_address(lpp))
+ break;
+
+ if (savesched || !in_sched_functions(lpp)) {
+ if (skip) {
+ skip--;
+ } else {
+ trace->entries[trace->nr_entries++] = lpp;
+ if (trace->nr_entries >= trace->max_entries)
+ break;
+ }
+ }
+ fpn = (unsigned long *)fpp;
+ }
+}
diff --git a/arch/nds32/kernel/traps.c b/arch/nds32/kernel/traps.c
new file mode 100644
index 0000000..1680d29
--- /dev/null
+++ b/arch/nds32/kernel/traps.c
@@ -0,0 +1,441 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/personality.h>
+#include <linux/kallsyms.h>
+#include <linux/hardirq.h>
+#include <linux/kdebug.h>
+#include <linux/sched/task_stack.h>
+
+#include <asm/cacheflush.h>
+#include <asm/uaccess.h>
+#include <asm/unistd.h>
+
+#include <linux/ptrace.h>
+#include <nds32_intrinsic.h>
+
+extern void show_pte(struct mm_struct *mm, unsigned long addr);
+
+/*
+ * Dump out the contents of some memory nicely...
+ */
+void dump_mem(const char *lvl, unsigned long bottom, unsigned long top)
+{
+ unsigned long first;
+ mm_segment_t fs;
+ int i;
+
+ /*
+ * We need to switch to kernel mode so that we can use __get_user
+ * to safely read from kernel space. Note that we now dump the
+ * code first, just in case the backtrace kills us.
+ */
+ fs = get_fs();
+ set_fs(KERNEL_DS);
+
+ pr_emerg("%s(0x%08lx to 0x%08lx)\n", lvl, bottom, top);
+
+ for (first = bottom & ~31; first < top; first += 32) {
+ unsigned long p;
+ char str[sizeof(" 12345678") * 8 + 1];
+
+ memset(str, ' ', sizeof(str));
+ str[sizeof(str) - 1] = '\0';
+
+ for (p = first, i = 0; i < 8 && p < top; i++, p += 4) {
+ if (p >= bottom && p < top) {
+ unsigned long val;
+ if (__get_user(val, (unsigned long *)p) == 0)
+ sprintf(str + i * 9, " %08lx", val);
+ else
+ sprintf(str + i * 9, " ????????");
+ }
+ }
+ pr_emerg("%s%04lx:%s\n", lvl, first & 0xffff, str);
+ }
+
+ set_fs(fs);
+}
+
+EXPORT_SYMBOL(dump_mem);
+
+static void dump_instr(struct pt_regs *regs)
+{
+ unsigned long addr = instruction_pointer(regs);
+ mm_segment_t fs;
+ char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
+ int i;
+
+ return;
+ /*
+ * We need to switch to kernel mode so that we can use __get_user
+ * to safely read from kernel space. Note that we now dump the
+ * code first, just in case the backtrace kills us.
+ */
+ fs = get_fs();
+ set_fs(KERNEL_DS);
+
+ pr_emerg("Code: ");
+ for (i = -4; i < 1; i++) {
+ unsigned int val, bad;
+
+ bad = __get_user(val, &((u32 *) addr)[i]);
+
+ if (!bad) {
+ p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val);
+ } else {
+ p += sprintf(p, "bad PC value");
+ break;
+ }
+ }
+ pr_emerg("Code: %s\n", str);
+
+ set_fs(fs);
+}
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+#include <linux/ftrace.h>
+static void
+get_real_ret_addr(unsigned long *addr, struct task_struct *tsk, int *graph)
+{
+ if (*addr == (unsigned long)return_to_handler) {
+ int index = tsk->curr_ret_stack;
+
+ if (tsk->ret_stack && index >= *graph) {
+ index -= *graph;
+ *addr = tsk->ret_stack[index].ret;
+ (*graph)++;
+ }
+ }
+}
+#else
+static inline void
+get_real_ret_addr(unsigned long *addr, struct task_struct *tsk, int *graph)
+{
+}
+#endif
+
+#define LOOP_TIMES (100)
+static void __dump(struct task_struct *tsk, unsigned long *base_reg)
+{
+ unsigned long ret_addr;
+ int cnt = LOOP_TIMES, graph = 0;
+ pr_emerg("Call Trace:\n");
+ if (!IS_ENABLED(CONFIG_FRAME_POINTER)) {
+ while (!kstack_end(base_reg)) {
+ ret_addr = *base_reg++;
+ if (__kernel_text_address(ret_addr)) {
+ get_real_ret_addr(&ret_addr, tsk, &graph);
+ print_ip_sym(ret_addr);
+ }
+ if (--cnt < 0)
+ break;
+ }
+ } else {
+ while (!kstack_end((void *)base_reg) &&
+ !((unsigned long)base_reg & 0x3) &&
+ ((unsigned long)base_reg >= TASK_SIZE)) {
+ unsigned long next_fp;
+#if !defined(NDS32_ABI_2)
+ ret_addr = base_reg[0];
+ next_fp = base_reg[1];
+#else
+ ret_addr = base_reg[-1];
+ next_fp = base_reg[FP_OFFSET];
+#endif
+ if (__kernel_text_address(ret_addr)) {
+ get_real_ret_addr(&ret_addr, tsk, &graph);
+ print_ip_sym(ret_addr);
+ }
+ if (--cnt < 0)
+ break;
+ base_reg = (unsigned long *)next_fp;
+ }
+ }
+ pr_emerg("\n");
+}
+
+void dump_stack(void)
+{
+ unsigned long *base_reg;
+ if (!IS_ENABLED(CONFIG_FRAME_POINTER))
+ __asm__ __volatile__("\tori\t%0, $sp, #0\n":"=r"(base_reg));
+ else
+ __asm__ __volatile__("\tori\t%0, $fp, #0\n":"=r"(base_reg));
+ __dump(NULL, base_reg);
+}
+
+EXPORT_SYMBOL(dump_stack);
+
+void show_stack(struct task_struct *tsk, unsigned long *sp)
+{
+ unsigned long *base_reg;
+
+ if (!tsk)
+ tsk = current;
+ if (!IS_ENABLED(CONFIG_FRAME_POINTER)) {
+ if (tsk != current)
+ base_reg = (unsigned long *)(tsk->thread.cpu_context.sp);
+ else
+ __asm__ __volatile__("\tori\t%0, $sp, #0\n":"=r"(base_reg));
+ } else {
+ if (tsk != current)
+ base_reg = (unsigned long *)(tsk->thread.cpu_context.fp);
+ else
+ __asm__ __volatile__("\tori\t%0, $fp, #0\n":"=r"(base_reg));
+ }
+ __dump(tsk, base_reg);
+ barrier();
+}
+
+DEFINE_SPINLOCK(die_lock);
+
+/*
+ * This function is protected against re-entrancy.
+ */
+void die(const char *str, struct pt_regs *regs, int err)
+{
+ struct task_struct *tsk = current;
+ static int die_counter;
+
+ console_verbose();
+ spin_lock_irq(&die_lock);
+ bust_spinlocks(1);
+
+ pr_emerg("Internal error: %s: %x [#%d]\n", str, err, ++die_counter);
+ print_modules();
+ pr_emerg("CPU: %i\n", smp_processor_id());
+ show_regs(regs);
+ pr_emerg("Process %s (pid: %d, stack limit = 0x%p)\n",
+ tsk->comm, tsk->pid, task_thread_info(tsk) + 1);
+
+ if (!user_mode(regs) || in_interrupt()) {
+ dump_mem("Stack: ", regs->sp,
+ THREAD_SIZE + (unsigned long)task_thread_info(tsk));
+ dump_instr(regs);
+ dump_stack();
+ }
+
+ bust_spinlocks(0);
+ spin_unlock_irq(&die_lock);
+ do_exit(SIGSEGV);
+}
+
+EXPORT_SYMBOL(die);
+
+void die_if_kernel(const char *str, struct pt_regs *regs, int err)
+{
+ if (user_mode(regs))
+ return;
+
+ die(str, regs, err);
+}
+
+int bad_syscall(int n, struct pt_regs *regs)
+{
+ siginfo_t info;
+
+ if (current->personality != PER_LINUX) {
+ send_sig(SIGSEGV, current, 1);
+ return regs->uregs[0];
+ }
+
+ info.si_signo = SIGILL;
+ info.si_errno = 0;
+ info.si_code = ILL_ILLTRP;
+ info.si_addr = (void __user *)instruction_pointer(regs) - 4;
+
+ force_sig_info(SIGILL, &info, current);
+ die_if_kernel("Oops - bad syscall", regs, n);
+ return regs->uregs[0];
+}
+
+void __pte_error(const char *file, int line, unsigned long val)
+{
+ pr_emerg("%s:%d: bad pte %08lx.\n", file, line, val);
+}
+
+void __pmd_error(const char *file, int line, unsigned long val)
+{
+ pr_emerg("%s:%d: bad pmd %08lx.\n", file, line, val);
+}
+
+void __pgd_error(const char *file, int line, unsigned long val)
+{
+ pr_emerg("%s:%d: bad pgd %08lx.\n", file, line, val);
+}
+
+extern char *exception_vector, *exception_vector_end;
+void __init trap_init(void)
+{
+ return;
+}
+
+void __init early_trap_init(void)
+{
+ unsigned long ivb = 0;
+ unsigned long base = PAGE_OFFSET;
+
+ memcpy((unsigned long *)base, (unsigned long *)&exception_vector,
+ ((unsigned long)&exception_vector_end -
+ (unsigned long)&exception_vector));
+ ivb = __nds32__mfsr(NDS32_SR_IVB);
+ /* Check platform support. */
+ if (((ivb & IVB_mskNIVIC) >> IVB_offNIVIC) < 2)
+ panic
+ ("IVIC mode is not allowed on the platform with interrupt controller\n");
+ __nds32__mtsr((ivb & ~IVB_mskESZ) | (IVB_valESZ16 << IVB_offESZ) |
+ IVB_BASE, NDS32_SR_IVB);
+ __nds32__mtsr(INT_MASK_INITAIAL_VAL, NDS32_SR_INT_MASK);
+
+ /*
+ * 0x800 = 128 vectors * 16byte.
+ * It should be enough to flush a page.
+ */
+ flush_icache_range(base, base + PAGE_SIZE);
+}
+
+void do_debug_trap(unsigned long entry, unsigned long addr,
+ unsigned long type, struct pt_regs *regs)
+{
+ if (notify_die(DIE_OOPS, "Oops", regs, addr, type, SIGTRAP)
+ == NOTIFY_STOP)
+ return;
+
+ if (user_mode(regs)) {
+ /* trap_signal */
+ send_sigtrap(current, regs, 0, TRAP_BRKPT);
+ } else {
+ /* kernel_trap */
+ if (!fixup_exception(regs))
+ die("unexpected kernel_trap", regs, 0);
+ }
+}
+
+void unhandled_interruption(struct pt_regs *regs)
+{
+ siginfo_t si;
+ pr_emerg("unhandled_interruption\n");
+ show_regs(regs);
+ if (!user_mode(regs))
+ do_exit(SIGKILL);
+ si.si_signo = SIGKILL;
+ si.si_errno = 0;
+ force_sig_info(SIGKILL, &si, current);
+}
+
+void unhandled_exceptions(unsigned long entry, unsigned long addr,
+ unsigned long type, struct pt_regs *regs)
+{
+ siginfo_t si;
+ pr_emerg("Unhandled Exception: entry: %lx addr:%lx itype:%lx\n", entry,
+ addr, type);
+ show_regs(regs);
+ if (!user_mode(regs))
+ do_exit(SIGKILL);
+ si.si_signo = SIGKILL;
+ si.si_errno = 0;
+ si.si_addr = (void *)addr;
+ force_sig_info(SIGKILL, &si, current);
+}
+
+extern int do_page_fault(unsigned long entry, unsigned long addr,
+ unsigned int error_code, struct pt_regs *regs);
+
+/*
+ * 2:DEF dispatch for TLB MISC exception handler
+*/
+
+void do_dispatch_tlb_misc(unsigned long entry, unsigned long addr,
+ unsigned long type, struct pt_regs *regs)
+{
+ type = type & (ITYPE_mskINST | ITYPE_mskETYPE);
+ if ((type & ITYPE_mskETYPE) < 5) {
+ /* Permission exceptions */
+ do_page_fault(entry, addr, type, regs);
+ } else
+ unhandled_exceptions(entry, addr, type, regs);
+}
+
+void do_revinsn(struct pt_regs *regs)
+{
+ siginfo_t si;
+ pr_emerg("Reserved Instruction\n");
+ show_regs(regs);
+ if (!user_mode(regs))
+ do_exit(SIGILL);
+ si.si_signo = SIGILL;
+ si.si_errno = 0;
+ force_sig_info(SIGILL, &si, current);
+}
+
+#ifdef CONFIG_ALIGNMENT_TRAP
+extern int unalign_access_mode;
+extern int do_unaligned_access(unsigned long entry, unsigned long addr,
+ unsigned long type, struct pt_regs *regs);
+#endif
+void do_dispatch_general(unsigned long entry, unsigned long addr,
+ unsigned long itype, struct pt_regs *regs,
+ unsigned long oipc)
+{
+ unsigned int swid = itype >> ITYPE_offSWID;
+ unsigned long type = itype & (ITYPE_mskINST | ITYPE_mskETYPE);
+ if (type == ETYPE_ALIGNMENT_CHECK) {
+#ifdef CONFIG_ALIGNMENT_TRAP
+ /* Alignment check */
+ if (unalign_access_mode & 0x3) {
+ int ret;
+ ret = do_unaligned_access(entry, addr, type, regs);
+
+ if (ret == 0)
+ return;
+
+ if (ret == -EFAULT)
+ pr_emerg
+ ("Unhandled unaligned access exception\n");
+ }
+#endif
+ do_page_fault(entry, addr, type, regs);
+ } else if (type == ETYPE_RESERVED_INSTRUCTION) {
+ /* Reserved instruction */
+ do_revinsn(regs);
+ } else if (type == ETYPE_TRAP && swid == SWID_RAISE_INTERRUPT_LEVEL) {
+ /* trap, used on v3 EDM target debugging workaround */
+ /*
+ * DIPC(OIPC) is passed as parameter before
+ * interrupt is enabled, so the DIPC will not be corrupted
+ * even though interrupts are coming in
+ */
+ /*
+ * 1. update ipc
+ * 2. update pt_regs ipc with oipc
+ * 3. update pt_regs ipsw (clear DEX)
+ */
+ __asm__ volatile ("mtsr %0, $IPC\n\t"::"r" (oipc));
+ regs->ipc = oipc;
+ if (regs->pipsw & PSW_mskDEX) {
+ pr_emerg
+ ("Nested Debug exception is possibly happened\n");
+ pr_emerg("ipc:%08x pipc:%08x\n",
+ (unsigned int)regs->ipc,
+ (unsigned int)regs->pipc);
+ }
+ do_debug_trap(entry, addr, itype, regs);
+ regs->ipsw &= ~PSW_mskDEX;
+ } else
+ unhandled_exceptions(entry, addr, type, regs);
+}
diff --git a/arch/nds32/mm/alignment.c b/arch/nds32/mm/alignment.c
new file mode 100644
index 0000000..19aba59
--- /dev/null
+++ b/arch/nds32/mm/alignment.c
@@ -0,0 +1,622 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/proc_fs.h>
+#include <linux/uaccess.h>
+#include <linux/sysctl.h>
+#include <asm/unaligned.h>
+
+#define DEBUG(enable, tagged, ...) \
+ do{ \
+ if (enable) { \
+ if (tagged) \
+ pr_warn("[ %30s() ] ", __func__); \
+ pr_warn(__VA_ARGS__); \
+ } \
+ } while (0)
+
+#define RT(inst) (((inst) >> 20) & 0x1FUL)
+#define RA(inst) (((inst) >> 15) & 0x1FUL)
+#define RB(inst) (((inst) >> 10) & 0x1FUL)
+#define SV(inst) (((inst) >> 8) & 0x3UL)
+#define IMM(inst) (((inst) >> 0) & 0x3FFFUL)
+
+#define RA3(inst) (((inst) >> 3) & 0x7UL)
+#define RT3(inst) (((inst) >> 6) & 0x7UL)
+#define IMM3U(inst) (((inst) >> 0) & 0x7UL)
+
+#define RA5(inst) (((inst) >> 0) & 0x1FUL)
+#define RT4(inst) (((inst) >> 5) & 0xFUL)
+
+#define __get8_data(val,addr,err) \
+ __asm__( \
+ "1: lbi.bi %1, [%2], #1\n" \
+ "2:\n" \
+ " .pushsection .text.fixup,\"ax\"\n" \
+ " .align 2\n" \
+ "3: movi %0, #1\n" \
+ " j 2b\n" \
+ " .popsection\n" \
+ " .pushsection __ex_table,\"a\"\n" \
+ " .align 3\n" \
+ " .long 1b, 3b\n" \
+ " .popsection\n" \
+ : "=r" (err), "=&r" (val), "=r" (addr) \
+ : "0" (err), "2" (addr))
+
+#define get16_data(addr, val_ptr) \
+ do { \
+ unsigned int err = 0, v, a = addr; \
+ __get8_data(v,a,err); \
+ *val_ptr = v << 0; \
+ __get8_data(v,a,err); \
+ *val_ptr |= v << 8; \
+ if (err) \
+ goto fault; \
+ *val_ptr = le16_to_cpu(*val_ptr); \
+ } while(0)
+
+#define get32_data(addr, val_ptr) \
+ do { \
+ unsigned int err = 0, v, a = addr; \
+ __get8_data(v,a,err); \
+ *val_ptr = v << 0; \
+ __get8_data(v,a,err); \
+ *val_ptr |= v << 8; \
+ __get8_data(v,a,err); \
+ *val_ptr |= v << 16; \
+ __get8_data(v,a,err); \
+ *val_ptr |= v << 24; \
+ if (err) \
+ goto fault; \
+ *val_ptr = le32_to_cpu(*val_ptr); \
+ } while(0)
+
+#define get_data(addr, val_ptr, len) \
+ if (len == 2) \
+ get16_data(addr, val_ptr); \
+ else \
+ get32_data(addr, val_ptr);
+
+
+#define set16_data(addr, val) \
+ do { \
+ unsigned int err = 0, *ptr = addr ; \
+ val = le32_to_cpu(val); \
+ __asm__( \
+ "1: sbi.bi %2, [%1], #1\n" \
+ " srli %2, %2, #8\n" \
+ "2: sbi %2, [%1]\n" \
+ "3:\n" \
+ " .pushsection .text.fixup,\"ax\"\n" \
+ " .align 2\n" \
+ "4: movi %0, #1\n" \
+ " j 3b\n" \
+ " .popsection\n" \
+ " .pushsection __ex_table,\"a\"\n" \
+ " .align 3\n" \
+ " .long 1b, 4b\n" \
+ " .long 2b, 4b\n" \
+ " .popsection\n" \
+ : "=r" (err), "+r" (ptr), "+r" (val) \
+ : "0" (err) \
+ ); \
+ if (err) \
+ goto fault; \
+ } while(0)
+
+#define set32_data(addr, val) \
+ do { \
+ unsigned int err = 0, *ptr = addr ; \
+ val = le32_to_cpu(val); \
+ __asm__( \
+ "1: sbi.bi %2, [%1], #1\n" \
+ " srli %2, %2, #8\n" \
+ "2: sbi.bi %2, [%1], #1\n" \
+ " srli %2, %2, #8\n" \
+ "3: sbi.bi %2, [%1], #1\n" \
+ " srli %2, %2, #8\n" \
+ "4: sbi %2, [%1]\n" \
+ "5:\n" \
+ " .pushsection .text.fixup,\"ax\"\n" \
+ " .align 2\n" \
+ "6: movi %0, #1\n" \
+ " j 5b\n" \
+ " .popsection\n" \
+ " .pushsection __ex_table,\"a\"\n" \
+ " .align 3\n" \
+ " .long 1b, 6b\n" \
+ " .long 2b, 6b\n" \
+ " .long 3b, 6b\n" \
+ " .long 4b, 6b\n" \
+ " .popsection\n" \
+ : "=r" (err), "+r" (ptr), "+r" (val) \
+ : "0" (err) \
+ ); \
+ if (err) \
+ goto fault; \
+ } while(0)
+#define set_data(addr, val, len) \
+ if (len == 2) \
+ set16_data(addr, val); \
+ else \
+ set32_data(addr, val);
+extern pte_t va_present(struct mm_struct *mm, unsigned long addr);
+extern pte_t va_kernel_present(unsigned long addr);
+extern int va_readable(struct pt_regs *regs, unsigned long addr);
+extern int va_writable(struct pt_regs *regs, unsigned long addr);
+
+int unalign_access_mode = 0, unalign_access_debug = 0;
+
+static inline unsigned long *idx_to_addr(struct pt_regs *regs, int idx)
+{
+ /* this should be consistent with ptrace.h */
+ if (idx >= 0 && idx <= 25) /* R0-R25 */
+ return ®s->uregs[0] + idx;
+ else if (idx >= 28 && idx <= 30) /* FP, GP, LP */
+ return ®s->fp + (idx - 28);
+ else if (idx == 31) /* SP */
+ return ®s->sp;
+ else
+ return NULL; /* cause a segfault */
+}
+
+static inline unsigned long get_inst(unsigned long addr)
+{
+ return be32_to_cpu(get_unaligned((u32 *) addr));
+}
+
+
+static inline unsigned long sign_extend(unsigned long val, int len)
+{
+ unsigned long ret = 0;
+ unsigned char *s, *t;
+ int i = 0;
+
+ val = cpu_to_le32(val);
+
+ s = (void *)&val;
+ t = (void *)&ret;
+
+ while (i++ < len)
+ *t++ = *s++;
+
+ if (((*(t - 1)) & 0x80) && (i < 4)) {
+
+ while (i++ <= 4)
+ *t++ = 0xff;
+ }
+
+ return le32_to_cpu(ret);
+}
+
+static inline int do_16(unsigned long inst, struct pt_regs *regs)
+{
+ int imm, regular, load, len, addr_mode, idx_mode;
+ unsigned long unaligned_addr, target_val, source_idx, target_idx,
+ shift = 0;
+ switch ((inst >> 9) & 0x3F) {
+
+ case 0x12: /* LHI333 */
+ imm = 1;
+ regular = 1;
+ load = 1;
+ len = 2;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x10: /* LWI333 */
+ imm = 1;
+ regular = 1;
+ load = 1;
+ len = 4;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x11: /* LWI333.bi */
+ imm = 1;
+ regular = 0;
+ load = 1;
+ len = 4;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x1A: /* LWI450 */
+ imm = 0;
+ regular = 1;
+ load = 1;
+ len = 4;
+ addr_mode = 5;
+ idx_mode = 4;
+ break;
+ case 0x16: /* SHI333 */
+ imm = 1;
+ regular = 1;
+ load = 0;
+ len = 2;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x14: /* SWI333 */
+ imm = 1;
+ regular = 1;
+ load = 0;
+ len = 4;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x15: /* SWI333.bi */
+ imm = 1;
+ regular = 0;
+ load = 0;
+ len = 4;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x1B: /* SWI450 */
+ imm = 0;
+ regular = 1;
+ load = 0;
+ len = 4;
+ addr_mode = 5;
+ idx_mode = 4;
+ break;
+
+ default:
+ return -EFAULT;
+ }
+
+ if (addr_mode == 3) {
+ unaligned_addr = *idx_to_addr(regs, RA3(inst));
+ source_idx = RA3(inst);
+ } else {
+ unaligned_addr = *idx_to_addr(regs, RA5(inst));
+ source_idx = RA5(inst);
+ }
+
+ if (idx_mode == 3)
+ target_idx = RT3(inst);
+ else
+ target_idx = RT4(inst);
+
+ if (imm)
+ shift = IMM3U(inst) * len;
+
+ if (regular)
+ unaligned_addr += shift;
+
+ if (load) {
+ if (!access_ok(VERIFY_READ, (void *)unaligned_addr, len))
+ return -EACCES;
+
+ get_data(unaligned_addr,&target_val,len);
+ *idx_to_addr(regs, target_idx) = target_val;
+ } else {
+ if (!access_ok(VERIFY_WRITE, (void *)unaligned_addr, len))
+ return -EACCES;
+ target_val = *idx_to_addr(regs, target_idx);
+ set_data((void *)unaligned_addr, target_val, len);
+ }
+
+ if(!regular)
+ *idx_to_addr(regs, source_idx) = unaligned_addr + shift;
+ regs->ipc += 2;
+
+ return 0;
+fault:
+ return -EACCES;
+}
+
+static inline int do_32(unsigned long inst, struct pt_regs *regs)
+{
+ int imm, regular, load, len, sign_ext;
+ unsigned long unaligned_addr, target_val, shift;
+
+ unaligned_addr = *idx_to_addr(regs, RA(inst));
+
+ switch ((inst >> 25) << 1) {
+
+ case 0x02: /* LHI */
+ imm = 1;
+ regular = 1;
+ load = 1;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x0A: /* LHI.bi */
+ imm = 1;
+ regular = 0;
+ load = 1;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x22: /* LHSI */
+ imm = 1;
+ regular = 1;
+ load = 1;
+ len = 2;
+ sign_ext = 1;
+ break;
+ case 0x2A: /* LHSI.bi */
+ imm = 1;
+ regular = 0;
+ load = 1;
+ len = 2;
+ sign_ext = 1;
+ break;
+ case 0x04: /* LWI */
+ imm = 1;
+ regular = 1;
+ load = 1;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x0C: /* LWI.bi */
+ imm = 1;
+ regular = 0;
+ load = 1;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x12: /* SHI */
+ imm = 1;
+ regular = 1;
+ load = 0;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x1A: /* SHI.bi */
+ imm = 1;
+ regular = 0;
+ load = 0;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x14: /* SWI */
+ imm = 1;
+ regular = 1;
+ load = 0;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x1C: /* SWI.bi */
+ imm = 1;
+ regular = 0;
+ load = 0;
+ len = 4;
+ sign_ext = 0;
+ break;
+
+ default:
+ switch (inst & 0xff) {
+
+ case 0x01: /* LH */
+ imm = 0;
+ regular = 1;
+ load = 1;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x05: /* LH.bi */
+ imm = 0;
+ regular = 0;
+ load = 1;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x11: /* LHS */
+ imm = 0;
+ regular = 1;
+ load = 1;
+ len = 2;
+ sign_ext = 1;
+ break;
+ case 0x15: /* LHS.bi */
+ imm = 0;
+ regular = 0;
+ load = 1;
+ len = 2;
+ sign_ext = 1;
+ break;
+ case 0x02: /* LW */
+ imm = 0;
+ regular = 1;
+ load = 1;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x06: /* LW.bi */
+ imm = 0;
+ regular = 0;
+ load = 1;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x09: /* SH */
+ imm = 0;
+ regular = 1;
+ load = 0;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x0D: /* SH.bi */
+ imm = 0;
+ regular = 0;
+ load = 0;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x0A: /* SW */
+ imm = 0;
+ regular = 1;
+ load = 0;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x0E: /* SW.bi */
+ imm = 0;
+ regular = 0;
+ load = 0;
+ len = 4;
+ sign_ext = 0;
+ break;
+
+ default:
+ return -EFAULT;
+ }
+ }
+
+ if (imm)
+ shift = IMM(inst) * len;
+ else
+ shift = *idx_to_addr(regs, RB(inst)) << SV(inst);
+
+
+ if (regular)
+ unaligned_addr += shift;
+
+ if (load) {
+
+ if (!access_ok(VERIFY_READ, (void *)unaligned_addr, len))
+ return -EACCES;
+
+ get_data(unaligned_addr,&target_val,len);
+
+ if (sign_ext)
+ *idx_to_addr(regs, RT(inst)) =
+ sign_extend(target_val, len);
+ else
+ *idx_to_addr(regs, RT(inst)) = target_val;
+ } else {
+
+ if (!access_ok(VERIFY_WRITE, (void *)unaligned_addr, len))
+ return -EACCES;
+
+ target_val = *idx_to_addr(regs, RT(inst));
+ set_data((void *)unaligned_addr, target_val, len);
+ }
+
+ if(!regular)
+ *idx_to_addr(regs, RA(inst)) = unaligned_addr + shift;
+
+ regs->ipc += 4;
+
+ return 0;
+fault:
+ return -EACCES;
+}
+
+int do_unaligned_access(unsigned long entry, unsigned long addr,
+ unsigned long type, struct pt_regs *regs)
+{
+ unsigned long inst;
+ int ret = -EFAULT;
+
+ inst = get_inst(regs->ipc);
+
+ DEBUG((unalign_access_debug > 0), 1,
+ "Faulting addr: 0x%08lx, pc: 0x%08lx [inst: 0x%08lx ]\n"
+ "unalign_access_mode: %x\n"
+ , addr,regs->ipc, inst, unalign_access_mode);
+
+ if ((user_mode(regs) && (unalign_access_mode & 0x01))
+ || (!user_mode(regs) && (unalign_access_mode & 0x02))) {
+
+ mm_segment_t seg = get_fs();
+
+ user_mode(regs)?set_fs(USER_DS):set_fs(KERNEL_DS);
+
+ if (inst & 0x80000000)
+ {
+ ret = do_16((inst >> 16) & 0xffff, regs);
+ }
+ else
+ {
+ ret = do_32(inst, regs);
+ }
+ set_fs(seg);
+ }
+
+ return ret;
+}
+
+#ifdef CONFIG_PROC_FS
+
+static
+int unalign_access_policy(struct ctl_table *ctl, int write,
+ void __user * buffer, size_t * lenp, loff_t * ppos)
+{
+ int val = *(int *)(ctl->data);
+ loff_t pos = *ppos;
+ struct ctl_table lctl;
+ int ret;
+
+ lctl = *ctl;
+ lctl.data = &val;
+ ret = proc_dointvec(&lctl, write, buffer, lenp, ppos);
+
+ if (ret)
+ *ppos = pos;
+ else {
+ *(int *)ctl->data = val;
+ if (val > 3)
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static struct ctl_table alignment_tbl[3] = {
+ {
+ .procname = "enable_mode",
+ .data = &unalign_access_mode,
+ .maxlen = sizeof(unalign_access_mode),
+ .mode = 0666,
+ .proc_handler = unalign_access_policy,
+ },
+ {
+ .procname = "debug",
+ .data = &unalign_access_debug,
+ .maxlen = sizeof(unalign_access_mode),
+ .mode = 0644,
+ .proc_handler = &proc_dointvec
+ },
+ {}
+};
+
+static struct ctl_table nds32_sysctl_table[2] = {
+ {
+ .procname = "unaligned_acess",
+ .mode = 0555,
+ .child = alignment_tbl},
+ {}
+};
+static struct ctl_path nds32_path[2] = {
+ {.procname = "nds32" },
+ {}
+};
+
+/*
+ * Initialize nds32 alignment-correction interface
+ */
+static int __init nds32_sysctl_init(void)
+{
+ register_sysctl_paths(nds32_path, nds32_sysctl_table);
+ return 0;
+}
+
+__initcall(nds32_sysctl_init);
+#endif /* CONFIG_PROC_FS */
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 02/35] nds32: Kernel booting and initialization
From: Greentime Hu @ 2017-11-27 12:27 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial
Cc: green.hu, Vincent Chen
In-Reply-To: <cover.1511785528.git.green.hu@gmail.com>
From: Greentime Hu <greentime@andestech.com>
This patch includes the kernel startup code. It can get dtb pointer
passed from bootloader. It will create a temp mapping by tlb
instructions at beginning and goto start_kernel.
Signed-off-by: Vincent Chen <vincentc@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
---
arch/nds32/kernel/head.S | 198 ++++++++++++++++++++++
arch/nds32/kernel/setup.c | 407 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 605 insertions(+)
create mode 100644 arch/nds32/kernel/head.S
create mode 100644 arch/nds32/kernel/setup.c
diff --git a/arch/nds32/kernel/head.S b/arch/nds32/kernel/head.S
new file mode 100644
index 0000000..bdf6a1a
--- /dev/null
+++ b/arch/nds32/kernel/head.S
@@ -0,0 +1,198 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/ptrace.h>
+#include <asm/asm-offsets.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/l2_cache.h>
+#include <asm/sizes.h>
+#include <asm/thread_info.h>
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define OF_DT_MAGIC 0xd00dfeed
+#else
+#define OF_DT_MAGIC 0xedfe0dd0
+#endif
+
+ .globl swapper_pg_dir
+ .equ swapper_pg_dir, TEXTADDR - 0x4000
+
+/*
+ * Kernel startup entry point.
+ */
+ .section ".head.text", "ax"
+ .type _stext, %function
+ENTRY(_stext)
+ setgie.d ! Disable interrupt
+ isb
+/*
+ * Disable I/D-cache and enable it at a proper time
+ */
+ mfsr $r0, $mr8
+ li $r1, #~(CACHE_CTL_mskIC_EN|CACHE_CTL_mskDC_EN)
+ and $r0, $r0, $r1
+ mtsr $r0, $mr8
+
+/*
+ * Process device tree blob
+ */
+ andi $r0,$r2,#0x3
+ li $r10, 0
+ bne $r0, $r10, _nodtb
+ lwi $r0, [$r2]
+ li $r1, OF_DT_MAGIC
+ bne $r0, $r1, _nodtb
+ move $r10, $r2
+_nodtb:
+
+/*
+ * Create a temporary mapping area for booting, before start_kernel
+ */
+ sethi $r4, hi20(swapper_pg_dir)
+ li $p0, (PAGE_OFFSET - PHYS_OFFSET)
+ sub $r4, $r4, $p0
+ tlbop FlushAll ! invalidate TLB\n"
+ isb
+ mtsr $r4, $L1_PPTB ! load page table pointer\n"
+
+/* set NTC0 cacheable/writeback, mutliple page size in use */
+ mfsr $r3, $MMU_CTL
+ li $r0, #~MMU_CTL_mskNTC0
+ and $r3, $r3, $r0
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+ ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << MMU_CTL_offNTC0))
+#else
+ ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << MMU_CTL_offNTC0)|MMU_CTL_mskD)
+#endif
+ mtsr $r3, $MMU_CTL
+ isb
+
+/* set page size and size of kernel image */
+ mfsr $r0, $MMU_CFG
+ srli $r3, $r0, MMU_CFG_offfEPSZ
+ zeb $r3, $r3
+ bnez $r3, _extra_page_size_support
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+ li $r5, #SZ_4K ! Use 4KB page size
+#else
+ li $r5, #SZ_8K ! Use 8KB page size
+ li $r3, #1
+#endif
+ mtsr $r3, $TLB_MISC
+ b _image_size_check
+
+_extra_page_size_support: ! Use epzs pages size
+ clz $r6, $r3
+ subri $r2, $r6, #31
+ li $r3, #1
+ sll $r3, $r3, $r2
+ /* MMU_CFG.EPSZ value -> meaning */
+ mul $r5, $r3, $r3
+ slli $r5, $r5, #14
+ /* MMU_CFG.EPSZ -> TLB_MISC.ACC_PSZ */
+ addi $r3, $r2, #0x2
+ mtsr $r3, $TLB_MISC
+
+_image_size_check:
+ /* calculate the image maximum size accepted by TLB config */
+ andi $r6, $r0, MMU_CFG_mskTBW
+ andi $r0, $r0, MMU_CFG_mskTBS
+ srli $r6, $r6, MMU_CFG_offTBW
+ srli $r0, $r0, MMU_CFG_offTBS
+ /*
+ * we just map the kernel to the maximum way - 1 of tlb
+ * reserver one way for UART VA mapping
+ * it will cause page fault if UART mapping cover the kernel mapping
+ *
+ * direct mapping is not supported now.
+ */
+ li $r2, 't'
+ beqz $r6, __error ! MMU_CFG.TBW = 0 is direct mappin
+ addi $r0, $r0, #0x2 ! MMU_CFG.TBS value -> meaning
+ sll $r0, $r6, $r0 ! entries = k-way * n-set
+ mul $r6, $r0, $r5 ! max size = entries * page size
+ /* check kernel image size */
+ la $r3, (_end - PAGE_OFFSET)
+ li $r2, 's'
+ bgt $r3, $r6, __error
+
+ li $r2, #(PHYS_OFFSET + TLB_DATA_kernel_text_attr)
+ li $r3, PAGE_OFFSET
+ add $r6, $r6, $r3
+
+_tlb:
+ mtsr $r3, $TLB_VPN
+ dsb
+ tlbop $r2, RWR
+ isb
+ add $r3, $r3, $r5
+ add $r2, $r2, $r5
+ bgt $r6, $r3, _tlb
+ mfsr $r3, $TLB_MISC ! setup access page size
+ li $r2, #~0xf
+ and $r3, $r3, $r2
+#ifdef CONFIG_ANDES_PAGE_SIZE_8KB
+ ori $r3, $r3, #0x1
+#endif
+ mtsr $r3, $TLB_MISC
+
+ mfsr $r0, $MISC_CTL ! Enable BTB and RTP and shadow sp
+ ori $r0, $r0, #MISC_init
+ mtsr $r0, $MISC_CTL
+
+ mfsr $p1, $PSW
+ li $r15, #~PSW_clr ! clear WBNA|DME|IME|DT|IT|POM|INTL|GIE
+ and $p1, $p1, $r15
+ ori $p1, $p1, #PSW_init
+ mtsr $p1, $IPSW ! when iret, it will automatically enable MMU
+ la $lp, __mmap_switched
+ mtsr $lp, $IPC
+ iret
+ nop
+
+ .type __switch_data, %object
+__switch_data:
+ .long __bss_start ! $r6
+ .long _end ! $r7
+ .long __atags_pointer ! $atag_pointer
+ .long init_task ! $r9, move to $r25
+ .long init_thread_union + THREAD_SIZE ! $sp
+
+
+/*
+ * The following fragment of code is executed with the MMU on in MMU mode,
+ * and uses absolute addresses; this is not position independent.
+ */
+ .align
+ .type __mmap_switched, %function
+__mmap_switched:
+ la $r3, __switch_data
+ lmw.bim $r6, [$r3], $r9, #0b0001
+ move $r25, $r9
+ move $fp, #0 ! Clear BSS (and zero $fp)
+ beq $r7, $r6, _RRT
+1: swi.bi $fp, [$r6], #4
+ bne $r7, $r6, 1b
+ swi $r10, [$r8]
+
+_RRT:
+ b start_kernel
+
+__error:
+ b __error
diff --git a/arch/nds32/kernel/setup.c b/arch/nds32/kernel/setup.c
new file mode 100644
index 0000000..6253cf2
--- /dev/null
+++ b/arch/nds32/kernel/setup.c
@@ -0,0 +1,407 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/cpu.h>
+#include <linux/bootmem.h>
+#include <linux/seq_file.h>
+#include <linux/memblock.h>
+#include <linux/console.h>
+#include <linux/screen_info.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
+#include <asm/setup.h>
+#include <asm/sections.h>
+#include <asm/proc-fns.h>
+#include <asm/cache_info.h>
+#include <asm/elf.h>
+#include <nds32_intrinsic.h>
+
+#define HWCAP_MFUSR_PC 0x000001
+#define HWCAP_EXT 0x000002
+#define HWCAP_EXT2 0x000004
+#define HWCAP_FPU 0x000008
+#define HWCAP_AUDIO 0x000010
+#define HWCAP_BASE16 0x000020
+#define HWCAP_STRING 0x000040
+#define HWCAP_REDUCED_REGS 0x000080
+#define HWCAP_VIDEO 0x000100
+#define HWCAP_ENCRYPT 0x000200
+#define HWCAP_EDM 0x000400
+#define HWCAP_LMDMA 0x000800
+#define HWCAP_PFM 0x001000
+#define HWCAP_HSMP 0x002000
+#define HWCAP_TRACE 0x004000
+#define HWCAP_DIV 0x008000
+#define HWCAP_MAC 0x010000
+#define HWCAP_L2C 0x020000
+#define HWCAP_FPU_DP 0x040000
+#define HWCAP_V2 0x080000
+#define HWCAP_DX_REGS 0x100000
+
+extern struct mm_struct init_mm;
+unsigned long cpu_id, cpu_rev, cpu_cfgid;
+char cpu_series;
+char *endianness = NULL;
+
+unsigned int __atags_pointer __initdata;
+unsigned int elf_hwcap;
+EXPORT_SYMBOL(elf_hwcap);
+
+extern void __init early_init_devtree(void *params);
+extern void __init early_trap_init(void);
+/*
+ * The following string table, must sync with HWCAP_xx bitmask,
+ * which is defined in <asm/procinfo.h>
+ */
+static const char *hwcap_str[] = {
+ "mfusr_pc",
+ "perf1",
+ "perf2",
+ "fpu",
+ "audio",
+ "16b",
+ "string",
+ "reduced_regs",
+ "video",
+ "encrypt",
+ "edm",
+ "lmdma",
+ "pfm",
+ "hsmp",
+ "trace",
+ "div",
+ "mac",
+ "l2c",
+ "dx_regs",
+ "v2",
+ NULL,
+};
+
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+#define WRITE_METHOD "write through"
+#else
+#define WRITE_METHOD "write back"
+#endif
+
+struct cache_info L1_cache_info[2];
+static void __init dump_cpu_info(int cpu)
+{
+ int i, p = 0;
+ char str[sizeof(hwcap_str) + 16];
+
+ for (i = 0; hwcap_str[i]; i++) {
+ if (elf_hwcap & (1 << i)) {
+ sprintf(str + p, "%s ", hwcap_str[i]);
+ p += strlen(hwcap_str[i]) + 1;
+ }
+ }
+
+ pr_info("CPU%d Featuretures: %s\n", cpu, str);
+
+ L1_cache_info[ICACHE].ways = CACHE_WAY(ICACHE);
+ L1_cache_info[ICACHE].line_size = CACHE_LINE_SIZE(ICACHE);
+ L1_cache_info[ICACHE].sets = CACHE_SET(ICACHE);
+ L1_cache_info[ICACHE].size =
+ L1_cache_info[ICACHE].ways * L1_cache_info[ICACHE].line_size *
+ L1_cache_info[ICACHE].sets / 1024;
+ pr_info("L1I:%dKB/%dS/%dW/%dB\n", L1_cache_info[ICACHE].size,
+ L1_cache_info[ICACHE].sets, L1_cache_info[ICACHE].ways,
+ L1_cache_info[ICACHE].line_size);
+ L1_cache_info[DCACHE].ways = CACHE_WAY(DCACHE);
+ L1_cache_info[DCACHE].line_size = CACHE_LINE_SIZE(DCACHE);
+ L1_cache_info[DCACHE].sets = CACHE_SET(DCACHE);
+ L1_cache_info[DCACHE].size =
+ L1_cache_info[DCACHE].ways * L1_cache_info[DCACHE].line_size *
+ L1_cache_info[DCACHE].sets / 1024;
+ pr_info("L1D:%dKB/%dS/%dW/%dB\n", L1_cache_info[DCACHE].size,
+ L1_cache_info[DCACHE].sets, L1_cache_info[DCACHE].ways,
+ L1_cache_info[DCACHE].line_size);
+ pr_info("L1 D-Cache is %s\n", WRITE_METHOD);
+ if (L1_cache_info[DCACHE].size != L1_CACHE_BYTES)
+ pr_crit
+ ("The cache line size(%d) of this processor is not the same as L1_CACHE_BYTES(%d).\n",
+ L1_cache_info[DCACHE].size, L1_CACHE_BYTES);
+#ifndef CONFIG_CPU_CACHE_NONALIASING
+ {
+ int aliasing_num;
+ aliasing_num =
+ L1_cache_info[ICACHE].size * 1024 / PAGE_SIZE /
+ L1_cache_info[ICACHE].ways;
+ L1_cache_info[ICACHE].aliasing_num = aliasing_num;
+ L1_cache_info[ICACHE].aliasing_mask =
+ (aliasing_num - 1) << PAGE_SHIFT;
+ aliasing_num =
+ L1_cache_info[DCACHE].size * 1024 / PAGE_SIZE /
+ L1_cache_info[DCACHE].ways;
+ L1_cache_info[DCACHE].aliasing_num = aliasing_num;
+ L1_cache_info[DCACHE].aliasing_mask =
+ (aliasing_num - 1) << PAGE_SHIFT;
+ }
+#endif
+}
+
+static void __init setup_cpuinfo(void)
+{
+ unsigned long tmp = 0, cpu_name;
+
+ cpu_dcache_inval_all();
+ cpu_icache_inval_all();
+ __nds32__isb();
+
+ cpu_id = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCPUID) >> CPU_VER_offCPUID;
+ cpu_name = ((cpu_id) & 0xf0) >> 4;
+ cpu_series = cpu_name ? cpu_name - 10 + 'A' : 'N';
+ cpu_id = cpu_id & 0xf;
+ cpu_rev = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskREV) >> CPU_VER_offREV;
+ cpu_cfgid = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCFGID) >> CPU_VER_offCFGID;
+
+ pr_info("CPU:%c%ld, CPU_VER 0x%08x(id %lu, rev %lu, cfg %lu)\n",
+ cpu_series, cpu_id, __nds32__mfsr(NDS32_SR_CPU_VER), cpu_id, cpu_rev, cpu_cfgid);
+
+ elf_hwcap |= HWCAP_MFUSR_PC;
+
+ if (((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskBASEV) >> MSC_CFG_offBASEV) == 0) {
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskDIV)
+ elf_hwcap |= HWCAP_DIV;
+
+ if ((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskMAC)
+ || (cpu_id == 12 && cpu_rev < 4))
+ elf_hwcap |= HWCAP_MAC;
+ } else {
+ elf_hwcap |= HWCAP_V2;
+ elf_hwcap |= HWCAP_DIV;
+ elf_hwcap |= HWCAP_MAC;
+ }
+
+ if (cpu_cfgid & 0x0001)
+ elf_hwcap |= HWCAP_EXT;
+
+ if (cpu_cfgid & 0x0002)
+ elf_hwcap |= HWCAP_BASE16;
+
+ if (cpu_cfgid & 0x0004)
+ elf_hwcap |= HWCAP_EXT2;
+
+ if (cpu_cfgid & 0x0008)
+ elf_hwcap |= HWCAP_FPU;
+
+ if (cpu_cfgid & 0x0010)
+ elf_hwcap |= HWCAP_STRING;
+
+ if (__nds32__mfsr(NDS32_SR_MMU_CFG) & MMU_CFG_mskDE)
+ endianness = "MSB";
+ else
+ endianness = "LSB";
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskEDM)
+ elf_hwcap |= HWCAP_EDM;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskLMDMA)
+ elf_hwcap |= HWCAP_LMDMA;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskPFM)
+ elf_hwcap |= HWCAP_PFM;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskHSMP)
+ elf_hwcap |= HWCAP_HSMP;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskTRACE)
+ elf_hwcap |= HWCAP_TRACE;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskAUDIO)
+ elf_hwcap |= HWCAP_AUDIO;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C)
+ elf_hwcap |= HWCAP_L2C;
+
+ tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL);
+ if (!IS_ENABLED(CONFIG_CPU_DCACHE_DISABLE))
+ tmp |= CACHE_CTL_mskDC_EN;
+
+ if (!IS_ENABLED(CONFIG_CPU_ICACHE_DISABLE))
+ tmp |= CACHE_CTL_mskIC_EN;
+ __nds32__mtsr_isb(tmp, NDS32_SR_CACHE_CTL);
+
+ dump_cpu_info(smp_processor_id());
+}
+
+static unsigned long __init setup_memory(void)
+{
+ unsigned long bootmap_size;
+ unsigned long ram_start_pfn;
+ unsigned long free_ram_start_pfn;
+ phys_addr_t memory_start, memory_end;
+ struct memblock_region *region;
+
+ memory_end = memory_start = 0;
+
+ /* Find main memory where is the kernel */
+ for_each_memblock(memory, region) {
+ memory_start = region->base;
+ memory_end = region->base + region->size;
+ pr_info("%s: Memory: 0x%x-0x%x\n", __func__,
+ memory_start, memory_end);
+ }
+
+ if (!memory_end) {
+ panic("No memory!");
+ }
+
+ ram_start_pfn = PFN_UP(memblock_start_of_DRAM());
+ /* free_ram_start_pfn is first page after kernel */
+ free_ram_start_pfn = PFN_UP(__pa(&_end));
+ max_pfn = PFN_DOWN(memblock_end_of_DRAM());
+ /* it could update max_pfn */
+ if (max_pfn - ram_start_pfn <= MAXMEM_PFN)
+ max_low_pfn = max_pfn;
+ else {
+ max_low_pfn = MAXMEM_PFN + ram_start_pfn;
+ if (!IS_ENABLED(CONFIG_HIGHMEM))
+ max_pfn = MAXMEM_PFN + ram_start_pfn;
+ }
+ /* high_memory is related with VMALLOC */
+ high_memory = (void *)__va(max_low_pfn * PAGE_SIZE);
+ min_low_pfn = free_ram_start_pfn;
+
+ /*
+ * initialize the boot-time allocator (with low memory only).
+ *
+ * This makes the memory from the end of the kernel to the end of
+ * RAM usable.
+ * init_bootmem sets the global values min_low_pfn, max_low_pfn.
+ */
+ bootmap_size = init_bootmem_node(NODE_DATA(0), free_ram_start_pfn,
+ ram_start_pfn, max_low_pfn);
+ free_bootmem(PFN_PHYS(free_ram_start_pfn),
+ (max_low_pfn - free_ram_start_pfn) << PAGE_SHIFT);
+ reserve_bootmem(PFN_PHYS(free_ram_start_pfn), bootmap_size,
+ BOOTMEM_DEFAULT);
+
+ for_each_memblock(reserved, region) {
+ if (region->size != 0) {
+ pr_info("Reserved - 0x%08x-0x%08x\n",
+ (u32) region->base, (u32) region->size);
+ reserve_bootmem(region->base, region->size,
+ BOOTMEM_DEFAULT);
+ }
+ }
+ return max_low_pfn;
+}
+
+void __init setup_arch(char **cmdline_p)
+{
+ early_init_devtree(__atags_pointer ?
+ phys_to_virt(__atags_pointer) : __dtb_start);
+
+ setup_cpuinfo();
+
+ init_mm.start_code = (unsigned long)&_stext;
+ init_mm.end_code = (unsigned long)&_etext;
+ init_mm.end_data = (unsigned long)&_edata;
+ init_mm.brk = (unsigned long)&_end;
+
+ /* setup bootmem allocator */
+ setup_memory();
+
+ /* paging_init() sets up the MMU and marks all pages as reserved */
+ paging_init();
+
+ /* use generic way to parse */
+ parse_early_param();
+
+ unflatten_and_copy_device_tree();
+
+ if(IS_ENABLED(CONFIG_VT)) {
+ if(IS_ENABLED(CONFIG_VGA_CONSOLE))
+ conswitchp = &vga_con;
+ else if(IS_ENABLED(CONFIG_DUMMY_CONSOLE))
+ conswitchp = &dummy_con;
+ }
+
+ *cmdline_p = boot_command_line;
+ early_trap_init();
+}
+
+void calibrate_delay(void)
+{
+ const int *val;
+ struct device_node *cpu = NULL;
+ cpu = of_find_compatible_node(NULL, NULL, "andestech,n13");
+ val = of_get_property(cpu, "clock-frequency", NULL);
+ if (!val)
+ panic("no cpu 'clock-frequency' parameter in device tree");
+ loops_per_jiffy = *val / HZ;
+ pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n",
+ loops_per_jiffy / (500000 / HZ),
+ (loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy);
+}
+
+static int c_show(struct seq_file *m, void *v)
+{
+ int i;
+
+ seq_printf(m, "Processor\t: %c%ld (id %lu, rev %lu, cfg %lu)\n",
+ cpu_series, cpu_id, cpu_id, cpu_rev, cpu_cfgid);
+
+ seq_printf(m, "L1I\t\t: %luKB/%luS/%luW/%luB\n",
+ CACHE_SET(ICACHE) * CACHE_WAY(ICACHE) *
+ CACHE_LINE_SIZE(ICACHE) / 1024, CACHE_SET(ICACHE),
+ CACHE_WAY(ICACHE), CACHE_LINE_SIZE(ICACHE));
+
+ seq_printf(m, "L1D\t\t: %luKB/%luS/%luW/%luB\n",
+ CACHE_SET(DCACHE) * CACHE_WAY(DCACHE) *
+ CACHE_LINE_SIZE(DCACHE) / 1024, CACHE_SET(DCACHE),
+ CACHE_WAY(DCACHE), CACHE_LINE_SIZE(DCACHE));
+
+ seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
+ loops_per_jiffy / (500000 / HZ),
+ (loops_per_jiffy / (5000 / HZ)) % 100);
+
+ /* dump out the processor features */
+ seq_puts(m, "Features\t: ");
+
+ for (i = 0; hwcap_str[i]; i++)
+ if (elf_hwcap & (1 << i))
+ seq_printf(m, "%s ", hwcap_str[i]);
+
+ seq_puts(m, "\n\n");
+
+ return 0;
+}
+
+static void *c_start(struct seq_file *m, loff_t * pos)
+{
+ return *pos < 1 ? (void *)1 : NULL;
+}
+
+static void *c_next(struct seq_file *m, void *v, loff_t * pos)
+{
+ ++*pos;
+ return NULL;
+}
+
+static void c_stop(struct seq_file *m, void *v)
+{
+}
+
+struct seq_operations cpuinfo_op = {
+ .start = c_start,
+ .next = c_next,
+ .stop = c_stop,
+ .show = c_show
+};
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 01/35] nds32: Assembly macros and definitions
From: Greentime Hu @ 2017-11-27 12:27 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial
Cc: green.hu, Vincent Chen
In-Reply-To: <cover.1511785528.git.green.hu@gmail.com>
From: Greentime Hu <greentime@andestech.com>
This patch includes assembly macros, bit field definitions used in .S
files across arch/nds32/.
Signed-off-by: Vincent Chen <vincentc@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
---
arch/nds32/include/asm/assembler.h | 52 ++
arch/nds32/include/asm/bitfield.h | 974 ++++++++++++++++++++++++++++++++++++
arch/nds32/include/asm/nds32.h | 96 ++++
arch/nds32/kernel/asm-offsets.c | 41 ++
4 files changed, 1163 insertions(+)
create mode 100644 arch/nds32/include/asm/assembler.h
create mode 100644 arch/nds32/include/asm/bitfield.h
create mode 100644 arch/nds32/include/asm/nds32.h
create mode 100644 arch/nds32/kernel/asm-offsets.c
diff --git a/arch/nds32/include/asm/assembler.h b/arch/nds32/include/asm/assembler.h
new file mode 100644
index 0000000..d469af0
--- /dev/null
+++ b/arch/nds32/include/asm/assembler.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __NDS32_ASSEMBLER_H__
+#define __NDS32_ASSEMBLER_H__
+
+.macro gie_disable
+ setgie.d
+ dsb
+.endm
+
+.macro gie_enable
+ setgie.e
+ dsb
+.endm
+
+.macro gie_save oldpsw
+ mfsr \oldpsw, $ir0
+ setgie.d
+ dsb
+.endm
+
+.macro gie_restore oldpsw
+ andi \oldpsw, \oldpsw, #0x1
+ beqz \oldpsw, 7001f
+ setgie.e
+ dsb
+7001:
+.endm
+
+
+#define USER(insn, reg, addr, opr) \
+9999: insn reg, addr, opr; \
+ .section __ex_table,"a"; \
+ .align 3; \
+ .long 9999b, 9001f; \
+ .previous
+
+#endif /* __NDS32_ASSEMBLER_H__ */
diff --git a/arch/nds32/include/asm/bitfield.h b/arch/nds32/include/asm/bitfield.h
new file mode 100644
index 0000000..e5c783d
--- /dev/null
+++ b/arch/nds32/include/asm/bitfield.h
@@ -0,0 +1,974 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __NDS32_BITFIELD_H__
+#define __NDS32_BITFIELD_H__
+/******************************************************************************
+ * cr0: CPU_VER (CPU Version Register)
+ *****************************************************************************/
+#define CPU_VER_offCFGID 0 /* Minor configuration */
+#define CPU_VER_offREV 16 /* Revision of the CPU version */
+#define CPU_VER_offCPUID 24 /* Major CPU versions */
+
+#define CPU_VER_mskCFGID ( 0xFFFF << CPU_VER_offCFGID )
+#define CPU_VER_mskREV ( 0xFF << CPU_VER_offREV )
+#define CPU_VER_mskCPUID ( 0xFF << CPU_VER_offCPUID )
+
+/******************************************************************************
+ * cr1: ICM_CFG (Instruction Cache/Memory Configuration Register)
+ *****************************************************************************/
+#define ICM_CFG_offISET 0 /* I-cache sets (# of cache lines) per way */
+#define ICM_CFG_offIWAY 3 /* I-cache ways */
+#define ICM_CFG_offISZ 6 /* I-cache line size */
+#define ICM_CFG_offILCK 9 /* I-cache locking support */
+#define ICM_CFG_offILMB 10 /* On-chip ILM banks */
+#define ICM_CFG_offBSAV 13 /* ILM base register alignment version */
+/* bit 15:31 reserved */
+
+#define ICM_CFG_mskISET ( 0x7 << ICM_CFG_offISET )
+#define ICM_CFG_mskIWAY ( 0x7 << ICM_CFG_offIWAY )
+#define ICM_CFG_mskISZ ( 0x7 << ICM_CFG_offISZ )
+#define ICM_CFG_mskILCK ( 0x1 << ICM_CFG_offILCK )
+#define ICM_CFG_mskILMB ( 0x7 << ICM_CFG_offILMB )
+#define ICM_CFG_mskBSAV ( 0x3 << ICM_CFG_offBSAV )
+
+/******************************************************************************
+ * cr2: DCM_CFG (Data Cache/Memory Configuration Register)
+ *****************************************************************************/
+#define DCM_CFG_offDSET 0 /* D-cache sets (# of cache lines) per way */
+#define DCM_CFG_offDWAY 3 /* D-cache ways */
+#define DCM_CFG_offDSZ 6 /* D-cache line size */
+#define DCM_CFG_offDLCK 9 /* D-cache locking support */
+#define DCM_CFG_offDLMB 10 /* On-chip DLM banks */
+#define DCM_CFG_offBSAV 13 /* DLM base register alignment version */
+/* bit 15:31 reserved */
+
+#define DCM_CFG_mskDSET ( 0x7 << DCM_CFG_offDSET )
+#define DCM_CFG_mskDWAY ( 0x7 << DCM_CFG_offDWAY )
+#define DCM_CFG_mskDSZ ( 0x7 << DCM_CFG_offDSZ )
+#define DCM_CFG_mskDLCK ( 0x1 << DCM_CFG_offDLCK )
+#define DCM_CFG_mskDLMB ( 0x7 << DCM_CFG_offDLMB )
+#define DCM_CFG_mskBSAV ( 0x3 << DCM_CFG_offBSAV )
+
+/******************************************************************************
+ * cr3: MMU_CFG (MMU Configuration Register)
+ *****************************************************************************/
+#define MMU_CFG_offMMPS 0 /* Memory management protection scheme */
+#define MMU_CFG_offMMPV 2 /* Memory management protection version number */
+#define MMU_CFG_offFATB 7 /* Fully-associative or non-fully-associative TLB */
+
+#define MMU_CFG_offTBW 8 /* TLB ways(non-associative) TBS */
+#define MMU_CFG_offTBS 11 /* TLB sets per way(non-associative) TBS */
+/* bit 14:14 reserved */
+
+#define MMU_CFG_offEP8MIN4 15 /* 8KB page supported while minimum page is 4KB */
+#define MMU_CFG_offfEPSZ 16 /* Extra page size supported */
+#define MMU_CFG_offTLBLCK 24 /* TLB locking support */
+#define MMU_CFG_offHPTWK 25 /* Hardware Page Table Walker implemented */
+#define MMU_CFG_offDE 26 /* Default endian */
+#define MMU_CFG_offNTPT 27 /* Partitions for non-translated attributes */
+#define MMU_CFG_offIVTB 28 /* Invisible TLB */
+#define MMU_CFG_offVLPT 29 /* VLPT for fast TLB fill handling implemented */
+#define MMU_CFG_offNTME 30 /* Non-translated VA to PA mapping */
+/* bit 31 reserved */
+
+#define MMU_CFG_mskMMPS ( 0x3 << MMU_CFG_offMMPS )
+#define MMU_CFG_mskMMPV ( 0x1F << MMU_CFG_offMMPV )
+#define MMU_CFG_mskFATB ( 0x1 << MMU_CFG_offFATB )
+#define MMU_CFG_mskTBW ( 0x7 << MMU_CFG_offTBW )
+#define MMU_CFG_mskTBS ( 0x7 << MMU_CFG_offTBS )
+#define MMU_CFG_mskEP8MIN4 ( 0x1 << MMU_CFG_offEP8MIN4 )
+#define MMU_CFG_mskfEPSZ ( 0xFF << MMU_CFG_offfEPSZ )
+#define MMU_CFG_mskTLBLCK ( 0x1 << MMU_CFG_offTLBLCK )
+#define MMU_CFG_mskHPTWK ( 0x1 << MMU_CFG_offHPTWK )
+#define MMU_CFG_mskDE ( 0x1 << MMU_CFG_offDE )
+#define MMU_CFG_mskNTPT ( 0x1 << MMU_CFG_offNTPT )
+#define MMU_CFG_mskIVTB ( 0x1 << MMU_CFG_offIVTB )
+#define MMU_CFG_mskVLPT ( 0x1 << MMU_CFG_offVLPT )
+#define MMU_CFG_mskNTME ( 0x1 << MMU_CFG_offNTME )
+
+/******************************************************************************
+ * cr4: MSC_CFG (Misc Configuration Register)
+ *****************************************************************************/
+#define MSC_CFG_offEDM 0
+#define MSC_CFG_offLMDMA 1
+#define MSC_CFG_offPFM 2
+#define MSC_CFG_offHSMP 3
+#define MSC_CFG_offTRACE 4
+#define MSC_CFG_offDIV 5
+#define MSC_CFG_offMAC 6
+#define MSC_CFG_offAUDIO 7
+#define MSC_CFG_offL2C 9
+#define MSC_CFG_offRDREG 10
+#define MSC_CFG_offADR24 11
+#define MSC_CFG_offINTLC 12
+#define MSC_CFG_offBASEV 13
+#define MSC_CFG_offNOD 16
+/* bit 13:31 reserved */
+
+#define MSC_CFG_mskEDM ( 0x1 << MSC_CFG_offEDM )
+#define MSC_CFG_mskLMDMA ( 0x1 << MSC_CFG_offLMDMA )
+#define MSC_CFG_mskPFM ( 0x1 << MSC_CFG_offPFM )
+#define MSC_CFG_mskHSMP ( 0x1 << MSC_CFG_offHSMP )
+#define MSC_CFG_mskTRACE ( 0x1 << MSC_CFG_offTRACE )
+#define MSC_CFG_mskDIV ( 0x1 << MSC_CFG_offDIV )
+#define MSC_CFG_mskMAC ( 0x1 << MSC_CFG_offMAC )
+#define MSC_CFG_mskAUDIO ( 0x3 << MSC_CFG_offAUDIO )
+#define MSC_CFG_mskL2C ( 0x1 << MSC_CFG_offL2C )
+#define MSC_CFG_mskRDREG ( 0x1 << MSC_CFG_offRDREG )
+#define MSC_CFG_mskADR24 ( 0x1 << MSC_CFG_offADR24 )
+#define MSC_CFG_mskINTLC ( 0x1 << MSC_CFG_offINTLC )
+#define MSC_CFG_mskBASEV ( 0x7 << MSC_CFG_offBASEV )
+#define MSC_CFG_mskNOD ( 0x1 << MSC_CFG_offNOD )
+
+/******************************************************************************
+ * cr5: CORE_CFG (Core Identification Register)
+ *****************************************************************************/
+#define CORE_ID_offCOREID 0
+/* bit 4:31 reserved */
+
+#define CORE_ID_mskCOREID ( 0xF << CORE_ID_offCOREID )
+
+/******************************************************************************
+ * cr6: FUCOP_EXIST (FPU and Coprocessor Existence Configuration Register)
+ *****************************************************************************/
+#define FUCOP_EXIST_offCP0EX 0
+#define FUCOP_EXIST_offCP1EX 1
+#define FUCOP_EXIST_offCP2EX 2
+#define FUCOP_EXIST_offCP3EX 3
+#define FUCOP_EXIST_offCP0ISFPU 31
+
+#define FUCOP_EXIST_mskCP0EX ( 0x1 << FUCOP_EXIST_offCP0EX )
+#define FUCOP_EXIST_mskCP1EX ( 0x1 << FUCOP_EXIST_offCP1EX )
+#define FUCOP_EXIST_mskCP2EX ( 0x1 << FUCOP_EXIST_offCP2EX )
+#define FUCOP_EXIST_mskCP3EX ( 0x1 << FUCOP_EXIST_offCP3EX )
+#define FUCOP_EXIST_mskCP0ISFPU ( 0x1 << FUCOP_EXIST_offCP0ISFPU )
+
+/******************************************************************************
+ * ir0: PSW (Processor Status Word Register)
+ * ir1: IPSW (Interruption PSW Register)
+ * ir2: P_IPSW (Previous IPSW Register)
+ *****************************************************************************/
+#define PSW_offGIE 0 /* Global Interrupt Enable */
+#define PSW_offINTL 1 /* Interruption Stack Level */
+#define PSW_offPOM 3 /* Processor Operation Mode, User/Superuser */
+#define PSW_offBE 5 /* Endianness for data memory access, 1:MSB, 0:LSB */
+#define PSW_offIT 6 /* Enable instruction address translation */
+#define PSW_offDT 7 /* Enable data address translation */
+#define PSW_offIME 8 /* Instruction Machine Error flag */
+#define PSW_offDME 9 /* Data Machine Error flag */
+#define PSW_offDEX 10 /* Debug Exception */
+#define PSW_offHSS 11 /* Hardware Single Stepping */
+#define PSW_offDRBE 12 /* Device Register Endian Mode */
+#define PSW_offAEN 13 /* Audio ISA special feature */
+#define PSW_offWBNA 14 /* Write Back Non-Allocate */
+#define PSW_offIFCON 15 /* IFC On */
+#define PSW_offCPL 16 /* Current Priority Level */
+/* bit 19:31 reserved */
+
+#define PSW_mskGIE ( 0x1 << PSW_offGIE )
+#define PSW_mskINTL ( 0x3 << PSW_offINTL )
+#define PSW_mskPOM ( 0x3 << PSW_offPOM )
+#define PSW_mskBE ( 0x1 << PSW_offBE )
+#define PSW_mskIT ( 0x1 << PSW_offIT )
+#define PSW_mskDT ( 0x1 << PSW_offDT )
+#define PSW_mskIME ( 0x1 << PSW_offIME )
+#define PSW_mskDME ( 0x1 << PSW_offDME )
+#define PSW_mskDEX ( 0x1 << PSW_offDEX )
+#define PSW_mskHSS ( 0x1 << PSW_offHSS )
+#define PSW_mskDRBE ( 0x1 << PSW_offDRBE )
+#define PSW_mskAEN ( 0x1 << PSW_offAEN )
+#define PSW_mskWBNA ( 0x1 << PSW_offWBNA )
+#define PSW_mskIFCON ( 0x1 << PSW_offIFCON )
+#define PSW_mskCPL ( 0x7 << PSW_offCPL )
+
+#define PSW_SYSTEM ( 1 << PSW_offPOM )
+#define PSW_INTL_1 ( 1 << PSW_offINTL )
+#define PSW_CPL_NO ( 0 << PSW_offCPL )
+#define PSW_CPL_ANY ( 7 << PSW_offCPL )
+
+#define PSW_clr (PSW_mskGIE|PSW_mskINTL|PSW_mskPOM|PSW_mskIT|PSW_mskDT|PSW_mskIME|PSW_mskWBNA)
+#ifdef __NDS32_EB__
+#ifdef CONFIG_WBNA
+#define PSW_init (PSW_mskWBNA|(1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT|PSW_mskBE)
+#else
+#define PSW_init ((1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT|PSW_mskBE)
+#endif
+#else
+#ifdef CONFIG_WBNA
+#define PSW_init (PSW_mskWBNA|(1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT)
+#else
+#define PSW_init ((1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT)
+#endif
+#endif
+/******************************************************************************
+ * ir3: IVB (Interruption Vector Base Register)
+ *****************************************************************************/
+/* bit 0:12 reserved */
+#define IVB_offNIVIC 1 /* Number of input for IVIC Controller */
+#define IVB_offIVIC_VER 11 /* IVIC Version */
+#define IVB_offEVIC 13 /* External Vector Interrupt Controller mode */
+#define IVB_offESZ 14 /* Size of each vector entry */
+#define IVB_offIVBASE 16 /* BasePA of interrupt vector table */
+
+#define IVB_mskNIVIC ( 0x7 << IVB_offNIVIC )
+#define IVB_mskIVIC_VER ( 0x3 << IVB_offIVIC_VER )
+#define IVB_mskEVIC ( 0x1 << IVB_offEVIC )
+#define IVB_mskESZ ( 0x3 << IVB_offESZ )
+#define IVB_mskIVBASE ( 0xFFFF << IVB_offIVBASE )
+
+#define IVB_valESZ4 0
+#define IVB_valESZ16 1
+#define IVB_valESZ64 2
+#define IVB_valESZ256 3
+/******************************************************************************
+ * ir4: EVA (Exception Virtual Address Register)
+ * ir5: P_EVA (Previous EVA Register)
+ *****************************************************************************/
+
+ /* This register contains the VA that causes the exception */
+
+/******************************************************************************
+ * ir6: ITYPE (Interruption Type Register)
+ * ir7: P_ITYPE (Previous ITYPE Register)
+ *****************************************************************************/
+#define ITYPE_offETYPE 0 /* Exception Type */
+#define ITYPE_offINST 4 /* Exception caused by insn fetch or data access */
+/* bit 5:15 reserved */
+#define ITYPE_offVECTOR 5 /* Vector */
+#define ITYPE_offSWID 16 /* SWID of debugging exception */
+/* bit 31:31 reserved */
+
+#define ITYPE_mskETYPE ( 0xF << ITYPE_offETYPE )
+#define ITYPE_mskINST ( 0x1 << ITYPE_offINST )
+#define ITYPE_mskVECTOR ( 0x7F << ITYPE_offVECTOR )
+#define ITYPE_mskSWID ( 0x7FFF << ITYPE_offSWID )
+
+/* Additional definitions for ITYPE register */
+#define ITYPE_offSTYPE 16 /* Arithmetic Sub Type */
+#define ITYPE_offCPID 20 /* Co-Processor ID which generate the exception */
+
+#define ITYPE_mskSTYPE ( 0xF << ITYPE_offSTYPE )
+#define ITYPE_mskCPID ( 0x3 << ITYPE_offCPID )
+
+#define NDS32_VECTOR_mskNONEXCEPTION 0x78
+#define NDS32_VECTOR_offEXCEPTION 8
+#define NDS32_VECTOR_offINTERRUPT 9
+
+/* Interrupt vector entry */
+#define ENTRY_RESET_NMI 0
+#define ENTRY_TLB_FILL 1
+#define ENTRY_PTE_NOT_PRESENT 2
+#define ENTRY_TLB_MISC 3
+#define ENTRY_TLB_VLPT_MISS 4
+#define ENTRY_MACHINE_ERROR 5
+#define ENTRY_DEBUG_RELATED 6
+#define ENTRY_GENERAL_EXCPETION 7
+#define ENTRY_SYSCALL 8
+
+/* PTE not present exception definition */
+#define ETYPE_NON_LEAF_PTE_NOT_PRESENT 0
+#define ETYPE_LEAF_PTE_NOT_PRESENT 1
+
+/* General exception ETYPE definition */
+#define ETYPE_ALIGNMENT_CHECK 0
+#define ETYPE_RESERVED_INSTRUCTION 1
+#define ETYPE_TRAP 2
+#define ETYPE_ARITHMETIC 3
+#define ETYPE_PRECISE_BUS_ERROR 4
+#define ETYPE_IMPRECISE_BUS_ERROR 5
+#define ETYPE_COPROCESSOR 6
+#define ETYPE_RESERVED_VALUE 7
+#define ETYPE_NONEXISTENT_MEM_ADDRESS 8
+#define ETYPE_MPZIU_CONTROL 9
+#define ETYPE_NEXT_PRECISE_STACK_OFL 10
+
+/* Kerenl reserves software ID */
+#define SWID_RAISE_INTERRUPT_LEVEL 0x1a /* SWID_RAISE_INTERRUPT_LEVEL is used to
+ * raise interrupt level for debug exception
+ */
+
+/******************************************************************************
+ * ir8: MERR (Machine Error Log Register)
+ *****************************************************************************/
+/* bit 0:30 reserved */
+#define MERR_offBUSERR 31 /* Bus error caused by a load insn */
+
+#define MERR_mskBUSERR ( 0x1 << MERR_offBUSERR )
+
+/******************************************************************************
+ * ir9: IPC (Interruption Program Counter Register)
+ * ir10: P_IPC (Previous IPC Register)
+ * ir11: OIPC (Overflow Interruption Program Counter Register)
+ *****************************************************************************/
+
+ /* This is the shadow stack register of the Program Counter */
+
+/******************************************************************************
+ * ir12: P_P0 (Previous P0 Register)
+ * ir13: P_P1 (Previous P1 Register)
+ *****************************************************************************/
+
+ /* These are shadow registers of $p0 and $p1 */
+
+/******************************************************************************
+ * ir14: INT_MASK (Interruption Masking Register)
+ *****************************************************************************/
+#define INT_MASK_offH0IM 0 /* Hardware Interrupt 0 Mask bit */
+#define INT_MASK_offH1IM 1 /* Hardware Interrupt 1 Mask bit */
+#define INT_MASK_offH2IM 2 /* Hardware Interrupt 2 Mask bit */
+#define INT_MASK_offH3IM 3 /* Hardware Interrupt 3 Mask bit */
+#define INT_MASK_offH4IM 4 /* Hardware Interrupt 4 Mask bit */
+#define INT_MASK_offH5IM 5 /* Hardware Interrupt 5 Mask bit */
+/* bit 6:15 reserved */
+#define INT_MASK_offSIM 16 /* Software Interrupt Mask bit */
+/* bit 17:29 reserved */
+#define INT_MASK_offIDIVZE 30 /* Enable detection for Divide-By-Zero */
+#define INT_MASK_offDSSIM 31 /* Default Single Stepping Interruption Mask */
+
+#define INT_MASK_mskH0IM ( 0x1 << INT_MASK_offH0IM )
+#define INT_MASK_mskH1IM ( 0x1 << INT_MASK_offH1IM )
+#define INT_MASK_mskH2IM ( 0x1 << INT_MASK_offH2IM )
+#define INT_MASK_mskH3IM ( 0x1 << INT_MASK_offH3IM )
+#define INT_MASK_mskH4IM ( 0x1 << INT_MASK_offH4IM )
+#define INT_MASK_mskH5IM ( 0x1 << INT_MASK_offH5IM )
+#define INT_MASK_mskSIM ( 0x1 << INT_MASK_offSIM )
+#define INT_MASK_mskIDIVZE ( 0x1 << INT_MASK_offIDIVZE )
+#define INT_MASK_mskDSSIM ( 0x1 << INT_MASK_offDSSIM )
+
+#define INT_MASK_INITAIAL_VAL 0x10003
+
+/******************************************************************************
+ * ir15: INT_PEND (Interrupt Pending Register)
+ *****************************************************************************/
+#define INT_PEND_offH0I 0 /* Hardware Interrupt 0 pending bit */
+#define INT_PEND_offH1I 1 /* Hardware Interrupt 1 pending bit */
+#define INT_PEND_offH2I 2 /* Hardware Interrupt 2 pending bit */
+#define INT_PEND_offH3I 3 /* Hardware Interrupt 3 pending bit */
+#define INT_PEND_offH4I 4 /* Hardware Interrupt 4 pending bit */
+#define INT_PEND_offH5I 5 /* Hardware Interrupt 5 pending bit */
+
+#define INT_PEND_offCIPL 0 /* Current Interrupt Priority Level */
+
+/* bit 6:15 reserved */
+#define INT_PEND_offSWI 16 /* Software Interrupt pending bit */
+/* bit 17:31 reserved */
+
+#define INT_PEND_mskH0I ( 0x1 << INT_PEND_offH0I )
+#define INT_PEND_mskH1I ( 0x1 << INT_PEND_offH1I )
+#define INT_PEND_mskH2I ( 0x1 << INT_PEND_offH2I )
+#define INT_PEND_mskH3I ( 0x1 << INT_PEND_offH3I )
+#define INT_PEND_mskH4I ( 0x1 << INT_PEND_offH4I )
+#define INT_PEND_mskH5I ( 0x1 << INT_PEND_offH5I )
+#define INT_PEND_mskCIPL ( 0x1 << INT_PEND_offCIPL )
+#define INT_PEND_mskSWI ( 0x1 << INT_PEND_offSWI )
+
+/******************************************************************************
+ * mr0: MMU_CTL (MMU Control Register)
+ *****************************************************************************/
+#define MMU_CTL_offD 0 /* Default minimum page size */
+#define MMU_CTL_offNTC0 1 /* Non-Translated Cachebility of partition 0 */
+#define MMU_CTL_offNTC1 3 /* Non-Translated Cachebility of partition 1 */
+#define MMU_CTL_offNTC2 5 /* Non-Translated Cachebility of partition 2 */
+#define MMU_CTL_offNTC3 7 /* Non-Translated Cachebility of partition 3 */
+#define MMU_CTL_offTBALCK 9 /* TLB all-lock resolution scheme */
+#define MMU_CTL_offMPZIU 10 /* Multiple Page Size In Use bit */
+#define MMU_CTL_offNTM0 11 /* Non-Translated VA to PA of partition 0 */
+#define MMU_CTL_offNTM1 13 /* Non-Translated VA to PA of partition 1 */
+#define MMU_CTL_offNTM2 15 /* Non-Translated VA to PA of partition 2 */
+#define MMU_CTL_offNTM3 17 /* Non-Translated VA to PA of partition 3 */
+/* bit 19:31 reserved */
+
+#define MMU_CTL_mskD ( 0x1 << MMU_CTL_offD )
+#define MMU_CTL_mskNTC0 ( 0x3 << MMU_CTL_offNTC0 )
+#define MMU_CTL_mskNTC1 ( 0x3 << MMU_CTL_offNTC1 )
+#define MMU_CTL_mskNTC2 ( 0x3 << MMU_CTL_offNTC2 )
+#define MMU_CTL_mskNTC3 ( 0x3 << MMU_CTL_offNTC3 )
+#define MMU_CTL_mskTBALCK ( 0x1 << MMU_CTL_offTBALCK )
+#define MMU_CTL_mskMPZIU ( 0x1 << MMU_CTL_offMPZIU )
+#define MMU_CTL_mskNTM0 ( 0x3 << MMU_CTL_offNTM0 )
+#define MMU_CTL_mskNTM1 ( 0x3 << MMU_CTL_offNTM1 )
+#define MMU_CTL_mskNTM2 ( 0x3 << MMU_CTL_offNTM2 )
+#define MMU_CTL_mskNTM3 ( 0x3 << MMU_CTL_offNTM3 )
+
+#define MMU_CTL_D4KB 0
+#define MMU_CTL_D8KB 1
+
+#define MMU_CTL_CACHEABLE_WB 2
+#define MMU_CTL_CACHEABLE_WT 3
+
+/******************************************************************************
+ * mr1: L1_PPTB (L1 Physical Page Table Base Register)
+ *****************************************************************************/
+#define L1_PPTB_offNV 0 /* Enable Hardware Page Table Walker (HPTWK) */
+/* bit 1:11 reserved */
+#define L1_PPTB_offBASE 12 /* First level physical page table base address */
+
+#define L1_PPTB_mskNV ( 0x1 << L1_PPTB_offNV )
+#define L1_PPTB_mskBASE ( 0xFFFFF << L1_PPTB_offBASE )
+
+/******************************************************************************
+ * mr2: TLB_VPN (TLB Access VPN Register)
+ *****************************************************************************/
+/* bit 0:11 reserved */
+#define TLB_VPN_offVPN 12 /* Virtual Page Number */
+
+#define TLB_VPN_mskVPN ( 0xFFFFF << TLB_VPN_offVPN )
+
+/******************************************************************************
+ * mr3: TLB_DATA (TLB Access Data Register)
+ *****************************************************************************/
+#define TLB_DATA_offV 0 /* PTE is valid and present */
+#define TLB_DATA_offM 1 /* Page read/write access privilege */
+#define TLB_DATA_offD 4 /* Dirty bit */
+#define TLB_DATA_offX 5 /* Executable bit */
+#define TLB_DATA_offA 6 /* Access bit */
+#define TLB_DATA_offG 7 /* Global page (shared across contexts) */
+#define TLB_DATA_offC 8 /* Cacheability atribute */
+/* bit 11:11 reserved */
+#define TLB_DATA_offPPN 12 /* Phisical Page Number */
+
+#define TLB_DATA_mskV ( 0x1 << TLB_DATA_offV )
+#define TLB_DATA_mskM ( 0x7 << TLB_DATA_offM )
+#define TLB_DATA_mskD ( 0x1 << TLB_DATA_offD )
+#define TLB_DATA_mskX ( 0x1 << TLB_DATA_offX )
+#define TLB_DATA_mskA ( 0x1 << TLB_DATA_offA )
+#define TLB_DATA_mskG ( 0x1 << TLB_DATA_offG )
+#define TLB_DATA_mskC ( 0x7 << TLB_DATA_offC )
+#define TLB_DATA_mskPPN ( 0xFFFFF << TLB_DATA_offPPN )
+
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+#define TLB_DATA_kernel_text_attr (TLB_DATA_mskV|TLB_DATA_mskM|TLB_DATA_mskD|TLB_DATA_mskX|TLB_DATA_mskG|TLB_DATA_mskC)
+#else
+#define TLB_DATA_kernel_text_attr (TLB_DATA_mskV|TLB_DATA_mskM|TLB_DATA_mskD|TLB_DATA_mskX|TLB_DATA_mskG|(0x6 << TLB_DATA_offC))
+#endif
+
+/******************************************************************************
+ * mr4: TLB_MISC (TLB Access Misc Register)
+ *****************************************************************************/
+#define TLB_MISC_offACC_PSZ 0 /* Page size of a PTE entry */
+#define TLB_MISC_offCID 4 /* Context id */
+/* bit 13:31 reserved */
+
+#define TLB_MISC_mskACC_PSZ ( 0xF << TLB_MISC_offACC_PSZ )
+#define TLB_MISC_mskCID ( 0x1FF << TLB_MISC_offCID )
+
+/******************************************************************************
+ * mr5: VLPT_IDX (Virtual Linear Page Table Index Register)
+ *****************************************************************************/
+#define VLPT_IDX_offZERO 0 /* Always 0 */
+#define VLPT_IDX_offEVPN 2 /* Exception Virtual Page Number */
+#define VLPT_IDX_offVLPTB 22 /* Base VA of VLPT */
+
+#define VLPT_IDX_mskZERO ( 0x3 << VLPT_IDX_offZERO )
+#define VLPT_IDX_mskEVPN ( 0xFFFFF << VLPT_IDX_offEVPN )
+#define VLPT_IDX_mskVLPTB ( 0x3FF << VLPT_IDX_offVLPTB )
+
+/******************************************************************************
+ * mr6: ILMB (Instruction Local Memory Base Register)
+ *****************************************************************************/
+#define ILMB_offIEN 0 /* Enable ILM */
+#define ILMB_offILMSZ 1 /* Size of ILM */
+/* bit 5:19 reserved */
+#define ILMB_offIBPA 20 /* Base PA of ILM */
+
+#define ILMB_mskIEN ( 0x1 << ILMB_offIEN )
+#define ILMB_mskILMSZ ( 0xF << ILMB_offILMSZ )
+#define ILMB_mskIBPA ( 0xFFF << ILMB_offIBPA )
+
+/******************************************************************************
+ * mr7: DLMB (Data Local Memory Base Register)
+ *****************************************************************************/
+#define DLMB_offDEN 0 /* Enable DLM */
+#define DLMB_offDLMSZ 1 /* Size of DLM */
+#define DLMB_offDBM 5 /* Enable Double-Buffer Mode for DLM */
+#define DLMB_offDBB 6 /* Double-buffer bank which can be accessed by the processor */
+/* bit 7:19 reserved */
+#define DLMB_offDBPA 20 /* Base PA of DLM */
+
+#define DLMB_mskDEN ( 0x1 << DLMB_offDEN )
+#define DLMB_mskDLMSZ ( 0xF << DLMB_offDLMSZ )
+#define DLMB_mskDBM ( 0x1 << DLMB_offDBM )
+#define DLMB_mskDBB ( 0x1 << DLMB_offDBB )
+#define DLMB_mskDBPA ( 0xFFF << DLMB_offDBPA )
+
+/******************************************************************************
+ * mr8: CACHE_CTL (Cache Control Register)
+ *****************************************************************************/
+#define CACHE_CTL_offIC_EN 0 /* Enable I-cache */
+#define CACHE_CTL_offDC_EN 1 /* Enable D-cache */
+#define CACHE_CTL_offICALCK 2 /* I-cache all-lock resolution scheme */
+#define CACHE_CTL_offDCALCK 3 /* D-cache all-lock resolution scheme */
+#define CACHE_CTL_offDCCWF 4 /* Enable D-cache Critical Word Forwarding */
+#define CACHE_CTL_offDCPMW 5 /* Enable D-cache concurrent miss and write-back processing */
+/* bit 6:31 reserved */
+
+#define CACHE_CTL_mskIC_EN ( 0x1 << CACHE_CTL_offIC_EN )
+#define CACHE_CTL_mskDC_EN ( 0x1 << CACHE_CTL_offDC_EN )
+#define CACHE_CTL_mskICALCK ( 0x1 << CACHE_CTL_offICALCK )
+#define CACHE_CTL_mskDCALCK ( 0x1 << CACHE_CTL_offDCALCK )
+#define CACHE_CTL_mskDCCWF ( 0x1 << CACHE_CTL_offDCCWF )
+#define CACHE_CTL_mskDCPMW ( 0x1 << CACHE_CTL_offDCPMW )
+
+/******************************************************************************
+ * mr9: HSMP_SADDR (High Speed Memory Port Starting Address)
+ *****************************************************************************/
+#define HSMP_SADDR_offEN 0 /* Enable control bit for the High Speed Memory port */
+/* bit 1:19 reserved */
+
+#define HSMP_SADDR_offRANGE 1 /* Denote the address range (only defined in HSMP v2 ) */
+#define HSMP_SADDR_offSADDR 20 /* Starting base PA of the High Speed Memory Port region */
+
+#define HSMP_SADDR_mskEN ( 0x1 << HSMP_SADDR_offEN )
+#define HSMP_SADDR_mskRANGE ( 0xFFF << HSMP_SADDR_offRANGE )
+#define HSMP_SADDR_mskSADDR ( 0xFFF << HSMP_SADDR_offSADDR )
+
+/******************************************************************************
+ * mr10: HSMP_EADDR (High Speed Memory Port Ending Address)
+ *****************************************************************************/
+/* bit 0:19 reserved */
+#define HSMP_EADDR_offEADDR 20
+
+#define HSMP_EADDR_mskEADDR ( 0xFFF << HSMP_EADDR_offEADDR )
+
+/******************************************************************************
+ * dr0+(n*5): BPCn (n=0-7) (Breakpoint Control Register)
+ *****************************************************************************/
+#define BPC_offWP 0 /* Configuration of BPAn */
+#define BPC_offEL 1 /* Enable BPAn */
+#define BPC_offS 2 /* Data address comparison for a store instruction */
+#define BPC_offP 3 /* Compared data address is PA */
+#define BPC_offC 4 /* CID value is compared with the BPCIDn register */
+#define BPC_offBE0 5 /* Enable byte mask for the comparison with register */
+#define BPC_offBE1 6 /* Enable byte mask for the comparison with register */
+#define BPC_offBE2 7 /* Enable byte mask for the comparison with register */
+#define BPC_offBE3 8 /* Enable byte mask for the comparison with register */
+#define BPC_offT 9 /* Enable breakpoint Embedded Tracer triggering operation */
+
+#define BPC_mskWP ( 0x1 << BPC_offWP )
+#define BPC_mskEL ( 0x1 << BPC_offEL )
+#define BPC_mskS ( 0x1 << BPC_offS )
+#define BPC_mskP ( 0x1 << BPC_offP )
+#define BPC_mskC ( 0x1 << BPC_offC )
+#define BPC_mskBE0 ( 0x1 << BPC_offBE0 )
+#define BPC_mskBE1 ( 0x1 << BPC_offBE1 )
+#define BPC_mskBE2 ( 0x1 << BPC_offBE2 )
+#define BPC_mskBE3 ( 0x1 << BPC_offBE3 )
+#define BPC_mskT ( 0x1 << BPC_offT )
+
+/******************************************************************************
+ * dr1+(n*5): BPAn (n=0-7) (Breakpoint Address Register)
+ *****************************************************************************/
+
+ /* These registers contain break point address */
+
+/******************************************************************************
+ * dr2+(n*5): BPAMn (n=0-7) (Breakpoint Address Mask Register)
+ *****************************************************************************/
+
+ /* These registerd contain the address comparison mask for the BPAn register */
+
+/******************************************************************************
+ * dr3+(n*5): BPVn (n=0-7) Breakpoint Data Value Register
+ *****************************************************************************/
+
+ /* The BPVn register contains the data value that will be compared with the
+ * incoming load/store data value */
+
+/******************************************************************************
+ * dr4+(n*5): BPCIDn (n=0-7) (Breakpoint Context ID Register)
+ *****************************************************************************/
+#define BPCID_offCID 0 /* CID that will be compared with a process's CID */
+/* bit 9:31 reserved */
+
+#define BPCID_mskCID ( 0x1FF << BPCID_offCID )
+
+/******************************************************************************
+ * dr40: EDM_CFG (EDM Configuration Register)
+ *****************************************************************************/
+#define EDM_CFG_offBC 0 /* Number of hardware breakpoint sets implemented */
+#define EDM_CFG_offDIMU 3 /* Debug Instruction Memory Unit exists */
+/* bit 4:15 reserved */
+#define EDM_CFG_offVER 16 /* EDM version */
+
+#define EDM_CFG_mskBC ( 0x7 << EDM_CFG_offBC )
+#define EDM_CFG_mskDIMU ( 0x1 << EDM_CFG_offDIMU )
+#define EDM_CFG_mskVER ( 0xFFFF << EDM_CFG_offVER )
+
+/******************************************************************************
+ * dr41: EDMSW (EDM Status Word)
+ *****************************************************************************/
+#define EDMSW_offWV 0 /* Write Valid */
+#define EDMSW_offRV 1 /* Read Valid */
+#define EDMSW_offDE 2 /* Debug exception has occurred for this core */
+/* bit 3:31 reserved */
+
+#define EDMSW_mskWV ( 0x1 << EDMSW_offWV )
+#define EDMSW_mskRV ( 0x1 << EDMSW_offRV )
+#define EDMSW_mskDE ( 0x1 << EDMSW_offDE )
+
+/******************************************************************************
+ * dr42: EDM_CTL (EDM Control Register)
+ *****************************************************************************/
+/* bit 0:30 reserved */
+#define EDM_CTL_offV3_EDM_MODE 6 /* EDM compatibility control bit */
+#define EDM_CTL_offDEH_SEL 31 /* Controls where debug exception is directed to */
+
+#define EDM_CTL_mskV3_EDM_MODE ( 0x1 << EDM_CTL_offV3_EDM_MODE )
+#define EDM_CTL_mskDEH_SEL ( 0x1 << EDM_CTL_offDEH_SEL )
+
+/******************************************************************************
+ * dr43: EDM_DTR (EDM Data Transfer Register)
+ *****************************************************************************/
+
+ /* This is used to exchange data between the embedded EDM logic
+ * and the processor core */
+
+/******************************************************************************
+ * dr44: BPMTC (Breakpoint Match Trigger Counter Register)
+ *****************************************************************************/
+#define BPMTC_offBPMTC 0 /* Breakpoint match trigger counter value */
+/* bit 16:31 reserved */
+
+#define BPMTC_mskBPMTC ( 0xFFFF << BPMTC_offBPMTC )
+
+/******************************************************************************
+ * dr45: DIMBR (Debug Instruction Memory Base Register)
+ *****************************************************************************/
+/* bit 0:11 reserved */
+#define DIMBR_offDIMB 12 /* Base address of the Debug Instruction Memory (DIM) */
+#define DIMBR_mskDIMB ( 0xFFFFF << DIMBR_offDIMB )
+
+/******************************************************************************
+ * dr46: TECR0(Trigger Event Control register 0)
+ * dr47: TECR1 (Trigger Event Control register 1)
+ *****************************************************************************/
+#define TECR_offBP 0 /* Controld which BP is used as a trigger source */
+#define TECR_offNMI 8 /* Use NMI as a trigger source */
+#define TECR_offHWINT 9 /* Corresponding interrupt is used as a trigger source */
+#define TECR_offEVIC 15 /* Enable HWINT as a trigger source in EVIC mode */
+#define TECR_offSYS 16 /* Enable SYSCALL instruction as a trigger source */
+#define TECR_offDBG 17 /* Enable debug exception as a trigger source */
+#define TECR_offMRE 18 /* Enable MMU related exception as a trigger source */
+#define TECR_offE 19 /* An exception is used as a trigger source */
+/* bit 20:30 reserved */
+#define TECR_offL 31 /* Link/Cascade TECR0 trigger event to TECR1 trigger event */
+
+#define TECR_mskBP ( 0xFF << TECR_offBP )
+#define TECR_mskNMI ( 0x1 << TECR_offBNMI )
+#define TECR_mskHWINT ( 0x3F << TECR_offBHWINT )
+#define TECR_mskEVIC ( 0x1 << TECR_offBEVIC )
+#define TECR_mskSYS ( 0x1 << TECR_offBSYS )
+#define TECR_mskDBG ( 0x1 << TECR_offBDBG )
+#define TECR_mskMRE ( 0x1 << TECR_offBMRE )
+#define TECR_mskE ( 0x1 << TECR_offE )
+#define TECR_mskL ( 0x1 << TECR_offL )
+
+/******************************************************************************
+ * pfr0-2: PFMC0-2 (Performance Counter Register 0-2)
+ *****************************************************************************/
+
+ /* These registers contains performance event count */
+
+/******************************************************************************
+ * pfr3: PFM_CTL (Performance Counter Control Register)
+ *****************************************************************************/
+#define PFM_CTL_offEN0 0 /* Enable PFMC0 */
+#define PFM_CTL_offEN1 1 /* Enable PFMC1 */
+#define PFM_CTL_offEN2 2 /* Enable PFMC2 */
+#define PFM_CTL_offIE0 3 /* Enable interrupt for PFMC0 */
+#define PFM_CTL_offIE1 4 /* Enable interrupt for PFMC1 */
+#define PFM_CTL_offIE2 5 /* Enable interrupt for PFMC2 */
+#define PFM_CTL_offOVF0 6 /* Overflow bit of PFMC0 */
+#define PFM_CTL_offOVF1 7 /* Overflow bit of PFMC1 */
+#define PFM_CTL_offOVF2 8 /* Overflow bit of PFMC2 */
+#define PFM_CTL_offKS0 9 /* Enable superuser mode event counting for PFMC0 */
+#define PFM_CTL_offKS1 10 /* Enable superuser mode event counting for PFMC1 */
+#define PFM_CTL_offKS2 11 /* Enable superuser mode event counting for PFMC2 */
+#define PFM_CTL_offKU0 12 /* Enable user mode event counting for PFMC0 */
+#define PFM_CTL_offKU1 13 /* Enable user mode event counting for PFMC1 */
+#define PFM_CTL_offKU2 14 /* Enable user mode event counting for PFMC2 */
+#define PFM_CTL_offSEL0 15 /* The event selection for PFMC0 */
+#define PFM_CTL_offSEL1 21 /* The event selection for PFMC1 */
+#define PFM_CTL_offSEL2 27 /* The event selection for PFMC2 */
+/* bit 28:31 reserved */
+
+#define PFM_CTL_mskEN0 ( 0x01 << PFM_CTL_offEN0 )
+#define PFM_CTL_mskEN1 ( 0x01 << PFM_CTL_offEN1 )
+#define PFM_CTL_mskEN2 ( 0x01 << PFM_CTL_offEN2 )
+#define PFM_CTL_mskIE0 ( 0x01 << PFM_CTL_offIE0 )
+#define PFM_CTL_mskIE1 ( 0x01 << PFM_CTL_offIE1 )
+#define PFM_CTL_mskIE2 ( 0x01 << PFM_CTL_offIE2 )
+#define PFM_CTL_mskOVF0 ( 0x01 << PFM_CTL_offOVF0 )
+#define PFM_CTL_mskOVF1 ( 0x01 << PFM_CTL_offOVF1 )
+#define PFM_CTL_mskOVF2 ( 0x01 << PFM_CTL_offOVF2 )
+#define PFM_CTL_mskKS0 ( 0x01 << PFM_CTL_offKS0 )
+#define PFM_CTL_mskKS1 ( 0x01 << PFM_CTL_offKS1 )
+#define PFM_CTL_mskKS2 ( 0x01 << PFM_CTL_offKS2 )
+#define PFM_CTL_mskKU0 ( 0x01 << PFM_CTL_offKU0 )
+#define PFM_CTL_mskKU1 ( 0x01 << PFM_CTL_offKU1 )
+#define PFM_CTL_mskKU2 ( 0x01 << PFM_CTL_offKU2 )
+#define PFM_CTL_mskSEL0 ( 0x01 << PFM_CTL_offSEL0 )
+#define PFM_CTL_mskSEL1 ( 0x3F << PFM_CTL_offSEL1 )
+#define PFM_CTL_mskSEL2 ( 0x3F << PFM_CTL_offSEL2 )
+
+/******************************************************************************
+ * SDZ_CTL (Structure Downsizing Control Register)
+ *****************************************************************************/
+#define SDZ_CTL_offICDZ 0 /* I-cache downsizing control */
+#define SDZ_CTL_offDCDZ 3 /* D-cache downsizing control */
+#define SDZ_CTL_offMTBDZ 6 /* MTLB downsizing control */
+#define SDZ_CTL_offBTBDZ 9 /* Branch Target Table downsizing control */
+/* bit 12:31 reserved */
+#define SDZ_CTL_mskICDZ ( 0x07 << SDZ_CTL_offICDZ )
+#define SDZ_CTL_mskDCDZ ( 0x07 << SDZ_CTL_offDCDZ )
+#define SDZ_CTL_mskMTBDZ ( 0x07 << SDZ_CTL_offMTBDZ )
+#define SDZ_CTL_mskBTBDZ ( 0x07 << SDZ_CTL_offBTBDZ )
+
+/******************************************************************************
+ * N13MISC_CTL (N13 Miscellaneous Control Register)
+ *****************************************************************************/
+#define N13MISC_CTL_offBTB 0 /* Disable Branch Target Buffer */
+#define N13MISC_CTL_offRTP 1 /* Disable Return Target Predictor */
+#define N13MISC_CTL_offPTEPF 2 /* Disable HPTWK L2 PTE pefetch */
+#define N13MISC_CTL_offSP_SHADOW_EN 4 /* Enable shadow stack pointers */
+/* bit 6, 9:31 reserved */
+
+#define N13MISC_CTL_makBTB ( 0x1 << N13MISC_CTL_offBTB )
+#define N13MISC_CTL_makRTP ( 0x1 << N13MISC_CTL_offRTP )
+#define N13MISC_CTL_makPTEPF ( 0x1 << N13MISC_CTL_offPTEPF )
+#define N13MISC_CTL_makSP_SHADOW_EN ( 0x1 << N13MISC_CTL_offSP_SHADOW_EN )
+
+#define MISC_init (N13MISC_CTL_makBTB|N13MISC_CTL_makRTP|N13MISC_CTL_makSP_SHADOW_EN)
+
+/******************************************************************************
+ * PRUSR_ACC_CTL (Privileged Resource User Access Control Registers)
+ *****************************************************************************/
+#define PRUSR_ACC_CTL_offDMA_EN 0 /* Allow user mode access of DMA registers */
+#define PRUSR_ACC_CTL_offPFM_EN 1 /* Allow user mode access of PFM registers */
+
+#define PRUSR_ACC_CTL_mskDMA_EN ( 0x1 << PRUSR_ACC_CTL_offDMA_EN )
+#define PRUSR_ACC_CTL_mskPFM_EN ( 0x1 << PRUSR_ACC_CTL_offPFM_EN )
+
+/******************************************************************************
+ * dmar0: DMA_CFG (DMA Configuration Register)
+ *****************************************************************************/
+#define DMA_CFG_offNCHN 0 /* The number of DMA channels implemented */
+#define DMA_CFG_offUNEA 2 /* Un-aligned External Address transfer feature */
+#define DMA_CFG_off2DET 3 /* 2-D Element Transfer feature */
+/* bit 4:15 reserved */
+#define DMA_CFG_offVER 16 /* DMA architecture and implementation version */
+
+#define DMA_CFG_mskNCHN ( 0x3 << DMA_CFG_offNCHN )
+#define DMA_CFG_mskUNEA ( 0x1 << DMA_CFG_offUNEA )
+#define DMA_CFG_msk2DET ( 0x1 << DMA_CFG_off2DET )
+#define DMA_CFG_mskVER ( 0xFFFF << DMA_CFG_offVER )
+
+/******************************************************************************
+ * dmar1: DMA_GCSW (DMA Global Control and Status Word Register)
+ *****************************************************************************/
+#define DMA_GCSW_offC0STAT 0 /* DMA channel 0 state */
+#define DMA_GCSW_offC1STAT 3 /* DMA channel 1 state */
+/* bit 6:11 reserved */
+#define DMA_GCSW_offC0INT 12 /* DMA channel 0 generate interrupt */
+#define DMA_GCSW_offC1INT 13 /* DMA channel 1 generate interrupt */
+/* bit 14:30 reserved */
+#define DMA_GCSW_offEN 31 /* Enable DMA engine */
+
+#define DMA_GCSW_mskC0STAT ( 0x7 << DMA_GCSW_offC0STAT )
+#define DMA_GCSW_mskC1STAT ( 0x7 << DMA_GCSW_offC1STAT )
+#define DMA_GCSW_mskC0INT ( 0x1 << DMA_GCSW_offC0INT )
+#define DMA_GCSW_mskC1INT ( 0x1 << DMA_GCSW_offC1INT )
+#define DMA_GCSW_mskEN ( 0x1 << DMA_GCSW_offEN )
+
+/******************************************************************************
+ * dmar2: DMA_CHNSEL (DMA Channel Selection Register)
+ *****************************************************************************/
+#define DMA_CHNSEL_offCHAN 0 /* Selected channel number */
+/* bit 2:31 reserved */
+
+#define DMA_CHNSEL_mskCHAN ( 0x3 << DMA_CHNSEL_offCHAN )
+
+/******************************************************************************
+ * dmar3: DMA_ACT (DMA Action Register)
+ *****************************************************************************/
+#define DMA_ACT_offACMD 0 /* DMA Action Command */
+/* bit 2:31 reserved */
+#define DMA_ACT_mskACMD ( 0x3 << DMA_ACT_offACMD )
+
+/******************************************************************************
+ * dmar4: DMA_SETUP (DMA Setup Register)
+ *****************************************************************************/
+#define DMA_SETUP_offLM 0 /* Local Memory Selection */
+#define DMA_SETUP_offTDIR 1 /* Transfer Direction */
+#define DMA_SETUP_offTES 2 /* Transfer Element Size */
+#define DMA_SETUP_offESTR 4 /* External memory transfer Stride */
+#define DMA_SETUP_offCIE 16 /* Interrupt Enable on Completion */
+#define DMA_SETUP_offSIE 17 /* Interrupt Enable on explicit Stop */
+#define DMA_SETUP_offEIE 18 /* Interrupt Enable on Error */
+#define DMA_SETUP_offUE 19 /* Enable the Un-aligned External Address */
+#define DMA_SETUP_off2DE 20 /* Enable the 2-D External Transfer */
+#define DMA_SETUP_offCOA 21 /* Transfer Coalescable */
+/* bit 22:31 reserved */
+
+#define DMA_SETUP_mskLM ( 0x1 << DMA_SETUP_offLM )
+#define DMA_SETUP_mskTDIR ( 0x1 << DMA_SETUP_offTDIR )
+#define DMA_SETUP_mskTES ( 0x3 << DMA_SETUP_offTES )
+#define DMA_SETUP_mskESTR ( 0xFFF << DMA_SETUP_offESTR )
+#define DMA_SETUP_mskCIE ( 0x1 << DMA_SETUP_offCIE )
+#define DMA_SETUP_mskSIE ( 0x1 << DMA_SETUP_offSIE )
+#define DMA_SETUP_mskEIE ( 0x1 << DMA_SETUP_offEIE )
+#define DMA_SETUP_mskUE ( 0x1 << DMA_SETUP_offUE )
+#define DMA_SETUP_msk2DE ( 0x1 << DMA_SETUP_off2DE )
+#define DMA_SETUP_mskCOA ( 0x1 << DMA_SETUP_offCOA )
+
+/******************************************************************************
+ * dmar5: DMA_ISADDR (DMA Internal Start Address Register)
+ *****************************************************************************/
+#define DMA_ISADDR_offISADDR 0 /* Internal Start Address */
+/* bit 20:31 reserved */
+#define DMA_ISADDR_mskISADDR ( 0xFFFFF << DMA_ISADDR_offISADDR )
+
+/******************************************************************************
+ * dmar6: DMA_ESADDR (DMA External Start Address Register)
+ *****************************************************************************/
+/* This register holds External Start Address */
+
+/******************************************************************************
+ * dmar7: DMA_TCNT (DMA Transfer Element Count Register)
+ *****************************************************************************/
+#define DMA_TCNT_offTCNT 0 /* DMA transfer element count */
+/* bit 18:31 reserved */
+#define DMA_TCNT_mskTCNT ( 0x3FFFF << DMA_TCNT_offTCNT )
+
+/******************************************************************************
+ * dmar8: DMA_STATUS (DMA Status Register)
+ *****************************************************************************/
+#define DMA_STATUS_offSTAT 0 /* DMA channel state */
+#define DMA_STATUS_offSTUNA 3 /* Un-aligned error on External Stride value */
+#define DMA_STATUS_offDERR 4 /* DMA Transfer Disruption Error */
+#define DMA_STATUS_offEUNA 5 /* Un-aligned error on the External address */
+#define DMA_STATUS_offIUNA 6 /* Un-aligned error on the Internal address */
+#define DMA_STATUS_offIOOR 7 /* Out-Of-Range error on the Internal address */
+#define DMA_STATUS_offEBUS 8 /* Bus Error on an External DMA transfer */
+#define DMA_STATUS_offESUP 9 /* DMA setup error */
+/* bit 10:31 reserved */
+
+#define DMA_STATUS_mskSTAT ( 0x7 << DMA_STATUS_offSTAT )
+#define DMA_STATUS_mskSTUNA ( 0x1 << DMDMA_STATUS_offSTUNA )
+#define DMA_STATUS_mskDERR ( 0x1 << DMDMA_STATUS_offDERR )
+#define DMA_STATUS_mskEUNA ( 0x1 << DMDMA_STATUS_offEUNA )
+#define DMA_STATUS_mskIUNA ( 0x1 << DMDMA_STATUS_offIUNA )
+#define DMA_STATUS_mskIOOR ( 0x1 << DMDMA_STATUS_offIOOR )
+#define DMA_STATUS_mskEBUS ( 0x1 << DMDMA_STATUS_offEBUS )
+#define DMA_STATUS_mskESUP ( 0x1 << DMDMA_STATUS_offESUP )
+
+/******************************************************************************
+ * dmar9: DMA_2DSET (DMA 2D Setup Register)
+ *****************************************************************************/
+#define DMA_2DSET_offWECNT 0 /* The Width Element Count for a 2-D region */
+#define DMA_2DSET_offHTSTR 16 /* The Height Stride for a 2-D region */
+
+#define DMA_2DSET_mskHTSTR ( 0xFFFF << DMA_2DSET_offHTSTR )
+#define DMA_2DSET_mskWECNT ( 0xFFFF << DMA_2DSET_offWECNT )
+
+/******************************************************************************
+ * dmar10: DMA_2DSCTL (DMA 2D Startup Control Register)
+ *****************************************************************************/
+#define DMA_2DSCTL_offSTWECNT 0 /* Startup Width Element Count for a 2-D region */
+/* bit 16:31 reserved */
+
+#define DMA_2DSCTL_mskSTWECNT ( 0xFFFF << DMA_2DSCTL_offSTWECNT )
+
+/******************************************************************************
+ * fpcsr: FPCSR (Floating-Point Control Status Register)
+ *****************************************************************************/
+#define FPCSR_offRM 0
+#define FPCSR_offIVO 2
+#define FPCSR_offDBZ 3
+#define FPCSR_offOVF 4
+#define FPCSR_offUDF 5
+#define FPCSR_offIEX 6
+#define FPCSR_offIVOE 7
+#define FPCSR_offDBZE 8
+#define FPCSR_offOVFE 9
+#define FPCSR_offUDFE 10
+#define FPCSR_offIEXE 11
+#define FPCSR_offDNZ 12
+#define FPCSR_offIVOT 13
+#define FPCSR_offDBZT 14
+#define FPCSR_offOVFT 15
+#define FPCSR_offUDFT 16
+#define FPCSR_offIEXT 17
+#define FPCSR_offDNIT 18
+#define FPCSR_offRIT 19
+
+#define FPCSR_mskRM ( 0x3 << FPCSR_offRM )
+#define FPCSR_mskIVO ( 0x1 << FPCSR_offIVO )
+#define FPCSR_mskDBZ ( 0x1 << FPCSR_offDBZ )
+#define FPCSR_mskOVF ( 0x1 << FPCSR_offOVF )
+#define FPCSR_mskUDF ( 0x1 << FPCSR_offUDF )
+#define FPCSR_mskIEX ( 0x1 << FPCSR_offIEX )
+#define FPCSR_mskIVOE ( 0x1 << FPCSR_offIVOE )
+#define FPCSR_mskDBZE ( 0x1 << FPCSR_offDBZE )
+#define FPCSR_mskOVFE ( 0x1 << FPCSR_offOVFE )
+#define FPCSR_mskUDFE ( 0x1 << FPCSR_offUDFE )
+#define FPCSR_mskIEXE ( 0x1 << FPCSR_offIEXE )
+#define FPCSR_mskDNZ ( 0x1 << FPCSR_offDNZ )
+#define FPCSR_mskIVOT ( 0x1 << FPCSR_offIVOT )
+#define FPCSR_mskDBZT ( 0x1 << FPCSR_offDBZT )
+#define FPCSR_mskOVFT ( 0x1 << FPCSR_offOVFT )
+#define FPCSR_mskUDFT ( 0x1 << FPCSR_offUDFT )
+#define FPCSR_mskIEXT ( 0x1 << FPCSR_offIEXT )
+#define FPCSR_mskDNIT ( 0x1 << FPCSR_offDNIT )
+#define FPCSR_mskRIT ( 0x1 << FPCSR_offRIT )
+#define FPCSR_mskALL (FPCSR_mskIVO | FPCSR_mskDBZ | FPCSR_mskOVF | FPCSR_mskUDF | FPCSR_mskIEX)
+#define FPCSR_mskALLE (FPCSR_mskIVOE | FPCSR_mskDBZE | FPCSR_mskOVFE | FPCSR_mskUDFE | FPCSR_mskIEXE)
+#define FPCSR_mskALLT (FPCSR_mskIVOT | FPCSR_mskDBZT | FPCSR_mskOVFT | FPCSR_mskUDFT | FPCSR_mskIEXT |FPCSR_mskDNIT | FPCSR_mskRIT)
+
+/******************************************************************************
+ * fpcfg: FPCFG (Floating-Point Configuration Register)
+ *****************************************************************************/
+#define FPCFG_offSP 0
+#define FPCFG_offDP 1
+#define FPCFG_offFREG 2
+#define FPCFG_offFMA 4
+#define FPCFG_offIMVER 22
+#define FPCFG_offAVER 27
+
+#define FPCFG_mskSP ( 0x1 << FPCFG_offSP )
+#define FPCFG_mskDP ( 0x1 << FPCFG_offDP )
+#define FPCFG_mskFREG ( 0x3 << FPCFG_offFREG )
+#define FPCFG_mskFMA ( 0x1 << FPCFG_offFMA )
+#define FPCFG_mskIMVER ( 0x1F << FPCFG_offIMVER )
+#define FPCFG_mskAVER ( 0x1F << FPCFG_offAVER )
+
+/******************************************************************************
+ * fucpr: FUCOP_CTL (FPU and Coprocessor Enable Control Register)
+ *****************************************************************************/
+#define FUCOP_CTL_offCP0EN 0
+#define FUCOP_CTL_offCP1EN 1
+#define FUCOP_CTL_offCP2EN 2
+#define FUCOP_CTL_offCP3EN 3
+#define FUCOP_CTL_offAUEN 31
+
+#define FUCOP_CTL_mskCP0EN ( 0x1 << FUCOP_CTL_offCP0EN )
+#define FUCOP_CTL_mskCP1EN ( 0x1 << FUCOP_CTL_offCP1EN )
+#define FUCOP_CTL_mskCP2EN ( 0x1 << FUCOP_CTL_offCP2EN )
+#define FUCOP_CTL_mskCP3EN ( 0x1 << FUCOP_CTL_offCP3EN )
+#define FUCOP_CTL_mskAUEN ( 0x1 << FUCOP_CTL_offAUEN )
+
+#endif /* __NDS32_BITFIELD_H__ */
diff --git a/arch/nds32/include/asm/nds32.h b/arch/nds32/include/asm/nds32.h
new file mode 100644
index 0000000..edaa286
--- /dev/null
+++ b/arch/nds32/include/asm/nds32.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _ASM_NDS32_NDS32_H_
+#define _ASM_NDS32_NDS32_H_
+
+#include <asm/bitfield.h>
+#include <asm/cachectl.h>
+
+#ifndef __ASSEMBLY__
+#include <asm/barrier.h>
+#include <nds32_intrinsic.h>
+
+#ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
+#define FP_OFFSET (-3)
+#else
+#define FP_OFFSET (-2)
+#endif
+
+static inline void GIE_ENABLE(void)
+{
+ mb();
+ __nds32__gie_en();
+}
+
+static inline void GIE_DISABLE(void)
+{
+ mb();
+ __nds32__gie_dis();
+}
+
+static inline unsigned long CACHE_SET(unsigned char cache)
+{
+
+ if (cache == ICACHE)
+ return 64 << ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISET) >>
+ ICM_CFG_offISET);
+ else
+ return 64 << ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSET) >>
+ DCM_CFG_offDSET);
+}
+
+static inline unsigned long CACHE_WAY(unsigned char cache)
+{
+
+ if (cache == ICACHE)
+ return 1 +
+ ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskIWAY) >> ICM_CFG_offIWAY);
+ else
+ return 1 +
+ ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDWAY) >> DCM_CFG_offDWAY);
+}
+
+static inline unsigned long CACHE_LINE_SIZE(unsigned char cache)
+{
+
+ if (cache == ICACHE)
+ return 8 <<
+ (((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISZ) >> ICM_CFG_offISZ) - 1);
+ else
+ return 8 <<
+ (((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSZ) >> DCM_CFG_offDSZ) - 1);
+}
+
+#endif /* __ASSEMBLY__ */
+
+/* tbl and why is used in ex-scall.S and ex-exit.S */
+#define tbl $r8
+#define why $r8
+
+#define IVB_BASE PHYS_OFFSET /* in user space for intr/exc/trap/break table base, 64KB aligned
+ * We defined at the start of the physical memory */
+
+/* dispatched sub-entry exception handler numbering */
+#define RD_PROT 0 /* read protrection */
+#define WRT_PROT 1 /* write protection */
+#define NOEXEC 2 /* non executable */
+#define PAGE_MODIFY 3 /* page modified */
+#define ACC_BIT 4 /* access bit */
+#define RESVED_PTE 5 /* reserved PTE attribute */
+/* reserved 6 ~ 16 */
+
+#endif /* _ASM_NDS32_NDS32_H_ */
diff --git a/arch/nds32/kernel/asm-offsets.c b/arch/nds32/kernel/asm-offsets.c
new file mode 100644
index 0000000..bfbd4ac
--- /dev/null
+++ b/arch/nds32/kernel/asm-offsets.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/sched.h>
+#include <linux/sched/task_stack.h>
+#include <linux/kbuild.h>
+#include <asm/thread_info.h>
+#include <asm/ptrace.h>
+
+int main(void)
+{
+ DEFINE(TSK_TI_FLAGS, offsetof(struct task_struct, thread_info.flags));
+ DEFINE(TSK_TI_PREEMPT,
+ offsetof(struct task_struct, thread_info.preempt_count));
+ DEFINE(THREAD_CPU_CONTEXT,
+ offsetof(struct task_struct, thread.cpu_context));
+ DEFINE(OSP_OFFSET, offsetof(struct pt_regs, osp));
+ DEFINE(SP_OFFSET, offsetof(struct pt_regs, sp));
+ DEFINE(FUCOP_CTL_OFFSET, offsetof(struct pt_regs, fucop_ctl));
+ DEFINE(IPSW_OFFSET, offsetof(struct pt_regs, ipsw));
+ DEFINE(SYSCALLNO_OFFSET, offsetof(struct pt_regs, syscallno));
+ DEFINE(IPC_OFFSET, offsetof(struct pt_regs, ipc));
+ DEFINE(R0_OFFSET, offsetof(struct pt_regs, uregs[0]));
+ DEFINE(R15_OFFSET, offsetof(struct pt_regs, uregs[15]));
+ DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
+ DEFINE(CLOCK_COARSE_RES, LOW_RES_NSEC);
+ return 0;
+}
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 00/35] Andes(nds32) Linux Kernel Port
From: Greentime Hu @ 2017-11-27 12:27 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial
Cc: Greentime Hu
This is the 2nd version patchset to add the Linux kernel port for Andes(nds32)
processors. Almost all of the feedback from v1 patchseries has been addressed.
Thanks to everyone who provided feedback on the previous version.
This patchset adds core architecture support to Linux for Andestech's
N13, N15, D15, N10, D10 processor cores.
Based on the 16/32-bit AndeStar RISC-like architecture, we designed the
configurable AndesCore series of embedded processor families. AndesCores
range from highly performance-efficient small-footprint cores for
microcontrollers and deeply-embedded applications to 1GHz+ cores running
Linux, covering general-purpose N-series cores for a wide range of computing
need, DSP-capable D-series cores for digital signal control,
instruction-extensible E-series cores for application-specific acceleration,
and secure S-series cores for best protection of the most valuable.
The patches are based on v4.14-rc8, and can also be found in the
following git tree:
https://github.com/andestech/linux.git nds32-4.14-rc8-v2
The build script and toolchain repositories are able to be found here:
https://github.com/andestech/build_script.git
Freely available instruction set and architecture overview documents can
be found on the following page:
http://www.andestech.com/product.php?cls=9
Vincent Ren-Wei Chen and I will maintain this port. Thanks to everyone who
helped us and contributed to it. :) Any feedback is welcome.
Changes in v2:
- Set GENERIC_CALIBRATE_DELAY default n
- Add earlycon support
- Remove earlyprintk
- Add CPU_BIG_ENDIAN, CPU_LITTLE_ENDIAN support
- Refine unalignment access exception handler
- Add VMSPLIT support
- Use only one defconfig
- Change interrupt-cells from 2 to 1
- Refine andestech cpu names in bindings/nds32/cpus.txt
- Get clock frequency in dts because fpga bitmap doesn't include this feature
- Update MAINTAINERS for bindings
- Remove unused configs in Kconfig
- Refine device tree scripts
- Refine coding style
- Use generic ioremap_nocache
- Remove L2CC_PA_BASE define and its codes in head.S. It will be moved to bootloader.
- Set PHYS_OFFSET to 0x0 instead of CONFIG_MEMORY_START
- Remove unused macros
- Simplify cpu_cache_* API
- Change __asm__ __volatile__ to asm volatile
- Refine uaccess.h
- Remove unused/deprecated syscall
- Use generic posix_types.h
- Remove arch_trace_hardirqs_on/arch_trace_hardirqs_off
- Fix bug of restart syscall
- Refine syscall implementations
- Use IS_ENABLED to replace ifdef as possible
- Remove device_initcall(nds32_device_probe)
- Refine vdso implementations
- Refine copy_from_user()/copy_to_user()/clear_user()/get_user()/memmove()/memcpy()
- Refine ioremap.c
- Refine irq-ativic32.c
- Fix a bug of earlycon.c
- Export ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt
- Add atcpit100 driver
Greentime Hu (32):
nds32: Assembly macros and definitions
nds32: Kernel booting and initialization
nds32: Exception handling
nds32: MMU definitions
nds32: MMU initialization
nds32: MMU fault handling and page table management
nds32: Cache and TLB routines
nds32: Process management
nds32: IRQ handling
nds32: Atomic operations
nds32: Device specific operations
nds32: DMA mapping API
nds32: ELF definitions
nds32: System calls handling
nds32: VDSO support
nds32: Signal handling support
nds32: Library functions
nds32: Debugging support
nds32: L2 cache support
nds32: Loadable modules
nds32: Generic timers support
nds32: Device tree support
nds32: Miscellaneous header files
nds32: defconfig
nds32: Build infrastructure
dt-bindings: interrupt-controller: Andestech Internal Vector
Interrupt Controller
irqchip: Andestech Internal Vector Interrupt Controller driver
MAINTAINERS: Add nds32
dt-bindings: nds32 CPU Bindings
net: faraday add nds32 support.
earlycon: add reg-offset to physical address before mapping
asm-generic/io.h: move
ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef
CONFIG_MMU
Rick Chen (3):
clocksource/drivers/atcpit100: Add andestech atcpit100 timer
clocksource/drivers/Kconfig: Support andestech atcpit100 timer
dt-bindings: timer: Add andestech atcpit100 timer binding doc
.../interrupt-controller/andestech,ativic32.txt | 19 +
Documentation/devicetree/bindings/nds32/cpus.txt | 32 +
.../bindings/timer/andestech,atcpit100-timer.txt | 33 +
MAINTAINERS | 11 +
arch/nds32/Kconfig | 107 +++
arch/nds32/Kconfig.cpu | 131 +++
arch/nds32/Makefile | 66 ++
arch/nds32/boot/Makefile | 15 +
arch/nds32/boot/dts/Makefile | 8 +
arch/nds32/boot/dts/ae3xx.dts | 55 ++
arch/nds32/boot/dts/ag101p.dts | 60 ++
arch/nds32/configs/defconfig | 111 +++
arch/nds32/include/asm/Kbuild | 54 ++
arch/nds32/include/asm/assembler.h | 52 ++
arch/nds32/include/asm/bitfield.h | 974 ++++++++++++++++++++
arch/nds32/include/asm/cache.h | 25 +
arch/nds32/include/asm/cache_info.h | 26 +
arch/nds32/include/asm/cacheflush.h | 57 ++
arch/nds32/include/asm/current.h | 25 +
arch/nds32/include/asm/delay.h | 51 +
arch/nds32/include/asm/dma-mapping.h | 27 +
arch/nds32/include/asm/elf.h | 192 ++++
arch/nds32/include/asm/fixmap.h | 42 +
arch/nds32/include/asm/futex.h | 116 +++
arch/nds32/include/asm/highmem.h | 78 ++
arch/nds32/include/asm/io.h | 25 +
arch/nds32/include/asm/irqflags.h | 49 +
arch/nds32/include/asm/l2_cache.h | 155 ++++
arch/nds32/include/asm/linkage.h | 24 +
arch/nds32/include/asm/memory.h | 118 +++
arch/nds32/include/asm/mmu.h | 25 +
arch/nds32/include/asm/mmu_context.h | 81 ++
arch/nds32/include/asm/module.h | 24 +
arch/nds32/include/asm/nds32.h | 96 ++
arch/nds32/include/asm/page.h | 78 ++
arch/nds32/include/asm/pgalloc.h | 109 +++
arch/nds32/include/asm/pgtable.h | 426 +++++++++
arch/nds32/include/asm/proc-fns.h | 57 ++
arch/nds32/include/asm/processor.h | 116 +++
arch/nds32/include/asm/ptrace.h | 79 ++
arch/nds32/include/asm/shmparam.h | 32 +
arch/nds32/include/asm/spinlock.h | 184 ++++
arch/nds32/include/asm/string.h | 30 +
arch/nds32/include/asm/swab.h | 48 +
arch/nds32/include/asm/syscall.h | 203 ++++
arch/nds32/include/asm/syscalls.h | 27 +
arch/nds32/include/asm/thread_info.h | 91 ++
arch/nds32/include/asm/tlb.h | 41 +
arch/nds32/include/asm/tlbflush.h | 60 ++
arch/nds32/include/asm/uaccess.h | 296 ++++++
arch/nds32/include/asm/unistd.h | 19 +
arch/nds32/include/asm/vdso.h | 35 +
arch/nds32/include/asm/vdso_datapage.h | 51 +
arch/nds32/include/uapi/asm/Kbuild | 27 +
arch/nds32/include/uapi/asm/auxvec.h | 25 +
arch/nds32/include/uapi/asm/byteorder.h | 26 +
arch/nds32/include/uapi/asm/cachectl.h | 19 +
arch/nds32/include/uapi/asm/param.h | 24 +
arch/nds32/include/uapi/asm/ptrace.h | 42 +
arch/nds32/include/uapi/asm/sigcontext.h | 73 ++
arch/nds32/include/uapi/asm/signal.h | 23 +
arch/nds32/include/uapi/asm/unistd.h | 32 +
arch/nds32/kernel/Makefile | 23 +
arch/nds32/kernel/asm-offsets.c | 41 +
arch/nds32/kernel/atl2c.c | 77 ++
arch/nds32/kernel/cacheinfo.c | 62 ++
arch/nds32/kernel/devtree.c | 45 +
arch/nds32/kernel/dma.c | 472 ++++++++++
arch/nds32/kernel/ex-entry.S | 170 ++++
arch/nds32/kernel/ex-exit.S | 206 +++++
arch/nds32/kernel/ex-scall.S | 145 +++
arch/nds32/kernel/head.S | 198 ++++
arch/nds32/kernel/irq.c | 22 +
arch/nds32/kernel/module.c | 299 ++++++
arch/nds32/kernel/nds32_ksyms.c | 44 +
arch/nds32/kernel/process.c | 217 +++++
arch/nds32/kernel/ptrace.c | 325 +++++++
arch/nds32/kernel/setup.c | 407 ++++++++
arch/nds32/kernel/signal.c | 354 +++++++
arch/nds32/kernel/stacktrace.c | 60 ++
arch/nds32/kernel/sys_nds32.c | 74 ++
arch/nds32/kernel/syscall_table.c | 28 +
arch/nds32/kernel/time.c | 22 +
arch/nds32/kernel/traps.c | 441 +++++++++
arch/nds32/kernel/vdso.c | 245 +++++
arch/nds32/kernel/vdso/Makefile | 82 ++
arch/nds32/kernel/vdso/datapage.S | 34 +
arch/nds32/kernel/vdso/gen_vdso_offsets.sh | 15 +
arch/nds32/kernel/vdso/gettimeofday.c | 266 ++++++
arch/nds32/kernel/vdso/note.S | 29 +
arch/nds32/kernel/vdso/sigreturn.S | 33 +
arch/nds32/kernel/vdso/vdso.S | 33 +
arch/nds32/kernel/vdso/vdso.lds.S | 87 ++
arch/nds32/kernel/vmlinux.lds.S | 70 ++
arch/nds32/lib/Makefile | 3 +
arch/nds32/lib/clear_user.S | 55 ++
arch/nds32/lib/copy_from_user.S | 58 ++
arch/nds32/lib/copy_page.S | 50 +
arch/nds32/lib/copy_template.S | 83 ++
arch/nds32/lib/copy_to_user.S | 58 ++
arch/nds32/lib/memcpy.S | 43 +
arch/nds32/lib/memmove.S | 83 ++
arch/nds32/lib/memset.S | 46 +
arch/nds32/lib/memzero.S | 31 +
arch/nds32/mm/Makefile | 7 +
arch/nds32/mm/alignment.c | 622 +++++++++++++
arch/nds32/mm/cacheflush.c | 331 +++++++
arch/nds32/mm/extable.c | 29 +
arch/nds32/mm/fault.c | 420 +++++++++
arch/nds32/mm/highmem.c | 92 ++
arch/nds32/mm/init.c | 318 +++++++
arch/nds32/mm/ioremap.c | 75 ++
arch/nds32/mm/mm-nds32.c | 103 +++
arch/nds32/mm/mmap.c | 86 ++
arch/nds32/mm/proc.c | 601 ++++++++++++
arch/nds32/mm/tlb.c | 63 ++
drivers/clocksource/Kconfig | 6 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-atcpit100.c | 247 +++++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-ativic32.c | 119 +++
drivers/net/ethernet/faraday/Kconfig | 6 +-
drivers/tty/serial/earlycon.c | 3 +-
include/asm-generic/io.h | 18 +-
124 files changed, 13508 insertions(+), 13 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt
create mode 100644 Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
create mode 100644 arch/nds32/Kconfig
create mode 100644 arch/nds32/Kconfig.cpu
create mode 100644 arch/nds32/Makefile
create mode 100644 arch/nds32/boot/Makefile
create mode 100644 arch/nds32/boot/dts/Makefile
create mode 100644 arch/nds32/boot/dts/ae3xx.dts
create mode 100644 arch/nds32/boot/dts/ag101p.dts
create mode 100644 arch/nds32/configs/defconfig
create mode 100644 arch/nds32/include/asm/Kbuild
create mode 100644 arch/nds32/include/asm/assembler.h
create mode 100644 arch/nds32/include/asm/bitfield.h
create mode 100644 arch/nds32/include/asm/cache.h
create mode 100644 arch/nds32/include/asm/cache_info.h
create mode 100644 arch/nds32/include/asm/cacheflush.h
create mode 100644 arch/nds32/include/asm/current.h
create mode 100644 arch/nds32/include/asm/delay.h
create mode 100644 arch/nds32/include/asm/dma-mapping.h
create mode 100644 arch/nds32/include/asm/elf.h
create mode 100644 arch/nds32/include/asm/fixmap.h
create mode 100644 arch/nds32/include/asm/futex.h
create mode 100644 arch/nds32/include/asm/highmem.h
create mode 100644 arch/nds32/include/asm/io.h
create mode 100644 arch/nds32/include/asm/irqflags.h
create mode 100644 arch/nds32/include/asm/l2_cache.h
create mode 100644 arch/nds32/include/asm/linkage.h
create mode 100644 arch/nds32/include/asm/memory.h
create mode 100644 arch/nds32/include/asm/mmu.h
create mode 100644 arch/nds32/include/asm/mmu_context.h
create mode 100644 arch/nds32/include/asm/module.h
create mode 100644 arch/nds32/include/asm/nds32.h
create mode 100644 arch/nds32/include/asm/page.h
create mode 100644 arch/nds32/include/asm/pgalloc.h
create mode 100644 arch/nds32/include/asm/pgtable.h
create mode 100644 arch/nds32/include/asm/proc-fns.h
create mode 100644 arch/nds32/include/asm/processor.h
create mode 100644 arch/nds32/include/asm/ptrace.h
create mode 100644 arch/nds32/include/asm/shmparam.h
create mode 100644 arch/nds32/include/asm/spinlock.h
create mode 100644 arch/nds32/include/asm/string.h
create mode 100644 arch/nds32/include/asm/swab.h
create mode 100644 arch/nds32/include/asm/syscall.h
create mode 100644 arch/nds32/include/asm/syscalls.h
create mode 100644 arch/nds32/include/asm/thread_info.h
create mode 100644 arch/nds32/include/asm/tlb.h
create mode 100644 arch/nds32/include/asm/tlbflush.h
create mode 100644 arch/nds32/include/asm/uaccess.h
create mode 100644 arch/nds32/include/asm/unistd.h
create mode 100644 arch/nds32/include/asm/vdso.h
create mode 100644 arch/nds32/include/asm/vdso_datapage.h
create mode 100644 arch/nds32/include/uapi/asm/Kbuild
create mode 100644 arch/nds32/include/uapi/asm/auxvec.h
create mode 100644 arch/nds32/include/uapi/asm/byteorder.h
create mode 100644 arch/nds32/include/uapi/asm/cachectl.h
create mode 100644 arch/nds32/include/uapi/asm/param.h
create mode 100644 arch/nds32/include/uapi/asm/ptrace.h
create mode 100644 arch/nds32/include/uapi/asm/sigcontext.h
create mode 100644 arch/nds32/include/uapi/asm/signal.h
create mode 100644 arch/nds32/include/uapi/asm/unistd.h
create mode 100644 arch/nds32/kernel/Makefile
create mode 100644 arch/nds32/kernel/asm-offsets.c
create mode 100644 arch/nds32/kernel/atl2c.c
create mode 100644 arch/nds32/kernel/cacheinfo.c
create mode 100644 arch/nds32/kernel/devtree.c
create mode 100644 arch/nds32/kernel/dma.c
create mode 100644 arch/nds32/kernel/ex-entry.S
create mode 100644 arch/nds32/kernel/ex-exit.S
create mode 100644 arch/nds32/kernel/ex-scall.S
create mode 100644 arch/nds32/kernel/head.S
create mode 100644 arch/nds32/kernel/irq.c
create mode 100644 arch/nds32/kernel/module.c
create mode 100644 arch/nds32/kernel/nds32_ksyms.c
create mode 100644 arch/nds32/kernel/process.c
create mode 100644 arch/nds32/kernel/ptrace.c
create mode 100644 arch/nds32/kernel/setup.c
create mode 100644 arch/nds32/kernel/signal.c
create mode 100644 arch/nds32/kernel/stacktrace.c
create mode 100644 arch/nds32/kernel/sys_nds32.c
create mode 100644 arch/nds32/kernel/syscall_table.c
create mode 100644 arch/nds32/kernel/time.c
create mode 100644 arch/nds32/kernel/traps.c
create mode 100644 arch/nds32/kernel/vdso.c
create mode 100644 arch/nds32/kernel/vdso/Makefile
create mode 100644 arch/nds32/kernel/vdso/datapage.S
create mode 100755 arch/nds32/kernel/vdso/gen_vdso_offsets.sh
create mode 100644 arch/nds32/kernel/vdso/gettimeofday.c
create mode 100644 arch/nds32/kernel/vdso/note.S
create mode 100644 arch/nds32/kernel/vdso/sigreturn.S
create mode 100644 arch/nds32/kernel/vdso/vdso.S
create mode 100644 arch/nds32/kernel/vdso/vdso.lds.S
create mode 100644 arch/nds32/kernel/vmlinux.lds.S
create mode 100644 arch/nds32/lib/Makefile
create mode 100644 arch/nds32/lib/clear_user.S
create mode 100644 arch/nds32/lib/copy_from_user.S
create mode 100644 arch/nds32/lib/copy_page.S
create mode 100644 arch/nds32/lib/copy_template.S
create mode 100644 arch/nds32/lib/copy_to_user.S
create mode 100644 arch/nds32/lib/memcpy.S
create mode 100644 arch/nds32/lib/memmove.S
create mode 100644 arch/nds32/lib/memset.S
create mode 100644 arch/nds32/lib/memzero.S
create mode 100644 arch/nds32/mm/Makefile
create mode 100644 arch/nds32/mm/alignment.c
create mode 100644 arch/nds32/mm/cacheflush.c
create mode 100644 arch/nds32/mm/extable.c
create mode 100644 arch/nds32/mm/fault.c
create mode 100644 arch/nds32/mm/highmem.c
create mode 100644 arch/nds32/mm/init.c
create mode 100644 arch/nds32/mm/ioremap.c
create mode 100644 arch/nds32/mm/mm-nds32.c
create mode 100644 arch/nds32/mm/mmap.c
create mode 100644 arch/nds32/mm/proc.c
create mode 100644 arch/nds32/mm/tlb.c
create mode 100644 drivers/clocksource/timer-atcpit100.c
create mode 100644 drivers/irqchip/irq-ativic32.c
--
1.7.9.5
^ permalink raw reply
* [PATCH 1/1] ARM: dts: sunxi: Update dts for A20-OLinuXino boards
From: Stefan Mavrodiev @ 2017-11-27 12:03 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Maxime Ripard,
Chen-Yu Tsai, devicetree, linux-arm-kernel, linux-kernel
Cc: linux-sunxi, Stefan Mavrodiev
There will be option with 16MB flash for the following boards:
* A20-OLinuXino-MICRO Rev.K
* A20-OLinuXino-LIME Rev.J
* A20-OLinuXino-LIME2 Rev.J
* A20-SOM-EVB Rev.E
The used flash chip is Winbond W25Q128FV, which is connected to
SPI0 port. Since this is optional feature, spi0 node is dissabled
by default. Also this option is incompatible with NAND flash, so
they shouldn't be enabled at the same time.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
---
arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 14 ++++++++++++++
arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 14 ++++++++++++++
arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 14 ++++++++++++++
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 14 ++++++++++++++
4 files changed, 56 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
index 64c8ef9..98b7697 100644
--- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
@@ -291,6 +291,20 @@
status = "okay";
};
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins_b>,<&spi0_cs0_pins_b>;
+ status = "disabled";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "winbond,w25q128","jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>,
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
index edf9c3c..354af5d 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
@@ -218,6 +218,20 @@
status = "okay";
};
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins_b>,<&spi0_cs0_pins_b>;
+ status = "disabled";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "winbond,w25q128","jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
index ba25018..6fcdd6e 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
@@ -268,6 +268,20 @@
status = "okay";
};
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins_b>,<&spi0_cs0_pins_b>;
+ status = "disabled";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "winbond,w25q128","jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index dffbaa2..db85895 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -331,6 +331,20 @@
status = "okay";
};
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins_b>,<&spi0_cs0_pins_b>;
+ status = "disabled";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "winbond,w25q128","jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>,
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v2 04/11] media: rkisp1: add Rockchip MIPI Synopsys DPHY driver
From: Hans Verkuil @ 2017-11-27 12:01 UTC (permalink / raw)
To: Jacob Chen, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
mchehab-DgEjT+Ai2ygdnm+yROfE0A,
linux-media-u79uwXL29TY76Z2rM5mHXA,
sakari.ailus-VuQAYsv1563Yd54FQh9/CA,
hans.verkuil-FYB4Gu1CFyUAvxtiuMwx3w, tfiga-F7+t8E8rja9g9hUCZPvPmw,
zhengsq-TNX95d0MmH7DzftRWevZcw,
laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw,
zyc-TNX95d0MmH7DzftRWevZcw,
eddie.cai.linux-Re5JQEeQqe8AvxtiuMwx3w,
jeffy.chen-TNX95d0MmH7DzftRWevZcw,
allon.huang-TNX95d0MmH7DzftRWevZcw,
devicetree-u79uwXL29TY76Z2rM5mHXA, heiko-4mtYJXux2i+zQB+pC5nmwQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, Jacob Chen, Jose Abreu
In-Reply-To: <20171124023706.5702-5-jacob-chen-fyOeoxGR3m/QT0dZR+AlfA@public.gmane.org>
I'm CC-ing Jose Abreu from Synopsys to this. Jose, can you or a colleague take
a look at this as well?
Jacob, I have some high-level questions first:
1) to what extend is this code rockchip-specific as opposed to be more synopsys-generic?
2) I don't quite see how this works when there are two sensors. Is only one active at a
time? Or are they multiplexed somehow?
3) Same as for the previous patch: some more comments would be welcome.
On 11/24/2017 03:36 AM, Jacob Chen wrote:
> From: Jacob Chen <jacob2.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>
> This commit adds a subdev driver for Rockchip MIPI Synopsys DPHY driver.
>
> The phy driver is kind of independent compare to the other parts, but i'd like
> to keep it in rkisp1 driver, unless people want to generalize it
>
> Signed-off-by: Jacob Chen <jacob2.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Signed-off-by: Shunqian Zheng <zhengsq-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Signed-off-by: Tomasz Figa <tfiga-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> ---
> drivers/media/platform/rockchip/isp1/Makefile | 1 +
> .../media/platform/rockchip/isp1/mipi_dphy_sy.c | 805 +++++++++++++++++++++
> 2 files changed, 806 insertions(+)
> create mode 100644 drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
>
> diff --git a/drivers/media/platform/rockchip/isp1/Makefile b/drivers/media/platform/rockchip/isp1/Makefile
> index 8f52f959398e..18af64853734 100644
> --- a/drivers/media/platform/rockchip/isp1/Makefile
> +++ b/drivers/media/platform/rockchip/isp1/Makefile
> @@ -4,4 +4,5 @@ video_rkisp1-objs += rkisp1.o \
> regs.o \
> isp_stats.o \
> isp_params.o \
> + mipi_dphy_sy.o \
> capture.o
> diff --git a/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
> new file mode 100644
> index 000000000000..56deff2be6fd
> --- /dev/null
> +++ b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
> @@ -0,0 +1,805 @@
> +/*
> + * Rockchip MIPI Synopsys DPHY driver
> + *
> + * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
> + *
> + * This software is available to you under a choice of one of two
> + * licenses. You may choose to be licensed under the terms of the GNU
> + * General Public License (GPL) Version 2, available from the file
> + * COPYING in the main directory of this source tree, or the
> + * OpenIB.org BSD license below:
> + *
> + * Redistribution and use in source and binary forms, with or
> + * without modification, are permitted provided that the following
> + * conditions are met:
> + *
> + * - Redistributions of source code must retain the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer.
> + *
> + * - Redistributions in binary form must reproduce the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer in the documentation and/or other materials
> + * provided with the distribution.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <media/media-entity.h>
> +#include <media/v4l2-ctrls.h>
> +#include <media/v4l2-fwnode.h>
> +#include <media/v4l2-subdev.h>
> +
> +#define RK3288_GRF_SOC_CON6 0x025c
> +#define RK3288_GRF_SOC_CON8 0x0264
> +#define RK3288_GRF_SOC_CON9 0x0268
> +#define RK3288_GRF_SOC_CON10 0x026c
> +#define RK3288_GRF_SOC_CON14 0x027c
> +#define RK3288_GRF_SOC_STATUS21 0x02d4
> +#define RK3288_GRF_IO_VSEL 0x0380
> +#define RK3288_GRF_SOC_CON15 0x03a4
> +
> +#define RK3399_GRF_SOC_CON9 0x6224
> +#define RK3399_GRF_SOC_CON21 0x6254
> +#define RK3399_GRF_SOC_CON22 0x6258
> +#define RK3399_GRF_SOC_CON23 0x625c
> +#define RK3399_GRF_SOC_CON24 0x6260
> +#define RK3399_GRF_SOC_CON25 0x6264
> +#define RK3399_GRF_SOC_STATUS1 0xe2a4
> +
> +#define CLOCK_LANE_HS_RX_CONTROL 0x34
> +#define LANE0_HS_RX_CONTROL 0x44
> +#define LANE1_HS_RX_CONTROL 0x54
> +#define LANE2_HS_RX_CONTROL 0x84
> +#define LANE3_HS_RX_CONTROL 0x94
> +#define HS_RX_DATA_LANES_THS_SETTLE__CONTROL 0x75
> +
> +#define HIWORD_UPDATE(val, mask, shift) \
> + ((val) << (shift) | (mask) << ((shift) + 16))
> +
> +enum mipi_dphy_sy_pads {
> + MIPI_DPHY_SY_PAD_SINK = 0,
> + MIPI_DPHY_SY_PAD_SOURCE,
> + MIPI_DPHY_SY_PADS_NUM,
> +};
> +
> +enum dphy_reg_id {
> + GRF_DPHY_RX0_TURNDISABLE = 0,
> + GRF_DPHY_RX0_FORCERXMODE,
> + GRF_DPHY_RX0_FORCETXSTOPMODE,
> + GRF_DPHY_RX0_ENABLE,
> + GRF_DPHY_RX0_TESTCLR,
> + GRF_DPHY_RX0_TESTCLK,
> + GRF_DPHY_RX0_TESTEN,
> + GRF_DPHY_RX0_TESTDIN,
> + GRF_DPHY_RX0_TURNREQUEST,
> + GRF_DPHY_RX0_TESTDOUT,
> + GRF_DPHY_TX0_TURNDISABLE,
> + GRF_DPHY_TX0_FORCERXMODE,
> + GRF_DPHY_TX0_FORCETXSTOPMODE,
> + GRF_DPHY_TX0_TURNREQUEST,
> + GRF_DPHY_TX1RX1_TURNDISABLE,
> + GRF_DPHY_TX1RX1_FORCERXMODE,
> + GRF_DPHY_TX1RX1_FORCETXSTOPMODE,
> + GRF_DPHY_TX1RX1_ENABLE,
> + GRF_DPHY_TX1RX1_MASTERSLAVEZ,
> + GRF_DPHY_TX1RX1_BASEDIR,
> + GRF_DPHY_TX1RX1_ENABLECLK,
> + GRF_DPHY_TX1RX1_TURNREQUEST,
> + GRF_DPHY_RX1_SRC_SEL,
> + /* rk3288 only */
> + GRF_CON_DISABLE_ISP,
> + GRF_CON_ISP_DPHY_SEL,
> + GRF_DSI_CSI_TESTBUS_SEL,
> + GRF_DVP_V18SEL,
> + /* below is for rk3399 only */
> + GRF_DPHY_RX0_CLK_INV_SEL,
> + GRF_DPHY_RX1_CLK_INV_SEL,
> +};
> +
> +struct dphy_reg {
> + u32 offset;
> + u32 mask;
> + u32 shift;
> +};
> +
> +#define PHY_REG(_offset, _width, _shift) \
> + { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
> +
> +static const struct dphy_reg rk3399_grf_dphy_regs[] = {
> + [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0),
> + [GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10),
> + [GRF_DPHY_RX1_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 11),
> + [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0),
> + [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 4),
> + [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 8),
> + [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 12),
> + [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 0),
> + [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 4),
> + [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 8),
> + [GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 12),
> + [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 0),
> + [GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 4),
> + [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 8),
> + [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 12),
> + [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON24, 4, 0),
> + [GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 4),
> + [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 5),
> + [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 6),
> + [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 7),
> + [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3399_GRF_SOC_CON25, 8, 0),
> + [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 8),
> + [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 9),
> + [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 10),
> + [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3399_GRF_SOC_STATUS1, 8, 0),
> +};
> +
> +static const struct dphy_reg rk3288_grf_dphy_regs[] = {
> + [GRF_CON_DISABLE_ISP] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 0),
> + [GRF_CON_ISP_DPHY_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 1),
> + [GRF_DSI_CSI_TESTBUS_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 14),
> + [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 0),
> + [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 4),
> + [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 8),
> + [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 0),
> + [GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 4),
> + [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 8),
> + [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 12),
> + [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 0),
> + [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 4),
> + [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 8),
> + [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 12),
> + [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 0),
> + [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 1),
> + [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 2),
> + [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3288_GRF_SOC_CON14, 8, 3),
> + [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 12),
> + [GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 13),
> + [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 14),
> + [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 15),
> + [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 4, 0),
> + [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 4, 4),
> + [GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 3, 8),
> + [GRF_DVP_V18SEL] = PHY_REG(RK3288_GRF_IO_VSEL, 1, 1),
> + [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3288_GRF_SOC_STATUS21, 8, 0),
> +};
> +
> +struct hsfreq_range {
> + u32 range_h;
> + u8 cfg_bit;
> +};
> +
> +struct dphy_drv_data {
> + const char * const *clks;
> + int num_clks;
> + const struct hsfreq_range *hsfreq_ranges;
> + int num_hsfreq_ranges;
> + const struct dphy_reg *regs;
> +};
> +
> +struct sensor_async_subdev {
> + struct v4l2_async_subdev asd;
> + struct v4l2_mbus_config mbus;
> + int lanes;
> +};
> +
> +#define MAX_DPHY_CLK 8
> +#define MAX_DPHY_SENSORS 2
> +
> +struct mipidphy_sensor {
> + struct v4l2_subdev *sd;
> + struct v4l2_mbus_config mbus;
> + int lanes;
> +};
> +
> +struct mipidphy_priv {
> + struct device *dev;
> + struct regmap *regmap_grf;
> + const struct dphy_reg *grf_regs;
> + struct clk *clks[MAX_DPHY_CLK];
> + const struct dphy_drv_data *drv_data;
> + u64 data_rate_mbps;
> + struct v4l2_async_notifier notifier;
> + struct v4l2_subdev sd;
> + struct media_pad pads[MIPI_DPHY_SY_PADS_NUM];
> + struct mipidphy_sensor sensors[MAX_DPHY_SENSORS];
> + int num_sensors;
> + bool is_streaming;
> +};
> +
> +static inline struct mipidphy_priv *to_dphy_priv(struct v4l2_subdev *subdev)
> +{
> + return container_of(subdev, struct mipidphy_priv, sd);
> +}
> +
> +static inline void write_reg(struct mipidphy_priv *priv, int index, u8 value)
> +{
> + const struct dphy_reg *reg = &priv->grf_regs[index];
> + unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
> +
> + WARN_ON(!reg->offset);
> + regmap_write(priv->regmap_grf, reg->offset, val);
> +}
> +
> +static void mipidphy_wr_reg(struct mipidphy_priv *priv,
> + u8 test_code, u8 test_data)
> +{
> + /*
> + * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
> + * is latched internally as the current test code. Test data is
> + * programmed internally by rising edge on TESTCLK.
> + */
> + write_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
> + write_reg(priv, GRF_DPHY_RX0_TESTDIN, test_code);
> + write_reg(priv, GRF_DPHY_RX0_TESTEN, 1);
> + write_reg(priv, GRF_DPHY_RX0_TESTCLK, 0);
> + write_reg(priv, GRF_DPHY_RX0_TESTEN, 0);
> + write_reg(priv, GRF_DPHY_RX0_TESTDIN, test_data);
> + write_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
> +}
> +
> +static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd)
> +{
> + struct media_pad *local, *remote;
> + struct media_entity *sensor_me;
> +
> + local = &sd->entity.pads[MIPI_DPHY_SY_PAD_SINK];
> + remote = media_entity_remote_pad(local);
> + if (!remote) {
> + v4l2_warn(sd, "No link between dphy and sensor\n");
> + return NULL;
> + }
> +
> + sensor_me = media_entity_remote_pad(local)->entity;
> + return media_entity_to_v4l2_subdev(sensor_me);
> +}
> +
> +static struct mipidphy_sensor *sd_to_sensor(struct mipidphy_priv *priv,
> + struct v4l2_subdev *sd)
> +{
> + int i;
> +
> + for (i = 0; i < priv->num_sensors; ++i)
> + if (priv->sensors[i].sd == sd)
> + return &priv->sensors[i];
> +
> + return NULL;
> +}
> +
> +static int mipidphy_get_sensor_data_rate(struct v4l2_subdev *sd)
> +{
> + struct mipidphy_priv *priv = to_dphy_priv(sd);
> + struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
> + struct v4l2_ctrl *link_freq;
> + struct v4l2_querymenu qm = { .id = V4L2_CID_LINK_FREQ, };
> + int ret;
> +
> + link_freq = v4l2_ctrl_find(sensor_sd->ctrl_handler, V4L2_CID_LINK_FREQ);
> + if (!link_freq) {
> + v4l2_warn(sd, "No pixel rate control in subdev\n");
> + return -EPIPE;
> + }
> +
> + qm.index = v4l2_ctrl_g_ctrl(link_freq);
> + ret = v4l2_querymenu(sensor_sd->ctrl_handler, &qm);
> + if (ret < 0) {
> + v4l2_err(sd, "Failed to get menu item\n");
> + return ret;
> + }
> +
> + if (!qm.value) {
> + v4l2_err(sd, "Invalid link_freq\n");
> + return -EINVAL;
> + }
> + priv->data_rate_mbps = qm.value * 2;
> + do_div(priv->data_rate_mbps, 1000 * 1000);
> +
> + return 0;
> +}
> +
> +static int mipidphy_s_stream_start(struct v4l2_subdev *sd)
> +{
> + struct mipidphy_priv *priv = to_dphy_priv(sd);
> + const struct dphy_drv_data *drv_data = priv->drv_data;
> + const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
> + int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
> + struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
> + struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
> + int i, ret, hsfreq = 0;
> +
> + if (priv->is_streaming)
> + return 0;
> +
> + ret = mipidphy_get_sensor_data_rate(sd);
> + if (ret < 0)
> + return ret;
> +
> + for (i = 0; i < num_hsfreq_ranges; i++) {
> + if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
> + hsfreq = hsfreq_ranges[i].cfg_bit;
> + break;
> + }
> + }
> +
> + write_reg(priv, GRF_DPHY_RX0_FORCERXMODE, 0);
> + write_reg(priv, GRF_DPHY_RX0_FORCETXSTOPMODE, 0);
> + /* Disable lan turn around, which is ignored in receive mode */
> + write_reg(priv, GRF_DPHY_RX0_TURNREQUEST, 0);
> + write_reg(priv, GRF_DPHY_RX0_TURNDISABLE, 0xf);
> +
> + write_reg(priv, GRF_DPHY_RX0_ENABLE, GENMASK(sensor->lanes - 1, 0));
> +
> + /* dphy start */
> + write_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
> + write_reg(priv, GRF_DPHY_RX0_TESTCLR, 1);
> + usleep_range(100, 150);
> + write_reg(priv, GRF_DPHY_RX0_TESTCLR, 0);
> + usleep_range(100, 150);
> +
> + /* set clock lane */
> + /* HS hsfreq_range & lane 0 settle bypass */
> + mipidphy_wr_reg(priv, CLOCK_LANE_HS_RX_CONTROL, 0);
> + /* HS RX Control of lane0 */
> + mipidphy_wr_reg(priv, LANE0_HS_RX_CONTROL, hsfreq << 1);
> + /* HS RX Control of lane1 */
> + mipidphy_wr_reg(priv, LANE1_HS_RX_CONTROL, 0);
> + /* HS RX Control of lane2 */
> + mipidphy_wr_reg(priv, LANE2_HS_RX_CONTROL, 0);
> + /* HS RX Control of lane3 */
> + mipidphy_wr_reg(priv, LANE3_HS_RX_CONTROL, 0);
> + /* HS RX Data Lanes Settle State Time Control */
> + mipidphy_wr_reg(priv, HS_RX_DATA_LANES_THS_SETTLE__CONTROL, 0x04);
> +
> + /* Normal operation */
> + mipidphy_wr_reg(priv, 0x0, 0);
> +
> + priv->is_streaming = true;
> +
> + return 0;
> +}
> +
> +static int mipidphy_s_stream_stop(struct v4l2_subdev *sd)
> +{
> + struct mipidphy_priv *priv = to_dphy_priv(sd);
> +
> + if (!priv->is_streaming)
> + return 0;
> +
> + priv->is_streaming = false;
> +
> + return 0;
> +}
> +
> +static int mipidphy_s_stream(struct v4l2_subdev *sd, int on)
> +{
> + if (on)
> + return mipidphy_s_stream_start(sd);
> + else
> + return mipidphy_s_stream_stop(sd);
> +}
> +
> +static int mipidphy_g_mbus_config(struct v4l2_subdev *sd,
> + struct v4l2_mbus_config *config)
> +{
> + struct mipidphy_priv *priv = to_dphy_priv(sd);
> + struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
> + struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
> +
> + *config = sensor->mbus;
> +
> + return 0;
> +}
> +
> +static int mipidphy_s_power(struct v4l2_subdev *sd, int on)
> +{
> + struct mipidphy_priv *priv = to_dphy_priv(sd);
> +
> + if (on)
> + return pm_runtime_get_sync(priv->dev);
> + else
> + return pm_runtime_put(priv->dev);
> +}
> +
> +static int mipidphy_runtime_suspend(struct device *dev)
> +{
> + struct media_entity *me = dev_get_drvdata(dev);
> + struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
> + struct mipidphy_priv *priv = to_dphy_priv(sd);
> + int i, num_clks;
> +
> + num_clks = priv->drv_data->num_clks;
> + for (i = num_clks - 1; i >= 0; i--)
> + clk_disable_unprepare(priv->clks[i]);
> +
> + return 0;
> +}
> +
> +static int mipidphy_runtime_resume(struct device *dev)
> +{
> + struct media_entity *me = dev_get_drvdata(dev);
> + struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
> + struct mipidphy_priv *priv = to_dphy_priv(sd);
> + int i, num_clks, ret;
> +
> + num_clks = priv->drv_data->num_clks;
> + for (i = 0; i < num_clks; i++) {
> + ret = clk_prepare_enable(priv->clks[i]);
> + if (ret < 0)
> + goto err;
> + }
> +
> + return 0;
> +err:
> + while (--i >= 0)
> + clk_disable_unprepare(priv->clks[i]);
> + return ret;
> +}
> +
> +/* dphy accepts all fmt/size from sensor */
> +static int mipidphy_get_set_fmt(struct v4l2_subdev *sd,
> + struct v4l2_subdev_pad_config *cfg,
> + struct v4l2_subdev_format *fmt)
> +{
> + struct v4l2_subdev *sensor = get_remote_sensor(sd);
> +
> + /*
> + * Do not allow format changes and just relay whatever
> + * set currently in the sensor.
> + */
> + return v4l2_subdev_call(sensor, pad, get_fmt, NULL, fmt);
> +}
> +
> +static const struct v4l2_subdev_pad_ops mipidphy_subdev_pad_ops = {
> + .set_fmt = mipidphy_get_set_fmt,
> + .get_fmt = mipidphy_get_set_fmt,
> +};
> +
> +static const struct v4l2_subdev_core_ops mipidphy_core_ops = {
> + .s_power = mipidphy_s_power,
> +};
> +
> +static const struct v4l2_subdev_video_ops mipidphy_video_ops = {
> + .g_mbus_config = mipidphy_g_mbus_config,
Why do you need this?
> + .s_stream = mipidphy_s_stream,
> +};
> +
> +static const struct v4l2_subdev_ops mipidphy_subdev_ops = {
> + .core = &mipidphy_core_ops,
> + .video = &mipidphy_video_ops,
> + .pad = &mipidphy_subdev_pad_ops,
> +};
> +
> +/* These tables must be sorted by .range_h ascending. */
> +static const struct hsfreq_range rk3288_mipidphy_hsfreq_ranges[] = {
> + { 89, 0x00}, { 99, 0x10}, { 109, 0x20}, { 129, 0x01},
> + { 139, 0x11}, { 149, 0x21}, { 169, 0x02}, { 179, 0x12},
> + { 199, 0x22}, { 219, 0x03}, { 239, 0x13}, { 249, 0x23},
> + { 269, 0x04}, { 299, 0x14}, { 329, 0x05}, { 359, 0x15},
> + { 399, 0x25}, { 449, 0x06}, { 499, 0x16}, { 549, 0x07},
> + { 599, 0x17}, { 649, 0x08}, { 699, 0x18}, { 749, 0x09},
> + { 799, 0x19}, { 849, 0x29}, { 899, 0x39}, { 949, 0x0a},
> + { 999, 0x1a}
> +};
> +
> +static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = {
> + { 89, 0x00}, { 99, 0x10}, { 109, 0x20}, { 129, 0x01},
> + { 139, 0x11}, { 149, 0x21}, { 169, 0x02}, { 179, 0x12},
> + { 199, 0x22}, { 219, 0x03}, { 239, 0x13}, { 249, 0x23},
> + { 269, 0x04}, { 299, 0x14}, { 329, 0x05}, { 359, 0x15},
> + { 399, 0x25}, { 449, 0x06}, { 499, 0x16}, { 549, 0x07},
> + { 599, 0x17}, { 649, 0x08}, { 699, 0x18}, { 749, 0x09},
> + { 799, 0x19}, { 849, 0x29}, { 899, 0x39}, { 949, 0x0a},
> + { 999, 0x1a}, {1049, 0x2a}, {1099, 0x3a}, {1149, 0x0b},
> + {1199, 0x1b}, {1249, 0x2b}, {1299, 0x3b}, {1349, 0x0c},
> + {1399, 0x1c}, {1449, 0x2c}, {1500, 0x3c}
> +};
> +
> +static const char * const rk3399_mipidphy_clks[] = {
> + "dphy-ref",
> + "dphy-cfg",
> + "grf",
> +};
> +
> +static const char * const rk3288_mipidphy_clks[] = {
> + "dphy-ref",
> + "pclk",
> +};
> +
> +static const struct dphy_drv_data rk3288_mipidphy_drv_data = {
> + .clks = rk3288_mipidphy_clks,
> + .num_clks = ARRAY_SIZE(rk3288_mipidphy_clks),
> + .hsfreq_ranges = rk3288_mipidphy_hsfreq_ranges,
> + .num_hsfreq_ranges = ARRAY_SIZE(rk3288_mipidphy_hsfreq_ranges),
> + .regs = rk3288_grf_dphy_regs,
> +};
> +
> +static const struct dphy_drv_data rk3399_mipidphy_drv_data = {
> + .clks = rk3399_mipidphy_clks,
> + .num_clks = ARRAY_SIZE(rk3399_mipidphy_clks),
> + .hsfreq_ranges = rk3399_mipidphy_hsfreq_ranges,
> + .num_hsfreq_ranges = ARRAY_SIZE(rk3399_mipidphy_hsfreq_ranges),
> + .regs = rk3399_grf_dphy_regs,
> +};
> +
> +static const struct of_device_id rockchip_mipidphy_match_id[] = {
> + {
> + .compatible = "rockchip,rk3399-mipi-dphy",
> + .data = &rk3399_mipidphy_drv_data,
> + },
> + {
> + .compatible = "rockchip,rk3288-mipi-dphy",
> + .data = &rk3288_mipidphy_drv_data,
> + },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, rockchip_mipidphy_match_id);
> +
> +/* The .bound() notifier callback when a match is found */
> +static int
> +rockchip_mipidphy_notifier_bound(struct v4l2_async_notifier *notifier,
> + struct v4l2_subdev *sd,
> + struct v4l2_async_subdev *asd)
> +{
> + struct mipidphy_priv *priv = container_of(notifier,
> + struct mipidphy_priv,
> + notifier);
> + struct sensor_async_subdev *s_asd = container_of(asd,
> + struct sensor_async_subdev, asd);
> + struct mipidphy_sensor *sensor;
> +
> + if (priv->num_sensors == ARRAY_SIZE(priv->sensors))
> + return -EBUSY;
> +
> + sensor = &priv->sensors[priv->num_sensors++];
> + sensor->lanes = s_asd->lanes;
> + sensor->mbus = s_asd->mbus;
> + sensor->sd = sd;
> +
> + return 0;
> +}
> +
> +/* The .unbind callback */
> +static void
> +rockchip_mipidphy_notifier_unbind(struct v4l2_async_notifier *notifier,
> + struct v4l2_subdev *sd,
> + struct v4l2_async_subdev *asd)
> +{
> + struct mipidphy_priv *priv = container_of(notifier,
> + struct mipidphy_priv,
> + notifier);
> + struct mipidphy_sensor *sensor = sd_to_sensor(priv, sd);
> +
> + sensor->sd = NULL;
> +}
> +
> +/* .complete() is called after all subdevices have been located */
> +static int
> +rockchip_mipidphy_notifier_complete(struct v4l2_async_notifier *notifier)
> +{
> + struct mipidphy_priv *priv = container_of(notifier,
> + struct mipidphy_priv,
> + notifier);
> + unsigned int pad;
> + int ret;
> + int i;
> +
> + for (i = 0; i < priv->num_sensors; ++i) {
> + struct mipidphy_sensor *sensor = &priv->sensors[i];
> +
> + for (pad = 0; pad < sensor->sd->entity.num_pads; pad++)
> + if (sensor->sd->entity.pads[pad].flags
> + & MEDIA_PAD_FL_SOURCE)
> + break;
> +
> + if (pad == sensor->sd->entity.num_pads) {
> + dev_err(priv->dev,
> + "failed to find src pad for %s\n",
> + sensor->sd->name);
> +
> + return -ENXIO;
> + }
> +
> + ret = media_create_pad_link(
> + &sensor->sd->entity, pad,
> + &priv->sd.entity, MIPI_DPHY_SY_PAD_SINK,
> + i ? 0 : MEDIA_LNK_FL_ENABLED);
> + if (ret) {
> + dev_err(priv->dev,
> + "failed to create link for %s\n",
> + sensor->sd->name);
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static const
> +struct v4l2_async_notifier_operationsrockchip_mipidphy_async_ops = {
> + .bound = rockchip_mipidphy_notifier_bound,
> + .unbind = rockchip_mipidphy_notifier_unbind,
> + .complete = rockchip_mipidphy_notifier_complete,
> +};
> +
> +static int rockchip_mipidphy_fwnode_parse(struct device *dev,
> + struct v4l2_fwnode_endpoint *vep,
> + struct v4l2_async_subdev *asd)
> +{
> + struct sensor_async_subdev *s_asd =
> + container_of(asd, struct sensor_async_subdev, asd);
> + struct v4l2_mbus_config *config = &s_asd->mbus;
> +
> + if (vep->bus_type != V4L2_MBUS_CSI2) {
> + dev_err(dev, "Only CSI2 bus type is currently supported\n");
> + return -EINVAL;
> + }
> +
> + if (vep->base.port != 0) {
> + dev_err(dev, "The PHY has only port 0\n");
> + return -EINVAL;
> + }
> +
> + config->type = V4L2_MBUS_CSI2;
> + config->flags = vep->bus.mipi_csi2.flags;
> + s_asd->lanes = vep->bus.mipi_csi2.num_data_lanes;
> +
> + switch (vep->bus.mipi_csi2.num_data_lanes) {
> + case 1:
> + config->flags |= V4L2_MBUS_CSI2_1_LANE;
> + break;
> + case 2:
> + config->flags |= V4L2_MBUS_CSI2_2_LANE;
> + break;
> + case 3:
> + config->flags |= V4L2_MBUS_CSI2_3_LANE;
> + break;
> + case 4:
> + config->flags |= V4L2_MBUS_CSI2_4_LANE;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int rockchip_mipidphy_media_init(struct mipidphy_priv *priv)
> +{
> + int ret;
> +
> + priv->pads[MIPI_DPHY_SY_PAD_SOURCE].flags =
> + MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT;
> + priv->pads[MIPI_DPHY_SY_PAD_SINK].flags =
> + MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
> +
> + ret = media_entity_pads_init(&priv->sd.entity,
> + MIPI_DPHY_SY_PADS_NUM, priv->pads);
> + if (ret < 0)
> + return ret;
> +
> + ret = v4l2_async_notifier_parse_fwnode_endpoints_by_port(
> + priv->dev, &priv->notifier,
> + sizeof(struct sensor_async_subdev), 0,
> + rockchip_mipidphy_fwnode_parse);
> + if (ret < 0)
> + return ret;
> +
> + if (!priv->notifier.num_subdevs)
> + return -ENODEV; /* no endpoint */
> +
> + priv->sd.subdev_notifier = &priv->notifier;
> + priv->notifier.ops = &rockchip_mipidphy_async_ops;
> + ret = v4l2_async_subdev_notifier_register(&priv->sd, &priv->notifier);
> + if (ret) {
> + dev_err(priv->dev,
> + "failed to register async notifier : %d\n", ret);
> + v4l2_async_notifier_cleanup(&priv->notifier);
> + return ret;
> + }
> +
> + return v4l2_async_register_subdev(&priv->sd);
> +}
> +
> +static int rockchip_mipidphy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct v4l2_subdev *sd;
> + struct mipidphy_priv *priv;
> + struct regmap *grf;
> + const struct of_device_id *of_id;
> + const struct dphy_drv_data *drv_data;
> + int i, ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> + priv->dev = dev;
> +
> + of_id = of_match_device(rockchip_mipidphy_match_id, dev);
> + if (!of_id)
> + return -EINVAL;
> +
> + grf = syscon_node_to_regmap(dev->parent->of_node);
> + if (IS_ERR(grf)) {
> + dev_err(dev, "Can't find GRF syscon\n");
> + return -ENODEV;
> + }
> + priv->regmap_grf = grf;
> +
> + drv_data = of_id->data;
> + for (i = 0; i < drv_data->num_clks; i++) {
> + priv->clks[i] = devm_clk_get(dev, drv_data->clks[i]);
> +
> + if (IS_ERR(priv->clks[i])) {
> + dev_err(dev, "Failed to get %s\n", drv_data->clks[i]);
> + return PTR_ERR(priv->clks[i]);
> + }
> + }
> +
> + priv->grf_regs = drv_data->regs;
> + priv->drv_data = drv_data;
> +
> + sd = &priv->sd;
> + v4l2_subdev_init(sd, &mipidphy_subdev_ops);
> + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
> + snprintf(sd->name, sizeof(sd->name), "rockchip-sy-mipi-dphy");
> + sd->dev = dev;
> +
> + platform_set_drvdata(pdev, &sd->entity);
> +
> + ret = rockchip_mipidphy_media_init(priv);
> + if (ret < 0)
> + return ret;
> +
> + pm_runtime_enable(&pdev->dev);
> +
> + return 0;
> +}
> +
> +static int rockchip_mipidphy_remove(struct platform_device *pdev)
> +{
> + struct media_entity *me = platform_get_drvdata(pdev);
> + struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
> +
> + media_entity_cleanup(&sd->entity);
> +
> + pm_runtime_disable(&pdev->dev);
> +
> + return 0;
> +}
> +
> +static const struct dev_pm_ops rockchip_mipidphy_pm_ops = {
> + SET_RUNTIME_PM_OPS(mipidphy_runtime_suspend,
> + mipidphy_runtime_resume, NULL)
> +};
> +
> +static struct platform_driver rockchip_isp_mipidphy_driver = {
> + .probe = rockchip_mipidphy_probe,
> + .remove = rockchip_mipidphy_remove,
> + .driver = {
> + .name = "rockchip-sy-mipi-dphy",
> + .pm = &rockchip_mipidphy_pm_ops,
> + .of_match_table = rockchip_mipidphy_match_id,
> + },
> +};
> +
> +module_platform_driver(rockchip_isp_mipidphy_driver);
> +MODULE_AUTHOR("Rockchip Camera/ISP team");
> +MODULE_DESCRIPTION("Rockchip MIPI DPHY driver");
> +MODULE_LICENSE("Dual BSD/GPL");
>
Regards,
Hans
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v2 03/11] media: rkisp1: add rockchip isp1 driver
From: Hans Verkuil @ 2017-11-27 11:40 UTC (permalink / raw)
To: Jacob Chen, linux-rockchip
Cc: linux-kernel, linux-arm-kernel, mchehab, linux-media,
sakari.ailus, hans.verkuil, tfiga, zhengsq, laurent.pinchart, zyc,
eddie.cai.linux, jeffy.chen, allon.huang, devicetree, heiko,
robh+dt, Jacob Chen, Jacob Chen
In-Reply-To: <20171124023706.5702-4-jacob-chen@iotwrt.com>
Hi Jacob,
Thank you for this driver! Much appreciated.
I have a bunch of comments below, nothing big, really. The main thing is that
you really need to sprinkle some more comments in the source code.
On 11/24/2017 03:36 AM, Jacob Chen wrote:
> From: Jacob Chen <jacob2.chen@rock-chips.com>
>
> This commit adds a ISP(Camera) v4l2 driver for rockchip rk3288/rk3399 SoC.
>
> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
> Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
> Signed-off-by: Yichong Zhong <zyc@rock-chips.com>
> Signed-off-by: Jacob Chen <cc@rock-chips.com>
> Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
> Signed-off-by: Allon Huang <allon.huang@rock-chips.com>
> Signed-off-by: Tomasz Figa <tfiga@chromium.org>
> ---
> drivers/media/platform/Kconfig | 10 +
> drivers/media/platform/Makefile | 1 +
> drivers/media/platform/rockchip/isp1/Makefile | 7 +
> drivers/media/platform/rockchip/isp1/capture.c | 1691 +++++++++++++++++++++
> drivers/media/platform/rockchip/isp1/capture.h | 46 +
> drivers/media/platform/rockchip/isp1/common.h | 330 ++++
> drivers/media/platform/rockchip/isp1/dev.c | 632 ++++++++
> drivers/media/platform/rockchip/isp1/isp_params.c | 1556 +++++++++++++++++++
> drivers/media/platform/rockchip/isp1/isp_params.h | 81 +
> drivers/media/platform/rockchip/isp1/isp_stats.c | 537 +++++++
> drivers/media/platform/rockchip/isp1/isp_stats.h | 81 +
> drivers/media/platform/rockchip/isp1/regs.c | 251 +++
> drivers/media/platform/rockchip/isp1/regs.h | 1578 +++++++++++++++++++
> drivers/media/platform/rockchip/isp1/rkisp1.c | 1230 +++++++++++++++
> drivers/media/platform/rockchip/isp1/rkisp1.h | 130 ++
> 15 files changed, 8161 insertions(+)
> create mode 100644 drivers/media/platform/rockchip/isp1/Makefile
> create mode 100644 drivers/media/platform/rockchip/isp1/capture.c
> create mode 100644 drivers/media/platform/rockchip/isp1/capture.h
> create mode 100644 drivers/media/platform/rockchip/isp1/common.h
> create mode 100644 drivers/media/platform/rockchip/isp1/dev.c
> create mode 100644 drivers/media/platform/rockchip/isp1/isp_params.c
> create mode 100644 drivers/media/platform/rockchip/isp1/isp_params.h
> create mode 100644 drivers/media/platform/rockchip/isp1/isp_stats.c
> create mode 100644 drivers/media/platform/rockchip/isp1/isp_stats.h
> create mode 100644 drivers/media/platform/rockchip/isp1/regs.c
> create mode 100644 drivers/media/platform/rockchip/isp1/regs.h
> create mode 100644 drivers/media/platform/rockchip/isp1/rkisp1.c
> create mode 100644 drivers/media/platform/rockchip/isp1/rkisp1.h
>
> diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
> index fd0c99859d6f..062fffc9ffb6 100644
> --- a/drivers/media/platform/Kconfig
> +++ b/drivers/media/platform/Kconfig
> @@ -117,6 +117,16 @@ config VIDEO_QCOM_CAMSS
> select VIDEOBUF2_DMA_SG
> select V4L2_FWNODE
>
> +config VIDEO_ROCKCHIP_ISP1
> + tristate "Rockchip Image Signal Processing v1 Unit driver"
> + depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
> + depends on ARCH_ROCKCHIP || COMPILE_TEST
> + select VIDEOBUF2_DMA_CONTIG
> + select V4L2_FWNODE
> + default n
> + ---help---
> + Support for ISP1 on the rockchip SoC.
> +
> config VIDEO_S3C_CAMIF
> tristate "Samsung S3C24XX/S3C64XX SoC Camera Interface driver"
> depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API
> diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
> index 003b0bb2cddf..d235908df63e 100644
> --- a/drivers/media/platform/Makefile
> +++ b/drivers/media/platform/Makefile
> @@ -67,6 +67,7 @@ obj-$(CONFIG_VIDEO_RENESAS_FDP1) += rcar_fdp1.o
> obj-$(CONFIG_VIDEO_RENESAS_JPU) += rcar_jpu.o
> obj-$(CONFIG_VIDEO_RENESAS_VSP1) += vsp1/
>
> +obj-$(CONFIG_VIDEO_ROCKCHIP_ISP1) += rockchip/isp1/
> obj-$(CONFIG_VIDEO_ROCKCHIP_RGA) += rockchip/rga/
>
> obj-y += omap/
> diff --git a/drivers/media/platform/rockchip/isp1/Makefile b/drivers/media/platform/rockchip/isp1/Makefile
> new file mode 100644
> index 000000000000..8f52f959398e
> --- /dev/null
> +++ b/drivers/media/platform/rockchip/isp1/Makefile
> @@ -0,0 +1,7 @@
> +obj-$(CONFIG_VIDEO_ROCKCHIP_ISP1) += video_rkisp1.o
> +video_rkisp1-objs += rkisp1.o \
> + dev.o \
> + regs.o \
> + isp_stats.o \
> + isp_params.o \
> + capture.o
> diff --git a/drivers/media/platform/rockchip/isp1/capture.c b/drivers/media/platform/rockchip/isp1/capture.c
> new file mode 100644
> index 000000000000..a751a923ba5d
> --- /dev/null
> +++ b/drivers/media/platform/rockchip/isp1/capture.c
> @@ -0,0 +1,1691 @@
> +/*
> + * Rockchip isp1 driver
> + *
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + *
> + * This software is available to you under a choice of one of two
> + * licenses. You may choose to be licensed under the terms of the GNU
> + * General Public License (GPL) Version 2, available from the file
> + * COPYING in the main directory of this source tree, or the
> + * OpenIB.org BSD license below:
> + *
> + * Redistribution and use in source and binary forms, with or
> + * without modification, are permitted provided that the following
> + * conditions are met:
> + *
> + * - Redistributions of source code must retain the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer.
> + *
> + * - Redistributions in binary form must reproduce the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer in the documentation and/or other materials
> + * provided with the distribution.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/pm_runtime.h>
> +#include <media/v4l2-common.h>
> +#include <media/v4l2-event.h>
> +#include <media/v4l2-fh.h>
> +#include <media/v4l2-ioctl.h>
> +#include <media/v4l2-subdev.h>
> +#include <media/videobuf2-dma-contig.h>
> +#include "capture.h"
> +#include "rkisp1.h"
> +#include "regs.h"
> +
> +#define CIF_ISP_REQ_BUFS_MIN 1
> +#define CIF_ISP_REQ_BUFS_MAX 8
> +
> +/*
> + * mp sink source: isp
> + * sp sink source : isp, no dma now
> + * mp sink pad fmts: yuv 422, raw
> + * sp sink pad fmts: yuv422( source isp), yuv420......
> + * mp source fmts: yuv, raw, no jpeg now
> + * sp source fmts: yuv, rgb
> + */
Is this a left-over comment as a reminder to yourself? If so, remove it,
if not, then it needs to be expanded since it's not clear what the
purpose of this comment is.
> +
> +#define STREAM_PAD_SINK 0
> +#define STREAM_PAD_SOURCE 1
> +
> +#define STREAM_MAX_MP_RSZ_OUTPUT_WIDTH 4416
> +#define STREAM_MAX_MP_RSZ_OUTPUT_HEIGHT 3312
> +#define STREAM_MAX_SP_RSZ_OUTPUT_WIDTH 1920
> +#define STREAM_MAX_SP_RSZ_OUTPUT_HEIGHT 1080
> +#define STREAM_MIN_RSZ_OUTPUT_WIDTH 32
> +#define STREAM_MIN_RSZ_OUTPUT_HEIGHT 16
> +
> +#define STREAM_MAX_MP_SP_INPUT_WIDTH STREAM_MAX_MP_RSZ_OUTPUT_WIDTH
> +#define STREAM_MAX_MP_SP_INPUT_HEIGHT STREAM_MAX_MP_RSZ_OUTPUT_HEIGHT
> +#define STREAM_MIN_MP_SP_INPUT_WIDTH 32
> +#define STREAM_MIN_MP_SP_INPUT_HEIGHT 32
> +
> +/*
> + * crop accepts only yuv422 format
> + * resizer can accept yuv444,yuv422,yuv420 format, can output yuv422, yuv420,
> + * yuv444 format
> + * sp resizer has two data source: DMA-reader or crop
> + * mp resizer has only one data source: crop
> + * if format is unsupported by path, crop and resizer should be bypassed
> + * (disabled)
> + */
Same for this comment.
> +
> +/* Get xsubs and ysubs for fourcc formats
> + *
> + * @xsubs: horizon color samples in a 4*4 matrix, for yuv
horizon -> horizontal
> + * @ysubs: vertical color samples in a 4*4 matrix, for yuv
> + */
> +static int fcc_xysubs(u32 fcc, u32 *xsubs, u32 *ysubs)
> +{
> + switch (fcc) {
> + case V4L2_PIX_FMT_GREY:
> + case V4L2_PIX_FMT_YUV444M:
> + *xsubs = 1;
> + *ysubs = 1;
> + break;
> + case V4L2_PIX_FMT_YUYV:
> + case V4L2_PIX_FMT_YVYU:
> + case V4L2_PIX_FMT_VYUY:
> + case V4L2_PIX_FMT_YUV422P:
> + case V4L2_PIX_FMT_NV16:
> + case V4L2_PIX_FMT_NV61:
> + case V4L2_PIX_FMT_YVU422M:
> + *xsubs = 2;
> + *ysubs = 1;
> + break;
> + case V4L2_PIX_FMT_NV21:
> + case V4L2_PIX_FMT_NV12:
> + case V4L2_PIX_FMT_NV21M:
> + case V4L2_PIX_FMT_NV12M:
> + case V4L2_PIX_FMT_YUV420:
> + case V4L2_PIX_FMT_YVU420:
> + *xsubs = 2;
> + *ysubs = 2;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int mbus_code_xysubs(u32 code, u32 *xsubs, u32 *ysubs)
> +{
> + switch (code) {
> + case MEDIA_BUS_FMT_YUYV8_2X8:
> + case MEDIA_BUS_FMT_YUYV8_1X16:
> + case MEDIA_BUS_FMT_YVYU8_1X16:
> + case MEDIA_BUS_FMT_UYVY8_1X16:
> + case MEDIA_BUS_FMT_VYUY8_1X16:
> + *xsubs = 2;
> + *ysubs = 1;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int mbus_code_sp_in_fmt(u32 code, u32 *format)
> +{
> + switch (code) {
> + case MEDIA_BUS_FMT_YUYV8_2X8:
> + *format = MI_CTRL_SP_INPUT_YUV422;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static const struct capture_fmt mp_fmts[] = {
> + /* yuv422 */
> + {
> + .fourcc = V4L2_PIX_FMT_YUYV,
> + .fmt_type = FMT_YUV,
> + .bpp = { 16 },
> + .cplanes = 1,
> + .mplanes = 1,
> + .uv_swap = 0,
> + .write_format = MI_CTRL_MP_WRITE_YUVINT,
> + }, {
> + .fourcc = V4L2_PIX_FMT_YVYU,
> + .fmt_type = FMT_YUV,
> + .bpp = { 16 },
> + .cplanes = 1,
> + .mplanes = 1,
> + .uv_swap = 1,
> + .write_format = MI_CTRL_MP_WRITE_YUVINT,
> + }, {
> + .fourcc = V4L2_PIX_FMT_VYUY,
> + .fmt_type = FMT_YUV,
> + .bpp = { 16 },
> + .cplanes = 1,
> + .mplanes = 1,
> + .uv_swap = 1,
> + .write_format = MI_CTRL_MP_WRITE_YUVINT,
> + }, {
> + .fourcc = V4L2_PIX_FMT_YUV422P,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 4, 4 },
> + .cplanes = 3,
> + .mplanes = 1,
> + .uv_swap = 0,
> + .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + }, {
> + .fourcc = V4L2_PIX_FMT_NV16,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 16 },
> + .cplanes = 2,
> + .mplanes = 1,
> + .uv_swap = 0,
> + .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
> + }, {
> + .fourcc = V4L2_PIX_FMT_NV61,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 16 },
> + .cplanes = 2,
> + .mplanes = 1,
> + .uv_swap = 1,
> + .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
> + }, {
> + .fourcc = V4L2_PIX_FMT_YVU422M,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 8, 8 },
> + .cplanes = 3,
> + .mplanes = 3,
> + .uv_swap = 1,
> + .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + },
> + /* yuv420 */
> + {
> + .fourcc = V4L2_PIX_FMT_NV21,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 16 },
> + .cplanes = 2,
> + .mplanes = 1,
> + .uv_swap = 1,
> + .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
> + }, {
> + .fourcc = V4L2_PIX_FMT_NV12,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 16 },
> + .cplanes = 2,
> + .mplanes = 1,
> + .uv_swap = 0,
> + .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
> + }, {
> + .fourcc = V4L2_PIX_FMT_NV21M,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 16 },
> + .cplanes = 2,
> + .mplanes = 2,
> + .uv_swap = 1,
> + .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
> + }, {
> + .fourcc = V4L2_PIX_FMT_NV12M,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 16 },
> + .cplanes = 2,
> + .mplanes = 2,
> + .uv_swap = 0,
> + .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
> + }, {
> + .fourcc = V4L2_PIX_FMT_YUV420,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 8, 8 },
> + .cplanes = 3,
> + .mplanes = 1,
> + .uv_swap = 0,
> + .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + }, {
> + .fourcc = V4L2_PIX_FMT_YVU420,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 8, 8 },
> + .cplanes = 3,
> + .mplanes = 1,
> + .uv_swap = 1,
> + .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + },
> + /* yuv444 */
> + {
> + .fourcc = V4L2_PIX_FMT_YUV444M,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 8, 8 },
> + .cplanes = 3,
> + .mplanes = 3,
> + .uv_swap = 0,
> + .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + },
> + /* yuv400 */
> + {
> + .fourcc = V4L2_PIX_FMT_GREY,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8 },
> + .cplanes = 1,
> + .mplanes = 1,
> + .uv_swap = 0,
> + .write_format = MI_CTRL_MP_WRITE_YUVINT,
> + },
> + /* raw */
> + {
> + .fourcc = V4L2_PIX_FMT_SRGGB8,
> + .fmt_type = FMT_BAYER,
> + .bpp = { 8 },
> + .mplanes = 1,
> + .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGRBG8,
> + .fmt_type = FMT_BAYER,
> + .bpp = { 8 },
> + .mplanes = 1,
> + .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGBRG8,
> + .fmt_type = FMT_BAYER,
> + .bpp = { 8 },
> + .mplanes = 1,
> + .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SBGGR8,
> + .fmt_type = FMT_BAYER,
> + .bpp = { 8 },
> + .mplanes = 1,
> + .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SRGGB8,
> + .fmt_type = FMT_BAYER,
> + .bpp = { 10 },
> + .mplanes = 1,
> + .write_format = MI_CTRL_MP_WRITE_RAW12,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGRBG10,
> + .fmt_type = FMT_BAYER,
> + .bpp = { 10 },
> + .mplanes = 1,
> + .write_format = MI_CTRL_MP_WRITE_RAW12,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGBRG10,
> + .fmt_type = FMT_BAYER,
> + .bpp = { 10 },
> + .mplanes = 1,
> + .write_format = MI_CTRL_MP_WRITE_RAW12,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SBGGR10,
> + .fmt_type = FMT_BAYER,
> + .bpp = { 10 },
> + .mplanes = 1,
> + .write_format = MI_CTRL_MP_WRITE_RAW12,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SRGGB12,
> + .fmt_type = FMT_BAYER,
> + .bpp = { 12 },
> + .mplanes = 1,
> + .write_format = MI_CTRL_MP_WRITE_RAW12,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGRBG12,
> + .fmt_type = FMT_BAYER,
> + .bpp = { 12 },
> + .mplanes = 1,
> + .write_format = MI_CTRL_MP_WRITE_RAW12,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGBRG12,
> + .fmt_type = FMT_BAYER,
> + .bpp = { 12 },
> + .mplanes = 1,
> + .write_format = MI_CTRL_MP_WRITE_RAW12,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SBGGR12,
> + .fmt_type = FMT_BAYER,
> + .bpp = { 12 },
> + .mplanes = 1,
> + .write_format = MI_CTRL_MP_WRITE_RAW12,
> + },
> +};
> +
> +static const struct capture_fmt sp_fmts[] = {
> + /* yuv422 */
> + {
> + .fourcc = V4L2_PIX_FMT_YUYV,
> + .fmt_type = FMT_YUV,
> + .bpp = { 16 },
> + .cplanes = 1,
> + .mplanes = 1,
> + .uv_swap = 0,
> + .write_format = MI_CTRL_SP_WRITE_INT,
> + .output_format = MI_CTRL_SP_OUTPUT_YUV422,
> + }, {
> + .fourcc = V4L2_PIX_FMT_YVYU,
> + .fmt_type = FMT_YUV,
> + .bpp = { 16 },
> + .cplanes = 1,
> + .mplanes = 1,
> + .uv_swap = 1,
> + .write_format = MI_CTRL_SP_WRITE_INT,
> + .output_format = MI_CTRL_SP_OUTPUT_YUV422,
> + }, {
> + .fourcc = V4L2_PIX_FMT_VYUY,
> + .fmt_type = FMT_YUV,
> + .bpp = { 16 },
> + .cplanes = 1,
> + .mplanes = 1,
> + .uv_swap = 1,
> + .write_format = MI_CTRL_SP_WRITE_INT,
> + .output_format = MI_CTRL_SP_OUTPUT_YUV422,
> + }, {
> + .fourcc = V4L2_PIX_FMT_YUV422P,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 8, 8 },
> + .cplanes = 3,
> + .mplanes = 1,
> + .uv_swap = 0,
> + .write_format = MI_CTRL_SP_WRITE_PLA,
> + .output_format = MI_CTRL_SP_OUTPUT_YUV422,
> + }, {
> + .fourcc = V4L2_PIX_FMT_NV16,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 16 },
> + .cplanes = 2,
> + .mplanes = 1,
> + .uv_swap = 0,
> + .write_format = MI_CTRL_SP_WRITE_SPLA,
> + .output_format = MI_CTRL_SP_OUTPUT_YUV422,
> + }, {
> + .fourcc = V4L2_PIX_FMT_NV61,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 16 },
> + .cplanes = 2,
> + .mplanes = 1,
> + .uv_swap = 1,
> + .write_format = MI_CTRL_SP_WRITE_SPLA,
> + .output_format = MI_CTRL_SP_OUTPUT_YUV422,
> + }, {
> + .fourcc = V4L2_PIX_FMT_YVU422M,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 8, 8 },
> + .cplanes = 3,
> + .mplanes = 3,
> + .uv_swap = 1,
> + .write_format = MI_CTRL_SP_WRITE_PLA,
> + .output_format = MI_CTRL_SP_OUTPUT_YUV422,
> + },
> + /* yuv420 */
> + {
> + .fourcc = V4L2_PIX_FMT_NV21,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 16 },
> + .cplanes = 2,
> + .mplanes = 1,
> + .uv_swap = 1,
> + .write_format = MI_CTRL_SP_WRITE_SPLA,
> + .output_format = MI_CTRL_SP_OUTPUT_YUV420,
> + }, {
> + .fourcc = V4L2_PIX_FMT_NV12,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 16 },
> + .cplanes = 2,
> + .mplanes = 1,
> + .uv_swap = 0,
> + .write_format = MI_CTRL_SP_WRITE_SPLA,
> + .output_format = MI_CTRL_SP_OUTPUT_YUV420,
> + }, {
> + .fourcc = V4L2_PIX_FMT_NV21M,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 16 },
> + .cplanes = 2,
> + .mplanes = 2,
> + .uv_swap = 1,
> + .write_format = MI_CTRL_SP_WRITE_SPLA,
> + .output_format = MI_CTRL_SP_OUTPUT_YUV420,
> + }, {
> + .fourcc = V4L2_PIX_FMT_NV12M,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 16 },
> + .cplanes = 2,
> + .mplanes = 2,
> + .uv_swap = 0,
> + .write_format = MI_CTRL_SP_WRITE_SPLA,
> + .output_format = MI_CTRL_SP_OUTPUT_YUV420,
> + }, {
> + .fourcc = V4L2_PIX_FMT_YUV420,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 8, 8 },
> + .cplanes = 3,
> + .mplanes = 1,
> + .uv_swap = 0,
> + .write_format = MI_CTRL_SP_WRITE_PLA,
> + .output_format = MI_CTRL_SP_OUTPUT_YUV420,
> + }, {
> + .fourcc = V4L2_PIX_FMT_YVU420,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 8, 8 },
> + .cplanes = 3,
> + .mplanes = 1,
> + .uv_swap = 1,
> + .write_format = MI_CTRL_SP_WRITE_PLA,
> + .output_format = MI_CTRL_SP_OUTPUT_YUV420,
> + },
> + /* yuv444 */
> + {
> + .fourcc = V4L2_PIX_FMT_YUV444M,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8, 8, 8 },
> + .cplanes = 3,
> + .mplanes = 3,
> + .uv_swap = 0,
> + .write_format = MI_CTRL_SP_WRITE_PLA,
> + .output_format = MI_CTRL_SP_OUTPUT_YUV444,
> + },
> + /* yuv400 */
> + {
> + .fourcc = V4L2_PIX_FMT_GREY,
> + .fmt_type = FMT_YUV,
> + .bpp = { 8 },
> + .cplanes = 1,
> + .mplanes = 1,
> + .uv_swap = 0,
> + .write_format = MI_CTRL_SP_WRITE_INT,
> + .output_format = MI_CTRL_SP_OUTPUT_YUV400,
> + },
> + /* rgb */
> + {
> + .fourcc = V4L2_PIX_FMT_RGB24,
> + .fmt_type = FMT_RGB,
> + .bpp = { 24 },
> + .mplanes = 1,
> + .write_format = MI_CTRL_SP_WRITE_PLA,
> + .output_format = MI_CTRL_SP_OUTPUT_RGB888,
> + }, {
> + .fourcc = V4L2_PIX_FMT_RGB565,
> + .fmt_type = FMT_RGB,
> + .bpp = { 16 },
> + .mplanes = 1,
> + .write_format = MI_CTRL_SP_WRITE_PLA,
> + .output_format = MI_CTRL_SP_OUTPUT_RGB565,
> + }, {
> + .fourcc = V4L2_PIX_FMT_BGR666,
> + .fmt_type = FMT_RGB,
> + .bpp = { 18 },
> + .mplanes = 1,
> + .write_format = MI_CTRL_SP_WRITE_PLA,
> + .output_format = MI_CTRL_SP_OUTPUT_RGB666,
> + },
> +};
> +
> +static struct stream_config rkisp1_mp_stream_config = {
> + .fmts = mp_fmts,
> + .fmt_size = ARRAY_SIZE(mp_fmts),
> + /* constrains */
constrains -> constraints
> + .max_rsz_width = STREAM_MAX_MP_RSZ_OUTPUT_WIDTH,
> + .max_rsz_height = STREAM_MAX_MP_RSZ_OUTPUT_HEIGHT,
> + .min_rsz_width = STREAM_MIN_RSZ_OUTPUT_WIDTH,
> + .min_rsz_height = STREAM_MIN_RSZ_OUTPUT_HEIGHT,
> + /* registers */
> + .rsz = {
> + .ctrl = CIF_MRSZ_CTRL,
> + .scale_hy = CIF_MRSZ_SCALE_HY,
> + .scale_hcr = CIF_MRSZ_SCALE_HCR,
> + .scale_hcb = CIF_MRSZ_SCALE_HCB,
> + .scale_vy = CIF_MRSZ_SCALE_VY,
> + .scale_vc = CIF_MRSZ_SCALE_VC,
> + .scale_lut = CIF_MRSZ_SCALE_LUT,
> + .scale_lut_addr = CIF_MRSZ_SCALE_LUT_ADDR,
> + .scale_hy_shd = CIF_MRSZ_SCALE_HY_SHD,
> + .scale_hcr_shd = CIF_MRSZ_SCALE_HCR_SHD,
> + .scale_hcb_shd = CIF_MRSZ_SCALE_HCB_SHD,
> + .scale_vy_shd = CIF_MRSZ_SCALE_VY_SHD,
> + .scale_vc_shd = CIF_MRSZ_SCALE_VC_SHD,
> + .phase_hy = CIF_MRSZ_PHASE_HY,
> + .phase_hc = CIF_MRSZ_PHASE_HC,
> + .phase_vy = CIF_MRSZ_PHASE_VY,
> + .phase_vc = CIF_MRSZ_PHASE_VC,
> + .ctrl_shd = CIF_MRSZ_CTRL_SHD,
> + .phase_hy_shd = CIF_MRSZ_PHASE_HY_SHD,
> + .phase_hc_shd = CIF_MRSZ_PHASE_HC_SHD,
> + .phase_vy_shd = CIF_MRSZ_PHASE_VY_SHD,
> + .phase_vc_shd = CIF_MRSZ_PHASE_VC_SHD,
> + },
> + .dual_crop = {
> + .ctrl = CIF_DUAL_CROP_CTRL,
> + .yuvmode_mask = CIF_DUAL_CROP_MP_MODE_YUV,
> + .rawmode_mask = CIF_DUAL_CROP_MP_MODE_RAW,
> + .h_offset = CIF_DUAL_CROP_M_H_OFFS,
> + .v_offset = CIF_DUAL_CROP_M_V_OFFS,
> + .h_size = CIF_DUAL_CROP_M_H_SIZE,
> + .v_size = CIF_DUAL_CROP_M_V_SIZE,
> + },
> + .mi = {
> + .y_size_init = CIF_MI_MP_Y_SIZE_INIT,
> + .cb_size_init = CIF_MI_MP_CB_SIZE_INIT,
> + .cr_size_init = CIF_MI_MP_CR_SIZE_INIT,
> + .y_base_ad_init = CIF_MI_MP_Y_BASE_AD_INIT,
> + .cb_base_ad_init = CIF_MI_MP_CB_BASE_AD_INIT,
> + .cr_base_ad_init = CIF_MI_MP_CR_BASE_AD_INIT,
> + .y_offs_cnt_init = CIF_MI_MP_Y_OFFS_CNT_INIT,
> + .cb_offs_cnt_init = CIF_MI_MP_CB_OFFS_CNT_INIT,
> + .cr_offs_cnt_init = CIF_MI_MP_CR_OFFS_CNT_INIT,
> + },
> +};
> +
> +static struct stream_config rkisp1_sp_stream_config = {
> + .fmts = sp_fmts,
> + .fmt_size = ARRAY_SIZE(sp_fmts),
> + /* constrains */
> + .max_rsz_width = STREAM_MAX_SP_RSZ_OUTPUT_WIDTH,
> + .max_rsz_height = STREAM_MAX_SP_RSZ_OUTPUT_HEIGHT,
> + .min_rsz_width = STREAM_MIN_RSZ_OUTPUT_WIDTH,
> + .min_rsz_height = STREAM_MIN_RSZ_OUTPUT_HEIGHT,
> + /* registers */
> + .rsz = {
> + .ctrl = CIF_SRSZ_CTRL,
> + .scale_hy = CIF_SRSZ_SCALE_HY,
> + .scale_hcr = CIF_SRSZ_SCALE_HCR,
> + .scale_hcb = CIF_SRSZ_SCALE_HCB,
> + .scale_vy = CIF_SRSZ_SCALE_VY,
> + .scale_vc = CIF_SRSZ_SCALE_VC,
> + .scale_lut = CIF_SRSZ_SCALE_LUT,
> + .scale_lut_addr = CIF_SRSZ_SCALE_LUT_ADDR,
> + .scale_hy_shd = CIF_SRSZ_SCALE_HY_SHD,
> + .scale_hcr_shd = CIF_SRSZ_SCALE_HCR_SHD,
> + .scale_hcb_shd = CIF_SRSZ_SCALE_HCB_SHD,
> + .scale_vy_shd = CIF_SRSZ_SCALE_VY_SHD,
> + .scale_vc_shd = CIF_SRSZ_SCALE_VC_SHD,
> + .phase_hy = CIF_SRSZ_PHASE_HY,
> + .phase_hc = CIF_SRSZ_PHASE_HC,
> + .phase_vy = CIF_SRSZ_PHASE_VY,
> + .phase_vc = CIF_SRSZ_PHASE_VC,
> + .ctrl_shd = CIF_SRSZ_CTRL_SHD,
> + .phase_hy_shd = CIF_SRSZ_PHASE_HY_SHD,
> + .phase_hc_shd = CIF_SRSZ_PHASE_HC_SHD,
> + .phase_vy_shd = CIF_SRSZ_PHASE_VY_SHD,
> + .phase_vc_shd = CIF_SRSZ_PHASE_VC_SHD,
> + },
> + .dual_crop = {
> + .ctrl = CIF_DUAL_CROP_CTRL,
> + .yuvmode_mask = CIF_DUAL_CROP_SP_MODE_YUV,
> + .rawmode_mask = CIF_DUAL_CROP_SP_MODE_RAW,
> + .h_offset = CIF_DUAL_CROP_S_H_OFFS,
> + .v_offset = CIF_DUAL_CROP_S_V_OFFS,
> + .h_size = CIF_DUAL_CROP_S_H_SIZE,
> + .v_size = CIF_DUAL_CROP_S_V_SIZE,
> + },
> + .mi = {
> + .y_size_init = CIF_MI_SP_Y_SIZE_INIT,
> + .cb_size_init = CIF_MI_SP_CB_SIZE_INIT,
> + .cr_size_init = CIF_MI_SP_CR_SIZE_INIT,
> + .y_base_ad_init = CIF_MI_SP_Y_BASE_AD_INIT,
> + .cb_base_ad_init = CIF_MI_SP_CB_BASE_AD_INIT,
> + .cr_base_ad_init = CIF_MI_SP_CR_BASE_AD_INIT,
> + .y_offs_cnt_init = CIF_MI_SP_Y_OFFS_CNT_INIT,
> + .cb_offs_cnt_init = CIF_MI_SP_CB_OFFS_CNT_INIT,
> + .cr_offs_cnt_init = CIF_MI_SP_CR_OFFS_CNT_INIT,
> + },
> +};
> +
> +static const
> +struct capture_fmt *find_fmt(struct rkisp1_stream *stream, const u32 pixelfmt)
> +{
> + const struct capture_fmt *fmt;
> + int i;
> +
> + for (i = 0; i < stream->config->fmt_size; i++) {
> + fmt = &stream->config->fmts[i];
> + if (fmt->fourcc == pixelfmt)
> + return fmt;
> + }
> + return NULL;
> +}
> +
> +static int rkisp1_config_dcrop(struct rkisp1_stream *stream, bool async)
> +{
> + struct rkisp1_device *dev = stream->ispdev;
> + struct v4l2_rect *dcrop = &stream->dcrop;
> + struct v4l2_rect *input_win;
> +
> + input_win = rkisp1_get_isp_sd_win(dev);
> +
> + if (dcrop->width == input_win->width &&
> + dcrop->height == input_win->height &&
> + dcrop->left == 0 && dcrop->top == 0) {
> + disable_dcrop(stream, async);
> + return 0;
> + }
> +
> + config_dcrop(stream, dcrop, async);
> +
> + return 0;
> +}
> +
> +static int rkisp1_config_rsz(struct rkisp1_stream *stream, bool async)
> +{
> + struct rkisp1_device *dev = stream->ispdev;
> + struct v4l2_pix_format_mplane output_fmt = stream->out_fmt;
> + struct capture_fmt *output_isp_fmt = &stream->out_isp_fmt;
> + struct ispsd_out_fmt *input_isp_fmt = rkisp1_get_ispsd_out_fmt(dev);
> + struct v4l2_rect in_y, in_c, out_y, out_c;
> + u32 xsubs_in, ysubs_in, xsubs_out, ysubs_out;
> +
> + if (input_isp_fmt->fmt_type == FMT_BAYER)
> + goto disable;
> +
> + /* set input and output sizes for scale calculation */
> + in_y.width = stream->dcrop.width;
> + in_y.height = stream->dcrop.height;
> + out_y.width = output_fmt.width;
> + out_y.height = output_fmt.height;
> +
> + if (mbus_code_xysubs(input_isp_fmt->mbus_code, &xsubs_in, &ysubs_in)) {
> + v4l2_err(&dev->v4l2_dev, "Not xsubs/ysubs found\n");
> + return -EINVAL;
> + }
> + in_c.width = in_y.width / xsubs_in;
> + in_c.height = in_y.height / ysubs_in;
> +
> + if (output_isp_fmt->fmt_type == FMT_YUV) {
> + fcc_xysubs(output_isp_fmt->fourcc, &xsubs_out, &ysubs_out);
> + out_c.width = out_y.width / xsubs_out;
> + out_c.height = out_y.height / ysubs_out;
> + } else {
> + out_c.width = out_y.width / xsubs_in;
> + out_c.height = out_y.height / ysubs_in;
> + }
> +
> + if (in_c.width == out_c.width && in_c.height == out_c.height)
> + goto disable;
> +
> + /* set RSZ input and output */
> + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
> + "stream: %d fmt: %08x %dx%d -> fmt: %08x %dx%d\n",
> + stream->id, input_isp_fmt->mbus_code,
> + stream->dcrop.width, stream->dcrop.height,
> + output_isp_fmt->fourcc, output_fmt.width,
> + output_fmt.height);
> + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
> + "chroma scaling %dx%d -> %dx%d\n",
> + in_c.width, in_c.height, out_c.width, out_c.height);
> +
> + /* calculate and set scale */
> + config_rsz(stream, &in_y, &in_c, &out_y, &out_c, async);
> +
> + if (rkisp1_debug)
> + dump_rsz_regs(stream);
> +
> + return 0;
> +
> +disable:
> + disable_rsz(stream, async);
> +
> + return 0;
> +}
> +
> +/***************************** stream operations*******************************/
> +static int mp_config_mi(struct rkisp1_stream *stream)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> +
> + /*
> + * plane_fmt[0].sizeimage is total size of all planes for single
> + * memory plane formats, so calculate the size explicitly.
> + */
> + mi_set_y_size(stream, stream->out_fmt.plane_fmt[0].bytesperline *
> + stream->out_fmt.height);
> + mi_set_cb_size(stream, stream->out_fmt.plane_fmt[1].sizeimage);
> + mi_set_cr_size(stream, stream->out_fmt.plane_fmt[2].sizeimage);
> +
> + mp_frame_end_int_enable(base);
> + if (stream->out_isp_fmt.uv_swap)
> + mp_set_uv_swap(base);
> +
> + config_mi_ctrl(stream);
> + mp_mi_ctrl_set_format(base, stream->out_isp_fmt.write_format);
> + mp_mi_ctrl_autoupdate_en(base);
> +
> + return 0;
> +}
> +
> +static int sp_config_mi(struct rkisp1_stream *stream)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> + struct rkisp1_device *dev = stream->ispdev;
> + struct capture_fmt *output_isp_fmt = &stream->out_isp_fmt;
> + struct ispsd_out_fmt *input_isp_fmt = rkisp1_get_ispsd_out_fmt(dev);
> + u32 sp_in_fmt;
> +
> + if (mbus_code_sp_in_fmt(input_isp_fmt->mbus_code, &sp_in_fmt)) {
> + v4l2_err(&dev->v4l2_dev, "Can't find the input format\n");
> + return -EINVAL;
> + }
> + mi_set_y_size(stream, stream->out_fmt.plane_fmt[0].bytesperline *
> + stream->out_fmt.height);
> + mi_set_cb_size(stream, stream->out_fmt.plane_fmt[1].sizeimage);
> + mi_set_cr_size(stream, stream->out_fmt.plane_fmt[2].sizeimage);
> +
> + sp_set_y_width(base, stream->out_fmt.width);
> + sp_set_y_height(base, stream->out_fmt.height);
> + sp_set_y_line_length(base, stream->u.sp.y_stride);
> +
> + sp_frame_end_int_enable(base);
> + if (output_isp_fmt->uv_swap)
> + sp_set_uv_swap(base);
> +
> + config_mi_ctrl(stream);
> + sp_mi_ctrl_set_format(base, stream->out_isp_fmt.write_format |
> + sp_in_fmt | output_isp_fmt->output_format);
> +
> + sp_mi_ctrl_autoupdate_en(base);
> +
> + return 0;
> +}
> +
> +static struct rkisp1_stream *get_other_stream(struct rkisp1_stream *stream)
> +{
> + struct rkisp1_device *dev = stream->ispdev;
> +
> + return &dev->stream[stream->id ^ 1];
> +}
> +
> +static int mp_check_against(struct rkisp1_stream *stream)
> +{
> + struct rkisp1_stream *sp = get_other_stream(stream);
> +
> + if (sp->state == RKISP1_STATE_STREAMING)
> + return -EAGAIN;
> +
> + return 0;
> +}
Hmm, can you add some comments before these functions? I noticed very few comments in
this driver, and it really could use some. E.g. 'mp_check_against': it's not clear
what it checks against. And what's _mi in sp_config_mi?
I know, adding comments is a bit of a chore, but this driver really could use some
more of that.
> +
> +static int sp_check_against(struct rkisp1_stream *stream)
> +{
> + struct rkisp1_stream *mp = get_other_stream(stream);
> + struct v4l2_device *v4l2_dev = &stream->ispdev->v4l2_dev;
> +
> + if (mp->u.mp.raw_enable && mp->state == RKISP1_STATE_STREAMING) {
> + v4l2_err(v4l2_dev, "can't start SP path when MP RAW active\n");
> + return -EBUSY;
> + }
> +
> + if (mp->state == RKISP1_STATE_STREAMING)
> + return -EAGAIN;
> +
> + return 0;
> +}
> +
> +static void mp_enable_mi(struct rkisp1_stream *stream)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> + struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
> +
> + mi_ctrl_mp_disable(base);
> + if (isp_fmt->fmt_type == FMT_BAYER)
> + mi_ctrl_mpraw_enable(base);
> + else if (isp_fmt->fmt_type == FMT_YUV)
> + mi_ctrl_mpyuv_enable(base);
> +}
> +
> +static void sp_enable_mi(struct rkisp1_stream *stream)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> +
> + mi_ctrl_spyuv_enable(base);
> +}
> +
> +static void mp_disable_mi(struct rkisp1_stream *stream)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> +
> + mi_ctrl_mp_disable(base);
> +}
> +
> +static void sp_disable_mi(struct rkisp1_stream *stream)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> +
> + mi_ctrl_spyuv_disable(base);
> +}
> +
> +static void update_mi(struct rkisp1_stream *stream)
> +{
> + struct rkisp1_dummy_buffer *dummy_buf = &stream->dummy_buf;
> +
> + if (stream->next_buf) {
> + mi_set_y_addr(stream,
> + stream->next_buf->buff_addr[RKISP1_PLANE_Y]);
> + mi_set_cb_addr(stream,
> + stream->next_buf->buff_addr[RKISP1_PLANE_CB]);
> + mi_set_cr_addr(stream,
> + stream->next_buf->buff_addr[RKISP1_PLANE_CR]);
> + } else {
> + /* Throw data to dummy space */
> + mi_set_y_addr(stream, dummy_buf->dma_addr);
> + mi_set_cb_addr(stream, dummy_buf->dma_addr);
> + mi_set_cr_addr(stream, dummy_buf->dma_addr);
> + }
> +
> + mi_set_y_offset(stream, 0);
> + mi_set_cb_offset(stream, 0);
> + mi_set_cr_offset(stream, 0);
> +}
> +
> +static void mp_stop_mi(struct rkisp1_stream *stream)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> +
> + if (stream->state != RKISP1_STATE_STREAMING)
> + return;
> + /*mp_frame_end_int_disable(base);*/
> + stream->ops->clr_frame_end_int(base);
> + stream->ops->disable_mi(stream);
> +}
> +
> +static void sp_stop_mi(struct rkisp1_stream *stream)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> +
> + if (stream->state != RKISP1_STATE_STREAMING)
> + return;
> + /*sp_frame_end_int_disable(base);*/
> + stream->ops->clr_frame_end_int(base);
> + stream->ops->disable_mi(stream);
> +}
> +
> +static struct streams_ops rkisp1_mp_streams_ops = {
> + .check_against = mp_check_against,
> + .config_mi = mp_config_mi,
> + .enable_mi = mp_enable_mi,
> + .disable_mi = mp_disable_mi,
> + .stop_mi = mp_stop_mi,
> + .set_data_path = mp_set_data_path,
> + .clr_frame_end_int = mp_clr_frame_end_int,
> + .is_frame_end_int_masked = mp_is_frame_end_int_masked,
> +};
> +
> +static struct streams_ops rkisp1_sp_streams_ops = {
> + .check_against = sp_check_against,
> + .config_mi = sp_config_mi,
> + .enable_mi = sp_enable_mi,
> + .disable_mi = sp_disable_mi,
> + .stop_mi = sp_stop_mi,
> + .set_data_path = sp_set_data_path,
> + .clr_frame_end_int = sp_clr_frame_end_int,
> + .is_frame_end_int_masked = sp_is_frame_end_int_masked,
> +};
> +
> +static void rkisp1_stream_stop(struct rkisp1_stream *stream)
> +{
> + struct rkisp1_device *dev = stream->ispdev;
> + struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
> + int ret = 0;
> +
> + stream->stop = true;
> + ret = wait_event_timeout(stream->done,
> + stream->state != RKISP1_STATE_STREAMING,
> + msecs_to_jiffies(1000));
> + if (!ret) {
> + v4l2_warn(v4l2_dev, "waiting on event return error %d\n", ret);
> + stream->ops->stop_mi(stream);
> + stream->stop = false;
> + stream->state = RKISP1_STATE_READY;
> + }
> + disable_dcrop(stream, true);
> + disable_rsz(stream, true);
> +}
> +
> +static int mi_frame_end(struct rkisp1_stream *stream)
> +{
> + struct rkisp1_isp_subdev *isp_sd = &stream->ispdev->isp_sdev;
> + struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
> + unsigned long lock_flags = 0;
> + int i = 0;
> +
> + if (stream->curr_buf) {
> + /* Dequeue a filled buffer */
> + for (i = 0; i < isp_fmt->mplanes; i++) {
> + u32 payload_size =
> + stream->out_fmt.plane_fmt[i].sizeimage;
> + vb2_set_plane_payload(
> + &stream->curr_buf->vb.vb2_buf, i,
> + payload_size);
> + }
> + stream->curr_buf->vb.sequence =
> + atomic_read(&isp_sd->frm_sync_seq) - 1;
> + stream->curr_buf->vb.vb2_buf.timestamp = ktime_get_ns();
> + vb2_buffer_done(&stream->curr_buf->vb.vb2_buf,
> + VB2_BUF_STATE_DONE);
> + }
> +
> + /* Next frame is writing to it */
> + stream->curr_buf = stream->next_buf;
> + stream->next_buf = NULL;
> +
> + /* Set up an empty buffer for the next-next frame */
> + spin_lock_irqsave(&stream->vbq_lock, lock_flags);
> + if (!list_empty(&stream->buf_queue)) {
> + stream->next_buf = list_first_entry(&stream->buf_queue,
> + struct rkisp1_buffer, queue);
> + list_del(&stream->next_buf->queue);
> + }
> +
> + spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
> +
> + update_mi(stream);
> +
> + return 0;
> +}
> +
> +/*
> + * Videobuf2 operations.
> + */
> +static int rkisp1_start(struct rkisp1_stream *stream)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> + int ret;
> +
> + stream->ops->set_data_path(base);
> + ret = stream->ops->config_mi(stream);
> + if (ret)
> + return ret;
> +
> + /* Set up an buffer for the next frame */
> + mi_frame_end(stream);
> + /* Update shadow register */
> + force_cfg_update(base);
> + /* Set up an buffer for the next-next frame */
> + mi_frame_end(stream);
> +
> + stream->ops->enable_mi(stream);
> + stream->state = RKISP1_STATE_STREAMING;
> +
> + return 0;
> +}
> +
> +static int rkisp1_restart(struct rkisp1_stream *stream)
> +{
> + struct rkisp1_device *dev = stream->ispdev;
> + int ret;
> +
> + rkisp1_stream_stop(stream);
> +
> + ret = dev->pipe.set_stream(&dev->pipe, false);
> + if (ret < 0)
> + return ret;
> +
> + ret = rkisp1_start(stream);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int rkisp1_queue_setup(struct vb2_queue *queue,
> + unsigned int *num_buffers,
> + unsigned int *num_planes,
> + unsigned int sizes[],
> + struct device *alloc_devs[])
> +{
> + struct rkisp1_stream *stream = queue->drv_priv;
> + struct rkisp1_device *isp_dev = stream->ispdev;
> + const struct v4l2_pix_format_mplane *pixm = &stream->out_fmt;
> + const struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
> + u32 i;
> +
> + *num_buffers = clamp_t(u32, *num_buffers, CIF_ISP_REQ_BUFS_MIN,
> + CIF_ISP_REQ_BUFS_MAX);
Since min_buffers_needed is set to CIF_ISP_REQ_BUFS_MIN, then you don't need to check
against CIF_ISP_REQ_BUFS_MIN again.
> + *num_planes = isp_fmt->mplanes;
> +
> + for (i = 0; i < isp_fmt->mplanes; i++) {
> + const struct v4l2_plane_pix_format *plane_fmt;
> +
> + plane_fmt = &pixm->plane_fmt[i];
> +
> + sizes[i] = plane_fmt->sizeimage;
> + alloc_devs[i] = isp_dev->dev;
You don't need this. Just set queue->dev to isp_dev->dev when initializing the queue.
alloc_devs[] is only needed if the device would differ per-plane (seen in weird
Samsung exynos hardware).
> + }
> +
> + v4l2_dbg(1, rkisp1_debug, &isp_dev->v4l2_dev, "%s count %d, size %d\n",
> + v4l2_type_names[queue->type], *num_buffers, sizes[0]);
> +
> + return 0;
> +}
> +
> +static void rkisp1_buf_queue(struct vb2_buffer *vb)
> +{
> + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
> + struct rkisp1_buffer *ispbuf = to_rkisp1_buffer(vbuf);
> + struct vb2_queue *queue = vb->vb2_queue;
> + struct rkisp1_stream *stream = queue->drv_priv;
> + unsigned long lock_flags = 0;
> + struct v4l2_pix_format_mplane *pixm = &stream->out_fmt;
> + struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
> + int i;
> +
> + memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr));
> + for (i = 0; i < isp_fmt->mplanes; i++)
> + ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
> +
> + if (isp_fmt->mplanes == 1) {
> + for (i = 0; i < isp_fmt->cplanes - 1; i++) {
> + ispbuf->buff_addr[i + 1] =
> + ispbuf->buff_addr[i] +
> + pixm->plane_fmt[i].bytesperline *
> + pixm->height;
> + }
> + }
> +
> + spin_lock_irqsave(&stream->vbq_lock, lock_flags);
> + list_add_tail(&ispbuf->queue, &stream->buf_queue);
> + spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
> +}
> +
> +static int rkisp1_create_dummy_buf(struct rkisp1_stream *stream)
> +{
> + struct rkisp1_dummy_buffer *dummy_buf = &stream->dummy_buf;
> + struct rkisp1_device *dev = stream->ispdev;
> +
> + /* get a minimum size */
> + dummy_buf->size = max3(stream->out_fmt.plane_fmt[0].bytesperline *
> + stream->out_fmt.height,
> + stream->out_fmt.plane_fmt[1].sizeimage,
> + stream->out_fmt.plane_fmt[2].sizeimage);
> +
> + dummy_buf->vaddr = dma_alloc_coherent(dev->dev, dummy_buf->size,
> + &dummy_buf->dma_addr,
> + GFP_KERNEL);
> + if (!dummy_buf->vaddr) {
> + v4l2_err(&dev->v4l2_dev,
> + "Failed to allocate the memory for dummy buffer\n");
> + return -ENOMEM;
> + }
> +
> + return 0;
> +}
> +
> +static void rkisp1_destory_dummy_buf(struct rkisp1_stream *stream)
> +{
> + struct rkisp1_dummy_buffer *dummy_buf = &stream->dummy_buf;
> + struct rkisp1_device *dev = stream->ispdev;
> +
> + dma_free_coherent(dev->dev, dummy_buf->size,
> + dummy_buf->vaddr, dummy_buf->dma_addr);
> +}
> +
> +static void rkisp1_stop_streaming(struct vb2_queue *queue)
> +{
> + struct rkisp1_stream *stream = queue->drv_priv;
> + struct rkisp1_vdev_node *node = &stream->vnode;
> + struct rkisp1_device *dev = stream->ispdev;
> + struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
> + struct rkisp1_buffer *buf;
> + unsigned long lock_flags = 0;
> + int ret;
> + LIST_HEAD(queued_buffers);
> +
> + rkisp1_stream_stop(stream);
> + ret = dev->pipe.set_stream(&dev->pipe, false);
> + if (ret < 0)
> + return;
> +
> + stream->state = RKISP1_STATE_READY;
> +
> + spin_lock_irqsave(&stream->vbq_lock, lock_flags);
> + if (stream->curr_buf) {
> + list_add_tail(&stream->curr_buf->queue, &stream->buf_queue);
> + stream->curr_buf = NULL;
> + }
> + if (stream->next_buf) {
> + list_add_tail(&stream->next_buf->queue, &stream->buf_queue);
> + stream->next_buf = NULL;
> + }
> + while (!list_empty(&stream->buf_queue)) {
> + buf = list_first_entry(&stream->buf_queue,
> + struct rkisp1_buffer, queue);
> + list_del(&buf->queue);
> + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
> + }
> + spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
> +
> + ret = dev->pipe.close(&dev->pipe);
> + if (ret < 0) {
> + v4l2_err(v4l2_dev, "pipeline close failed error:%d\n", ret);
> + return;
> + }
> +
> + media_pipeline_stop(&node->vdev.entity);
> +
> + rkisp1_destory_dummy_buf(stream);
> +}
> +
> +static int
> +rkisp1_start_streaming(struct vb2_queue *queue, unsigned int count)
> +{
> + struct rkisp1_stream *stream = queue->drv_priv;
> + struct rkisp1_vdev_node *node = &stream->vnode;
> + struct rkisp1_device *dev = stream->ispdev;
> + struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
> + int ret;
> +
> + ret = rkisp1_create_dummy_buf(stream);
> + if (ret < 0)
> + return ret;
> +
> + ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe);
> + if (ret < 0) {
> + v4l2_err(&dev->v4l2_dev, "start pipeline failed %d\n", ret);
> + goto err;
> + }
> +
> + ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true);
> + if (ret < 0) {
> + v4l2_err(v4l2_dev, "open cif pipeline failed %d\n", ret);
> + goto err;
> + }
> +
> + if (stream->state != RKISP1_STATE_READY) {
> + v4l2_err(v4l2_dev, "stream not enabled\n");
> + ret = -EBUSY;
> + goto err;
> + }
> +
> + ret = stream->ops->check_against(stream);
> + if (ret == -EAGAIN) {
> + struct rkisp1_stream *other;
> +
> + other = get_other_stream(stream);
> + if (other)
> + rkisp1_restart(other);
> + } else if (ret == -EBUSY) {
> + goto err;
> + }
> +
> + ret = rkisp1_start(stream);
> + if (ret < 0)
> + goto err;
> +
> + ret = rkisp1_config_rsz(stream, false);
> + if (ret < 0) {
> + v4l2_err(v4l2_dev, "failed with error %d\n", ret);
> + goto err;
> + }
> +
> + ret = rkisp1_config_dcrop(stream, false);
> + if (ret < 0) {
> + v4l2_err(v4l2_dev, "failed with error %d\n", ret);
> + goto err;
> + }
> +
> + /* pipeline stream on */
> + ret = dev->pipe.set_stream(&dev->pipe, true);
> + if (ret < 0)
> + goto err;
> + return 0;
> +
> +err:
> + rkisp1_destory_dummy_buf(stream);
> +
> + return ret;
> +}
> +
> +static struct vb2_ops rkisp1_vb2_ops = {
> + .queue_setup = rkisp1_queue_setup,
> + .buf_queue = rkisp1_buf_queue,
> + .wait_prepare = vb2_ops_wait_prepare,
> + .wait_finish = vb2_ops_wait_finish,
> + .stop_streaming = rkisp1_stop_streaming,
> + .start_streaming = rkisp1_start_streaming,
> +};
> +
> +static int rkisp_init_vb2_queue(struct vb2_queue *q,
> + struct rkisp1_stream *stream,
> + enum v4l2_buf_type buf_type)
> +{
> + struct rkisp1_vdev_node *node;
> +
> + node = queue_to_node(q);
> +
> + q->type = buf_type;
> + q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
Don't use VB2_USERPTR unless there is an iommu that would allow you to
use a malloc()ed buffer. Usually that's not the case for dma-contig streaming.
Either because there is no iommu, or because there are alignment requirements
(e.g. start at the page boundary) that do not fit a malloc()ed buffer.
> + q->drv_priv = stream;
> + q->ops = &rkisp1_vb2_ops;
> + q->mem_ops = &vb2_dma_contig_memops;
> + q->buf_struct_size = sizeof(struct rkisp1_buffer);
> + q->min_buffers_needed = CIF_ISP_REQ_BUFS_MIN;
> + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
> + q->lock = &node->vlock;
> +
> + return vb2_queue_init(q);
> +}
> +
> +static void rkisp1_set_fmt(struct rkisp1_stream *stream,
> + struct v4l2_pix_format_mplane *pixm,
> + bool try)
> +{
> + const struct capture_fmt *fmt;
> + unsigned int imagsize = 0;
> + unsigned int planes;
> + u32 xsubs = 1, ysubs = 1;
> + int i;
> +
> + fmt = find_fmt(stream, pixm->pixelformat);
> + if (!fmt)
> + fmt = stream->config->fmts;
> +
> + /* do checks on resolution */
> + pixm->width = clamp_t(u32, pixm->width,
> + stream->config->min_rsz_width,
> + stream->config->max_rsz_width);
> + pixm->height = clamp_t(u32, pixm->height,
> + stream->config->min_rsz_height,
> + stream->config->max_rsz_height);
> + pixm->num_planes = fmt->mplanes;
> + pixm->colorspace = rkisp1_get_colorspace(fmt->fmt_type);
> + pixm->field = V4L2_FIELD_NONE;
> + /* TODO: quantization */
> + pixm->quantization = 0;
> +
> + fcc_xysubs(fmt->fourcc, &xsubs, &ysubs);
> + planes = fmt->cplanes ? fmt->cplanes : fmt->mplanes;
> + for (i = 0; i < planes; i++) {
> + struct v4l2_plane_pix_format *plane_fmt;
> + int width, height, bytesperline;
> +
> + plane_fmt = pixm->plane_fmt + i;
> +
> + if (i == 0) {
> + width = pixm->width;
> + height = pixm->height;
> + } else {
> + width = pixm->width / xsubs;
> + height = pixm->height / ysubs;
> + }
> +
> + bytesperline = width * DIV_ROUND_UP(fmt->bpp[i], 8);
> + /* stride is only available for sp stream and y plane */
> + if (stream->id != RKISP1_STREAM_SP || i != 0 ||
> + plane_fmt->bytesperline < bytesperline)
> + plane_fmt->bytesperline = bytesperline;
> +
> + plane_fmt->sizeimage = plane_fmt->bytesperline * height;
> +
> + imagsize += plane_fmt->sizeimage;
> + }
> +
> + /* convert to non-MPLANE format */
> + if (fmt->mplanes == 1)
> + pixm->plane_fmt[0].sizeimage = imagsize;
> +
> + if (!try) {
> + stream->out_isp_fmt = *fmt;
> + stream->out_fmt = *pixm;
> +
> + if (stream->id == RKISP1_STREAM_SP) {
> + stream->u.sp.y_stride =
> + pixm->plane_fmt[0].bytesperline /
> + DIV_ROUND_UP(fmt->bpp[0], 8);
> + } else {
> + stream->u.mp.raw_enable = (fmt->fmt_type == FMT_BAYER);
> + }
> + }
> +}
> +
> +/************************* v4l2_file_operations***************************/
> +void rkisp1_stream_init(struct rkisp1_device *dev, u32 id)
> +{
> + struct rkisp1_stream *stream = &dev->stream[id];
> + struct v4l2_pix_format_mplane pixm;
> +
> + memset(stream, 0, sizeof(*stream));
> + stream->id = id;
> + stream->ispdev = dev;
> +
> + INIT_LIST_HEAD(&stream->buf_queue);
> + init_waitqueue_head(&stream->done);
> + spin_lock_init(&stream->vbq_lock);
> + if (stream->id == RKISP1_STREAM_SP) {
> + stream->ops = &rkisp1_sp_streams_ops;
> + stream->config = &rkisp1_sp_stream_config;
> + } else {
> + stream->ops = &rkisp1_mp_streams_ops;
> + stream->config = &rkisp1_mp_stream_config;
> + }
> +
> + stream->state = RKISP1_STATE_READY;
> +
> + memset(&pixm, 0, sizeof(pixm));
> + pixm.pixelformat = V4L2_PIX_FMT_YUYV;
> + pixm.width = RKISP1_DEFAULT_WIDTH;
> + pixm.height = RKISP1_DEFAULT_HEIGHT;
> + rkisp1_set_fmt(stream, &pixm, false);
> +
> + stream->dcrop.left = 0;
> + stream->dcrop.top = 0;
> + stream->dcrop.width = RKISP1_DEFAULT_WIDTH;
> + stream->dcrop.height = RKISP1_DEFAULT_HEIGHT;
> +}
> +
> +static const struct v4l2_file_operations rkisp1_fops = {
> + .open = v4l2_fh_open,
> + .release = vb2_fop_release,
> + .unlocked_ioctl = video_ioctl2,
> + .poll = vb2_fop_poll,
> + .mmap = vb2_fop_mmap,
> +};
> +
> +/*
> + * mp and sp v4l2_ioctl_ops
> + */
> +
> +/* keep for compatibility */
> +static int rkisp1_enum_input(struct file *file, void *priv,
> + struct v4l2_input *input)
> +{
> + if (input->index > 0)
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +static int rkisp1_try_fmt_vid_cap_mplane(struct file *file, void *fh,
> + struct v4l2_format *f)
> +{
> + struct rkisp1_stream *stream = video_drvdata(file);
> +
> + rkisp1_set_fmt(stream, &f->fmt.pix_mp, true);
> +
> + return 0;
> +}
> +
> +static int rkisp1_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
> + struct v4l2_fmtdesc *f)
> +{
> + struct rkisp1_stream *stream = video_drvdata(file);
> + const struct capture_fmt *fmt = NULL;
> +
> + if (f->index >= stream->config->fmt_size)
> + return -EINVAL;
> +
> + fmt = &stream->config->fmts[f->index];
> + f->pixelformat = fmt->fourcc;
> +
> + return 0;
> +}
> +
> +static int rkisp1_s_fmt_vid_cap_mplane(struct file *file,
> + void *priv, struct v4l2_format *f)
> +{
> + struct rkisp1_stream *stream = video_drvdata(file);
> + struct video_device *vdev = &stream->vnode.vdev;
> + struct rkisp1_vdev_node *node = vdev_to_node(vdev);
> + struct rkisp1_device *dev = stream->ispdev;
> +
> + if (vb2_is_busy(&node->buf_queue)) {
> + v4l2_err(&dev->v4l2_dev, "%s queue busy\n", __func__);
> + return -EBUSY;
> + }
> +
> + rkisp1_set_fmt(stream, &f->fmt.pix_mp, false);
> +
> + return 0;
> +}
> +
> +static int rkisp1_g_fmt_vid_cap_mplane(struct file *file, void *fh,
> + struct v4l2_format *f)
> +{
> + struct rkisp1_stream *stream = video_drvdata(file);
> +
> + f->fmt.pix_mp = stream->out_fmt;
> +
> + return 0;
> +}
> +
> +static int rkisp1_g_selection(struct file *file, void *prv,
> + struct v4l2_selection *sel)
> +{
> + struct rkisp1_stream *stream = video_drvdata(file);
> + struct rkisp1_device *dev = stream->ispdev;
> + struct v4l2_rect *dcrop = &stream->dcrop;
> + struct v4l2_rect *input_win;
> +
> + input_win = rkisp1_get_isp_sd_win(dev);
> +
> + switch (sel->target) {
> + case V4L2_SEL_TGT_CROP_BOUNDS:
> + sel->r.width = input_win->width;
> + sel->r.height = input_win->height;
> + sel->r.left = 0;
> + sel->r.top = 0;
> + break;
> + case V4L2_SEL_TGT_CROP:
> + sel->r = *dcrop;
> + break;
> + case V4L2_SEL_TGT_COMPOSE_BOUNDS:
> + sel->r.width = stream->out_fmt.width;
> + sel->r.height = stream->out_fmt.height;
> + sel->r.left = 0;
> + sel->r.top = 0;
> + break;
> + case V4L2_SEL_TGT_COMPOSE:
> + /* The composing rectangles always have the same size */
> + sel->r.width = stream->out_fmt.width;
> + sel->r.height = stream->out_fmt.height;
> + sel->r.left = 0;
> + sel->r.top = 0;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int rkisp1_s_selection(struct file *file, void *prv,
> + struct v4l2_selection *sel)
> +{
> + struct rkisp1_stream *stream = video_drvdata(file);
> + struct rkisp1_device *dev = stream->ispdev;
> + struct v4l2_rect *dcrop = &stream->dcrop;
> + struct v4l2_rect *input_win;
> +
> + input_win = rkisp1_get_isp_sd_win(dev);
> +
> + if (sel->target != V4L2_SEL_TGT_CROP &&
> + sel->target != V4L2_SEL_TGT_COMPOSE)
> + return -EINVAL;
> +
> + if (sel->flags != 0)
> + return -EINVAL;
> +
> + if (sel->target == V4L2_SEL_TGT_CROP) {
> + sel->r.left = ALIGN(sel->r.left, 2);
> + sel->r.width = ALIGN(sel->r.width, 2);
> +
> + sel->r.left =
> + clamp_t(u32, sel->r.left, 0,
> + input_win->width - STREAM_MIN_MP_SP_INPUT_WIDTH);
> + sel->r.top =
> + clamp_t(u32, sel->r.top, 0,
> + input_win->height - STREAM_MIN_MP_SP_INPUT_HEIGHT);
> + sel->r.width =
> + clamp_t(u32, sel->r.width,
> + STREAM_MIN_MP_SP_INPUT_WIDTH,
> + input_win->width - sel->r.left);
> + sel->r.height =
> + clamp_t(u32, sel->r.height,
> + STREAM_MIN_MP_SP_INPUT_HEIGHT,
> + input_win->height - sel->r.top);
> +
> + /* check whether input fmt is raw */
> + if (stream->id == RKISP1_STREAM_MP &&
> + stream->out_isp_fmt.fmt_type == FMT_BAYER) {
> + sel->r.left = 0;
> + sel->r.top = 0;
> + sel->r.width = input_win->width;
> + sel->r.height = input_win->height;
> + }
> +
> + *dcrop = sel->r;
> + } else if (sel->target == V4L2_SEL_TGT_COMPOSE) {
> + /* CamHal compatibility */
Huh? If you don't support compose, then this shouldn't be indicated.
When you say "CamHal compatibility" then I assume you refer to a Rockchip
Android Camera HAL implementation? I think it should be fixed there instead
of adding a hack here.
> + sel->r.left = 0;
> + sel->r.top = 0;
> + sel->r.width = stream->out_fmt.width;
> + sel->r.height = stream->out_fmt.height;
> + }
> +
> + return 0;
> +}
> +
> +static int rkisp1_querycap(struct file *file, void *priv,
> + struct v4l2_capability *cap)
> +{
> + struct rkisp1_stream *stream = video_drvdata(file);
> + struct device *dev = stream->ispdev->dev;
> +
> + strlcpy(cap->driver, dev->driver->name, sizeof(cap->driver));
> + strlcpy(cap->card, dev->driver->name, sizeof(cap->card));
> + snprintf(cap->bus_info, sizeof(cap->bus_info),
> + "platform:%s", dev_name(dev));
> +
> + return 0;
> +}
> +
> +static const struct v4l2_ioctl_ops rkisp1_v4l2_ioctl_ops = {
> + .vidioc_reqbufs = vb2_ioctl_reqbufs,
> + .vidioc_querybuf = vb2_ioctl_querybuf,
> + .vidioc_create_bufs = vb2_ioctl_create_bufs,
> + .vidioc_qbuf = vb2_ioctl_qbuf,
> + .vidioc_expbuf = vb2_ioctl_expbuf,
> + .vidioc_dqbuf = vb2_ioctl_dqbuf,
vidioc_preparebuf is missing.
> + .vidioc_streamon = vb2_ioctl_streamon,
> + .vidioc_streamoff = vb2_ioctl_streamoff,
> + .vidioc_enum_input = rkisp1_enum_input,
> + .vidioc_try_fmt_vid_cap_mplane = rkisp1_try_fmt_vid_cap_mplane,
> + .vidioc_enum_fmt_vid_cap_mplane = rkisp1_enum_fmt_vid_cap_mplane,
> + .vidioc_s_fmt_vid_cap_mplane = rkisp1_s_fmt_vid_cap_mplane,
> + .vidioc_g_fmt_vid_cap_mplane = rkisp1_g_fmt_vid_cap_mplane,
> + .vidioc_s_selection = rkisp1_s_selection,
> + .vidioc_g_selection = rkisp1_g_selection,
> + .vidioc_querycap = rkisp1_querycap,
> +};
> +
> +static void rkisp1_unregister_stream_vdev(struct rkisp1_stream *stream)
> +{
> + media_entity_cleanup(&stream->vnode.vdev.entity);
> + video_unregister_device(&stream->vnode.vdev);
> +}
> +
> +void rkisp1_unregister_stream_vdevs(struct rkisp1_device *dev)
> +{
> + struct rkisp1_stream *mp_stream = &dev->stream[RKISP1_STREAM_MP];
> + struct rkisp1_stream *sp_stream = &dev->stream[RKISP1_STREAM_SP];
> +
> + rkisp1_unregister_stream_vdev(mp_stream);
> + rkisp1_unregister_stream_vdev(sp_stream);
> +}
> +
> +static int rkisp1_register_stream_vdev(struct rkisp1_stream *stream)
> +{
> + struct rkisp1_device *dev = stream->ispdev;
> + struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
> + struct video_device *vdev = &stream->vnode.vdev;
> + struct rkisp1_vdev_node *node;
> + int ret;
> +
> + strlcpy(vdev->name,
> + stream->id == RKISP1_STREAM_SP ? SP_VDEV_NAME : MP_VDEV_NAME,
> + sizeof(vdev->name));
> + node = vdev_to_node(vdev);
> + mutex_init(&node->vlock);
> +
> + vdev->ioctl_ops = &rkisp1_v4l2_ioctl_ops;
> + vdev->release = video_device_release_empty;
> + vdev->fops = &rkisp1_fops;
> + vdev->minor = -1;
> + vdev->v4l2_dev = v4l2_dev;
> + vdev->lock = &node->vlock;
> + vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
> + V4L2_CAP_STREAMING;
> + video_set_drvdata(vdev, stream);
> + vdev->vfl_dir = VFL_DIR_RX;
> + node->pad.flags = MEDIA_PAD_FL_SINK;
> +
> + rkisp_init_vb2_queue(&node->buf_queue, stream,
> + V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
> + vdev->queue = &node->buf_queue;
> +
> + ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
> + if (ret < 0) {
> + v4l2_err(v4l2_dev,
> + "video_register_device failed with error %d\n", ret);
> + return ret;
> + }
> +
> + vdev->entity.function = MEDIA_ENT_F_IO_V4L;
> + ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
> + if (ret < 0)
> + goto unreg;
> +
> + return 0;
> +unreg:
> + video_unregister_device(vdev);
> + return ret;
> +}
> +
> +int rkisp1_register_stream_vdevs(struct rkisp1_device *dev)
> +{
> + struct rkisp1_stream *stream;
> + int i, j, ret;
> +
> + for (i = 0; i < RKISP1_MAX_STREAM; i++) {
> + stream = &dev->stream[i];
> + stream->ispdev = dev;
> + ret = rkisp1_register_stream_vdev(stream);
> + if (ret < 0)
> + goto err;
> + }
> +
> + return 0;
> +err:
> + for (j = 0; j < i; j++) {
> + stream = &dev->stream[j];
> + rkisp1_unregister_stream_vdev(stream);
> + }
> +
> + return ret;
> +}
> +
> +void rkisp1_mi_isr(struct rkisp1_stream *stream)
> +{
> + struct rkisp1_device *dev = stream->ispdev;
> + void __iomem *base = stream->ispdev->base_addr;
> + u32 val;
> +
> + stream->ops->clr_frame_end_int(base);
> + val = stream->ops->is_frame_end_int_masked(base);
> + if (val) {
> + val = mi_get_masked_int_status(base);
> + v4l2_err(&dev->v4l2_dev, "icr err: 0x%x\n", val);
> + }
> +
> + mi_frame_end(stream);
> +
> + if (stream->stop) {
> + stream->ops->stop_mi(stream);
> + stream->stop = false;
> + stream->state = RKISP1_STATE_READY;
> + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
> + "stream %d stopped\n", stream->id);
> + wake_up(&stream->done);
> + }
> +}
> diff --git a/drivers/media/platform/rockchip/isp1/capture.h b/drivers/media/platform/rockchip/isp1/capture.h
> new file mode 100644
> index 000000000000..e30d49deb214
> --- /dev/null
> +++ b/drivers/media/platform/rockchip/isp1/capture.h
> @@ -0,0 +1,46 @@
> +/*
> + * Rockchip isp1 driver
> + *
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + *
> + * This software is available to you under a choice of one of two
> + * licenses. You may choose to be licensed under the terms of the GNU
> + * General Public License (GPL) Version 2, available from the file
> + * COPYING in the main directory of this source tree, or the
> + * OpenIB.org BSD license below:
> + *
> + * Redistribution and use in source and binary forms, with or
> + * without modification, are permitted provided that the following
> + * conditions are met:
> + *
> + * - Redistributions of source code must retain the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer.
> + *
> + * - Redistributions in binary form must reproduce the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer in the documentation and/or other materials
> + * provided with the distribution.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#ifndef _RKISP1_PATH_VIDEO_H
> +#define _RKISP1_PATH_VIDEO_H
> +
> +struct rkisp1_device;
> +struct rkisp1_stream;
> +
> +void rkisp1_unregister_stream_vdevs(struct rkisp1_device *dev);
> +int rkisp1_register_stream_vdevs(struct rkisp1_device *dev);
> +void rkisp1_mi_isr(struct rkisp1_stream *stream);
> +void rkisp1_stream_init(struct rkisp1_device *dev, u32 id);
> +
> +#endif /* _RKISP1_PATH_VIDEO_H */
> diff --git a/drivers/media/platform/rockchip/isp1/common.h b/drivers/media/platform/rockchip/isp1/common.h
> new file mode 100644
> index 000000000000..5c5b8c3814ea
> --- /dev/null
> +++ b/drivers/media/platform/rockchip/isp1/common.h
> @@ -0,0 +1,330 @@
> +/*
> + * Rockchip isp1 driver
> + *
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + *
> + * This software is available to you under a choice of one of two
> + * licenses. You may choose to be licensed under the terms of the GNU
> + * General Public License (GPL) Version 2, available from the file
> + * COPYING in the main directory of this source tree, or the
> + * OpenIB.org BSD license below:
> + *
> + * Redistribution and use in source and binary forms, with or
> + * without modification, are permitted provided that the following
> + * conditions are met:
> + *
> + * - Redistributions of source code must retain the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer.
> + *
> + * - Redistributions in binary form must reproduce the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer in the documentation and/or other materials
> + * provided with the distribution.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#ifndef _RKISP1_COMMON_H
> +#define _RKISP1_COMMON_H
> +
> +#include <media/media-device.h>
> +#include <media/media-entity.h>
> +#include <media/v4l2-ctrls.h>
> +#include <media/v4l2-device.h>
> +#include <media/videobuf2-v4l2.h>
> +
> +#define DRIVER_NAME "rkisp1"
> +#define ISP_VDEV_NAME DRIVER_NAME "_ispdev"
> +#define SP_VDEV_NAME DRIVER_NAME "_selfpath"
> +#define MP_VDEV_NAME DRIVER_NAME "_mainpath"
> +#define DMA_VDEV_NAME DRIVER_NAME "_dmapath"
> +
> +#define GRP_ID_SENSOR BIT(0)
> +#define GRP_ID_MIPIPHY BIT(1)
> +#define GRP_ID_ISP BIT(2)
> +#define GRP_ID_ISP_MP BIT(3)
> +#define GRP_ID_ISP_SP BIT(4)
> +
> +#define RKISP1_DEFAULT_WIDTH 800
> +#define RKISP1_DEFAULT_HEIGHT 600
> +
> +#define RKISP1_MAX_STREAM 2
> +#define RKISP1_STREAM_SP 0
> +#define RKISP1_STREAM_MP 1
> +
> +#define RKISP1_PLANE_Y 0
> +#define RKISP1_PLANE_CB 1
> +#define RKISP1_PLANE_CR 2
> +
> +#define RKISP1_PIPELINE_MAX 4
> +
> +enum rkisp1_sd_type {
> + RKISP1_SD_SENSOR,
> + RKISP1_SD_PHY_CSI,
> + RKISP1_SD_VCM,
> + RKISP1_SD_FLASH,
> + RKISP1_SD_MAX,
> +};
> +
> +struct rkisp1_pipeline;
> +
> +/*
> + * struct rkisp1_pipeline - An ISP hardware pipeline
> + * @entities: Bitmask of entities in the pipeline (indexed by entity ID)
> + */
> +struct rkisp1_pipeline {
> + struct media_pipeline pipe;
> + int num_subdevs;
> + struct v4l2_subdev *subdevs[RKISP1_PIPELINE_MAX];
> + int (*open)(struct rkisp1_pipeline *p,
> + struct media_entity *me, bool prepare);
> + int (*close)(struct rkisp1_pipeline *p);
> + int (*set_stream)(struct rkisp1_pipeline *p, bool on);
> +};
> +
> +/* One structure per video node */
> +struct rkisp1_vdev_node {
> + struct vb2_queue buf_queue;
> + /* vfd lock */
> + struct mutex vlock;
> + struct video_device vdev;
> + struct media_pad pad;
> +};
> +
> +enum rkisp1_fmt_pix_type {
> + FMT_YUV,
> + FMT_RGB,
> + FMT_BAYER,
> + FMT_JPEG,
> + FMT_MAX
> +};
> +
> +enum rkisp1_fmt_raw_pat_type {
> + RAW_RGGB = 0,
> + RAW_GRBG,
> + RAW_GBRG,
> + RAW_BGGR,
> +};
> +
> +struct ispsd_in_fmt {
> + u32 mbus_code;
> + u8 fmt_type;
> + u32 mipi_dt;
> + u32 yuv_seq;
> + enum rkisp1_fmt_raw_pat_type bayer_pat;
> + u8 bus_width;
> +};
> +
> +struct ispsd_out_fmt {
> + u32 mbus_code;
> + u8 fmt_type;
> +};
> +
> +/*
> + * @fourcc: pixel format
> + * @mbus_code: pixel format over bus
> + * @fmt_type: helper filed for pixel format
> + * @bpp: bits per pixel
> + * @bayer_pat: bayer patten type
> + * @cplanes: number of colour planes
> + * @mplanes: number of stored memory planes
> + * @uv_swap: if cb cr swaped, for yuv
> + * @write_format: defines how YCbCr self picture data is written to memory
> + * @input_format: defines sp input format
> + * @output_format: defines sp output format
> + */
> +struct capture_fmt {
> + u32 fourcc;
> + u32 mbus_code;
> + u8 fmt_type;
> + u8 cplanes;
> + u8 mplanes;
> + u8 uv_swap;
> + u32 write_format;
> + u32 output_format;
> + u8 bpp[VIDEO_MAX_PLANES];
> +};
> +
> +enum rkisp1_state {
> + /* path not yet opened: */
> + RKISP1_STATE_DISABLED,
> + /* path opened and configured, ready for streaming: */
> + RKISP1_STATE_READY,
> + /* path is streaming: */
> + RKISP1_STATE_STREAMING
> +};
> +
> +struct rkisp1_buffer {
> + struct vb2_v4l2_buffer vb;
> + struct list_head queue;
> + union {
> + u32 buff_addr[VIDEO_MAX_PLANES];
> + void *vaddr[VIDEO_MAX_PLANES];
> + };
> +};
> +
> +struct rkisp1_dummy_buffer {
> + void *vaddr;
> + dma_addr_t dma_addr;
> + u32 size;
> +};
> +
> +enum rkisp1_sp_inp {
> + RKISP1_SP_INP_ISP,
> + RKISP1_SP_INP_DMA_SP,
> + RKISP1_SP_INP_MAX
> +};
> +
> +struct rkisp1_device;
> +struct rkisp1_stream;
> +
> +struct rkisp1_stream_sp {
> + int y_stride;
> + enum rkisp1_sp_inp input_sel;
> +};
> +
> +struct rkisp1_stream_mp {
> + bool raw_enable;
> +};
> +
> +struct stream_config {
> + const struct capture_fmt *fmts;
> + int fmt_size;
> + /* constrains */
> + const int max_rsz_width;
> + const int max_rsz_height;
> + const int min_rsz_width;
> + const int min_rsz_height;
> + /* registers */
> + struct {
> + u32 ctrl;
> + u32 ctrl_shd;
> + u32 scale_hy;
> + u32 scale_hcr;
> + u32 scale_hcb;
> + u32 scale_vy;
> + u32 scale_vc;
> + u32 scale_lut;
> + u32 scale_lut_addr;
> + u32 scale_hy_shd;
> + u32 scale_hcr_shd;
> + u32 scale_hcb_shd;
> + u32 scale_vy_shd;
> + u32 scale_vc_shd;
> + u32 phase_hy;
> + u32 phase_hc;
> + u32 phase_vy;
> + u32 phase_vc;
> + u32 phase_hy_shd;
> + u32 phase_hc_shd;
> + u32 phase_vy_shd;
> + u32 phase_vc_shd;
> + } rsz;
> + struct {
> + u32 ctrl;
> + u32 yuvmode_mask;
> + u32 rawmode_mask;
> + u32 h_offset;
> + u32 v_offset;
> + u32 h_size;
> + u32 v_size;
> + } dual_crop;
> + struct {
> + u32 y_size_init;
> + u32 cb_size_init;
> + u32 cr_size_init;
> + u32 y_base_ad_init;
> + u32 cb_base_ad_init;
> + u32 cr_base_ad_init;
> + u32 y_offs_cnt_init;
> + u32 cb_offs_cnt_init;
> + u32 cr_offs_cnt_init;
> + } mi;
> +};
> +
> +struct streams_ops {
> + int (*check_against)(struct rkisp1_stream *stream);
> + int (*config_mi)(struct rkisp1_stream *stream);
> + void (*stop_mi)(struct rkisp1_stream *stream);
> + void (*enable_mi)(struct rkisp1_stream *stream);
> + void (*disable_mi)(struct rkisp1_stream *stream);
> + void (*set_data_path)(void __iomem *base);
> + void (*clr_frame_end_int)(void __iomem *base);
> + u32 (*is_frame_end_int_masked)(void __iomem *base);
> +};
> +
> +struct rkisp1_stream {
> + u32 id;
> + struct rkisp1_device *ispdev;
> + struct rkisp1_vdev_node vnode;
> + enum rkisp1_state state;
> + enum rkisp1_state saved_state;
> + struct capture_fmt out_isp_fmt;
> + struct v4l2_pix_format_mplane out_fmt;
> + struct v4l2_rect dcrop;
> + struct streams_ops *ops;
> + struct stream_config *config;
> + /* spinlock for videobuf queues */
> + spinlock_t vbq_lock;
> + /* mi config */
> + struct list_head buf_queue;
> + struct rkisp1_dummy_buffer dummy_buf;
> + struct rkisp1_buffer *curr_buf;
> + struct rkisp1_buffer *next_buf;
> + bool stop;
> + wait_queue_head_t done;
> + union {
> + struct rkisp1_stream_sp sp;
> + struct rkisp1_stream_mp mp;
> + } u;
> +};
> +
> +extern int rkisp1_debug;
> +
> +static inline u32 rkisp1_get_colorspace(u32 fmt_type)
> +{
> + switch (fmt_type) {
> + case FMT_BAYER:
> + return V4L2_COLORSPACE_SRGB;
> + case FMT_YUV:
> + case FMT_JPEG:
> + return V4L2_COLORSPACE_JPEG;
> + case FMT_RGB:
> + return V4L2_COLORSPACE_RAW;
> + default:
> + return V4L2_COLORSPACE_DEFAULT;
This is wrong. The colorspace needs to come from the source subdevice.
You can't set it here, the ISP won't know it. Instead read it from the
media bus format.
> + }
> +}
> +
> +static inline
> +struct rkisp1_vdev_node *vdev_to_node(struct video_device *vdev)
> +{
> + return container_of(vdev, struct rkisp1_vdev_node, vdev);
> +}
> +
> +static inline struct rkisp1_vdev_node *queue_to_node(struct vb2_queue *q)
> +{
> + return container_of(q, struct rkisp1_vdev_node, buf_queue);
> +}
> +
> +static inline struct rkisp1_buffer *to_rkisp1_buffer(struct vb2_v4l2_buffer *vb)
> +{
> + return container_of(vb, struct rkisp1_buffer, vb);
> +}
> +
> +static inline struct vb2_queue *to_vb2_queue(struct file *file)
> +{
> + struct rkisp1_vdev_node *vnode = video_drvdata(file);
> +
> + return &vnode->buf_queue;
> +}
> +
> +#endif /* _RKISP1_COMMON_H */
> diff --git a/drivers/media/platform/rockchip/isp1/dev.c b/drivers/media/platform/rockchip/isp1/dev.c
> new file mode 100644
> index 000000000000..3d6537077209
> --- /dev/null
> +++ b/drivers/media/platform/rockchip/isp1/dev.c
> @@ -0,0 +1,632 @@
> +/*
> + * Rockchip isp1 driver
> + *
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + *
> + * This software is available to you under a choice of one of two
> + * licenses. You may choose to be licensed under the terms of the GNU
> + * General Public License (GPL) Version 2, available from the file
> + * COPYING in the main directory of this source tree, or the
> + * OpenIB.org BSD license below:
> + *
> + * Redistribution and use in source and binary forms, with or
> + * without modification, are permitted provided that the following
> + * conditions are met:
> + *
> + * - Redistributions of source code must retain the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer.
> + *
> + * - Redistributions in binary form must reproduce the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer in the documentation and/or other materials
> + * provided with the distribution.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_graph.h>
> +#include <linux/of_platform.h>
> +#include <linux/pm_runtime.h>
> +#include "regs.h"
> +#include "rkisp1.h"
> +
> +struct isp_match_data {
> + const char * const *clks;
> + int size;
> +};
> +
> +int rkisp1_debug;
> +module_param_named(debug, rkisp1_debug, int, 0644);
> +MODULE_PARM_DESC(debug, "Debug level (0-1)");
> +
> +static int __isp_pipeline_prepare(struct rkisp1_pipeline *p,
> + struct media_entity *me)
> +{
> + struct rkisp1_device *dev = container_of(p, struct rkisp1_device, pipe);
> + struct v4l2_subdev *sd;
> + int i;
> +
> + p->num_subdevs = 0;
> + memset(p->subdevs, 0, sizeof(p->subdevs));
> +
> + while (1) {
> + struct media_pad *pad = NULL;
> +
> + /* Find remote source pad */
> + for (i = 0; i < me->num_pads; i++) {
> + struct media_pad *spad = &me->pads[i];
> +
> + if (!(spad->flags & MEDIA_PAD_FL_SINK))
> + continue;
> + pad = media_entity_remote_pad(spad);
> + if (pad)
> + break;
> + }
> +
> + if (!pad)
> + break;
> +
> + sd = media_entity_to_v4l2_subdev(pad->entity);
> + if (sd != &dev->isp_sdev.sd)
> + p->subdevs[p->num_subdevs++] = sd;
> +
> + me = &sd->entity;
> + if (me->num_pads == 1)
> + break;
> + }
> + return 0;
> +}
> +
> +static int __subdev_set_power(struct v4l2_subdev *sd, int on)
> +{
> + int *use_count;
> + int ret;
> +
> + v4l2_info(sd, "%d: name %s,on %d\n", __LINE__, sd->name, on);
> +
> + if (!sd)
> + return -ENXIO;
> +
> + use_count = &sd->entity.use_count;
> + if (on && (*use_count)++ > 0)
> + return 0;
> + else if (!on && (*use_count == 0 || --(*use_count) > 0))
> + return 0;
> + ret = v4l2_subdev_call(sd, core, s_power, on);
> +
> + return ret != -ENOIOCTLCMD ? ret : 0;
> +}
> +
> +static int __isp_pipeline_s_power(struct rkisp1_pipeline *p, bool on)
> +{
> + struct rkisp1_device *dev = container_of(p, struct rkisp1_device, pipe);
> + int i, ret;
> +
> + if (on) {
> + __subdev_set_power(&dev->isp_sdev.sd, true);
> +
> + for (i = p->num_subdevs - 1; i >= 0; --i) {
> + ret = __subdev_set_power(p->subdevs[i], true);
> + if (ret < 0 && ret != -ENXIO)
> + goto err_power_off;
> + }
> + } else {
> + for (i = 0; i < p->num_subdevs; ++i)
> + __subdev_set_power(p->subdevs[i], false);
> +
> + __subdev_set_power(&dev->isp_sdev.sd, false);
> + }
> +
> + return 0;
> +
> +err_power_off:
> + for (++i; i < p->num_subdevs; ++i)
> + __subdev_set_power(p->subdevs[i], false);
> + __subdev_set_power(&dev->isp_sdev.sd, true);
> + return ret;
> +}
> +
> +static int rkisp1_pipeline_open(struct rkisp1_pipeline *p,
> + struct media_entity *me,
> + bool prepare)
> +{
> + int ret;
> +
> + if (WARN_ON(!p || !me))
> + return -EINVAL;
> +
> + if (prepare)
> + __isp_pipeline_prepare(p, me);
> +
> + if (!p->num_subdevs)
> + return -EINVAL;
> +
> + ret = __isp_pipeline_s_power(p, 1);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int rkisp1_pipeline_close(struct rkisp1_pipeline *p)
> +{
> + int ret;
> +
> + ret = __isp_pipeline_s_power(p, 0);
> +
> + return ret == -ENXIO ? 0 : ret;
> +}
> +
> +static int rkisp1_pipeline_set_stream(struct rkisp1_pipeline *p, bool on)
> +{
> + struct rkisp1_device *dev = container_of(p, struct rkisp1_device, pipe);
> + int i, ret;
> +
> + if (on)
> + v4l2_subdev_call(&dev->isp_sdev.sd, video, s_stream, true);
> +
> + for (i = 0; i < p->num_subdevs; ++i) {
> + ret = v4l2_subdev_call(p->subdevs[i], video, s_stream, on);
> + if (on && ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV)
> + goto err_stream_off;
> + }
> +
> + if (!on)
> + v4l2_subdev_call(&dev->isp_sdev.sd, video, s_stream, false);
> +
> + return 0;
> +
> +err_stream_off:
> + for (--i; i >= 0; --i)
> + v4l2_subdev_call(p->subdevs[i], video, s_stream, false);
> + v4l2_subdev_call(&dev->isp_sdev.sd, video, s_stream, false);
> + return ret;
> +}
> +
> +static int rkisp1_create_links(struct rkisp1_device *dev)
> +{
> + struct media_entity *source, *sink;
> + unsigned int flags, s, pad;
> + int ret;
> +
> + /* sensor links(or mipi-phy) */
> + for (s = 0; s < dev->num_sensors; ++s) {
> + struct rkisp1_sensor_info *sensor = &dev->sensors[s];
> +
> + for (pad = 0; pad < sensor->sd->entity.num_pads; pad++)
> + if (sensor->sd->entity.pads[pad].flags & MEDIA_PAD_FL_SOURCE)
> + break;
> +
> + if (pad == sensor->sd->entity.num_pads) {
> + dev_err(dev->dev,
> + "failed to find src pad for %s\n",
> + sensor->sd->name);
> +
> + return -ENXIO;
> + }
> +
> + ret = media_create_pad_link(&sensor->sd->entity, pad,
> + &dev->isp_sdev.sd.entity,
> + RKISP1_ISP_PAD_SINK + s,
> + s ? 0 : MEDIA_LNK_FL_ENABLED);
> + if (ret) {
> + dev_err(dev->dev,
> + "failed to create link for %s\n",
> + sensor->sd->name);
> + return ret;
> + }
> + }
> +
> + /* params links */
> + source = &dev->params_vdev.vnode.vdev.entity;
> + sink = &dev->isp_sdev.sd.entity;
> + flags = MEDIA_LNK_FL_ENABLED;
> + ret = media_create_pad_link(source, 0, sink,
> + RKISP1_ISP_PAD_SINK_PARAMS, flags);
> + if (ret < 0)
> + return ret;
> +
> + /* create isp internal links */
> + /* SP links */
> + source = &dev->isp_sdev.sd.entity;
> + sink = &dev->stream[RKISP1_STREAM_SP].vnode.vdev.entity;
> + ret = media_create_pad_link(source, RKISP1_ISP_PAD_SOURCE_PATH,
> + sink, 0, flags);
> + if (ret < 0)
> + return ret;
> +
> + /* MP links */
> + source = &dev->isp_sdev.sd.entity;
> + sink = &dev->stream[RKISP1_STREAM_MP].vnode.vdev.entity;
> + ret = media_create_pad_link(source, RKISP1_ISP_PAD_SOURCE_PATH,
> + sink, 0, flags);
> + if (ret < 0)
> + return ret;
> +
> + /* 3A stats links */
> + source = &dev->isp_sdev.sd.entity;
> + sink = &dev->stats_vdev.vnode.vdev.entity;
> + return media_create_pad_link(source, RKISP1_ISP_PAD_SOURCE_STATS,
> + sink, 0, flags);
> +}
> +
> +static int subdev_notifier_complete(struct v4l2_async_notifier *notifier)
> +{
> + struct rkisp1_device *dev;
> + int ret;
> +
> + dev = container_of(notifier, struct rkisp1_device, notifier);
> +
> + mutex_lock(&dev->media_dev.graph_mutex);
> + ret = rkisp1_create_links(dev);
> + if (ret < 0)
> + goto unlock;
> + ret = v4l2_device_register_subdev_nodes(&dev->v4l2_dev);
> + if (ret < 0)
> + goto unlock;
> +
> + v4l2_info(&dev->v4l2_dev, "Async subdev notifier completed\n");
> +
> +unlock:
> + mutex_unlock(&dev->media_dev.graph_mutex);
> + return ret;
> +}
> +
> +struct rkisp1_async_subdev {
> + struct v4l2_async_subdev asd;
> + struct v4l2_mbus_config mbus;
> +};
> +
> +static int subdev_notifier_bound(struct v4l2_async_notifier *notifier,
> + struct v4l2_subdev *subdev,
> + struct v4l2_async_subdev *asd)
> +{
> + struct rkisp1_device *isp_dev = container_of(notifier,
> + struct rkisp1_device, notifier);
> + struct rkisp1_async_subdev *s_asd = container_of(asd,
> + struct rkisp1_async_subdev, asd);
> +
> + if (isp_dev->num_sensors == ARRAY_SIZE(isp_dev->sensors))
> + return -EBUSY;
> +
> + isp_dev->sensors[isp_dev->num_sensors].mbus = s_asd->mbus;
> + isp_dev->sensors[isp_dev->num_sensors].sd = subdev;
> + ++isp_dev->num_sensors;
> +
> + v4l2_dbg(1, rkisp1_debug, subdev, "Async registered subdev\n");
> +
> + return 0;
> +}
> +
> +static int rkisp1_fwnode_parse(struct device *dev,
> + struct v4l2_fwnode_endpoint *vep,
> + struct v4l2_async_subdev *asd)
> +{
> + struct rkisp1_async_subdev *rk_asd =
> + container_of(asd, struct rkisp1_async_subdev, asd);
> + struct v4l2_fwnode_bus_parallel *bus = &vep->bus.parallel;
> +
> + if (vep->bus_type != V4L2_MBUS_BT656 &&
> + vep->bus_type != V4L2_MBUS_PARALLEL)
> + return 0;
> +
> + rk_asd->mbus.flags = bus->flags;
> + rk_asd->mbus.type = vep->bus_type;
> +
> + return 0;
> +}
> +
> +static const struct v4l2_async_notifier_operations subdev_notifier_ops = {
> + .bound = subdev_notifier_bound,
> + .complete = subdev_notifier_complete,
> +};
> +
> +static int isp_subdev_notifier(struct rkisp1_device *isp_dev)
> +{
> + struct v4l2_async_notifier *ntf = &isp_dev->notifier;
> + struct device *dev = isp_dev->dev;
> + int ret;
> +
> + ret = v4l2_async_notifier_parse_fwnode_endpoints(dev, ntf,
> + sizeof(struct rkisp1_async_subdev), rkisp1_fwnode_parse);
> + if (ret < 0)
> + return ret;
> +
> + if (!ntf->num_subdevs)
> + return -ENODEV; /* no endpoint */
> +
> + ntf->ops = &subdev_notifier_ops;
> +
> + return v4l2_async_notifier_register(&isp_dev->v4l2_dev, ntf);
> +}
> +
> +static int rkisp1_register_platform_subdevs(struct rkisp1_device *dev)
> +{
> + int ret;
> +
> + ret = rkisp1_register_isp_subdev(dev, &dev->v4l2_dev);
> + if (ret < 0)
> + return ret;
> +
> + ret = rkisp1_register_stream_vdevs(dev);
> + if (ret < 0)
> + goto err_unreg_isp_subdev;
> +
> + ret = rkisp1_register_stats_vdev(&dev->stats_vdev, &dev->v4l2_dev, dev);
> + if (ret < 0)
> + goto err_unreg_stream_vdev;
> +
> + ret = rkisp1_register_params_vdev(&dev->params_vdev, &dev->v4l2_dev,
> + dev);
> + if (ret < 0)
> + goto err_unreg_stats_vdev;
> +
> + ret = isp_subdev_notifier(dev);
> + if (ret < 0) {
> + v4l2_err(&dev->v4l2_dev,
> + "Failed to register subdev notifier(%d)\n", ret);
> + goto err_unreg_params_vdev;
> + }
> +
> + return 0;
> +err_unreg_params_vdev:
> + rkisp1_unregister_params_vdev(&dev->params_vdev);
> +err_unreg_stats_vdev:
> + rkisp1_unregister_stats_vdev(&dev->stats_vdev);
> +err_unreg_stream_vdev:
> + rkisp1_unregister_stream_vdevs(dev);
> +err_unreg_isp_subdev:
> + rkisp1_unregister_isp_subdev(dev);
> + return ret;
> +}
> +
> +static const char * const rk3399_isp_clks[] = {
> + "clk_isp",
> + "aclk_isp",
> + "hclk_isp",
> + "aclk_isp_wrap",
> + "hclk_isp_wrap",
> +};
> +
> +static const char * const rk3288_isp_clks[] = {
> + "clk_isp",
> + "aclk_isp",
> + "hclk_isp",
> + "pclk_isp_in",
> + "sclk_isp_jpe",
> +};
> +
> +static const struct isp_match_data rk3288_isp_clk_data = {
> + .clks = rk3288_isp_clks,
> + .size = ARRAY_SIZE(rk3288_isp_clks),
> +};
> +
> +static const struct isp_match_data rk3399_isp_clk_data = {
> + .clks = rk3399_isp_clks,
> + .size = ARRAY_SIZE(rk3399_isp_clks),
> +};
> +
> +static const struct of_device_id rkisp1_plat_of_match[] = {
> + {
> + .compatible = "rockchip,rk3288-cif-isp",
> + .data = &rk3288_isp_clk_data,
> + }, {
> + .compatible = "rockchip,rk3399-cif-isp",
> + .data = &rk3399_isp_clk_data,
> + },
> + {},
> +};
> +
> +static irqreturn_t rkisp1_irq_handler(int irq, void *cntxt)
> +{
> + struct device *dev = cntxt;
> + struct rkisp1_device *rkisp1_dev = dev_get_drvdata(dev);
> + void __iomem *base = rkisp1_dev->base_addr;
> + unsigned int mis_val, i;
> +
> + mis_val = readl(rkisp1_dev->base_addr + CIF_ISP_MIS);
> + if (mis_val)
> + rkisp1_isp_isr(mis_val, rkisp1_dev);
> +
> + mis_val = readl(rkisp1_dev->base_addr + CIF_MIPI_MIS);
> + if (mis_val)
> + rkisp1_mipi_isr(mis_val, rkisp1_dev);
> +
> + for (i = 0; i < RKISP1_MAX_STREAM; ++i) {
> + struct rkisp1_stream *stream = &rkisp1_dev->stream[i];
> +
> + mis_val = stream->ops->is_frame_end_int_masked(base);
> + if (mis_val)
> + rkisp1_mi_isr(stream);
> + }
> +
> + clr_all_int(base);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void rkisp1_disable_sys_clk(struct rkisp1_device *rkisp1_dev)
> +{
> + int i;
> +
> + for (i = rkisp1_dev->clk_size - 1; i >= 0; i--)
> + clk_disable_unprepare(rkisp1_dev->clks[i]);
> +}
> +
> +static int rkisp1_enable_sys_clk(struct rkisp1_device *rkisp1_dev)
> +{
> + int i, ret = -EINVAL;
> +
> + for (i = 0; i < rkisp1_dev->clk_size; i++) {
> + ret = clk_prepare_enable(rkisp1_dev->clks[i]);
> + if (ret < 0)
> + goto err;
> + }
> + return 0;
> +err:
> + for (--i; i >= 0; --i)
> + clk_disable_unprepare(rkisp1_dev->clks[i]);
> + return ret;
> +}
> +
> +static int rkisp1_plat_probe(struct platform_device *pdev)
> +{
> + const struct of_device_id *match;
> + struct device_node *node = pdev->dev.of_node;
> + struct device *dev = &pdev->dev;
> + struct v4l2_device *v4l2_dev;
> + struct rkisp1_device *isp_dev;
> + const struct isp_match_data *clk_data;
> +
> + struct resource *res;
> + int i, ret, irq;
> +
> + match = of_match_node(rkisp1_plat_of_match, node);
> + isp_dev = devm_kzalloc(dev, sizeof(*isp_dev), GFP_KERNEL);
> + if (!isp_dev)
> + return -ENOMEM;
> +
> + dev_set_drvdata(dev, isp_dev);
> + atomic_set(&isp_dev->poweron_cnt, 0);
> + isp_dev->dev = dev;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + isp_dev->base_addr = devm_ioremap_resource(dev, res);
> + if (IS_ERR(isp_dev->base_addr))
> + return PTR_ERR(isp_dev->base_addr);
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0)
> + return irq;
> +
> + ret = devm_request_irq(dev, irq, rkisp1_irq_handler, IRQF_SHARED,
> + dev_driver_string(dev), dev);
> + if (ret < 0) {
> + dev_err(dev, "request irq failed: %d\n", ret);
> + return ret;
> + }
> +
> + isp_dev->irq = irq;
> + clk_data = match->data;
> + for (i = 0; i < clk_data->size; i++) {
> + struct clk *clk = devm_clk_get(dev, clk_data->clks[i]);
> +
> + if (IS_ERR(clk)) {
> + dev_err(dev, "failed to get %s\n", clk_data->clks[i]);
> + return PTR_ERR(clk);
> + }
> + isp_dev->clks[i] = clk;
> + }
> + isp_dev->clk_size = clk_data->size;
> +
> + isp_dev->pipe.open = rkisp1_pipeline_open;
> + isp_dev->pipe.close = rkisp1_pipeline_close;
> + isp_dev->pipe.set_stream = rkisp1_pipeline_set_stream;
> +
> + rkisp1_stream_init(isp_dev, RKISP1_STREAM_SP);
> + rkisp1_stream_init(isp_dev, RKISP1_STREAM_MP);
> +
> + strlcpy(isp_dev->media_dev.model, "rkisp1",
> + sizeof(isp_dev->media_dev.model));
> + isp_dev->media_dev.dev = &pdev->dev;
> + media_device_init(&isp_dev->media_dev);
> +
> + v4l2_dev = &isp_dev->v4l2_dev;
> + v4l2_dev->mdev = &isp_dev->media_dev;
> + strlcpy(v4l2_dev->name, "rkisp1", sizeof(v4l2_dev->name));
> +
> + ret = v4l2_device_register(isp_dev->dev, &isp_dev->v4l2_dev);
> + if (ret < 0)
> + return ret;
> +
> + ret = media_device_register(&isp_dev->media_dev);
> + if (ret < 0) {
> + v4l2_err(v4l2_dev, "Failed to register media device: %d\n",
> + ret);
> + goto err_unreg_v4l2_dev;
> + }
> +
> + /* create & register platefom subdev (from of_node) */
> + ret = rkisp1_register_platform_subdevs(isp_dev);
> + if (ret < 0)
> + goto err_unreg_media_dev;
> +
> + pm_runtime_enable(&pdev->dev);
> +
> + return 0;
> +
> +err_unreg_media_dev:
> + media_device_unregister(&isp_dev->media_dev);
> +err_unreg_v4l2_dev:
> + v4l2_device_unregister(&isp_dev->v4l2_dev);
> + return ret;
> +}
> +
> +static int rkisp1_plat_remove(struct platform_device *pdev)
> +{
> + struct rkisp1_device *isp_dev = platform_get_drvdata(pdev);
> +
> + pm_runtime_disable(&pdev->dev);
> + media_device_unregister(&isp_dev->media_dev);
> + v4l2_device_unregister(&isp_dev->v4l2_dev);
> + rkisp1_unregister_params_vdev(&isp_dev->params_vdev);
> + rkisp1_unregister_stats_vdev(&isp_dev->stats_vdev);
> + rkisp1_unregister_stream_vdevs(isp_dev);
> + rkisp1_unregister_isp_subdev(isp_dev);
> +
> + return 0;
> +}
> +
> +static int __maybe_unused rkisp1_runtime_suspend(struct device *dev)
> +{
> + struct rkisp1_device *isp_dev = dev_get_drvdata(dev);
> +
> + rkisp1_disable_sys_clk(isp_dev);
> + return pinctrl_pm_select_sleep_state(dev);
> +}
> +
> +static int __maybe_unused rkisp1_runtime_resume(struct device *dev)
> +{
> + struct rkisp1_device *isp_dev = dev_get_drvdata(dev);
> + int ret;
> +
> + ret = pinctrl_pm_select_default_state(dev);
> + if (ret < 0)
> + return ret;
> + rkisp1_enable_sys_clk(isp_dev);
> +
> + return 0;
> +}
> +
> +static const struct dev_pm_ops rkisp1_plat_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
> + pm_runtime_force_resume)
> + SET_RUNTIME_PM_OPS(rkisp1_runtime_suspend, rkisp1_runtime_resume, NULL)
> +};
> +
> +static struct platform_driver rkisp1_plat_drv = {
> + .driver = {
> + .name = DRIVER_NAME,
> + .of_match_table = of_match_ptr(rkisp1_plat_of_match),
> + .pm = &rkisp1_plat_pm_ops,
> + },
> + .probe = rkisp1_plat_probe,
> + .remove = rkisp1_plat_remove,
> +};
> +
> +module_platform_driver(rkisp1_plat_drv);
> +MODULE_AUTHOR("Rockchip Camera/ISP team");
> +MODULE_DESCRIPTION("Rockchip ISP1 platform driver");
> +MODULE_LICENSE("Dual BSD/GPL");
> diff --git a/drivers/media/platform/rockchip/isp1/isp_params.c b/drivers/media/platform/rockchip/isp1/isp_params.c
> new file mode 100644
> index 000000000000..76c9755bde2a
> --- /dev/null
> +++ b/drivers/media/platform/rockchip/isp1/isp_params.c
> @@ -0,0 +1,1556 @@
> +/*
> + * Rockchip isp1 driver
> + *
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + *
> + * This software is available to you under a choice of one of two
> + * licenses. You may choose to be licensed under the terms of the GNU
> + * General Public License (GPL) Version 2, available from the file
> + * COPYING in the main directory of this source tree, or the
> + * OpenIB.org BSD license below:
> + *
> + * Redistribution and use in source and binary forms, with or
> + * without modification, are permitted provided that the following
> + * conditions are met:
> + *
> + * - Redistributions of source code must retain the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer.
> + *
> + * - Redistributions in binary form must reproduce the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer in the documentation and/or other materials
> + * provided with the distribution.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#include <media/v4l2-common.h>
> +#include <media/v4l2-ioctl.h>
> +#include <media/videobuf2-core.h>
> +#include <media/videobuf2-vmalloc.h> /* for ISP params */
> +#include "regs.h"
> +#include "rkisp1.h"
> +#include "isp_params.h"
> +
> +#define RKISP1_ISP_PARAMS_REQ_BUFS_MIN 2
> +#define RKISP1_ISP_PARAMS_REQ_BUFS_MAX 8
> +
> +#define BLS_START_H_MAX_IS_VALID(val) ((val) < CIFISP_BLS_START_H_MAX)
> +#define BLS_STOP_H_MAX_IS_VALID(val) ((val) < CIFISP_BLS_STOP_H_MAX)
> +
> +#define BLS_START_V_MAX_IS_VALID(val) ((val) < CIFISP_BLS_START_V_MAX)
> +#define BLS_STOP_V_MAX_IS_VALID(val) ((val) < CIFISP_BLS_STOP_V_MAX)
> +
> +#define BLS_SAMPLE_MAX_IS_VALID(val) ((val) < CIFISP_BLS_SAMPLES_MAX)
> +
> +#define BLS_FIX_SUB_IS_VALID(val) \
> + ((val) > (s16)CIFISP_BLS_FIX_SUB_MIN && (val) < CIFISP_BLS_FIX_SUB_MAX)
> +
> +static inline void rkisp1_iowrite32(struct rkisp1_isp_params_vdev *params_vdev,
> + u32 value, u32 addr)
> +{
> + iowrite32(value, params_vdev->dev->base_addr + addr);
> +}
> +
> +static inline u32 rkisp1_ioread32(struct rkisp1_isp_params_vdev *params_vdev,
> + u32 addr)
> +{
> + return ioread32(params_vdev->dev->base_addr + addr);
> +}
> +
> +static inline void isp_param_set_bits(struct rkisp1_isp_params_vdev
> + *params_vdev,
> + u32 reg, u32 bit_mask)
> +{
> + u32 val;
> +
> + val = rkisp1_ioread32(params_vdev, reg);
> + rkisp1_iowrite32(params_vdev, val | bit_mask, reg);
> +}
> +
> +static inline void isp_param_clear_bits(struct rkisp1_isp_params_vdev
> + *params_vdev,
> + u32 reg, u32 bit_mask)
> +{
> + u32 val;
> +
> + val = rkisp1_ioread32(params_vdev, reg);
> + rkisp1_iowrite32(params_vdev, val & ~bit_mask, reg);
> +}
> +
> +/* ISP BP interface function */
> +static void dpcc_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_dpcc_config *arg)
> +{
> + unsigned int i;
> +
> + rkisp1_iowrite32(params_vdev, arg->mode, CIF_ISP_DPCC_MODE);
> + rkisp1_iowrite32(params_vdev, arg->output_mode,
> + CIF_ISP_DPCC_OUTPUT_MODE);
> + rkisp1_iowrite32(params_vdev, arg->set_use, CIF_ISP_DPCC_SET_USE);
> +
> + rkisp1_iowrite32(params_vdev, arg->methods[0].method,
> + CIF_ISP_DPCC_METHODS_SET_1);
> + rkisp1_iowrite32(params_vdev, arg->methods[1].method,
> + CIF_ISP_DPCC_METHODS_SET_2);
> + rkisp1_iowrite32(params_vdev, arg->methods[2].method,
> + CIF_ISP_DPCC_METHODS_SET_3);
> + for (i = 0; i < CIFISP_DPCC_METHODS_MAX; i++) {
> + rkisp1_iowrite32(params_vdev, arg->methods[i].line_thresh,
> + CIF_ISP_DPCC_LINE_THRESH_1 + 0x14 * i);
> + rkisp1_iowrite32(params_vdev, arg->methods[i].line_mad_fac,
> + CIF_ISP_DPCC_LINE_MAD_FAC_1 + 0x14 * i);
> + rkisp1_iowrite32(params_vdev, arg->methods[i].pg_fac,
> + CIF_ISP_DPCC_PG_FAC_1 + 0x14 * i);
> + rkisp1_iowrite32(params_vdev, arg->methods[i].rnd_thresh,
> + CIF_ISP_DPCC_RND_THRESH_1 + 0x14 * i);
> + rkisp1_iowrite32(params_vdev, arg->methods[i].rg_fac,
> + CIF_ISP_DPCC_RG_FAC_1 + 0x14 * i);
> + }
> +
> + rkisp1_iowrite32(params_vdev, arg->rnd_offs, CIF_ISP_DPCC_RND_OFFS);
> + rkisp1_iowrite32(params_vdev, arg->ro_limits, CIF_ISP_DPCC_RO_LIMITS);
> +}
> +
> +/* ISP black level subtraction interface function */
> +static void bls_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_bls_config *arg)
> +{
> + u32 new_control = 0;
> +
> + /* fixed subtraction values */
> + if (!arg->enable_auto) {
> + const struct cifisp_bls_fixed_val *pval = &arg->fixed_val;
> +
> + switch (params_vdev->raw_type) {
> + case RAW_BGGR:
> + rkisp1_iowrite32(params_vdev,
> + pval->r, CIF_ISP_BLS_D_FIXED);
> + rkisp1_iowrite32(params_vdev,
> + pval->gr, CIF_ISP_BLS_C_FIXED);
> + rkisp1_iowrite32(params_vdev,
> + pval->gb, CIF_ISP_BLS_B_FIXED);
> + rkisp1_iowrite32(params_vdev,
> + pval->b, CIF_ISP_BLS_A_FIXED);
> + break;
> + case RAW_GBRG:
> + rkisp1_iowrite32(params_vdev,
> + pval->r, CIF_ISP_BLS_C_FIXED);
> + rkisp1_iowrite32(params_vdev,
> + pval->gr, CIF_ISP_BLS_D_FIXED);
> + rkisp1_iowrite32(params_vdev,
> + pval->gb, CIF_ISP_BLS_A_FIXED);
> + rkisp1_iowrite32(params_vdev,
> + pval->b, CIF_ISP_BLS_B_FIXED);
> + break;
> + case RAW_GRBG:
> + rkisp1_iowrite32(params_vdev,
> + pval->r, CIF_ISP_BLS_B_FIXED);
> + rkisp1_iowrite32(params_vdev,
> + pval->gr, CIF_ISP_BLS_A_FIXED);
> + rkisp1_iowrite32(params_vdev,
> + pval->gb, CIF_ISP_BLS_D_FIXED);
> + rkisp1_iowrite32(params_vdev,
> + pval->b, CIF_ISP_BLS_C_FIXED);
> + break;
> + case RAW_RGGB:
> + rkisp1_iowrite32(params_vdev,
> + pval->r, CIF_ISP_BLS_A_FIXED);
> + rkisp1_iowrite32(params_vdev,
> + pval->gr, CIF_ISP_BLS_B_FIXED);
> + rkisp1_iowrite32(params_vdev,
> + pval->gb, CIF_ISP_BLS_C_FIXED);
> + rkisp1_iowrite32(params_vdev,
> + pval->b, CIF_ISP_BLS_D_FIXED);
> + break;
> + default:
> + break;
> + }
> +
> + new_control = CIF_ISP_BLS_MODE_FIXED;
> + rkisp1_iowrite32(params_vdev, new_control, CIF_ISP_BLS_CTRL);
> + } else {
> + if (arg->en_windows & 2) {
> + rkisp1_iowrite32(params_vdev, arg->bls_window2.h_offs,
> + CIF_ISP_BLS_H2_START);
> + rkisp1_iowrite32(params_vdev, arg->bls_window2.h_size,
> + CIF_ISP_BLS_H2_STOP);
> + rkisp1_iowrite32(params_vdev, arg->bls_window2.v_offs,
> + CIF_ISP_BLS_V2_START);
> + rkisp1_iowrite32(params_vdev, arg->bls_window2.v_size,
> + CIF_ISP_BLS_V2_STOP);
> + new_control |= CIF_ISP_BLS_WINDOW_2;
> + }
> +
> + if (arg->en_windows & 1) {
> + rkisp1_iowrite32(params_vdev, arg->bls_window1.h_offs,
> + CIF_ISP_BLS_H1_START);
> + rkisp1_iowrite32(params_vdev, arg->bls_window1.h_size,
> + CIF_ISP_BLS_H1_STOP);
> + rkisp1_iowrite32(params_vdev, arg->bls_window1.v_offs,
> + CIF_ISP_BLS_V1_START);
> + rkisp1_iowrite32(params_vdev, arg->bls_window1.v_size,
> + CIF_ISP_BLS_V1_STOP);
> + new_control |= CIF_ISP_BLS_WINDOW_1;
> + }
> +
> + rkisp1_iowrite32(params_vdev, arg->bls_samples,
> + CIF_ISP_BLS_SAMPLES);
> +
> + new_control |= CIF_ISP_BLS_MODE_MEASURED;
> +
> + rkisp1_iowrite32(params_vdev, new_control, CIF_ISP_BLS_CTRL);
> + }
> +}
> +
> +/* ISP LS correction interface function */
> +static void
> +__lsc_correct_matrix_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_lsc_config *pconfig)
> +{
> + int i, j;
> + unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel;
> + unsigned int data;
> +
> + isp_lsc_status = rkisp1_ioread32(params_vdev, CIF_ISP_LSC_STATUS);
> +
> + /* CIF_ISP_LSC_TABLE_ADDRESS_153 = ( 17 * 18 ) >> 1 */
> + sram_addr = (isp_lsc_status & CIF_ISP_LSC_ACTIVE_TABLE) ?
> + CIF_ISP_LSC_TABLE_ADDRESS_0 :
> + CIF_ISP_LSC_TABLE_ADDRESS_153;
> + rkisp1_iowrite32(params_vdev, sram_addr, CIF_ISP_LSC_R_TABLE_ADDR);
> + rkisp1_iowrite32(params_vdev, sram_addr, CIF_ISP_LSC_GR_TABLE_ADDR);
> + rkisp1_iowrite32(params_vdev, sram_addr, CIF_ISP_LSC_GB_TABLE_ADDR);
> + rkisp1_iowrite32(params_vdev, sram_addr, CIF_ISP_LSC_B_TABLE_ADDR);
> +
> + /* program data tables (table size is 9 * 17 = 153) */
> + for (i = 0; i < ((CIF_ISP_LSC_SECTORS_MAX + 1) *
> + (CIF_ISP_LSC_SECTORS_MAX + 1));
> + i += CIF_ISP_LSC_SECTORS_MAX + 1) {
> + /*
> + * 17 sectors with 2 values in one DWORD = 9
> + * DWORDs (2nd value of last DWORD unused)
> + */
> + for (j = 0; j < (CIF_ISP_LSC_SECTORS_MAX + 1); j += 2) {
> + data = CIF_ISP_LSC_TABLE_DATA(
> + pconfig->r_data_tbl[i + j],
> + pconfig->r_data_tbl[i + j + 1]);
> + rkisp1_iowrite32(params_vdev, data,
> + CIF_ISP_LSC_R_TABLE_DATA);
> +
> + data = CIF_ISP_LSC_TABLE_DATA(
> + pconfig->gr_data_tbl[i + j],
> + pconfig->gr_data_tbl[i + j + 1]);
> + rkisp1_iowrite32(params_vdev, data,
> + CIF_ISP_LSC_GR_TABLE_DATA);
> +
> + data = CIF_ISP_LSC_TABLE_DATA(
> + pconfig->gb_data_tbl[i + j],
> + pconfig->gb_data_tbl[i + j + 1]);
> + rkisp1_iowrite32(params_vdev, data,
> + CIF_ISP_LSC_GB_TABLE_DATA);
> +
> + data = CIF_ISP_LSC_TABLE_DATA(
> + pconfig->b_data_tbl[i + j],
> + pconfig->b_data_tbl[i + j + 1]);
> + rkisp1_iowrite32(params_vdev, data,
> + CIF_ISP_LSC_B_TABLE_DATA);
> + }
> + }
> +
> + isp_lsc_table_sel = (isp_lsc_status & CIF_ISP_LSC_ACTIVE_TABLE) ?
> + CIF_ISP_LSC_TABLE_0 : CIF_ISP_LSC_TABLE_1;
> + rkisp1_iowrite32(params_vdev, isp_lsc_table_sel, CIF_ISP_LSC_TABLE_SEL);
> +}
> +
> +static void lsc_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_lsc_config *arg)
> +{
> + int i;
> + unsigned int data;
> + u32 lsc_ctrl;
> +
> + /* To config must be off , store the current status firstly */
> + lsc_ctrl = rkisp1_ioread32(params_vdev, CIF_ISP_LSC_CTRL);
> + isp_param_clear_bits(params_vdev, CIF_ISP_LSC_CTRL,
> + CIF_ISP_LSC_CTRL_ENA);
> + __lsc_correct_matrix_config(params_vdev, arg);
> +
> + if (params_vdev->active_lsc_width !=
> + arg->config_width ||
> + params_vdev->active_lsc_height != arg->config_height) {
> + for (i = 0; i < 4; i++) {
> + /* program x size tables */
> + data = CIF_ISP_LSC_SECT_SIZE(arg->x_size_tbl[i * 2],
> + arg->x_size_tbl[i * 2 + 1]);
> + rkisp1_iowrite32(params_vdev, data,
> + CIF_ISP_LSC_XSIZE_01 + i * 4);
> +
> + /* program x grad tables */
> + data = CIF_ISP_LSC_SECT_SIZE(arg->x_grad_tbl[i * 2],
> + arg->x_grad_tbl[i * 2 + 1]);
> + rkisp1_iowrite32(params_vdev, data,
> + CIF_ISP_LSC_XGRAD_01 + i * 4);
> +
> + /* program y size tables */
> + data = CIF_ISP_LSC_SECT_SIZE(arg->y_size_tbl[i * 2],
> + arg->y_size_tbl[i * 2 + 1]);
> + rkisp1_iowrite32(params_vdev, data,
> + CIF_ISP_LSC_YSIZE_01 + i * 4);
> +
> + /* program y grad tables */
> + data = CIF_ISP_LSC_SECT_SIZE(arg->y_grad_tbl[i * 2],
> + arg->y_grad_tbl[i * 2 + 1]);
> + rkisp1_iowrite32(params_vdev, data,
> + CIF_ISP_LSC_YGRAD_01 + i * 4);
> + }
> +
> + params_vdev->active_lsc_width = arg->config_width;
> + params_vdev->active_lsc_height = arg->config_height;
> + }
> +
> + /* restore the bls ctrl status */
> + if (lsc_ctrl & CIF_ISP_LSC_CTRL_ENA) {
> + isp_param_set_bits(params_vdev,
> + CIF_ISP_LSC_CTRL,
> + CIF_ISP_LSC_CTRL_ENA);
> + } else {
> + isp_param_clear_bits(params_vdev,
> + CIF_ISP_LSC_CTRL,
> + CIF_ISP_LSC_CTRL_ENA);
> + }
> +}
> +
> +/* ISP Filtering function */
> +static void flt_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_flt_config *arg)
> +{
> + rkisp1_iowrite32(params_vdev, arg->thresh_bl0, CIF_ISP_FILT_THRESH_BL0);
> + rkisp1_iowrite32(params_vdev, arg->thresh_bl1, CIF_ISP_FILT_THRESH_BL1);
> + rkisp1_iowrite32(params_vdev, arg->thresh_sh0, CIF_ISP_FILT_THRESH_SH0);
> + rkisp1_iowrite32(params_vdev, arg->thresh_sh1, CIF_ISP_FILT_THRESH_SH1);
> + rkisp1_iowrite32(params_vdev, arg->fac_bl0, CIF_ISP_FILT_FAC_BL0);
> + rkisp1_iowrite32(params_vdev, arg->fac_bl1, CIF_ISP_FILT_FAC_BL1);
> + rkisp1_iowrite32(params_vdev, arg->fac_mid, CIF_ISP_FILT_FAC_MID);
> + rkisp1_iowrite32(params_vdev, arg->fac_sh0, CIF_ISP_FILT_FAC_SH0);
> + rkisp1_iowrite32(params_vdev, arg->fac_sh1, CIF_ISP_FILT_FAC_SH1);
> + rkisp1_iowrite32(params_vdev, arg->lum_weight, CIF_ISP_FILT_LUM_WEIGHT);
> +
> + rkisp1_iowrite32(params_vdev, (arg->mode ? CIF_ISP_FLT_MODE_DNR : 0) |
> + CIF_ISP_FLT_CHROMA_V_MODE(arg->chr_v_mode) |
> + CIF_ISP_FLT_CHROMA_H_MODE(arg->chr_h_mode) |
> + CIF_ISP_FLT_GREEN_STAGE1(arg->grn_stage1),
> + CIF_ISP_FILT_MODE);
> +}
> +
> +/* ISP demosaic interface function */
> +static int bdm_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_bdm_config *arg)
> +{
> + /*set demosaic threshold */
> + rkisp1_iowrite32(params_vdev, arg->demosaic_th, CIF_ISP_DEMOSAIC);
> + return 0;
> +}
> +
> +/* ISP GAMMA correction interface function */
> +static void sdg_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_sdg_config *arg)
> +{
> + int i;
> +
> + rkisp1_iowrite32(params_vdev,
> + arg->xa_pnts.gamma_dx0, CIF_ISP_GAMMA_DX_LO);
> + rkisp1_iowrite32(params_vdev,
> + arg->xa_pnts.gamma_dx1, CIF_ISP_GAMMA_DX_HI);
> +
> + for (i = 0; i < CIFISP_DEGAMMA_CURVE_SIZE; i++) {
> + rkisp1_iowrite32(params_vdev, arg->curve_r.gamma_y[i],
> + CIF_ISP_GAMMA_R_Y0 + i * 4);
> + rkisp1_iowrite32(params_vdev, arg->curve_g.gamma_y[i],
> + CIF_ISP_GAMMA_G_Y0 + i * 4);
> + rkisp1_iowrite32(params_vdev, arg->curve_b.gamma_y[i],
> + CIF_ISP_GAMMA_B_Y0 + i * 4);
> + }
> +}
> +
> +/* ISP GAMMA correction interface function */
> +static void goc_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_goc_config *arg)
> +{
> + int i;
> +
> + isp_param_clear_bits(params_vdev, CIF_ISP_CTRL,
> + CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
> + rkisp1_iowrite32(params_vdev, arg->mode, CIF_ISP_GAMMA_OUT_MODE);
> +
> + for (i = 0; i < CIFISP_GAMMA_OUT_MAX_SAMPLES; i++)
> + rkisp1_iowrite32(params_vdev, arg->gamma_y[i],
> + CIF_ISP_GAMMA_OUT_Y_0 + i * 4);
> +}
> +
> +/* ISP Cross Talk */
> +static void ctk_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_ctk_config *arg)
> +{
> + rkisp1_iowrite32(params_vdev, arg->coeff0, CIF_ISP_CT_COEFF_0);
> + rkisp1_iowrite32(params_vdev, arg->coeff1, CIF_ISP_CT_COEFF_1);
> + rkisp1_iowrite32(params_vdev, arg->coeff2, CIF_ISP_CT_COEFF_2);
> + rkisp1_iowrite32(params_vdev, arg->coeff3, CIF_ISP_CT_COEFF_3);
> + rkisp1_iowrite32(params_vdev, arg->coeff4, CIF_ISP_CT_COEFF_4);
> + rkisp1_iowrite32(params_vdev, arg->coeff5, CIF_ISP_CT_COEFF_5);
> + rkisp1_iowrite32(params_vdev, arg->coeff6, CIF_ISP_CT_COEFF_6);
> + rkisp1_iowrite32(params_vdev, arg->coeff7, CIF_ISP_CT_COEFF_7);
> + rkisp1_iowrite32(params_vdev, arg->coeff8, CIF_ISP_CT_COEFF_8);
> + rkisp1_iowrite32(params_vdev, arg->ct_offset_r, CIF_ISP_CT_OFFSET_R);
> + rkisp1_iowrite32(params_vdev, arg->ct_offset_g, CIF_ISP_CT_OFFSET_G);
> + rkisp1_iowrite32(params_vdev, arg->ct_offset_b, CIF_ISP_CT_OFFSET_B);
> +}
> +
> +static void ctk_enable(struct rkisp1_isp_params_vdev *params_vdev, bool en)
> +{
> + if (en)
> + return;
> +
> + /* Write back the default values. */
> + rkisp1_iowrite32(params_vdev, 0x80, CIF_ISP_CT_COEFF_0);
> + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_COEFF_1);
> + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_COEFF_2);
> + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_COEFF_3);
> + rkisp1_iowrite32(params_vdev, 0x80, CIF_ISP_CT_COEFF_4);
> + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_COEFF_5);
> + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_COEFF_6);
> + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_COEFF_7);
> + rkisp1_iowrite32(params_vdev, 0x80, CIF_ISP_CT_COEFF_8);
> +
> + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_OFFSET_R);
> + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_OFFSET_G);
> + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_OFFSET_B);
> +}
> +
> +/* ISP White Balance Mode */
> +static void awb_meas_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_awb_meas_config *arg)
> +{
> + /* based on the mode,configure the awb module */
> + if (arg->awb_mode == CIFISP_AWB_MODE_YCBCR) {
> + /* Reference Cb and Cr */
> + rkisp1_iowrite32(params_vdev,
> + CIF_ISP_AWB_REF_CR_SET(arg->awb_ref_cr) |
> + arg->awb_ref_cb, CIF_ISP_AWB_REF);
> + /* Yc Threshold */
> + rkisp1_iowrite32(params_vdev,
> + CIF_ISP_AWB_MAX_Y_SET(arg->max_y) |
> + CIF_ISP_AWB_MIN_Y_SET(arg->min_y) |
> + CIF_ISP_AWB_MAX_CS_SET(arg->max_csum) |
> + arg->min_c, CIF_ISP_AWB_THRESH);
> + }
> +
> + /* window offset */
> + rkisp1_iowrite32(params_vdev,
> + arg->awb_wnd.v_offs, CIF_ISP_AWB_WND_V_OFFS);
> + rkisp1_iowrite32(params_vdev,
> + arg->awb_wnd.h_offs, CIF_ISP_AWB_WND_H_OFFS);
> + /* AWB window size */
> + rkisp1_iowrite32(params_vdev,
> + arg->awb_wnd.v_size, CIF_ISP_AWB_WND_V_SIZE);
> + rkisp1_iowrite32(params_vdev,
> + arg->awb_wnd.h_size, CIF_ISP_AWB_WND_H_SIZE);
> + /* Number of frames */
> + rkisp1_iowrite32(params_vdev,
> + arg->frames, CIF_ISP_AWB_FRAMES);
> +}
> +
> +static void awb_meas_enable(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_awb_meas_config *arg, bool en)
> +{
> + u32 reg_val = rkisp1_ioread32(params_vdev, CIF_ISP_AWB_PROP);
> +
> + /* switch off */
> + reg_val &= CIF_ISP_AWB_MODE_MASK_NONE;
> +
> + if (en) {
> + if (arg->awb_mode == CIFISP_AWB_MODE_RGB)
> + reg_val |= CIF_ISP_AWB_MODE_RGB_EN;
> + else
> + reg_val |= CIF_ISP_AWB_MODE_YCBCR_EN;
> +
> + rkisp1_iowrite32(params_vdev, reg_val, CIF_ISP_AWB_PROP);
> +
> + /* Measurements require AWB block be active. */
> + /* TODO: need to enable here ? awb_gain_enable has done this */
> + isp_param_set_bits(params_vdev, CIF_ISP_CTRL,
> + CIF_ISP_CTRL_ISP_AWB_ENA);
> + } else {
> + rkisp1_iowrite32(params_vdev,
> + reg_val, CIF_ISP_AWB_PROP);
> + isp_param_clear_bits(params_vdev, CIF_ISP_CTRL,
> + CIF_ISP_CTRL_ISP_AWB_ENA);
> + }
> +}
> +
> +static void awb_gain_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_awb_gain_config *arg)
> +{
> + rkisp1_iowrite32(params_vdev,
> + CIF_ISP_AWB_GAIN_R_SET(arg->gain_green_r) |
> + arg->gain_green_b, CIF_ISP_AWB_GAIN_G);
> +
> + rkisp1_iowrite32(params_vdev, CIF_ISP_AWB_GAIN_R_SET(arg->gain_red) |
> + arg->gain_blue, CIF_ISP_AWB_GAIN_RB);
> +}
> +
> +static void aec_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_aec_config *arg)
> +{
> + unsigned int block_hsize, block_vsize;
> +
> + rkisp1_iowrite32(params_vdev,
> + ((arg->autostop) ? CIF_ISP_EXP_CTRL_AUTOSTOP : 0) |
> + ((arg->mode == CIFISP_EXP_MEASURING_MODE_1) ?
> + CIF_ISP_EXP_CTRL_MEASMODE_1 : 0), CIF_ISP_EXP_CTRL);
> +
> + rkisp1_iowrite32(params_vdev,
> + arg->meas_window.h_offs, CIF_ISP_EXP_H_OFFSET);
> + rkisp1_iowrite32(params_vdev,
> + arg->meas_window.v_offs, CIF_ISP_EXP_V_OFFSET);
> +
> + block_hsize = arg->meas_window.h_size / CIF_ISP_EXP_COLUMN_NUM - 1;
> + block_vsize = arg->meas_window.v_size / CIF_ISP_EXP_ROW_NUM - 1;
> +
> + rkisp1_iowrite32(params_vdev, CIF_ISP_EXP_H_SIZE_SET(block_hsize),
> + CIF_ISP_EXP_H_SIZE);
> + rkisp1_iowrite32(params_vdev, CIF_ISP_EXP_V_SIZE_SET(block_vsize),
> + CIF_ISP_EXP_V_SIZE);
> +}
> +
> +static void cproc_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_cproc_config *arg)
> +{
> + /* TODO: get quantization, ie effect*/
> + u32 quantization = V4L2_QUANTIZATION_FULL_RANGE;
> + u32 effect = V4L2_COLORFX_NONE;
> +
> + rkisp1_iowrite32(params_vdev, arg->contrast, CIF_C_PROC_CONTRAST);
> + rkisp1_iowrite32(params_vdev, arg->hue, CIF_C_PROC_HUE);
> + rkisp1_iowrite32(params_vdev, arg->sat, CIF_C_PROC_SATURATION);
> + rkisp1_iowrite32(params_vdev, arg->brightness, CIF_C_PROC_BRIGHTNESS);
> +
> + if (quantization != V4L2_QUANTIZATION_FULL_RANGE ||
> + effect != V4L2_COLORFX_NONE) {
> + isp_param_clear_bits(params_vdev, CIF_C_PROC_CTRL,
> + CIF_C_PROC_YOUT_FULL |
> + CIF_C_PROC_YIN_FULL |
> + CIF_C_PROC_COUT_FULL);
> + } else {
> + isp_param_set_bits(params_vdev, CIF_C_PROC_CTRL,
> + CIF_C_PROC_YOUT_FULL |
> + CIF_C_PROC_YIN_FULL |
> + CIF_C_PROC_COUT_FULL);
> + }
> +}
> +
> +static void hst_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_hst_config *arg)
> +{
> + unsigned int block_hsize, block_vsize;
> + static const u32 hist_weight_regs[] = {
> + CIF_ISP_HIST_WEIGHT_00TO30, CIF_ISP_HIST_WEIGHT_40TO21,
> + CIF_ISP_HIST_WEIGHT_31TO12, CIF_ISP_HIST_WEIGHT_22TO03,
> + CIF_ISP_HIST_WEIGHT_13TO43, CIF_ISP_HIST_WEIGHT_04TO34,
> + CIF_ISP_HIST_WEIGHT_44,
> + };
> + const u8 *weight;
> + int i;
> +
> + rkisp1_iowrite32(params_vdev,
> + CIF_ISP_HIST_PREDIV_SET(arg->histogram_predivider),
> + CIF_ISP_HIST_PROP);
> + rkisp1_iowrite32(params_vdev,
> + arg->meas_window.h_offs,
> + CIF_ISP_HIST_H_OFFS);
> + rkisp1_iowrite32(params_vdev,
> + arg->meas_window.v_offs,
> + CIF_ISP_HIST_V_OFFS);
> +
> + block_hsize = arg->meas_window.h_size / CIF_ISP_HIST_COLUMN_NUM - 1;
> + block_vsize = arg->meas_window.v_size / CIF_ISP_HIST_ROW_NUM - 1;
> +
> + rkisp1_iowrite32(params_vdev, block_hsize, CIF_ISP_HIST_H_SIZE);
> + rkisp1_iowrite32(params_vdev, block_vsize, CIF_ISP_HIST_V_SIZE);
> +
> + weight = arg->hist_weight;
> + for (i = 0; i < ARRAY_SIZE(hist_weight_regs); ++i, weight += 4)
> + rkisp1_iowrite32(params_vdev, CIF_ISP_HIST_WEIGHT_SET(
> + weight[0], weight[1], weight[2], weight[3]),
> + hist_weight_regs[i]);
> +}
> +
> +static void hst_enable(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_hst_config *arg, bool en)
> +{
> + if (en) {
> + u32 hist_prop = rkisp1_ioread32(params_vdev, CIF_ISP_HIST_PROP);
> +
> + hist_prop &= ~CIF_ISP_HIST_PROP_MODE_MASK | arg->mode;
> + isp_param_set_bits(params_vdev, CIF_ISP_HIST_PROP, hist_prop);
> + } else {
> + isp_param_clear_bits(params_vdev, CIF_ISP_HIST_PROP,
> + CIF_ISP_HIST_PROP_MODE_MASK);
> + }
> +}
> +
> +static inline unsigned int afm_calc_luminanceshift(const unsigned int
> + maxpixelcnt)
> +{
> + unsigned int lgrad = maxpixelcnt;
> + unsigned int lshift = 0U;
> +
> + while (lgrad > 65793) {
> + ++lshift;
> + lgrad >>= 1;
> + }
> +
> + return lshift;
> +}
> +
> +static inline unsigned int afm_calc_tennenggradshift(const unsigned int
> + maxpixelcnt)
> +{
> + unsigned int tgrad = maxpixelcnt;
> + unsigned int tshift = 0U;
> +
> + while (tgrad > (128 * 128)) {
> + ++tshift;
> + tgrad >>= 1;
> + }
> +
> + return tshift;
> +}
> +
> +static void afm_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_afc_config *arg)
> +{
> + size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->afm_win), arg->num_afm_win);
> + int i;
> +
> + /* Switch off to configure. Enabled during normal flow in frame isr. */
> + isp_param_clear_bits(params_vdev, CIF_ISP_AFM_CTRL, CIF_ISP_AFM_ENA);
> +
> + for (i = 0; i < num_of_win; i++) {
> + rkisp1_iowrite32(params_vdev,
> + CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_offs) |
> + CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_offs),
> + CIF_ISP_AFM_LT_A + i * 8);
> + rkisp1_iowrite32(params_vdev,
> + CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_size +
> + arg->afm_win[i].h_offs) |
> + CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_size +
> + arg->afm_win[i].v_offs),
> + CIF_ISP_AFM_RB_A + i * 8);
> + }
> + rkisp1_iowrite32(params_vdev, arg->thres, CIF_ISP_AFM_THRES);
> + rkisp1_iowrite32(params_vdev, arg->var_shift, CIF_ISP_AFM_VAR_SHIFT);
> +}
> +
> +static void ie_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_ie_config *arg)
> +{
> + u32 eff_ctrl;
> +
> + eff_ctrl = rkisp1_ioread32(params_vdev, CIF_IMG_EFF_CTRL);
> + eff_ctrl &= ~CIF_IMG_EFF_CTRL_MODE_MASK;
> +
> + switch (arg->effect) {
> + case V4L2_COLORFX_SEPIA:
> + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA;
> + break;
> + case V4L2_COLORFX_SET_CBCR:
> + rkisp1_iowrite32(params_vdev, arg->eff_tint, CIF_IMG_EFF_TINT);
> + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA;
> + break;
> + /*
> + * Color selection is similar to water color(AQUA):
> + * grayscale + selected color w threshold
> + */
> + case V4L2_COLORFX_AQUA:
> + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_COLOR_SEL;
> + rkisp1_iowrite32(params_vdev, arg->color_sel,
> + CIF_IMG_EFF_COLOR_SEL);
> + break;
> + case V4L2_COLORFX_EMBOSS:
> + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_EMBOSS;
> + rkisp1_iowrite32(params_vdev, arg->eff_mat_1,
> + CIF_IMG_EFF_MAT_1);
> + rkisp1_iowrite32(params_vdev, arg->eff_mat_2,
> + CIF_IMG_EFF_MAT_2);
> + rkisp1_iowrite32(params_vdev, arg->eff_mat_3,
> + CIF_IMG_EFF_MAT_3);
> + break;
> + case V4L2_COLORFX_SKETCH:
> + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SKETCH;
> + rkisp1_iowrite32(params_vdev, arg->eff_mat_3,
> + CIF_IMG_EFF_MAT_3);
> + rkisp1_iowrite32(params_vdev, arg->eff_mat_4,
> + CIF_IMG_EFF_MAT_4);
> + rkisp1_iowrite32(params_vdev, arg->eff_mat_5,
> + CIF_IMG_EFF_MAT_5);
> + break;
> + case V4L2_COLORFX_BW:
> + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_BLACKWHITE;
> + break;
> + case V4L2_COLORFX_NEGATIVE:
> + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_NEGATIVE;
> + break;
> + default:
> + break;
> + }
> +
> + rkisp1_iowrite32(params_vdev, eff_ctrl, CIF_IMG_EFF_CTRL);
> +}
> +
> +static void ie_enable(struct rkisp1_isp_params_vdev *params_vdev, bool en)
> +{
> + if (en) {
> + isp_param_set_bits(params_vdev, CIF_ICCL, CIF_ICCL_IE_CLK);
> + rkisp1_iowrite32(params_vdev, CIF_IMG_EFF_CTRL_ENABLE,
> + CIF_IMG_EFF_CTRL);
> + isp_param_set_bits(params_vdev, CIF_IMG_EFF_CTRL,
> + CIF_IMG_EFF_CTRL_CFG_UPD);
> + } else {
> + /* Disable measurement */
> + isp_param_clear_bits(params_vdev, CIF_IMG_EFF_CTRL,
> + CIF_IMG_EFF_CTRL_ENABLE);
> + isp_param_clear_bits(params_vdev, CIF_ICCL, CIF_ICCL_IE_CLK);
> + }
> +}
> +
> +static void csm_config(struct rkisp1_isp_params_vdev *params_vdev,
> + bool full_range)
> +{
> + static const u16 full_range_coeff[] = {
> + 0x0026, 0x004b, 0x000f,
> + 0x01ea, 0x01d6, 0x0040,
> + 0x0040, 0x01ca, 0x01f6
> + };
> + static const u16 limited_range_coeff[] = {
> + 0x0021, 0x0040, 0x000d,
> + 0x01ed, 0x01db, 0x0038,
> + 0x0038, 0x01d1, 0x01f7,
> + };
> + int i;
> +
> + if (full_range) {
> + for (i = 0; i < ARRAY_SIZE(full_range_coeff); i++)
> + rkisp1_iowrite32(params_vdev, full_range_coeff[i],
> + CIF_ISP_CC_COEFF_0 + i * 4);
> +
> + isp_param_set_bits(params_vdev, CIF_ISP_CTRL,
> + CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA |
> + CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA);
> + } else {
> + for (i = 0; i < ARRAY_SIZE(limited_range_coeff); i++)
> + rkisp1_iowrite32(params_vdev, limited_range_coeff[i],
> + CIF_ISP_CC_COEFF_0 + i * 4);
> +
> + isp_param_clear_bits(params_vdev, CIF_ISP_CTRL,
> + CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA |
> + CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA);
> + }
> +}
> +
> +/* ISP De-noise Pre-Filter(DPF) function */
> +static void dpf_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_dpf_config *arg)
> +{
> + unsigned int isp_dpf_mode;
> + unsigned int spatial_coeff;
> + unsigned int i;
> +
> + switch (arg->gain.mode) {
> + case CIFISP_DPF_GAIN_USAGE_NF_GAINS:
> + isp_dpf_mode = CIF_ISP_DPF_MODE_USE_NF_GAIN |
> + CIF_ISP_DPF_MODE_AWB_GAIN_COMP;
> + break;
> + case CIFISP_DPF_GAIN_USAGE_LSC_GAINS:
> + isp_dpf_mode = CIF_ISP_DPF_MODE_LSC_GAIN_COMP;
> + break;
> + case CIFISP_DPF_GAIN_USAGE_NF_LSC_GAINS:
> + isp_dpf_mode = CIF_ISP_DPF_MODE_USE_NF_GAIN |
> + CIF_ISP_DPF_MODE_AWB_GAIN_COMP |
> + CIF_ISP_DPF_MODE_LSC_GAIN_COMP;
> + break;
> + case CIFISP_DPF_GAIN_USAGE_AWB_GAINS:
> + isp_dpf_mode = CIF_ISP_DPF_MODE_AWB_GAIN_COMP;
> + break;
> + case CIFISP_DPF_GAIN_USAGE_AWB_LSC_GAINS:
> + isp_dpf_mode = CIF_ISP_DPF_MODE_LSC_GAIN_COMP |
> + CIF_ISP_DPF_MODE_AWB_GAIN_COMP;
> + break;
> + case CIFISP_DPF_GAIN_USAGE_DISABLED:
> + default:
> + isp_dpf_mode = 0;
> + break;
> + }
> +
> + if (arg->nll.scale_mode == CIFISP_NLL_SCALE_LOGARITHMIC)
> + isp_dpf_mode |= CIF_ISP_DPF_MODE_NLL_SEGMENTATION;
> + if (arg->rb_flt.fltsize == CIFISP_DPF_RB_FILTERSIZE_9x9)
> + isp_dpf_mode |= CIF_ISP_DPF_MODE_RB_FLTSIZE_9x9;
> + if (!arg->rb_flt.r_enable)
> + isp_dpf_mode |= CIF_ISP_DPF_MODE_R_FLT_DIS;
> + if (!arg->rb_flt.b_enable)
> + isp_dpf_mode |= CIF_ISP_DPF_MODE_B_FLT_DIS;
> + if (!arg->g_flt.gb_enable)
> + isp_dpf_mode |= CIF_ISP_DPF_MODE_GB_FLT_DIS;
> + if (!arg->g_flt.gr_enable)
> + isp_dpf_mode |= CIF_ISP_DPF_MODE_GR_FLT_DIS;
> +
> + isp_param_set_bits(params_vdev, CIF_ISP_DPF_MODE, isp_dpf_mode);
> + rkisp1_iowrite32(params_vdev, arg->gain.nf_b_gain,
> + CIF_ISP_DPF_NF_GAIN_B);
> + rkisp1_iowrite32(params_vdev, arg->gain.nf_r_gain,
> + CIF_ISP_DPF_NF_GAIN_R);
> + rkisp1_iowrite32(params_vdev, arg->gain.nf_gb_gain,
> + CIF_ISP_DPF_NF_GAIN_GB);
> + rkisp1_iowrite32(params_vdev, arg->gain.nf_gr_gain,
> + CIF_ISP_DPF_NF_GAIN_GR);
> +
> + for (i = 0; i < CIFISP_DPF_MAX_NLF_COEFFS; i++) {
> + rkisp1_iowrite32(params_vdev, arg->nll.coeff[i],
> + CIF_ISP_DPF_NULL_COEFF_0 + i * 4);
> + }
> +
> + spatial_coeff = arg->g_flt.spatial_coeff[0] |
> + (arg->g_flt.spatial_coeff[1] << 8) |
> + (arg->g_flt.spatial_coeff[2] << 16) |
> + (arg->g_flt.spatial_coeff[3] << 24);
> + rkisp1_iowrite32(params_vdev, spatial_coeff,
> + CIF_ISP_DPF_S_WEIGHT_G_1_4);
> +
> + spatial_coeff = arg->g_flt.spatial_coeff[4] |
> + (arg->g_flt.spatial_coeff[5] << 8);
> + rkisp1_iowrite32(params_vdev, spatial_coeff,
> + CIF_ISP_DPF_S_WEIGHT_G_5_6);
> +
> + spatial_coeff = arg->rb_flt.spatial_coeff[0] |
> + (arg->rb_flt.spatial_coeff[1] << 8) |
> + (arg->rb_flt.spatial_coeff[2] << 16) |
> + (arg->rb_flt.spatial_coeff[3] << 24);
> + rkisp1_iowrite32(params_vdev, spatial_coeff,
> + CIF_ISP_DPF_S_WEIGHT_RB_1_4);
> +
> + spatial_coeff = arg->rb_flt.spatial_coeff[4] |
> + (arg->rb_flt.spatial_coeff[5] << 8);
> + rkisp1_iowrite32(params_vdev, spatial_coeff,
> + CIF_ISP_DPF_S_WEIGHT_RB_5_6);
> +}
> +
> +static void dpf_strength_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct cifisp_dpf_strength_config *arg)
> +{
> + rkisp1_iowrite32(params_vdev, arg->b, CIF_ISP_DPF_STRENGTH_B);
> + rkisp1_iowrite32(params_vdev, arg->g, CIF_ISP_DPF_STRENGTH_G);
> + rkisp1_iowrite32(params_vdev, arg->r, CIF_ISP_DPF_STRENGTH_R);
> +}
> +
> +static __maybe_unused
> +void __isp_isr_other_config(struct rkisp1_isp_params_vdev *params_vdev,
> + const struct rkisp1_isp_params_cfg *new_params)
> +{
> + unsigned int module_en_update, module_cfg_update, module_ens;
> +
> + module_en_update = new_params->module_en_update;
> + module_cfg_update = new_params->module_cfg_update;
> + module_ens = new_params->module_ens;
> +
> + if ((module_en_update & CIFISP_MODULE_DPCC) ||
> + (module_cfg_update & CIFISP_MODULE_DPCC)) {
> + /*update dpc config */
> + if ((module_cfg_update & CIFISP_MODULE_DPCC))
> + dpcc_config(params_vdev,
> + &new_params->others.dpcc_config);
> +
> + if (module_en_update & CIFISP_MODULE_DPCC) {
> + if (!!(module_ens & CIFISP_MODULE_DPCC))
> + isp_param_set_bits(params_vdev,
> + CIF_ISP_DPCC_MODE,
> + CIF_ISP_DPCC_ENA);
> + else
> + isp_param_clear_bits(params_vdev,
> + CIF_ISP_DPCC_MODE,
> + CIF_ISP_DPCC_ENA);
> + }
> + }
> +
> + if ((module_en_update & CIFISP_MODULE_BLS) ||
> + (module_cfg_update & CIFISP_MODULE_BLS)) {
> + /* update bls config */
> + if ((module_cfg_update & CIFISP_MODULE_BLS))
> + bls_config(params_vdev, &new_params->others.bls_config);
> +
> + if (module_en_update & CIFISP_MODULE_BLS) {
> + if (!!(module_ens & CIFISP_MODULE_BLS))
> + isp_param_set_bits(params_vdev,
> + CIF_ISP_BLS_CTRL,
> + CIF_ISP_BLS_ENA);
> + else
> + isp_param_clear_bits(params_vdev,
> + CIF_ISP_BLS_CTRL,
> + CIF_ISP_BLS_ENA);
> + }
> + }
> +
> + if ((module_en_update & CIFISP_MODULE_SDG) ||
> + (module_cfg_update & CIFISP_MODULE_SDG)) {
> + /* update sdg config */
> + if ((module_cfg_update & CIFISP_MODULE_SDG))
> + sdg_config(params_vdev, &new_params->others.sdg_config);
> +
> + if (module_en_update & CIFISP_MODULE_SDG) {
> + if (!!(module_ens & CIFISP_MODULE_SDG))
> + isp_param_set_bits(params_vdev,
> + CIF_ISP_CTRL,
> + CIF_ISP_CTRL_ISP_GAMMA_IN_ENA);
> + else
> + isp_param_clear_bits(params_vdev,
> + CIF_ISP_CTRL,
> + CIF_ISP_CTRL_ISP_GAMMA_IN_ENA);
> + }
> + }
> +
> + if ((module_en_update & CIFISP_MODULE_LSC) ||
> + (module_cfg_update & CIFISP_MODULE_LSC)) {
> + /* update lsc config */
> + if ((module_cfg_update & CIFISP_MODULE_LSC))
> + lsc_config(params_vdev, &new_params->others.lsc_config);
> +
> + if (module_en_update & CIFISP_MODULE_LSC) {
> + if (!!(module_ens & CIFISP_MODULE_LSC))
> + isp_param_set_bits(params_vdev,
> + CIF_ISP_LSC_CTRL,
> + CIF_ISP_LSC_CTRL_ENA);
> + else
> + isp_param_clear_bits(params_vdev,
> + CIF_ISP_LSC_CTRL,
> + CIF_ISP_LSC_CTRL_ENA);
> + }
> + }
> +
> + if ((module_en_update & CIFISP_MODULE_AWB_GAIN) ||
> + (module_cfg_update & CIFISP_MODULE_AWB_GAIN)) {
> + /* update awb gains */
> + if ((module_cfg_update & CIFISP_MODULE_AWB_GAIN))
> + awb_gain_config(params_vdev,
> + &new_params->others.awb_gain_config);
> +
> + if (module_en_update & CIFISP_MODULE_AWB_GAIN) {
> + if (!!(module_ens & CIFISP_MODULE_AWB_GAIN))
> + isp_param_set_bits(params_vdev,
> + CIF_ISP_CTRL,
> + CIF_ISP_CTRL_ISP_AWB_ENA);
> + else
> + isp_param_clear_bits(params_vdev,
> + CIF_ISP_CTRL,
> + CIF_ISP_CTRL_ISP_AWB_ENA);
> + }
> + }
> +
> + if ((module_en_update & CIFISP_MODULE_BDM) ||
> + (module_cfg_update & CIFISP_MODULE_BDM)) {
> + /* update bdm config */
> + if ((module_cfg_update & CIFISP_MODULE_BDM))
> + bdm_config(params_vdev, &new_params->others.bdm_config);
> +
> + if (module_en_update & CIFISP_MODULE_BDM) {
> + if (!!(module_ens & CIFISP_MODULE_BDM))
> + isp_param_set_bits(params_vdev,
> + CIF_ISP_DEMOSAIC,
> + CIF_ISP_DEMOSAIC_BYPASS);
> + else
> + isp_param_clear_bits(params_vdev,
> + CIF_ISP_DEMOSAIC,
> + CIF_ISP_DEMOSAIC_BYPASS);
> + }
> + }
> +
> + if ((module_en_update & CIFISP_MODULE_FLT) ||
> + (module_cfg_update & CIFISP_MODULE_FLT)) {
> + /* update filter config */
> + if ((module_cfg_update & CIFISP_MODULE_FLT))
> + flt_config(params_vdev, &new_params->others.flt_config);
> +
> + if (module_en_update & CIFISP_MODULE_FLT) {
> + if (!!(module_ens & CIFISP_MODULE_FLT))
> + isp_param_set_bits(params_vdev,
> + CIF_ISP_FILT_MODE,
> + CIF_ISP_FLT_ENA);
> + else
> + isp_param_clear_bits(params_vdev,
> + CIF_ISP_FILT_MODE,
> + CIF_ISP_FLT_ENA);
> + }
> + }
> +
> + if ((module_en_update & CIFISP_MODULE_CTK) ||
> + (module_cfg_update & CIFISP_MODULE_CTK)) {
> + /* update ctk config */
> + if ((module_cfg_update & CIFISP_MODULE_CTK))
> + ctk_config(params_vdev, &new_params->others.ctk_config);
> +
> + if (module_en_update & CIFISP_MODULE_CTK)
> + ctk_enable(params_vdev,
> + !!(module_ens & CIFISP_MODULE_CTK));
> + }
> +
> + if ((module_en_update & CIFISP_MODULE_GOC) ||
> + (module_cfg_update & CIFISP_MODULE_GOC)) {
> + /* update goc config */
> + if ((module_cfg_update & CIFISP_MODULE_CTK))
> + goc_config(params_vdev, &new_params->others.goc_config);
> +
> + if (module_en_update & CIFISP_MODULE_GOC) {
> + if (!!(module_ens & CIFISP_MODULE_GOC))
> + isp_param_set_bits(params_vdev,
> + CIF_ISP_CTRL,
> + CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
> + else
> + isp_param_clear_bits(params_vdev,
> + CIF_ISP_CTRL,
> + CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
> + }
> + }
> +
> + if ((module_en_update & CIFISP_MODULE_CPROC) ||
> + (module_cfg_update & CIFISP_MODULE_CPROC)) {
> + /* update cprc config */
> + if ((module_cfg_update & CIFISP_MODULE_CPROC)) {
> + cproc_config(params_vdev,
> + &new_params->others.cproc_config);
> + /* TODO: get range */
> + csm_config(params_vdev, true);
> + }
> +
> + if (module_en_update & CIFISP_MODULE_CPROC) {
> + if (!!(module_ens & CIFISP_MODULE_CPROC))
> + isp_param_set_bits(params_vdev,
> + CIF_C_PROC_CTRL,
> + CIF_C_PROC_CTR_ENABLE);
> + else
> + isp_param_clear_bits(params_vdev,
> + CIF_C_PROC_CTRL,
> + CIF_C_PROC_CTR_ENABLE);
> + }
> + }
> +
> + if ((module_en_update & CIFISP_MODULE_IE) ||
> + (module_cfg_update & CIFISP_MODULE_IE)) {
> + /* update ie config */
> + if ((module_cfg_update & CIFISP_MODULE_IE))
> + ie_config(params_vdev, &new_params->others.ie_config);
> +
> + if (module_en_update & CIFISP_MODULE_IE)
> + ie_enable(params_vdev,
> + !!(module_ens & CIFISP_MODULE_IE));
> + }
> +
> + if ((module_en_update & CIFISP_MODULE_DPF) ||
> + (module_cfg_update & CIFISP_MODULE_DPF)) {
> + /* update dpf config */
> + if ((module_cfg_update & CIFISP_MODULE_DPF))
> + dpf_config(params_vdev, &new_params->others.dpf_config);
> +
> + if (module_en_update & CIFISP_MODULE_DPF) {
> + if (!!(module_ens & CIFISP_MODULE_DPF))
> + isp_param_set_bits(params_vdev,
> + CIF_ISP_DPF_MODE,
> + CIF_ISP_DPF_MODE_EN);
> + else
> + isp_param_clear_bits(params_vdev,
> + CIF_ISP_DPF_MODE,
> + CIF_ISP_DPF_MODE_EN);
> + }
> + }
> +
> + if ((module_en_update & CIFISP_MODULE_DPF_STRENGTH) ||
> + (module_cfg_update & CIFISP_MODULE_DPF_STRENGTH)) {
> + /* update dpf strength config */
> + dpf_strength_config(params_vdev,
> + &new_params->others.dpf_strength_config);
> + }
> +}
> +
> +static __maybe_unused
> +void __isp_isr_meas_config(struct rkisp1_isp_params_vdev *params_vdev,
> + struct rkisp1_isp_params_cfg *new_params)
> +{
> + unsigned int module_en_update, module_cfg_update, module_ens;
> +
> + module_en_update = new_params->module_en_update;
> + module_cfg_update = new_params->module_cfg_update;
> + module_ens = new_params->module_ens;
> +
> + if ((module_en_update & CIFISP_MODULE_AWB) ||
> + (module_cfg_update & CIFISP_MODULE_AWB)) {
> + /* update awb config */
> + if ((module_cfg_update & CIFISP_MODULE_AWB))
> + awb_meas_config(params_vdev,
> + &new_params->meas.awb_meas_config);
> +
> + if (module_en_update & CIFISP_MODULE_AWB)
> + awb_meas_enable(params_vdev,
> + &new_params->meas.awb_meas_config,
> + !!(module_ens & CIFISP_MODULE_AWB));
> + }
> +
> + if ((module_en_update & CIFISP_MODULE_AFC) ||
> + (module_cfg_update & CIFISP_MODULE_AFC)) {
> + /* update afc config */
> + if ((module_cfg_update & CIFISP_MODULE_AFC))
> + afm_config(params_vdev, &new_params->meas.afc_config);
> +
> + if (module_en_update & CIFISP_MODULE_AFC) {
> + if (!!(module_ens & CIFISP_MODULE_AFC))
> + isp_param_set_bits(params_vdev,
> + CIF_ISP_AFM_CTRL,
> + CIF_ISP_AFM_ENA);
> + else
> + isp_param_clear_bits(params_vdev,
> + CIF_ISP_AFM_CTRL,
> + CIF_ISP_AFM_ENA);
> + }
> + }
> +
> + if ((module_en_update & CIFISP_MODULE_HST) ||
> + (module_cfg_update & CIFISP_MODULE_HST)) {
> + /* update hst config */
> + if ((module_cfg_update & CIFISP_MODULE_HST))
> + hst_config(params_vdev, &new_params->meas.hst_config);
> +
> + if (module_en_update & CIFISP_MODULE_HST)
> + hst_enable(params_vdev,
> + &new_params->meas.hst_config,
> + !!(module_ens & CIFISP_MODULE_HST));
> + }
> +
> + if ((module_en_update & CIFISP_MODULE_AEC) ||
> + (module_cfg_update & CIFISP_MODULE_AEC)) {
> + /* update aec config */
> + if ((module_cfg_update & CIFISP_MODULE_AEC))
> + aec_config(params_vdev, &new_params->meas.aec_config);
> +
> + if (module_en_update & CIFISP_MODULE_AEC) {
> + if (!!(module_ens & CIFISP_MODULE_AEC))
> + isp_param_set_bits(params_vdev,
> + CIF_ISP_EXP_CTRL,
> + CIF_ISP_EXP_ENA);
> + else
> + isp_param_clear_bits(params_vdev,
> + CIF_ISP_EXP_CTRL,
> + CIF_ISP_EXP_ENA);
> + }
> + }
> +}
> +
> +void rkisp1_params_isr(struct rkisp1_isp_params_vdev *params_vdev, u32 isp_mis)
> +{
> + struct rkisp1_isp_params_cfg *new_params;
> + struct rkisp1_buffer *cur_buf = NULL;
> +
> + spin_lock(¶ms_vdev->config_lock);
> + if (!params_vdev->streamon) {
> + spin_unlock(¶ms_vdev->config_lock);
> + return;
> + }
> +
> + /* get one empty buffer */
> + if (!list_empty(¶ms_vdev->params))
> + cur_buf = list_first_entry(¶ms_vdev->params,
> + struct rkisp1_buffer, queue);
> + spin_unlock(¶ms_vdev->config_lock);
> +
> + if (!cur_buf)
> + return;
> +
> + new_params = (struct rkisp1_isp_params_cfg *)(cur_buf->vaddr[0]);
> +
> + if (isp_mis & CIF_ISP_FRAME) {
> + /* __isp_isr_other_config(params_vdev, new_params); */
> + /* __isp_isr_meas_config(params_vdev, new_params); */
> + spin_lock(¶ms_vdev->config_lock);
> + list_del(&cur_buf->queue);
> + spin_unlock(¶ms_vdev->config_lock);
> + vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
> + }
> +}
> +
> +static const struct cifisp_awb_meas_config awb_params_default_config = {
> + {
> + 0, 0, RKISP1_DEFAULT_WIDTH, RKISP1_DEFAULT_HEIGHT
> + },
> + CIFISP_AWB_MODE_YCBCR, 200, 30, 20, 20, 0, 128, 128
> +};
> +
> +static const struct cifisp_aec_config aec_params_default_config = {
> + CIFISP_EXP_MEASURING_MODE_0,
> + CIFISP_EXP_CTRL_AUTOSTOP_0,
> + {
> + RKISP1_DEFAULT_WIDTH >> 2, RKISP1_DEFAULT_HEIGHT >> 2,
> + RKISP1_DEFAULT_WIDTH >> 1, RKISP1_DEFAULT_HEIGHT >> 1
> + }
> +};
> +
> +static const struct cifisp_hst_config hst_params_default_config = {
> + CIFISP_HISTOGRAM_MODE_RGB_COMBINED,
> + 3,
> + {
> + RKISP1_DEFAULT_WIDTH >> 2, RKISP1_DEFAULT_HEIGHT >> 2,
> + RKISP1_DEFAULT_WIDTH >> 1, RKISP1_DEFAULT_HEIGHT >> 1
> + },
> + {
> + 0, /* To be filled in with 0x01 at runtime. */
> + }
> +};
> +
> +static const struct cifisp_afc_config afc_params_default_config = {
> + 1,
> + {
> + {
> + 300, 225, 200, 150
> + }
> + },
> + 4,
> + 14
> +};
> +
> +static
> +void rkisp1_params_config_parameter(struct rkisp1_isp_params_vdev *params_vdev)
> +{
> + struct cifisp_hst_config hst = hst_params_default_config;
> +
> + spin_lock(¶ms_vdev->config_lock);
> +
> + awb_meas_config(params_vdev, &awb_params_default_config);
> + awb_meas_enable(params_vdev, &awb_params_default_config, true);
> +
> + aec_config(params_vdev, &aec_params_default_config);
> + isp_param_set_bits(params_vdev, CIF_ISP_EXP_CTRL, CIF_ISP_EXP_ENA);
> +
> + afm_config(params_vdev, &afc_params_default_config);
> + isp_param_set_bits(params_vdev, CIF_ISP_AFM_CTRL, CIF_ISP_AFM_ENA);
> +
> + memset(hst.hist_weight, 0x01, sizeof(hst.hist_weight));
> + hst_config(params_vdev, &hst);
> + isp_param_set_bits(params_vdev, CIF_ISP_HIST_PROP,
> + ~CIF_ISP_HIST_PROP_MODE_MASK |
> + hst_params_default_config.mode);
> +
> + spin_unlock(¶ms_vdev->config_lock);
> +}
> +
> +/* Not called when the camera active, thus not isr protection. */
> +void rkisp1_configure_isp(struct rkisp1_isp_params_vdev *params_vdev,
> + struct ispsd_in_fmt *in_fmt,
> + enum v4l2_quantization quantization)
> +{
> + /*TODO: default config ? */
> + rkisp1_params_config_parameter(params_vdev);
> +}
> +
> +/* Not called when the camera active, thus not isr protection. */
> +void rkisp1_disable_isp(struct rkisp1_isp_params_vdev *params_vdev)
> +{
> + isp_param_clear_bits(params_vdev, CIF_ISP_DPCC_MODE, CIF_ISP_DPCC_ENA);
> + isp_param_clear_bits(params_vdev, CIF_ISP_LSC_CTRL,
> + CIF_ISP_LSC_CTRL_ENA);
> + isp_param_clear_bits(params_vdev, CIF_ISP_BLS_CTRL, CIF_ISP_BLS_ENA);
> + isp_param_clear_bits(params_vdev, CIF_ISP_CTRL,
> + CIF_ISP_CTRL_ISP_GAMMA_IN_ENA);
> + isp_param_clear_bits(params_vdev, CIF_ISP_CTRL,
> + CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
> + isp_param_clear_bits(params_vdev, CIF_ISP_DEMOSAIC,
> + CIF_ISP_DEMOSAIC_BYPASS);
> + isp_param_clear_bits(params_vdev, CIF_ISP_FILT_MODE, CIF_ISP_FLT_ENA);
> + awb_meas_enable(params_vdev, NULL, false);
> + isp_param_clear_bits(params_vdev, CIF_ISP_CTRL,
> + CIF_ISP_CTRL_ISP_AWB_ENA);
> + isp_param_clear_bits(params_vdev, CIF_ISP_EXP_CTRL, CIF_ISP_EXP_ENA);
> + ctk_enable(params_vdev, false);
> + isp_param_clear_bits(params_vdev, CIF_C_PROC_CTRL,
> + CIF_C_PROC_CTR_ENABLE);
> + hst_enable(params_vdev, NULL, false);
> + isp_param_clear_bits(params_vdev, CIF_ISP_AFM_CTRL, CIF_ISP_AFM_ENA);
> + ie_enable(params_vdev, false);
> + isp_param_clear_bits(params_vdev, CIF_ISP_DPF_MODE,
> + CIF_ISP_DPF_MODE_EN);
> +}
> +
> +/* TODO: should add RKISP1_PARAMS_FMT pixel format to V4L2 framework ? */
> +static int rkisp1_params_enum_fmt_meta_out(struct file *file, void *priv,
> + struct v4l2_fmtdesc *f)
> +{
> + struct video_device *video = video_devdata(file);
> + struct rkisp1_isp_params_vdev *params_vdev = video_get_drvdata(video);
> +
> + if (f->index > 0 || f->type != video->queue->type)
> + return -EINVAL;
> +
> + f->pixelformat = params_vdev->vdev_fmt.fmt.meta.dataformat;
> +
> + return 0;
> +}
> +
> +static int rkisp1_params_g_fmt_meta_out(struct file *file, void *fh,
> + struct v4l2_format *f)
> +{
> + struct video_device *video = video_devdata(file);
> + struct rkisp1_isp_params_vdev *params_vdev = video_get_drvdata(video);
> + struct v4l2_meta_format *meta = &f->fmt.meta;
> +
> + if (f->type != video->queue->type)
> + return -EINVAL;
> +
> + memset(meta, 0, sizeof(*meta));
> + meta->dataformat = params_vdev->vdev_fmt.fmt.meta.dataformat;
> + meta->buffersize = params_vdev->vdev_fmt.fmt.meta.buffersize;
> +
> + return 0;
> +}
> +
> +static int rkisp1_params_querycap(struct file *file,
> + void *priv, struct v4l2_capability *cap)
> +{
> + struct video_device *vdev = video_devdata(file);
> +
> + strcpy(cap->driver, DRIVER_NAME);
> + strlcpy(cap->card, vdev->name, sizeof(cap->card));
> + strlcpy(cap->bus_info, "platform: " DRIVER_NAME, sizeof(cap->bus_info));
> +
> + return 0;
> +}
> +
> +/* ISP params video device IOCTLs */
> +static const struct v4l2_ioctl_ops rkisp1_params_ioctl = {
> + .vidioc_reqbufs = vb2_ioctl_reqbufs,
> + .vidioc_querybuf = vb2_ioctl_querybuf,
> + .vidioc_create_bufs = vb2_ioctl_create_bufs,
> + .vidioc_qbuf = vb2_ioctl_qbuf,
> + .vidioc_dqbuf = vb2_ioctl_dqbuf,
> + .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
> + .vidioc_expbuf = vb2_ioctl_expbuf,
> + .vidioc_streamon = vb2_ioctl_streamon,
> + .vidioc_streamoff = vb2_ioctl_streamoff,
> + .vidioc_enum_fmt_meta_out = rkisp1_params_enum_fmt_meta_out,
> + .vidioc_g_fmt_meta_out = rkisp1_params_g_fmt_meta_out,
> + .vidioc_s_fmt_meta_out = rkisp1_params_g_fmt_meta_out,
> + .vidioc_try_fmt_meta_out = rkisp1_params_g_fmt_meta_out,
> + .vidioc_querycap = rkisp1_params_querycap
> +};
> +
> +static int rkisp1_params_vb2_queue_setup(struct vb2_queue *vq,
> + unsigned int *num_buffers,
> + unsigned int *num_planes,
> + unsigned int sizes[],
> + struct device *alloc_devs[])
> +{
> + struct rkisp1_isp_params_vdev *params_vdev = vq->drv_priv;
> +
> + *num_buffers = clamp_t(u32, *num_buffers,
> + RKISP1_ISP_PARAMS_REQ_BUFS_MIN,
> + RKISP1_ISP_PARAMS_REQ_BUFS_MAX);
> +
> + *num_planes = 1;
> +
> + sizes[0] = sizeof(struct rkisp1_isp_params_cfg);
> +
> + INIT_LIST_HEAD(¶ms_vdev->params);
> + params_vdev->first_params = true;
> +
> + return 0;
> +}
> +
> +static void rkisp1_params_vb2_buf_queue(struct vb2_buffer *vb)
> +{
> + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
> + struct rkisp1_buffer *params_buf = to_rkisp1_buffer(vbuf);
> + struct vb2_queue *vq = vb->vb2_queue;
> + struct rkisp1_isp_params_vdev *params_vdev = vq->drv_priv;
> + struct rkisp1_isp_params_cfg *new_params;
> + unsigned long flags;
> +
> + if (params_vdev->first_params) {
> + new_params = (struct rkisp1_isp_params_cfg *)
> + (vb2_plane_vaddr(vb, 0));
> + spin_lock_irqsave(¶ms_vdev->config_lock, flags);
> + /* __isp_isr_other_config(params_vdev, new_params); */
> + /* __isp_isr_meas_config(params_vdev, new_params); */
> + spin_unlock_irqrestore(¶ms_vdev->config_lock, flags);
> + vb2_buffer_done(¶ms_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
> + params_vdev->first_params = false;
> + params_vdev->cur_params = *new_params;
> + return;
> + }
> +
> + params_buf->vaddr[0] = vb2_plane_vaddr(vb, 0);
> + spin_lock_irqsave(¶ms_vdev->config_lock, flags);
> + list_add_tail(¶ms_buf->queue, ¶ms_vdev->params);
> + spin_unlock_irqrestore(¶ms_vdev->config_lock, flags);
> +}
> +
> +static void rkisp1_params_vb2_stop_streaming(struct vb2_queue *vq)
> +{
> + struct rkisp1_isp_params_vdev *params_vdev = vq->drv_priv;
> + struct rkisp1_buffer *buf;
> + unsigned long flags;
> + int i;
> +
> + /* stop params input firstly */
> + spin_lock_irqsave(¶ms_vdev->config_lock, flags);
> + params_vdev->streamon = false;
> + spin_unlock_irqrestore(¶ms_vdev->config_lock, flags);
> +
> + for (i = 0; i < RKISP1_ISP_PARAMS_REQ_BUFS_MAX; i++) {
> + spin_lock_irqsave(¶ms_vdev->config_lock, flags);
> + if (!list_empty(¶ms_vdev->params)) {
> + buf = list_first_entry(¶ms_vdev->params,
> + struct rkisp1_buffer, queue);
> + list_del(&buf->queue);
> + spin_unlock_irqrestore(¶ms_vdev->config_lock,
> + flags);
> + } else {
> + spin_unlock_irqrestore(¶ms_vdev->config_lock,
> + flags);
> + break;
> + }
> +
> + if (buf)
> + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
> + buf = NULL;
> + }
> +}
> +
> +static int
> +rkisp1_params_vb2_start_streaming(struct vb2_queue *queue, unsigned int count)
> +{
> + struct rkisp1_isp_params_vdev *params_vdev = queue->drv_priv;
> + unsigned long flags;
> +
> + spin_lock_irqsave(¶ms_vdev->config_lock, flags);
> + params_vdev->streamon = true;
> + spin_unlock_irqrestore(¶ms_vdev->config_lock, flags);
> +
> + return 0;
> +}
> +
> +static struct vb2_ops rkisp1_params_vb2_ops = {
> + .queue_setup = rkisp1_params_vb2_queue_setup,
> + .wait_prepare = vb2_ops_wait_prepare,
> + .wait_finish = vb2_ops_wait_finish,
> + .buf_queue = rkisp1_params_vb2_buf_queue,
> + .start_streaming = rkisp1_params_vb2_start_streaming,
> + .stop_streaming = rkisp1_params_vb2_stop_streaming,
> +
> +};
> +
> +struct v4l2_file_operations rkisp1_params_fops = {
> + .mmap = vb2_fop_mmap,
> + .unlocked_ioctl = video_ioctl2,
> + .poll = vb2_fop_poll,
> + .open = v4l2_fh_open,
> + .release = vb2_fop_release
> +};
> +
> +static int
> +rkisp1_params_init_vb2_queue(struct vb2_queue *q,
> + struct rkisp1_isp_params_vdev *params_vdev)
> +{
> + struct rkisp1_vdev_node *node;
> +
> + node = queue_to_node(q);
> +
> + q->type = V4L2_BUF_TYPE_META_OUTPUT;
> + q->io_modes = VB2_MMAP | VB2_USERPTR;
Either add VB2_DMABUF or remove expbuf from the ioctl ops. I would just add VB2_DMABUF.
It doesn't cost anything.
> + q->drv_priv = params_vdev;
> + q->ops = &rkisp1_params_vb2_ops;
> + q->mem_ops = &vb2_vmalloc_memops;
> + q->buf_struct_size = sizeof(struct rkisp1_buffer);
> + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
> + q->lock = &node->vlock;
> +
> + return vb2_queue_init(q);
> +}
> +
> +static void rkisp1_init_params_vdev(struct rkisp1_isp_params_vdev *params_vdev)
> +{
> + params_vdev->vdev_fmt.fmt.meta.dataformat =
> + V4L2_META_FMT_RK_ISP1_PARAMS;
> + params_vdev->vdev_fmt.fmt.meta.buffersize =
> + sizeof(struct rkisp1_isp_params_cfg);
> +}
> +
> +int rkisp1_register_params_vdev(struct rkisp1_isp_params_vdev *params_vdev,
> + struct v4l2_device *v4l2_dev,
> + struct rkisp1_device *dev)
> +{
> + int ret;
> + struct rkisp1_vdev_node *node = ¶ms_vdev->vnode;
> + struct video_device *vdev = &node->vdev;
> +
> + params_vdev->dev = dev;
> + mutex_init(&node->vlock);
> + spin_lock_init(¶ms_vdev->config_lock);
> +
> + strlcpy(vdev->name, "rkisp1-input-params", sizeof(vdev->name));
> +
> + video_set_drvdata(vdev, params_vdev);
> + vdev->ioctl_ops = &rkisp1_params_ioctl;
> + vdev->fops = &rkisp1_params_fops;
> + vdev->release = video_device_release_empty;
> + /*
> + * Provide a mutex to v4l2 core. It will be used
> + * to protect all fops and v4l2 ioctls.
> + */
> + vdev->lock = &node->vlock;
> + vdev->v4l2_dev = v4l2_dev;
> + vdev->queue = &node->buf_queue;
> + vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_META_OUTPUT;
> + vdev->vfl_dir = VFL_DIR_TX;
> + rkisp1_params_init_vb2_queue(vdev->queue, params_vdev);
> + rkisp1_init_params_vdev(params_vdev);
> + video_set_drvdata(vdev, params_vdev);
> +
> + node->pad.flags = MEDIA_PAD_FL_SOURCE;
> + vdev->entity.function = MEDIA_ENT_F_IO_V4L;
> + ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
> + if (ret < 0)
> + goto err_release_queue;
> + ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
> + if (ret < 0) {
> + dev_err(&vdev->dev,
> + "could not register Video for Linux device\n");
> + goto err_cleanup_media_entity;
> + }
> + return 0;
> +err_cleanup_media_entity:
> + media_entity_cleanup(&vdev->entity);
> +err_release_queue:
> + vb2_queue_release(vdev->queue);
> + return ret;
> +}
> +
> +void rkisp1_unregister_params_vdev(struct rkisp1_isp_params_vdev *params_vdev)
> +{
> + struct rkisp1_vdev_node *node = ¶ms_vdev->vnode;
> + struct video_device *vdev = &node->vdev;
> +
> + video_unregister_device(vdev);
> + media_entity_cleanup(&vdev->entity);
> + vb2_queue_release(vdev->queue);
> +}
> diff --git a/drivers/media/platform/rockchip/isp1/isp_params.h b/drivers/media/platform/rockchip/isp1/isp_params.h
> new file mode 100644
> index 000000000000..87604dc370bd
> --- /dev/null
> +++ b/drivers/media/platform/rockchip/isp1/isp_params.h
> @@ -0,0 +1,81 @@
> +/*
> + * Rockchip isp1 driver
> + *
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + *
> + * This software is available to you under a choice of one of two
> + * licenses. You may choose to be licensed under the terms of the GNU
> + * General Public License (GPL) Version 2, available from the file
> + * COPYING in the main directory of this source tree, or the
> + * OpenIB.org BSD license below:
> + *
> + * Redistribution and use in source and binary forms, with or
> + * without modification, are permitted provided that the following
> + * conditions are met:
> + *
> + * - Redistributions of source code must retain the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer.
> + *
> + * - Redistributions in binary form must reproduce the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer in the documentation and/or other materials
> + * provided with the distribution.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#ifndef _RKISP1_ISP_H
> +#define _RKISP1_ISP_H
> +
> +#include <linux/rkisp1-config.h>
> +#include "common.h"
> +
> +struct rkisp1_device;
> +
> +struct rkisp1_isp_params_vdev {
> + struct rkisp1_vdev_node vnode;
> + struct rkisp1_device *dev;
> +
> + /* Current ISP parameters */
> + spinlock_t config_lock;
> + struct list_head params;
> + struct rkisp1_isp_params_cfg cur_params;
> + struct v4l2_format vdev_fmt;
> + bool streamon;
> + bool first_params;
> +
> + bool rkisp1_ism_cropping;
> + enum v4l2_quantization quantization;
> + enum rkisp1_fmt_raw_pat_type raw_type;
> +
> + /* input resolution needed for LSC param check */
> + unsigned int isp_acq_width;
> + unsigned int isp_acq_height;
> + unsigned int active_lsc_width;
> + unsigned int active_lsc_height;
> +
> +};
> +
> +/* config params before ISP streaming */
> +void rkisp1_configure_isp(struct rkisp1_isp_params_vdev *params_vdev,
> + struct ispsd_in_fmt *in_fmt,
> + enum v4l2_quantization quantization);
> +void rkisp1_disable_isp(struct rkisp1_isp_params_vdev *params_vdev);
> +
> +int rkisp1_register_params_vdev(struct rkisp1_isp_params_vdev *params_vdev,
> + struct v4l2_device *v4l2_dev,
> + struct rkisp1_device *dev);
> +
> +void rkisp1_unregister_params_vdev(struct rkisp1_isp_params_vdev *params_vdev);
> +
> +void rkisp1_params_isr(struct rkisp1_isp_params_vdev *params_vdev, u32 isp_mis);
> +
> +#endif /* _RKISP1_ISP_H */
> diff --git a/drivers/media/platform/rockchip/isp1/isp_stats.c b/drivers/media/platform/rockchip/isp1/isp_stats.c
> new file mode 100644
> index 000000000000..afa2579a1241
> --- /dev/null
> +++ b/drivers/media/platform/rockchip/isp1/isp_stats.c
> @@ -0,0 +1,537 @@
> +/*
> + * Rockchip isp1 driver
> + *
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + *
> + * This software is available to you under a choice of one of two
> + * licenses. You may choose to be licensed under the terms of the GNU
> + * General Public License (GPL) Version 2, available from the file
> + * COPYING in the main directory of this source tree, or the
> + * OpenIB.org BSD license below:
> + *
> + * Redistribution and use in source and binary forms, with or
> + * without modification, are permitted provided that the following
> + * conditions are met:
> + *
> + * - Redistributions of source code must retain the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer.
> + *
> + * - Redistributions in binary form must reproduce the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer in the documentation and/or other materials
> + * provided with the distribution.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#include <media/v4l2-common.h>
> +#include <media/v4l2-ioctl.h>
> +#include <media/videobuf2-core.h>
> +#include <media/videobuf2-vmalloc.h> /* for ISP statistics */
> +#include "regs.h"
> +#include "isp_stats.h"
> +#include "isp_params.h"
> +#include "rkisp1.h"
> +
> +#define RKISP1_ISP_STATS_REQ_BUFS_MIN 2
> +#define RKISP1_ISP_STATS_REQ_BUFS_MAX 8
> +
> +static int rkisp1_stats_enum_fmt_meta_cap(struct file *file, void *priv,
> + struct v4l2_fmtdesc *f)
> +{
> + struct video_device *video = video_devdata(file);
> + struct rkisp1_isp_stats_vdev *stats_vdev = video_get_drvdata(video);
> +
> + if (f->index > 0 || f->type != video->queue->type)
> + return -EINVAL;
> +
> + f->pixelformat = stats_vdev->vdev_fmt.fmt.meta.dataformat;
> + return 0;
> +}
> +
> +static int rkisp1_stats_g_fmt_meta_cap(struct file *file, void *priv,
> + struct v4l2_format *f)
> +{
> + struct video_device *video = video_devdata(file);
> + struct rkisp1_isp_stats_vdev *stats_vdev = video_get_drvdata(video);
> + struct v4l2_meta_format *meta = &f->fmt.meta;
> +
> + if (f->type != video->queue->type)
> + return -EINVAL;
> +
> + memset(meta, 0, sizeof(*meta));
> + meta->dataformat = stats_vdev->vdev_fmt.fmt.meta.dataformat;
> + meta->buffersize = stats_vdev->vdev_fmt.fmt.meta.buffersize;
> +
> + return 0;
> +}
> +
> +static int rkisp1_stats_querycap(struct file *file,
> + void *priv, struct v4l2_capability *cap)
> +{
> + struct video_device *vdev = video_devdata(file);
> +
> + strcpy(cap->driver, DRIVER_NAME);
> + strlcpy(cap->card, vdev->name, sizeof(cap->card));
> + strlcpy(cap->bus_info, "platform: " DRIVER_NAME, sizeof(cap->bus_info));
> +
> + return 0;
> +}
> +
> +/* ISP video device IOCTLs */
> +static const struct v4l2_ioctl_ops rkisp1_stats_ioctl = {
> + .vidioc_reqbufs = vb2_ioctl_reqbufs,
> + .vidioc_querybuf = vb2_ioctl_querybuf,
> + .vidioc_create_bufs = vb2_ioctl_create_bufs,
> + .vidioc_qbuf = vb2_ioctl_qbuf,
> + .vidioc_dqbuf = vb2_ioctl_dqbuf,
> + .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
> + .vidioc_expbuf = vb2_ioctl_expbuf,
> + .vidioc_streamon = vb2_ioctl_streamon,
> + .vidioc_streamoff = vb2_ioctl_streamoff,
> + .vidioc_enum_fmt_meta_cap = rkisp1_stats_enum_fmt_meta_cap,
> + .vidioc_g_fmt_meta_cap = rkisp1_stats_g_fmt_meta_cap,
> + .vidioc_s_fmt_meta_cap = rkisp1_stats_g_fmt_meta_cap,
> + .vidioc_try_fmt_meta_cap = rkisp1_stats_g_fmt_meta_cap,
> + .vidioc_querycap = rkisp1_stats_querycap
> +};
> +
> +struct v4l2_file_operations rkisp1_stats_fops = {
> + .mmap = vb2_fop_mmap,
> + .unlocked_ioctl = video_ioctl2,
> + .poll = vb2_fop_poll,
> + .open = v4l2_fh_open,
> + .release = vb2_fop_release
> +};
> +
> +static int rkisp1_stats_vb2_queue_setup(struct vb2_queue *vq,
> + unsigned int *num_buffers,
> + unsigned int *num_planes,
> + unsigned int sizes[],
> + struct device *alloc_devs[])
> +{
> + struct rkisp1_isp_stats_vdev *stats_vdev = vq->drv_priv;
> +
> + *num_planes = 1;
> +
> + *num_buffers = clamp_t(u32, *num_buffers, RKISP1_ISP_STATS_REQ_BUFS_MIN,
> + RKISP1_ISP_STATS_REQ_BUFS_MAX);
> +
> + sizes[0] = sizeof(struct rkisp1_stat_buffer);
> +
> + INIT_LIST_HEAD(&stats_vdev->stat);
> +
> + return 0;
> +}
> +
> +static void rkisp1_stats_vb2_buf_queue(struct vb2_buffer *vb)
> +{
> + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
> + struct rkisp1_buffer *stats_buf = to_rkisp1_buffer(vbuf);
> + struct vb2_queue *vq = vb->vb2_queue;
> + struct rkisp1_isp_stats_vdev *stats_dev = vq->drv_priv;
> + unsigned long flags;
> +
> + stats_buf->vaddr[0] = vb2_plane_vaddr(vb, 0);
> + spin_lock_irqsave(&stats_dev->irq_lock, flags);
> + list_add_tail(&stats_buf->queue, &stats_dev->stat);
> + spin_unlock_irqrestore(&stats_dev->irq_lock, flags);
> +}
> +
> +static void rkisp1_stats_vb2_stop_streaming(struct vb2_queue *vq)
> +{
> + struct rkisp1_isp_stats_vdev *stats_vdev = vq->drv_priv;
> + struct rkisp1_buffer *buf;
> + unsigned long flags;
> + int i;
> +
> + /* stop stats received firstly */
> + spin_lock_irqsave(&stats_vdev->irq_lock, flags);
> + stats_vdev->streamon = false;
> + spin_unlock_irqrestore(&stats_vdev->irq_lock, flags);
> +
> + drain_workqueue(stats_vdev->readout_wq);
> +
> + for (i = 0; i < RKISP1_ISP_STATS_REQ_BUFS_MAX; i++) {
> + spin_lock_irqsave(&stats_vdev->irq_lock, flags);
> + if (!list_empty(&stats_vdev->stat)) {
> + buf = list_first_entry(&stats_vdev->stat,
> + struct rkisp1_buffer, queue);
> + list_del(&buf->queue);
> + spin_unlock_irqrestore(&stats_vdev->irq_lock, flags);
> + } else {
> + spin_unlock_irqrestore(&stats_vdev->irq_lock, flags);
> + break;
> + }
> +
> + if (buf)
> + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
> + buf = NULL;
> + }
> +}
> +
> +static int
> +rkisp1_stats_vb2_start_streaming(struct vb2_queue *queue,
> + unsigned int count)
> +{
> + struct rkisp1_isp_stats_vdev *stats_vdev = queue->drv_priv;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&stats_vdev->irq_lock, flags);
> + stats_vdev->streamon = true;
> + spin_unlock_irqrestore(&stats_vdev->irq_lock, flags);
> +
> + return 0;
> +}
> +
> +static struct vb2_ops rkisp1_stats_vb2_ops = {
> + .queue_setup = rkisp1_stats_vb2_queue_setup,
> + .buf_queue = rkisp1_stats_vb2_buf_queue,
> + .wait_prepare = vb2_ops_wait_prepare,
> + .wait_finish = vb2_ops_wait_finish,
> + .stop_streaming = rkisp1_stats_vb2_stop_streaming,
> + .start_streaming = rkisp1_stats_vb2_start_streaming,
> +};
> +
> +static int rkisp1_stats_init_vb2_queue(struct vb2_queue *q,
> + struct rkisp1_isp_stats_vdev *stats_vdev)
> +{
> + struct rkisp1_vdev_node *node;
> +
> + node = queue_to_node(q);
> +
> + q->type = V4L2_BUF_TYPE_META_CAPTURE;
> + q->io_modes = VB2_MMAP | VB2_USERPTR;
Either add VB2_DMABUF or remove vidioc_expbuf from the ioctl ops.
> + q->drv_priv = stats_vdev;
> + q->ops = &rkisp1_stats_vb2_ops;
> + q->mem_ops = &vb2_vmalloc_memops;
> + q->buf_struct_size = sizeof(struct rkisp1_buffer);
> + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
> + q->lock = &node->vlock;
> +
> + return vb2_queue_init(q);
> +}
> +
> +static void rkisp1_stats_get_awb_meas(struct rkisp1_isp_stats_vdev *stats_vdev,
> + struct rkisp1_stat_buffer *pbuf)
> +{
> + /* Protect against concurrent access from ISR? */
> + u32 reg_val;
> +
> + pbuf->meas_type |= CIFISP_STAT_AWB;
> + reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT);
> + pbuf->params.awb.awb_mean[0].cnt = CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
> + reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN);
> +
> + pbuf->params.awb.awb_mean[0].mean_cr_or_r =
> + CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);
> + pbuf->params.awb.awb_mean[0].mean_cb_or_b =
> + CIF_ISP_AWB_GET_MEAN_CB_B(reg_val);
> + pbuf->params.awb.awb_mean[0].mean_y_or_g =
> + CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);
> +}
> +
> +static void rkisp1_stats_get_aec_meas(struct rkisp1_isp_stats_vdev *stats_vdev,
> + struct rkisp1_stat_buffer *pbuf)
> +{
> + unsigned int i;
> + void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_EXP_MEAN_00;
> +
> + pbuf->meas_type |= CIFISP_STAT_AUTOEXP;
> + for (i = 0; i < CIFISP_AE_MEAN_MAX; i++)
> + pbuf->params.ae.exp_mean[i] = (u8)readl(addr + i * 4);
> +}
> +
> +static void rkisp1_stats_get_afc_meas(struct rkisp1_isp_stats_vdev *stats_vdev,
> + struct rkisp1_stat_buffer *pbuf)
> +{
> + pbuf->meas_type = CIFISP_STAT_AFM_FIN;
> +
> + pbuf->params.af.window[0].sum =
> + readl(stats_vdev->dev->base_addr + CIF_ISP_AFM_SUM_A);
> + pbuf->params.af.window[0].lum =
> + readl(stats_vdev->dev->base_addr + CIF_ISP_AFM_LUM_A);
> + pbuf->params.af.window[1].sum =
> + readl(stats_vdev->dev->base_addr + CIF_ISP_AFM_SUM_B);
> + pbuf->params.af.window[1].lum =
> + readl(stats_vdev->dev->base_addr + CIF_ISP_AFM_LUM_B);
> + pbuf->params.af.window[2].sum =
> + readl(stats_vdev->dev->base_addr + CIF_ISP_AFM_SUM_C);
> + pbuf->params.af.window[2].lum =
> + readl(stats_vdev->dev->base_addr + CIF_ISP_AFM_LUM_C);
> +}
> +
> +static void rkisp1_stats_get_hst_meas(struct rkisp1_isp_stats_vdev *stats_vdev,
> + struct rkisp1_stat_buffer *pbuf)
> +{
> + int i;
> + void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_HIST_BIN_0;
> +
> + pbuf->meas_type |= CIFISP_STAT_HIST;
> + for (i = 0; i < CIFISP_HIST_BIN_N_MAX; i++)
> + pbuf->params.hist.hist_bins[i] = readl(addr + (i * 4));
> +}
> +
> +static void rkisp1_stats_get_bls_meas(struct rkisp1_isp_stats_vdev *stats_vdev,
> + struct rkisp1_stat_buffer *pbuf)
> +{
> + struct rkisp1_device *dev = stats_vdev->dev;
> + struct rkisp1_isp_subdev *sd = &dev->isp_sdev;
> + const struct ispsd_in_fmt *in_fmt = &sd->in_fmt;
> + void __iomem *base = stats_vdev->dev->base_addr;
> +
> + /* TODO: get in_fmt */
> + if (in_fmt->bayer_pat == RAW_BGGR) {
> + pbuf->params.ae.bls_val.meas_b =
> + readl(base + CIF_ISP_BLS_A_MEASURED);
> + pbuf->params.ae.bls_val.meas_gb =
> + readl(base + CIF_ISP_BLS_B_MEASURED);
> + pbuf->params.ae.bls_val.meas_gr =
> + readl(base + CIF_ISP_BLS_C_MEASURED);
> + pbuf->params.ae.bls_val.meas_r =
> + readl(base + CIF_ISP_BLS_D_MEASURED);
> + } else if (in_fmt->bayer_pat == RAW_GBRG) {
> + pbuf->params.ae.bls_val.meas_gb =
> + readl(base + CIF_ISP_BLS_A_MEASURED);
> + pbuf->params.ae.bls_val.meas_b =
> + readl(base + CIF_ISP_BLS_B_MEASURED);
> + pbuf->params.ae.bls_val.meas_r =
> + readl(base + CIF_ISP_BLS_C_MEASURED);
> + pbuf->params.ae.bls_val.meas_gr =
> + readl(base + CIF_ISP_BLS_D_MEASURED);
> + } else if (in_fmt->bayer_pat == RAW_GRBG) {
> + pbuf->params.ae.bls_val.meas_gr =
> + readl(base + CIF_ISP_BLS_A_MEASURED);
> + pbuf->params.ae.bls_val.meas_r =
> + readl(base + CIF_ISP_BLS_B_MEASURED);
> + pbuf->params.ae.bls_val.meas_b =
> + readl(base + CIF_ISP_BLS_C_MEASURED);
> + pbuf->params.ae.bls_val.meas_gb =
> + readl(base + CIF_ISP_BLS_D_MEASURED);
> + } else if (in_fmt->bayer_pat == RAW_RGGB) {
> + pbuf->params.ae.bls_val.meas_r =
> + readl(base + CIF_ISP_BLS_A_MEASURED);
> + pbuf->params.ae.bls_val.meas_gr =
> + readl(base + CIF_ISP_BLS_B_MEASURED);
> + pbuf->params.ae.bls_val.meas_gb =
> + readl(base + CIF_ISP_BLS_C_MEASURED);
> + pbuf->params.ae.bls_val.meas_b =
> + readl(base + CIF_ISP_BLS_D_MEASURED);
> + }
> +}
> +
> +static void
> +rkisp1_stats_send_measurement(struct rkisp1_isp_stats_vdev *stats_vdev,
> + struct rkisp1_isp_readout_work *meas_work)
> +{
> + unsigned long lock_flags = 0;
> + unsigned int cur_frame_id = -1;
> + struct rkisp1_stat_buffer *cur_stat_buf;
> + struct rkisp1_buffer *cur_buf = NULL;
> +
> + spin_lock_irqsave(&stats_vdev->irq_lock, lock_flags);
> + cur_frame_id = atomic_read(&stats_vdev->dev->isp_sdev.frm_sync_seq) - 1;
> + if (cur_frame_id != meas_work->frame_id) {
> + v4l2_warn(stats_vdev->vnode.vdev.v4l2_dev,
> + "Measurement late(%d, %d)\n",
> + cur_frame_id, meas_work->frame_id);
> + }
> + /* get one empty buffer */
> + if (!list_empty(&stats_vdev->stat)) {
> + cur_buf = list_first_entry(&stats_vdev->stat,
> + struct rkisp1_buffer, queue);
> + list_del(&cur_buf->queue);
> + }
> + spin_unlock_irqrestore(&stats_vdev->irq_lock, lock_flags);
> +
> + if (!cur_buf)
> + return;
> +
> + cur_stat_buf =
> + (struct rkisp1_stat_buffer *)(cur_buf->vaddr[0]);
> +
> + if (meas_work->isp_ris & CIF_ISP_AWB_DONE) {
> + rkisp1_stats_get_awb_meas(stats_vdev, cur_stat_buf);
> + cur_stat_buf->meas_type |= CIFISP_STAT_AWB;
> + }
> +
> + if (meas_work->isp_ris & CIF_ISP_AFM_FIN) {
> + rkisp1_stats_get_afc_meas(stats_vdev, cur_stat_buf);
> + cur_stat_buf->meas_type |= CIFISP_STAT_AFM_FIN;
> + }
> +
> + if (meas_work->isp_ris & CIF_ISP_EXP_END) {
> + rkisp1_stats_get_aec_meas(stats_vdev, cur_stat_buf);
> + rkisp1_stats_get_bls_meas(stats_vdev, cur_stat_buf);
> + cur_stat_buf->meas_type |= CIFISP_STAT_AUTOEXP;
> + }
> +
> + if (meas_work->isp_ris & CIF_ISP_HIST_MEASURE_RDY) {
> + rkisp1_stats_get_hst_meas(stats_vdev, cur_stat_buf);
> + cur_stat_buf->meas_type |= CIFISP_STAT_HIST;
> + }
> +
> + vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0,
> + sizeof(struct rkisp1_stat_buffer));
> + vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
> +}
> +
> +static void rkisp1_stats_readout_work(struct work_struct *work)
> +{
> + struct rkisp1_isp_readout_work *readout_work = container_of(work,
> + struct rkisp1_isp_readout_work,
> + work);
> + struct rkisp1_isp_stats_vdev *stats_vdev = readout_work->stats_vdev;
> +
> + if (readout_work->readout == RKISP1_ISP_READOUT_MEAS)
> + rkisp1_stats_send_measurement(stats_vdev, readout_work);
> +
> + kfree(readout_work);
> +}
> +
> +int rkisp1_stats_isr(struct rkisp1_isp_stats_vdev *stats_vdev, u32 isp_ris)
> +{
> + unsigned int isp_mis_tmp = 0;
> + struct rkisp1_isp_readout_work *work;
> + unsigned int cur_frame_id =
> + atomic_read(&stats_vdev->dev->isp_sdev.frm_sync_seq) - 1;
> +#ifdef LOG_ISR_EXE_TIME
> + ktime_t in_t = ktime_get();
> +#endif
> +
> + writel((CIF_ISP_AWB_DONE | CIF_ISP_AFM_FIN | CIF_ISP_EXP_END |
> + CIF_ISP_HIST_MEASURE_RDY),
> + stats_vdev->dev->base_addr + CIF_ISP_ICR);
> +
> + isp_mis_tmp = readl(stats_vdev->dev->base_addr + CIF_ISP_MIS);
> + if (isp_mis_tmp &
> + (CIF_ISP_AWB_DONE | CIF_ISP_AFM_FIN |
> + CIF_ISP_EXP_END | CIF_ISP_HIST_MEASURE_RDY))
> + v4l2_err(stats_vdev->vnode.vdev.v4l2_dev,
> + "isp icr 3A info err: 0x%x\n",
> + isp_mis_tmp);
> +
> + if (isp_ris & (CIF_ISP_AWB_DONE | CIF_ISP_AFM_FIN | CIF_ISP_EXP_END |
> + CIF_ISP_HIST_MEASURE_RDY)) {
> + work = (struct rkisp1_isp_readout_work *)
> + kzalloc(sizeof(struct rkisp1_isp_readout_work),
> + GFP_ATOMIC);
> + if (work) {
> + INIT_WORK(&work->work,
> + rkisp1_stats_readout_work);
> + work->readout = RKISP1_ISP_READOUT_MEAS;
> + work->stats_vdev = stats_vdev;
> + work->frame_id = cur_frame_id;
> + work->isp_ris = isp_ris;
> + if (!queue_work(stats_vdev->readout_wq,
> + &work->work))
> + kfree(work);
> + } else {
> + v4l2_err(stats_vdev->vnode.vdev.v4l2_dev,
> + "Could not allocate work\n");
> + }
> + }
> +
> +#ifdef LOG_ISR_EXE_TIME
> + if (isp_ris & (CIF_ISP_EXP_END | CIF_ISP_AWB_DONE |
> + CIF_ISP_FRAME | CIF_ISP_HIST_MEASURE_RDY)) {
> + unsigned int diff_us =
> + ktime_to_us(ktime_sub(ktime_get(), in_t));
> +
> + if (diff_us > g_longest_isr_time)
> + g_longest_isr_time = diff_us;
> +
> + v4l2_info(stats_vdev->vnode.vdev.v4l2_dev,
> + "isp_isr time %d %d\n", diff_us, g_longest_isr_time);
> + }
> +#endif
> +
> + return 0;
> +}
> +
> +static void rkisp1_init_stats_vdev(struct rkisp1_isp_stats_vdev *stats_vdev)
> +{
> + stats_vdev->vdev_fmt.fmt.meta.dataformat =
> + V4L2_META_FMT_RK_ISP1_STAT_3A;
> + stats_vdev->vdev_fmt.fmt.meta.buffersize =
> + sizeof(struct rkisp1_stat_buffer);
> +}
> +
> +int rkisp1_register_stats_vdev(struct rkisp1_isp_stats_vdev *stats_vdev,
> + struct v4l2_device *v4l2_dev,
> + struct rkisp1_device *dev)
> +{
> + int ret;
> + struct rkisp1_vdev_node *node = &stats_vdev->vnode;
> + struct video_device *vdev = &node->vdev;
> +
> + stats_vdev->dev = dev;
> + mutex_init(&node->vlock);
> + INIT_LIST_HEAD(&stats_vdev->stat);
> + spin_lock_init(&stats_vdev->irq_lock);
> +
> + strlcpy(vdev->name, "rkisp1-statistics", sizeof(vdev->name));
> +
> + video_set_drvdata(vdev, stats_vdev);
> + vdev->ioctl_ops = &rkisp1_stats_ioctl;
> + vdev->fops = &rkisp1_stats_fops;
> + vdev->release = video_device_release_empty;
> + vdev->lock = &node->vlock;
> + vdev->v4l2_dev = v4l2_dev;
> + vdev->queue = &node->buf_queue;
> + vdev->device_caps = V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING;
> + vdev->vfl_dir = VFL_DIR_RX;
> + rkisp1_stats_init_vb2_queue(vdev->queue, stats_vdev);
> + rkisp1_init_stats_vdev(stats_vdev);
> + video_set_drvdata(vdev, stats_vdev);
> +
> + node->pad.flags = MEDIA_PAD_FL_SINK;
> + vdev->entity.function = MEDIA_ENT_F_IO_V4L;
> + ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
> + if (ret < 0)
> + goto err_release_queue;
> +
> + ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
> + if (ret < 0) {
> + dev_err(&vdev->dev,
> + "could not register Video for Linux device\n");
> + goto err_cleanup_media_entity;
> + }
> +
> + stats_vdev->readout_wq =
> + alloc_workqueue("measurement_queue",
> + WQ_UNBOUND | WQ_MEM_RECLAIM, 1);
> +
> + if (!stats_vdev->readout_wq) {
> + ret = -ENOMEM;
> + goto err_unreg_vdev;
> + }
> +
> + return 0;
> +err_unreg_vdev:
> + video_unregister_device(vdev);
> +err_cleanup_media_entity:
> + media_entity_cleanup(&vdev->entity);
> +err_release_queue:
> + vb2_queue_release(vdev->queue);
> + return ret;
> +}
> +
> +void rkisp1_unregister_stats_vdev(struct rkisp1_isp_stats_vdev *stats_vdev)
> +{
> + struct rkisp1_vdev_node *node = &stats_vdev->vnode;
> + struct video_device *vdev = &node->vdev;
> +
> + destroy_workqueue(stats_vdev->readout_wq);
> + video_unregister_device(vdev);
> + media_entity_cleanup(&vdev->entity);
> + vb2_queue_release(vdev->queue);
> +}
> diff --git a/drivers/media/platform/rockchip/isp1/isp_stats.h b/drivers/media/platform/rockchip/isp1/isp_stats.h
> new file mode 100644
> index 000000000000..d42cd9e75efd
> --- /dev/null
> +++ b/drivers/media/platform/rockchip/isp1/isp_stats.h
> @@ -0,0 +1,81 @@
> +/*
> + * Rockchip isp1 driver
> + *
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + *
> + * This software is available to you under a choice of one of two
> + * licenses. You may choose to be licensed under the terms of the GNU
> + * General Public License (GPL) Version 2, available from the file
> + * COPYING in the main directory of this source tree, or the
> + * OpenIB.org BSD license below:
> + *
> + * Redistribution and use in source and binary forms, with or
> + * without modification, are permitted provided that the following
> + * conditions are met:
> + *
> + * - Redistributions of source code must retain the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer.
> + *
> + * - Redistributions in binary form must reproduce the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer in the documentation and/or other materials
> + * provided with the distribution.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#ifndef _RKISP1_ISP_STATS_H
> +#define _RKISP1_ISP_STATS_H
> +
> +#include <linux/rkisp1-config.h>
> +#include "common.h"
> +
> +struct rkisp1_isp_stats_vdev;
> +struct rkisp1_device;
> +
> +enum rkisp1_isp_readout_cmd {
> + RKISP1_ISP_READOUT_MEAS,
> + /* TODO: metadata */
> + RKISP1_ISP_READOUT_META,
> +};
> +
> +struct rkisp1_isp_readout_work {
> + struct work_struct work;
> + struct rkisp1_isp_stats_vdev *stats_vdev;
> +
> + unsigned int frame_id;
> + unsigned int isp_ris;
> + enum rkisp1_isp_readout_cmd readout;
> + struct vb2_buffer *vb;
> +};
> +
> +struct rkisp1_isp_stats_vdev {
> + struct rkisp1_vdev_node vnode;
> + struct rkisp1_device *dev;
> +
> + /* ISP statistics related */
> + spinlock_t irq_lock;
> + struct list_head stat; /* stats buffer list */
> + struct v4l2_format vdev_fmt;
> + bool streamon;
> +
> + struct workqueue_struct *readout_wq;
> +};
> +
> +int rkisp1_stats_isr(struct rkisp1_isp_stats_vdev *stats_vdev, u32 isp_ris);
> +
> +int rkisp1_register_stats_vdev(struct rkisp1_isp_stats_vdev *stats_vdev,
> + struct v4l2_device *v4l2_dev,
> + struct rkisp1_device *dev);
> +
> +void rkisp1_unregister_stats_vdev(struct rkisp1_isp_stats_vdev *stats_vdev);
> +
> +#endif /* _RKISP1_ISP_STATS_H */
> diff --git a/drivers/media/platform/rockchip/isp1/regs.c b/drivers/media/platform/rockchip/isp1/regs.c
> new file mode 100644
> index 000000000000..496fdcef466f
> --- /dev/null
> +++ b/drivers/media/platform/rockchip/isp1/regs.c
> @@ -0,0 +1,251 @@
> +/*
> + * Rockchip isp1 driver
> + *
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + *
> + * This software is available to you under a choice of one of two
> + * licenses. You may choose to be licensed under the terms of the GNU
> + * General Public License (GPL) Version 2, available from the file
> + * COPYING in the main directory of this source tree, or the
> + * OpenIB.org BSD license below:
> + *
> + * Redistribution and use in source and binary forms, with or
> + * without modification, are permitted provided that the following
> + * conditions are met:
> + *
> + * - Redistributions of source code must retain the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer.
> + *
> + * - Redistributions in binary form must reproduce the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer in the documentation and/or other materials
> + * provided with the distribution.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#include <media/v4l2-common.h>
> +#include "regs.h"
> +
> +void disable_dcrop(struct rkisp1_stream *stream, bool async)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> + void __iomem *dc_ctrl_addr = base + stream->config->dual_crop.ctrl;
> + u32 dc_ctrl = readl(dc_ctrl_addr);
> + u32 mask = ~(stream->config->dual_crop.yuvmode_mask |
> + stream->config->dual_crop.rawmode_mask);
> + u32 val = dc_ctrl & mask;
> +
> + if (async)
> + val |= CIF_DUAL_CROP_GEN_CFG_UPD;
> + else
> + val |= CIF_DUAL_CROP_CFG_UPD;
> + writel(val, dc_ctrl_addr);
> +}
> +
> +void config_dcrop(struct rkisp1_stream *stream, struct v4l2_rect *rect, bool async)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> + void __iomem *dc_ctrl_addr = base + stream->config->dual_crop.ctrl;
> + u32 dc_ctrl = readl(dc_ctrl_addr);
> +
> + writel(rect->left, base + stream->config->dual_crop.h_offset);
> + writel(rect->top, base + stream->config->dual_crop.v_offset);
> + writel(rect->width, base + stream->config->dual_crop.h_size);
> + writel(rect->height, base + stream->config->dual_crop.v_size);
> + dc_ctrl |= stream->config->dual_crop.yuvmode_mask;
> + if (async)
> + dc_ctrl |= CIF_DUAL_CROP_GEN_CFG_UPD;
> + else
> + dc_ctrl |= CIF_DUAL_CROP_CFG_UPD;
> + writel(dc_ctrl, dc_ctrl_addr);
> +}
> +
> +void dump_rsz_regs(struct rkisp1_stream *stream)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> +
> + pr_info("RSZ_CTRL 0x%08x/0x%08x\n"
> + "RSZ_SCALE_HY %d/%d\n"
> + "RSZ_SCALE_HCB %d/%d\n"
> + "RSZ_SCALE_HCR %d/%d\n"
> + "RSZ_SCALE_VY %d/%d\n"
> + "RSZ_SCALE_VC %d/%d\n"
> + "RSZ_PHASE_HY %d/%d\n"
> + "RSZ_PHASE_HC %d/%d\n"
> + "RSZ_PHASE_VY %d/%d\n"
> + "RSZ_PHASE_VC %d/%d\n",
> + readl(base + stream->config->rsz.ctrl),
> + readl(base + stream->config->rsz.ctrl_shd),
> + readl(base + stream->config->rsz.scale_hy),
> + readl(base + stream->config->rsz.scale_hy_shd),
> + readl(base + stream->config->rsz.scale_hcb),
> + readl(base + stream->config->rsz.scale_hcb_shd),
> + readl(base + stream->config->rsz.scale_hcr),
> + readl(base + stream->config->rsz.scale_hcr_shd),
> + readl(base + stream->config->rsz.scale_vy),
> + readl(base + stream->config->rsz.scale_vy_shd),
> + readl(base + stream->config->rsz.scale_vc),
> + readl(base + stream->config->rsz.scale_vc_shd),
> + readl(base + stream->config->rsz.phase_hy),
> + readl(base + stream->config->rsz.phase_hy_shd),
> + readl(base + stream->config->rsz.phase_hc),
> + readl(base + stream->config->rsz.phase_hc_shd),
> + readl(base + stream->config->rsz.phase_vy),
> + readl(base + stream->config->rsz.phase_vy_shd),
> + readl(base + stream->config->rsz.phase_vc),
> + readl(base + stream->config->rsz.phase_vc_shd));
> +}
> +
> +static void update_rsz_shadow(struct rkisp1_stream *stream)
> +{
> + void *addr = stream->ispdev->base_addr + stream->config->rsz.ctrl;
> + u32 ctrl_cfg = readl(addr);
> +
> + writel(CIF_RSZ_CTRL_CFG_UPD | ctrl_cfg, addr);
> +}
> +
> +static void set_scale(struct rkisp1_stream *stream, struct v4l2_rect *in_y,
> + struct v4l2_rect *in_c, struct v4l2_rect *out_y,
> + struct v4l2_rect *out_c)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> + void __iomem *scale_hy_addr = base + stream->config->rsz.scale_hy;
> + void __iomem *scale_hcr_addr = base + stream->config->rsz.scale_hcr;
> + void __iomem *scale_hcb_addr = base + stream->config->rsz.scale_hcb;
> + void __iomem *scale_vy_addr = base + stream->config->rsz.scale_vy;
> + void __iomem *scale_vc_addr = base + stream->config->rsz.scale_vc;
> + void __iomem *rsz_ctrl_addr = base + stream->config->rsz.ctrl;
> + u32 scale_hy, scale_hc, scale_vy, scale_vc, rsz_ctrl = 0;
> +
> + if (in_y->width < out_y->width) {
> + rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HY_ENABLE |
> + CIF_RSZ_CTRL_SCALE_HY_UP;
> + scale_hy = ((in_y->width - 1) * CIF_RSZ_SCALER_FACTOR) /
> + (out_y->width - 1);
> + writel(scale_hy, scale_hy_addr);
> + } else if (in_y->width > out_y->width) {
> + rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HY_ENABLE;
> + scale_hy = ((out_y->width - 1) * CIF_RSZ_SCALER_FACTOR) /
> + (in_y->width - 1) + 1;
> + writel(scale_hy, scale_hy_addr);
> + }
> + if (in_c->width < out_c->width) {
> + rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HC_ENABLE |
> + CIF_RSZ_CTRL_SCALE_HC_UP;
> + scale_hc = ((in_c->width - 1) * CIF_RSZ_SCALER_FACTOR) /
> + (out_c->width - 1);
> + writel(scale_hc, scale_hcb_addr);
> + writel(scale_hc, scale_hcr_addr);
> + } else if (in_c->width > out_c->width) {
> + rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HC_ENABLE;
> + scale_hc = ((out_c->width - 1) * CIF_RSZ_SCALER_FACTOR) /
> + (in_c->width - 1) + 1;
> + writel(scale_hc, scale_hcb_addr);
> + writel(scale_hc, scale_hcr_addr);
> + }
> +
> + if (in_y->height < out_y->height) {
> + rsz_ctrl |= CIF_RSZ_CTRL_SCALE_VY_ENABLE |
> + CIF_RSZ_CTRL_SCALE_VY_UP;
> + scale_vy = ((in_y->height - 1) * CIF_RSZ_SCALER_FACTOR) /
> + (out_y->height - 1);
> + writel(scale_vy, scale_vy_addr);
> + } else if (in_y->height > out_y->height) {
> + rsz_ctrl |= CIF_RSZ_CTRL_SCALE_VY_ENABLE;
> + scale_vy = ((out_y->height - 1) * CIF_RSZ_SCALER_FACTOR) /
> + (in_y->height - 1) + 1;
> + writel(scale_vy, scale_vy_addr);
> + }
> +
> + if (in_c->height < out_c->height) {
> + rsz_ctrl |= CIF_RSZ_CTRL_SCALE_VC_ENABLE |
> + CIF_RSZ_CTRL_SCALE_VC_UP;
> + scale_vc = ((in_c->height - 1) * CIF_RSZ_SCALER_FACTOR) /
> + (out_c->height - 1);
> + writel(scale_vc, scale_vc_addr);
> + } else if (in_c->height > out_c->height) {
> + rsz_ctrl |= CIF_RSZ_CTRL_SCALE_VC_ENABLE;
> + scale_vc = ((out_c->height - 1) * CIF_RSZ_SCALER_FACTOR) /
> + (in_c->height - 1) + 1;
> + writel(scale_vc, scale_vc_addr);
> + }
> +
> + writel(rsz_ctrl, rsz_ctrl_addr);
> +}
> +
> +void config_rsz(struct rkisp1_stream *stream, struct v4l2_rect *in_y,
> + struct v4l2_rect *in_c, struct v4l2_rect *out_y,
> + struct v4l2_rect *out_c, bool async)
> +{
> + int i = 0;
> +
> + /* No phase offset */
> + writel(0, stream->ispdev->base_addr + stream->config->rsz.phase_hy);
> + writel(0, stream->ispdev->base_addr + stream->config->rsz.phase_hc);
> + writel(0, stream->ispdev->base_addr + stream->config->rsz.phase_vy);
> + writel(0, stream->ispdev->base_addr + stream->config->rsz.phase_vc);
> +
> + /* Linear interpolation */
> + for (i = 0; i < 64; i++) {
> + writel(i, stream->ispdev->base_addr + stream->config->rsz.scale_lut_addr);
> + writel(i, stream->ispdev->base_addr + stream->config->rsz.scale_lut);
> + }
> +
> + set_scale(stream, in_y, in_c, out_y, out_c);
> +
> + if (!async)
> + update_rsz_shadow(stream);
> +}
> +
> +void disable_rsz(struct rkisp1_stream *stream, bool async)
> +{
> + writel(0, stream->ispdev->base_addr + stream->config->rsz.ctrl);
> +
> + if (!async)
> + update_rsz_shadow(stream);
> +}
> +
> +void config_mi_ctrl(struct rkisp1_stream *stream)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> + void __iomem *addr = base + CIF_MI_CTRL;
> + u32 reg;
> +
> + reg = readl(addr) & ~GENMASK(17, 16);
> + writel(reg | CIF_MI_CTRL_BURST_LEN_LUM_64, addr);
> + reg = readl(addr) & ~GENMASK(19, 18);
> + writel(reg | CIF_MI_CTRL_BURST_LEN_CHROM_64, addr);
> + reg = readl(addr);
> + writel(reg | CIF_MI_CTRL_INIT_BASE_EN, addr);
> + reg = readl(addr);
> + writel(reg | CIF_MI_CTRL_INIT_OFFSET_EN, addr);
> +}
> +
> +void mp_clr_frame_end_int(void __iomem *base)
> +{
> + writel(CIF_MI_MP_FRAME, base + CIF_MI_ICR);
> +}
> +
> +void sp_clr_frame_end_int(void __iomem *base)
> +{
> + writel(CIF_MI_SP_FRAME, base + CIF_MI_ICR);
> +}
> +
> +u32 mp_is_frame_end_int_masked(void __iomem *base)
> +{
> + return (mi_get_masked_int_status(base) & CIF_MI_MP_FRAME);
> +}
> +
> +u32 sp_is_frame_end_int_masked(void __iomem *base)
> +{
> + return (mi_get_masked_int_status(base) & CIF_MI_SP_FRAME);
> +}
> diff --git a/drivers/media/platform/rockchip/isp1/regs.h b/drivers/media/platform/rockchip/isp1/regs.h
> new file mode 100644
> index 000000000000..70c554459b7d
> --- /dev/null
> +++ b/drivers/media/platform/rockchip/isp1/regs.h
> @@ -0,0 +1,1578 @@
> +/*
> + * Rockchip isp1 driver
> + *
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + *
> + * This software is available to you under a choice of one of two
> + * licenses. You may choose to be licensed under the terms of the GNU
> + * General Public License (GPL) Version 2, available from the file
> + * COPYING in the main directory of this source tree, or the
> + * OpenIB.org BSD license below:
> + *
> + * Redistribution and use in source and binary forms, with or
> + * without modification, are permitted provided that the following
> + * conditions are met:
> + *
> + * - Redistributions of source code must retain the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer.
> + *
> + * - Redistributions in binary form must reproduce the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer in the documentation and/or other materials
> + * provided with the distribution.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#ifndef _RKISP1_REGS_H
> +#define _RKISP1_REGS_H
> +#include "common.h"
> +#include "rkisp1.h"
> +
> +/* ISP_CTRL */
> +#define CIF_ISP_CTRL_ISP_ENABLE BIT(0)
> +#define CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
> +#define CIF_ISP_CTRL_ISP_MODE_ITU656 (1 << 1)
> +#define CIF_ISP_CTRL_ISP_MODE_ITU601 (2 << 1)
> +#define CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601 (3 << 1)
> +#define CIF_ISP_CTRL_ISP_MODE_DATA_MODE (4 << 1)
> +#define CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656 (5 << 1)
> +#define CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656 (6 << 1)
> +#define CIF_ISP_CTRL_ISP_INFORM_ENABLE BIT(4)
> +#define CIF_ISP_CTRL_ISP_GAMMA_IN_ENA BIT(6)
> +#define CIF_ISP_CTRL_ISP_AWB_ENA BIT(7)
> +#define CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT BIT(8)
> +#define CIF_ISP_CTRL_ISP_CFG_UPD BIT(9)
> +#define CIF_ISP_CTRL_ISP_GEN_CFG_UPD BIT(10)
> +#define CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA BIT(11)
> +#define CIF_ISP_CTRL_ISP_FLASH_MODE_ENA BIT(12)
> +#define CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA BIT(13)
> +#define CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA BIT(14)
> +
> +/* ISP_ACQ_PROP */
> +#define CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
> +#define CIF_ISP_ACQ_PROP_HSYNC_LOW BIT(1)
> +#define CIF_ISP_ACQ_PROP_VSYNC_LOW BIT(2)
> +#define CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
> +#define CIF_ISP_ACQ_PROP_BAYER_PAT_GRBG (1 << 3)
> +#define CIF_ISP_ACQ_PROP_BAYER_PAT_GBRG (2 << 3)
> +#define CIF_ISP_ACQ_PROP_BAYER_PAT_BGGR (3 << 3)
> +#define CIF_ISP_ACQ_PROP_BAYER_PAT(pat) ((pat) << 3)
> +#define CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
> +#define CIF_ISP_ACQ_PROP_YCRYCB (1 << 7)
> +#define CIF_ISP_ACQ_PROP_CBYCRY (2 << 7)
> +#define CIF_ISP_ACQ_PROP_CRYCBY (3 << 7)
> +#define CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
> +#define CIF_ISP_ACQ_PROP_FIELD_SEL_EVEN (1 << 9)
> +#define CIF_ISP_ACQ_PROP_FIELD_SEL_ODD (2 << 9)
> +#define CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
> +#define CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO (1 << 12)
> +#define CIF_ISP_ACQ_PROP_IN_SEL_10B_MSB (2 << 12)
> +#define CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO (3 << 12)
> +#define CIF_ISP_ACQ_PROP_IN_SEL_8B_MSB (4 << 12)
> +
> +/* VI_DPCL */
> +#define CIF_VI_DPCL_DMA_JPEG (0 << 0)
> +#define CIF_VI_DPCL_MP_MUX_MRSZ_MI (1 << 0)
> +#define CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
> +#define CIF_VI_DPCL_CHAN_MODE_MP (1 << 2)
> +#define CIF_VI_DPCL_CHAN_MODE_SP (2 << 2)
> +#define CIF_VI_DPCL_CHAN_MODE_MPSP (3 << 2)
> +#define CIF_VI_DPCL_DMA_SW_SPMUX (0 << 4)
> +#define CIF_VI_DPCL_DMA_SW_SI (1 << 4)
> +#define CIF_VI_DPCL_DMA_SW_IE (2 << 4)
> +#define CIF_VI_DPCL_DMA_SW_JPEG (3 << 4)
> +#define CIF_VI_DPCL_DMA_SW_ISP (4 << 4)
> +#define CIF_VI_DPCL_IF_SEL_PARALLEL (0 << 8)
> +#define CIF_VI_DPCL_IF_SEL_SMIA (1 << 8)
> +#define CIF_VI_DPCL_IF_SEL_MIPI (2 << 8)
> +#define CIF_VI_DPCL_DMA_IE_MUX_DMA BIT(10)
> +#define CIF_VI_DPCL_DMA_SP_MUX_DMA BIT(11)
> +
> +/* ISP_IMSC - ISP_MIS - ISP_RIS - ISP_ICR - ISP_ISR */
> +#define CIF_ISP_OFF BIT(0)
> +#define CIF_ISP_FRAME BIT(1)
> +#define CIF_ISP_DATA_LOSS BIT(2)
> +#define CIF_ISP_PIC_SIZE_ERROR BIT(3)
> +#define CIF_ISP_AWB_DONE BIT(4)
> +#define CIF_ISP_FRAME_IN BIT(5)
> +#define CIF_ISP_V_START BIT(6)
> +#define CIF_ISP_H_START BIT(7)
> +#define CIF_ISP_FLASH_ON BIT(8)
> +#define CIF_ISP_FLASH_OFF BIT(9)
> +#define CIF_ISP_SHUTTER_ON BIT(10)
> +#define CIF_ISP_SHUTTER_OFF BIT(11)
> +#define CIF_ISP_AFM_SUM_OF BIT(12)
> +#define CIF_ISP_AFM_LUM_OF BIT(13)
> +#define CIF_ISP_AFM_FIN BIT(14)
> +#define CIF_ISP_HIST_MEASURE_RDY BIT(15)
> +#define CIF_ISP_FLASH_CAP BIT(17)
> +#define CIF_ISP_EXP_END BIT(18)
> +#define CIF_ISP_VSM_END BIT(19)
> +
> +/* ISP_ERR */
> +#define CIF_ISP_ERR_INFORM_SIZE BIT(0)
> +#define CIF_ISP_ERR_IS_SIZE BIT(1)
> +#define CIF_ISP_ERR_OUTFORM_SIZE BIT(2)
> +
> +/* MI_CTRL */
> +#define CIF_MI_CTRL_MP_ENABLE (1 << 0)
> +#define CIF_MI_CTRL_SP_ENABLE (2 << 0)
> +#define CIF_MI_CTRL_JPEG_ENABLE (4 << 0)
> +#define CIF_MI_CTRL_RAW_ENABLE (8 << 0)
> +#define CIF_MI_CTRL_HFLIP BIT(4)
> +#define CIF_MI_CTRL_VFLIP BIT(5)
> +#define CIF_MI_CTRL_ROT BIT(6)
> +#define CIF_MI_BYTE_SWAP BIT(7)
> +#define CIF_MI_SP_Y_FULL_YUV2RGB BIT(8)
> +#define CIF_MI_SP_CBCR_FULL_YUV2RGB BIT(9)
> +#define CIF_MI_SP_422NONCOSITEED BIT(10)
> +#define CIF_MI_MP_PINGPONG_ENABEL BIT(11)
> +#define CIF_MI_SP_PINGPONG_ENABEL BIT(12)
> +#define CIF_MI_MP_AUTOUPDATE_ENABLE BIT(13)
> +#define CIF_MI_SP_AUTOUPDATE_ENABLE BIT(14)
> +#define CIF_MI_LAST_PIXEL_SIG_ENABLE BIT(15)
> +#define CIF_MI_CTRL_BURST_LEN_LUM_16 (0 << 16)
> +#define CIF_MI_CTRL_BURST_LEN_LUM_32 (1 << 16)
> +#define CIF_MI_CTRL_BURST_LEN_LUM_64 (2 << 16)
> +#define CIF_MI_CTRL_BURST_LEN_CHROM_16 (0 << 18)
> +#define CIF_MI_CTRL_BURST_LEN_CHROM_32 (1 << 18)
> +#define CIF_MI_CTRL_BURST_LEN_CHROM_64 (2 << 18)
> +#define CIF_MI_CTRL_INIT_BASE_EN BIT(20)
> +#define CIF_MI_CTRL_INIT_OFFSET_EN BIT(21)
> +#define MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8 (0 << 22)
> +#define MI_CTRL_MP_WRITE_YUV_SPLA (1 << 22)
> +#define MI_CTRL_MP_WRITE_YUVINT (2 << 22)
> +#define MI_CTRL_MP_WRITE_RAW12 (2 << 22)
> +#define MI_CTRL_SP_WRITE_PLA (0 << 24)
> +#define MI_CTRL_SP_WRITE_SPLA (1 << 24)
> +#define MI_CTRL_SP_WRITE_INT (2 << 24)
> +#define MI_CTRL_SP_INPUT_YUV400 (0 << 26)
> +#define MI_CTRL_SP_INPUT_YUV420 (1 << 26)
> +#define MI_CTRL_SP_INPUT_YUV422 (2 << 26)
> +#define MI_CTRL_SP_INPUT_YUV444 (3 << 26)
> +#define MI_CTRL_SP_OUTPUT_YUV400 (0 << 28)
> +#define MI_CTRL_SP_OUTPUT_YUV420 (1 << 28)
> +#define MI_CTRL_SP_OUTPUT_YUV422 (2 << 28)
> +#define MI_CTRL_SP_OUTPUT_YUV444 (3 << 28)
> +#define MI_CTRL_SP_OUTPUT_RGB565 (4 << 28)
> +#define MI_CTRL_SP_OUTPUT_RGB666 (5 << 28)
> +#define MI_CTRL_SP_OUTPUT_RGB888 (6 << 28)
> +
> +#define MI_CTRL_MP_FMT_MASK GENMASK(23, 22)
> +#define MI_CTRL_SP_FMT_MASK GENMASK(30, 24)
> +
> +/* MI_INIT */
> +#define CIF_MI_INIT_SKIP BIT(2)
> +#define CIF_MI_INIT_SOFT_UPD BIT(4)
> +
> +/* RSZ_CTRL */
> +#define CIF_RSZ_CTRL_SCALE_HY_ENABLE BIT(0)
> +#define CIF_RSZ_CTRL_SCALE_HC_ENABLE BIT(1)
> +#define CIF_RSZ_CTRL_SCALE_VY_ENABLE BIT(2)
> +#define CIF_RSZ_CTRL_SCALE_VC_ENABLE BIT(3)
> +#define CIF_RSZ_CTRL_SCALE_HY_UP BIT(4)
> +#define CIF_RSZ_CTRL_SCALE_HC_UP BIT(5)
> +#define CIF_RSZ_CTRL_SCALE_VY_UP BIT(6)
> +#define CIF_RSZ_CTRL_SCALE_VC_UP BIT(7)
> +#define CIF_RSZ_CTRL_CFG_UPD BIT(8)
> +#define CIF_RSZ_CTRL_CFG_UPD_AUTO BIT(9)
> +#define CIF_RSZ_SCALER_FACTOR BIT(16)
> +
> +/* MI_IMSC - MI_MIS - MI_RIS - MI_ICR - MI_ISR */
> +#define CIF_MI_MP_FRAME BIT(0)
> +#define CIF_MI_SP_FRAME BIT(1)
> +#define CIF_MI_MBLK_LINE BIT(2)
> +#define CIF_MI_FILL_MP_Y BIT(3)
> +#define CIF_MI_WRAP_MP_Y BIT(4)
> +#define CIF_MI_WRAP_MP_CB BIT(5)
> +#define CIF_MI_WRAP_MP_CR BIT(6)
> +#define CIF_MI_WRAP_SP_Y BIT(7)
> +#define CIF_MI_WRAP_SP_CB BIT(8)
> +#define CIF_MI_WRAP_SP_CR BIT(9)
> +#define CIF_MI_DMA_READY BIT(11)
> +
> +/* MI_STATUS */
> +#define CIF_MI_STATUS_MP_Y_FIFO_FULL BIT(0)
> +#define CIF_MI_STATUS_SP_Y_FIFO_FULL BIT(4)
> +
> +/* MI_DMA_CTRL */
> +#define CIF_MI_DMA_CTRL_BURST_LEN_LUM_16 (0 << 0)
> +#define CIF_MI_DMA_CTRL_BURST_LEN_LUM_32 (1 << 0)
> +#define CIF_MI_DMA_CTRL_BURST_LEN_LUM_64 (2 << 0)
> +#define CIF_MI_DMA_CTRL_BURST_LEN_CHROM_16 (0 << 2)
> +#define CIF_MI_DMA_CTRL_BURST_LEN_CHROM_32 (1 << 2)
> +#define CIF_MI_DMA_CTRL_BURST_LEN_CHROM_64 (2 << 2)
> +#define CIF_MI_DMA_CTRL_READ_FMT_PLANAR (0 << 4)
> +#define CIF_MI_DMA_CTRL_READ_FMT_SPLANAR (1 << 4)
> +#define CIF_MI_DMA_CTRL_FMT_YUV400 (0 << 6)
> +#define CIF_MI_DMA_CTRL_FMT_YUV420 (1 << 6)
> +#define CIF_MI_DMA_CTRL_READ_FMT_PACKED (2 << 4)
> +#define CIF_MI_DMA_CTRL_FMT_YUV422 (2 << 6)
> +#define CIF_MI_DMA_CTRL_FMT_YUV444 (3 << 6)
> +#define CIF_MI_DMA_CTRL_BYTE_SWAP BIT(8)
> +#define CIF_MI_DMA_CTRL_CONTINUOUS_ENA BIT(9)
> +#define CIF_MI_DMA_CTRL_RGB_BAYER_NO (0 << 12)
> +#define CIF_MI_DMA_CTRL_RGB_BAYER_8BIT (1 << 12)
> +#define CIF_MI_DMA_CTRL_RGB_BAYER_16BIT (2 << 12)
> +/* MI_DMA_START */
> +#define CIF_MI_DMA_START_ENABLE BIT(0)
> +/* MI_XTD_FORMAT_CTRL */
> +#define CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP BIT(0)
> +#define CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP BIT(1)
> +#define CIF_MI_XTD_FMT_CTRL_DMA_CB_CR_SWAP BIT(2)
> +
> +/* CCL */
> +#define CIF_CCL_CIF_CLK_DIS BIT(2)
> +/* ICCL */
> +#define CIF_ICCL_ISP_CLK BIT(0)
> +#define CIF_ICCL_CP_CLK BIT(1)
> +#define CIF_ICCL_RES_2 BIT(2)
> +#define CIF_ICCL_MRSZ_CLK BIT(3)
> +#define CIF_ICCL_SRSZ_CLK BIT(4)
> +#define CIF_ICCL_JPEG_CLK BIT(5)
> +#define CIF_ICCL_MI_CLK BIT(6)
> +#define CIF_ICCL_RES_7 BIT(7)
> +#define CIF_ICCL_IE_CLK BIT(8)
> +#define CIF_ICCL_SIMP_CLK BIT(9)
> +#define CIF_ICCL_SMIA_CLK BIT(10)
> +#define CIF_ICCL_MIPI_CLK BIT(11)
> +#define CIF_ICCL_DCROP_CLK BIT(12)
> +/* IRCL */
> +#define CIF_IRCL_ISP_SW_RST BIT(0)
> +#define CIF_IRCL_CP_SW_RST BIT(1)
> +#define CIF_IRCL_YCS_SW_RST BIT(2)
> +#define CIF_IRCL_MRSZ_SW_RST BIT(3)
> +#define CIF_IRCL_SRSZ_SW_RST BIT(4)
> +#define CIF_IRCL_JPEG_SW_RST BIT(5)
> +#define CIF_IRCL_MI_SW_RST BIT(6)
> +#define CIF_IRCL_CIF_SW_RST BIT(7)
> +#define CIF_IRCL_IE_SW_RST BIT(8)
> +#define CIF_IRCL_SI_SW_RST BIT(9)
> +#define CIF_IRCL_MIPI_SW_RST BIT(11)
> +
> +/* C_PROC_CTR */
> +#define CIF_C_PROC_CTR_ENABLE BIT(0)
> +#define CIF_C_PROC_YOUT_FULL BIT(1)
> +#define CIF_C_PROC_YIN_FULL BIT(2)
> +#define CIF_C_PROC_COUT_FULL BIT(3)
> +#define CIF_C_PROC_CTRL_RESERVED 0xFFFFFFFE
> +#define CIF_C_PROC_CONTRAST_RESERVED 0xFFFFFF00
> +#define CIF_C_PROC_BRIGHTNESS_RESERVED 0xFFFFFF00
> +#define CIF_C_PROC_HUE_RESERVED 0xFFFFFF00
> +#define CIF_C_PROC_SATURATION_RESERVED 0xFFFFFF00
> +#define CIF_C_PROC_MACC_RESERVED 0xE000E000
> +#define CIF_C_PROC_TONE_RESERVED 0xF000
> +/* DUAL_CROP_CTRL */
> +#define CIF_DUAL_CROP_MP_MODE_BYPASS (0 << 0)
> +#define CIF_DUAL_CROP_MP_MODE_YUV (1 << 0)
> +#define CIF_DUAL_CROP_MP_MODE_RAW (2 << 0)
> +#define CIF_DUAL_CROP_SP_MODE_BYPASS (0 << 2)
> +#define CIF_DUAL_CROP_SP_MODE_YUV (1 << 2)
> +#define CIF_DUAL_CROP_SP_MODE_RAW (2 << 2)
> +#define CIF_DUAL_CROP_CFG_UPD_PERMANENT BIT(4)
> +#define CIF_DUAL_CROP_CFG_UPD BIT(5)
> +#define CIF_DUAL_CROP_GEN_CFG_UPD BIT(6)
> +
> +/* IMG_EFF_CTRL */
> +#define CIF_IMG_EFF_CTRL_ENABLE BIT(0)
> +#define CIF_IMG_EFF_CTRL_MODE_BLACKWHITE (0 << 1)
> +#define CIF_IMG_EFF_CTRL_MODE_NEGATIVE (1 << 1)
> +#define CIF_IMG_EFF_CTRL_MODE_SEPIA (2 << 1)
> +#define CIF_IMG_EFF_CTRL_MODE_COLOR_SEL (3 << 1)
> +#define CIF_IMG_EFF_CTRL_MODE_EMBOSS (4 << 1)
> +#define CIF_IMG_EFF_CTRL_MODE_SKETCH (5 << 1)
> +#define CIF_IMG_EFF_CTRL_MODE_SHARPEN (6 << 1)
> +#define CIF_IMG_EFF_CTRL_CFG_UPD BIT(4)
> +#define CIF_IMG_EFF_CTRL_YCBCR_FULL BIT(5)
> +
> +#define CIF_IMG_EFF_CTRL_MODE_BLACKWHITE_SHIFT 0
> +#define CIF_IMG_EFF_CTRL_MODE_NEGATIVE_SHIFT 1
> +#define CIF_IMG_EFF_CTRL_MODE_SEPIA_SHIFT 2
> +#define CIF_IMG_EFF_CTRL_MODE_COLOR_SEL_SHIFT 3
> +#define CIF_IMG_EFF_CTRL_MODE_EMBOSS_SHIFT 4
> +#define CIF_IMG_EFF_CTRL_MODE_SKETCH_SHIFT 5
> +#define CIF_IMG_EFF_CTRL_MODE_SHARPEN_SHIFT 6
> +#define CIF_IMG_EFF_CTRL_MODE_MASK 0xE
> +
> +/* IMG_EFF_COLOR_SEL */
> +#define CIF_IMG_EFF_COLOR_RGB 0
> +#define CIF_IMG_EFF_COLOR_B (1 << 0)
> +#define CIF_IMG_EFF_COLOR_G (2 << 0)
> +#define CIF_IMG_EFF_COLOR_GB (3 << 0)
> +#define CIF_IMG_EFF_COLOR_R (4 << 0)
> +#define CIF_IMG_EFF_COLOR_RB (5 << 0)
> +#define CIF_IMG_EFF_COLOR_RG (6 << 0)
> +#define CIF_IMG_EFF_COLOR_RGB2 (7 << 0)
> +
> +/* MIPI_CTRL */
> +#define CIF_MIPI_CTRL_OUTPUT_ENA BIT(0)
> +#define CIF_MIPI_CTRL_SHUTDOWNLANES(a) (((a) & 0xF) << 8)
> +#define CIF_MIPI_CTRL_NUM_LANES(a) (((a) & 0x3) << 12)
> +#define CIF_MIPI_CTRL_ERR_SOT_HS_SKIP BIT(16)
> +#define CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP BIT(17)
> +#define CIF_MIPI_CTRL_CLOCKLANE_ENA BIT(18)
> +
> +/* MIPI_DATA_SEL */
> +#define CIF_MIPI_DATA_SEL_VC(a) (((a) & 0x3) << 6)
> +#define CIF_MIPI_DATA_SEL_DT(a) (((a) & 0x3F) << 0)
> +/* MIPI DATA_TYPE */
> +#define CIF_CSI2_DT_YUV420_8b 0x18
> +#define CIF_CSI2_DT_YUV420_10b 0x19
> +#define CIF_CSI2_DT_YUV422_8b 0x1E
> +#define CIF_CSI2_DT_YUV422_10b 0x1F
> +#define CIF_CSI2_DT_RGB565 0x22
> +#define CIF_CSI2_DT_RGB666 0x23
> +#define CIF_CSI2_DT_RGB888 0x24
> +#define CIF_CSI2_DT_RAW8 0x2A
> +#define CIF_CSI2_DT_RAW10 0x2B
> +#define CIF_CSI2_DT_RAW12 0x2C
> +
> +/* MIPI_IMSC, MIPI_RIS, MIPI_MIS, MIPI_ICR, MIPI_ISR */
> +#define CIF_MIPI_SYNC_FIFO_OVFLW(a) (((a) & 0xF) << 0)
> +#define CIF_MIPI_ERR_SOT(a) (((a) & 0xF) << 4)
> +#define CIF_MIPI_ERR_SOT_SYNC(a) (((a) & 0xF) << 8)
> +#define CIF_MIPI_ERR_EOT_SYNC(a) (((a) & 0xF) << 12)
> +#define CIF_MIPI_ERR_CTRL(a) (((a) & 0xF) << 16)
> +#define CIF_MIPI_ERR_PROTOCOL BIT(20)
> +#define CIF_MIPI_ERR_ECC1 BIT(21)
> +#define CIF_MIPI_ERR_ECC2 BIT(22)
> +#define CIF_MIPI_ERR_CS BIT(23)
> +#define CIF_MIPI_FRAME_END BIT(24)
> +#define CIF_MIPI_ADD_DATA_OVFLW BIT(25)
> +#define CIF_MIPI_ADD_DATA_WATER_MARK BIT(26)
> +
> +#define CIF_MIPI_ERR_CSI (CIF_MIPI_ERR_PROTOCOL | \
> + CIF_MIPI_ERR_ECC1 | \
> + CIF_MIPI_ERR_ECC2 | \
> + CIF_MIPI_ERR_CS)
> +
> +#define CIF_MIPI_ERR_DPHY (CIF_MIPI_ERR_SOT(3) | \
> + CIF_MIPI_ERR_SOT_SYNC(3) | \
> + CIF_MIPI_ERR_EOT_SYNC(3) | \
> + CIF_MIPI_ERR_CTRL(3))
> +
> +/* SUPER_IMPOSE */
> +#define CIF_SUPER_IMP_CTRL_NORMAL_MODE BIT(0)
> +#define CIF_SUPER_IMP_CTRL_REF_IMG_MEM BIT(1)
> +#define CIF_SUPER_IMP_CTRL_TRANSP_DIS BIT(2)
> +
> +/* ISP HISTOGRAM CALCULATION : ISP_HIST_PROP */
> +#define CIF_ISP_HIST_PROP_MODE_DIS (0 << 0)
> +#define CIF_ISP_HIST_PROP_MODE_RGB (1 << 0)
> +#define CIF_ISP_HIST_PROP_MODE_RED (2 << 0)
> +#define CIF_ISP_HIST_PROP_MODE_GREEN (3 << 0)
> +#define CIF_ISP_HIST_PROP_MODE_BLUE (4 << 0)
> +#define CIF_ISP_HIST_PROP_MODE_LUM (5 << 0)
> +#define CIF_ISP_HIST_PROP_MODE_MASK 0x7
> +#define CIF_ISP_HIST_PREDIV_SET(x) (((x) & 0x7F) << 3)
> +#define CIF_ISP_HIST_WEIGHT_SET(v0, v1, v2, v3) \
> + (((v0) & 0x1F) | (((v1) & 0x1F) << 8) |\
> + (((v2) & 0x1F) << 16) | \
> + (((v3) & 0x1F) << 24))
> +
> +#define CIF_ISP_HIST_WINDOW_OFFSET_RESERVED 0xFFFFF000
> +#define CIF_ISP_HIST_WINDOW_SIZE_RESERVED 0xFFFFF800
> +#define CIF_ISP_HIST_WEIGHT_RESERVED 0xE0E0E0E0
> +#define CIF_ISP_MAX_HIST_PREDIVIDER 0x0000007F
> +#define CIF_ISP_HIST_ROW_NUM 5
> +#define CIF_ISP_HIST_COLUMN_NUM 5
> +
> +/* AUTO FOCUS MEASUREMENT: ISP_AFM_CTRL */
> +#define ISP_AFM_CTRL_ENABLE BIT(0)
> +
> +/* SHUTTER CONTROL */
> +#define CIF_ISP_SH_CTRL_SH_ENA BIT(0)
> +#define CIF_ISP_SH_CTRL_REP_EN BIT(1)
> +#define CIF_ISP_SH_CTRL_SRC_SH_TRIG BIT(2)
> +#define CIF_ISP_SH_CTRL_EDGE_POS BIT(3)
> +#define CIF_ISP_SH_CTRL_POL_LOW BIT(4)
> +
> +/* FLASH MODULE */
> +/* ISP_FLASH_CMD */
> +#define CIF_FLASH_CMD_PRELIGHT_ON BIT(0)
> +#define CIF_FLASH_CMD_FLASH_ON BIT(1)
> +#define CIF_FLASH_CMD_PRE_FLASH_ON BIT(2)
> +/* ISP_FLASH_CONFIG */
> +#define CIF_FLASH_CONFIG_PRELIGHT_END BIT(0)
> +#define CIF_FLASH_CONFIG_VSYNC_POS BIT(1)
> +#define CIF_FLASH_CONFIG_PRELIGHT_LOW BIT(2)
> +#define CIF_FLASH_CONFIG_SRC_FL_TRIG BIT(3)
> +#define CIF_FLASH_CONFIG_DELAY(a) (((a) & 0xF) << 4)
> +
> +/* Demosaic: ISP_DEMOSAIC */
> +#define CIF_ISP_DEMOSAIC_BYPASS BIT(10)
> +#define CIF_ISP_DEMOSAIC_TH(x) ((x) & 0xFF)
> +
> +/* AWB */
> +/* ISP_AWB_PROP */
> +#define CIF_ISP_AWB_YMAX_CMP_EN BIT(2)
> +#define CIFISP_AWB_YMAX_READ(x) (((x) >> 2) & 1)
> +#define CIF_ISP_AWB_MODE_RGB_EN ((1 << 31) | (0x2 << 0))
> +#define CIF_ISP_AWB_MODE_YCBCR_EN ((0 << 31) | (0x2 << 0))
> +#define CIF_ISP_AWB_MODE_YCBCR_EN ((0 << 31) | (0x2 << 0))
> +#define CIF_ISP_AWB_MODE_MASK_NONE 0xFFFFFFFC
> +#define CIF_ISP_AWB_MODE_READ(x) ((x) & 3)
> +/* ISP_AWB_GAIN_RB, ISP_AWB_GAIN_G */
> +#define CIF_ISP_AWB_GAIN_R_SET(x) (((x) & 0x3FF) << 16)
> +#define CIF_ISP_AWB_GAIN_R_READ(x) (((x) >> 16) & 0x3FF)
> +#define CIF_ISP_AWB_GAIN_B_SET(x) ((x) & 0x3FFF)
> +#define CIF_ISP_AWB_GAIN_B_READ(x) ((x) & 0x3FFF)
> +/* ISP_AWB_REF */
> +#define CIF_ISP_AWB_REF_CR_SET(x) (((x) & 0xFF) << 8)
> +#define CIF_ISP_AWB_REF_CR_READ(x) (((x) >> 8) & 0xFF)
> +#define CIF_ISP_AWB_REF_CB_READ(x) ((x) & 0xFF)
> +/* ISP_AWB_THRESH */
> +#define CIF_ISP_AWB_MAX_CS_SET(x) (((x) & 0xFF) << 8)
> +#define CIF_ISP_AWB_MAX_CS_READ(x) (((x) >> 8) & 0xFF)
> +#define CIF_ISP_AWB_MIN_C_READ(x) ((x) & 0xFF)
> +#define CIF_ISP_AWB_MIN_Y_SET(x) (((x) & 0xFF) << 16)
> +#define CIF_ISP_AWB_MIN_Y_READ(x) (((x) >> 16) & 0xFF)
> +#define CIF_ISP_AWB_MAX_Y_SET(x) (((x) & 0xFF) << 24)
> +#define CIF_ISP_AWB_MAX_Y_READ(x) (((x) >> 24) & 0xFF)
> +/* ISP_AWB_MEAN */
> +#define CIF_ISP_AWB_GET_MEAN_CR_R(x) ((x) & 0xFF)
> +#define CIF_ISP_AWB_GET_MEAN_CB_B(x) (((x) >> 8) & 0xFF)
> +#define CIF_ISP_AWB_GET_MEAN_Y_G(x) (((x) >> 16) & 0xFF)
> +/* ISP_AWB_WHITE_CNT */
> +#define CIF_ISP_AWB_GET_PIXEL_CNT(x) ((x) & 0x3FFFFFF)
> +
> +#define CIF_ISP_AWB_GAINS_MAX_VAL 0x000003FF
> +#define CIF_ISP_AWB_WINDOW_OFFSET_MAX 0x00000FFF
> +#define CIF_ISP_AWB_WINDOW_MAX_SIZE 0x00001FFF
> +#define CIF_ISP_AWB_CBCR_MAX_REF 0x000000FF
> +#define CIF_ISP_AWB_THRES_MAX_YC 0x000000FF
> +
> +/* AE */
> +/* ISP_EXP_CTRL */
> +#define CIF_ISP_EXP_ENA BIT(0)
> +#define CIF_ISP_EXP_CTRL_AUTOSTOP BIT(1)
> +/*
> + *'1' luminance calculation according to Y=(R+G+B) x 0.332 (85/256)
> + *'0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B
> + */
> +#define CIF_ISP_EXP_CTRL_MEASMODE_1 BIT(31)
> +
> +/* ISP_EXP_H_SIZE */
> +#define CIF_ISP_EXP_H_SIZE_SET(x) ((x) & 0x7FF)
> +#define CIF_ISP_EXP_HEIGHT_MASK 0x000007FF
> +/* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */
> +#define CIF_ISP_EXP_V_SIZE_SET(x) ((x) & 0x7FE)
> +
> +/* ISP_EXP_H_OFFSET */
> +#define CIF_ISP_EXP_H_OFFSET_SET(x) ((x) & 0x1FFF)
> +#define CIF_ISP_EXP_MAX_HOFFS 2424
> +/* ISP_EXP_V_OFFSET */
> +#define CIF_ISP_EXP_V_OFFSET_SET(x) ((x) & 0x1FFF)
> +#define CIF_ISP_EXP_MAX_VOFFS 1806
> +
> +#define CIF_ISP_EXP_ROW_NUM 5
> +#define CIF_ISP_EXP_COLUMN_NUM 5
> +#define CIF_ISP_EXP_NUM_LUMA_REGS \
> + (CIF_ISP_EXP_ROW_NUM * CIF_ISP_EXP_COLUMN_NUM)
> +#define CIF_ISP_EXP_BLOCK_MAX_HSIZE 516
> +#define CIF_ISP_EXP_BLOCK_MIN_HSIZE 35
> +#define CIF_ISP_EXP_BLOCK_MAX_VSIZE 390
> +#define CIF_ISP_EXP_BLOCK_MIN_VSIZE 28
> +#define CIF_ISP_EXP_MAX_HSIZE \
> + (CIF_ISP_EXP_BLOCK_MAX_HSIZE * CIF_ISP_EXP_COLUMN_NUM + 1)
> +#define CIF_ISP_EXP_MIN_HSIZE \
> + (CIF_ISP_EXP_BLOCK_MIN_HSIZE * CIF_ISP_EXP_COLUMN_NUM + 1)
> +#define CIF_ISP_EXP_MAX_VSIZE \
> + (CIF_ISP_EXP_BLOCK_MAX_VSIZE * CIF_ISP_EXP_ROW_NUM + 1)
> +#define CIF_ISP_EXP_MIN_VSIZE \
> + (CIF_ISP_EXP_BLOCK_MIN_VSIZE * CIF_ISP_EXP_ROW_NUM + 1)
> +
> +/* LSC: ISP_LSC_CTRL */
> +#define CIF_ISP_LSC_CTRL_ENA BIT(0)
> +#define CIF_ISP_LSC_SECT_SIZE_RESERVED 0xFC00FC00
> +#define CIF_ISP_LSC_GRAD_RESERVED 0xF000F000
> +#define CIF_ISP_LSC_SAMPLE_RESERVED 0xF000F000
> +#define CIF_ISP_LSC_SECTORS_MAX 16
> +#define CIF_ISP_LSC_TABLE_DATA(v0, v1) \
> + (((v0) & 0xFFF) | (((v1) & 0xFFF) << 12))
> +#define CIF_ISP_LSC_SECT_SIZE(v0, v1) \
> + (((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
> +#define CIF_ISP_LSC_GRAD_SIZE(v0, v1) \
> + (((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
> +
> +/* LSC: ISP_LSC_TABLE_SEL */
> +#define CIF_ISP_LSC_TABLE_0 0
> +#define CIF_ISP_LSC_TABLE_1 1
> +
> +/* LSC: ISP_LSC_STATUS */
> +#define CIF_ISP_LSC_ACTIVE_TABLE BIT(1)
> +#define CIF_ISP_LSC_TABLE_ADDRESS_0 0
> +#define CIF_ISP_LSC_TABLE_ADDRESS_153 153
> +
> +/* FLT */
> +/* ISP_FILT_MODE */
> +#define CIF_ISP_FLT_ENA BIT(0)
> +
> +/*
> + * 0: green filter static mode (active filter factor = FILT_FAC_MID)
> + * 1: dynamic noise reduction/sharpen Default
> + */
> +#define CIF_ISP_FLT_MODE_DNR BIT(1)
> +#define CIF_ISP_FLT_MODE_MAX 1
> +#define CIF_ISP_FLT_CHROMA_V_MODE(x) (((x) & 0x3) << 4)
> +#define CIF_ISP_FLT_CHROMA_H_MODE(x) (((x) & 0x3) << 6)
> +#define CIF_ISP_FLT_CHROMA_MODE_MAX 3
> +#define CIF_ISP_FLT_GREEN_STAGE1(x) (((x) & 0xF) << 8)
> +#define CIF_ISP_FLT_GREEN_STAGE1_MAX 8
> +#define CIF_ISP_FLT_THREAD_RESERVED 0xFFFFFC00
> +#define CIF_ISP_FLT_FAC_RESERVED 0xFFFFFFC0
> +#define CIF_ISP_FLT_LUM_WEIGHT_RESERVED 0xFFF80000
> +
> +#define CIF_ISP_CTK_COEFF_RESERVED 0xFFFFF800
> +#define CIF_ISP_XTALK_OFFSET_RESERVED 0xFFFFF000
> +
> +/* GOC */
> +#define CIF_ISP_GAMMA_OUT_MODE_EQU BIT(0)
> +#define CIF_ISP_GOC_MODE_MAX 1
> +#define CIF_ISP_GOC_RESERVED 0xFFFFF800
> +/* ISP_CTRL BIT 11*/
> +#define CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA_READ(x) (((x) >> 11) & 1)
> +
> +/* DPCC */
> +/* ISP_DPCC_MODE */
> +#define CIF_ISP_DPCC_ENA BIT(0)
> +#define CIF_ISP_DPCC_MODE_MAX 0x07
> +#define CIF_ISP_DPCC_OUTPUTMODE_MAX 0x0F
> +#define CIF_ISP_DPCC_SETUSE_MAX 0x0F
> +#define CIF_ISP_DPCC_METHODS_SET_RESERVED 0xFFFFE000
> +#define CIF_ISP_DPCC_LINE_THRESH_RESERVED 0xFFFF0000
> +#define CIF_ISP_DPCC_LINE_MAD_FAC_RESERVED 0xFFFFC0C0
> +#define CIF_ISP_DPCC_PG_FAC_RESERVED 0xFFFFC0C0
> +#define CIF_ISP_DPCC_RND_THRESH_RESERVED 0xFFFF0000
> +#define CIF_ISP_DPCC_RG_FAC_RESERVED 0xFFFFC0C0
> +#define CIF_ISP_DPCC_RO_LIMIT_RESERVED 0xFFFFF000
> +#define CIF_ISP_DPCC_RND_OFFS_RESERVED 0xFFFFF000
> +
> +/* BLS */
> +/* ISP_BLS_CTRL */
> +#define CIF_ISP_BLS_ENA BIT(0)
> +#define CIF_ISP_BLS_MODE_MEASURED BIT(1)
> +#define CIF_ISP_BLS_MODE_FIXED 0
> +#define CIF_ISP_BLS_WINDOW_1 (1 << 2)
> +#define CIF_ISP_BLS_WINDOW_2 (2 << 2)
> +
> +/* GAMMA-IN */
> +#define CIFISP_DEGAMMA_X_RESERVED \
> + ((1 << 31) | (1 << 27) | (1 << 23) | (1 << 19) |\
> + (1 << 15) | (1 << 11) | (1 << 7) | (1 << 3))
> +#define CIFISP_DEGAMMA_Y_RESERVED 0xFFFFF000
> +
> +/* AFM */
> +#define CIF_ISP_AFM_ENA BIT(0)
> +#define CIF_ISP_AFM_THRES_RESERVED 0xFFFF0000
> +#define CIF_ISP_AFM_VAR_SHIFT_RESERVED 0xFFF8FFF8
> +#define CIF_ISP_AFM_WINDOW_X_RESERVED 0xE000
> +#define CIF_ISP_AFM_WINDOW_Y_RESERVED 0xF000
> +#define CIF_ISP_AFM_WINDOW_X_MIN 0x5
> +#define CIF_ISP_AFM_WINDOW_Y_MIN 0x2
> +#define CIF_ISP_AFM_WINDOW_X(x) (((x) & 0x1FFF) << 16)
> +#define CIF_ISP_AFM_WINDOW_Y(x) ((x) & 0x1FFF)
> +
> +/* DPF */
> +#define CIF_ISP_DPF_MODE_EN BIT(0)
> +#define CIF_ISP_DPF_MODE_B_FLT_DIS BIT(1)
> +#define CIF_ISP_DPF_MODE_GB_FLT_DIS BIT(2)
> +#define CIF_ISP_DPF_MODE_GR_FLT_DIS BIT(3)
> +#define CIF_ISP_DPF_MODE_R_FLT_DIS BIT(4)
> +#define CIF_ISP_DPF_MODE_RB_FLTSIZE_9x9 BIT(5)
> +#define CIF_ISP_DPF_MODE_NLL_SEGMENTATION BIT(6)
> +#define CIF_ISP_DPF_MODE_AWB_GAIN_COMP BIT(7)
> +#define CIF_ISP_DPF_MODE_LSC_GAIN_COMP BIT(8)
> +#define CIF_ISP_DPF_MODE_USE_NF_GAIN BIT(9)
> +#define CIF_ISP_DPF_NF_GAIN_RESERVED 0xFFFFF000
> +#define CIF_ISP_DPF_SPATIAL_COEFF_MAX 0x1F
> +#define CIF_ISP_DPF_NLL_COEFF_N_MAX 0x3FF
> +
> +/* =================================================================== */
> +/* CIF Registers */
> +/* =================================================================== */
> +#define CIF_CTRL_BASE 0x00000000
> +#define CIF_CCL (CIF_CTRL_BASE + 0x00000000)
> +#define CIF_VI_ID (CIF_CTRL_BASE + 0x00000008)
> +#define CIF_ICCL (CIF_CTRL_BASE + 0x00000010)
> +#define CIF_IRCL (CIF_CTRL_BASE + 0x00000014)
> +#define CIF_VI_DPCL (CIF_CTRL_BASE + 0x00000018)
> +
> +#define CIF_IMG_EFF_BASE 0x00000200
> +#define CIF_IMG_EFF_CTRL (CIF_IMG_EFF_BASE + 0x00000000)
> +#define CIF_IMG_EFF_COLOR_SEL (CIF_IMG_EFF_BASE + 0x00000004)
> +#define CIF_IMG_EFF_MAT_1 (CIF_IMG_EFF_BASE + 0x00000008)
> +#define CIF_IMG_EFF_MAT_2 (CIF_IMG_EFF_BASE + 0x0000000C)
> +#define CIF_IMG_EFF_MAT_3 (CIF_IMG_EFF_BASE + 0x00000010)
> +#define CIF_IMG_EFF_MAT_4 (CIF_IMG_EFF_BASE + 0x00000014)
> +#define CIF_IMG_EFF_MAT_5 (CIF_IMG_EFF_BASE + 0x00000018)
> +#define CIF_IMG_EFF_TINT (CIF_IMG_EFF_BASE + 0x0000001C)
> +#define CIF_IMG_EFF_CTRL_SHD (CIF_IMG_EFF_BASE + 0x00000020)
> +#define CIF_IMG_EFF_SHARPEN (CIF_IMG_EFF_BASE + 0x00000024)
> +
> +#define CIF_SUPER_IMP_BASE 0x00000300
> +#define CIF_SUPER_IMP_CTRL (CIF_SUPER_IMP_BASE + 0x00000000)
> +#define CIF_SUPER_IMP_OFFSET_X (CIF_SUPER_IMP_BASE + 0x00000004)
> +#define CIF_SUPER_IMP_OFFSET_Y (CIF_SUPER_IMP_BASE + 0x00000008)
> +#define CIF_SUPER_IMP_COLOR_Y (CIF_SUPER_IMP_BASE + 0x0000000C)
> +#define CIF_SUPER_IMP_COLOR_CB (CIF_SUPER_IMP_BASE + 0x00000010)
> +#define CIF_SUPER_IMP_COLOR_CR (CIF_SUPER_IMP_BASE + 0x00000014)
> +
> +#define CIF_ISP_BASE 0x00000400
> +#define CIF_ISP_CTRL (CIF_ISP_BASE + 0x00000000)
> +#define CIF_ISP_ACQ_PROP (CIF_ISP_BASE + 0x00000004)
> +#define CIF_ISP_ACQ_H_OFFS (CIF_ISP_BASE + 0x00000008)
> +#define CIF_ISP_ACQ_V_OFFS (CIF_ISP_BASE + 0x0000000C)
> +#define CIF_ISP_ACQ_H_SIZE (CIF_ISP_BASE + 0x00000010)
> +#define CIF_ISP_ACQ_V_SIZE (CIF_ISP_BASE + 0x00000014)
> +#define CIF_ISP_ACQ_NR_FRAMES (CIF_ISP_BASE + 0x00000018)
> +#define CIF_ISP_GAMMA_DX_LO (CIF_ISP_BASE + 0x0000001C)
> +#define CIF_ISP_GAMMA_DX_HI (CIF_ISP_BASE + 0x00000020)
> +#define CIF_ISP_GAMMA_R_Y0 (CIF_ISP_BASE + 0x00000024)
> +#define CIF_ISP_GAMMA_R_Y1 (CIF_ISP_BASE + 0x00000028)
> +#define CIF_ISP_GAMMA_R_Y2 (CIF_ISP_BASE + 0x0000002C)
> +#define CIF_ISP_GAMMA_R_Y3 (CIF_ISP_BASE + 0x00000030)
> +#define CIF_ISP_GAMMA_R_Y4 (CIF_ISP_BASE + 0x00000034)
> +#define CIF_ISP_GAMMA_R_Y5 (CIF_ISP_BASE + 0x00000038)
> +#define CIF_ISP_GAMMA_R_Y6 (CIF_ISP_BASE + 0x0000003C)
> +#define CIF_ISP_GAMMA_R_Y7 (CIF_ISP_BASE + 0x00000040)
> +#define CIF_ISP_GAMMA_R_Y8 (CIF_ISP_BASE + 0x00000044)
> +#define CIF_ISP_GAMMA_R_Y9 (CIF_ISP_BASE + 0x00000048)
> +#define CIF_ISP_GAMMA_R_Y10 (CIF_ISP_BASE + 0x0000004C)
> +#define CIF_ISP_GAMMA_R_Y11 (CIF_ISP_BASE + 0x00000050)
> +#define CIF_ISP_GAMMA_R_Y12 (CIF_ISP_BASE + 0x00000054)
> +#define CIF_ISP_GAMMA_R_Y13 (CIF_ISP_BASE + 0x00000058)
> +#define CIF_ISP_GAMMA_R_Y14 (CIF_ISP_BASE + 0x0000005C)
> +#define CIF_ISP_GAMMA_R_Y15 (CIF_ISP_BASE + 0x00000060)
> +#define CIF_ISP_GAMMA_R_Y16 (CIF_ISP_BASE + 0x00000064)
> +#define CIF_ISP_GAMMA_G_Y0 (CIF_ISP_BASE + 0x00000068)
> +#define CIF_ISP_GAMMA_G_Y1 (CIF_ISP_BASE + 0x0000006C)
> +#define CIF_ISP_GAMMA_G_Y2 (CIF_ISP_BASE + 0x00000070)
> +#define CIF_ISP_GAMMA_G_Y3 (CIF_ISP_BASE + 0x00000074)
> +#define CIF_ISP_GAMMA_G_Y4 (CIF_ISP_BASE + 0x00000078)
> +#define CIF_ISP_GAMMA_G_Y5 (CIF_ISP_BASE + 0x0000007C)
> +#define CIF_ISP_GAMMA_G_Y6 (CIF_ISP_BASE + 0x00000080)
> +#define CIF_ISP_GAMMA_G_Y7 (CIF_ISP_BASE + 0x00000084)
> +#define CIF_ISP_GAMMA_G_Y8 (CIF_ISP_BASE + 0x00000088)
> +#define CIF_ISP_GAMMA_G_Y9 (CIF_ISP_BASE + 0x0000008C)
> +#define CIF_ISP_GAMMA_G_Y10 (CIF_ISP_BASE + 0x00000090)
> +#define CIF_ISP_GAMMA_G_Y11 (CIF_ISP_BASE + 0x00000094)
> +#define CIF_ISP_GAMMA_G_Y12 (CIF_ISP_BASE + 0x00000098)
> +#define CIF_ISP_GAMMA_G_Y13 (CIF_ISP_BASE + 0x0000009C)
> +#define CIF_ISP_GAMMA_G_Y14 (CIF_ISP_BASE + 0x000000A0)
> +#define CIF_ISP_GAMMA_G_Y15 (CIF_ISP_BASE + 0x000000A4)
> +#define CIF_ISP_GAMMA_G_Y16 (CIF_ISP_BASE + 0x000000A8)
> +#define CIF_ISP_GAMMA_B_Y0 (CIF_ISP_BASE + 0x000000AC)
> +#define CIF_ISP_GAMMA_B_Y1 (CIF_ISP_BASE + 0x000000B0)
> +#define CIF_ISP_GAMMA_B_Y2 (CIF_ISP_BASE + 0x000000B4)
> +#define CIF_ISP_GAMMA_B_Y3 (CIF_ISP_BASE + 0x000000B8)
> +#define CIF_ISP_GAMMA_B_Y4 (CIF_ISP_BASE + 0x000000BC)
> +#define CIF_ISP_GAMMA_B_Y5 (CIF_ISP_BASE + 0x000000C0)
> +#define CIF_ISP_GAMMA_B_Y6 (CIF_ISP_BASE + 0x000000C4)
> +#define CIF_ISP_GAMMA_B_Y7 (CIF_ISP_BASE + 0x000000C8)
> +#define CIF_ISP_GAMMA_B_Y8 (CIF_ISP_BASE + 0x000000CC)
> +#define CIF_ISP_GAMMA_B_Y9 (CIF_ISP_BASE + 0x000000D0)
> +#define CIF_ISP_GAMMA_B_Y10 (CIF_ISP_BASE + 0x000000D4)
> +#define CIF_ISP_GAMMA_B_Y11 (CIF_ISP_BASE + 0x000000D8)
> +#define CIF_ISP_GAMMA_B_Y12 (CIF_ISP_BASE + 0x000000DC)
> +#define CIF_ISP_GAMMA_B_Y13 (CIF_ISP_BASE + 0x000000E0)
> +#define CIF_ISP_GAMMA_B_Y14 (CIF_ISP_BASE + 0x000000E4)
> +#define CIF_ISP_GAMMA_B_Y15 (CIF_ISP_BASE + 0x000000E8)
> +#define CIF_ISP_GAMMA_B_Y16 (CIF_ISP_BASE + 0x000000EC)
> +#define CIF_ISP_AWB_PROP (CIF_ISP_BASE + 0x00000110)
> +#define CIF_ISP_AWB_WND_H_OFFS (CIF_ISP_BASE + 0x00000114)
> +#define CIF_ISP_AWB_WND_V_OFFS (CIF_ISP_BASE + 0x00000118)
> +#define CIF_ISP_AWB_WND_H_SIZE (CIF_ISP_BASE + 0x0000011C)
> +#define CIF_ISP_AWB_WND_V_SIZE (CIF_ISP_BASE + 0x00000120)
> +#define CIF_ISP_AWB_FRAMES (CIF_ISP_BASE + 0x00000124)
> +#define CIF_ISP_AWB_REF (CIF_ISP_BASE + 0x00000128)
> +#define CIF_ISP_AWB_THRESH (CIF_ISP_BASE + 0x0000012C)
> +#define CIF_ISP_AWB_GAIN_G (CIF_ISP_BASE + 0x00000138)
> +#define CIF_ISP_AWB_GAIN_RB (CIF_ISP_BASE + 0x0000013C)
> +#define CIF_ISP_AWB_WHITE_CNT (CIF_ISP_BASE + 0x00000140)
> +#define CIF_ISP_AWB_MEAN (CIF_ISP_BASE + 0x00000144)
> +#define CIF_ISP_CC_COEFF_0 (CIF_ISP_BASE + 0x00000170)
> +#define CIF_ISP_CC_COEFF_1 (CIF_ISP_BASE + 0x00000174)
> +#define CIF_ISP_CC_COEFF_2 (CIF_ISP_BASE + 0x00000178)
> +#define CIF_ISP_CC_COEFF_3 (CIF_ISP_BASE + 0x0000017C)
> +#define CIF_ISP_CC_COEFF_4 (CIF_ISP_BASE + 0x00000180)
> +#define CIF_ISP_CC_COEFF_5 (CIF_ISP_BASE + 0x00000184)
> +#define CIF_ISP_CC_COEFF_6 (CIF_ISP_BASE + 0x00000188)
> +#define CIF_ISP_CC_COEFF_7 (CIF_ISP_BASE + 0x0000018C)
> +#define CIF_ISP_CC_COEFF_8 (CIF_ISP_BASE + 0x00000190)
> +#define CIF_ISP_OUT_H_OFFS (CIF_ISP_BASE + 0x00000194)
> +#define CIF_ISP_OUT_V_OFFS (CIF_ISP_BASE + 0x00000198)
> +#define CIF_ISP_OUT_H_SIZE (CIF_ISP_BASE + 0x0000019C)
> +#define CIF_ISP_OUT_V_SIZE (CIF_ISP_BASE + 0x000001A0)
> +#define CIF_ISP_DEMOSAIC (CIF_ISP_BASE + 0x000001A4)
> +#define CIF_ISP_FLAGS_SHD (CIF_ISP_BASE + 0x000001A8)
> +#define CIF_ISP_OUT_H_OFFS_SHD (CIF_ISP_BASE + 0x000001AC)
> +#define CIF_ISP_OUT_V_OFFS_SHD (CIF_ISP_BASE + 0x000001B0)
> +#define CIF_ISP_OUT_H_SIZE_SHD (CIF_ISP_BASE + 0x000001B4)
> +#define CIF_ISP_OUT_V_SIZE_SHD (CIF_ISP_BASE + 0x000001B8)
> +#define CIF_ISP_IMSC (CIF_ISP_BASE + 0x000001BC)
> +#define CIF_ISP_RIS (CIF_ISP_BASE + 0x000001C0)
> +#define CIF_ISP_MIS (CIF_ISP_BASE + 0x000001C4)
> +#define CIF_ISP_ICR (CIF_ISP_BASE + 0x000001C8)
> +#define CIF_ISP_ISR (CIF_ISP_BASE + 0x000001CC)
> +#define CIF_ISP_CT_COEFF_0 (CIF_ISP_BASE + 0x000001D0)
> +#define CIF_ISP_CT_COEFF_1 (CIF_ISP_BASE + 0x000001D4)
> +#define CIF_ISP_CT_COEFF_2 (CIF_ISP_BASE + 0x000001D8)
> +#define CIF_ISP_CT_COEFF_3 (CIF_ISP_BASE + 0x000001DC)
> +#define CIF_ISP_CT_COEFF_4 (CIF_ISP_BASE + 0x000001E0)
> +#define CIF_ISP_CT_COEFF_5 (CIF_ISP_BASE + 0x000001E4)
> +#define CIF_ISP_CT_COEFF_6 (CIF_ISP_BASE + 0x000001E8)
> +#define CIF_ISP_CT_COEFF_7 (CIF_ISP_BASE + 0x000001EC)
> +#define CIF_ISP_CT_COEFF_8 (CIF_ISP_BASE + 0x000001F0)
> +#define CIF_ISP_GAMMA_OUT_MODE (CIF_ISP_BASE + 0x000001F4)
> +#define CIF_ISP_GAMMA_OUT_Y_0 (CIF_ISP_BASE + 0x000001F8)
> +#define CIF_ISP_GAMMA_OUT_Y_1 (CIF_ISP_BASE + 0x000001FC)
> +#define CIF_ISP_GAMMA_OUT_Y_2 (CIF_ISP_BASE + 0x00000200)
> +#define CIF_ISP_GAMMA_OUT_Y_3 (CIF_ISP_BASE + 0x00000204)
> +#define CIF_ISP_GAMMA_OUT_Y_4 (CIF_ISP_BASE + 0x00000208)
> +#define CIF_ISP_GAMMA_OUT_Y_5 (CIF_ISP_BASE + 0x0000020C)
> +#define CIF_ISP_GAMMA_OUT_Y_6 (CIF_ISP_BASE + 0x00000210)
> +#define CIF_ISP_GAMMA_OUT_Y_7 (CIF_ISP_BASE + 0x00000214)
> +#define CIF_ISP_GAMMA_OUT_Y_8 (CIF_ISP_BASE + 0x00000218)
> +#define CIF_ISP_GAMMA_OUT_Y_9 (CIF_ISP_BASE + 0x0000021C)
> +#define CIF_ISP_GAMMA_OUT_Y_10 (CIF_ISP_BASE + 0x00000220)
> +#define CIF_ISP_GAMMA_OUT_Y_11 (CIF_ISP_BASE + 0x00000224)
> +#define CIF_ISP_GAMMA_OUT_Y_12 (CIF_ISP_BASE + 0x00000228)
> +#define CIF_ISP_GAMMA_OUT_Y_13 (CIF_ISP_BASE + 0x0000022C)
> +#define CIF_ISP_GAMMA_OUT_Y_14 (CIF_ISP_BASE + 0x00000230)
> +#define CIF_ISP_GAMMA_OUT_Y_15 (CIF_ISP_BASE + 0x00000234)
> +#define CIF_ISP_GAMMA_OUT_Y_16 (CIF_ISP_BASE + 0x00000238)
> +#define CIF_ISP_ERR (CIF_ISP_BASE + 0x0000023C)
> +#define CIF_ISP_ERR_CLR (CIF_ISP_BASE + 0x00000240)
> +#define CIF_ISP_FRAME_COUNT (CIF_ISP_BASE + 0x00000244)
> +#define CIF_ISP_CT_OFFSET_R (CIF_ISP_BASE + 0x00000248)
> +#define CIF_ISP_CT_OFFSET_G (CIF_ISP_BASE + 0x0000024C)
> +#define CIF_ISP_CT_OFFSET_B (CIF_ISP_BASE + 0x00000250)
> +
> +#define CIF_ISP_FLASH_BASE 0x00000660
> +#define CIF_ISP_FLASH_CMD (CIF_ISP_FLASH_BASE + 0x00000000)
> +#define CIF_ISP_FLASH_CONFIG (CIF_ISP_FLASH_BASE + 0x00000004)
> +#define CIF_ISP_FLASH_PREDIV (CIF_ISP_FLASH_BASE + 0x00000008)
> +#define CIF_ISP_FLASH_DELAY (CIF_ISP_FLASH_BASE + 0x0000000C)
> +#define CIF_ISP_FLASH_TIME (CIF_ISP_FLASH_BASE + 0x00000010)
> +#define CIF_ISP_FLASH_MAXP (CIF_ISP_FLASH_BASE + 0x00000014)
> +
> +#define CIF_ISP_SH_BASE 0x00000680
> +#define CIF_ISP_SH_CTRL (CIF_ISP_SH_BASE + 0x00000000)
> +#define CIF_ISP_SH_PREDIV (CIF_ISP_SH_BASE + 0x00000004)
> +#define CIF_ISP_SH_DELAY (CIF_ISP_SH_BASE + 0x00000008)
> +#define CIF_ISP_SH_TIME (CIF_ISP_SH_BASE + 0x0000000C)
> +
> +#define CIF_C_PROC_BASE 0x00000800
> +#define CIF_C_PROC_CTRL (CIF_C_PROC_BASE + 0x00000000)
> +#define CIF_C_PROC_CONTRAST (CIF_C_PROC_BASE + 0x00000004)
> +#define CIF_C_PROC_BRIGHTNESS (CIF_C_PROC_BASE + 0x00000008)
> +#define CIF_C_PROC_SATURATION (CIF_C_PROC_BASE + 0x0000000C)
> +#define CIF_C_PROC_HUE (CIF_C_PROC_BASE + 0x00000010)
> +
> +#define CIF_DUAL_CROP_BASE 0x00000880
> +#define CIF_DUAL_CROP_CTRL (CIF_DUAL_CROP_BASE + 0x00000000)
> +#define CIF_DUAL_CROP_M_H_OFFS (CIF_DUAL_CROP_BASE + 0x00000004)
> +#define CIF_DUAL_CROP_M_V_OFFS (CIF_DUAL_CROP_BASE + 0x00000008)
> +#define CIF_DUAL_CROP_M_H_SIZE (CIF_DUAL_CROP_BASE + 0x0000000C)
> +#define CIF_DUAL_CROP_M_V_SIZE (CIF_DUAL_CROP_BASE + 0x00000010)
> +#define CIF_DUAL_CROP_S_H_OFFS (CIF_DUAL_CROP_BASE + 0x00000014)
> +#define CIF_DUAL_CROP_S_V_OFFS (CIF_DUAL_CROP_BASE + 0x00000018)
> +#define CIF_DUAL_CROP_S_H_SIZE (CIF_DUAL_CROP_BASE + 0x0000001C)
> +#define CIF_DUAL_CROP_S_V_SIZE (CIF_DUAL_CROP_BASE + 0x00000020)
> +#define CIF_DUAL_CROP_M_H_OFFS_SHD (CIF_DUAL_CROP_BASE + 0x00000024)
> +#define CIF_DUAL_CROP_M_V_OFFS_SHD (CIF_DUAL_CROP_BASE + 0x00000028)
> +#define CIF_DUAL_CROP_M_H_SIZE_SHD (CIF_DUAL_CROP_BASE + 0x0000002C)
> +#define CIF_DUAL_CROP_M_V_SIZE_SHD (CIF_DUAL_CROP_BASE + 0x00000030)
> +#define CIF_DUAL_CROP_S_H_OFFS_SHD (CIF_DUAL_CROP_BASE + 0x00000034)
> +#define CIF_DUAL_CROP_S_V_OFFS_SHD (CIF_DUAL_CROP_BASE + 0x00000038)
> +#define CIF_DUAL_CROP_S_H_SIZE_SHD (CIF_DUAL_CROP_BASE + 0x0000003C)
> +#define CIF_DUAL_CROP_S_V_SIZE_SHD (CIF_DUAL_CROP_BASE + 0x00000040)
> +
> +#define CIF_MRSZ_BASE 0x00000C00
> +#define CIF_MRSZ_CTRL (CIF_MRSZ_BASE + 0x00000000)
> +#define CIF_MRSZ_SCALE_HY (CIF_MRSZ_BASE + 0x00000004)
> +#define CIF_MRSZ_SCALE_HCB (CIF_MRSZ_BASE + 0x00000008)
> +#define CIF_MRSZ_SCALE_HCR (CIF_MRSZ_BASE + 0x0000000C)
> +#define CIF_MRSZ_SCALE_VY (CIF_MRSZ_BASE + 0x00000010)
> +#define CIF_MRSZ_SCALE_VC (CIF_MRSZ_BASE + 0x00000014)
> +#define CIF_MRSZ_PHASE_HY (CIF_MRSZ_BASE + 0x00000018)
> +#define CIF_MRSZ_PHASE_HC (CIF_MRSZ_BASE + 0x0000001C)
> +#define CIF_MRSZ_PHASE_VY (CIF_MRSZ_BASE + 0x00000020)
> +#define CIF_MRSZ_PHASE_VC (CIF_MRSZ_BASE + 0x00000024)
> +#define CIF_MRSZ_SCALE_LUT_ADDR (CIF_MRSZ_BASE + 0x00000028)
> +#define CIF_MRSZ_SCALE_LUT (CIF_MRSZ_BASE + 0x0000002C)
> +#define CIF_MRSZ_CTRL_SHD (CIF_MRSZ_BASE + 0x00000030)
> +#define CIF_MRSZ_SCALE_HY_SHD (CIF_MRSZ_BASE + 0x00000034)
> +#define CIF_MRSZ_SCALE_HCB_SHD (CIF_MRSZ_BASE + 0x00000038)
> +#define CIF_MRSZ_SCALE_HCR_SHD (CIF_MRSZ_BASE + 0x0000003C)
> +#define CIF_MRSZ_SCALE_VY_SHD (CIF_MRSZ_BASE + 0x00000040)
> +#define CIF_MRSZ_SCALE_VC_SHD (CIF_MRSZ_BASE + 0x00000044)
> +#define CIF_MRSZ_PHASE_HY_SHD (CIF_MRSZ_BASE + 0x00000048)
> +#define CIF_MRSZ_PHASE_HC_SHD (CIF_MRSZ_BASE + 0x0000004C)
> +#define CIF_MRSZ_PHASE_VY_SHD (CIF_MRSZ_BASE + 0x00000050)
> +#define CIF_MRSZ_PHASE_VC_SHD (CIF_MRSZ_BASE + 0x00000054)
> +
> +#define CIF_SRSZ_BASE 0x00001000
> +#define CIF_SRSZ_CTRL (CIF_SRSZ_BASE + 0x00000000)
> +#define CIF_SRSZ_SCALE_HY (CIF_SRSZ_BASE + 0x00000004)
> +#define CIF_SRSZ_SCALE_HCB (CIF_SRSZ_BASE + 0x00000008)
> +#define CIF_SRSZ_SCALE_HCR (CIF_SRSZ_BASE + 0x0000000C)
> +#define CIF_SRSZ_SCALE_VY (CIF_SRSZ_BASE + 0x00000010)
> +#define CIF_SRSZ_SCALE_VC (CIF_SRSZ_BASE + 0x00000014)
> +#define CIF_SRSZ_PHASE_HY (CIF_SRSZ_BASE + 0x00000018)
> +#define CIF_SRSZ_PHASE_HC (CIF_SRSZ_BASE + 0x0000001C)
> +#define CIF_SRSZ_PHASE_VY (CIF_SRSZ_BASE + 0x00000020)
> +#define CIF_SRSZ_PHASE_VC (CIF_SRSZ_BASE + 0x00000024)
> +#define CIF_SRSZ_SCALE_LUT_ADDR (CIF_SRSZ_BASE + 0x00000028)
> +#define CIF_SRSZ_SCALE_LUT (CIF_SRSZ_BASE + 0x0000002C)
> +#define CIF_SRSZ_CTRL_SHD (CIF_SRSZ_BASE + 0x00000030)
> +#define CIF_SRSZ_SCALE_HY_SHD (CIF_SRSZ_BASE + 0x00000034)
> +#define CIF_SRSZ_SCALE_HCB_SHD (CIF_SRSZ_BASE + 0x00000038)
> +#define CIF_SRSZ_SCALE_HCR_SHD (CIF_SRSZ_BASE + 0x0000003C)
> +#define CIF_SRSZ_SCALE_VY_SHD (CIF_SRSZ_BASE + 0x00000040)
> +#define CIF_SRSZ_SCALE_VC_SHD (CIF_SRSZ_BASE + 0x00000044)
> +#define CIF_SRSZ_PHASE_HY_SHD (CIF_SRSZ_BASE + 0x00000048)
> +#define CIF_SRSZ_PHASE_HC_SHD (CIF_SRSZ_BASE + 0x0000004C)
> +#define CIF_SRSZ_PHASE_VY_SHD (CIF_SRSZ_BASE + 0x00000050)
> +#define CIF_SRSZ_PHASE_VC_SHD (CIF_SRSZ_BASE + 0x00000054)
> +
> +#define CIF_MI_BASE 0x00001400
> +#define CIF_MI_CTRL (CIF_MI_BASE + 0x00000000)
> +#define CIF_MI_INIT (CIF_MI_BASE + 0x00000004)
> +#define CIF_MI_MP_Y_BASE_AD_INIT (CIF_MI_BASE + 0x00000008)
> +#define CIF_MI_MP_Y_SIZE_INIT (CIF_MI_BASE + 0x0000000C)
> +#define CIF_MI_MP_Y_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000010)
> +#define CIF_MI_MP_Y_OFFS_CNT_START (CIF_MI_BASE + 0x00000014)
> +#define CIF_MI_MP_Y_IRQ_OFFS_INIT (CIF_MI_BASE + 0x00000018)
> +#define CIF_MI_MP_CB_BASE_AD_INIT (CIF_MI_BASE + 0x0000001C)
> +#define CIF_MI_MP_CB_SIZE_INIT (CIF_MI_BASE + 0x00000020)
> +#define CIF_MI_MP_CB_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000024)
> +#define CIF_MI_MP_CB_OFFS_CNT_START (CIF_MI_BASE + 0x00000028)
> +#define CIF_MI_MP_CR_BASE_AD_INIT (CIF_MI_BASE + 0x0000002C)
> +#define CIF_MI_MP_CR_SIZE_INIT (CIF_MI_BASE + 0x00000030)
> +#define CIF_MI_MP_CR_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000034)
> +#define CIF_MI_MP_CR_OFFS_CNT_START (CIF_MI_BASE + 0x00000038)
> +#define CIF_MI_SP_Y_BASE_AD_INIT (CIF_MI_BASE + 0x0000003C)
> +#define CIF_MI_SP_Y_SIZE_INIT (CIF_MI_BASE + 0x00000040)
> +#define CIF_MI_SP_Y_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000044)
> +#define CIF_MI_SP_Y_OFFS_CNT_START (CIF_MI_BASE + 0x00000048)
> +#define CIF_MI_SP_Y_LLENGTH (CIF_MI_BASE + 0x0000004C)
> +#define CIF_MI_SP_CB_BASE_AD_INIT (CIF_MI_BASE + 0x00000050)
> +#define CIF_MI_SP_CB_SIZE_INIT (CIF_MI_BASE + 0x00000054)
> +#define CIF_MI_SP_CB_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000058)
> +#define CIF_MI_SP_CB_OFFS_CNT_START (CIF_MI_BASE + 0x0000005C)
> +#define CIF_MI_SP_CR_BASE_AD_INIT (CIF_MI_BASE + 0x00000060)
> +#define CIF_MI_SP_CR_SIZE_INIT (CIF_MI_BASE + 0x00000064)
> +#define CIF_MI_SP_CR_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000068)
> +#define CIF_MI_SP_CR_OFFS_CNT_START (CIF_MI_BASE + 0x0000006C)
> +#define CIF_MI_BYTE_CNT (CIF_MI_BASE + 0x00000070)
> +#define CIF_MI_CTRL_SHD (CIF_MI_BASE + 0x00000074)
> +#define CIF_MI_MP_Y_BASE_AD_SHD (CIF_MI_BASE + 0x00000078)
> +#define CIF_MI_MP_Y_SIZE_SHD (CIF_MI_BASE + 0x0000007C)
> +#define CIF_MI_MP_Y_OFFS_CNT_SHD (CIF_MI_BASE + 0x00000080)
> +#define CIF_MI_MP_Y_IRQ_OFFS_SHD (CIF_MI_BASE + 0x00000084)
> +#define CIF_MI_MP_CB_BASE_AD_SHD (CIF_MI_BASE + 0x00000088)
> +#define CIF_MI_MP_CB_SIZE_SHD (CIF_MI_BASE + 0x0000008C)
> +#define CIF_MI_MP_CB_OFFS_CNT_SHD (CIF_MI_BASE + 0x00000090)
> +#define CIF_MI_MP_CR_BASE_AD_SHD (CIF_MI_BASE + 0x00000094)
> +#define CIF_MI_MP_CR_SIZE_SHD (CIF_MI_BASE + 0x00000098)
> +#define CIF_MI_MP_CR_OFFS_CNT_SHD (CIF_MI_BASE + 0x0000009C)
> +#define CIF_MI_SP_Y_BASE_AD_SHD (CIF_MI_BASE + 0x000000A0)
> +#define CIF_MI_SP_Y_SIZE_SHD (CIF_MI_BASE + 0x000000A4)
> +#define CIF_MI_SP_Y_OFFS_CNT_SHD (CIF_MI_BASE + 0x000000A8)
> +#define CIF_MI_SP_CB_BASE_AD_SHD (CIF_MI_BASE + 0x000000B0)
> +#define CIF_MI_SP_CB_SIZE_SHD (CIF_MI_BASE + 0x000000B4)
> +#define CIF_MI_SP_CB_OFFS_CNT_SHD (CIF_MI_BASE + 0x000000B8)
> +#define CIF_MI_SP_CR_BASE_AD_SHD (CIF_MI_BASE + 0x000000BC)
> +#define CIF_MI_SP_CR_SIZE_SHD (CIF_MI_BASE + 0x000000C0)
> +#define CIF_MI_SP_CR_OFFS_CNT_SHD (CIF_MI_BASE + 0x000000C4)
> +#define CIF_MI_DMA_Y_PIC_START_AD (CIF_MI_BASE + 0x000000C8)
> +#define CIF_MI_DMA_Y_PIC_WIDTH (CIF_MI_BASE + 0x000000CC)
> +#define CIF_MI_DMA_Y_LLENGTH (CIF_MI_BASE + 0x000000D0)
> +#define CIF_MI_DMA_Y_PIC_SIZE (CIF_MI_BASE + 0x000000D4)
> +#define CIF_MI_DMA_CB_PIC_START_AD (CIF_MI_BASE + 0x000000D8)
> +#define CIF_MI_DMA_CR_PIC_START_AD (CIF_MI_BASE + 0x000000E8)
> +#define CIF_MI_IMSC (CIF_MI_BASE + 0x000000F8)
> +#define CIF_MI_RIS (CIF_MI_BASE + 0x000000FC)
> +#define CIF_MI_MIS (CIF_MI_BASE + 0x00000100)
> +#define CIF_MI_ICR (CIF_MI_BASE + 0x00000104)
> +#define CIF_MI_ISR (CIF_MI_BASE + 0x00000108)
> +#define CIF_MI_STATUS (CIF_MI_BASE + 0x0000010C)
> +#define CIF_MI_STATUS_CLR (CIF_MI_BASE + 0x00000110)
> +#define CIF_MI_SP_Y_PIC_WIDTH (CIF_MI_BASE + 0x00000114)
> +#define CIF_MI_SP_Y_PIC_HEIGHT (CIF_MI_BASE + 0x00000118)
> +#define CIF_MI_SP_Y_PIC_SIZE (CIF_MI_BASE + 0x0000011C)
> +#define CIF_MI_DMA_CTRL (CIF_MI_BASE + 0x00000120)
> +#define CIF_MI_DMA_START (CIF_MI_BASE + 0x00000124)
> +#define CIF_MI_DMA_STATUS (CIF_MI_BASE + 0x00000128)
> +#define CIF_MI_PIXEL_COUNT (CIF_MI_BASE + 0x0000012C)
> +#define CIF_MI_MP_Y_BASE_AD_INIT2 (CIF_MI_BASE + 0x00000130)
> +#define CIF_MI_MP_CB_BASE_AD_INIT2 (CIF_MI_BASE + 0x00000134)
> +#define CIF_MI_MP_CR_BASE_AD_INIT2 (CIF_MI_BASE + 0x00000138)
> +#define CIF_MI_SP_Y_BASE_AD_INIT2 (CIF_MI_BASE + 0x0000013C)
> +#define CIF_MI_SP_CB_BASE_AD_INIT2 (CIF_MI_BASE + 0x00000140)
> +#define CIF_MI_SP_CR_BASE_AD_INIT2 (CIF_MI_BASE + 0x00000144)
> +#define CIF_MI_XTD_FORMAT_CTRL (CIF_MI_BASE + 0x00000148)
> +
> +#define CIF_SMIA_BASE 0x00001A00
> +#define CIF_SMIA_CTRL (CIF_SMIA_BASE + 0x00000000)
> +#define CIF_SMIA_STATUS (CIF_SMIA_BASE + 0x00000004)
> +#define CIF_SMIA_IMSC (CIF_SMIA_BASE + 0x00000008)
> +#define CIF_SMIA_RIS (CIF_SMIA_BASE + 0x0000000C)
> +#define CIF_SMIA_MIS (CIF_SMIA_BASE + 0x00000010)
> +#define CIF_SMIA_ICR (CIF_SMIA_BASE + 0x00000014)
> +#define CIF_SMIA_ISR (CIF_SMIA_BASE + 0x00000018)
> +#define CIF_SMIA_DATA_FORMAT_SEL (CIF_SMIA_BASE + 0x0000001C)
> +#define CIF_SMIA_SOF_EMB_DATA_LINES (CIF_SMIA_BASE + 0x00000020)
> +#define CIF_SMIA_EMB_HSTART (CIF_SMIA_BASE + 0x00000024)
> +#define CIF_SMIA_EMB_HSIZE (CIF_SMIA_BASE + 0x00000028)
> +#define CIF_SMIA_EMB_VSTART (CIF_SMIA_BASE + 0x0000002c)
> +#define CIF_SMIA_NUM_LINES (CIF_SMIA_BASE + 0x00000030)
> +#define CIF_SMIA_EMB_DATA_FIFO (CIF_SMIA_BASE + 0x00000034)
> +#define CIF_SMIA_EMB_DATA_WATERMARK (CIF_SMIA_BASE + 0x00000038)
> +
> +#define CIF_MIPI_BASE 0x00001C00
> +#define CIF_MIPI_CTRL (CIF_MIPI_BASE + 0x00000000)
> +#define CIF_MIPI_STATUS (CIF_MIPI_BASE + 0x00000004)
> +#define CIF_MIPI_IMSC (CIF_MIPI_BASE + 0x00000008)
> +#define CIF_MIPI_RIS (CIF_MIPI_BASE + 0x0000000C)
> +#define CIF_MIPI_MIS (CIF_MIPI_BASE + 0x00000010)
> +#define CIF_MIPI_ICR (CIF_MIPI_BASE + 0x00000014)
> +#define CIF_MIPI_ISR (CIF_MIPI_BASE + 0x00000018)
> +#define CIF_MIPI_CUR_DATA_ID (CIF_MIPI_BASE + 0x0000001C)
> +#define CIF_MIPI_IMG_DATA_SEL (CIF_MIPI_BASE + 0x00000020)
> +#define CIF_MIPI_ADD_DATA_SEL_1 (CIF_MIPI_BASE + 0x00000024)
> +#define CIF_MIPI_ADD_DATA_SEL_2 (CIF_MIPI_BASE + 0x00000028)
> +#define CIF_MIPI_ADD_DATA_SEL_3 (CIF_MIPI_BASE + 0x0000002C)
> +#define CIF_MIPI_ADD_DATA_SEL_4 (CIF_MIPI_BASE + 0x00000030)
> +#define CIF_MIPI_ADD_DATA_FIFO (CIF_MIPI_BASE + 0x00000034)
> +#define CIF_MIPI_FIFO_FILL_LEVEL (CIF_MIPI_BASE + 0x00000038)
> +#define CIF_MIPI_COMPRESSED_MODE (CIF_MIPI_BASE + 0x0000003C)
> +#define CIF_MIPI_FRAME (CIF_MIPI_BASE + 0x00000040)
> +#define CIF_MIPI_GEN_SHORT_DT (CIF_MIPI_BASE + 0x00000044)
> +#define CIF_MIPI_GEN_SHORT_8_9 (CIF_MIPI_BASE + 0x00000048)
> +#define CIF_MIPI_GEN_SHORT_A_B (CIF_MIPI_BASE + 0x0000004C)
> +#define CIF_MIPI_GEN_SHORT_C_D (CIF_MIPI_BASE + 0x00000050)
> +#define CIF_MIPI_GEN_SHORT_E_F (CIF_MIPI_BASE + 0x00000054)
> +
> +#define CIF_ISP_AFM_BASE 0x00002000
> +#define CIF_ISP_AFM_CTRL (CIF_ISP_AFM_BASE + 0x00000000)
> +#define CIF_ISP_AFM_LT_A (CIF_ISP_AFM_BASE + 0x00000004)
> +#define CIF_ISP_AFM_RB_A (CIF_ISP_AFM_BASE + 0x00000008)
> +#define CIF_ISP_AFM_LT_B (CIF_ISP_AFM_BASE + 0x0000000C)
> +#define CIF_ISP_AFM_RB_B (CIF_ISP_AFM_BASE + 0x00000010)
> +#define CIF_ISP_AFM_LT_C (CIF_ISP_AFM_BASE + 0x00000014)
> +#define CIF_ISP_AFM_RB_C (CIF_ISP_AFM_BASE + 0x00000018)
> +#define CIF_ISP_AFM_THRES (CIF_ISP_AFM_BASE + 0x0000001C)
> +#define CIF_ISP_AFM_VAR_SHIFT (CIF_ISP_AFM_BASE + 0x00000020)
> +#define CIF_ISP_AFM_SUM_A (CIF_ISP_AFM_BASE + 0x00000024)
> +#define CIF_ISP_AFM_SUM_B (CIF_ISP_AFM_BASE + 0x00000028)
> +#define CIF_ISP_AFM_SUM_C (CIF_ISP_AFM_BASE + 0x0000002C)
> +#define CIF_ISP_AFM_LUM_A (CIF_ISP_AFM_BASE + 0x00000030)
> +#define CIF_ISP_AFM_LUM_B (CIF_ISP_AFM_BASE + 0x00000034)
> +#define CIF_ISP_AFM_LUM_C (CIF_ISP_AFM_BASE + 0x00000038)
> +
> +#define CIF_ISP_LSC_BASE 0x00002200
> +#define CIF_ISP_LSC_CTRL (CIF_ISP_LSC_BASE + 0x00000000)
> +#define CIF_ISP_LSC_R_TABLE_ADDR (CIF_ISP_LSC_BASE + 0x00000004)
> +#define CIF_ISP_LSC_GR_TABLE_ADDR (CIF_ISP_LSC_BASE + 0x00000008)
> +#define CIF_ISP_LSC_B_TABLE_ADDR (CIF_ISP_LSC_BASE + 0x0000000C)
> +#define CIF_ISP_LSC_GB_TABLE_ADDR (CIF_ISP_LSC_BASE + 0x00000010)
> +#define CIF_ISP_LSC_R_TABLE_DATA (CIF_ISP_LSC_BASE + 0x00000014)
> +#define CIF_ISP_LSC_GR_TABLE_DATA (CIF_ISP_LSC_BASE + 0x00000018)
> +#define CIF_ISP_LSC_B_TABLE_DATA (CIF_ISP_LSC_BASE + 0x0000001C)
> +#define CIF_ISP_LSC_GB_TABLE_DATA (CIF_ISP_LSC_BASE + 0x00000020)
> +#define CIF_ISP_LSC_XGRAD_01 (CIF_ISP_LSC_BASE + 0x00000024)
> +#define CIF_ISP_LSC_XGRAD_23 (CIF_ISP_LSC_BASE + 0x00000028)
> +#define CIF_ISP_LSC_XGRAD_45 (CIF_ISP_LSC_BASE + 0x0000002C)
> +#define CIF_ISP_LSC_XGRAD_67 (CIF_ISP_LSC_BASE + 0x00000030)
> +#define CIF_ISP_LSC_YGRAD_01 (CIF_ISP_LSC_BASE + 0x00000034)
> +#define CIF_ISP_LSC_YGRAD_23 (CIF_ISP_LSC_BASE + 0x00000038)
> +#define CIF_ISP_LSC_YGRAD_45 (CIF_ISP_LSC_BASE + 0x0000003C)
> +#define CIF_ISP_LSC_YGRAD_67 (CIF_ISP_LSC_BASE + 0x00000040)
> +#define CIF_ISP_LSC_XSIZE_01 (CIF_ISP_LSC_BASE + 0x00000044)
> +#define CIF_ISP_LSC_XSIZE_23 (CIF_ISP_LSC_BASE + 0x00000048)
> +#define CIF_ISP_LSC_XSIZE_45 (CIF_ISP_LSC_BASE + 0x0000004C)
> +#define CIF_ISP_LSC_XSIZE_67 (CIF_ISP_LSC_BASE + 0x00000050)
> +#define CIF_ISP_LSC_YSIZE_01 (CIF_ISP_LSC_BASE + 0x00000054)
> +#define CIF_ISP_LSC_YSIZE_23 (CIF_ISP_LSC_BASE + 0x00000058)
> +#define CIF_ISP_LSC_YSIZE_45 (CIF_ISP_LSC_BASE + 0x0000005C)
> +#define CIF_ISP_LSC_YSIZE_67 (CIF_ISP_LSC_BASE + 0x00000060)
> +#define CIF_ISP_LSC_TABLE_SEL (CIF_ISP_LSC_BASE + 0x00000064)
> +#define CIF_ISP_LSC_STATUS (CIF_ISP_LSC_BASE + 0x00000068)
> +
> +#define CIF_ISP_IS_BASE 0x00002300
> +#define CIF_ISP_IS_CTRL (CIF_ISP_IS_BASE + 0x00000000)
> +#define CIF_ISP_IS_RECENTER (CIF_ISP_IS_BASE + 0x00000004)
> +#define CIF_ISP_IS_H_OFFS (CIF_ISP_IS_BASE + 0x00000008)
> +#define CIF_ISP_IS_V_OFFS (CIF_ISP_IS_BASE + 0x0000000C)
> +#define CIF_ISP_IS_H_SIZE (CIF_ISP_IS_BASE + 0x00000010)
> +#define CIF_ISP_IS_V_SIZE (CIF_ISP_IS_BASE + 0x00000014)
> +#define CIF_ISP_IS_MAX_DX (CIF_ISP_IS_BASE + 0x00000018)
> +#define CIF_ISP_IS_MAX_DY (CIF_ISP_IS_BASE + 0x0000001C)
> +#define CIF_ISP_IS_DISPLACE (CIF_ISP_IS_BASE + 0x00000020)
> +#define CIF_ISP_IS_H_OFFS_SHD (CIF_ISP_IS_BASE + 0x00000024)
> +#define CIF_ISP_IS_V_OFFS_SHD (CIF_ISP_IS_BASE + 0x00000028)
> +#define CIF_ISP_IS_H_SIZE_SHD (CIF_ISP_IS_BASE + 0x0000002C)
> +#define CIF_ISP_IS_V_SIZE_SHD (CIF_ISP_IS_BASE + 0x00000030)
> +
> +#define CIF_ISP_HIST_BASE 0x00002400
> +
> +#define CIF_ISP_HIST_PROP (CIF_ISP_HIST_BASE + 0x00000000)
> +#define CIF_ISP_HIST_H_OFFS (CIF_ISP_HIST_BASE + 0x00000004)
> +#define CIF_ISP_HIST_V_OFFS (CIF_ISP_HIST_BASE + 0x00000008)
> +#define CIF_ISP_HIST_H_SIZE (CIF_ISP_HIST_BASE + 0x0000000C)
> +#define CIF_ISP_HIST_V_SIZE (CIF_ISP_HIST_BASE + 0x00000010)
> +#define CIF_ISP_HIST_BIN_0 (CIF_ISP_HIST_BASE + 0x00000014)
> +#define CIF_ISP_HIST_BIN_1 (CIF_ISP_HIST_BASE + 0x00000018)
> +#define CIF_ISP_HIST_BIN_2 (CIF_ISP_HIST_BASE + 0x0000001C)
> +#define CIF_ISP_HIST_BIN_3 (CIF_ISP_HIST_BASE + 0x00000020)
> +#define CIF_ISP_HIST_BIN_4 (CIF_ISP_HIST_BASE + 0x00000024)
> +#define CIF_ISP_HIST_BIN_5 (CIF_ISP_HIST_BASE + 0x00000028)
> +#define CIF_ISP_HIST_BIN_6 (CIF_ISP_HIST_BASE + 0x0000002C)
> +#define CIF_ISP_HIST_BIN_7 (CIF_ISP_HIST_BASE + 0x00000030)
> +#define CIF_ISP_HIST_BIN_8 (CIF_ISP_HIST_BASE + 0x00000034)
> +#define CIF_ISP_HIST_BIN_9 (CIF_ISP_HIST_BASE + 0x00000038)
> +#define CIF_ISP_HIST_BIN_10 (CIF_ISP_HIST_BASE + 0x0000003C)
> +#define CIF_ISP_HIST_BIN_11 (CIF_ISP_HIST_BASE + 0x00000040)
> +#define CIF_ISP_HIST_BIN_12 (CIF_ISP_HIST_BASE + 0x00000044)
> +#define CIF_ISP_HIST_BIN_13 (CIF_ISP_HIST_BASE + 0x00000048)
> +#define CIF_ISP_HIST_BIN_14 (CIF_ISP_HIST_BASE + 0x0000004C)
> +#define CIF_ISP_HIST_BIN_15 (CIF_ISP_HIST_BASE + 0x00000050)
> +#define CIF_ISP_HIST_WEIGHT_00TO30 (CIF_ISP_HIST_BASE + 0x00000054)
> +#define CIF_ISP_HIST_WEIGHT_40TO21 (CIF_ISP_HIST_BASE + 0x00000058)
> +#define CIF_ISP_HIST_WEIGHT_31TO12 (CIF_ISP_HIST_BASE + 0x0000005C)
> +#define CIF_ISP_HIST_WEIGHT_22TO03 (CIF_ISP_HIST_BASE + 0x00000060)
> +#define CIF_ISP_HIST_WEIGHT_13TO43 (CIF_ISP_HIST_BASE + 0x00000064)
> +#define CIF_ISP_HIST_WEIGHT_04TO34 (CIF_ISP_HIST_BASE + 0x00000068)
> +#define CIF_ISP_HIST_WEIGHT_44 (CIF_ISP_HIST_BASE + 0x0000006C)
> +
> +#define CIF_ISP_FILT_BASE 0x00002500
> +#define CIF_ISP_FILT_MODE (CIF_ISP_FILT_BASE + 0x00000000)
> +#define CIF_ISP_FILT_THRESH_BL0 (CIF_ISP_FILT_BASE + 0x00000028)
> +#define CIF_ISP_FILT_THRESH_BL1 (CIF_ISP_FILT_BASE + 0x0000002c)
> +#define CIF_ISP_FILT_THRESH_SH0 (CIF_ISP_FILT_BASE + 0x00000030)
> +#define CIF_ISP_FILT_THRESH_SH1 (CIF_ISP_FILT_BASE + 0x00000034)
> +#define CIF_ISP_FILT_LUM_WEIGHT (CIF_ISP_FILT_BASE + 0x00000038)
> +#define CIF_ISP_FILT_FAC_SH1 (CIF_ISP_FILT_BASE + 0x0000003c)
> +#define CIF_ISP_FILT_FAC_SH0 (CIF_ISP_FILT_BASE + 0x00000040)
> +#define CIF_ISP_FILT_FAC_MID (CIF_ISP_FILT_BASE + 0x00000044)
> +#define CIF_ISP_FILT_FAC_BL0 (CIF_ISP_FILT_BASE + 0x00000048)
> +#define CIF_ISP_FILT_FAC_BL1 (CIF_ISP_FILT_BASE + 0x0000004C)
> +
> +#define CIF_ISP_CAC_BASE 0x00002580
> +#define CIF_ISP_CAC_CTRL (CIF_ISP_CAC_BASE + 0x00000000)
> +#define CIF_ISP_CAC_COUNT_START (CIF_ISP_CAC_BASE + 0x00000004)
> +#define CIF_ISP_CAC_A (CIF_ISP_CAC_BASE + 0x00000008)
> +#define CIF_ISP_CAC_B (CIF_ISP_CAC_BASE + 0x0000000C)
> +#define CIF_ISP_CAC_C (CIF_ISP_CAC_BASE + 0x00000010)
> +#define CIF_ISP_X_NORM (CIF_ISP_CAC_BASE + 0x00000014)
> +#define CIF_ISP_Y_NORM (CIF_ISP_CAC_BASE + 0x00000018)
> +
> +#define CIF_ISP_EXP_BASE 0x00002600
> +#define CIF_ISP_EXP_CTRL (CIF_ISP_EXP_BASE + 0x00000000)
> +#define CIF_ISP_EXP_H_OFFSET (CIF_ISP_EXP_BASE + 0x00000004)
> +#define CIF_ISP_EXP_V_OFFSET (CIF_ISP_EXP_BASE + 0x00000008)
> +#define CIF_ISP_EXP_H_SIZE (CIF_ISP_EXP_BASE + 0x0000000C)
> +#define CIF_ISP_EXP_V_SIZE (CIF_ISP_EXP_BASE + 0x00000010)
> +#define CIF_ISP_EXP_MEAN_00 (CIF_ISP_EXP_BASE + 0x00000014)
> +#define CIF_ISP_EXP_MEAN_10 (CIF_ISP_EXP_BASE + 0x00000018)
> +#define CIF_ISP_EXP_MEAN_20 (CIF_ISP_EXP_BASE + 0x0000001c)
> +#define CIF_ISP_EXP_MEAN_30 (CIF_ISP_EXP_BASE + 0x00000020)
> +#define CIF_ISP_EXP_MEAN_40 (CIF_ISP_EXP_BASE + 0x00000024)
> +#define CIF_ISP_EXP_MEAN_01 (CIF_ISP_EXP_BASE + 0x00000028)
> +#define CIF_ISP_EXP_MEAN_11 (CIF_ISP_EXP_BASE + 0x0000002c)
> +#define CIF_ISP_EXP_MEAN_21 (CIF_ISP_EXP_BASE + 0x00000030)
> +#define CIF_ISP_EXP_MEAN_31 (CIF_ISP_EXP_BASE + 0x00000034)
> +#define CIF_ISP_EXP_MEAN_41 (CIF_ISP_EXP_BASE + 0x00000038)
> +#define CIF_ISP_EXP_MEAN_02 (CIF_ISP_EXP_BASE + 0x0000003c)
> +#define CIF_ISP_EXP_MEAN_12 (CIF_ISP_EXP_BASE + 0x00000040)
> +#define CIF_ISP_EXP_MEAN_22 (CIF_ISP_EXP_BASE + 0x00000044)
> +#define CIF_ISP_EXP_MEAN_32 (CIF_ISP_EXP_BASE + 0x00000048)
> +#define CIF_ISP_EXP_MEAN_42 (CIF_ISP_EXP_BASE + 0x0000004c)
> +#define CIF_ISP_EXP_MEAN_03 (CIF_ISP_EXP_BASE + 0x00000050)
> +#define CIF_ISP_EXP_MEAN_13 (CIF_ISP_EXP_BASE + 0x00000054)
> +#define CIF_ISP_EXP_MEAN_23 (CIF_ISP_EXP_BASE + 0x00000058)
> +#define CIF_ISP_EXP_MEAN_33 (CIF_ISP_EXP_BASE + 0x0000005c)
> +#define CIF_ISP_EXP_MEAN_43 (CIF_ISP_EXP_BASE + 0x00000060)
> +#define CIF_ISP_EXP_MEAN_04 (CIF_ISP_EXP_BASE + 0x00000064)
> +#define CIF_ISP_EXP_MEAN_14 (CIF_ISP_EXP_BASE + 0x00000068)
> +#define CIF_ISP_EXP_MEAN_24 (CIF_ISP_EXP_BASE + 0x0000006c)
> +#define CIF_ISP_EXP_MEAN_34 (CIF_ISP_EXP_BASE + 0x00000070)
> +#define CIF_ISP_EXP_MEAN_44 (CIF_ISP_EXP_BASE + 0x00000074)
> +
> +#define CIF_ISP_BLS_BASE 0x00002700
> +#define CIF_ISP_BLS_CTRL (CIF_ISP_BLS_BASE + 0x00000000)
> +#define CIF_ISP_BLS_SAMPLES (CIF_ISP_BLS_BASE + 0x00000004)
> +#define CIF_ISP_BLS_H1_START (CIF_ISP_BLS_BASE + 0x00000008)
> +#define CIF_ISP_BLS_H1_STOP (CIF_ISP_BLS_BASE + 0x0000000c)
> +#define CIF_ISP_BLS_V1_START (CIF_ISP_BLS_BASE + 0x00000010)
> +#define CIF_ISP_BLS_V1_STOP (CIF_ISP_BLS_BASE + 0x00000014)
> +#define CIF_ISP_BLS_H2_START (CIF_ISP_BLS_BASE + 0x00000018)
> +#define CIF_ISP_BLS_H2_STOP (CIF_ISP_BLS_BASE + 0x0000001c)
> +#define CIF_ISP_BLS_V2_START (CIF_ISP_BLS_BASE + 0x00000020)
> +#define CIF_ISP_BLS_V2_STOP (CIF_ISP_BLS_BASE + 0x00000024)
> +#define CIF_ISP_BLS_A_FIXED (CIF_ISP_BLS_BASE + 0x00000028)
> +#define CIF_ISP_BLS_B_FIXED (CIF_ISP_BLS_BASE + 0x0000002c)
> +#define CIF_ISP_BLS_C_FIXED (CIF_ISP_BLS_BASE + 0x00000030)
> +#define CIF_ISP_BLS_D_FIXED (CIF_ISP_BLS_BASE + 0x00000034)
> +#define CIF_ISP_BLS_A_MEASURED (CIF_ISP_BLS_BASE + 0x00000038)
> +#define CIF_ISP_BLS_B_MEASURED (CIF_ISP_BLS_BASE + 0x0000003c)
> +#define CIF_ISP_BLS_C_MEASURED (CIF_ISP_BLS_BASE + 0x00000040)
> +#define CIF_ISP_BLS_D_MEASURED (CIF_ISP_BLS_BASE + 0x00000044)
> +
> +#define CIF_ISP_DPF_BASE 0x00002800
> +#define CIF_ISP_DPF_MODE (CIF_ISP_DPF_BASE + 0x00000000)
> +#define CIF_ISP_DPF_STRENGTH_R (CIF_ISP_DPF_BASE + 0x00000004)
> +#define CIF_ISP_DPF_STRENGTH_G (CIF_ISP_DPF_BASE + 0x00000008)
> +#define CIF_ISP_DPF_STRENGTH_B (CIF_ISP_DPF_BASE + 0x0000000C)
> +#define CIF_ISP_DPF_S_WEIGHT_G_1_4 (CIF_ISP_DPF_BASE + 0x00000010)
> +#define CIF_ISP_DPF_S_WEIGHT_G_5_6 (CIF_ISP_DPF_BASE + 0x00000014)
> +#define CIF_ISP_DPF_S_WEIGHT_RB_1_4 (CIF_ISP_DPF_BASE + 0x00000018)
> +#define CIF_ISP_DPF_S_WEIGHT_RB_5_6 (CIF_ISP_DPF_BASE + 0x0000001C)
> +#define CIF_ISP_DPF_NULL_COEFF_0 (CIF_ISP_DPF_BASE + 0x00000020)
> +#define CIF_ISP_DPF_NULL_COEFF_1 (CIF_ISP_DPF_BASE + 0x00000024)
> +#define CIF_ISP_DPF_NULL_COEFF_2 (CIF_ISP_DPF_BASE + 0x00000028)
> +#define CIF_ISP_DPF_NULL_COEFF_3 (CIF_ISP_DPF_BASE + 0x0000002C)
> +#define CIF_ISP_DPF_NULL_COEFF_4 (CIF_ISP_DPF_BASE + 0x00000030)
> +#define CIF_ISP_DPF_NULL_COEFF_5 (CIF_ISP_DPF_BASE + 0x00000034)
> +#define CIF_ISP_DPF_NULL_COEFF_6 (CIF_ISP_DPF_BASE + 0x00000038)
> +#define CIF_ISP_DPF_NULL_COEFF_7 (CIF_ISP_DPF_BASE + 0x0000003C)
> +#define CIF_ISP_DPF_NULL_COEFF_8 (CIF_ISP_DPF_BASE + 0x00000040)
> +#define CIF_ISP_DPF_NULL_COEFF_9 (CIF_ISP_DPF_BASE + 0x00000044)
> +#define CIF_ISP_DPF_NULL_COEFF_10 (CIF_ISP_DPF_BASE + 0x00000048)
> +#define CIF_ISP_DPF_NULL_COEFF_11 (CIF_ISP_DPF_BASE + 0x0000004C)
> +#define CIF_ISP_DPF_NULL_COEFF_12 (CIF_ISP_DPF_BASE + 0x00000050)
> +#define CIF_ISP_DPF_NULL_COEFF_13 (CIF_ISP_DPF_BASE + 0x00000054)
> +#define CIF_ISP_DPF_NULL_COEFF_14 (CIF_ISP_DPF_BASE + 0x00000058)
> +#define CIF_ISP_DPF_NULL_COEFF_15 (CIF_ISP_DPF_BASE + 0x0000005C)
> +#define CIF_ISP_DPF_NULL_COEFF_16 (CIF_ISP_DPF_BASE + 0x00000060)
> +#define CIF_ISP_DPF_NF_GAIN_R (CIF_ISP_DPF_BASE + 0x00000064)
> +#define CIF_ISP_DPF_NF_GAIN_GR (CIF_ISP_DPF_BASE + 0x00000068)
> +#define CIF_ISP_DPF_NF_GAIN_GB (CIF_ISP_DPF_BASE + 0x0000006C)
> +#define CIF_ISP_DPF_NF_GAIN_B (CIF_ISP_DPF_BASE + 0x00000070)
> +
> +#define CIF_ISP_DPCC_BASE 0x00002900
> +#define CIF_ISP_DPCC_MODE (CIF_ISP_DPCC_BASE + 0x00000000)
> +#define CIF_ISP_DPCC_OUTPUT_MODE (CIF_ISP_DPCC_BASE + 0x00000004)
> +#define CIF_ISP_DPCC_SET_USE (CIF_ISP_DPCC_BASE + 0x00000008)
> +#define CIF_ISP_DPCC_METHODS_SET_1 (CIF_ISP_DPCC_BASE + 0x0000000C)
> +#define CIF_ISP_DPCC_METHODS_SET_2 (CIF_ISP_DPCC_BASE + 0x00000010)
> +#define CIF_ISP_DPCC_METHODS_SET_3 (CIF_ISP_DPCC_BASE + 0x00000014)
> +#define CIF_ISP_DPCC_LINE_THRESH_1 (CIF_ISP_DPCC_BASE + 0x00000018)
> +#define CIF_ISP_DPCC_LINE_MAD_FAC_1 (CIF_ISP_DPCC_BASE + 0x0000001C)
> +#define CIF_ISP_DPCC_PG_FAC_1 (CIF_ISP_DPCC_BASE + 0x00000020)
> +#define CIF_ISP_DPCC_RND_THRESH_1 (CIF_ISP_DPCC_BASE + 0x00000024)
> +#define CIF_ISP_DPCC_RG_FAC_1 (CIF_ISP_DPCC_BASE + 0x00000028)
> +#define CIF_ISP_DPCC_LINE_THRESH_2 (CIF_ISP_DPCC_BASE + 0x0000002C)
> +#define CIF_ISP_DPCC_LINE_MAD_FAC_2 (CIF_ISP_DPCC_BASE + 0x00000030)
> +#define CIF_ISP_DPCC_PG_FAC_2 (CIF_ISP_DPCC_BASE + 0x00000034)
> +#define CIF_ISP_DPCC_RND_THRESH_2 (CIF_ISP_DPCC_BASE + 0x00000038)
> +#define CIF_ISP_DPCC_RG_FAC_2 (CIF_ISP_DPCC_BASE + 0x0000003C)
> +#define CIF_ISP_DPCC_LINE_THRESH_3 (CIF_ISP_DPCC_BASE + 0x00000040)
> +#define CIF_ISP_DPCC_LINE_MAD_FAC_3 (CIF_ISP_DPCC_BASE + 0x00000044)
> +#define CIF_ISP_DPCC_PG_FAC_3 (CIF_ISP_DPCC_BASE + 0x00000048)
> +#define CIF_ISP_DPCC_RND_THRESH_3 (CIF_ISP_DPCC_BASE + 0x0000004C)
> +#define CIF_ISP_DPCC_RG_FAC_3 (CIF_ISP_DPCC_BASE + 0x00000050)
> +#define CIF_ISP_DPCC_RO_LIMITS (CIF_ISP_DPCC_BASE + 0x00000054)
> +#define CIF_ISP_DPCC_RND_OFFS (CIF_ISP_DPCC_BASE + 0x00000058)
> +#define CIF_ISP_DPCC_BPT_CTRL (CIF_ISP_DPCC_BASE + 0x0000005C)
> +#define CIF_ISP_DPCC_BPT_NUMBER (CIF_ISP_DPCC_BASE + 0x00000060)
> +#define CIF_ISP_DPCC_BPT_ADDR (CIF_ISP_DPCC_BASE + 0x00000064)
> +#define CIF_ISP_DPCC_BPT_DATA (CIF_ISP_DPCC_BASE + 0x00000068)
> +
> +#define CIF_ISP_WDR_BASE 0x00002A00
> +#define CIF_ISP_WDR_CTRL (CIF_ISP_WDR_BASE + 0x00000000)
> +#define CIF_ISP_WDR_TONECURVE_1 (CIF_ISP_WDR_BASE + 0x00000004)
> +#define CIF_ISP_WDR_TONECURVE_2 (CIF_ISP_WDR_BASE + 0x00000008)
> +#define CIF_ISP_WDR_TONECURVE_3 (CIF_ISP_WDR_BASE + 0x0000000C)
> +#define CIF_ISP_WDR_TONECURVE_4 (CIF_ISP_WDR_BASE + 0x00000010)
> +#define CIF_ISP_WDR_TONECURVE_YM_0 (CIF_ISP_WDR_BASE + 0x00000014)
> +#define CIF_ISP_WDR_TONECURVE_YM_1 (CIF_ISP_WDR_BASE + 0x00000018)
> +#define CIF_ISP_WDR_TONECURVE_YM_2 (CIF_ISP_WDR_BASE + 0x0000001C)
> +#define CIF_ISP_WDR_TONECURVE_YM_3 (CIF_ISP_WDR_BASE + 0x00000020)
> +#define CIF_ISP_WDR_TONECURVE_YM_4 (CIF_ISP_WDR_BASE + 0x00000024)
> +#define CIF_ISP_WDR_TONECURVE_YM_5 (CIF_ISP_WDR_BASE + 0x00000028)
> +#define CIF_ISP_WDR_TONECURVE_YM_6 (CIF_ISP_WDR_BASE + 0x0000002C)
> +#define CIF_ISP_WDR_TONECURVE_YM_7 (CIF_ISP_WDR_BASE + 0x00000030)
> +#define CIF_ISP_WDR_TONECURVE_YM_8 (CIF_ISP_WDR_BASE + 0x00000034)
> +#define CIF_ISP_WDR_TONECURVE_YM_9 (CIF_ISP_WDR_BASE + 0x00000038)
> +#define CIF_ISP_WDR_TONECURVE_YM_10 (CIF_ISP_WDR_BASE + 0x0000003C)
> +#define CIF_ISP_WDR_TONECURVE_YM_11 (CIF_ISP_WDR_BASE + 0x00000040)
> +#define CIF_ISP_WDR_TONECURVE_YM_12 (CIF_ISP_WDR_BASE + 0x00000044)
> +#define CIF_ISP_WDR_TONECURVE_YM_13 (CIF_ISP_WDR_BASE + 0x00000048)
> +#define CIF_ISP_WDR_TONECURVE_YM_14 (CIF_ISP_WDR_BASE + 0x0000004C)
> +#define CIF_ISP_WDR_TONECURVE_YM_15 (CIF_ISP_WDR_BASE + 0x00000050)
> +#define CIF_ISP_WDR_TONECURVE_YM_16 (CIF_ISP_WDR_BASE + 0x00000054)
> +#define CIF_ISP_WDR_TONECURVE_YM_17 (CIF_ISP_WDR_BASE + 0x00000058)
> +#define CIF_ISP_WDR_TONECURVE_YM_18 (CIF_ISP_WDR_BASE + 0x0000005C)
> +#define CIF_ISP_WDR_TONECURVE_YM_19 (CIF_ISP_WDR_BASE + 0x00000060)
> +#define CIF_ISP_WDR_TONECURVE_YM_20 (CIF_ISP_WDR_BASE + 0x00000064)
> +#define CIF_ISP_WDR_TONECURVE_YM_21 (CIF_ISP_WDR_BASE + 0x00000068)
> +#define CIF_ISP_WDR_TONECURVE_YM_22 (CIF_ISP_WDR_BASE + 0x0000006C)
> +#define CIF_ISP_WDR_TONECURVE_YM_23 (CIF_ISP_WDR_BASE + 0x00000070)
> +#define CIF_ISP_WDR_TONECURVE_YM_24 (CIF_ISP_WDR_BASE + 0x00000074)
> +#define CIF_ISP_WDR_TONECURVE_YM_25 (CIF_ISP_WDR_BASE + 0x00000078)
> +#define CIF_ISP_WDR_TONECURVE_YM_26 (CIF_ISP_WDR_BASE + 0x0000007C)
> +#define CIF_ISP_WDR_TONECURVE_YM_27 (CIF_ISP_WDR_BASE + 0x00000080)
> +#define CIF_ISP_WDR_TONECURVE_YM_28 (CIF_ISP_WDR_BASE + 0x00000084)
> +#define CIF_ISP_WDR_TONECURVE_YM_29 (CIF_ISP_WDR_BASE + 0x00000088)
> +#define CIF_ISP_WDR_TONECURVE_YM_30 (CIF_ISP_WDR_BASE + 0x0000008C)
> +#define CIF_ISP_WDR_TONECURVE_YM_31 (CIF_ISP_WDR_BASE + 0x00000090)
> +#define CIF_ISP_WDR_TONECURVE_YM_32 (CIF_ISP_WDR_BASE + 0x00000094)
> +#define CIF_ISP_WDR_OFFSET (CIF_ISP_WDR_BASE + 0x00000098)
> +#define CIF_ISP_WDR_DELTAMIN (CIF_ISP_WDR_BASE + 0x0000009C)
> +#define CIF_ISP_WDR_TONECURVE_1_SHD (CIF_ISP_WDR_BASE + 0x000000A0)
> +#define CIF_ISP_WDR_TONECURVE_2_SHD (CIF_ISP_WDR_BASE + 0x000000A4)
> +#define CIF_ISP_WDR_TONECURVE_3_SHD (CIF_ISP_WDR_BASE + 0x000000A8)
> +#define CIF_ISP_WDR_TONECURVE_4_SHD (CIF_ISP_WDR_BASE + 0x000000AC)
> +#define CIF_ISP_WDR_TONECURVE_YM_0_SHD (CIF_ISP_WDR_BASE + 0x000000B0)
> +#define CIF_ISP_WDR_TONECURVE_YM_1_SHD (CIF_ISP_WDR_BASE + 0x000000B4)
> +#define CIF_ISP_WDR_TONECURVE_YM_2_SHD (CIF_ISP_WDR_BASE + 0x000000B8)
> +#define CIF_ISP_WDR_TONECURVE_YM_3_SHD (CIF_ISP_WDR_BASE + 0x000000BC)
> +#define CIF_ISP_WDR_TONECURVE_YM_4_SHD (CIF_ISP_WDR_BASE + 0x000000C0)
> +#define CIF_ISP_WDR_TONECURVE_YM_5_SHD (CIF_ISP_WDR_BASE + 0x000000C4)
> +#define CIF_ISP_WDR_TONECURVE_YM_6_SHD (CIF_ISP_WDR_BASE + 0x000000C8)
> +#define CIF_ISP_WDR_TONECURVE_YM_7_SHD (CIF_ISP_WDR_BASE + 0x000000CC)
> +#define CIF_ISP_WDR_TONECURVE_YM_8_SHD (CIF_ISP_WDR_BASE + 0x000000D0)
> +#define CIF_ISP_WDR_TONECURVE_YM_9_SHD (CIF_ISP_WDR_BASE + 0x000000D4)
> +#define CIF_ISP_WDR_TONECURVE_YM_10_SHD (CIF_ISP_WDR_BASE + 0x000000D8)
> +#define CIF_ISP_WDR_TONECURVE_YM_11_SHD (CIF_ISP_WDR_BASE + 0x000000DC)
> +#define CIF_ISP_WDR_TONECURVE_YM_12_SHD (CIF_ISP_WDR_BASE + 0x000000E0)
> +#define CIF_ISP_WDR_TONECURVE_YM_13_SHD (CIF_ISP_WDR_BASE + 0x000000E4)
> +#define CIF_ISP_WDR_TONECURVE_YM_14_SHD (CIF_ISP_WDR_BASE + 0x000000E8)
> +#define CIF_ISP_WDR_TONECURVE_YM_15_SHD (CIF_ISP_WDR_BASE + 0x000000EC)
> +#define CIF_ISP_WDR_TONECURVE_YM_16_SHD (CIF_ISP_WDR_BASE + 0x000000F0)
> +#define CIF_ISP_WDR_TONECURVE_YM_17_SHD (CIF_ISP_WDR_BASE + 0x000000F4)
> +#define CIF_ISP_WDR_TONECURVE_YM_18_SHD (CIF_ISP_WDR_BASE + 0x000000F8)
> +#define CIF_ISP_WDR_TONECURVE_YM_19_SHD (CIF_ISP_WDR_BASE + 0x000000FC)
> +#define CIF_ISP_WDR_TONECURVE_YM_20_SHD (CIF_ISP_WDR_BASE + 0x00000100)
> +#define CIF_ISP_WDR_TONECURVE_YM_21_SHD (CIF_ISP_WDR_BASE + 0x00000104)
> +#define CIF_ISP_WDR_TONECURVE_YM_22_SHD (CIF_ISP_WDR_BASE + 0x00000108)
> +#define CIF_ISP_WDR_TONECURVE_YM_23_SHD (CIF_ISP_WDR_BASE + 0x0000010C)
> +#define CIF_ISP_WDR_TONECURVE_YM_24_SHD (CIF_ISP_WDR_BASE + 0x00000110)
> +#define CIF_ISP_WDR_TONECURVE_YM_25_SHD (CIF_ISP_WDR_BASE + 0x00000114)
> +#define CIF_ISP_WDR_TONECURVE_YM_26_SHD (CIF_ISP_WDR_BASE + 0x00000118)
> +#define CIF_ISP_WDR_TONECURVE_YM_27_SHD (CIF_ISP_WDR_BASE + 0x0000011C)
> +#define CIF_ISP_WDR_TONECURVE_YM_28_SHD (CIF_ISP_WDR_BASE + 0x00000120)
> +#define CIF_ISP_WDR_TONECURVE_YM_29_SHD (CIF_ISP_WDR_BASE + 0x00000124)
> +#define CIF_ISP_WDR_TONECURVE_YM_30_SHD (CIF_ISP_WDR_BASE + 0x00000128)
> +#define CIF_ISP_WDR_TONECURVE_YM_31_SHD (CIF_ISP_WDR_BASE + 0x0000012C)
> +#define CIF_ISP_WDR_TONECURVE_YM_32_SHD (CIF_ISP_WDR_BASE + 0x00000130)
> +
> +#define CIF_ISP_VSM_BASE 0x00002F00
> +#define CIF_ISP_VSM_MODE (CIF_ISP_VSM_BASE + 0x00000000)
> +#define CIF_ISP_VSM_H_OFFS (CIF_ISP_VSM_BASE + 0x00000004)
> +#define CIF_ISP_VSM_V_OFFS (CIF_ISP_VSM_BASE + 0x00000008)
> +#define CIF_ISP_VSM_H_SIZE (CIF_ISP_VSM_BASE + 0x0000000C)
> +#define CIF_ISP_VSM_V_SIZE (CIF_ISP_VSM_BASE + 0x00000010)
> +#define CIF_ISP_VSM_H_SEGMENTS (CIF_ISP_VSM_BASE + 0x00000014)
> +#define CIF_ISP_VSM_V_SEGMENTS (CIF_ISP_VSM_BASE + 0x00000018)
> +#define CIF_ISP_VSM_DELTA_H (CIF_ISP_VSM_BASE + 0x0000001C)
> +#define CIF_ISP_VSM_DELTA_V (CIF_ISP_VSM_BASE + 0x00000020)
> +
> +void disable_dcrop(struct rkisp1_stream *stream, bool async);
> +void config_dcrop(struct rkisp1_stream *stream, struct v4l2_rect *rect,
> + bool async);
> +
> +void dump_rsz_regs(struct rkisp1_stream *stream);
> +void disable_rsz(struct rkisp1_stream *stream, bool async);
> +void config_rsz(struct rkisp1_stream *stream, struct v4l2_rect *in_y,
> + struct v4l2_rect *in_c, struct v4l2_rect *out_y,
> + struct v4l2_rect *out_c, bool async);
> +
> +void config_mi_ctrl(struct rkisp1_stream *stream);
> +
> +void mp_clr_frame_end_int(void __iomem * base);
> +void sp_clr_frame_end_int(void __iomem * base);
> +
> +u32 mp_is_frame_end_int_masked(void __iomem * base);
> +u32 sp_is_frame_end_int_masked(void __iomem * base);
> +
> +static inline void mi_set_y_size(struct rkisp1_stream *stream, int val)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> +
> + writel(val, base + stream->config->mi.y_size_init);
> +}
> +
> +static inline void mi_set_cb_size(struct rkisp1_stream *stream, int val)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> +
> + writel(val, base + stream->config->mi.cb_size_init);
> +}
> +
> +static inline void mi_set_cr_size(struct rkisp1_stream *stream, int val)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> +
> + writel(val, base + stream->config->mi.cr_size_init);
> +}
> +
> +static inline void mi_set_y_addr(struct rkisp1_stream *stream, int val)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> +
> + writel(val, base + stream->config->mi.y_base_ad_init);
> +}
> +
> +static inline void mi_set_cb_addr(struct rkisp1_stream *stream, int val)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> +
> + writel(val, base + stream->config->mi.cb_base_ad_init);
> +}
> +
> +static inline void mi_set_cr_addr(struct rkisp1_stream *stream, int val)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> +
> + writel(val, base + stream->config->mi.cr_base_ad_init);
> +}
> +
> +static inline void mi_set_y_offset(struct rkisp1_stream *stream, int val)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> +
> + writel(val, base + stream->config->mi.y_offs_cnt_init);
> +}
> +
> +static inline void mi_set_cb_offset(struct rkisp1_stream *stream, int val)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> +
> + writel(val, base + stream->config->mi.cb_offs_cnt_init);
> +}
> +
> +static inline void mi_set_cr_offset(struct rkisp1_stream *stream, int val)
> +{
> + void __iomem *base = stream->ispdev->base_addr;
> +
> + writel(val, base + stream->config->mi.cr_offs_cnt_init);
> +}
> +
> +static inline void mp_set_chain_mode(void __iomem *base)
> +{
> + u32 dpcl = readl(base + CIF_VI_DPCL);
> +
> + dpcl |= CIF_VI_DPCL_CHAN_MODE_MP;
> + writel(dpcl, base + CIF_VI_DPCL);
> +}
> +
> +static inline void sp_set_chain_mode(void __iomem *base)
> +{
> + u32 dpcl = readl(base + CIF_VI_DPCL);
> +
> + dpcl |= CIF_VI_DPCL_CHAN_MODE_SP;
> + writel(dpcl, base + CIF_VI_DPCL);
> +}
> +
> +static inline void mp_set_data_path(void __iomem *base)
> +{
> + u32 dpcl = readl(base + CIF_VI_DPCL);
> +
> + dpcl = dpcl | CIF_VI_DPCL_CHAN_MODE_MP | CIF_VI_DPCL_MP_MUX_MRSZ_MI;
> + writel(dpcl, base + CIF_VI_DPCL);
> +}
> +
> +static inline void sp_set_data_path(void __iomem *base)
> +{
> + u32 dpcl = readl(base + CIF_VI_DPCL);
> +
> + dpcl |= CIF_VI_DPCL_CHAN_MODE_SP;
> + writel(dpcl, base + CIF_VI_DPCL);
> +}
> +
> +static inline void mp_frame_end_int_enable(void __iomem *base)
> +{
> + void __iomem *addr = base + CIF_MI_IMSC;
> +
> + writel(CIF_MI_MP_FRAME | readl(addr), addr);
> +}
> +
> +static inline void sp_frame_end_int_enable(void __iomem *base)
> +{
> + void __iomem *addr = base + CIF_MI_IMSC;
> +
> + writel(CIF_MI_SP_FRAME | readl(addr), addr);
> +}
> +
> +static inline void mp_frame_end_int_disable(void __iomem *base)
> +{
> + void __iomem *addr = base + CIF_MI_IMSC;
> +
> + writel(~CIF_MI_MP_FRAME & readl(addr), addr);
> +}
> +
> +static inline void sp_frame_end_int_disable(void __iomem *base)
> +{
> + void __iomem *addr = base + CIF_MI_IMSC;
> +
> + writel(~CIF_MI_SP_FRAME & readl(addr), addr);
> +}
> +
> +static inline void frame_end_int_disable(void __iomem *base)
> +{
> + void __iomem *addr = base + CIF_MI_IMSC;
> +
> + writel(~(CIF_MI_SP_FRAME | CIF_MI_MP_FRAME) & readl(addr), addr);
> +}
> +
> +static inline void clr_mpsp_frame_end_int(void __iomem *base)
> +{
> + writel(CIF_MI_SP_FRAME | CIF_MI_MP_FRAME, base + CIF_MI_ICR);
> +}
> +
> +static inline void clr_mp_crop_rsz_int(void __iomem *base)
> +{
> + writel(~CIF_MI_MP_FRAME, base + CIF_MI_ICR);
> +}
> +
> +static inline void clr_sp_crop_rsz_int(void __iomem *base)
> +{
> + writel(~CIF_MI_SP_FRAME, base + CIF_MI_ICR);
> +}
> +
> +static inline void clr_all_int(void __iomem *base)
> +{
> + writel(~0, base + CIF_MI_ICR);
> +}
> +
> +static inline void mp_set_uv_swap(void __iomem *base)
> +{
> + void __iomem *addr = base + CIF_MI_XTD_FORMAT_CTRL;
> + u32 reg = readl(addr) & ~GENMASK(2, 0);
> +
> + writel(reg | CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP, addr);
> +}
> +
> +static inline void sp_set_uv_swap(void __iomem *base)
> +{
> + void __iomem *addr = base + CIF_MI_XTD_FORMAT_CTRL;
> + u32 reg = readl(addr) & ~GENMASK(2, 0);
> +
> + writel(reg | CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP, addr);
> +}
> +
> +static inline void sp_set_y_width(void __iomem *base, u32 val)
> +{
> + writel(val, base + CIF_MI_SP_Y_PIC_WIDTH);
> +}
> +
> +static inline void sp_set_y_height(void __iomem *base, u32 val)
> +{
> + writel(val, base + CIF_MI_SP_Y_PIC_HEIGHT);
> +}
> +
> +static inline void sp_set_y_line_length(void __iomem *base, u32 val)
> +{
> + writel(val, base + CIF_MI_SP_Y_LLENGTH);
> +}
> +
> +static inline void mp_mi_ctrl_set_format(void __iomem *base, u32 val)
> +{
> + void __iomem *addr = base + CIF_MI_CTRL;
> + u32 reg = readl(addr) & ~MI_CTRL_MP_FMT_MASK;
> +
> + writel(reg | val, addr);
> +}
> +
> +static inline void sp_mi_ctrl_set_format(void __iomem *base, u32 val)
> +{
> + void __iomem *addr = base + CIF_MI_CTRL;
> + u32 reg = readl(addr) & ~MI_CTRL_SP_FMT_MASK;
> +
> + writel(reg | val, addr);
> +}
> +
> +static inline void mi_ctrl_mpyuv_enable(void __iomem *base)
> +{
> + void __iomem *addr = base + CIF_MI_CTRL;
> +
> + writel(CIF_MI_CTRL_MP_ENABLE | readl(addr), addr);
> +}
> +
> +static inline void mi_ctrl_mpyuv_disable(void __iomem *base)
> +{
> + void __iomem *addr = base + CIF_MI_CTRL;
> +
> + writel(~CIF_MI_CTRL_MP_ENABLE & readl(addr), addr);
> +}
> +
> +static inline void mi_ctrl_mp_disable(void __iomem *base)
> +{
> + void __iomem *addr = base + CIF_MI_CTRL;
> +
> + writel(~(CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE) & readl(addr),
> + addr);
> +}
> +
> +static inline void mi_ctrl_spyuv_enable(void __iomem *base)
> +{
> + void __iomem *addr = base + CIF_MI_CTRL;
> +
> + writel(CIF_MI_CTRL_SP_ENABLE | readl(addr), addr);
> +}
> +
> +static inline void mi_ctrl_spyuv_disable(void __iomem *base)
> +{
> + void __iomem *addr = base + CIF_MI_CTRL;
> +
> + writel(~CIF_MI_CTRL_SP_ENABLE & readl(addr), addr);
> +}
> +
> +static inline void mi_ctrl_sp_disable(void __iomem *base)
> +{
> + mi_ctrl_spyuv_disable(base);
> +}
> +
> +static inline void mi_ctrl_mpraw_enable(void __iomem *base)
> +{
> + void __iomem *addr = base + CIF_MI_CTRL;
> +
> + writel(CIF_MI_CTRL_RAW_ENABLE | readl(addr), addr);
> +}
> +
> +static inline void mi_ctrl_mpraw_disable(void __iomem *base)
> +{
> + void __iomem *addr = base + CIF_MI_CTRL;
> +
> + writel(~CIF_MI_CTRL_RAW_ENABLE & readl(addr), addr);
> +}
> +
> +static inline void mp_mi_ctrl_autoupdate_en(void __iomem *base)
> +{
> + void __iomem *addr = base + CIF_MI_CTRL;
> +
> + writel(readl(addr) | CIF_MI_MP_AUTOUPDATE_ENABLE, addr);
> +}
> +
> +static inline void sp_mi_ctrl_autoupdate_en(void __iomem *base)
> +{
> + void __iomem *addr = base + CIF_MI_CTRL;
> +
> + writel(readl(addr) | CIF_MI_SP_AUTOUPDATE_ENABLE, addr);
> +}
> +
> +static inline void force_cfg_update(void __iomem * base)
> +{
> + writel(CIF_MI_INIT_SOFT_UPD, base + CIF_MI_INIT);
> +}
> +
> +static inline u32 mi_get_masked_int_status(void __iomem *base)
> +{
> + return readl(base + CIF_MI_MIS);
> +}
> +
> +#endif /* _RKISP1_REGS_H */
> diff --git a/drivers/media/platform/rockchip/isp1/rkisp1.c b/drivers/media/platform/rockchip/isp1/rkisp1.c
> new file mode 100644
> index 000000000000..98be90f4d24a
> --- /dev/null
> +++ b/drivers/media/platform/rockchip/isp1/rkisp1.c
> @@ -0,0 +1,1230 @@
> +/*
> + * Rockchip isp1 driver
> + *
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + *
> + * This software is available to you under a choice of one of two
> + * licenses. You may choose to be licensed under the terms of the GNU
> + * General Public License (GPL) Version 2, available from the file
> + * COPYING in the main directory of this source tree, or the
> + * OpenIB.org BSD license below:
> + *
> + * Redistribution and use in source and binary forms, with or
> + * without modification, are permitted provided that the following
> + * conditions are met:
> + *
> + * - Redistributions of source code must retain the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer.
> + *
> + * - Redistributions in binary form must reproduce the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer in the documentation and/or other materials
> + * provided with the distribution.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#include <linux/iopoll.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/videodev2.h>
> +#include <linux/vmalloc.h>
> +#include <media/v4l2-event.h>
> +#include "capture.h"
> +#include "regs.h"
> +#include "rkisp1.h"
> +
> +/* TODO: define the isp frame size constrains */
> +#define CIF_ISP_INPUT_W_MAX 4032
> +#define CIF_ISP_INPUT_H_MAX 3024
> +#define CIF_ISP_INPUT_W_MIN 32
> +#define CIF_ISP_INPUT_H_MIN 32
> +#define CIF_ISP_OUTPUT_W_MAX CIF_ISP_INPUT_W_MAX
> +#define CIF_ISP_OUTPUT_H_MAX CIF_ISP_INPUT_H_MAX
> +#define CIF_ISP_OUTPUT_W_MIN CIF_ISP_INPUT_W_MIN
> +#define CIF_ISP_OUTPUT_H_MIN CIF_ISP_INPUT_H_MIN
> +
> +/*
> + * Cropping regions of ISP
> + *
> + * +---------------------------------------------------------+
> + * | Sensor image |
> + * | +---------------------------------------------------+ |
> + * | | ISP_ACQ (for black level) | |
> + * | | in_frm | |
> + * | | +--------------------------------------------+ | |
> + * | | | ISP_OUT | | |
> + * | | | in_crop | | |
> + * | | | +---------------------------------+ | | |
> + * | | | | ISP_IS | | | |
> + * | | | | rkisp1_isp_subdev: out_crop | | | |
> + * | | | +---------------------------------+ | | |
> + * | | +--------------------------------------------+ | |
> + * | +---------------------------------------------------+ |
> + * +---------------------------------------------------------+
> + */
> +
> +static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd)
> +{
> + struct media_pad *local, *remote;
> + struct media_entity *sensor_me;
> +
> + local = &sd->entity.pads[RKISP1_ISP_PAD_SINK];
> + remote = media_entity_remote_pad(local);
> + if (!remote) {
> + v4l2_warn(sd, "No link between dphy and sensor\n");
> + return NULL;
> + }
> +
> + sensor_me = media_entity_remote_pad(local)->entity;
> + return media_entity_to_v4l2_subdev(sensor_me);
> +}
> +
> +static struct rkisp1_sensor_info *sd_to_sensor(struct rkisp1_device *dev,
> + struct v4l2_subdev *sd)
> +{
> + int i;
> +
> + for (i = 0; i < dev->num_sensors; ++i)
> + if (dev->sensors[i].sd == sd)
> + return &dev->sensors[i];
> +
> + return NULL;
> +}
> +
> +/*
> + * This should only be called when configuring CIF
> + * or at the frame end interrupt
> + */
> +static void rkisp1_config_ism(struct rkisp1_device *dev)
> +{
> + void __iomem *base = dev->base_addr;
> + struct v4l2_rect *out_crop = &dev->isp_sdev.out_crop;
> + u32 val;
> +
> + writel(0, base + CIF_ISP_IS_RECENTER);
> + writel(0, base + CIF_ISP_IS_MAX_DX);
> + writel(0, base + CIF_ISP_IS_MAX_DY);
> + writel(0, base + CIF_ISP_IS_DISPLACE);
> + writel(out_crop->left, base + CIF_ISP_IS_H_OFFS);
> + writel(out_crop->top, base + CIF_ISP_IS_V_OFFS);
> + writel(out_crop->width, base + CIF_ISP_IS_H_SIZE);
> + writel(out_crop->height, base + CIF_ISP_IS_V_SIZE);
> +
> + /* IS(Image Stabilization) is always on, working as output crop */
> + writel(1, base + CIF_ISP_IS_CTRL);
> + val = readl(base + CIF_ISP_CTRL);
> + val |= CIF_ISP_CTRL_ISP_CFG_UPD;
> + writel(val, base + CIF_ISP_CTRL);
> +}
> +
> +static int rkisp1_config_isp(struct rkisp1_device *dev)
> +{
> + struct ispsd_in_fmt *in_fmt;
> + struct ispsd_out_fmt *out_fmt;
> + struct v4l2_mbus_framefmt *in_frm;
> + struct v4l2_rect *out_crop, *in_crop;
> + struct rkisp1_sensor_info *sensor;
> + void __iomem *base = dev->base_addr;
> + u32 isp_ctrl;
> + u32 irq_mask = 0;
> + u32 signal = 0;
> + u32 acq_mult;
> + u32 val;
> +
> + sensor = dev->active_sensor;
> + in_frm = &dev->isp_sdev.in_frm;
> + in_fmt = &dev->isp_sdev.in_fmt;
> + out_fmt = &dev->isp_sdev.out_fmt;
> + out_crop = &dev->isp_sdev.out_crop;
> + in_crop = &dev->isp_sdev.in_crop;
> + val = readl(base + CIF_ICCL);
> + writel(val | CIF_ICCL_ISP_CLK, base + CIF_ICCL);
> +
> + if (in_fmt->fmt_type == FMT_BAYER) {
> + acq_mult = 1;
> + if (out_fmt->fmt_type == FMT_BAYER) {
> + if (sensor->mbus.type == V4L2_MBUS_BT656)
> + isp_ctrl =
> + CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656;
> + else
> + isp_ctrl =
> + CIF_ISP_CTRL_ISP_MODE_RAW_PICT;
> + } else {
> + writel(CIF_ISP_DEMOSAIC_TH(0xc),
> + base + CIF_ISP_DEMOSAIC);
> +
> + if (sensor->mbus.type == V4L2_MBUS_BT656)
> + isp_ctrl = CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656;
> + else
> + isp_ctrl = CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601;
> + }
> + } else if (in_fmt->fmt_type == FMT_YUV) {
> + acq_mult = 2;
> + if (sensor->mbus.type == V4L2_MBUS_CSI2) {
> + isp_ctrl = CIF_ISP_CTRL_ISP_MODE_ITU601;
> + } else {
> + if (sensor->mbus.type == V4L2_MBUS_BT656)
> + isp_ctrl = CIF_ISP_CTRL_ISP_MODE_ITU656;
> + else
> + isp_ctrl = CIF_ISP_CTRL_ISP_MODE_ITU601;
> +
> + }
> +
> + irq_mask |= CIF_ISP_DATA_LOSS;
> + }
> +
> + /* Set up input acquisition properties */
> + if (sensor->mbus.type == V4L2_MBUS_BT656 ||
> + sensor->mbus.type == V4L2_MBUS_PARALLEL) {
> + if (sensor->mbus.flags &
> + V4L2_MBUS_PCLK_SAMPLE_RISING)
> + signal = CIF_ISP_ACQ_PROP_POS_EDGE;
> + }
> +
> + if (sensor->mbus.type == V4L2_MBUS_PARALLEL) {
> + if (sensor->mbus.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
> + signal |= CIF_ISP_ACQ_PROP_VSYNC_LOW;
> +
> + if (sensor->mbus.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
> + signal |= CIF_ISP_ACQ_PROP_HSYNC_LOW;
> + }
> +
> + writel(isp_ctrl, base + CIF_ISP_CTRL);
> + writel(signal | in_fmt->yuv_seq |
> + CIF_ISP_ACQ_PROP_BAYER_PAT(in_fmt->bayer_pat) |
> + CIF_ISP_ACQ_PROP_FIELD_SEL_ALL, base + CIF_ISP_ACQ_PROP);
> + writel(0, base + CIF_ISP_ACQ_NR_FRAMES);
> +
> + /* Acquisition Size */
> + writel(0, base + CIF_ISP_ACQ_H_OFFS);
> + writel(0, base + CIF_ISP_ACQ_V_OFFS);
> + writel(acq_mult * in_frm->width, base + CIF_ISP_ACQ_H_SIZE);
> + writel(in_frm->height, base + CIF_ISP_ACQ_V_SIZE);
> +
> + /* ISP Out Area */
> + writel(in_crop->left, base + CIF_ISP_OUT_H_OFFS);
> + writel(in_crop->top, base + CIF_ISP_OUT_V_OFFS);
> + writel(in_crop->width, base + CIF_ISP_OUT_H_SIZE);
> + writel(in_crop->height, base + CIF_ISP_OUT_V_SIZE);
> +
> + /* interrupt mask */
> + irq_mask |= CIF_ISP_FRAME | CIF_ISP_V_START | CIF_ISP_PIC_SIZE_ERROR |
> + CIF_ISP_FRAME_IN;
> + writel(irq_mask, base + CIF_ISP_IMSC);
> +
> + if (out_fmt->fmt_type == FMT_BAYER)
> + rkisp1_disable_isp(&dev->params_vdev);
> + else
> + rkisp1_configure_isp(&dev->params_vdev, in_fmt,
> + V4L2_QUANTIZATION_FULL_RANGE);
> +
> + return 0;
> +}
> +
> +static int rkisp1_config_dvp(struct rkisp1_device *dev)
> +{
> + struct ispsd_in_fmt *in_fmt = &dev->isp_sdev.in_fmt;
> + void __iomem *base = dev->base_addr;
> + u32 val, input_sel;
> +
> + switch (in_fmt->bus_width) {
> + case 8:
> + input_sel = CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO;
> + break;
> + case 10:
> + input_sel = CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO;
> + break;
> + case 12:
> + input_sel = CIF_ISP_ACQ_PROP_IN_SEL_12B;
> + break;
> + default:
> + v4l2_err(&dev->v4l2_dev, "Invalid bus width\n");
> + return -EINVAL;
> + }
> +
> + val = readl(base + CIF_ISP_ACQ_PROP);
> + writel(val | input_sel, base + CIF_ISP_ACQ_PROP);
> +
> + return 0;
> +}
> +
> +static int rkisp1_config_mipi(struct rkisp1_device *dev)
> +{
> + u32 mipi_ctrl, val;
> + void __iomem *base = dev->base_addr;
> + struct ispsd_in_fmt *in_fmt = &dev->isp_sdev.in_fmt;
> + struct rkisp1_sensor_info *sensor = dev->active_sensor;
> + int lanes;
> +
> + switch (sensor->mbus.flags & V4L2_MBUS_CSI2_LANES) {
> + case V4L2_MBUS_CSI2_4_LANE:
> + lanes = 4;
> + break;
> + case V4L2_MBUS_CSI2_3_LANE:
> + lanes = 3;
> + break;
> + case V4L2_MBUS_CSI2_2_LANE:
> + lanes = 2;
> + break;
> + case V4L2_MBUS_CSI2_1_LANE:
> + lanes = 1;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + val = readl(base + CIF_ICCL);
> + writel(val | CIF_ICCL_MIPI_CLK, base + CIF_ICCL);
> +
> + mipi_ctrl = CIF_MIPI_CTRL_NUM_LANES(lanes - 1) |
> + CIF_MIPI_CTRL_SHUTDOWNLANES(0xf) |
> + CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP |
> + CIF_MIPI_CTRL_CLOCKLANE_ENA;
> +
> + writel(mipi_ctrl, base + CIF_MIPI_CTRL);
> +
> + /* Configure Data Type and Virtual Channel */
> + writel(CIF_MIPI_DATA_SEL_DT(in_fmt->mipi_dt) | CIF_MIPI_DATA_SEL_VC(0),
> + base + CIF_MIPI_IMG_DATA_SEL);
> +
> + /* Clear MIPI interrupts */
> + writel(~0, base + CIF_MIPI_ICR);
> + /*
> + * Disable CIF_MIPI_ERR_DPHY interrupt here temporary for
> + * isp bus may be dead when switch isp.
> + */
> + writel(CIF_MIPI_FRAME_END | CIF_MIPI_ERR_CSI | CIF_MIPI_ERR_DPHY |
> + CIF_MIPI_SYNC_FIFO_OVFLW(0x03) | CIF_MIPI_ADD_DATA_OVFLW,
> + base + CIF_MIPI_IMSC);
> +
> + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev, "\n MIPI_CTRL 0x%08x\n"
> + " MIPI_IMG_DATA_SEL 0x%08x\n"
> + " MIPI_STATUS 0x%08x\n"
> + " MIPI_IMSC 0x%08x\n",
> + readl(base + CIF_MIPI_CTRL),
> + readl(base + CIF_MIPI_IMG_DATA_SEL),
> + readl(base + CIF_MIPI_STATUS),
> + readl(base + CIF_MIPI_IMSC));
> +
> + return 0;
> +}
> +
> +static int rkisp1_config_path(struct rkisp1_device *dev)
> +{
> + int ret = 0;
> + struct rkisp1_sensor_info *sensor = dev->active_sensor;
> + u32 dpcl = readl(dev->base_addr + CIF_VI_DPCL);
> +
> + if (sensor->mbus.type == V4L2_MBUS_BT656 ||
> + sensor->mbus.type == V4L2_MBUS_PARALLEL) {
> + ret = rkisp1_config_dvp(dev);
> + dpcl |= CIF_VI_DPCL_IF_SEL_PARALLEL;
> + } else if (sensor->mbus.type == V4L2_MBUS_CSI2) {
> + ret = rkisp1_config_mipi(dev);
> + dpcl |= CIF_VI_DPCL_IF_SEL_MIPI;
> + }
> +
> + writel(dpcl, dev->base_addr + CIF_VI_DPCL);
> +
> + return ret;
> +}
> +
> +static int rkisp1_config_cif(struct rkisp1_device *dev)
> +{
> + int ret = 0;
> + u32 cif_id;
> +
> + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
> + "SP state = %d, MP state = %d\n",
> + dev->stream[RKISP1_STREAM_SP].state,
> + dev->stream[RKISP1_STREAM_MP].state);
> +
> + cif_id = readl(dev->base_addr + CIF_VI_ID);
> + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev, "CIF_ID 0x%08x\n", cif_id);
> +
> + ret = rkisp1_config_isp(dev);
> + if (ret < 0)
> + return ret;
> + ret = rkisp1_config_path(dev);
> + if (ret < 0)
> + return ret;
> + rkisp1_config_ism(dev);
> +
> + return 0;
> +}
> +
> +static int rkisp1_isp_stop(struct rkisp1_device *dev)
> +{
> + void __iomem *base = dev->base_addr;
> + u32 val;
> +
> + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
> + "SP state = %d, MP state = %d\n",
> + dev->stream[RKISP1_STREAM_SP].state,
> + dev->stream[RKISP1_STREAM_MP].state);
> +
> + /*
> + * ISP(mi) stop in mi frame end -> Stop ISP(mipi) ->
> + * Stop ISP(isp) ->wait for ISP isp off
> + */
> + /* stop and clear MI, MIPI, and ISP interrupts */
> + writel(0, base + CIF_MIPI_IMSC);
> + writel(~0, base + CIF_MIPI_ICR);
> +
> + writel(0, base + CIF_ISP_IMSC);
> + writel(~0, base + CIF_ISP_ICR);
> +
> + writel(0, base + CIF_MI_IMSC);
> + writel(~0, base + CIF_MI_ICR);
> + val = readl(base + CIF_MIPI_CTRL);
> + writel(val & (~CIF_MIPI_CTRL_OUTPUT_ENA), base + CIF_MIPI_CTRL);
> + /* stop ISP */
> + val = readl(base + CIF_ISP_CTRL);
> + val &= ~(CIF_ISP_CTRL_ISP_INFORM_ENABLE | CIF_ISP_CTRL_ISP_ENABLE);
> + writel(val, base + CIF_ISP_CTRL);
> +
> + val = readl(base + CIF_ISP_CTRL);
> + writel(val | CIF_ISP_CTRL_ISP_CFG_UPD, base + CIF_ISP_CTRL);
> +
> + readx_poll_timeout(readl, base + CIF_ISP_RIS,
> + val, val & CIF_ISP_OFF, 20, 100);
> + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
> + "state(MP:%d, SP:%d), MI_CTRL:%x, ISP_CTRL:%x, MIPI_CTRL:%x\n",
> + dev->stream[RKISP1_STREAM_SP].state,
> + dev->stream[RKISP1_STREAM_MP].state,
> + readl(base + CIF_MI_CTRL),
> + readl(base + CIF_ISP_CTRL),
> + readl(base + CIF_MIPI_CTRL));
> +
> + writel(CIF_IRCL_MIPI_SW_RST | CIF_IRCL_ISP_SW_RST, base + CIF_IRCL);
> + writel(0x0, base + CIF_IRCL);
> +
> + return 0;
> +}
> +
> +static int rkisp1_isp_start(struct rkisp1_device *dev)
> +{
> + struct rkisp1_sensor_info *sensor = dev->active_sensor;
> + void __iomem *base = dev->base_addr;
> + u32 val;
> +
> + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
> + "SP state = %d, MP state = %d\n",
> + dev->stream[RKISP1_STREAM_SP].state,
> + dev->stream[RKISP1_STREAM_MP].state);
> +
> + /* Activate MIPI */
> + if (sensor->mbus.type == V4L2_MBUS_CSI2) {
> + val = readl(base + CIF_MIPI_CTRL);
> + writel(val | CIF_MIPI_CTRL_OUTPUT_ENA, base + CIF_MIPI_CTRL);
> + }
> + /* Activate ISP */
> + val = readl(base + CIF_ISP_CTRL);
> + val |= CIF_ISP_CTRL_ISP_CFG_UPD | CIF_ISP_CTRL_ISP_ENABLE |
> + CIF_ISP_CTRL_ISP_INFORM_ENABLE;
> + writel(val, base + CIF_ISP_CTRL);
> +
> + /* TODO: Is the 1000us too long?
> + * CIF spec says to wait for sufficient time after enabling
> + * the MIPI interface and before starting the sensor output.
> + */
> + usleep_range(1000, 1200);
> +
> + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
> + "SP state = %d, MP state = %d MI_CTRL 0x%08x\n"
> + " ISP_CTRL 0x%08x MIPI_CTRL 0x%08x\n",
> + dev->stream[RKISP1_STREAM_SP].state,
> + dev->stream[RKISP1_STREAM_MP].state,
> + readl(base + CIF_MI_CTRL),
> + readl(base + CIF_ISP_CTRL),
> + readl(base + CIF_MIPI_CTRL));
> +
> + return 0;
> +}
> +
> +static const struct ispsd_in_fmt rkisp1_isp_input_formats[] = {
> + {
> + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
> + .fmt_type = FMT_BAYER,
> + .mipi_dt = CIF_CSI2_DT_RAW10,
> + .bayer_pat = RAW_BGGR,
> + .bus_width = 10,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
> + .fmt_type = FMT_BAYER,
> + .mipi_dt = CIF_CSI2_DT_RAW10,
> + .bayer_pat = RAW_RGGB,
> + .bus_width = 10,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
> + .fmt_type = FMT_BAYER,
> + .mipi_dt = CIF_CSI2_DT_RAW10,
> + .bayer_pat = RAW_GBRG,
> + .bus_width = 10,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
> + .fmt_type = FMT_BAYER,
> + .mipi_dt = CIF_CSI2_DT_RAW10,
> + .bayer_pat = RAW_GRBG,
> + .bus_width = 10,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
> + .fmt_type = FMT_BAYER,
> + .mipi_dt = CIF_CSI2_DT_RAW12,
> + .bayer_pat = RAW_RGGB,
> + .bus_width = 12,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
> + .fmt_type = FMT_BAYER,
> + .mipi_dt = CIF_CSI2_DT_RAW12,
> + .bayer_pat = RAW_BGGR,
> + .bus_width = 12,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
> + .fmt_type = FMT_BAYER,
> + .mipi_dt = CIF_CSI2_DT_RAW12,
> + .bayer_pat = RAW_GBRG,
> + .bus_width = 12,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
> + .fmt_type = FMT_BAYER,
> + .mipi_dt = CIF_CSI2_DT_RAW12,
> + .bayer_pat = RAW_GRBG,
> + .bus_width = 12,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
> + .fmt_type = FMT_BAYER,
> + .mipi_dt = CIF_CSI2_DT_RAW8,
> + .bayer_pat = RAW_RGGB,
> + .bus_width = 8,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
> + .fmt_type = FMT_BAYER,
> + .mipi_dt = CIF_CSI2_DT_RAW8,
> + .bayer_pat = RAW_BGGR,
> + .bus_width = 8,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
> + .fmt_type = FMT_BAYER,
> + .mipi_dt = CIF_CSI2_DT_RAW8,
> + .bayer_pat = RAW_GBRG,
> + .bus_width = 8,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
> + .fmt_type = FMT_BAYER,
> + .mipi_dt = CIF_CSI2_DT_RAW8,
> + .bayer_pat = RAW_GRBG,
> + .bus_width = 8,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_YUYV8_1X16,
> + .fmt_type = FMT_YUV,
> + .mipi_dt = CIF_CSI2_DT_YUV422_8b,
> + .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
> + .bus_width = 16,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_YVYU8_1X16,
> + .fmt_type = FMT_YUV,
> + .mipi_dt = CIF_CSI2_DT_YUV422_8b,
> + .yuv_seq = CIF_ISP_ACQ_PROP_YCRYCB,
> + .bus_width = 16,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_UYVY8_1X16,
> + .fmt_type = FMT_YUV,
> + .mipi_dt = CIF_CSI2_DT_YUV422_8b,
> + .yuv_seq = CIF_ISP_ACQ_PROP_CBYCRY,
> + .bus_width = 16,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_VYUY8_1X16,
> + .fmt_type = FMT_YUV,
> + .mipi_dt = CIF_CSI2_DT_YUV422_8b,
> + .yuv_seq = CIF_ISP_ACQ_PROP_CRYCBY,
> + .bus_width = 16,
> + },
> +};
> +
> +static const struct ispsd_out_fmt rkisp1_isp_output_formats[] = {
> + {
> + .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
> + .fmt_type = FMT_YUV,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
> + .fmt_type = FMT_BAYER,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
> + .fmt_type = FMT_BAYER,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
> + .fmt_type = FMT_BAYER,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
> + .fmt_type = FMT_BAYER,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
> + .fmt_type = FMT_BAYER,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
> + .fmt_type = FMT_BAYER,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
> + .fmt_type = FMT_BAYER,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
> + .fmt_type = FMT_BAYER,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
> + .fmt_type = FMT_BAYER,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
> + .fmt_type = FMT_BAYER,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
> + .fmt_type = FMT_BAYER,
> + }, {
> + .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
> + .fmt_type = FMT_BAYER,
> + },
> +};
> +
> +static const struct ispsd_in_fmt *find_in_fmt(u32 mbus_code)
> +{
> + const struct ispsd_in_fmt *fmt;
> + int i, array_size = ARRAY_SIZE(rkisp1_isp_input_formats);
> +
> + for (i = 0; i < array_size; i++) {
> + fmt = &rkisp1_isp_input_formats[i];
> + if (fmt->mbus_code == mbus_code)
> + return fmt;
> + }
> +
> + return NULL;
> +}
> +
> +static const struct ispsd_out_fmt *find_out_fmt(u32 mbus_code)
> +{
> + const struct ispsd_out_fmt *fmt;
> + int i, array_size = ARRAY_SIZE(rkisp1_isp_output_formats);
> +
> + for (i = 0; i < array_size; i++) {
> + fmt = &rkisp1_isp_output_formats[i];
> + if (fmt->mbus_code == mbus_code)
> + return fmt;
> + }
> +
> + return NULL;
> +}
> +
> +static int rkisp1_isp_sd_enum_mbus_code(struct v4l2_subdev *sd,
> + struct v4l2_subdev_pad_config *cfg,
> + struct v4l2_subdev_mbus_code_enum *code)
> +{
> + int i = code->index;
> +
> + if (code->pad == RKISP1_ISP_PAD_SINK) {
> + if (i >= ARRAY_SIZE(rkisp1_isp_input_formats))
> + return -EINVAL;
> + code->code = rkisp1_isp_input_formats[i].mbus_code;
> + } else {
> + if (i >= ARRAY_SIZE(rkisp1_isp_output_formats))
> + return -EINVAL;
> + code->code = rkisp1_isp_output_formats[i].mbus_code;
> + }
> +
> + return 0;
> +}
> +
> +#define sd_to_isp_sd(_sd) container_of(_sd, struct rkisp1_isp_subdev, sd)
> +static int rkisp1_isp_sd_get_fmt(struct v4l2_subdev *sd,
> + struct v4l2_subdev_pad_config *cfg,
> + struct v4l2_subdev_format *fmt)
> +{
> + struct v4l2_mbus_framefmt *mf = &fmt->format;
> + struct rkisp1_isp_subdev *isp_sd = sd_to_isp_sd(sd);
> +
> + if ((fmt->pad != RKISP1_ISP_PAD_SINK) &&
> + (fmt->pad != RKISP1_ISP_PAD_SOURCE_PATH))
> + return -EINVAL;
> +
> + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
> + mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
> + fmt->format = *mf;
> + return 0;
> + }
> +
> + if (fmt->pad == RKISP1_ISP_PAD_SINK) {
> + *mf = isp_sd->in_frm;
> + } else if (fmt->pad == RKISP1_ISP_PAD_SOURCE_PATH) {
> + *mf = isp_sd->in_frm;
> + mf->width = isp_sd->out_crop.width;
> + mf->height = isp_sd->out_crop.height;
> + }
> + mf->field = V4L2_FIELD_NONE;
> +
> + return 0;
> +}
> +
> +static void rkisp1_isp_sd_try_fmt(struct v4l2_subdev *sd,
> + unsigned int pad,
> + struct v4l2_mbus_framefmt *fmt)
> +{
> + struct rkisp1_device *isp_dev = sd_to_isp_dev(sd);
> + struct rkisp1_isp_subdev *isp_sd = &isp_dev->isp_sdev;
> + const struct ispsd_in_fmt *in_fmt;
> + const struct ispsd_out_fmt *out_fmt;
> +
> + switch (pad) {
> + case RKISP1_ISP_PAD_SINK:
> + in_fmt = find_in_fmt(fmt->code);
> + if (in_fmt) {
> + fmt->code = in_fmt->mbus_code;
> + fmt->colorspace = rkisp1_get_colorspace(in_fmt->fmt_type);
Just propagate the colorspace information from the incoming mediabus format. You
can't guess it based on the mbus_code.
> + } else {
> + fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
> + fmt->colorspace = V4L2_COLORSPACE_SRGB;
> + }
> + fmt->width = clamp_t(u32, fmt->width, CIF_ISP_INPUT_W_MIN,
> + CIF_ISP_INPUT_W_MAX);
> + fmt->height = clamp_t(u32, fmt->height, CIF_ISP_INPUT_H_MIN,
> + CIF_ISP_INPUT_H_MAX);
> + break;
> + case RKISP1_ISP_PAD_SOURCE_PATH:
> + out_fmt = find_out_fmt(fmt->code);
> + if (out_fmt) {
> + fmt->code = out_fmt->mbus_code;
> + fmt->colorspace = rkisp1_get_colorspace(out_fmt->fmt_type);
Ditto.
> + } else {
> + fmt->code = MEDIA_BUS_FMT_YUYV8_2X8;
> + fmt->colorspace = V4L2_COLORSPACE_JPEG;
> + }
> + /* Size is set in s_selection */
> + fmt->width = isp_sd->out_crop.width;
> + fmt->height = isp_sd->out_crop.height;
> + break;
> + }
> +
> + fmt->field = V4L2_FIELD_NONE;
> +}
> +
> +static int rkisp1_isp_sd_set_fmt(struct v4l2_subdev *sd,
> + struct v4l2_subdev_pad_config *cfg,
> + struct v4l2_subdev_format *fmt)
> +{
> + struct rkisp1_device *isp_dev = sd_to_isp_dev(sd);
> + struct rkisp1_isp_subdev *isp_sd = &isp_dev->isp_sdev;
> + struct v4l2_mbus_framefmt *mf = &fmt->format;
> +
> + if ((fmt->pad != RKISP1_ISP_PAD_SINK) &&
> + (fmt->pad != RKISP1_ISP_PAD_SOURCE_PATH))
> + return -EINVAL;
> +
> + rkisp1_isp_sd_try_fmt(sd, fmt->pad, mf);
> +
> + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
> + struct v4l2_mbus_framefmt *try_mf;
> +
> + mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
> + *try_mf = *mf;
> + return 0;
> + }
> +
> + if (fmt->pad == RKISP1_ISP_PAD_SINK) {
> + const struct ispsd_in_fmt *in_fmt;
> +
> + in_fmt = find_in_fmt(mf->code);
> + isp_sd->in_fmt = *in_fmt;
> + isp_sd->in_frm = *mf;
> + } else if (fmt->pad == RKISP1_ISP_PAD_SOURCE_PATH) {
> + const struct ispsd_out_fmt *out_fmt;
> +
> + /* Ignore width/height */
> + out_fmt = find_out_fmt(mf->code);
> + isp_sd->out_fmt = *out_fmt;
> + }
> +
> + return 0;
> +}
> +
> +static void rkisp1_isp_sd_try_crop(struct v4l2_subdev *sd,
> + struct v4l2_subdev_pad_config *cfg,
> + struct v4l2_subdev_selection *sel)
> +{
> + struct rkisp1_isp_subdev *isp_sd = sd_to_isp_sd(sd);
> + struct v4l2_mbus_framefmt in_frm = isp_sd->in_frm;
> + struct v4l2_rect in_crop = isp_sd->in_crop;
> + struct v4l2_rect *input = &sel->r;
> +
> + if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
> + in_frm = *v4l2_subdev_get_try_format(sd, cfg, RKISP1_ISP_PAD_SINK);
> + in_crop = *v4l2_subdev_get_try_crop(sd, cfg, RKISP1_ISP_PAD_SINK);
> + }
> +
> + input->left = ALIGN(input->left, 2);
> + input->width = ALIGN(input->width, 2);
> +
> + if (sel->pad == RKISP1_ISP_PAD_SINK) {
> + input->left = clamp_t(u32, input->left, 0, in_frm.width);
> + input->top = clamp_t(u32, input->top, 0, in_frm.height);
> + input->width = clamp_t(u32, input->width, CIF_ISP_INPUT_W_MIN,
> + in_frm.width - input->left);
> + input->height = clamp_t(u32, input->height,
> + CIF_ISP_INPUT_H_MIN,
> + in_frm.height - input->top);
> + } else if (sel->pad == RKISP1_ISP_PAD_SOURCE_PATH) {
> + input->left = clamp_t(u32, input->left, 0, in_crop.width);
> + input->top = clamp_t(u32, input->top, 0, in_crop.height);
> + input->width = clamp_t(u32, input->width, CIF_ISP_OUTPUT_W_MIN,
> + in_crop.width - input->left);
> + input->height = clamp_t(u32, input->height, CIF_ISP_OUTPUT_H_MIN,
> + in_crop.height - input->top);
> + }
> +}
> +
> +static int rkisp1_isp_sd_get_selection(struct v4l2_subdev *sd,
> + struct v4l2_subdev_pad_config *cfg,
> + struct v4l2_subdev_selection *sel)
> +{
> + struct rkisp1_isp_subdev *isp_sd = sd_to_isp_sd(sd);
> +
> + if (sel->pad != RKISP1_ISP_PAD_SOURCE_PATH &&
> + sel->pad != RKISP1_ISP_PAD_SINK)
> + return -EINVAL;
Just checking: the hardware can crop both on the sink (incoming) side and on
the source (outgoing) side? I would expect it to be just on the sink side.
> +
> + if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
> + struct v4l2_rect *try_sel;
> +
> + try_sel = v4l2_subdev_get_try_crop(sd, cfg, sel->pad);
> + sel->r = *try_sel;
> + return 0;
> + }
> +
> + switch (sel->target) {
> + case V4L2_SEL_TGT_CROP_BOUNDS:
> + if (sel->pad == RKISP1_ISP_PAD_SINK) {
> + sel->r.height = isp_sd->in_frm.height;
> + sel->r.width = isp_sd->in_frm.width;
> + sel->r.left = 0;
> + sel->r.top = 0;
> + } else {
> + sel->r = isp_sd->in_crop;
> + }
> + break;
> + case V4L2_SEL_TGT_CROP:
> + if (sel->pad == RKISP1_ISP_PAD_SINK)
> + sel->r = isp_sd->in_crop;
> + else
> + sel->r = isp_sd->out_crop;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int rkisp1_isp_sd_set_selection(struct v4l2_subdev *sd,
> + struct v4l2_subdev_pad_config *cfg,
> + struct v4l2_subdev_selection *sel)
> +{
> + struct rkisp1_isp_subdev *isp_sd = sd_to_isp_sd(sd);
> +
> + if (sel->pad != RKISP1_ISP_PAD_SOURCE_PATH &&
> + sel->pad != RKISP1_ISP_PAD_SINK)
> + return -EINVAL;
> + if (sel->target != V4L2_SEL_TGT_CROP)
> + return -EINVAL;
> +
> + rkisp1_isp_sd_try_crop(sd, cfg, sel);
> +
> + if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
> + struct v4l2_rect *try_sel;
> +
> + try_sel = v4l2_subdev_get_try_crop(sd, cfg, sel->pad);
> + *try_sel = sel->r;
> + return 0;
> + }
> +
> + if (sel->pad == RKISP1_ISP_PAD_SINK)
> + isp_sd->in_crop = sel->r;
> + else
> + isp_sd->out_crop = sel->r;
> +
> + return 0;
> +}
> +
> +static int rkisp1_isp_sd_s_stream(struct v4l2_subdev *sd, int on)
> +{
> + struct rkisp1_device *isp_dev = sd_to_isp_dev(sd);
> + struct rkisp1_sensor_info *sensor;
> + struct v4l2_subdev *sensor_sd;
> + int ret = 0;
> +
> + if (!on)
> + return rkisp1_isp_stop(isp_dev);
> +
> + sensor_sd = get_remote_sensor(sd);
> + if (!sensor_sd)
> + return -ENODEV;
> +
> + sensor = sd_to_sensor(isp_dev, sensor_sd);
> + /*
> + * Update sensor bus configuration. This is only effective
> + * for sensors chained off an external CSI2 PHY.
> + */
> + ret = v4l2_subdev_call(sensor->sd, video, g_mbus_config,
> + &sensor->mbus);
What do you need g_mbus_config for? We have plans to remove this op in the
future.
> + if (ret && ret != -ENOIOCTLCMD)
> + return ret;
> + isp_dev->active_sensor = sensor;
> +
> + atomic_set(&isp_dev->isp_sdev.frm_sync_seq, 0);
> + ret = rkisp1_config_cif(isp_dev);
> + if (ret < 0)
> + return ret;
> +
> + return rkisp1_isp_start(isp_dev);
> +}
> +
> +static void rkisp1_config_clk(struct rkisp1_device *dev)
> +{
> + u32 val = CIF_ICCL_ISP_CLK | CIF_ICCL_CP_CLK | CIF_ICCL_MRSZ_CLK |
> + CIF_ICCL_SRSZ_CLK | CIF_ICCL_JPEG_CLK | CIF_ICCL_MI_CLK |
> + CIF_ICCL_MIPI_CLK | CIF_ICCL_DCROP_CLK;
> +
> + writel(val, dev->base_addr + CIF_ICCL);
> +}
> +
> +static int rkisp1_isp_sd_s_power(struct v4l2_subdev *sd, int on)
> +{
> + struct rkisp1_device *dev = sd_to_isp_dev(sd);
> + int ret;
> +
> + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
> + "streaming count %d, s_power: %d\n",
> + atomic_read(&dev->poweron_cnt), on);
> +
> + if (on) {
> + ret = pm_runtime_get_sync(dev->dev);
> + if (ret < 0)
> + return ret;
> +
> + /* TODO: Reset the isp would clear iommu too */
> + /* writel(CIF_IRCL_CIF_SW_RST, dev->base_addr + CIF_IRCL); */
> + /* udelay(1); wait at least 10 module clock cycles */
> +
> + rkisp1_config_clk(dev);
> + } else {
> + ret = pm_runtime_put(dev->dev);
> + if (ret < 0)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int rkisp1_subdev_link_validate(struct media_link *link)
> +{
> + if (link->source->index == RKISP1_ISP_PAD_SINK_PARAMS)
> + return 0;
> +
> + return v4l2_subdev_link_validate(link);
> +}
> +
> +static int rkisp1_subdev_fmt_link_validate(struct v4l2_subdev *sd,
> + struct media_link *link,
> + struct v4l2_subdev_format *source_fmt,
> + struct v4l2_subdev_format *sink_fmt)
> +{
> + if (source_fmt->format.code != sink_fmt->format.code)
> + return -EINVAL;
> +
> + /* Crop is available */
> + if (source_fmt->format.width < sink_fmt->format.width ||
> + source_fmt->format.height < sink_fmt->format.height)
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +static void
> +riksp1_isp_queue_event_sof(struct rkisp1_isp_subdev *isp)
> +{
> + struct v4l2_event event = {
> + .type = V4L2_EVENT_FRAME_SYNC,
> + .u.frame_sync.frame_sequence =
> + atomic_inc_return(&isp->frm_sync_seq) - 1,
> + };
> + v4l2_event_queue(isp->sd.devnode, &event);
> +}
> +
> +static int rkisp1_isp_sd_subs_evt(struct v4l2_subdev *sd, struct v4l2_fh *fh,
> + struct v4l2_event_subscription *sub)
> +{
> + if (sub->type != V4L2_EVENT_FRAME_SYNC)
> + return -EINVAL;
> +
> + /* Line number. For now only zero accepted. */
> + if (sub->id != 0)
> + return -EINVAL;
> +
> + return v4l2_event_subscribe(fh, sub, 0, NULL);
> +}
> +
> +static const struct v4l2_subdev_pad_ops rkisp1_isp_sd_pad_ops = {
> + .enum_mbus_code = rkisp1_isp_sd_enum_mbus_code,
> + .get_selection = rkisp1_isp_sd_get_selection,
> + .set_selection = rkisp1_isp_sd_set_selection,
> + .get_fmt = rkisp1_isp_sd_get_fmt,
> + .set_fmt = rkisp1_isp_sd_set_fmt,
> + .link_validate = rkisp1_subdev_fmt_link_validate,
> +};
> +
> +static const struct media_entity_operations rkisp1_isp_sd_media_ops = {
> + .link_validate = rkisp1_subdev_link_validate,
> +};
> +
> +static const struct v4l2_subdev_video_ops rkisp1_isp_sd_video_ops = {
> + .s_stream = rkisp1_isp_sd_s_stream,
> +};
> +
> +static const struct v4l2_subdev_core_ops rkisp1_isp_core_ops = {
> + .subscribe_event = rkisp1_isp_sd_subs_evt,
> + .unsubscribe_event = v4l2_event_subdev_unsubscribe,
> + .s_power = rkisp1_isp_sd_s_power,
> +};
> +
> +static struct v4l2_subdev_ops rkisp1_isp_sd_ops = {
> + .core = &rkisp1_isp_core_ops,
> + .video = &rkisp1_isp_sd_video_ops,
> + .pad = &rkisp1_isp_sd_pad_ops,
> +};
> +
> +static void rkisp1_isp_sd_init_default_fmt(struct rkisp1_isp_subdev *isp_sd)
> +{
> + struct v4l2_mbus_framefmt *in_frm = &isp_sd->in_frm;
> + struct v4l2_rect *in_crop = &isp_sd->in_crop;
> + struct v4l2_rect *out_crop = &isp_sd->out_crop;
> + struct ispsd_in_fmt *in_fmt = &isp_sd->in_fmt;
> + struct ispsd_out_fmt *out_fmt = &isp_sd->out_fmt;
> +
> + *in_fmt = rkisp1_isp_input_formats[0];
> + in_frm->width = RKISP1_DEFAULT_WIDTH;
> + in_frm->height = RKISP1_DEFAULT_HEIGHT;
> + in_frm->colorspace = rkisp1_get_colorspace(in_fmt->fmt_type);
> + in_frm->code = in_fmt->mbus_code;
> +
> + in_crop->width = in_frm->width;
> + in_crop->height = in_frm->height;
> + in_crop->left = 0;
> + in_crop->top = 0;
> +
> + /* propagate to source */
> + *out_crop = *in_crop;
> + *out_fmt = rkisp1_isp_output_formats[0];
> +}
> +
> +int rkisp1_register_isp_subdev(struct rkisp1_device *isp_dev,
> + struct v4l2_device *v4l2_dev)
> +{
> + struct rkisp1_isp_subdev *isp_sdev = &isp_dev->isp_sdev;
> + struct v4l2_subdev *sd = &isp_sdev->sd;
> + int ret;
> +
> + v4l2_subdev_init(sd, &rkisp1_isp_sd_ops);
> + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
> + sd->entity.ops = &rkisp1_isp_sd_media_ops;
> + snprintf(sd->name, sizeof(sd->name), "rkisp1-isp-subdev");
> +
> + isp_sdev->pads[RKISP1_ISP_PAD_SINK].flags =
> + MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
> + isp_sdev->pads[RKISP1_ISP_PAD_SINK_PARAMS].flags = MEDIA_PAD_FL_SINK;
> + isp_sdev->pads[RKISP1_ISP_PAD_SOURCE_PATH].flags = MEDIA_PAD_FL_SOURCE;
> + isp_sdev->pads[RKISP1_ISP_PAD_SOURCE_STATS].flags = MEDIA_PAD_FL_SOURCE;
> + sd->entity.function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN;
> + ret = media_entity_pads_init(&sd->entity, RKISP1_ISP_PAD_MAX,
> + isp_sdev->pads);
> + if (ret < 0)
> + return ret;
> +
> + sd->owner = THIS_MODULE;
> + v4l2_set_subdevdata(sd, isp_dev);
> +
> + sd->grp_id = GRP_ID_ISP;
> + ret = v4l2_device_register_subdev(v4l2_dev, sd);
> + if (ret < 0) {
> + v4l2_err(sd, "Failed to register isp subdev\n");
> + goto err_cleanup_media_entity;
> + }
> +
> + rkisp1_isp_sd_init_default_fmt(isp_sdev);
> +
> + return 0;
> +err_cleanup_media_entity:
> + media_entity_cleanup(&sd->entity);
> + return ret;
> +}
> +
> +void rkisp1_unregister_isp_subdev(struct rkisp1_device *isp_dev)
> +{
> + struct v4l2_subdev *sd = &isp_dev->isp_sdev.sd;
> +
> + v4l2_device_unregister_subdev(sd);
> + media_entity_cleanup(&sd->entity);
> +}
> +
> +static void rkisp1_hw_restart(struct rkisp1_device *dev)
> +{
> + void __iomem *base = dev->base_addr;
> + u32 val;
> +
> + writel(CIF_IRCL_MIPI_SW_RST | CIF_IRCL_ISP_SW_RST | CIF_IRCL_MI_SW_RST,
> + base + CIF_IRCL);
> + writel(0x0, base + CIF_IRCL);
> +
> + /* enable mipi interrupts */
> + writel(CIF_MIPI_FRAME_END | CIF_MIPI_ERR_CSI |
> + CIF_MIPI_ERR_DPHY | CIF_MIPI_SYNC_FIFO_OVFLW(0x03) |
> + CIF_MIPI_ADD_DATA_OVFLW, base + CIF_MIPI_IMSC);
> +
> + writel(0x0, base + CIF_MI_MP_Y_OFFS_CNT_INIT);
> + writel(0x0, base + CIF_MI_MP_CR_OFFS_CNT_INIT);
> + writel(0x0, base + CIF_MI_MP_CB_OFFS_CNT_INIT);
> + writel(0x0, base + CIF_MI_SP_Y_OFFS_CNT_INIT);
> + writel(0x0, base + CIF_MI_SP_CR_OFFS_CNT_INIT);
> + writel(0x0, base + CIF_MI_SP_CB_OFFS_CNT_INIT);
> + val = readl(base + CIF_MI_CTRL);
> + writel(CIF_MI_CTRL_INIT_OFFSET_EN | val, base + CIF_MI_CTRL);
> +
> + /* Enable ISP */
> + val = readl(base + CIF_ISP_CTRL);
> + val |= CIF_ISP_CTRL_ISP_CFG_UPD | CIF_ISP_CTRL_ISP_ENABLE |
> + CIF_ISP_CTRL_ISP_INFORM_ENABLE;
> + writel(val, base + CIF_ISP_CTRL);
> + /* enable MIPI */
> + val = readl(base + CIF_MIPI_CTRL);
> + writel(val | CIF_MIPI_CTRL_OUTPUT_ENA, base + CIF_MIPI_CTRL);
> +}
> +
> +void rkisp1_mipi_isr(unsigned int mis, struct rkisp1_device *dev)
> +{
> + struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
> + void __iomem *base = dev->base_addr;
> + u32 val;
> +
> + writel(~0, base + CIF_MIPI_ICR);
> +
> + /*
> + * Disable DPHY errctrl interrupt, because this dphy
> + * erctrl signal is asserted until the next changes
> + * of line state. This time is may be too long and cpu
> + * is hold in this interrupt.
> + */
> + if (mis & CIF_MIPI_ERR_CTRL(3)) {
> + val = readl(base + CIF_MIPI_IMSC);
> + /*TODO: 0xf - one bit per lane?*/
> + writel(val | ~CIF_MIPI_ERR_CTRL(0x03), base + CIF_MIPI_IMSC);
> + dev->isp_sdev.dphy_errctrl_disabled = true;
> + }
> +
> + /*
> + * Enable DPHY errctrl interrupt again, if mipi have receive
> + * the whole frame without any error.
> + */
> + if (mis == CIF_MIPI_FRAME_END) {
> + /*
> + * Enable DPHY errctrl interrupt again, if mipi have receive
> + * the whole frame without any error.
> + */
> + if (dev->isp_sdev.dphy_errctrl_disabled) {
> + val = readl(base + CIF_MIPI_IMSC);
> + val |= CIF_MIPI_ERR_CTRL(0x03);
> + writel(val, base + CIF_MIPI_IMSC);
> + dev->isp_sdev.dphy_errctrl_disabled = false;
> + }
> + } else {
> + v4l2_warn(v4l2_dev, "MIPI mis error: 0x%08x\n", mis);
> + }
> +}
> +
> +void rkisp1_isp_isr(unsigned int isp_mis, struct rkisp1_device *dev)
> +{
> + void __iomem *base = dev->base_addr;
> + unsigned int isp_mis_tmp = 0;
> + unsigned int isp_err = 0;
> + u32 val;
> +
> + if (isp_mis & CIF_ISP_V_START) {
> + riksp1_isp_queue_event_sof(&dev->isp_sdev);
> +
> + writel(CIF_ISP_V_START, base + CIF_ISP_ICR);
> + isp_mis_tmp = readl(base + CIF_ISP_MIS);
> + if (isp_mis_tmp & CIF_ISP_V_START)
> + v4l2_err(&dev->v4l2_dev, "isp icr v_statr err: 0x%x\n",
> + isp_mis_tmp);
> + }
> +
> + if (isp_mis & (CIF_ISP_DATA_LOSS | CIF_ISP_PIC_SIZE_ERROR)) {
> + if ((isp_mis & CIF_ISP_PIC_SIZE_ERROR)) {
> + /* Clear pic_size_error */
> + writel(CIF_ISP_PIC_SIZE_ERROR, base + CIF_ISP_ICR);
> + isp_err = readl(base + CIF_ISP_ERR);
> + v4l2_err(&dev->v4l2_dev,
> + "CIF_ISP_PIC_SIZE_ERROR (0x%08x)", isp_err);
> + writel(isp_err, base + CIF_ISP_ERR_CLR);
> + } else if ((isp_mis & CIF_ISP_DATA_LOSS)) {
> + /* Clear data_loss */
> + writel(CIF_ISP_DATA_LOSS, base + CIF_ISP_ICR);
> + v4l2_err(&dev->v4l2_dev, "CIF_ISP_DATA_LOSS\n");
> + writel(CIF_ISP_DATA_LOSS, base + CIF_ISP_ICR);
> + }
> +
> + /* TODO: Restart ISP safely */
> + if (0) {
> + val = readl(base + CIF_ISP_CTRL);
> + val &= ~(CIF_ISP_CTRL_ISP_INFORM_ENABLE &
> + CIF_ISP_CTRL_ISP_ENABLE);
> + writel(val, base + CIF_ISP_CTRL);
> + /* isp_update */
> + val = readl(base + CIF_ISP_CTRL);
> + writel(val | CIF_ISP_CTRL_ISP_CFG_UPD, base + CIF_ISP_CTRL);
> + /*TODO: restart hw here is not safe, may cause machine hanging*/
> + rkisp1_hw_restart(dev);
> + }
> + }
> +
> + if (isp_mis & CIF_ISP_FRAME_IN) {
> + writel(CIF_ISP_FRAME_IN, base + CIF_ISP_ICR);
> + isp_mis_tmp = readl(base + CIF_ISP_MIS);
> + if (isp_mis_tmp & CIF_ISP_FRAME_IN)
> + v4l2_err(&dev->v4l2_dev, "isp icr frame_in err: 0x%x\n",
> + isp_mis_tmp);
> + }
> +
> + if (isp_mis & CIF_ISP_FRAME) {
> + u32 isp_ris = 0;
> + /* Clear Frame In (ISP) */
> + writel(CIF_ISP_FRAME, base + CIF_ISP_ICR);
> + isp_mis_tmp = readl(base + CIF_ISP_MIS);
> + if (isp_mis_tmp & CIF_ISP_FRAME)
> + v4l2_err(&dev->v4l2_dev,
> + "isp icr frame end err: 0x%x\n", isp_mis_tmp);
> +
> + isp_ris = readl(base + CIF_ISP_RIS);
> + if (isp_ris & (CIF_ISP_AWB_DONE | CIF_ISP_AFM_FIN |
> + CIF_ISP_EXP_END | CIF_ISP_HIST_MEASURE_RDY))
> + rkisp1_stats_isr(&dev->stats_vdev, isp_ris);
> + }
> +
> + /*
> + * Then update changed configs. Some of them involve
> + * lot of register writes. Do those only one per frame.
> + * Do the updates in the order of the processing flow.
> + */
> + rkisp1_params_isr(&dev->params_vdev, isp_mis);
> +}
> diff --git a/drivers/media/platform/rockchip/isp1/rkisp1.h b/drivers/media/platform/rockchip/isp1/rkisp1.h
> new file mode 100644
> index 000000000000..506b1efd4de8
> --- /dev/null
> +++ b/drivers/media/platform/rockchip/isp1/rkisp1.h
> @@ -0,0 +1,130 @@
> +/*
> + * Rockchip isp1 driver
> + *
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + *
> + * This software is available to you under a choice of one of two
> + * licenses. You may choose to be licensed under the terms of the GNU
> + * General Public License (GPL) Version 2, available from the file
> + * COPYING in the main directory of this source tree, or the
> + * OpenIB.org BSD license below:
> + *
> + * Redistribution and use in source and binary forms, with or
> + * without modification, are permitted provided that the following
> + * conditions are met:
> + *
> + * - Redistributions of source code must retain the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer.
> + *
> + * - Redistributions in binary form must reproduce the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer in the documentation and/or other materials
> + * provided with the distribution.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#ifndef _RKISP1_H
> +#define _RKISP1_H
> +
> +#include <linux/platform_device.h>
> +#include <media/v4l2-fwnode.h>
> +#include "common.h"
> +#include "isp_stats.h"
> +#include "isp_params.h"
> +#include "capture.h"
> +
> +#define RKISP1_MAX_BUS_CLK 8
> +#define RKISP1_MAX_SENSOR 2
> +
> +struct rkisp1_ie_config {
> + /* TODO: bit field ? */
> + unsigned int effect;
> +};
> +
> +enum rkisp1_isp_pad {
> + RKISP1_ISP_PAD_SINK,
> + RKISP1_ISP_PAD_SINK_PARAMS,
> + RKISP1_ISP_PAD_SOURCE_PATH,
> + RKISP1_ISP_PAD_SOURCE_STATS,
> + /* TODO: meta data pad ? */
> + RKISP1_ISP_PAD_MAX
> +};
> +
> +struct rkisp1_isp_subdev {
> + struct v4l2_subdev sd;
> + struct media_pad pads[RKISP1_ISP_PAD_MAX];
> + struct v4l2_ctrl_handler ctrl_handler;
> + struct v4l2_mbus_framefmt in_frm;
> + struct ispsd_in_fmt in_fmt;
> + struct v4l2_rect in_crop;
> + struct ispsd_out_fmt out_fmt;
> + struct v4l2_rect out_crop;
> + bool dphy_errctrl_disabled;
> + atomic_t frm_sync_seq;
> +};
> +
> +struct rkisp1_sensor_info {
> + struct v4l2_subdev *sd;
> + struct v4l2_mbus_config mbus;
> +};
> +
> +struct rkisp1_device {
> + void __iomem *base_addr;
> + int irq;
> + struct device *dev;
> + struct clk *clks[RKISP1_MAX_BUS_CLK];
> + int clk_size;
> + struct v4l2_device v4l2_dev;
> + struct media_device media_dev;
> + struct v4l2_async_notifier notifier;
> + struct v4l2_subdev *subdevs[RKISP1_SD_MAX];
> + struct rkisp1_sensor_info *active_sensor;
> + struct rkisp1_sensor_info sensors[RKISP1_MAX_SENSOR];
> + int num_sensors;
> + spinlock_t writel_verify_lock;
> + struct rkisp1_isp_subdev isp_sdev;
> + struct rkisp1_stream stream[RKISP1_MAX_STREAM];
> + struct rkisp1_isp_stats_vdev stats_vdev;
> + struct rkisp1_isp_params_vdev params_vdev;
> + struct rkisp1_pipeline pipe;
> + atomic_t poweron_cnt;
> +};
> +
> +/* Clean code starts from here */
> +
> +int rkisp1_register_isp_subdev(struct rkisp1_device *isp_dev,
> + struct v4l2_device *v4l2_dev);
> +
> +void rkisp1_unregister_isp_subdev(struct rkisp1_device *isp_dev);
> +
> +void rkisp1_mipi_isr(unsigned int mipi_mis, struct rkisp1_device *dev);
> +
> +void rkisp1_isp_isr(unsigned int isp_mis, struct rkisp1_device *dev);
> +
> +static inline struct rkisp1_device *sd_to_isp_dev(struct v4l2_subdev *sd)
> +{
> + return container_of(sd->v4l2_dev, struct rkisp1_device, v4l2_dev);
> +}
> +
> +static inline
> +struct ispsd_out_fmt *rkisp1_get_ispsd_out_fmt(struct rkisp1_device *isp_dev)
> +{
> + return &isp_dev->isp_sdev.out_fmt;
> +}
> +
> +static inline
> +struct v4l2_rect *rkisp1_get_isp_sd_win(struct rkisp1_device *isp_dev)
> +{
> + return &isp_dev->isp_sdev.out_crop;
> +}
> +
> +#endif /* _RKISP1_H */
>
Regards,
Hans
^ permalink raw reply
* Re: [RFC v2 1/2] backlight: pwm_bl: linear interpolation between values of brightness-levels
From: Enric Balletbo Serra @ 2017-11-27 11:21 UTC (permalink / raw)
To: Rob Herring
Cc: Enric Balletbo i Serra, Daniel Thompson, Jingoo Han,
Richard Purdie, Jacek Anaszewski, Pavel Machek, Doug Anderson,
Brian Norris, Guenter Roeck, Lee Jones, Alexandru Stan,
linux-leds, devicetree@vger.kernel.org, linux-kernel
In-Reply-To: <20171120185835.r4ded43i62wnu3jo@rob-hp-laptop>
Hi Rob,
2017-11-20 19:58 GMT+01:00 Rob Herring <robh@kernel.org>:
> On Thu, Nov 16, 2017 at 03:11:50PM +0100, Enric Balletbo i Serra wrote:
>> Setting use-linear-interpolation in the dts will allow you to have linear
>> interpolation between values of brightness-levels.
>>
>> There are now 256 between each of the values of brightness-levels. If
>> something is requested halfway between 2 values, we'll use linear
>> interpolation.
>>
>> This way a high resolution pwm duty cycle can be used without having to
>> list out every possible value in the dts.
>
> I thought we already had a way to do that.
>
>> This system also allows for
>> gamma corrected values (eg: "brightness-levels = <0 2 4 8 16 32>;").
>>
>> Patch based on the Alexandru M Stan work done for ChromeOS kernels.
>>
>> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
>> ---
>> .../bindings/leds/backlight/pwm-backlight.txt | 2 +
>> drivers/video/backlight/pwm_bl.c | 55 +++++++++++++++++-----
>> include/linux/pwm_backlight.h | 2 +
>> 3 files changed, 47 insertions(+), 12 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/leds/backlight/pwm-backlight.txt b/Documentation/devicetree/bindings/leds/backlight/pwm-backlight.txt
>> index 764db86..7c48f20 100644
>> --- a/Documentation/devicetree/bindings/leds/backlight/pwm-backlight.txt
>> +++ b/Documentation/devicetree/bindings/leds/backlight/pwm-backlight.txt
>> @@ -17,6 +17,8 @@ Optional properties:
>> "pwms" property (see PWM binding[0])
>> - enable-gpios: contains a single GPIO specifier for the GPIO which enables
>> and disables the backlight (see GPIO binding[1])
>> + - use-linear-interpolation: set this propriety to enable linear interpolation
>> + between each of the values of brightness-levels.
>
> Isn't this really just whether you allow values not listed because what
> other kind of interpolation would you do?
Yes, the idea behind this is just allow values not listed.
> Seems like you should just be
> able to query the resolution of the PWM and decide if it can take more
> values than listed.
>
Without using a new DT propriety and let decide the driver when use
intepolation and when not? Shouldn't this break current behavior then?
You can have a high resolution PWM but I'm not sure if you want allow
always more values than listed.
Regards,
Enric
> Rob
^ permalink raw reply
* Re: [PATCH v2] arm64: dts: renesas: r8a7795: Move nodes which have no reg property out of bus
From: Geert Uytterhoeven @ 2017-11-27 11:15 UTC (permalink / raw)
To: Simon Horman
Cc: Linux-Renesas, linux-arm-kernel@lists.infradead.org, Magnus Damm,
Arnd Bergmann, Rob Herring, Geert Uytterhoeven,
devicetree@vger.kernel.org
In-Reply-To: <20171127110430.ulgjrzgy3pdugs2s@verge.net.au>
Hi Simon,
On Mon, Nov 27, 2017 at 12:04 PM, Simon Horman <horms@verge.net.au> wrote:
> On Fri, Nov 24, 2017 at 12:09:47PM +0100, Geert Uytterhoeven wrote:
>> On Fri, Nov 24, 2017 at 11:52 AM, Simon Horman
>> <horms+renesas@verge.net.au> wrote:
>> > Move pmu_a5[73], timer and thermal-zones nodes from soc node to root node.
>> > The nodes that have been moved do not have any register properties and thus
>> > shouldn't be placed on the bus.
>> >
>> > This problem is flagged by the compiler as follows:
>> > $ make
>> > ...
>> > DTC arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb
>> > arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
>> > DTC arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb
>> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
>> > DTC arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb
>> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
>> > DTC arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb
>> > arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
>> > DTC arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb
>> > arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
>> > DTC arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb
>> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
>> > DTC arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb
>> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
>> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
>> >
>> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>> > ---
>> > v2
>> > * Preserve alphabetical order of nodes present in root node.
>>
>> Thanks for the update!
>>
>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> I just noticed that with this patch applied I now see:
>
> arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu_a57
> arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu_a53
> arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu_a57
> arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu_a53arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (interrupts_property): Missing interrupt-parent for /timer
>
> arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (interrupts_property): Missing interrupt-parent for /timer
Right, the "interrupt-parent = <&gic>;" inside the /soc node applies to child
nodes of the /soc node only.
You can find this in two ways:
1. Add "interrupt-parent = <&gic>;" to the /pmu_a57 and /pmu_a53 nodes.
2. Switch those nodes from "interrupt" to "interrupts-extended", e.g. turn
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
into
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
The latter is what e.g. arch/arm/boot/dts/armada-375.dtsi does.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v2] arm64: dts: renesas: r8a7795: Move nodes which have no reg property out of bus
From: Simon Horman @ 2017-11-27 11:04 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Linux-Renesas,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Magnus Damm, Arnd Bergmann, Rob Herring, Geert Uytterhoeven,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CAMuHMdW9V6Bkh5uS9qNA7awtygEs=qRd7jigwSHmpV2VM3n9dA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Fri, Nov 24, 2017 at 12:09:47PM +0100, Geert Uytterhoeven wrote:
> On Fri, Nov 24, 2017 at 11:52 AM, Simon Horman
> <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org> wrote:
> > Move pmu_a5[73], timer and thermal-zones nodes from soc node to root node.
> > The nodes that have been moved do not have any register properties and thus
> > shouldn't be placed on the bus.
> >
> > This problem is flagged by the compiler as follows:
> > $ make
> > ...
> > DTC arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb
> > arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
> > DTC arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb
> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
> > DTC arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb
> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
> > DTC arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb
> > arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
> > DTC arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb
> > arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
> > DTC arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb
> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
> > DTC arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb
> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
> >
> > Signed-off-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
> > ---
> > v2
> > * Preserve alphabetical order of nodes present in root node.
>
> Thanks for the update!
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
I just noticed that with this patch applied I now see:
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu_a57
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu_a53
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu_a57
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu_a53arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (interrupts_property): Missing interrupt-parent for /timer
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (interrupts_property): Missing interrupt-parent for /timer
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v2 2/3] hwrng: exynos - add Samsung Exynos True RNG driver
From: Krzysztof Kozlowski @ 2017-11-27 10:49 UTC (permalink / raw)
To: Łukasz Stelmach
Cc: Andrew F. Davis, PrasannaKumar Muralidharan, Rob Herring,
Matt Mackall, Herbert Xu, devicetree, linux-crypto,
linux-samsung-soc, linux-kernel, Marek Szyprowski,
Bartlomiej Zolnierkiewicz
In-Reply-To: <20171127095804.7128-3-l.stelmach@samsung.com>
On Mon, Nov 27, 2017 at 10:58 AM, Łukasz Stelmach
<l.stelmach@samsung.com> wrote:
> Add support for True Random Number Generator found in Samsung Exynos
> 5250+ SoCs.
>
> Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
> ---
> MAINTAINERS | 7 +
> drivers/char/hw_random/Kconfig | 12 ++
> drivers/char/hw_random/Makefile | 1 +
> drivers/char/hw_random/exynos-trng.c | 245 +++++++++++++++++++++++++++++++++++
> 4 files changed, 265 insertions(+)
> create mode 100644 drivers/char/hw_random/exynos-trng.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 2811a211632c..992074cca612 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11780,6 +11780,13 @@ S: Maintained
> F: drivers/crypto/exynos-rng.c
> F: Documentation/devicetree/bindings/rng/samsung,exynos-rng4.txt
>
> +SAMSUNG EXYNOS TRUE RANDOM NUMBER GENERATOR (TRNG) DRIVER
> +M: Łukasz Stelmach <l.stelmach@samsung.com>
> +L: linux-samsung-soc@vger.kernel.org
> +S: Maintained
> +F: drivers/char/hw_random/exynos-trng.c
> +F: Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.txt
> +
> SAMSUNG FRAMEBUFFER DRIVER
> M: Jingoo Han <jingoohan1@gmail.com>
> L: linux-fbdev@vger.kernel.org
> diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
> index 95a031e9eced..292e6b36d493 100644
> --- a/drivers/char/hw_random/Kconfig
> +++ b/drivers/char/hw_random/Kconfig
> @@ -449,6 +449,18 @@ config HW_RANDOM_S390
>
> If unsure, say Y.
>
> +config HW_RANDOM_EXYNOS
> + tristate "Samsung Exynos True Random Number Generator support"
> + depends on ARCH_EXYNOS || COMPILE_TEST
> + default HW_RANDOM
> + ---help---
> + This driver provides support for the True Random Number
> + Generator available in Exynos SoCs.
> +
> + To compile this driver as a module, choose M here: the module
> + will be called exynos-trng.
> +
> + If unsure, say Y.
> endif # HW_RANDOM
>
> config UML_RANDOM
> diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
> index f3728d008fff..5595df97da7a 100644
> --- a/drivers/char/hw_random/Makefile
> +++ b/drivers/char/hw_random/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_HW_RANDOM_GEODE) += geode-rng.o
> obj-$(CONFIG_HW_RANDOM_N2RNG) += n2-rng.o
> n2-rng-y := n2-drv.o n2-asm.o
> obj-$(CONFIG_HW_RANDOM_VIA) += via-rng.o
> +obj-$(CONFIG_HW_RANDOM_EXYNOS) += exynos-trng.o
> obj-$(CONFIG_HW_RANDOM_IXP4XX) += ixp4xx-rng.o
> obj-$(CONFIG_HW_RANDOM_OMAP) += omap-rng.o
> obj-$(CONFIG_HW_RANDOM_OMAP3_ROM) += omap3-rom-rng.o
> diff --git a/drivers/char/hw_random/exynos-trng.c b/drivers/char/hw_random/exynos-trng.c
> new file mode 100644
> index 000000000000..91b2ddb249fa
> --- /dev/null
> +++ b/drivers/char/hw_random/exynos-trng.c
> @@ -0,0 +1,245 @@
> +/*
> + * RNG driver for Exynos TRNGs
> + *
> + * Author: Łukasz Stelmach <l.stelmach@samsung.com>
> + *
> + * Copyright 2017 (c) Samsung Electronics Software, Inc.
> + *
> + * Based on the Exynos PRNG driver drivers/crypto/exynos-rng by
> + * Krzysztof Kozłowski <krzk@kernel.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation;
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/crypto.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/hw_random.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +
> +#define EXYNOS_TRNG_CLKDIV (0x0)
> +#define EXYNOS_TRNG_CTRL (0x20)
> +#define EXYNOS_TRNG_POST_CTRL (0x30)
> +#define EXYNOS_TRNG_ONLINE_CTRL (0x40)
> +#define EXYNOS_TRNG_ONLINE_STAT (0x44)
> +#define EXYNOS_TRNG_ONLINE_MAXCHI2 (0x48)
> +#define EXYNOS_TRNG_FIFO_CTRL (0x50)
> +#define EXYNOS_TRNG_FIFO_0 (0x80)
> +#define EXYNOS_TRNG_FIFO_1 (0x84)
> +#define EXYNOS_TRNG_FIFO_2 (0x88)
> +#define EXYNOS_TRNG_FIFO_3 (0x8c)
> +#define EXYNOS_TRNG_FIFO_4 (0x90)
> +#define EXYNOS_TRNG_FIFO_5 (0x94)
> +#define EXYNOS_TRNG_FIFO_6 (0x98)
> +#define EXYNOS_TRNG_FIFO_7 (0x9c)
> +#define EXYNOS_TRNG_FIFO_LEN (8)
> +#define EXYNOS_TRNG_CLOCK_RATE (500000)
> +
> +#define TRNG_CTRL_RGNEN BIT(31)
Add a EXYNOS prefix and please put it after the register where it is
used (CTRL).
> +
> +struct exynos_trng_dev {
> + struct device *dev;
> + void __iomem *mem;
> + struct clk *clk;
> + struct hwrng rng;
> +};
> +
> +static int exynos_trng_do_read(struct hwrng *rng, void *data, size_t max,
> + bool wait)
> +{
> + struct exynos_trng_dev *trng;
> + u32 val;
> +
> + max = min_t(size_t, max, (EXYNOS_TRNG_FIFO_LEN * 4));
> +
> + trng = (struct exynos_trng_dev *)rng->priv;
> +
> + __raw_writel(max * 8, trng->mem + EXYNOS_TRNG_FIFO_CTRL);
> + val = readl_poll_timeout(trng->mem + EXYNOS_TRNG_FIFO_CTRL, val,
> + val == 0, 200, 1000000);
> + if (val < 0)
> + return val;
> +
> + memcpy_fromio(data, trng->mem + EXYNOS_TRNG_FIFO_0, max);
> +
> + return max;
> +}
> +
> +static int exynos_trng_init(struct hwrng *rng)
> +{
> + struct exynos_trng_dev *trng = (struct exynos_trng_dev *)rng->priv;
> + unsigned long sss_rate;
> + u32 val;
> +
> + sss_rate = clk_get_rate(trng->clk);
> +
> + /*
> + * For most TRNG circuits the clock frequency of under 500 kHz
> + * is safe.
> + */
> + val = sss_rate / (EXYNOS_TRNG_CLOCK_RATE * 2);
> + if (val > 0x7fff) {
> + dev_err(trng->dev, "clock divider too large: %d", val);
> + return -ERANGE;
> + }
> + val = val << 1;
> + __raw_writel(val, trng->mem + EXYNOS_TRNG_CLKDIV);
> +
> + /* Enable the generator. */
> + val = TRNG_CTRL_RGNEN;
> + __raw_writel(val, trng->mem + EXYNOS_TRNG_CTRL);
> +
> + /*
> + * Disable post-processing. /dev/hwrng is supposed to deliver
> + * unprocessed data.
> + */
> + __raw_writel(0, trng->mem + EXYNOS_TRNG_POST_CTRL);
> +
> + return 0;
> +}
> +
> +static int exynos_trng_probe(struct platform_device *pdev)
> +{
> + struct exynos_trng_dev *trng;
> + struct resource *res;
> + int ret = -ENOMEM;
> +
> + trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL);
> + if (!trng)
> + return ret;
> +
> + trng->rng.name = devm_kstrdup(&pdev->dev, dev_name(&pdev->dev),
> + GFP_KERNEL);
> + if (!trng->rng.name)
> + return ret;
> +
> + trng->rng.init = exynos_trng_init;
> + trng->rng.read = exynos_trng_do_read;
> + trng->rng.priv = (unsigned long) trng;
> +
> + platform_set_drvdata(pdev, trng);
> + trng->dev = &pdev->dev;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + trng->mem = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(trng->mem)) {
> + ret = PTR_ERR(trng->mem);
> + dev_err(&pdev->dev, "Could not map IO resources.\n");
> + goto err_ioremap;
Just return PTR_ERR(trng->mem)? Less lines and goto labels.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 1/3] dt-bindings: hwrng: Add Samsung Exynos 5250+ True RNG bindings
From: Krzysztof Kozlowski @ 2017-11-27 10:45 UTC (permalink / raw)
To: Łukasz Stelmach
Cc: Andrew F. Davis, PrasannaKumar Muralidharan, Rob Herring,
Matt Mackall, Herbert Xu, devicetree, linux-crypto,
linux-samsung-soc, linux-kernel, Marek Szyprowski,
Bartlomiej Zolnierkiewicz
In-Reply-To: <20171127095804.7128-2-l.stelmach@samsung.com>
On Mon, Nov 27, 2017 at 10:58 AM, Łukasz Stelmach
<l.stelmach@samsung.com> wrote:
> Add binding documentation for the True Random Number Generator
> found on Samsung Exynos 5250+ SoCs.
>
> Acked-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
> Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
A minor nit: add new tags after your Signed-off-by, in same order you
received them.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v8 0/6] stm32 clocksource driver rework
From: Benjamin Gaignard @ 2017-11-27 10:44 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King - ARM Linux,
Maxime Coquelin, Alexandre Torgue, Daniel Lezcano,
Thomas Gleixner, Ludovic Barre, Julien Thierry, Sudeep Holla,
Arnd Bergmann
Cc: devicetree, Linux ARM, Linux Kernel Mailing List,
Benjamin Gaignard
In-Reply-To: <1510649563-22975-1-git-send-email-benjamin.gaignard@linaro.org>
2017-11-14 9:52 GMT+01:00 Benjamin Gaignard <benjamin.gaignard@linaro.org>:
> version 8:
> - rebased on timers/core
> - change timer_of_exit() name to timer_of_cleanup()
> - update stm32 clocksource driver to use this function
>
Gentle ping to get this v8 reviewed, the first patch has already been merged
int v4.15-rc1
Thanks,
Benjamin
> version 7:
> - reword "clocksource: stm32: only use 32 bits timers" commit message
> to give more details about why 16 bits are problematics.
>
> version 6:
> - add dedicated patch min delta change
> - rework commit messages, I hope it will be better now
> - change new function name from timer_of_deinit to timer_of_exit
> - make stm32_clock_event_set_next_event() safer like done in other
> drivers
>
> version 6:
> - add timer_of_deinit function in core
> - rework failure cases in probe function
>
> version 5:
> - rebase on top of timer/core branch
> - rework commit message of the first patch
>
> version 4:
> - split patch in 3 parts
> - convert code to timer_of
> - only use 32 bits timers
> - add clocksource support
>
> version 3:
> - fix comments done by Daniel
> - use timer_of helper functions
>
> version 2:
> - fix uninitialized variable
>
> Benjamin Gaignard (6):
> clocksource: timer_of: rename timer_of_exit to timer_of_cleanup
> clocksource: stm32: convert driver to timer_of
> clocksource: stm32: increase min delta value
> clocksource: stm32: only use 32 bits timers
> clocksource: stm32: add clocksource support
> arm: dts: stm32: remove useless clocksource nodes
>
> arch/arm/boot/dts/stm32f429.dtsi | 32 -----
> arch/arm/boot/dts/stm32f746.dtsi | 32 -----
> drivers/clocksource/Kconfig | 1 +
> drivers/clocksource/timer-of.c | 9 +-
> drivers/clocksource/timer-of.h | 2 +-
> drivers/clocksource/timer-stm32.c | 242 ++++++++++++++++++++------------------
> 6 files changed, 138 insertions(+), 180 deletions(-)
>
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH v2 02/11] media: rkisp1: Add user space ABI definitions
From: Hans Verkuil @ 2017-11-27 10:26 UTC (permalink / raw)
To: Jacob Chen, linux-rockchip
Cc: linux-kernel, linux-arm-kernel, mchehab, linux-media,
sakari.ailus, hans.verkuil, tfiga, zhengsq, laurent.pinchart, zyc,
eddie.cai.linux, jeffy.chen, allon.huang, devicetree, heiko,
robh+dt, Jacob Chen
In-Reply-To: <20171124023706.5702-3-jacob-chen@iotwrt.com>
On 11/24/2017 03:36 AM, Jacob Chen wrote:
> From: Jeffy Chen <jeffy.chen@rock-chips.com>
>
> Add the header for userspace
I gather that this effectively documents the metadata?
I recommend using kernel-doc formatting here.
One thing I immediately noticed is that these structures will have a
different layout for 32 or 64 architectures. Which is a problem if you compile
for 32 bit on a 64 bit kernel on the rk3399.
I think you need to be very careful how you define these structures.
Are these parameters documented in a datasheet? If so, then add a reference
to that datasheet. Is it publicly available or do you need an NDA to get it?
>
> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
> ---
> include/uapi/linux/rkisp1-config.h | 554 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 554 insertions(+)
> create mode 100644 include/uapi/linux/rkisp1-config.h
>
> diff --git a/include/uapi/linux/rkisp1-config.h b/include/uapi/linux/rkisp1-config.h
> new file mode 100644
> index 000000000000..a801fbc9ef47
> --- /dev/null
> +++ b/include/uapi/linux/rkisp1-config.h
> @@ -0,0 +1,554 @@
> +/*
> + * Rockchip isp1 driver
> + *
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + *
> + * This software is available to you under a choice of one of two
> + * licenses. You may choose to be licensed under the terms of the GNU
> + * General Public License (GPL) Version 2, available from the file
> + * COPYING in the main directory of this source tree, or the
> + * OpenIB.org BSD license below:
> + *
> + * Redistribution and use in source and binary forms, with or
> + * without modification, are permitted provided that the following
> + * conditions are met:
> + *
> + * - Redistributions of source code must retain the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer.
> + *
> + * - Redistributions in binary form must reproduce the above
> + * copyright notice, this list of conditions and the following
> + * disclaimer in the documentation and/or other materials
> + * provided with the distribution.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#ifndef _UAPI_RKISP1_CONFIG_H
> +#define _UAPI_RKISP1_CONFIG_H
> +
> +#include <linux/types.h>
> +#include <linux/v4l2-controls.h>
> +
> +#define CIFISP_MODULE_DPCC (1 << 0)
> +#define CIFISP_MODULE_BLS (1 << 1)
> +#define CIFISP_MODULE_SDG (1 << 2)
> +#define CIFISP_MODULE_HST (1 << 3)
> +#define CIFISP_MODULE_LSC (1 << 4)
> +#define CIFISP_MODULE_AWB_GAIN (1 << 5)
> +#define CIFISP_MODULE_FLT (1 << 6)
> +#define CIFISP_MODULE_BDM (1 << 7)
> +#define CIFISP_MODULE_CTK (1 << 8)
> +#define CIFISP_MODULE_GOC (1 << 9)
> +#define CIFISP_MODULE_CPROC (1 << 10)
> +#define CIFISP_MODULE_AFC (1 << 11)
> +#define CIFISP_MODULE_AWB (1 << 12)
> +#define CIFISP_MODULE_IE (1 << 13)
> +#define CIFISP_MODULE_AEC (1 << 14)
> +#define CIFISP_MODULE_WDR (1 << 15)
> +#define CIFISP_MODULE_DPF (1 << 16)
> +#define CIFISP_MODULE_DPF_STRENGTH (1 << 17)
> +
> +#define CIFISP_CTK_COEFF_MAX 0x100
> +#define CIFISP_CTK_OFFSET_MAX 0x800
> +
> +#define CIFISP_AE_MEAN_MAX 25
> +#define CIFISP_HIST_BIN_N_MAX 16
> +#define CIFISP_AFM_MAX_WINDOWS 3
> +#define CIFISP_DEGAMMA_CURVE_SIZE 17
> +
> +#define CIFISP_BDM_MAX_TH 0xFF
> +
> +/* maximum value for horizontal start address */
> +#define CIFISP_BLS_START_H_MAX 0x00000FFF
> +/* maximum value for horizontal stop address */
> +#define CIFISP_BLS_STOP_H_MAX 0x00000FFF
> +/* maximum value for vertical start address */
> +#define CIFISP_BLS_START_V_MAX 0x00000FFF
> +/* maximum value for vertical stop address */
> +#define CIFISP_BLS_STOP_V_MAX 0x00000FFF
> +/* maximum is 2^18 = 262144*/
> +#define CIFISP_BLS_SAMPLES_MAX 0x00000012
> +/* maximum value for fixed black level */
> +#define CIFISP_BLS_FIX_SUB_MAX 0x00000FFF
> +/* minimum value for fixed black level */
> +#define CIFISP_BLS_FIX_SUB_MIN 0xFFFFF000
> +/* 13 bit range (signed)*/
> +#define CIFISP_BLS_FIX_MASK 0x00001FFF
> +/* AWB */
> +#define CIFISP_AWB_MAX_GRID 1
> +#define CIFISP_AWB_MAX_FRAMES 7
> +
> +/* Gamma out*/
> +/* Maximum number of color samples supported */
> +#define CIFISP_GAMMA_OUT_MAX_SAMPLES 17
> +
> +/* LSC */
> +#define CIFISP_LSC_GRAD_TBL_SIZE 8
> +#define CIFISP_LSC_SIZE_TBL_SIZE 8
> +/*
> + * The following matches the tuning process,
> + * not the max capabilities of the chip.
> + * Last value unused.
> + */
> +#define CIFISP_LSC_DATA_TBL_SIZE 290
> +/* HIST */
> +/* Last 3 values unused. */
> +#define CIFISP_HISTOGRAM_WEIGHT_GRIDS_SIZE 28
> +
> +/* DPCC */
> +#define CIFISP_DPCC_METHODS_MAX 3
> +
> +/* DPF */
> +#define CIFISP_DPF_MAX_NLF_COEFFS 17
> +#define CIFISP_DPF_MAX_SPATIAL_COEFFS 6
> +
> +/* measurement types */
> +#define CIFISP_STAT_AWB (1 << 0)
> +#define CIFISP_STAT_AUTOEXP (1 << 1)
> +#define CIFISP_STAT_AFM_FIN (1 << 2)
> +#define CIFISP_STAT_HIST (1 << 3)
> +
> +enum cifisp_histogram_mode {
> + CIFISP_HISTOGRAM_MODE_DISABLE,
> + CIFISP_HISTOGRAM_MODE_RGB_COMBINED,
> + CIFISP_HISTOGRAM_MODE_R_HISTOGRAM,
> + CIFISP_HISTOGRAM_MODE_G_HISTOGRAM,
> + CIFISP_HISTOGRAM_MODE_B_HISTOGRAM,
> + CIFISP_HISTOGRAM_MODE_Y_HISTOGRAM
> +};
> +
> +enum cifisp_exp_meas_mode {
> +/* < Y = 16 + 0.25R + 0.5G + 0.1094B */
> + CIFISP_EXP_MEASURING_MODE_0,
> +/* < Y = (R + G + B) x (85/256) */
> + CIFISP_EXP_MEASURING_MODE_1,
> +};
> +
> +enum cifisp_exp_ctrl_auotostop {
> + CIFISP_EXP_CTRL_AUTOSTOP_0 = 0,
> + CIFISP_EXP_CTRL_AUTOSTOP_1 = 1,
> +};
> +
> +struct cifisp_window {
> + unsigned short h_offs;
> + unsigned short v_offs;
> + unsigned short h_size;
> + unsigned short v_size;
> +};
> +
> +enum cifisp_awb_mode_type {
> + CIFISP_AWB_MODE_MANUAL,
> + CIFISP_AWB_MODE_RGB,
> + CIFISP_AWB_MODE_YCBCR
> +};
> +
> +enum cifisp_flt_mode {
> + CIFISP_FLT_STATIC_MODE,
> + CIFISP_FLT_DYNAMIC_MODE
> +};
> +
> +/*
> + * BLS fixed subtraction values. The values will be subtracted from the sensor
> + * values. Therefore a negative value means addition instead of subtraction!
> + */
> +struct cifisp_bls_fixed_val {
> + /*! Fixed (signed!) subtraction value for Bayer pattern R. */
What's the exact fixed point format used here?
> + signed short r;
> + /*! Fixed (signed!) subtraction value for Bayer pattern Gr. */
> + signed short gr;
> + /*! Fixed (signed!) subtraction value for Bayer pattern Gb. */
> + signed short gb;
> + /*! Fixed (signed!) subtraction value for Bayer pattern B. */
> + signed short b;
> +};
> +
> +/* Configuration used by black level subtraction */
> +struct cifisp_bls_config {
> + /*
> + * Automatic mode activated means that the measured values
> + * are subtracted.Otherwise the fixed subtraction
> + * values will be subtracted.
> + */
> + bool enable_auto;
> + unsigned char en_windows;
> + struct cifisp_window bls_window1; /* < Measurement window 1. */
> + struct cifisp_window bls_window2; /* !< Measurement window 2 */
> + /*
> + * Set amount of measured pixels for each Bayer position
> + * (A, B,C and D) to 2^bls_samples.
> + */
> + unsigned char bls_samples;
> + /* !< Fixed subtraction values. */
> + struct cifisp_bls_fixed_val fixed_val;
> +};
> +
> +struct cifisp_dpcc_methods_config {
> + unsigned int method;
> + unsigned int line_thresh;
> + unsigned int line_mad_fac;
> + unsigned int pg_fac;
> + unsigned int rnd_thresh;
> + unsigned int rg_fac;
> +};
> +
> +struct cifisp_dpcc_config {
> + unsigned int mode;
> + unsigned int output_mode;
> + unsigned int set_use;
> + struct cifisp_dpcc_methods_config methods[CIFISP_DPCC_METHODS_MAX];
> + unsigned int ro_limits;
> + unsigned int rnd_offs;
> +};
> +
> +struct cifisp_gamma_corr_curve {
> + unsigned short gamma_y[CIFISP_DEGAMMA_CURVE_SIZE];
> +};
> +
> +struct cifisp_gamma_curve_x_axis_pnts {
> + unsigned int gamma_dx0;
> + unsigned int gamma_dx1;
> +};
> +
> +/* Configuration used by sensor degamma */
> +struct cifisp_sdg_config {
> + struct cifisp_gamma_corr_curve curve_r;
> + struct cifisp_gamma_corr_curve curve_g;
> + struct cifisp_gamma_corr_curve curve_b;
> + struct cifisp_gamma_curve_x_axis_pnts xa_pnts;
> +};
> +
> +/* Configuration used by Lens shading correction */
> +struct cifisp_lsc_config {
> + unsigned int r_data_tbl[CIFISP_LSC_DATA_TBL_SIZE];
> + unsigned int gr_data_tbl[CIFISP_LSC_DATA_TBL_SIZE];
> + unsigned int gb_data_tbl[CIFISP_LSC_DATA_TBL_SIZE];
> + unsigned int b_data_tbl[CIFISP_LSC_DATA_TBL_SIZE];
> +
> + unsigned int x_grad_tbl[CIFISP_LSC_GRAD_TBL_SIZE];
> + unsigned int y_grad_tbl[CIFISP_LSC_GRAD_TBL_SIZE];
> +
> + unsigned int x_size_tbl[CIFISP_LSC_SIZE_TBL_SIZE];
> + unsigned int y_size_tbl[CIFISP_LSC_SIZE_TBL_SIZE];
> + unsigned short config_width;
> + unsigned short config_height;
> +};
> +
> +struct cifisp_ie_config {
> + enum v4l2_colorfx effect;
> + unsigned short color_sel;
> + /* 3x3 Matrix Coefficients for Emboss Effect 1 */
> + unsigned short eff_mat_1;
> + /* 3x3 Matrix Coefficients for Emboss Effect 2 */
> + unsigned short eff_mat_2;
> + /* 3x3 Matrix Coefficients for Emboss 3/Sketch 1 */
> + unsigned short eff_mat_3;
> + /* 3x3 Matrix Coefficients for Sketch Effect 2 */
> + unsigned short eff_mat_4;
> + /* 3x3 Matrix Coefficients for Sketch Effect 3 */
> + unsigned short eff_mat_5;
> + /* Chrominance increment values of tint (used for sepia effect) */
> + unsigned short eff_tint;
> +};
> +
> +struct cifisp_cproc_config {
> + unsigned char c_out_range;
> + unsigned char y_in_range;
> + unsigned char y_out_range;
> + unsigned char contrast;
> + unsigned char brightness;
> + unsigned char sat;
> + unsigned char hue;
> +};
> +
> +/* Configuration used by auto white balance */
> +struct cifisp_awb_meas_config {
> + /*
> + * white balance measurement window (in pixels)
> + * Note: currently the h and v offsets are mapped to grid offsets
> + */
> + struct cifisp_window awb_wnd;
> + enum cifisp_awb_mode_type awb_mode;
> + /*
> + * only pixels values < max_y contribute to awb measurement
> + * (set to 0 to disable this feature)
> + */
> + unsigned char max_y;
> + /* only pixels values > min_y contribute to awb measurement */
> + unsigned char min_y;
> + /*
> + * Chrominance sum maximum value, only consider pixels with Cb+Cr
> + * smaller than threshold for awb measurements
> + */
> + unsigned char max_csum;
> + /*
> + * Chrominance minimum value, only consider pixels with Cb/Cr
> + * each greater than threshold value for awb measurements
> + */
> + unsigned char min_c;
> + /*
> + * number of frames - 1 used for mean value calculation
> + * (ucFrames=0 means 1 Frame)
> + */
> + unsigned char frames;
> + /* reference Cr value for AWB regulation, target for AWB */
> + unsigned char awb_ref_cr;
> + /* reference Cb value for AWB regulation, target for AWB */
> + unsigned char awb_ref_cb;
> + bool enable_ymax_cmp;
> +};
> +
> +struct cifisp_awb_gain_config {
> + unsigned short gain_red;
> + unsigned short gain_green_r;
> + unsigned short gain_blue;
> + unsigned short gain_green_b;
> +};
> +
> +/* Configuration used by ISP filtering */
> +struct cifisp_flt_config {
> + enum cifisp_flt_mode mode; /* ISP_FILT_MODE register fields */
> + unsigned char grn_stage1; /* ISP_FILT_MODE register fields */
> + unsigned char chr_h_mode; /* ISP_FILT_MODE register fields */
> + unsigned char chr_v_mode; /* ISP_FILT_MODE register fields */
> + unsigned int thresh_bl0;
> + unsigned int thresh_bl1;
> + unsigned int thresh_sh0;
> + unsigned int thresh_sh1;
> + unsigned int lum_weight;
> + unsigned int fac_sh1;
> + unsigned int fac_sh0;
> + unsigned int fac_mid;
> + unsigned int fac_bl0;
> + unsigned int fac_bl1;
> +};
> +
> +/* Configuration used by Bayer DeMosaic */
> +struct cifisp_bdm_config {
> + unsigned char demosaic_th;
> +};
> +
> +/* Configuration used by Cross Talk correction */
> +struct cifisp_ctk_config {
> + unsigned short coeff0;
> + unsigned short coeff1;
> + unsigned short coeff2;
> + unsigned short coeff3;
> + unsigned short coeff4;
> + unsigned short coeff5;
> + unsigned short coeff6;
> + unsigned short coeff7;
> + unsigned short coeff8;
> + /* offset for the crosstalk correction matrix */
> + unsigned short ct_offset_r;
> + unsigned short ct_offset_g;
> + unsigned short ct_offset_b;
> +};
> +
> +enum cifisp_goc_mode {
> + CIFISP_GOC_MODE_LOGARITHMIC,
> + CIFISP_GOC_MODE_EQUIDISTANT
> +};
> +
> +/* Configuration used by Gamma Out correction */
> +struct cifisp_goc_config {
> + enum cifisp_goc_mode mode;
> + unsigned short gamma_y[CIFISP_GAMMA_OUT_MAX_SAMPLES];
> +};
> +
> +/* Configuration used by Histogram */
> +struct cifisp_hst_config {
> + enum cifisp_histogram_mode mode;
> + unsigned char histogram_predivider;
> + struct cifisp_window meas_window;
> + unsigned char hist_weight[CIFISP_HISTOGRAM_WEIGHT_GRIDS_SIZE];
> +};
> +
> +/* Configuration used by Auto Exposure Control */
> +struct cifisp_aec_config {
> + enum cifisp_exp_meas_mode mode;
> + __u32 autostop;
> + struct cifisp_window meas_window;
> +};
> +
> +struct cifisp_afc_config {
> + unsigned char num_afm_win; /* max CIFISP_AFM_MAX_WINDOWS */
> + struct cifisp_window afm_win[CIFISP_AFM_MAX_WINDOWS];
> + unsigned int thres;
> + unsigned int var_shift;
> +};
> +
> +enum cifisp_dpf_gain_usage {
> +/* don't use any gains in preprocessing stage */
> + CIFISP_DPF_GAIN_USAGE_DISABLED,
> +/* use only the noise function gains from registers DPF_NF_GAIN_R, ... */
> + CIFISP_DPF_GAIN_USAGE_NF_GAINS,
> +/* use only the gains from LSC module */
> + CIFISP_DPF_GAIN_USAGE_LSC_GAINS,
> +/* use the moise function gains and the gains from LSC module */
> + CIFISP_DPF_GAIN_USAGE_NF_LSC_GAINS,
> +/* use only the gains from AWB module */
> + CIFISP_DPF_GAIN_USAGE_AWB_GAINS,
> +/* use the gains from AWB and LSC module */
> + CIFISP_DPF_GAIN_USAGE_AWB_LSC_GAINS,
> +/* upper border (only for an internal evaluation) */
> + CIFISP_DPF_GAIN_USAGE_MAX
> +};
> +
> +enum cifisp_dpf_rb_filtersize {
> +/* red and blue filter kernel size 13x9 (means 7x5 active pixel) */
> + CIFISP_DPF_RB_FILTERSIZE_13x9,
> +/* red and blue filter kernel size 9x9 (means 5x5 active pixel) */
> + CIFISP_DPF_RB_FILTERSIZE_9x9,
> +};
> +
> +enum cifisp_dpf_nll_scale_mode {
> +/* use a linear scaling */
> + CIFISP_NLL_SCALE_LINEAR,
> +/* use a logarithmic scaling */
> + CIFISP_NLL_SCALE_LOGARITHMIC,
> +};
> +
> +struct cifisp_dpf_nll {
> + unsigned short coeff[CIFISP_DPF_MAX_NLF_COEFFS];
> + enum cifisp_dpf_nll_scale_mode scale_mode;
> +};
> +
> +struct cifisp_dpf_rb_flt {
> + enum cifisp_dpf_rb_filtersize fltsize;
> + unsigned char spatial_coeff[CIFISP_DPF_MAX_SPATIAL_COEFFS];
> + bool r_enable;
> + bool b_enable;
> +};
> +
> +struct cifisp_dpf_g_flt {
> + unsigned char spatial_coeff[CIFISP_DPF_MAX_SPATIAL_COEFFS];
> + bool gr_enable;
> + bool gb_enable;
> +};
> +
> +struct cifisp_dpf_gain {
> + enum cifisp_dpf_gain_usage mode;
> + unsigned short nf_r_gain;
> + unsigned short nf_b_gain;
> + unsigned short nf_gr_gain;
> + unsigned short nf_gb_gain;
> +};
> +
> +struct cifisp_dpf_config {
> + struct cifisp_dpf_gain gain;
> + struct cifisp_dpf_g_flt g_flt;
> + struct cifisp_dpf_rb_flt rb_flt;
> + struct cifisp_dpf_nll nll;
> +};
> +
> +struct cifisp_dpf_strength_config {
> + unsigned char r;
> + unsigned char g;
> + unsigned char b;
> +};
> +
> +struct cifisp_isp_other_cfg {
> + struct cifisp_dpcc_config dpcc_config;
> + struct cifisp_bls_config bls_config;
> + struct cifisp_sdg_config sdg_config;
> + struct cifisp_lsc_config lsc_config;
> + struct cifisp_awb_gain_config awb_gain_config;
> + struct cifisp_flt_config flt_config;
> + struct cifisp_bdm_config bdm_config;
> + struct cifisp_ctk_config ctk_config;
> + struct cifisp_goc_config goc_config;
> + struct cifisp_dpf_config dpf_config;
> + struct cifisp_dpf_strength_config dpf_strength_config;
> + /* post process configs, including hue, sharpness, brightness, contrast, color effect */
> + /* TODO: removed from here ? set by standard v4l2 controls ? */
> + struct cifisp_cproc_config cproc_config;
> + struct cifisp_ie_config ie_config;
> +};
> +
> +struct cifisp_isp_meas_cfg {
> + struct cifisp_awb_meas_config awb_meas_config;
> + struct cifisp_hst_config hst_config;
> + struct cifisp_aec_config aec_config;
> + struct cifisp_afc_config afc_config;
> +};
> +
> +struct rkisp1_isp_params_cfg {
> + /* mask the enable bits of which module should be updated */
> + unsigned int module_en_update;
> + /* mask the enable value of each module, only update the module which correspond
> + * bit was set in module_en_update
> + */
> + unsigned int module_ens;
> + /* mask the config bits of which module should be updated */
> + unsigned int module_cfg_update;
> +
> + struct cifisp_isp_meas_cfg meas;
> + struct cifisp_isp_other_cfg others;
> +};
> +
> +/* measurement statistics */
> +
> +struct cifisp_awb_meas {
> + unsigned int cnt;
> + unsigned char mean_y_or_g;
> + unsigned char mean_cb_or_b;
> + unsigned char mean_cr_or_r;
> +};
> +
> +struct cifisp_awb_stat {
> + struct cifisp_awb_meas awb_mean[CIFISP_AWB_MAX_GRID];
> +};
> +
> +struct cifisp_hist_stat {
> + unsigned short hist_bins[CIFISP_HIST_BIN_N_MAX];
> +};
> +
> +/*! BLS mean measured values */
> +struct cifisp_bls_meas_val {
> + /*! Mean measured value for Bayer pattern R. */
> + unsigned short meas_r;
> + /*! Mean measured value for Bayer pattern Gr. */
> + unsigned short meas_gr;
> + /*! Mean measured value for Bayer pattern Gb. */
> + unsigned short meas_gb;
> + /*! Mean measured value for Bayer pattern B. */
> + unsigned short meas_b;
> +};
> +
> +struct cifisp_ae_stat {
> + unsigned char exp_mean[CIFISP_AE_MEAN_MAX];
> + struct cifisp_bls_meas_val bls_val; /* available wit exposure results */
> +};
> +
> +struct cifisp_af_meas_val {
> + unsigned int sum;
> + unsigned int lum;
> +};
> +
> +struct cifisp_af_stat {
> + struct cifisp_af_meas_val window[CIFISP_AFM_MAX_WINDOWS];
> +};
> +
> +struct cifisp_stat {
> + struct cifisp_awb_stat awb;
> + struct cifisp_ae_stat ae;
> + struct cifisp_af_stat af;
> + struct cifisp_hist_stat hist;
> +};
> +
> +struct rkisp1_stat_buffer {
> + unsigned int meas_type;
> + unsigned int frame_id;
> + struct cifisp_stat params;
> +};
> +
> +#endif /* _UAPI_RKISP1_CONFIG_H */
>
You do need to document more of this. If the datasheet is publicly available
you can get away with referring to the relevant sections of that datasheet.
Regards,
Hans
^ permalink raw reply
* [PATCH] irqchip/gic-v3: Support MSIs via aliases and distributor
From: Stephen Boyd @ 2017-11-27 10:24 UTC (permalink / raw)
To: Thomas Gleixner, Jason Cooper, Marc Zyngier
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Srinivas Kandagatla
Some GIC configurations don't have an accessible ITS, but they
want to support MSIs through the distributor's SETSPI registers
or through the IMPLEMENTATION DEFINED message-based interrupt
request register region. This mode of operation is similar to the
v2m support on gic-400, but we don't necessarily know what
particular SPIs are supported as MSIs so we need some help from
firmware to know what to do.
Introduce an "arm,spi-ranges" property for this, similar to the
"marvell,spi-ranges" property, that indicates the base and size
of each MSI range. This property applies equally to the
distributor and alias registers. In either case, we detect this
mode of operation by looking for a node with the "msi-controller"
property and then probe the v2m frame code on top of it. Assume
these nodes will have the "arm,spi-ranges" property in them so
that the v2m code works mostly unmodified.
Cc: <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
Signed-off-by: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
.../bindings/interrupt-controller/arm,gic-v3.txt | 48 +++++++++-
drivers/irqchip/irq-gic-v2m.c | 102 ++++++++++++++++-----
drivers/irqchip/irq-gic-v3.c | 4 +
include/linux/irqchip/arm-gic-common.h | 3 +
4 files changed, 129 insertions(+), 28 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
index 0a57f2f4167d..ef319ac41be3 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
@@ -57,6 +57,11 @@ Optional
occupied by the redistributors. Required if more than one such
region is present.
+- msi-controller : Boolean property. Identifies the node as an MSI controller
+
+- arm,spi-ranges : Tuples of GIC SPI interrupt ranges (base, size) indicating
+ SPIs available for use as MSIs.
+
Sub-nodes:
PPI affinity can be expressed as a single "ppi-partitions" node,
@@ -75,14 +80,28 @@ These nodes must have the following properties:
- reg: Specifies the base physical address and size of the ITS
registers.
+GICv3 has an IMPLEMENTATION DEFINED set of aliases for message-based interrupt
+requests.
+
+These nodes must have the following properties:
+- compatible : Should at least contain one of
+ "qcom,gic-msi-aliases".
+- msi-controller : Boolean property. Identifies the node as an MSI controller
+- #msi-cells: Must be <1>. The single msi-cell is the DeviceID of the device
+ which will generate the MSI.
+- reg: Specifies the base physical address and size of the message-based
+ interrupt request registers.
+- arm,spi-ranges: Tuples of GIC SPI interrupt ranges (base, size) indicating
+ SPIs available for use as MSIs.
+
+Note: The main GIC node must contain the appropriate #address-cells,
+#size-cells and ranges properties for the reg property of all ITS and
+alias message-based interrupt nodes.
+
Optional:
- socionext,synquacer-pre-its: (u32, u32) tuple describing the untranslated
address and size of the pre-ITS window.
-The main GIC node must contain the appropriate #address-cells,
-#size-cells and ranges properties for the reg property of all ITS
-nodes.
-
Examples:
gic: interrupt-controller@2cf00000 {
@@ -149,6 +168,27 @@ Examples:
};
};
+ intc: interrupt-controller@9bc0000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x40000>;
+ reg = <0x09bc0000 0x10000>,
+ <0x09c00000 0x100000>;
+ interrupts = <1 9 4>;
+
+ msi_alias0: interrupt-controller@9bd0000 {
+ compatible = "qcom,gic-msi-aliases";
+ reg = <0x9bd0000 0x1000>;
+ msi-controller;
+ #msi-cells = <1>;
+ arm,spi-ranges = <544 96>;
+ };
+ };
device@0 {
reg = <0 0 0 4>;
diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c
index 993a8426a453..a254c29dbe69 100644
--- a/drivers/irqchip/irq-gic-v2m.c
+++ b/drivers/irqchip/irq-gic-v2m.c
@@ -26,6 +26,7 @@
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/irqchip/arm-gic.h>
+#include <linux/irqchip/arm-gic-common.h>
/*
* MSI_TYPER:
@@ -383,13 +384,57 @@ static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
return ret;
}
-static struct of_device_id gicv2m_device_id[] = {
- { .compatible = "arm,gic-v2m-frame", },
- {},
+static const struct of_device_id gicv2m_device_id[] = {
+ { .compatible = "arm,gic-v2m-frame", },
+ { .compatible = "qcom,gic-msi-aliases", },
+ {}
};
-static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
- struct irq_domain *parent)
+static int __init gicv2m_of_init_one(struct device_node *child)
+{
+ u32 spi_start = 0, nr_spis = 0;
+ struct resource res;
+ int ret, i, cnt;
+ struct fwnode_handle *fwnode = &child->fwnode;
+
+ if (!of_find_property(child, "msi-controller", NULL))
+ return 0;
+
+ ret = of_address_to_resource(child, 0, &res);
+ if (ret) {
+ pr_err("Failed to allocate v2m resource\n");
+ return ret;
+ }
+
+ if (!of_property_read_u32(child, "arm,msi-base-spi",
+ &spi_start) &&
+ !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
+ pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
+ spi_start, nr_spis);
+
+ cnt = of_property_count_u32_elems(child, "arm,spi-ranges");
+ if (cnt < 0)
+ cnt = 0;
+ cnt /= 2;
+
+ if (!cnt)
+ return gicv2m_init_one(fwnode, spi_start, nr_spis, &res);
+
+ /* Populate v2m for each SPI range */
+ for (i = 0; i < cnt; i++) {
+ of_property_read_u32_index(child, "arm,spi-ranges",
+ i * 2, &spi_start);
+ of_property_read_u32_index(child, "arm,spi-ranges",
+ i * 2 + 1, &nr_spis);
+ ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int __init gicv2m_of_init_children(struct fwnode_handle *parent_handle)
{
int ret = 0;
struct device_node *node = to_of_node(parent_handle);
@@ -397,35 +442,27 @@ static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
for (child = of_find_matching_node(node, gicv2m_device_id); child;
child = of_find_matching_node(child, gicv2m_device_id)) {
- u32 spi_start = 0, nr_spis = 0;
- struct resource res;
-
- if (!of_find_property(child, "msi-controller", NULL))
- continue;
-
- ret = of_address_to_resource(child, 0, &res);
- if (ret) {
- pr_err("Failed to allocate v2m resource.\n");
- break;
- }
-
- if (!of_property_read_u32(child, "arm,msi-base-spi",
- &spi_start) &&
- !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
- pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
- spi_start, nr_spis);
-
- ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, &res);
+ ret = gicv2m_of_init_one(child);
if (ret) {
of_node_put(child);
break;
}
}
+ return ret;
+}
+
+static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
+ struct irq_domain *parent)
+{
+ int ret;
+
+ ret = gicv2m_of_init_children(parent_handle);
if (!ret)
ret = gicv2m_allocate_domains(parent);
if (ret)
gicv2m_teardown();
+
return ret;
}
@@ -518,6 +555,23 @@ static int __init gicv2m_acpi_init(struct irq_domain *parent)
}
#endif /* CONFIG_ACPI */
+int __init gicv2m_init_gicv3(struct fwnode_handle *handle,
+ struct irq_domain *parent)
+{
+ int ret;
+ struct device_node *node = to_of_node(handle);
+
+ ret = gicv2m_of_init_children(handle);
+ if (!ret)
+ ret = gicv2m_of_init_one(node);
+ if (!ret)
+ ret = gicv2m_allocate_domains(parent);
+ if (ret)
+ gicv2m_teardown();
+
+ return ret;
+}
+
int __init gicv2m_init(struct fwnode_handle *parent_handle,
struct irq_domain *parent)
{
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 83a2d48344bd..f8510e67af3e 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -1267,6 +1267,10 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
if (static_key_true(&supports_deactivate))
gic_of_setup_kvm_info(node);
+
+ if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
+ gicv2m_init_gicv3(&node->fwnode, gic_data.domain);
+
return 0;
out_unmap_rdist:
diff --git a/include/linux/irqchip/arm-gic-common.h b/include/linux/irqchip/arm-gic-common.h
index 0a83b4379f34..d2eea9539d37 100644
--- a/include/linux/irqchip/arm-gic-common.h
+++ b/include/linux/irqchip/arm-gic-common.h
@@ -33,4 +33,7 @@ struct gic_kvm_info {
const struct gic_kvm_info *gic_get_kvm_info(void);
+int gicv2m_init_gicv3(struct fwnode_handle *parent_handle,
+ struct irq_domain *parent);
+
#endif /* __LINUX_IRQCHIP_ARM_GIC_COMMON_H */
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH v2 01/11] media: videodev2.h, v4l2-ioctl: add rkisp1 meta buffer format
From: Hans Verkuil @ 2017-11-27 10:17 UTC (permalink / raw)
To: Jacob Chen, linux-rockchip
Cc: linux-kernel, linux-arm-kernel, mchehab, linux-media,
sakari.ailus, hans.verkuil, tfiga, zhengsq, laurent.pinchart, zyc,
eddie.cai.linux, jeffy.chen, allon.huang, devicetree, heiko,
robh+dt, Jacob Chen
In-Reply-To: <20171124023706.5702-2-jacob-chen@iotwrt.com>
On 11/24/2017 03:36 AM, Jacob Chen wrote:
> From: Shunqian Zheng <zhengsq@rock-chips.com>
>
> Add the Rockchip ISP1 specific processing parameter format
> V4L2_META_FMT_RK_ISP1_PARAMS and metadata format
> V4L2_META_FMT_RK_ISP1_STAT_3A for 3A.
These formats are not documented in the V4L2 spec. I think it is documented in
rkisp1-config.h, so you need to add something to meta-formats.rst. It's OK to
refer to that header, as long as it is clear where the documentation of the
format can be found.
Regards,
Hans
>
> Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
> ---
> drivers/media/v4l2-core/v4l2-ioctl.c | 2 ++
> include/uapi/linux/videodev2.h | 4 ++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
> index d6587b3ec33e..0604ae9ea444 100644
> --- a/drivers/media/v4l2-core/v4l2-ioctl.c
> +++ b/drivers/media/v4l2-core/v4l2-ioctl.c
> @@ -1252,6 +1252,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
> case V4L2_TCH_FMT_TU08: descr = "8-bit unsigned touch data"; break;
> case V4L2_META_FMT_VSP1_HGO: descr = "R-Car VSP1 1-D Histogram"; break;
> case V4L2_META_FMT_VSP1_HGT: descr = "R-Car VSP1 2-D Histogram"; break;
> + case V4L2_META_FMT_RK_ISP1_PARAMS: descr = "Rockchip ISP1 3A params"; break;
> + case V4L2_META_FMT_RK_ISP1_STAT_3A: descr = "Rockchip ISP1 3A statistics"; break;
>
> default:
> /* Compressed formats */
> diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
> index 7c871291c1fa..961545e64c12 100644
> --- a/include/uapi/linux/videodev2.h
> +++ b/include/uapi/linux/videodev2.h
> @@ -691,6 +691,10 @@ struct v4l2_pix_format {
> #define V4L2_META_FMT_VSP1_HGO v4l2_fourcc('V', 'S', 'P', 'H') /* R-Car VSP1 1-D Histogram */
> #define V4L2_META_FMT_VSP1_HGT v4l2_fourcc('V', 'S', 'P', 'T') /* R-Car VSP1 2-D Histogram */
>
> +/* Vendor specific - used for IPU3 camera sub-system */
> +#define V4L2_META_FMT_RK_ISP1_PARAMS v4l2_fourcc('R', 'K', '1', 'P') /* Rockchip ISP1 params */
> +#define V4L2_META_FMT_RK_ISP1_STAT_3A v4l2_fourcc('R', 'K', '1', 'S') /* Rockchip ISP1 3A statistics */
> +
> /* priv field value to indicates that subsequent fields are valid. */
> #define V4L2_PIX_FMT_PRIV_MAGIC 0xfeedcafe
>
>
^ permalink raw reply
* Re: [PATCH v2] ARM: dts: imx6qdl-nitrogen6x: Add SPI NOR partitions
From: Gary Bisson @ 2017-11-27 10:17 UTC (permalink / raw)
To: Otavio Salvador
Cc: Otavio Salvador, linux-arm-kernel@lists.infradead.org,
Fabio Estevam, devicetree@vger.kernel.org, Sascha Hauer,
Kernel development list, Rob Herring, Mark Rutland, Russell King,
Shawn Guo
In-Reply-To: <CAP9ODKoefNEcQtrCCLEa7hzx2D_2vJTit0t8ooQGTx7Uyds1mQ@mail.gmail.com>
Hi Otavio,
On Sat, Nov 25, 2017 at 07:55:53AM -0200, Otavio Salvador wrote:
> On Fri, Nov 24, 2017 at 3:00 PM, Otavio Salvador
> <otavio@ossystems.com.br> wrote:
> > This adds the partitions definition for the SPI NOR to provide
> > backward compatibility with the documented[1] layout used with
> > Boundary Devices BSP.
> >
> > 1. https://boundarydevices.com/boot-flash-access-linux/
> >
> > It exports to Linux:
> >
> > mtd0: bootloader
> > mtd1: env
> > mtd2: splash
> >
> > Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
>
> After thinking a bit about Fabio's recommendation to use 'read-only'
> to protect the partitions, I think it'd be better to use 'lock' so it
> is still possible to write them on Linux but it requires a unlock
> prior changing it.
>
> In my case, I am interested in being capable of upgrading the
> bootloader from Linux.
>
> What people think?
Agreed, I would rather have the lock option, especially for the splash
and environment.
Regards,
Gary
^ permalink raw reply
* [PATCH V6 12/12] arm64: dts: add clocks for SC9860
From: Chunyan Zhang @ 2017-11-27 10:01 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, Rob Herring, Mark Rutland
Cc: Catalin Marinas, Will Deacon, linux-clk, linux-kernel, devicetree,
linux-arm-kernel, Arnd Bergmann, Mark Brown, Xiaolong Zhang,
Ben Li, Orson Zhai, Chunyan Zhang
In-Reply-To: <20171127100115.20655-1-chunyan.zhang@spreadtrum.com>
Some clocks on SC9860 are in the same address area with syscon devices,
those are what have a property of 'sprd,syscon' which would refer to
syscon devices, others would have a reg property indicated their address
ranges.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
---
arch/arm64/boot/dts/sprd/sc9860.dtsi | 115 +++++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/sprd/whale2.dtsi | 2 +-
2 files changed, 116 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi
index 7b7d8ce..bf03da4 100644
--- a/arch/arm64/boot/dts/sprd/sc9860.dtsi
+++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi
@@ -7,6 +7,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sprd,sc9860-clk.h>
#include "whale2.dtsi"
/ {
@@ -183,6 +184,120 @@
};
soc {
+ pmu_gate: pmu-gate {
+ compatible = "sprd,sc9860-pmu-gate";
+ sprd,syscon = <&pmu_regs>; /* 0x402b0000 */
+ clocks = <&ext_26m>;
+ #clock-cells = <1>;
+ };
+
+ pll: pll {
+ compatible = "sprd,sc9860-pll";
+ sprd,syscon = <&ana_regs>; /* 0x40400000 */
+ clocks = <&pmu_gate 0>;
+ #clock-cells = <1>;
+ };
+
+ ap_clk: clock-controller@20000000 {
+ compatible = "sprd,sc9860-ap-clk";
+ reg = <0 0x20000000 0 0x400>;
+ clocks = <&ext_26m>, <&pll 0>,
+ <&pmu_gate 0>;
+ #clock-cells = <1>;
+ };
+
+ aon_prediv: aon-prediv {
+ compatible = "sprd,sc9860-aon-prediv";
+ reg = <0 0x402d0000 0 0x400>;
+ clocks = <&ext_26m>, <&pll 0>,
+ <&pmu_gate 0>;
+ #clock-cells = <1>;
+ };
+
+ apahb_gate: apahb-gate {
+ compatible = "sprd,sc9860-apahb-gate";
+ sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */
+ clocks = <&aon_prediv 0>;
+ #clock-cells = <1>;
+ };
+
+ aon_gate: aon-gate {
+ compatible = "sprd,sc9860-aon-gate";
+ sprd,syscon = <&aon_regs>; /* 0x402e0000 */
+ clocks = <&aon_prediv 0>;
+ #clock-cells = <1>;
+ };
+
+ aonsecure_clk: clock-controller@40880000 {
+ compatible = "sprd,sc9860-aonsecure-clk";
+ reg = <0 0x40880000 0 0x400>;
+ clocks = <&ext_26m>, <&pll 0>;
+ #clock-cells = <1>;
+ };
+
+ agcp_gate: agcp-gate {
+ compatible = "sprd,sc9860-agcp-gate";
+ sprd,syscon = <&agcp_regs>; /* 0x415e0000 */
+ clocks = <&aon_prediv 0>;
+ #clock-cells = <1>;
+ };
+
+ gpu_clk: clock-controller@60200000 {
+ compatible = "sprd,sc9860-gpu-clk";
+ reg = <0 0x60200000 0 0x400>;
+ clocks = <&pll 0>;
+ #clock-cells = <1>;
+ };
+
+ vsp_clk: clock-controller@61000000 {
+ compatible = "sprd,sc9860-vsp-clk";
+ reg = <0 0x61000000 0 0x400>;
+ clocks = <&ext_26m>, <&pll 0>;
+ #clock-cells = <1>;
+ };
+
+ vsp_gate: vsp-gate {
+ compatible = "sprd,sc9860-vsp-gate";
+ sprd,syscon = <&vsp_regs>; /* 0x61100000 */
+ clocks = <&vsp_clk 0>;
+ #clock-cells = <1>;
+ };
+
+ cam_clk: clock-controller@62000000 {
+ compatible = "sprd,sc9860-cam-clk";
+ reg = <0 0x62000000 0 0x4000>;
+ clocks = <&ext_26m>, <&pll 0>;
+ #clock-cells = <1>;
+ };
+
+ cam_gate: cam-gate {
+ compatible = "sprd,sc9860-cam-gate";
+ sprd,syscon = <&cam_regs>; /* 0x62100000 */
+ clocks = <&cam_clk 0>;
+ #clock-cells = <1>;
+ };
+
+ disp_clk: clock-controller@63000000 {
+ compatible = "sprd,sc9860-disp-clk";
+ reg = <0 0x63000000 0 0x400>;
+ clocks = <&ext_26m>, <&pll 0>;
+ #clock-cells = <1>;
+ };
+
+ disp_gate: disp-gate {
+ compatible = "sprd,sc9860-disp-gate";
+ sprd,syscon = <&disp_regs>; /* 0x63100000 */
+ clocks = <&disp_clk 0>;
+ #clock-cells = <1>;
+ };
+
+ apapb_gate: apapb-gate {
+ compatible = "sprd,sc9860-apapb-gate";
+ sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */
+ clocks = <&ap_clk 0>;
+ #clock-cells = <1>;
+ };
+
funnel@10001000 { /* SoC Funnel */
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0x10001000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi
index 6ea3a75..eb004bb 100644
--- a/arch/arm64/boot/dts/sprd/whale2.dtsi
+++ b/arch/arm64/boot/dts/sprd/whale2.dtsi
@@ -110,6 +110,6 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
- clock-output-names = "ext_26m";
+ clock-output-names = "ext-26m";
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH V6 11/12] arm64: dts: add syscon for whale2 platform
From: Chunyan Zhang @ 2017-11-27 10:01 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, Rob Herring, Mark Rutland
Cc: Catalin Marinas, Will Deacon, linux-clk, linux-kernel, devicetree,
linux-arm-kernel, Arnd Bergmann, Mark Brown, Xiaolong Zhang,
Ben Li, Orson Zhai, Chunyan Zhang
In-Reply-To: <20171127100115.20655-1-chunyan.zhang@spreadtrum.com>
Some clocks on SC9860 are in the same address area with syscon
devices, the proper syscon node will be quoted under the
definitions of those clocks in DT.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
---
arch/arm64/boot/dts/sprd/whale2.dtsi | 46 +++++++++++++++++++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi
index 7c217c5..6ea3a75 100644
--- a/arch/arm64/boot/dts/sprd/whale2.dtsi
+++ b/arch/arm64/boot/dts/sprd/whale2.dtsi
@@ -17,6 +17,51 @@
#size-cells = <2>;
ranges;
+ ap_ahb_regs: syscon@20210000 {
+ compatible = "syscon";
+ reg = <0 0x20210000 0 0x10000>;
+ };
+
+ pmu_regs: syscon@402b0000 {
+ compatible = "syscon";
+ reg = <0 0x402b0000 0 0x10000>;
+ };
+
+ aon_regs: syscon@402e0000 {
+ compatible = "syscon";
+ reg = <0 0x402e0000 0 0x10000>;
+ };
+
+ ana_regs: syscon@40400000 {
+ compatible = "syscon";
+ reg = <0 0x40400000 0 0x10000>;
+ };
+
+ agcp_regs: syscon@415e0000 {
+ compatible = "syscon";
+ reg = <0 0x415e0000 0 0x1000000>;
+ };
+
+ vsp_regs: syscon@61100000 {
+ compatible = "syscon";
+ reg = <0 0x61100000 0 0x10000>;
+ };
+
+ cam_regs: syscon@62100000 {
+ compatible = "syscon";
+ reg = <0 0x62100000 0 0x10000>;
+ };
+
+ disp_regs: syscon@63100000 {
+ compatible = "syscon";
+ reg = <0 0x63100000 0 0x10000>;
+ };
+
+ ap_apb_regs: syscon@70b00000 {
+ compatible = "syscon";
+ reg = <0 0x70b00000 0 0x40000>;
+ };
+
ap-apb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -59,7 +104,6 @@
status = "disabled";
};
};
-
};
ext_26m: ext-26m {
--
2.7.4
^ permalink raw reply related
* [PATCH V6 10/12] clk: sprd: add clocks support for SC9860
From: Chunyan Zhang @ 2017-11-27 10:01 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, Rob Herring, Mark Rutland
Cc: Catalin Marinas, Will Deacon, linux-clk, linux-kernel, devicetree,
linux-arm-kernel, Arnd Bergmann, Mark Brown, Xiaolong Zhang,
Ben Li, Orson Zhai, Chunyan Zhang
In-Reply-To: <20171127100115.20655-1-chunyan.zhang@spreadtrum.com>
This patch added the list of clocks for Spreadtrum's SC9860 SoC,
together with clock initialization code.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
---
drivers/clk/sprd/Kconfig | 10 +
drivers/clk/sprd/Makefile | 3 +
drivers/clk/sprd/sc9860-clk.c | 1981 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 1994 insertions(+)
create mode 100644 drivers/clk/sprd/sc9860-clk.c
diff --git a/drivers/clk/sprd/Kconfig b/drivers/clk/sprd/Kconfig
index 67a3287..8789247 100644
--- a/drivers/clk/sprd/Kconfig
+++ b/drivers/clk/sprd/Kconfig
@@ -2,3 +2,13 @@ config SPRD_COMMON_CLK
tristate "Clock support for Spreadtrum SoCs"
depends on ARCH_SPRD || COMPILE_TEST
default ARCH_SPRD
+
+if SPRD_COMMON_CLK
+
+# SoC Drivers
+
+config SPRD_SC9860_CLK
+ tristate "Support for the Spreadtrum SC9860 clocks"
+ depends on (ARM64 && ARCH_SPRD) || COMPILE_TEST
+ default ARM64 && ARCH_SPRD
+endif
diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile
index d693969..b0d81e5 100644
--- a/drivers/clk/sprd/Makefile
+++ b/drivers/clk/sprd/Makefile
@@ -6,3 +6,6 @@ clk-sprd-y += mux.o
clk-sprd-y += div.o
clk-sprd-y += composite.o
clk-sprd-y += pll.o
+
+## SoC support
+obj-$(CONFIG_SPRD_SC9860_CLK) += sc9860-clk.o
diff --git a/drivers/clk/sprd/sc9860-clk.c b/drivers/clk/sprd/sc9860-clk.c
new file mode 100644
index 0000000..285d659
--- /dev/null
+++ b/drivers/clk/sprd/sc9860-clk.c
@@ -0,0 +1,1981 @@
+/*
+ * Spreatrum SC9860 clock driver
+ *
+ * Copyright (C) 2017 Spreadtrum, Inc.
+ * Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/sprd,sc9860-clk.h>
+
+#include "common.h"
+#include "composite.h"
+#include "div.h"
+#include "gate.h"
+#include "mux.h"
+#include "pll.h"
+
+static CLK_FIXED_RATE(ext_rco_100m, "ext-rco-100m", 0, 100000000, 0);
+static CLK_FIXED_RATE(ext_32k, "ext-32k", 0, 32768, 0);
+
+static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
+ 6, 1, 0);
+static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
+ 13, 1, 0);
+static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
+ 26, 1, 0);
+static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
+ 104, 1, 0);
+static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
+ 1, 1, 0);
+static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
+ 1, 1, 0);
+static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
+ 4, 1, 0);
+static CLK_FIXED_FACTOR(fac_rco_4m, "rco-4m", "ext-rc0-100m",
+ 25, 1, 0);
+static CLK_FIXED_FACTOR(fac_rco_2m, "rco-2m", "ext-rc0-100m",
+ 50, 1, 0);
+static CLK_FIXED_FACTOR(fac_3k2, "fac-3k2", "ext-32k",
+ 10, 1, 0);
+static CLK_FIXED_FACTOR(fac_1k, "fac-1k", "ext-32k",
+ 32, 1, 0);
+
+static SPRD_SC_GATE_CLK(mpll0_gate, "mpll0-gate", "ext-26m", 0xb0,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(mpll1_gate, "mpll1-gate", "ext-26m", 0xb0,
+ 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(dpll0_gate, "dpll0-gate", "ext-26m", 0xb4,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(dpll1_gate, "dpll1-gate", "ext-26m", 0xb4,
+ 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ltepll0_gate, "ltepll0-gate", "ext-26m", 0xb8,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(twpll_gate, "twpll-gate", "ext-26m", 0xbc,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ltepll1_gate, "ltepll1-gate", "ext-26m", 0x10c,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(rpll0_gate, "rpll0-gate", "ext-26m", 0x16c,
+ 0x1000, BIT(2), 0, 0);
+static SPRD_SC_GATE_CLK(rpll1_gate, "rpll1-gate", "ext-26m", 0x16c,
+ 0x1000, BIT(18), 0, 0);
+static SPRD_SC_GATE_CLK(cppll_gate, "cppll-gate", "ext-26m", 0x2b4,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(gpll_gate, "gpll-gate", "ext-26m", 0x32c,
+ 0x1000, BIT(0), CLK_IGNORE_UNUSED, CLK_GATE_SET_TO_DISABLE);
+
+static struct sprd_clk_common *sc9860_pmu_gate_clks[] = {
+ /* address base is 0x402b0000 */
+ &mpll0_gate.common,
+ &mpll1_gate.common,
+ &dpll0_gate.common,
+ &dpll1_gate.common,
+ <epll0_gate.common,
+ &twpll_gate.common,
+ <epll1_gate.common,
+ &rpll0_gate.common,
+ &rpll1_gate.common,
+ &cppll_gate.common,
+ &gpll_gate.common,
+};
+
+static struct clk_hw_onecell_data sc9860_pmu_gate_hws = {
+ .hws = {
+ [CLK_EXT_RCO_100M] = &ext_rco_100m.hw,
+ [CLK_EXT_32K] = &ext_32k.hw,
+ [CLK_FAC_4M] = &fac_4m.hw,
+ [CLK_FAC_2M] = &fac_2m.hw,
+ [CLK_FAC_1M] = &fac_1m.hw,
+ [CLK_FAC_250K] = &fac_250k.hw,
+ [CLK_FAC_RPLL0_26M] = &fac_rpll0_26m.hw,
+ [CLK_FAC_RPLL1_26M] = &fac_rpll1_26m.hw,
+ [CLK_FAC_RCO25M] = &fac_rco_25m.hw,
+ [CLK_FAC_RCO4M] = &fac_rco_4m.hw,
+ [CLK_FAC_RCO2M] = &fac_rco_2m.hw,
+ [CLK_FAC_3K2] = &fac_3k2.hw,
+ [CLK_FAC_1K] = &fac_1k.hw,
+ [CLK_MPLL0_GATE] = &mpll0_gate.common.hw,
+ [CLK_MPLL1_GATE] = &mpll1_gate.common.hw,
+ [CLK_DPLL0_GATE] = &dpll0_gate.common.hw,
+ [CLK_DPLL1_GATE] = &dpll1_gate.common.hw,
+ [CLK_LTEPLL0_GATE] = <epll0_gate.common.hw,
+ [CLK_TWPLL_GATE] = &twpll_gate.common.hw,
+ [CLK_LTEPLL1_GATE] = <epll1_gate.common.hw,
+ [CLK_RPLL0_GATE] = &rpll0_gate.common.hw,
+ [CLK_RPLL1_GATE] = &rpll1_gate.common.hw,
+ [CLK_CPPLL_GATE] = &cppll_gate.common.hw,
+ [CLK_GPLL_GATE] = &gpll_gate.common.hw,
+ },
+ .num = CLK_PMU_GATE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_pmu_gate_desc = {
+ .clk_clks = sc9860_pmu_gate_clks,
+ .num_clk_clks = ARRAY_SIZE(sc9860_pmu_gate_clks),
+ .hw_clks = &sc9860_pmu_gate_hws,
+};
+
+/* GPLL/LPLL/DPLL/RPLL/CPLL */
+static const u64 itable1[4] = {3, 780000000, 988000000, 1196000000};
+
+/* TWPLL/MPLL0/MPLL1 */
+static const u64 itable2[4] = {3, 1638000000, 2080000000, 2600000000UL};
+
+static const struct clk_bit_field f_mpll0[PLL_FACT_MAX] = {
+ { .shift = 20, .width = 1 }, /* lock_done */
+ { .shift = 19, .width = 1 }, /* div_s */
+ { .shift = 18, .width = 1 }, /* mod_en */
+ { .shift = 17, .width = 1 }, /* sdm_en */
+ { .shift = 0, .width = 0 }, /* refin */
+ { .shift = 11, .width = 2 }, /* ibias */
+ { .shift = 0, .width = 7 }, /* n */
+ { .shift = 57, .width = 7 }, /* nint */
+ { .shift = 32, .width = 23}, /* kint */
+ { .shift = 0, .width = 0 }, /* prediv */
+ { .shift = 56, .width = 1 }, /* postdiv */
+};
+static SPRD_PLL_WITH_ITABLE_K_FVCO(mpll0_clk, "mpll0", "mpll0-gate", 0x24,
+ 2, itable2, f_mpll0, 200,
+ 1000, 1000, 1, 1300000000);
+
+static const struct clk_bit_field f_mpll1[PLL_FACT_MAX] = {
+ { .shift = 20, .width = 1 }, /* lock_done */
+ { .shift = 19, .width = 1 }, /* div_s */
+ { .shift = 18, .width = 1 }, /* mod_en */
+ { .shift = 17, .width = 1 }, /* sdm_en */
+ { .shift = 0, .width = 0 }, /* refin */
+ { .shift = 11, .width = 2 }, /* ibias */
+ { .shift = 0, .width = 7 }, /* n */
+ { .shift = 57, .width = 7 }, /* nint */
+ { .shift = 32, .width = 23}, /* kint */
+ { .shift = 56, .width = 1 }, /* prediv */
+ { .shift = 0, .width = 0 }, /* postdiv */
+};
+static SPRD_PLL_WITH_ITABLE_1K(mpll1_clk, "mpll1", "mpll1-gate", 0x2c,
+ 2, itable2, f_mpll1, 200);
+
+static const struct clk_bit_field f_dpll[PLL_FACT_MAX] = {
+ { .shift = 16, .width = 1 }, /* lock_done */
+ { .shift = 15, .width = 1 }, /* div_s */
+ { .shift = 14, .width = 1 }, /* mod_en */
+ { .shift = 13, .width = 1 }, /* sdm_en */
+ { .shift = 0, .width = 0 }, /* refin */
+ { .shift = 8, .width = 2 }, /* ibias */
+ { .shift = 0, .width = 7 }, /* n */
+ { .shift = 57, .width = 7 }, /* nint */
+ { .shift = 32, .width = 23}, /* kint */
+ { .shift = 0, .width = 0 }, /* prediv */
+ { .shift = 0, .width = 0 }, /* postdiv */
+};
+static SPRD_PLL_WITH_ITABLE_1K(dpll0_clk, "dpll0", "dpll0-gate", 0x34,
+ 2, itable1, f_dpll, 200);
+
+static SPRD_PLL_WITH_ITABLE_1K(dpll1_clk, "dpll1", "dpll1-gate", 0x3c,
+ 2, itable1, f_dpll, 200);
+
+static const struct clk_bit_field f_rpll[PLL_FACT_MAX] = {
+ { .shift = 0, .width = 1 }, /* lock_done */
+ { .shift = 3, .width = 1 }, /* div_s */
+ { .shift = 80, .width = 1 }, /* mod_en */
+ { .shift = 81, .width = 1 }, /* sdm_en */
+ { .shift = 0, .width = 0 }, /* refin */
+ { .shift = 14, .width = 2 }, /* ibias */
+ { .shift = 16, .width = 7 }, /* n */
+ { .shift = 4, .width = 7 }, /* nint */
+ { .shift = 32, .width = 23}, /* kint */
+ { .shift = 0, .width = 0 }, /* prediv */
+ { .shift = 0, .width = 0 }, /* postdiv */
+};
+static SPRD_PLL_WITH_ITABLE_1K(rpll0_clk, "rpll0", "rpll0-gate", 0x44,
+ 3, itable1, f_rpll, 200);
+
+static SPRD_PLL_WITH_ITABLE_1K(rpll1_clk, "rpll1", "rpll1-gate", 0x50,
+ 3, itable1, f_rpll, 200);
+
+static const struct clk_bit_field f_twpll[PLL_FACT_MAX] = {
+ { .shift = 21, .width = 1 }, /* lock_done */
+ { .shift = 20, .width = 1 }, /* div_s */
+ { .shift = 19, .width = 1 }, /* mod_en */
+ { .shift = 18, .width = 1 }, /* sdm_en */
+ { .shift = 0, .width = 0 }, /* refin */
+ { .shift = 13, .width = 2 }, /* ibias */
+ { .shift = 0, .width = 7 }, /* n */
+ { .shift = 57, .width = 7 }, /* nint */
+ { .shift = 32, .width = 23}, /* kint */
+ { .shift = 0, .width = 0 }, /* prediv */
+ { .shift = 0, .width = 0 }, /* postdiv */
+};
+static SPRD_PLL_WITH_ITABLE_1K(twpll_clk, "twpll", "twpll-gate", 0x5c,
+ 2, itable2, f_twpll, 200);
+
+static const struct clk_bit_field f_ltepll[PLL_FACT_MAX] = {
+ { .shift = 31, .width = 1 }, /* lock_done */
+ { .shift = 27, .width = 1 }, /* div_s */
+ { .shift = 26, .width = 1 }, /* mod_en */
+ { .shift = 25, .width = 1 }, /* sdm_en */
+ { .shift = 0, .width = 0 }, /* refin */
+ { .shift = 20, .width = 2 }, /* ibias */
+ { .shift = 0, .width = 7 }, /* n */
+ { .shift = 57, .width = 7 }, /* nint */
+ { .shift = 32, .width = 23}, /* kint */
+ { .shift = 0, .width = 0 }, /* prediv */
+ { .shift = 0, .width = 0 }, /* postdiv */
+};
+static SPRD_PLL_WITH_ITABLE_1K(ltepll0_clk, "ltepll0", "ltepll0-gate",
+ 0x64, 2, itable1,
+ f_ltepll, 200);
+static SPRD_PLL_WITH_ITABLE_1K(ltepll1_clk, "ltepll1", "ltepll1-gate",
+ 0x6c, 2, itable1,
+ f_ltepll, 200);
+
+static const struct clk_bit_field f_gpll[PLL_FACT_MAX] = {
+ { .shift = 18, .width = 1 }, /* lock_done */
+ { .shift = 15, .width = 1 }, /* div_s */
+ { .shift = 14, .width = 1 }, /* mod_en */
+ { .shift = 13, .width = 1 }, /* sdm_en */
+ { .shift = 0, .width = 0 }, /* refin */
+ { .shift = 8, .width = 2 }, /* ibias */
+ { .shift = 0, .width = 7 }, /* n */
+ { .shift = 57, .width = 7 }, /* nint */
+ { .shift = 32, .width = 23}, /* kint */
+ { .shift = 0, .width = 0 }, /* prediv */
+ { .shift = 17, .width = 1 }, /* postdiv */
+};
+static SPRD_PLL_WITH_ITABLE_K_FVCO(gpll_clk, "gpll", "gpll-gate", 0x9c,
+ 2, itable1, f_gpll, 200,
+ 1000, 1000, 1, 600000000);
+
+static const struct clk_bit_field f_cppll[PLL_FACT_MAX] = {
+ { .shift = 17, .width = 1 }, /* lock_done */
+ { .shift = 15, .width = 1 }, /* div_s */
+ { .shift = 14, .width = 1 }, /* mod_en */
+ { .shift = 13, .width = 1 }, /* sdm_en */
+ { .shift = 0, .width = 0 }, /* refin */
+ { .shift = 8, .width = 2 }, /* ibias */
+ { .shift = 0, .width = 7 }, /* n */
+ { .shift = 57, .width = 7 }, /* nint */
+ { .shift = 32, .width = 23}, /* kint */
+ { .shift = 0, .width = 0 }, /* prediv */
+ { .shift = 0, .width = 0 }, /* postdiv */
+};
+static SPRD_PLL_WITH_ITABLE_1K(cppll_clk, "cppll", "cppll-gate", 0xc4,
+ 2, itable1, f_cppll, 200);
+
+static CLK_FIXED_FACTOR(gpll_42m5, "gpll-42m5", "gpll", 20, 1, 0);
+static CLK_FIXED_FACTOR(twpll_768m, "twpll-768m", "twpll", 2, 1, 0);
+static CLK_FIXED_FACTOR(twpll_384m, "twpll-384m", "twpll", 4, 1, 0);
+static CLK_FIXED_FACTOR(twpll_192m, "twpll-192m", "twpll", 8, 1, 0);
+static CLK_FIXED_FACTOR(twpll_96m, "twpll-96m", "twpll", 16, 1, 0);
+static CLK_FIXED_FACTOR(twpll_48m, "twpll-48m", "twpll", 32, 1, 0);
+static CLK_FIXED_FACTOR(twpll_24m, "twpll-24m", "twpll", 64, 1, 0);
+static CLK_FIXED_FACTOR(twpll_12m, "twpll-12m", "twpll", 128, 1, 0);
+static CLK_FIXED_FACTOR(twpll_512m, "twpll-512m", "twpll", 3, 1, 0);
+static CLK_FIXED_FACTOR(twpll_256m, "twpll-256m", "twpll", 6, 1, 0);
+static CLK_FIXED_FACTOR(twpll_128m, "twpll-128m", "twpll", 12, 1, 0);
+static CLK_FIXED_FACTOR(twpll_64m, "twpll-64m", "twpll", 24, 1, 0);
+static CLK_FIXED_FACTOR(twpll_307m2, "twpll-307m2", "twpll", 5, 1, 0);
+static CLK_FIXED_FACTOR(twpll_153m6, "twpll-153m6", "twpll", 10, 1, 0);
+static CLK_FIXED_FACTOR(twpll_76m8, "twpll-76m8", "twpll", 20, 1, 0);
+static CLK_FIXED_FACTOR(twpll_51m2, "twpll-51m2", "twpll", 30, 1, 0);
+static CLK_FIXED_FACTOR(twpll_38m4, "twpll-38m4", "twpll", 40, 1, 0);
+static CLK_FIXED_FACTOR(twpll_19m2, "twpll-19m2", "twpll", 80, 1, 0);
+static CLK_FIXED_FACTOR(l0_614m4, "l0-614m4", "ltepll0", 2, 1, 0);
+static CLK_FIXED_FACTOR(l0_409m6, "l0-409m6", "ltepll0", 3, 1, 0);
+static CLK_FIXED_FACTOR(l0_38m, "l0-38m", "ltepll0", 32, 1, 0);
+static CLK_FIXED_FACTOR(l1_38m, "l1-38m", "ltepll1", 32, 1, 0);
+static CLK_FIXED_FACTOR(rpll0_192m, "rpll0-192m", "rpll0", 6, 1, 0);
+static CLK_FIXED_FACTOR(rpll0_96m, "rpll0-96m", "rpll0", 12, 1, 0);
+static CLK_FIXED_FACTOR(rpll0_48m, "rpll0-48m", "rpll0", 24, 1, 0);
+static CLK_FIXED_FACTOR(rpll1_468m, "rpll1-468m", "rpll1", 2, 1, 0);
+static CLK_FIXED_FACTOR(rpll1_192m, "rpll1-192m", "rpll1", 6, 1, 0);
+static CLK_FIXED_FACTOR(rpll1_96m, "rpll1-96m", "rpll1", 12, 1, 0);
+static CLK_FIXED_FACTOR(rpll1_64m, "rpll1-64m", "rpll1", 18, 1, 0);
+static CLK_FIXED_FACTOR(rpll1_48m, "rpll1-48m", "rpll1", 24, 1, 0);
+static CLK_FIXED_FACTOR(dpll0_50m, "dpll0-50m", "dpll0", 16, 1, 0);
+static CLK_FIXED_FACTOR(dpll1_50m, "dpll1-50m", "dpll1", 16, 1, 0);
+static CLK_FIXED_FACTOR(cppll_50m, "cppll-50m", "cppll", 18, 1, 0);
+static CLK_FIXED_FACTOR(m0_39m, "m0-39m", "mpll0", 32, 1, 0);
+static CLK_FIXED_FACTOR(m1_63m, "m1-63m", "mpll1", 32, 1, 0);
+
+static struct sprd_clk_common *sc9860_pll_clks[] = {
+ /* address base is 0x40400000 */
+ &mpll0_clk.common,
+ &mpll1_clk.common,
+ &dpll0_clk.common,
+ &dpll1_clk.common,
+ &rpll0_clk.common,
+ &rpll1_clk.common,
+ &twpll_clk.common,
+ <epll0_clk.common,
+ <epll1_clk.common,
+ &gpll_clk.common,
+ &cppll_clk.common,
+};
+
+static struct clk_hw_onecell_data sc9860_pll_hws = {
+ .hws = {
+ [CLK_MPLL0] = &mpll0_clk.common.hw,
+ [CLK_MPLL1] = &mpll1_clk.common.hw,
+ [CLK_DPLL0] = &dpll0_clk.common.hw,
+ [CLK_DPLL1] = &dpll1_clk.common.hw,
+ [CLK_RPLL0] = &rpll0_clk.common.hw,
+ [CLK_RPLL1] = &rpll1_clk.common.hw,
+ [CLK_TWPLL] = &twpll_clk.common.hw,
+ [CLK_LTEPLL0] = <epll0_clk.common.hw,
+ [CLK_LTEPLL1] = <epll1_clk.common.hw,
+ [CLK_GPLL] = &gpll_clk.common.hw,
+ [CLK_CPPLL] = &cppll_clk.common.hw,
+ [CLK_GPLL_42M5] = &gpll_42m5.hw,
+ [CLK_TWPLL_768M] = &twpll_768m.hw,
+ [CLK_TWPLL_384M] = &twpll_384m.hw,
+ [CLK_TWPLL_192M] = &twpll_192m.hw,
+ [CLK_TWPLL_96M] = &twpll_96m.hw,
+ [CLK_TWPLL_48M] = &twpll_48m.hw,
+ [CLK_TWPLL_24M] = &twpll_24m.hw,
+ [CLK_TWPLL_12M] = &twpll_12m.hw,
+ [CLK_TWPLL_512M] = &twpll_512m.hw,
+ [CLK_TWPLL_256M] = &twpll_256m.hw,
+ [CLK_TWPLL_128M] = &twpll_128m.hw,
+ [CLK_TWPLL_64M] = &twpll_64m.hw,
+ [CLK_TWPLL_307M2] = &twpll_307m2.hw,
+ [CLK_TWPLL_153M6] = &twpll_153m6.hw,
+ [CLK_TWPLL_76M8] = &twpll_76m8.hw,
+ [CLK_TWPLL_51M2] = &twpll_51m2.hw,
+ [CLK_TWPLL_38M4] = &twpll_38m4.hw,
+ [CLK_TWPLL_19M2] = &twpll_19m2.hw,
+ [CLK_L0_614M4] = &l0_614m4.hw,
+ [CLK_L0_409M6] = &l0_409m6.hw,
+ [CLK_L0_38M] = &l0_38m.hw,
+ [CLK_L1_38M] = &l1_38m.hw,
+ [CLK_RPLL0_192M] = &rpll0_192m.hw,
+ [CLK_RPLL0_96M] = &rpll0_96m.hw,
+ [CLK_RPLL0_48M] = &rpll0_48m.hw,
+ [CLK_RPLL1_468M] = &rpll1_468m.hw,
+ [CLK_RPLL1_192M] = &rpll1_192m.hw,
+ [CLK_RPLL1_96M] = &rpll1_96m.hw,
+ [CLK_RPLL1_64M] = &rpll1_64m.hw,
+ [CLK_RPLL1_48M] = &rpll1_48m.hw,
+ [CLK_DPLL0_50M] = &dpll0_50m.hw,
+ [CLK_DPLL1_50M] = &dpll1_50m.hw,
+ [CLK_CPPLL_50M] = &cppll_50m.hw,
+ [CLK_M0_39M] = &m0_39m.hw,
+ [CLK_M1_63M] = &m1_63m.hw,
+ },
+ .num = CLK_PLL_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_pll_desc = {
+ .clk_clks = sc9860_pll_clks,
+ .num_clk_clks = ARRAY_SIZE(sc9860_pll_clks),
+ .hw_clks = &sc9860_pll_hws,
+};
+
+#define SC9860_MUX_FLAG \
+ (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT)
+
+static const char * const ap_apb_parents[] = { "ext-26m", "twpll-64m",
+ "twpll-96m", "twpll-128m" };
+static SPRD_MUX_CLK(ap_apb, "ap-apb", ap_apb_parents,
+ 0x20, 0, 1, SC9860_MUX_FLAG);
+
+static const char * const ap_apb_usb3[] = { "ext-32k", "twpll-24m" };
+static SPRD_MUX_CLK(ap_usb3, "ap-usb3", ap_apb_usb3,
+ 0x2c, 0, 1, SC9860_MUX_FLAG);
+
+static const char * const uart_parents[] = { "ext-26m", "twpll-48m",
+ "twpll-51m2", "twpll-96m" };
+static SPRD_COMP_CLK(uart0_clk, "uart0", uart_parents, 0x30,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(uart1_clk, "uart1", uart_parents, 0x34,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(uart2_clk, "uart2", uart_parents, 0x38,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(uart3_clk, "uart3", uart_parents, 0x3c,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(uart4_clk, "uart4", uart_parents, 0x40,
+ 0, 2, 8, 3, 0);
+
+static const char * const i2c_parents[] = { "ext-26m", "twpll-48m",
+ "twpll-51m2", "twpll-153m6" };
+static SPRD_COMP_CLK(i2c0_clk, "i2c0", i2c_parents, 0x44,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(i2c1_clk, "i2c1", i2c_parents, 0x48,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(i2c2_clk, "i2c2", i2c_parents, 0x4c,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(i2c3_clk, "i2c3", i2c_parents, 0x50,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(i2c4_clk, "i2c4", i2c_parents, 0x54,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(i2c5_clk, "i2c5", i2c_parents, 0x58,
+ 0, 2, 8, 3, 0);
+
+static const char * const spi_parents[] = { "ext-26m", "twpll-128m",
+ "twpll-153m6", "twpll-192m" };
+static SPRD_COMP_CLK(spi0_clk, "spi0", spi_parents, 0x5c,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(spi1_clk, "spi1", spi_parents, 0x60,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(spi2_clk, "spi2", spi_parents, 0x64,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(spi3_clk, "spi3", spi_parents, 0x68,
+ 0, 2, 8, 3, 0);
+
+static const char * const iis_parents[] = { "ext-26m",
+ "twpll-128m",
+ "twpll-153m6" };
+static SPRD_COMP_CLK(iis0_clk, "iis0", iis_parents, 0x6c,
+ 0, 2, 8, 6, 0);
+static SPRD_COMP_CLK(iis1_clk, "iis1", iis_parents, 0x70,
+ 0, 2, 8, 6, 0);
+static SPRD_COMP_CLK(iis2_clk, "iis2", iis_parents, 0x74,
+ 0, 2, 8, 6, 0);
+static SPRD_COMP_CLK(iis3_clk, "iis3", iis_parents, 0x78,
+ 0, 2, 8, 6, 0);
+
+static struct sprd_clk_common *sc9860_ap_clks[] = {
+ /* address base is 0x20000000 */
+ &ap_apb.common,
+ &ap_usb3.common,
+ &uart0_clk.common,
+ &uart1_clk.common,
+ &uart2_clk.common,
+ &uart3_clk.common,
+ &uart4_clk.common,
+ &i2c0_clk.common,
+ &i2c1_clk.common,
+ &i2c2_clk.common,
+ &i2c3_clk.common,
+ &i2c4_clk.common,
+ &i2c5_clk.common,
+ &spi0_clk.common,
+ &spi1_clk.common,
+ &spi2_clk.common,
+ &spi3_clk.common,
+ &iis0_clk.common,
+ &iis1_clk.common,
+ &iis2_clk.common,
+ &iis3_clk.common,
+};
+
+static struct clk_hw_onecell_data sc9860_ap_clk_hws = {
+ .hws = {
+ [CLK_AP_APB] = &ap_apb.common.hw,
+ [CLK_AP_USB3] = &ap_usb3.common.hw,
+ [CLK_UART0] = &uart0_clk.common.hw,
+ [CLK_UART1] = &uart1_clk.common.hw,
+ [CLK_UART2] = &uart2_clk.common.hw,
+ [CLK_UART3] = &uart3_clk.common.hw,
+ [CLK_UART4] = &uart4_clk.common.hw,
+ [CLK_I2C0] = &i2c0_clk.common.hw,
+ [CLK_I2C1] = &i2c1_clk.common.hw,
+ [CLK_I2C2] = &i2c2_clk.common.hw,
+ [CLK_I2C3] = &i2c3_clk.common.hw,
+ [CLK_I2C4] = &i2c4_clk.common.hw,
+ [CLK_I2C5] = &i2c5_clk.common.hw,
+ [CLK_SPI0] = &spi0_clk.common.hw,
+ [CLK_SPI1] = &spi1_clk.common.hw,
+ [CLK_SPI2] = &spi2_clk.common.hw,
+ [CLK_SPI3] = &spi3_clk.common.hw,
+ [CLK_IIS0] = &iis0_clk.common.hw,
+ [CLK_IIS1] = &iis1_clk.common.hw,
+ [CLK_IIS2] = &iis2_clk.common.hw,
+ [CLK_IIS3] = &iis3_clk.common.hw,
+ },
+ .num = CLK_AP_CLK_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_ap_clk_desc = {
+ .clk_clks = sc9860_ap_clks,
+ .num_clk_clks = ARRAY_SIZE(sc9860_ap_clks),
+ .hw_clks = &sc9860_ap_clk_hws,
+};
+
+static const char * const aon_apb_parents[] = { "rco-25m", "ext-26m",
+ "ext-rco-100m", "twpll-96m",
+ "twpll-128m",
+ "twpll-153m6" };
+static SPRD_COMP_CLK(aon_apb, "aon-apb", aon_apb_parents, 0x230,
+ 0, 3, 8, 2, 0);
+
+static const char * const aux_parents[] = { "ext-32k", "rpll0-26m",
+ "rpll1-26m", "ext-26m",
+ "cppll-50m", "rco-25m",
+ "dpll0-50m", "dpll1-50m",
+ "gpll-42m5", "twpll-48m",
+ "m0-39m", "m1-63m",
+ "l0-38m", "l1-38m" };
+
+static SPRD_COMP_CLK(aux0_clk, "aux0", aux_parents, 0x238,
+ 0, 5, 8, 4, 0);
+static SPRD_COMP_CLK(aux1_clk, "aux1", aux_parents, 0x23c,
+ 0, 5, 8, 4, 0);
+static SPRD_COMP_CLK(aux2_clk, "aux2", aux_parents, 0x240,
+ 0, 5, 8, 4, 0);
+static SPRD_COMP_CLK(probe_clk, "probe", aux_parents, 0x244,
+ 0, 5, 8, 4, 0);
+
+static const char * const sp_ahb_parents[] = { "rco-4m", "ext-26m",
+ "ext-rco-100m", "twpll-96m",
+ "twpll-128m",
+ "twpll-153m6" };
+static SPRD_COMP_CLK(sp_ahb, "sp-ahb", sp_ahb_parents, 0x2d0,
+ 0, 3, 8, 2, 0);
+
+static const char * const cci_parents[] = { "ext-26m", "twpll-384m",
+ "l0-614m4", "twpll-768m" };
+static SPRD_COMP_CLK(cci_clk, "cci", cci_parents, 0x300,
+ 0, 2, 8, 2, 0);
+static SPRD_COMP_CLK(gic_clk, "gic", cci_parents, 0x304,
+ 0, 2, 8, 2, 0);
+static SPRD_COMP_CLK(cssys_clk, "cssys", cci_parents, 0x310,
+ 0, 2, 8, 2, 0);
+
+static const char * const sdio_2x_parents[] = { "fac-1m", "ext-26m",
+ "twpll-307m2", "twpll-384m",
+ "l0-409m6" };
+static SPRD_COMP_CLK(sdio0_2x, "sdio0-2x", sdio_2x_parents, 0x328,
+ 0, 3, 8, 4, 0);
+static SPRD_COMP_CLK(sdio1_2x, "sdio1-2x", sdio_2x_parents, 0x330,
+ 0, 3, 8, 4, 0);
+static SPRD_COMP_CLK(sdio2_2x, "sdio2-2x", sdio_2x_parents, 0x338,
+ 0, 3, 8, 4, 0);
+static SPRD_COMP_CLK(emmc_2x, "emmc-2x", sdio_2x_parents, 0x340,
+ 0, 3, 8, 4, 0);
+
+static SPRD_DIV_CLK(sdio0_1x, "sdio0-1x", "sdio0-2x", 0x32c,
+ 8, 1, 0);
+static SPRD_DIV_CLK(sdio1_1x, "sdio1-1x", "sdio1-2x", 0x334,
+ 8, 1, 0);
+static SPRD_DIV_CLK(sdio2_1x, "sdio2-1x", "sdio2-2x", 0x33c,
+ 8, 1, 0);
+static SPRD_DIV_CLK(emmc_1x, "emmc-1x", "emmc-2x", 0x344,
+ 8, 1, 0);
+
+static const char * const adi_parents[] = { "rco-4m", "ext-26m",
+ "rco-25m", "twpll-38m4",
+ "twpll-51m2" };
+static SPRD_MUX_CLK(adi_clk, "adi", adi_parents, 0x234,
+ 0, 3, SC9860_MUX_FLAG);
+
+static const char * const pwm_parents[] = { "ext-32k", "ext-26m",
+ "rco-4m", "rco-25m",
+ "twpll-48m" };
+static SPRD_MUX_CLK(pwm0_clk, "pwm0", pwm_parents, 0x248,
+ 0, 3, SC9860_MUX_FLAG);
+static SPRD_MUX_CLK(pwm1_clk, "pwm1", pwm_parents, 0x24c,
+ 0, 3, SC9860_MUX_FLAG);
+static SPRD_MUX_CLK(pwm2_clk, "pwm2", pwm_parents, 0x250,
+ 0, 3, SC9860_MUX_FLAG);
+static SPRD_MUX_CLK(pwm3_clk, "pwm3", pwm_parents, 0x254,
+ 0, 3, SC9860_MUX_FLAG);
+
+static const char * const efuse_parents[] = { "rco-25m", "ext-26m" };
+static SPRD_MUX_CLK(efuse_clk, "efuse", efuse_parents, 0x258,
+ 0, 1, SC9860_MUX_FLAG);
+
+static const char * const cm3_uart_parents[] = { "rco-4m", "ext-26m",
+ "rco-100m", "twpll-48m",
+ "twpll-51m2", "twpll-96m",
+ "twpll-128m" };
+static SPRD_MUX_CLK(cm3_uart0, "cm3-uart0", cm3_uart_parents, 0x25c,
+ 0, 3, SC9860_MUX_FLAG);
+static SPRD_MUX_CLK(cm3_uart1, "cm3-uart1", cm3_uart_parents, 0x260,
+ 0, 3, SC9860_MUX_FLAG);
+
+static const char * const thm_parents[] = { "ext-32k", "fac-250k" };
+static SPRD_MUX_CLK(thm_clk, "thm", thm_parents, 0x270,
+ 0, 1, SC9860_MUX_FLAG);
+
+static const char * const cm3_i2c_parents[] = { "rco-4m",
+ "ext-26m",
+ "rco-100m",
+ "twpll-48m",
+ "twpll-51m2",
+ "twpll-153m6" };
+static SPRD_MUX_CLK(cm3_i2c0, "cm3-i2c0", cm3_i2c_parents, 0x274,
+ 0, 3, SC9860_MUX_FLAG);
+static SPRD_MUX_CLK(cm3_i2c1, "cm3-i2c1", cm3_i2c_parents, 0x278,
+ 0, 3, SC9860_MUX_FLAG);
+static SPRD_MUX_CLK(aon_i2c, "aon-i2c", cm3_i2c_parents, 0x280,
+ 0, 3, SC9860_MUX_FLAG);
+
+static const char * const cm4_spi_parents[] = { "ext-26m", "twpll-96m",
+ "rco-100m", "twpll-128m",
+ "twpll-153m6", "twpll-192m" };
+static SPRD_MUX_CLK(cm4_spi, "cm4-spi", cm4_spi_parents, 0x27c,
+ 0, 3, SC9860_MUX_FLAG);
+
+static SPRD_MUX_CLK(avs_clk, "avs", uart_parents, 0x284,
+ 0, 2, SC9860_MUX_FLAG);
+
+static const char * const ca53_dap_parents[] = { "ext-26m", "rco-4m",
+ "rco-100m", "twpll-76m8",
+ "twpll-128m", "twpll-153m6" };
+static SPRD_MUX_CLK(ca53_dap, "ca53-dap", ca53_dap_parents, 0x288,
+ 0, 3, SC9860_MUX_FLAG);
+
+static const char * const ca53_ts_parents[] = { "ext-32k", "ext-26m",
+ "clk-twpll-128m",
+ "clk-twpll-153m6" };
+static SPRD_MUX_CLK(ca53_ts, "ca53-ts", ca53_ts_parents, 0x290,
+ 0, 2, SC9860_MUX_FLAG);
+
+static const char * const djtag_tck_parents[] = { "rco-4m", "ext-26m" };
+static SPRD_MUX_CLK(djtag_tck, "djtag-tck", djtag_tck_parents, 0x2c8,
+ 0, 1, SC9860_MUX_FLAG);
+
+static const char * const pmu_parents[] = { "ext-32k", "rco-4m", "clk-4m" };
+static SPRD_MUX_CLK(pmu_clk, "pmu", pmu_parents, 0x2e0,
+ 0, 2, SC9860_MUX_FLAG);
+
+static const char * const pmu_26m_parents[] = { "rco-25m", "ext-26m" };
+static SPRD_MUX_CLK(pmu_26m, "pmu-26m", pmu_26m_parents, 0x2e4,
+ 0, 1, SC9860_MUX_FLAG);
+
+static const char * const debounce_parents[] = { "ext-32k", "rco-4m",
+ "rco-25m", "ext-26m" };
+static SPRD_MUX_CLK(debounce_clk, "debounce", debounce_parents, 0x2e8,
+ 0, 2, SC9860_MUX_FLAG);
+
+static const char * const otg2_ref_parents[] = { "twpll-12m", "twpll-24m" };
+static SPRD_MUX_CLK(otg2_ref, "otg2-ref", otg2_ref_parents, 0x2f4,
+ 0, 1, SC9860_MUX_FLAG);
+
+static const char * const usb3_ref_parents[] = { "twpll-24m", "twpll-19m2",
+ "twpll-48m" };
+static SPRD_MUX_CLK(usb3_ref, "usb3-ref", usb3_ref_parents, 0x2f8,
+ 0, 2, SC9860_MUX_FLAG);
+
+static const char * const ap_axi_parents[] = { "ext-26m", "twpll-76m8",
+ "twpll-128m", "twpll-256m" };
+static SPRD_MUX_CLK(ap_axi, "ap-axi", ap_axi_parents, 0x324,
+ 0, 2, SC9860_MUX_FLAG);
+
+static struct sprd_clk_common *sc9860_aon_prediv[] = {
+ /* address base is 0x402d0000 */
+ &aon_apb.common,
+ &aux0_clk.common,
+ &aux1_clk.common,
+ &aux2_clk.common,
+ &probe_clk.common,
+ &sp_ahb.common,
+ &cci_clk.common,
+ &gic_clk.common,
+ &cssys_clk.common,
+ &sdio0_2x.common,
+ &sdio1_2x.common,
+ &sdio2_2x.common,
+ &emmc_2x.common,
+ &sdio0_1x.common,
+ &sdio1_1x.common,
+ &sdio2_1x.common,
+ &emmc_1x.common,
+ &adi_clk.common,
+ &pwm0_clk.common,
+ &pwm1_clk.common,
+ &pwm2_clk.common,
+ &pwm3_clk.common,
+ &efuse_clk.common,
+ &cm3_uart0.common,
+ &cm3_uart1.common,
+ &thm_clk.common,
+ &cm3_i2c0.common,
+ &cm3_i2c1.common,
+ &cm4_spi.common,
+ &aon_i2c.common,
+ &avs_clk.common,
+ &ca53_dap.common,
+ &ca53_ts.common,
+ &djtag_tck.common,
+ &pmu_clk.common,
+ &pmu_26m.common,
+ &debounce_clk.common,
+ &otg2_ref.common,
+ &usb3_ref.common,
+ &ap_axi.common,
+};
+
+static struct clk_hw_onecell_data sc9860_aon_prediv_hws = {
+ .hws = {
+ [CLK_AON_APB] = &aon_apb.common.hw,
+ [CLK_AUX0] = &aux0_clk.common.hw,
+ [CLK_AUX1] = &aux1_clk.common.hw,
+ [CLK_AUX2] = &aux2_clk.common.hw,
+ [CLK_PROBE] = &probe_clk.common.hw,
+ [CLK_SP_AHB] = &sp_ahb.common.hw,
+ [CLK_CCI] = &cci_clk.common.hw,
+ [CLK_GIC] = &gic_clk.common.hw,
+ [CLK_CSSYS] = &cssys_clk.common.hw,
+ [CLK_SDIO0_2X] = &sdio0_2x.common.hw,
+ [CLK_SDIO1_2X] = &sdio1_2x.common.hw,
+ [CLK_SDIO2_2X] = &sdio2_2x.common.hw,
+ [CLK_EMMC_2X] = &emmc_2x.common.hw,
+ [CLK_SDIO0_1X] = &sdio0_1x.common.hw,
+ [CLK_SDIO1_1X] = &sdio1_1x.common.hw,
+ [CLK_SDIO2_1X] = &sdio2_1x.common.hw,
+ [CLK_EMMC_1X] = &emmc_1x.common.hw,
+ [CLK_ADI] = &adi_clk.common.hw,
+ [CLK_PWM0] = &pwm0_clk.common.hw,
+ [CLK_PWM1] = &pwm1_clk.common.hw,
+ [CLK_PWM2] = &pwm2_clk.common.hw,
+ [CLK_PWM3] = &pwm3_clk.common.hw,
+ [CLK_EFUSE] = &efuse_clk.common.hw,
+ [CLK_CM3_UART0] = &cm3_uart0.common.hw,
+ [CLK_CM3_UART1] = &cm3_uart1.common.hw,
+ [CLK_THM] = &thm_clk.common.hw,
+ [CLK_CM3_I2C0] = &cm3_i2c0.common.hw,
+ [CLK_CM3_I2C1] = &cm3_i2c1.common.hw,
+ [CLK_CM4_SPI] = &cm4_spi.common.hw,
+ [CLK_AON_I2C] = &aon_i2c.common.hw,
+ [CLK_AVS] = &avs_clk.common.hw,
+ [CLK_CA53_DAP] = &ca53_dap.common.hw,
+ [CLK_CA53_TS] = &ca53_ts.common.hw,
+ [CLK_DJTAG_TCK] = &djtag_tck.common.hw,
+ [CLK_PMU] = &pmu_clk.common.hw,
+ [CLK_PMU_26M] = &pmu_26m.common.hw,
+ [CLK_DEBOUNCE] = &debounce_clk.common.hw,
+ [CLK_OTG2_REF] = &otg2_ref.common.hw,
+ [CLK_USB3_REF] = &usb3_ref.common.hw,
+ [CLK_AP_AXI] = &ap_axi.common.hw,
+ },
+ .num = CLK_AON_PREDIV_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_aon_prediv_desc = {
+ .clk_clks = sc9860_aon_prediv,
+ .num_clk_clks = ARRAY_SIZE(sc9860_aon_prediv),
+ .hw_clks = &sc9860_aon_prediv_hws,
+};
+
+static SPRD_SC_GATE_CLK(usb3_eb, "usb3-eb", "ap-axi", 0x0,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(usb3_suspend, "usb3-suspend", "ap-axi", 0x0,
+ 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(usb3_ref_eb, "usb3-ref-eb", "ap-axi", 0x0,
+ 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(dma_eb, "dma-eb", "ap-axi", 0x0,
+ 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(sdio0_eb, "sdio0-eb", "ap-axi", 0x0,
+ 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(sdio1_eb, "sdio1-eb", "ap-axi", 0x0,
+ 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(sdio2_eb, "sdio2-eb", "ap-axi", 0x0,
+ 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(emmc_eb, "emmc-eb", "ap-axi", 0x0,
+ 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(rom_eb, "rom-eb", "ap-axi", 0x0,
+ 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(busmon_eb, "busmon-eb", "ap-axi", 0x0,
+ 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(cc63s_eb, "cc63s-eb", "ap-axi", 0x0,
+ 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(cc63p_eb, "cc63p-eb", "ap-axi", 0x0,
+ 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ce0_eb, "ce0-eb", "ap-axi", 0x0,
+ 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ce1_eb, "ce1-eb", "ap-axi", 0x0,
+ 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);
+
+static struct sprd_clk_common *sc9860_apahb_gate[] = {
+ /* address base is 0x20210000 */
+ &usb3_eb.common,
+ &usb3_suspend.common,
+ &usb3_ref_eb.common,
+ &dma_eb.common,
+ &sdio0_eb.common,
+ &sdio1_eb.common,
+ &sdio2_eb.common,
+ &emmc_eb.common,
+ &rom_eb.common,
+ &busmon_eb.common,
+ &cc63s_eb.common,
+ &cc63p_eb.common,
+ &ce0_eb.common,
+ &ce1_eb.common,
+};
+
+static struct clk_hw_onecell_data sc9860_apahb_gate_hws = {
+ .hws = {
+ [CLK_USB3_EB] = &usb3_eb.common.hw,
+ [CLK_USB3_SUSPEND_EB] = &usb3_suspend.common.hw,
+ [CLK_USB3_REF_EB] = &usb3_ref_eb.common.hw,
+ [CLK_DMA_EB] = &dma_eb.common.hw,
+ [CLK_SDIO0_EB] = &sdio0_eb.common.hw,
+ [CLK_SDIO1_EB] = &sdio1_eb.common.hw,
+ [CLK_SDIO2_EB] = &sdio2_eb.common.hw,
+ [CLK_EMMC_EB] = &emmc_eb.common.hw,
+ [CLK_ROM_EB] = &rom_eb.common.hw,
+ [CLK_BUSMON_EB] = &busmon_eb.common.hw,
+ [CLK_CC63S_EB] = &cc63s_eb.common.hw,
+ [CLK_CC63P_EB] = &cc63p_eb.common.hw,
+ [CLK_CE0_EB] = &ce0_eb.common.hw,
+ [CLK_CE1_EB] = &ce1_eb.common.hw,
+ },
+ .num = CLK_APAHB_GATE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_apahb_gate_desc = {
+ .clk_clks = sc9860_apahb_gate,
+ .num_clk_clks = ARRAY_SIZE(sc9860_apahb_gate),
+ .hw_clks = &sc9860_apahb_gate_hws,
+};
+
+static SPRD_SC_GATE_CLK(avs_lit_eb, "avs-lit-eb", "aon-apb", 0x0,
+ 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(avs_big_eb, "avs-big-eb", "aon-apb", 0x0,
+ 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_intc5_eb, "ap-intc5-eb", "aon-apb", 0x0,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(gpio_eb, "gpio-eb", "aon-apb", 0x0,
+ 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(pwm0_eb, "pwm0-eb", "aon-apb", 0x0,
+ 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(pwm1_eb, "pwm1-eb", "aon-apb", 0x0,
+ 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(pwm2_eb, "pwm2-eb", "aon-apb", 0x0,
+ 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(pwm3_eb, "pwm3-eb", "aon-apb", 0x0,
+ 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(kpd_eb, "kpd-eb", "aon-apb", 0x0,
+ 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(aon_sys_eb, "aon-sys-eb", "aon-apb", 0x0,
+ 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_sys_eb, "ap-sys-eb", "aon-apb", 0x0,
+ 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(aon_tmr_eb, "aon-tmr-eb", "aon-apb", 0x0,
+ 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_tmr0_eb, "ap-tmr0-eb", "aon-apb", 0x0,
+ 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(efuse_eb, "efuse-eb", "aon-apb", 0x0,
+ 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(eic_eb, "eic-eb", "aon-apb", 0x0,
+ 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(pub1_reg_eb, "pub1-reg-eb", "aon-apb", 0x0,
+ 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(adi_eb, "adi-eb", "aon-apb", 0x0,
+ 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_intc0_eb, "ap-intc0-eb", "aon-apb", 0x0,
+ 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_intc1_eb, "ap-intc1-eb", "aon-apb", 0x0,
+ 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_intc2_eb, "ap-intc2-eb", "aon-apb", 0x0,
+ 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_intc3_eb, "ap-intc3-eb", "aon-apb", 0x0,
+ 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_intc4_eb, "ap-intc4-eb", "aon-apb", 0x0,
+ 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(splk_eb, "splk-eb", "aon-apb", 0x0,
+ 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(mspi_eb, "mspi-eb", "aon-apb", 0x0,
+ 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(pub0_reg_eb, "pub0-reg-eb", "aon-apb", 0x0,
+ 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(pin_eb, "pin-eb", "aon-apb", 0x0,
+ 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(aon_ckg_eb, "aon-ckg-eb", "aon-apb", 0x0,
+ 0x1000, BIT(26), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(gpu_eb, "gpu-eb", "aon-apb", 0x0,
+ 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(apcpu_ts0_eb, "apcpu-ts0-eb", "aon-apb", 0x0,
+ 0x1000, BIT(28), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(apcpu_ts1_eb, "apcpu-ts1-eb", "aon-apb", 0x0,
+ 0x1000, BIT(29), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(dap_eb, "dap-eb", "aon-apb", 0x0,
+ 0x1000, BIT(30), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(i2c_eb, "i2c-eb", "aon-apb", 0x0,
+ 0x1000, BIT(31), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(pmu_eb, "pmu-eb", "aon-apb", 0x4,
+ 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(thm_eb, "thm-eb", "aon-apb", 0x4,
+ 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(aux0_eb, "aux0-eb", "aon-apb", 0x4,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(aux1_eb, "aux1-eb", "aon-apb", 0x4,
+ 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(aux2_eb, "aux2-eb", "aon-apb", 0x4,
+ 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(probe_eb, "probe-eb", "aon-apb", 0x4,
+ 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(gpu0_avs_eb, "gpu0-avs-eb", "aon-apb", 0x4,
+ 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(gpu1_avs_eb, "gpu1-avs-eb", "aon-apb", 0x4,
+ 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(apcpu_wdg_eb, "apcpu-wdg-eb", "aon-apb", 0x4,
+ 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_tmr1_eb, "ap-tmr1-eb", "aon-apb", 0x4,
+ 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_tmr2_eb, "ap-tmr2-eb", "aon-apb", 0x4,
+ 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(disp_emc_eb, "disp-emc-eb", "aon-apb", 0x4,
+ 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(zip_emc_eb, "zip-emc-eb", "aon-apb", 0x4,
+ 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(gsp_emc_eb, "gsp-emc-eb", "aon-apb", 0x4,
+ 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(osc_aon_eb, "osc-aon-eb", "aon-apb", 0x4,
+ 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(lvds_trx_eb, "lvds-trx-eb", "aon-apb", 0x4,
+ 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(lvds_tcxo_eb, "lvds-tcxo-eb", "aon-apb", 0x4,
+ 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(mdar_eb, "mdar-eb", "aon-apb", 0x4,
+ 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(rtc4m0_cal_eb, "rtc4m0-cal-eb", "aon-apb", 0x4,
+ 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(rct100m_cal_eb, "rct100m-cal-eb", "aon-apb", 0x4,
+ 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(djtag_eb, "djtag-eb", "aon-apb", 0x4,
+ 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(mbox_eb, "mbox-eb", "aon-apb", 0x4,
+ 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(aon_dma_eb, "aon-dma-eb", "aon-apb", 0x4,
+ 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(dbg_emc_eb, "dbg-emc-eb", "aon-apb", 0x4,
+ 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(lvds_pll_div_en, "lvds-pll-div-en", "aon-apb", 0x4,
+ 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(def_eb, "def-eb", "aon-apb", 0x4,
+ 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(aon_apb_rsv0, "aon-apb-rsv0", "aon-apb", 0x4,
+ 0x1000, BIT(26), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(orp_jtag_eb, "orp-jtag-eb", "aon-apb", 0x4,
+ 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(vsp_eb, "vsp-eb", "aon-apb", 0x4,
+ 0x1000, BIT(28), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(cam_eb, "cam-eb", "aon-apb", 0x4,
+ 0x1000, BIT(29), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(disp_eb, "disp-eb", "aon-apb", 0x4,
+ 0x1000, BIT(30), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(dbg_axi_if_eb, "dbg-axi-if-eb", "aon-apb", 0x4,
+ 0x1000, BIT(31), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(sdio0_2x_en, "sdio0-2x-en", "aon-apb", 0x13c,
+ 0x1000, BIT(2), 0, 0);
+static SPRD_SC_GATE_CLK(sdio1_2x_en, "sdio1-2x-en", "aon-apb", 0x13c,
+ 0x1000, BIT(4), 0, 0);
+static SPRD_SC_GATE_CLK(sdio2_2x_en, "sdio2-2x-en", "aon-apb", 0x13c,
+ 0x1000, BIT(6), 0, 0);
+static SPRD_SC_GATE_CLK(emmc_2x_en, "emmc-2x-en", "aon-apb", 0x13c,
+ 0x1000, BIT(9), 0, 0);
+
+static struct sprd_clk_common *sc9860_aon_gate[] = {
+ /* address base is 0x402e0000 */
+ &avs_lit_eb.common,
+ &avs_big_eb.common,
+ &ap_intc5_eb.common,
+ &gpio_eb.common,
+ &pwm0_eb.common,
+ &pwm1_eb.common,
+ &pwm2_eb.common,
+ &pwm3_eb.common,
+ &kpd_eb.common,
+ &aon_sys_eb.common,
+ &ap_sys_eb.common,
+ &aon_tmr_eb.common,
+ &ap_tmr0_eb.common,
+ &efuse_eb.common,
+ &eic_eb.common,
+ &pub1_reg_eb.common,
+ &adi_eb.common,
+ &ap_intc0_eb.common,
+ &ap_intc1_eb.common,
+ &ap_intc2_eb.common,
+ &ap_intc3_eb.common,
+ &ap_intc4_eb.common,
+ &splk_eb.common,
+ &mspi_eb.common,
+ &pub0_reg_eb.common,
+ &pin_eb.common,
+ &aon_ckg_eb.common,
+ &gpu_eb.common,
+ &apcpu_ts0_eb.common,
+ &apcpu_ts1_eb.common,
+ &dap_eb.common,
+ &i2c_eb.common,
+ &pmu_eb.common,
+ &thm_eb.common,
+ &aux0_eb.common,
+ &aux1_eb.common,
+ &aux2_eb.common,
+ &probe_eb.common,
+ &gpu0_avs_eb.common,
+ &gpu1_avs_eb.common,
+ &apcpu_wdg_eb.common,
+ &ap_tmr1_eb.common,
+ &ap_tmr2_eb.common,
+ &disp_emc_eb.common,
+ &zip_emc_eb.common,
+ &gsp_emc_eb.common,
+ &osc_aon_eb.common,
+ &lvds_trx_eb.common,
+ &lvds_tcxo_eb.common,
+ &mdar_eb.common,
+ &rtc4m0_cal_eb.common,
+ &rct100m_cal_eb.common,
+ &djtag_eb.common,
+ &mbox_eb.common,
+ &aon_dma_eb.common,
+ &dbg_emc_eb.common,
+ &lvds_pll_div_en.common,
+ &def_eb.common,
+ &aon_apb_rsv0.common,
+ &orp_jtag_eb.common,
+ &vsp_eb.common,
+ &cam_eb.common,
+ &disp_eb.common,
+ &dbg_axi_if_eb.common,
+ &sdio0_2x_en.common,
+ &sdio1_2x_en.common,
+ &sdio2_2x_en.common,
+ &emmc_2x_en.common,
+};
+
+static struct clk_hw_onecell_data sc9860_aon_gate_hws = {
+ .hws = {
+ [CLK_AVS_LIT_EB] = &avs_lit_eb.common.hw,
+ [CLK_AVS_BIG_EB] = &avs_big_eb.common.hw,
+ [CLK_AP_INTC5_EB] = &ap_intc5_eb.common.hw,
+ [CLK_GPIO_EB] = &gpio_eb.common.hw,
+ [CLK_PWM0_EB] = &pwm0_eb.common.hw,
+ [CLK_PWM1_EB] = &pwm1_eb.common.hw,
+ [CLK_PWM2_EB] = &pwm2_eb.common.hw,
+ [CLK_PWM3_EB] = &pwm3_eb.common.hw,
+ [CLK_KPD_EB] = &kpd_eb.common.hw,
+ [CLK_AON_SYS_EB] = &aon_sys_eb.common.hw,
+ [CLK_AP_SYS_EB] = &ap_sys_eb.common.hw,
+ [CLK_AON_TMR_EB] = &aon_tmr_eb.common.hw,
+ [CLK_AP_TMR0_EB] = &ap_tmr0_eb.common.hw,
+ [CLK_EFUSE_EB] = &efuse_eb.common.hw,
+ [CLK_EIC_EB] = &eic_eb.common.hw,
+ [CLK_PUB1_REG_EB] = &pub1_reg_eb.common.hw,
+ [CLK_ADI_EB] = &adi_eb.common.hw,
+ [CLK_AP_INTC0_EB] = &ap_intc0_eb.common.hw,
+ [CLK_AP_INTC1_EB] = &ap_intc1_eb.common.hw,
+ [CLK_AP_INTC2_EB] = &ap_intc2_eb.common.hw,
+ [CLK_AP_INTC3_EB] = &ap_intc3_eb.common.hw,
+ [CLK_AP_INTC4_EB] = &ap_intc4_eb.common.hw,
+ [CLK_SPLK_EB] = &splk_eb.common.hw,
+ [CLK_MSPI_EB] = &mspi_eb.common.hw,
+ [CLK_PUB0_REG_EB] = &pub0_reg_eb.common.hw,
+ [CLK_PIN_EB] = &pin_eb.common.hw,
+ [CLK_AON_CKG_EB] = &aon_ckg_eb.common.hw,
+ [CLK_GPU_EB] = &gpu_eb.common.hw,
+ [CLK_APCPU_TS0_EB] = &apcpu_ts0_eb.common.hw,
+ [CLK_APCPU_TS1_EB] = &apcpu_ts1_eb.common.hw,
+ [CLK_DAP_EB] = &dap_eb.common.hw,
+ [CLK_I2C_EB] = &i2c_eb.common.hw,
+ [CLK_PMU_EB] = &pmu_eb.common.hw,
+ [CLK_THM_EB] = &thm_eb.common.hw,
+ [CLK_AUX0_EB] = &aux0_eb.common.hw,
+ [CLK_AUX1_EB] = &aux1_eb.common.hw,
+ [CLK_AUX2_EB] = &aux2_eb.common.hw,
+ [CLK_PROBE_EB] = &probe_eb.common.hw,
+ [CLK_GPU0_AVS_EB] = &gpu0_avs_eb.common.hw,
+ [CLK_GPU1_AVS_EB] = &gpu1_avs_eb.common.hw,
+ [CLK_APCPU_WDG_EB] = &apcpu_wdg_eb.common.hw,
+ [CLK_AP_TMR1_EB] = &ap_tmr1_eb.common.hw,
+ [CLK_AP_TMR2_EB] = &ap_tmr2_eb.common.hw,
+ [CLK_DISP_EMC_EB] = &disp_emc_eb.common.hw,
+ [CLK_ZIP_EMC_EB] = &zip_emc_eb.common.hw,
+ [CLK_GSP_EMC_EB] = &gsp_emc_eb.common.hw,
+ [CLK_OSC_AON_EB] = &osc_aon_eb.common.hw,
+ [CLK_LVDS_TRX_EB] = &lvds_trx_eb.common.hw,
+ [CLK_LVDS_TCXO_EB] = &lvds_tcxo_eb.common.hw,
+ [CLK_MDAR_EB] = &mdar_eb.common.hw,
+ [CLK_RTC4M0_CAL_EB] = &rtc4m0_cal_eb.common.hw,
+ [CLK_RCT100M_CAL_EB] = &rct100m_cal_eb.common.hw,
+ [CLK_DJTAG_EB] = &djtag_eb.common.hw,
+ [CLK_MBOX_EB] = &mbox_eb.common.hw,
+ [CLK_AON_DMA_EB] = &aon_dma_eb.common.hw,
+ [CLK_DBG_EMC_EB] = &dbg_emc_eb.common.hw,
+ [CLK_LVDS_PLL_DIV_EN] = &lvds_pll_div_en.common.hw,
+ [CLK_DEF_EB] = &def_eb.common.hw,
+ [CLK_AON_APB_RSV0] = &aon_apb_rsv0.common.hw,
+ [CLK_ORP_JTAG_EB] = &orp_jtag_eb.common.hw,
+ [CLK_VSP_EB] = &vsp_eb.common.hw,
+ [CLK_CAM_EB] = &cam_eb.common.hw,
+ [CLK_DISP_EB] = &disp_eb.common.hw,
+ [CLK_DBG_AXI_IF_EB] = &dbg_axi_if_eb.common.hw,
+ [CLK_SDIO0_2X_EN] = &sdio0_2x_en.common.hw,
+ [CLK_SDIO1_2X_EN] = &sdio1_2x_en.common.hw,
+ [CLK_SDIO2_2X_EN] = &sdio2_2x_en.common.hw,
+ [CLK_EMMC_2X_EN] = &emmc_2x_en.common.hw,
+ },
+ .num = CLK_AON_GATE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_aon_gate_desc = {
+ .clk_clks = sc9860_aon_gate,
+ .num_clk_clks = ARRAY_SIZE(sc9860_aon_gate),
+ .hw_clks = &sc9860_aon_gate_hws,
+};
+
+static const u8 mcu_table[] = { 0, 1, 2, 3, 4, 8 };
+static const char * const lit_mcu_parents[] = { "ext-26m", "twpll-512m",
+ "twpll-768m", "ltepll0",
+ "twpll", "mpll0" };
+static SPRD_COMP_CLK_TABLE(lit_mcu, "lit-mcu", lit_mcu_parents, 0x20,
+ mcu_table, 0, 4, 4, 3, 0);
+
+static const char * const big_mcu_parents[] = { "ext-26m", "twpll-512m",
+ "twpll-768m", "ltepll0",
+ "twpll", "mpll1" };
+static SPRD_COMP_CLK_TABLE(big_mcu, "big-mcu", big_mcu_parents, 0x24,
+ mcu_table, 0, 4, 4, 3, 0);
+
+static struct sprd_clk_common *sc9860_aonsecure_clk[] = {
+ /* address base is 0x40880000 */
+ &lit_mcu.common,
+ &big_mcu.common,
+};
+
+static struct clk_hw_onecell_data sc9860_aonsecure_clk_hws = {
+ .hws = {
+ [CLK_LIT_MCU] = &lit_mcu.common.hw,
+ [CLK_BIG_MCU] = &big_mcu.common.hw,
+ },
+ .num = CLK_AONSECURE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_aonsecure_clk_desc = {
+ .clk_clks = sc9860_aonsecure_clk,
+ .num_clk_clks = ARRAY_SIZE(sc9860_aonsecure_clk),
+ .hw_clks = &sc9860_aonsecure_clk_hws,
+};
+
+static SPRD_SC_GATE_CLK(agcp_iis0_eb, "agcp-iis0-eb", "aon-apb",
+ 0x0, 0x100, BIT(0), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_iis1_eb, "agcp-iis1-eb", "aon-apb",
+ 0x0, 0x100, BIT(1), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_iis2_eb, "agcp-iis2-eb", "aon-apb",
+ 0x0, 0x100, BIT(2), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_iis3_eb, "agcp-iis3-eb", "aon-apb",
+ 0x0, 0x100, BIT(3), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_uart_eb, "agcp-uart-eb", "aon-apb",
+ 0x0, 0x100, BIT(4), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_dmacp_eb, "agcp-dmacp-eb", "aon-apb",
+ 0x0, 0x100, BIT(5), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_dmaap_eb, "agcp-dmaap-eb", "aon-apb",
+ 0x0, 0x100, BIT(6), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_arc48k_eb, "agcp-arc48k-eb", "aon-apb",
+ 0x0, 0x100, BIT(10), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_src44p1k_eb, "agcp-src44p1k-eb", "aon-apb",
+ 0x0, 0x100, BIT(11), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_mcdt_eb, "agcp-mcdt-eb", "aon-apb",
+ 0x0, 0x100, BIT(12), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_vbcifd_eb, "agcp-vbcifd-eb", "aon-apb",
+ 0x0, 0x100, BIT(13), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_vbc_eb, "agcp-vbc-eb", "aon-apb",
+ 0x0, 0x100, BIT(14), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_spinlock_eb, "agcp-spinlock-eb", "aon-apb",
+ 0x0, 0x100, BIT(15), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_icu_eb, "agcp-icu-eb", "aon-apb",
+ 0x0, 0x100, BIT(16), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(agcp_ap_ashb_eb, "agcp-ap-ashb-eb", "aon-apb",
+ 0x0, 0x100, BIT(17), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_cp_ashb_eb, "agcp-cp-ashb-eb", "aon-apb",
+ 0x0, 0x100, BIT(18), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_aud_eb, "agcp-aud-eb", "aon-apb",
+ 0x0, 0x100, BIT(19), 0, 0);
+static SPRD_SC_GATE_CLK(agcp_audif_eb, "agcp-audif-eb", "aon-apb",
+ 0x0, 0x100, BIT(20), 0, 0);
+
+static struct sprd_clk_common *sc9860_agcp_gate[] = {
+ /* address base is 0x415e0000 */
+ &agcp_iis0_eb.common,
+ &agcp_iis1_eb.common,
+ &agcp_iis2_eb.common,
+ &agcp_iis3_eb.common,
+ &agcp_uart_eb.common,
+ &agcp_dmacp_eb.common,
+ &agcp_dmaap_eb.common,
+ &agcp_arc48k_eb.common,
+ &agcp_src44p1k_eb.common,
+ &agcp_mcdt_eb.common,
+ &agcp_vbcifd_eb.common,
+ &agcp_vbc_eb.common,
+ &agcp_spinlock_eb.common,
+ &agcp_icu_eb.common,
+ &agcp_ap_ashb_eb.common,
+ &agcp_cp_ashb_eb.common,
+ &agcp_aud_eb.common,
+ &agcp_audif_eb.common,
+};
+
+static struct clk_hw_onecell_data sc9860_agcp_gate_hws = {
+ .hws = {
+ [CLK_AGCP_IIS0_EB] = &agcp_iis0_eb.common.hw,
+ [CLK_AGCP_IIS1_EB] = &agcp_iis1_eb.common.hw,
+ [CLK_AGCP_IIS2_EB] = &agcp_iis2_eb.common.hw,
+ [CLK_AGCP_IIS3_EB] = &agcp_iis3_eb.common.hw,
+ [CLK_AGCP_UART_EB] = &agcp_uart_eb.common.hw,
+ [CLK_AGCP_DMACP_EB] = &agcp_dmacp_eb.common.hw,
+ [CLK_AGCP_DMAAP_EB] = &agcp_dmaap_eb.common.hw,
+ [CLK_AGCP_ARC48K_EB] = &agcp_arc48k_eb.common.hw,
+ [CLK_AGCP_SRC44P1K_EB] = &agcp_src44p1k_eb.common.hw,
+ [CLK_AGCP_MCDT_EB] = &agcp_mcdt_eb.common.hw,
+ [CLK_AGCP_VBCIFD_EB] = &agcp_vbcifd_eb.common.hw,
+ [CLK_AGCP_VBC_EB] = &agcp_vbc_eb.common.hw,
+ [CLK_AGCP_SPINLOCK_EB] = &agcp_spinlock_eb.common.hw,
+ [CLK_AGCP_ICU_EB] = &agcp_icu_eb.common.hw,
+ [CLK_AGCP_AP_ASHB_EB] = &agcp_ap_ashb_eb.common.hw,
+ [CLK_AGCP_CP_ASHB_EB] = &agcp_cp_ashb_eb.common.hw,
+ [CLK_AGCP_AUD_EB] = &agcp_aud_eb.common.hw,
+ [CLK_AGCP_AUDIF_EB] = &agcp_audif_eb.common.hw,
+ },
+ .num = CLK_AGCP_GATE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_agcp_gate_desc = {
+ .clk_clks = sc9860_agcp_gate,
+ .num_clk_clks = ARRAY_SIZE(sc9860_agcp_gate),
+ .hw_clks = &sc9860_agcp_gate_hws,
+};
+
+static const char * const gpu_parents[] = { "twpll-512m",
+ "twpll-768m",
+ "gpll" };
+static SPRD_COMP_CLK(gpu_clk, "gpu", gpu_parents, 0x20,
+ 0, 2, 8, 4, 0);
+
+static struct sprd_clk_common *sc9860_gpu_clk[] = {
+ /* address base is 0x60200000 */
+ &gpu_clk.common,
+};
+
+static struct clk_hw_onecell_data sc9860_gpu_clk_hws = {
+ .hws = {
+ [CLK_GPU] = &gpu_clk.common.hw,
+ },
+ .num = CLK_GPU_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_gpu_clk_desc = {
+ .clk_clks = sc9860_gpu_clk,
+ .num_clk_clks = ARRAY_SIZE(sc9860_gpu_clk),
+ .hw_clks = &sc9860_gpu_clk_hws,
+};
+
+static const char * const ahb_parents[] = { "ext-26m", "twpll-96m",
+ "twpll-128m", "twpll-153m6" };
+static SPRD_MUX_CLK(ahb_vsp, "ahb-vsp", ahb_parents, 0x20,
+ 0, 2, SC9860_MUX_FLAG);
+
+static const char * const vsp_parents[] = { "twpll-76m8", "twpll-128m",
+ "twpll-256m", "twpll-307m2",
+ "twpll-384m" };
+static SPRD_COMP_CLK(vsp_clk, "vsp", vsp_parents, 0x24, 0, 3, 8, 2, 0);
+
+static const char * const dispc_parents[] = { "twpll-76m8", "twpll-128m",
+ "twpll-256m", "twpll-307m2" };
+static SPRD_COMP_CLK(vsp_enc, "vsp-enc", dispc_parents, 0x28, 0, 2, 8, 2, 0);
+
+static const char * const vpp_parents[] = { "twpll-96m", "twpll-153m6",
+ "twpll-192m", "twpll-256m" };
+static SPRD_MUX_CLK(vpp_clk, "vpp", vpp_parents, 0x2c,
+ 0, 2, SC9860_MUX_FLAG);
+static const char * const vsp_26m_parents[] = { "ext-26m" };
+static SPRD_MUX_CLK(vsp_26m, "vsp-26m", vsp_26m_parents, 0x30,
+ 0, 1, SC9860_MUX_FLAG);
+
+static struct sprd_clk_common *sc9860_vsp_clk[] = {
+ /* address base is 0x61000000 */
+ &ahb_vsp.common,
+ &vsp_clk.common,
+ &vsp_enc.common,
+ &vpp_clk.common,
+ &vsp_26m.common,
+};
+
+static struct clk_hw_onecell_data sc9860_vsp_clk_hws = {
+ .hws = {
+ [CLK_AHB_VSP] = &ahb_vsp.common.hw,
+ [CLK_VSP] = &vsp_clk.common.hw,
+ [CLK_VSP_ENC] = &vsp_enc.common.hw,
+ [CLK_VPP] = &vpp_clk.common.hw,
+ [CLK_VSP_26M] = &vsp_26m.common.hw,
+ },
+ .num = CLK_VSP_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_vsp_clk_desc = {
+ .clk_clks = sc9860_vsp_clk,
+ .num_clk_clks = ARRAY_SIZE(sc9860_vsp_clk),
+ .hw_clks = &sc9860_vsp_clk_hws,
+};
+
+static SPRD_SC_GATE_CLK(vsp_dec_eb, "vsp-dec-eb", "ahb-vsp", 0x0,
+ 0x1000, BIT(0), 0, 0);
+static SPRD_SC_GATE_CLK(vsp_ckg_eb, "vsp-ckg-eb", "ahb-vsp", 0x0,
+ 0x1000, BIT(1), 0, 0);
+static SPRD_SC_GATE_CLK(vsp_mmu_eb, "vsp-mmu-eb", "ahb-vsp", 0x0,
+ 0x1000, BIT(2), 0, 0);
+static SPRD_SC_GATE_CLK(vsp_enc_eb, "vsp-enc-eb", "ahb-vsp", 0x0,
+ 0x1000, BIT(3), 0, 0);
+static SPRD_SC_GATE_CLK(vpp_eb, "vpp-eb", "ahb-vsp", 0x0,
+ 0x1000, BIT(4), 0, 0);
+static SPRD_SC_GATE_CLK(vsp_26m_eb, "vsp-26m-eb", "ahb-vsp", 0x0,
+ 0x1000, BIT(5), 0, 0);
+static SPRD_GATE_CLK(vsp_axi_gate, "vsp-axi-gate", "ahb-vsp", 0x8,
+ BIT(0), 0, 0);
+static SPRD_GATE_CLK(vsp_enc_gate, "vsp-enc-gate", "ahb-vsp", 0x8,
+ BIT(1), 0, 0);
+static SPRD_GATE_CLK(vpp_axi_gate, "vpp-axi-gate", "ahb-vsp", 0x8,
+ BIT(2), 0, 0);
+static SPRD_GATE_CLK(vsp_bm_gate, "vsp-bm-gate", "ahb-vsp", 0x8,
+ BIT(8), 0, 0);
+static SPRD_GATE_CLK(vsp_enc_bm_gate, "vsp-enc-bm-gate", "ahb-vsp", 0x8,
+ BIT(9), 0, 0);
+static SPRD_GATE_CLK(vpp_bm_gate, "vpp-bm-gate", "ahb-vsp", 0x8,
+ BIT(10), 0, 0);
+
+static struct sprd_clk_common *sc9860_vsp_gate[] = {
+ /* address base is 0x61100000 */
+ &vsp_dec_eb.common,
+ &vsp_ckg_eb.common,
+ &vsp_mmu_eb.common,
+ &vsp_enc_eb.common,
+ &vpp_eb.common,
+ &vsp_26m_eb.common,
+ &vsp_axi_gate.common,
+ &vsp_enc_gate.common,
+ &vpp_axi_gate.common,
+ &vsp_bm_gate.common,
+ &vsp_enc_bm_gate.common,
+ &vpp_bm_gate.common,
+};
+
+static struct clk_hw_onecell_data sc9860_vsp_gate_hws = {
+ .hws = {
+ [CLK_VSP_DEC_EB] = &vsp_dec_eb.common.hw,
+ [CLK_VSP_CKG_EB] = &vsp_ckg_eb.common.hw,
+ [CLK_VSP_MMU_EB] = &vsp_mmu_eb.common.hw,
+ [CLK_VSP_ENC_EB] = &vsp_enc_eb.common.hw,
+ [CLK_VPP_EB] = &vpp_eb.common.hw,
+ [CLK_VSP_26M_EB] = &vsp_26m_eb.common.hw,
+ [CLK_VSP_AXI_GATE] = &vsp_axi_gate.common.hw,
+ [CLK_VSP_ENC_GATE] = &vsp_enc_gate.common.hw,
+ [CLK_VPP_AXI_GATE] = &vpp_axi_gate.common.hw,
+ [CLK_VSP_BM_GATE] = &vsp_bm_gate.common.hw,
+ [CLK_VSP_ENC_BM_GATE] = &vsp_enc_bm_gate.common.hw,
+ [CLK_VPP_BM_GATE] = &vpp_bm_gate.common.hw,
+ },
+ .num = CLK_VSP_GATE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_vsp_gate_desc = {
+ .clk_clks = sc9860_vsp_gate,
+ .num_clk_clks = ARRAY_SIZE(sc9860_vsp_gate),
+ .hw_clks = &sc9860_vsp_gate_hws,
+};
+
+static SPRD_MUX_CLK(ahb_cam, "ahb-cam", ahb_parents, 0x20,
+ 0, 2, SC9860_MUX_FLAG);
+static const char * const sensor_parents[] = { "ext-26m", "twpll-48m",
+ "twpll-76m8", "twpll-96m" };
+static SPRD_COMP_CLK(sensor0_clk, "sensor0", sensor_parents, 0x24,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(sensor1_clk, "sensor1", sensor_parents, 0x28,
+ 0, 2, 8, 3, 0);
+static SPRD_COMP_CLK(sensor2_clk, "sensor2", sensor_parents, 0x2c,
+ 0, 2, 8, 3, 0);
+static SPRD_GATE_CLK(mipi_csi0_eb, "mipi-csi0-eb", "ahb-cam", 0x4c,
+ BIT(16), 0, 0);
+static SPRD_GATE_CLK(mipi_csi1_eb, "mipi-csi1-eb", "ahb-cam", 0x50,
+ BIT(16), 0, 0);
+
+static struct sprd_clk_common *sc9860_cam_clk[] = {
+ /* address base is 0x62000000 */
+ &ahb_cam.common,
+ &sensor0_clk.common,
+ &sensor1_clk.common,
+ &sensor2_clk.common,
+ &mipi_csi0_eb.common,
+ &mipi_csi1_eb.common,
+};
+
+static struct clk_hw_onecell_data sc9860_cam_clk_hws = {
+ .hws = {
+ [CLK_AHB_CAM] = &ahb_cam.common.hw,
+ [CLK_SENSOR0] = &sensor0_clk.common.hw,
+ [CLK_SENSOR1] = &sensor1_clk.common.hw,
+ [CLK_SENSOR2] = &sensor2_clk.common.hw,
+ [CLK_MIPI_CSI0_EB] = &mipi_csi0_eb.common.hw,
+ [CLK_MIPI_CSI1_EB] = &mipi_csi1_eb.common.hw,
+ },
+ .num = CLK_CAM_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_cam_clk_desc = {
+ .clk_clks = sc9860_cam_clk,
+ .num_clk_clks = ARRAY_SIZE(sc9860_cam_clk),
+ .hw_clks = &sc9860_cam_clk_hws,
+};
+
+static SPRD_SC_GATE_CLK(dcam0_eb, "dcam0-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(0), 0, 0);
+static SPRD_SC_GATE_CLK(dcam1_eb, "dcam1-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(1), 0, 0);
+static SPRD_SC_GATE_CLK(isp0_eb, "isp0-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(2), 0, 0);
+static SPRD_SC_GATE_CLK(csi0_eb, "csi0-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(3), 0, 0);
+static SPRD_SC_GATE_CLK(csi1_eb, "csi1-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(4), 0, 0);
+static SPRD_SC_GATE_CLK(jpg0_eb, "jpg0-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(5), 0, 0);
+static SPRD_SC_GATE_CLK(jpg1_eb, "jpg1-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(6), 0, 0);
+static SPRD_SC_GATE_CLK(cam_ckg_eb, "cam-ckg-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(7), 0, 0);
+static SPRD_SC_GATE_CLK(cam_mmu_eb, "cam-mmu-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(8), 0, 0);
+static SPRD_SC_GATE_CLK(isp1_eb, "isp1-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(9), 0, 0);
+static SPRD_SC_GATE_CLK(cpp_eb, "cpp-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(10), 0, 0);
+static SPRD_SC_GATE_CLK(mmu_pf_eb, "mmu-pf-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(11), 0, 0);
+static SPRD_SC_GATE_CLK(isp2_eb, "isp2-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(12), 0, 0);
+static SPRD_SC_GATE_CLK(dcam2isp_if_eb, "dcam2isp-if-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(13), 0, 0);
+static SPRD_SC_GATE_CLK(isp2dcam_if_eb, "isp2dcam-if-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(14), 0, 0);
+static SPRD_SC_GATE_CLK(isp_lclk_eb, "isp-lclk-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(15), 0, 0);
+static SPRD_SC_GATE_CLK(isp_iclk_eb, "isp-iclk-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(16), 0, 0);
+static SPRD_SC_GATE_CLK(isp_mclk_eb, "isp-mclk-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(17), 0, 0);
+static SPRD_SC_GATE_CLK(isp_pclk_eb, "isp-pclk-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(18), 0, 0);
+static SPRD_SC_GATE_CLK(isp_isp2dcam_eb, "isp-isp2dcam-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(19), 0, 0);
+static SPRD_SC_GATE_CLK(dcam0_if_eb, "dcam0-if-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(20), 0, 0);
+static SPRD_SC_GATE_CLK(clk26m_if_eb, "clk26m-if-eb", "ahb-cam", 0x0,
+ 0x1000, BIT(21), 0, 0);
+static SPRD_GATE_CLK(cphy0_gate, "cphy0-gate", "ahb-cam", 0x8,
+ BIT(0), 0, 0);
+static SPRD_GATE_CLK(mipi_csi0_gate, "mipi-csi0-gate", "ahb-cam", 0x8,
+ BIT(1), 0, 0);
+static SPRD_GATE_CLK(cphy1_gate, "cphy1-gate", "ahb-cam", 0x8,
+ BIT(2), 0, 0);
+static SPRD_GATE_CLK(mipi_csi1, "mipi-csi1", "ahb-cam", 0x8,
+ BIT(3), 0, 0);
+static SPRD_GATE_CLK(dcam0_axi_gate, "dcam0-axi-gate", "ahb-cam", 0x8,
+ BIT(4), 0, 0);
+static SPRD_GATE_CLK(dcam1_axi_gate, "dcam1-axi-gate", "ahb-cam", 0x8,
+ BIT(5), 0, 0);
+static SPRD_GATE_CLK(sensor0_gate, "sensor0-gate", "ahb-cam", 0x8,
+ BIT(6), 0, 0);
+static SPRD_GATE_CLK(sensor1_gate, "sensor1-gate", "ahb-cam", 0x8,
+ BIT(7), 0, 0);
+static SPRD_GATE_CLK(jpg0_axi_gate, "jpg0-axi-gate", "ahb-cam", 0x8,
+ BIT(8), 0, 0);
+static SPRD_GATE_CLK(gpg1_axi_gate, "gpg1-axi-gate", "ahb-cam", 0x8,
+ BIT(9), 0, 0);
+static SPRD_GATE_CLK(isp0_axi_gate, "isp0-axi-gate", "ahb-cam", 0x8,
+ BIT(10), 0, 0);
+static SPRD_GATE_CLK(isp1_axi_gate, "isp1-axi-gate", "ahb-cam", 0x8,
+ BIT(11), 0, 0);
+static SPRD_GATE_CLK(isp2_axi_gate, "isp2-axi-gate", "ahb-cam", 0x8,
+ BIT(12), 0, 0);
+static SPRD_GATE_CLK(cpp_axi_gate, "cpp-axi-gate", "ahb-cam", 0x8,
+ BIT(13), 0, 0);
+static SPRD_GATE_CLK(d0_if_axi_gate, "d0-if-axi-gate", "ahb-cam", 0x8,
+ BIT(14), 0, 0);
+static SPRD_GATE_CLK(d2i_if_axi_gate, "d2i-if-axi-gate", "ahb-cam", 0x8,
+ BIT(15), 0, 0);
+static SPRD_GATE_CLK(i2d_if_axi_gate, "i2d-if-axi-gate", "ahb-cam", 0x8,
+ BIT(16), 0, 0);
+static SPRD_GATE_CLK(spare_axi_gate, "spare-axi-gate", "ahb-cam", 0x8,
+ BIT(17), 0, 0);
+static SPRD_GATE_CLK(sensor2_gate, "sensor2-gate", "ahb-cam", 0x8,
+ BIT(18), 0, 0);
+static SPRD_SC_GATE_CLK(d0if_in_d_en, "d0if-in-d-en", "ahb-cam", 0x28,
+ 0x1000, BIT(0), 0, 0);
+static SPRD_SC_GATE_CLK(d1if_in_d_en, "d1if-in-d-en", "ahb-cam", 0x28,
+ 0x1000, BIT(1), 0, 0);
+static SPRD_SC_GATE_CLK(d0if_in_d2i_en, "d0if-in-d2i-en", "ahb-cam", 0x28,
+ 0x1000, BIT(2), 0, 0);
+static SPRD_SC_GATE_CLK(d1if_in_d2i_en, "d1if-in-d2i-en", "ahb-cam", 0x28,
+ 0x1000, BIT(3), 0, 0);
+static SPRD_SC_GATE_CLK(ia_in_d2i_en, "ia-in-d2i-en", "ahb-cam", 0x28,
+ 0x1000, BIT(4), 0, 0);
+static SPRD_SC_GATE_CLK(ib_in_d2i_en, "ib-in-d2i-en", "ahb-cam", 0x28,
+ 0x1000, BIT(5), 0, 0);
+static SPRD_SC_GATE_CLK(ic_in_d2i_en, "ic-in-d2i-en", "ahb-cam", 0x28,
+ 0x1000, BIT(6), 0, 0);
+static SPRD_SC_GATE_CLK(ia_in_i_en, "ia-in-i-en", "ahb-cam", 0x28,
+ 0x1000, BIT(7), 0, 0);
+static SPRD_SC_GATE_CLK(ib_in_i_en, "ib-in-i-en", "ahb-cam", 0x28,
+ 0x1000, BIT(8), 0, 0);
+static SPRD_SC_GATE_CLK(ic_in_i_en, "ic-in-i-en", "ahb-cam", 0x28,
+ 0x1000, BIT(9), 0, 0);
+
+static struct sprd_clk_common *sc9860_cam_gate[] = {
+ /* address base is 0x62100000 */
+ &dcam0_eb.common,
+ &dcam1_eb.common,
+ &isp0_eb.common,
+ &csi0_eb.common,
+ &csi1_eb.common,
+ &jpg0_eb.common,
+ &jpg1_eb.common,
+ &cam_ckg_eb.common,
+ &cam_mmu_eb.common,
+ &isp1_eb.common,
+ &cpp_eb.common,
+ &mmu_pf_eb.common,
+ &isp2_eb.common,
+ &dcam2isp_if_eb.common,
+ &isp2dcam_if_eb.common,
+ &isp_lclk_eb.common,
+ &isp_iclk_eb.common,
+ &isp_mclk_eb.common,
+ &isp_pclk_eb.common,
+ &isp_isp2dcam_eb.common,
+ &dcam0_if_eb.common,
+ &clk26m_if_eb.common,
+ &cphy0_gate.common,
+ &mipi_csi0_gate.common,
+ &cphy1_gate.common,
+ &mipi_csi1.common,
+ &dcam0_axi_gate.common,
+ &dcam1_axi_gate.common,
+ &sensor0_gate.common,
+ &sensor1_gate.common,
+ &jpg0_axi_gate.common,
+ &gpg1_axi_gate.common,
+ &isp0_axi_gate.common,
+ &isp1_axi_gate.common,
+ &isp2_axi_gate.common,
+ &cpp_axi_gate.common,
+ &d0_if_axi_gate.common,
+ &d2i_if_axi_gate.common,
+ &i2d_if_axi_gate.common,
+ &spare_axi_gate.common,
+ &sensor2_gate.common,
+ &d0if_in_d_en.common,
+ &d1if_in_d_en.common,
+ &d0if_in_d2i_en.common,
+ &d1if_in_d2i_en.common,
+ &ia_in_d2i_en.common,
+ &ib_in_d2i_en.common,
+ &ic_in_d2i_en.common,
+ &ia_in_i_en.common,
+ &ib_in_i_en.common,
+ &ic_in_i_en.common,
+};
+
+static struct clk_hw_onecell_data sc9860_cam_gate_hws = {
+ .hws = {
+ [CLK_DCAM0_EB] = &dcam0_eb.common.hw,
+ [CLK_DCAM1_EB] = &dcam1_eb.common.hw,
+ [CLK_ISP0_EB] = &isp0_eb.common.hw,
+ [CLK_CSI0_EB] = &csi0_eb.common.hw,
+ [CLK_CSI1_EB] = &csi1_eb.common.hw,
+ [CLK_JPG0_EB] = &jpg0_eb.common.hw,
+ [CLK_JPG1_EB] = &jpg1_eb.common.hw,
+ [CLK_CAM_CKG_EB] = &cam_ckg_eb.common.hw,
+ [CLK_CAM_MMU_EB] = &cam_mmu_eb.common.hw,
+ [CLK_ISP1_EB] = &isp1_eb.common.hw,
+ [CLK_CPP_EB] = &cpp_eb.common.hw,
+ [CLK_MMU_PF_EB] = &mmu_pf_eb.common.hw,
+ [CLK_ISP2_EB] = &isp2_eb.common.hw,
+ [CLK_DCAM2ISP_IF_EB] = &dcam2isp_if_eb.common.hw,
+ [CLK_ISP2DCAM_IF_EB] = &isp2dcam_if_eb.common.hw,
+ [CLK_ISP_LCLK_EB] = &isp_lclk_eb.common.hw,
+ [CLK_ISP_ICLK_EB] = &isp_iclk_eb.common.hw,
+ [CLK_ISP_MCLK_EB] = &isp_mclk_eb.common.hw,
+ [CLK_ISP_PCLK_EB] = &isp_pclk_eb.common.hw,
+ [CLK_ISP_ISP2DCAM_EB] = &isp_isp2dcam_eb.common.hw,
+ [CLK_DCAM0_IF_EB] = &dcam0_if_eb.common.hw,
+ [CLK_CLK26M_IF_EB] = &clk26m_if_eb.common.hw,
+ [CLK_CPHY0_GATE] = &cphy0_gate.common.hw,
+ [CLK_MIPI_CSI0_GATE] = &mipi_csi0_gate.common.hw,
+ [CLK_CPHY1_GATE] = &cphy1_gate.common.hw,
+ [CLK_MIPI_CSI1] = &mipi_csi1.common.hw,
+ [CLK_DCAM0_AXI_GATE] = &dcam0_axi_gate.common.hw,
+ [CLK_DCAM1_AXI_GATE] = &dcam1_axi_gate.common.hw,
+ [CLK_SENSOR0_GATE] = &sensor0_gate.common.hw,
+ [CLK_SENSOR1_GATE] = &sensor1_gate.common.hw,
+ [CLK_JPG0_AXI_GATE] = &jpg0_axi_gate.common.hw,
+ [CLK_GPG1_AXI_GATE] = &gpg1_axi_gate.common.hw,
+ [CLK_ISP0_AXI_GATE] = &isp0_axi_gate.common.hw,
+ [CLK_ISP1_AXI_GATE] = &isp1_axi_gate.common.hw,
+ [CLK_ISP2_AXI_GATE] = &isp2_axi_gate.common.hw,
+ [CLK_CPP_AXI_GATE] = &cpp_axi_gate.common.hw,
+ [CLK_D0_IF_AXI_GATE] = &d0_if_axi_gate.common.hw,
+ [CLK_D2I_IF_AXI_GATE] = &d2i_if_axi_gate.common.hw,
+ [CLK_I2D_IF_AXI_GATE] = &i2d_if_axi_gate.common.hw,
+ [CLK_SPARE_AXI_GATE] = &spare_axi_gate.common.hw,
+ [CLK_SENSOR2_GATE] = &sensor2_gate.common.hw,
+ [CLK_D0IF_IN_D_EN] = &d0if_in_d_en.common.hw,
+ [CLK_D1IF_IN_D_EN] = &d1if_in_d_en.common.hw,
+ [CLK_D0IF_IN_D2I_EN] = &d0if_in_d2i_en.common.hw,
+ [CLK_D1IF_IN_D2I_EN] = &d1if_in_d2i_en.common.hw,
+ [CLK_IA_IN_D2I_EN] = &ia_in_d2i_en.common.hw,
+ [CLK_IB_IN_D2I_EN] = &ib_in_d2i_en.common.hw,
+ [CLK_IC_IN_D2I_EN] = &ic_in_d2i_en.common.hw,
+ [CLK_IA_IN_I_EN] = &ia_in_i_en.common.hw,
+ [CLK_IB_IN_I_EN] = &ib_in_i_en.common.hw,
+ [CLK_IC_IN_I_EN] = &ic_in_i_en.common.hw,
+ },
+ .num = CLK_CAM_GATE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_cam_gate_desc = {
+ .clk_clks = sc9860_cam_gate,
+ .num_clk_clks = ARRAY_SIZE(sc9860_cam_gate),
+ .hw_clks = &sc9860_cam_gate_hws,
+};
+
+static SPRD_MUX_CLK(ahb_disp, "ahb-disp", ahb_parents, 0x20,
+ 0, 2, SC9860_MUX_FLAG);
+static SPRD_COMP_CLK(dispc0_dpi, "dispc0-dpi", dispc_parents, 0x34,
+ 0, 2, 8, 2, 0);
+static SPRD_COMP_CLK(dispc1_dpi, "dispc1-dpi", dispc_parents, 0x40,
+ 0, 2, 8, 2, 0);
+
+static struct sprd_clk_common *sc9860_disp_clk[] = {
+ /* address base is 0x63000000 */
+ &ahb_disp.common,
+ &dispc0_dpi.common,
+ &dispc1_dpi.common,
+};
+
+static struct clk_hw_onecell_data sc9860_disp_clk_hws = {
+ .hws = {
+ [CLK_AHB_DISP] = &ahb_disp.common.hw,
+ [CLK_DISPC0_DPI] = &dispc0_dpi.common.hw,
+ [CLK_DISPC1_DPI] = &dispc1_dpi.common.hw,
+ },
+ .num = CLK_DISP_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_disp_clk_desc = {
+ .clk_clks = sc9860_disp_clk,
+ .num_clk_clks = ARRAY_SIZE(sc9860_disp_clk),
+ .hw_clks = &sc9860_disp_clk_hws,
+};
+
+static SPRD_SC_GATE_CLK(dispc0_eb, "dispc0-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(0), 0, 0);
+static SPRD_SC_GATE_CLK(dispc1_eb, "dispc1-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(1), 0, 0);
+static SPRD_SC_GATE_CLK(dispc_mmu_eb, "dispc-mmu-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(2), 0, 0);
+static SPRD_SC_GATE_CLK(gsp0_eb, "gsp0-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(3), 0, 0);
+static SPRD_SC_GATE_CLK(gsp1_eb, "gsp1-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(4), 0, 0);
+static SPRD_SC_GATE_CLK(gsp0_mmu_eb, "gsp0-mmu-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(5), 0, 0);
+static SPRD_SC_GATE_CLK(gsp1_mmu_eb, "gsp1-mmu-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(6), 0, 0);
+static SPRD_SC_GATE_CLK(dsi0_eb, "dsi0-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(7), 0, 0);
+static SPRD_SC_GATE_CLK(dsi1_eb, "dsi1-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(8), 0, 0);
+static SPRD_SC_GATE_CLK(disp_ckg_eb, "disp-ckg-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(9), 0, 0);
+static SPRD_SC_GATE_CLK(disp_gpu_eb, "disp-gpu-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(10), 0, 0);
+static SPRD_SC_GATE_CLK(gpu_mtx_eb, "gpu-mtx-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(13), 0, 0);
+static SPRD_SC_GATE_CLK(gsp_mtx_eb, "gsp-mtx-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(14), 0, 0);
+static SPRD_SC_GATE_CLK(tmc_mtx_eb, "tmc-mtx-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(15), 0, 0);
+static SPRD_SC_GATE_CLK(dispc_mtx_eb, "dispc-mtx-eb", "ahb-disp", 0x0,
+ 0x1000, BIT(16), 0, 0);
+static SPRD_GATE_CLK(dphy0_gate, "dphy0-gate", "ahb-disp", 0x8,
+ BIT(0), 0, 0);
+static SPRD_GATE_CLK(dphy1_gate, "dphy1-gate", "ahb-disp", 0x8,
+ BIT(1), 0, 0);
+static SPRD_GATE_CLK(gsp0_a_gate, "gsp0-a-gate", "ahb-disp", 0x8,
+ BIT(2), 0, 0);
+static SPRD_GATE_CLK(gsp1_a_gate, "gsp1-a-gate", "ahb-disp", 0x8,
+ BIT(3), 0, 0);
+static SPRD_GATE_CLK(gsp0_f_gate, "gsp0-f-gate", "ahb-disp", 0x8,
+ BIT(4), 0, 0);
+static SPRD_GATE_CLK(gsp1_f_gate, "gsp1-f-gate", "ahb-disp", 0x8,
+ BIT(5), 0, 0);
+static SPRD_GATE_CLK(d_mtx_f_gate, "d-mtx-f-gate", "ahb-disp", 0x8,
+ BIT(6), 0, 0);
+static SPRD_GATE_CLK(d_mtx_a_gate, "d-mtx-a-gate", "ahb-disp", 0x8,
+ BIT(7), 0, 0);
+static SPRD_GATE_CLK(d_noc_f_gate, "d-noc-f-gate", "ahb-disp", 0x8,
+ BIT(8), 0, 0);
+static SPRD_GATE_CLK(d_noc_a_gate, "d-noc-a-gate", "ahb-disp", 0x8,
+ BIT(9), 0, 0);
+static SPRD_GATE_CLK(gsp_mtx_f_gate, "gsp-mtx-f-gate", "ahb-disp", 0x8,
+ BIT(10), 0, 0);
+static SPRD_GATE_CLK(gsp_mtx_a_gate, "gsp-mtx-a-gate", "ahb-disp", 0x8,
+ BIT(11), 0, 0);
+static SPRD_GATE_CLK(gsp_noc_f_gate, "gsp-noc-f-gate", "ahb-disp", 0x8,
+ BIT(12), 0, 0);
+static SPRD_GATE_CLK(gsp_noc_a_gate, "gsp-noc-a-gate", "ahb-disp", 0x8,
+ BIT(13), 0, 0);
+static SPRD_GATE_CLK(dispm0idle_gate, "dispm0idle-gate", "ahb-disp", 0x8,
+ BIT(14), 0, 0);
+static SPRD_GATE_CLK(gspm0idle_gate, "gspm0idle-gate", "ahb-disp", 0x8,
+ BIT(15), 0, 0);
+
+static struct sprd_clk_common *sc9860_disp_gate[] = {
+ /* address base is 0x63100000 */
+ &dispc0_eb.common,
+ &dispc1_eb.common,
+ &dispc_mmu_eb.common,
+ &gsp0_eb.common,
+ &gsp1_eb.common,
+ &gsp0_mmu_eb.common,
+ &gsp1_mmu_eb.common,
+ &dsi0_eb.common,
+ &dsi1_eb.common,
+ &disp_ckg_eb.common,
+ &disp_gpu_eb.common,
+ &gpu_mtx_eb.common,
+ &gsp_mtx_eb.common,
+ &tmc_mtx_eb.common,
+ &dispc_mtx_eb.common,
+ &dphy0_gate.common,
+ &dphy1_gate.common,
+ &gsp0_a_gate.common,
+ &gsp1_a_gate.common,
+ &gsp0_f_gate.common,
+ &gsp1_f_gate.common,
+ &d_mtx_f_gate.common,
+ &d_mtx_a_gate.common,
+ &d_noc_f_gate.common,
+ &d_noc_a_gate.common,
+ &gsp_mtx_f_gate.common,
+ &gsp_mtx_a_gate.common,
+ &gsp_noc_f_gate.common,
+ &gsp_noc_a_gate.common,
+ &dispm0idle_gate.common,
+ &gspm0idle_gate.common,
+};
+
+static struct clk_hw_onecell_data sc9860_disp_gate_hws = {
+ .hws = {
+ [CLK_DISPC0_EB] = &dispc0_eb.common.hw,
+ [CLK_DISPC1_EB] = &dispc1_eb.common.hw,
+ [CLK_DISPC_MMU_EB] = &dispc_mmu_eb.common.hw,
+ [CLK_GSP0_EB] = &gsp0_eb.common.hw,
+ [CLK_GSP1_EB] = &gsp1_eb.common.hw,
+ [CLK_GSP0_MMU_EB] = &gsp0_mmu_eb.common.hw,
+ [CLK_GSP1_MMU_EB] = &gsp1_mmu_eb.common.hw,
+ [CLK_DSI0_EB] = &dsi0_eb.common.hw,
+ [CLK_DSI1_EB] = &dsi1_eb.common.hw,
+ [CLK_DISP_CKG_EB] = &disp_ckg_eb.common.hw,
+ [CLK_DISP_GPU_EB] = &disp_gpu_eb.common.hw,
+ [CLK_GPU_MTX_EB] = &gpu_mtx_eb.common.hw,
+ [CLK_GSP_MTX_EB] = &gsp_mtx_eb.common.hw,
+ [CLK_TMC_MTX_EB] = &tmc_mtx_eb.common.hw,
+ [CLK_DISPC_MTX_EB] = &dispc_mtx_eb.common.hw,
+ [CLK_DPHY0_GATE] = &dphy0_gate.common.hw,
+ [CLK_DPHY1_GATE] = &dphy1_gate.common.hw,
+ [CLK_GSP0_A_GATE] = &gsp0_a_gate.common.hw,
+ [CLK_GSP1_A_GATE] = &gsp1_a_gate.common.hw,
+ [CLK_GSP0_F_GATE] = &gsp0_f_gate.common.hw,
+ [CLK_GSP1_F_GATE] = &gsp1_f_gate.common.hw,
+ [CLK_D_MTX_F_GATE] = &d_mtx_f_gate.common.hw,
+ [CLK_D_MTX_A_GATE] = &d_mtx_a_gate.common.hw,
+ [CLK_D_NOC_F_GATE] = &d_noc_f_gate.common.hw,
+ [CLK_D_NOC_A_GATE] = &d_noc_a_gate.common.hw,
+ [CLK_GSP_MTX_F_GATE] = &gsp_mtx_f_gate.common.hw,
+ [CLK_GSP_MTX_A_GATE] = &gsp_mtx_a_gate.common.hw,
+ [CLK_GSP_NOC_F_GATE] = &gsp_noc_f_gate.common.hw,
+ [CLK_GSP_NOC_A_GATE] = &gsp_noc_a_gate.common.hw,
+ [CLK_DISPM0IDLE_GATE] = &dispm0idle_gate.common.hw,
+ [CLK_GSPM0IDLE_GATE] = &gspm0idle_gate.common.hw,
+ },
+ .num = CLK_DISP_GATE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_disp_gate_desc = {
+ .clk_clks = sc9860_disp_gate,
+ .num_clk_clks = ARRAY_SIZE(sc9860_disp_gate),
+ .hw_clks = &sc9860_disp_gate_hws,
+};
+
+static SPRD_SC_GATE_CLK(sim0_eb, "sim0-eb", "ap-apb", 0x0,
+ 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(iis0_eb, "iis0-eb", "ap-apb", 0x0,
+ 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(iis1_eb, "iis1-eb", "ap-apb", 0x0,
+ 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(iis2_eb, "iis2-eb", "ap-apb", 0x0,
+ 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(iis3_eb, "iis3-eb", "ap-apb", 0x0,
+ 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(spi0_eb, "spi0-eb", "ap-apb", 0x0,
+ 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(spi1_eb, "spi1-eb", "ap-apb", 0x0,
+ 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(spi2_eb, "spi2-eb", "ap-apb", 0x0,
+ 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(i2c0_eb, "i2c0-eb", "ap-apb", 0x0,
+ 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(i2c1_eb, "i2c1-eb", "ap-apb", 0x0,
+ 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(i2c2_eb, "i2c2-eb", "ap-apb", 0x0,
+ 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(i2c3_eb, "i2c3-eb", "ap-apb", 0x0,
+ 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(i2c4_eb, "i2c4-eb", "ap-apb", 0x0,
+ 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(i2c5_eb, "i2c5-eb", "ap-apb", 0x0,
+ 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(uart0_eb, "uart0-eb", "ap-apb", 0x0,
+ 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(uart1_eb, "uart1-eb", "ap-apb", 0x0,
+ 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(uart2_eb, "uart2-eb", "ap-apb", 0x0,
+ 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(uart3_eb, "uart3-eb", "ap-apb", 0x0,
+ 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(uart4_eb, "uart4-eb", "ap-apb", 0x0,
+ 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ap_ckg_eb, "ap-ckg-eb", "ap-apb", 0x0,
+ 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(spi3_eb, "spi3-eb", "ap-apb", 0x0,
+ 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
+
+static struct sprd_clk_common *sc9860_apapb_gate[] = {
+ /* address base is 0x70b00000 */
+ &sim0_eb.common,
+ &iis0_eb.common,
+ &iis1_eb.common,
+ &iis2_eb.common,
+ &iis3_eb.common,
+ &spi0_eb.common,
+ &spi1_eb.common,
+ &spi2_eb.common,
+ &i2c0_eb.common,
+ &i2c1_eb.common,
+ &i2c2_eb.common,
+ &i2c3_eb.common,
+ &i2c4_eb.common,
+ &i2c5_eb.common,
+ &uart0_eb.common,
+ &uart1_eb.common,
+ &uart2_eb.common,
+ &uart3_eb.common,
+ &uart4_eb.common,
+ &ap_ckg_eb.common,
+ &spi3_eb.common,
+};
+
+static struct clk_hw_onecell_data sc9860_apapb_gate_hws = {
+ .hws = {
+ [CLK_SIM0_EB] = &sim0_eb.common.hw,
+ [CLK_IIS0_EB] = &iis0_eb.common.hw,
+ [CLK_IIS1_EB] = &iis1_eb.common.hw,
+ [CLK_IIS2_EB] = &iis2_eb.common.hw,
+ [CLK_IIS3_EB] = &iis3_eb.common.hw,
+ [CLK_SPI0_EB] = &spi0_eb.common.hw,
+ [CLK_SPI1_EB] = &spi1_eb.common.hw,
+ [CLK_SPI2_EB] = &spi2_eb.common.hw,
+ [CLK_I2C0_EB] = &i2c0_eb.common.hw,
+ [CLK_I2C1_EB] = &i2c1_eb.common.hw,
+ [CLK_I2C2_EB] = &i2c2_eb.common.hw,
+ [CLK_I2C3_EB] = &i2c3_eb.common.hw,
+ [CLK_I2C4_EB] = &i2c4_eb.common.hw,
+ [CLK_I2C5_EB] = &i2c5_eb.common.hw,
+ [CLK_UART0_EB] = &uart0_eb.common.hw,
+ [CLK_UART1_EB] = &uart1_eb.common.hw,
+ [CLK_UART2_EB] = &uart2_eb.common.hw,
+ [CLK_UART3_EB] = &uart3_eb.common.hw,
+ [CLK_UART4_EB] = &uart4_eb.common.hw,
+ [CLK_AP_CKG_EB] = &ap_ckg_eb.common.hw,
+ [CLK_SPI3_EB] = &spi3_eb.common.hw,
+ },
+ .num = CLK_APAPB_GATE_NUM,
+};
+
+static const struct sprd_clk_desc sc9860_apapb_gate_desc = {
+ .clk_clks = sc9860_apapb_gate,
+ .num_clk_clks = ARRAY_SIZE(sc9860_apapb_gate),
+ .hw_clks = &sc9860_apapb_gate_hws,
+};
+
+static const struct of_device_id sprd_sc9860_clk_ids[] = {
+ { .compatible = "sprd,sc9860-pmu-gate", /* 0x402b */
+ .data = &sc9860_pmu_gate_desc },
+ { .compatible = "sprd,sc9860-pll", /* 0x4040 */
+ .data = &sc9860_pll_desc },
+ { .compatible = "sprd,sc9860-ap-clk", /* 0x2000 */
+ .data = &sc9860_ap_clk_desc },
+ { .compatible = "sprd,sc9860-aon-prediv", /* 0x402d */
+ .data = &sc9860_aon_prediv_desc },
+ { .compatible = "sprd,sc9860-apahb-gate", /* 0x2021 */
+ .data = &sc9860_apahb_gate_desc },
+ { .compatible = "sprd,sc9860-aon-gate", /* 0x402e */
+ .data = &sc9860_aon_gate_desc },
+ { .compatible = "sprd,sc9860-aonsecure-clk", /* 0x4088 */
+ .data = &sc9860_aonsecure_clk_desc },
+ { .compatible = "sprd,sc9860-agcp-gate", /* 0x415e */
+ .data = &sc9860_agcp_gate_desc },
+ { .compatible = "sprd,sc9860-gpu-clk", /* 0x6020 */
+ .data = &sc9860_gpu_clk_desc },
+ { .compatible = "sprd,sc9860-vsp-clk", /* 0x6100 */
+ .data = &sc9860_vsp_clk_desc },
+ { .compatible = "sprd,sc9860-vsp-gate", /* 0x6110 */
+ .data = &sc9860_vsp_gate_desc },
+ { .compatible = "sprd,sc9860-cam-clk", /* 0x6200 */
+ .data = &sc9860_cam_clk_desc },
+ { .compatible = "sprd,sc9860-cam-gate", /* 0x6210 */
+ .data = &sc9860_cam_gate_desc },
+ { .compatible = "sprd,sc9860-disp-clk", /* 0x6300 */
+ .data = &sc9860_disp_clk_desc },
+ { .compatible = "sprd,sc9860-disp-gate", /* 0x6310 */
+ .data = &sc9860_disp_gate_desc },
+ { .compatible = "sprd,sc9860-apapb-gate", /* 0x70b0 */
+ .data = &sc9860_apapb_gate_desc },
+ { }
+};
+MODULE_DEVICE_TABLE(of, sprd_sc9860_clk_ids);
+
+static int sc9860_clk_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *match;
+ const struct sprd_clk_desc *desc;
+
+ match = of_match_node(sprd_sc9860_clk_ids, pdev->dev.of_node);
+ if (!match) {
+ pr_err("%s: of_match_node() failed.", __func__);
+ return -ENODEV;
+ }
+
+ desc = match->data;
+ sprd_clk_regmap_init(pdev, desc);
+
+ return sprd_clk_probe(&pdev->dev, desc->hw_clks);
+}
+
+static struct platform_driver sc9860_clk_driver = {
+ .probe = sc9860_clk_probe,
+ .driver = {
+ .name = "sc9860-clk",
+ .of_match_table = sprd_sc9860_clk_ids,
+ },
+};
+module_platform_driver(sc9860_clk_driver);
+
+MODULE_DESCRIPTION("Spreadtrum SC9860 Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:sc9860-clk");
--
2.7.4
^ permalink raw reply related
* [PATCH V6 09/12] clk: sprd: Add dt-bindings include file for SC9860
From: Chunyan Zhang @ 2017-11-27 10:01 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, Rob Herring, Mark Rutland
Cc: Catalin Marinas, Will Deacon, linux-clk, linux-kernel, devicetree,
linux-arm-kernel, Arnd Bergmann, Mark Brown, Xiaolong Zhang,
Ben Li, Orson Zhai, Chunyan Zhang
In-Reply-To: <20171127100115.20655-1-chunyan.zhang@spreadtrum.com>
This file defines all SC9860 clock indexes, it should be included in the
device tree in which there's device using the clocks.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Acked-by: Rob Herring <robh@kernel.org>
---
include/dt-bindings/clock/sprd,sc9860-clk.h | 408 ++++++++++++++++++++++++++++
1 file changed, 408 insertions(+)
create mode 100644 include/dt-bindings/clock/sprd,sc9860-clk.h
diff --git a/include/dt-bindings/clock/sprd,sc9860-clk.h b/include/dt-bindings/clock/sprd,sc9860-clk.h
new file mode 100644
index 0000000..48e6052
--- /dev/null
+++ b/include/dt-bindings/clock/sprd,sc9860-clk.h
@@ -0,0 +1,408 @@
+/*
+ * Spreadtrum SC9860 platform clocks
+ *
+ * Copyright (C) 2017, Spreadtrum Communications Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_CLK_SC9860_H_
+#define _DT_BINDINGS_CLK_SC9860_H_
+
+#define CLK_EXT_RCO_100M 0
+#define CLK_EXT_32K 1
+#define CLK_FAC_4M 2
+#define CLK_FAC_2M 3
+#define CLK_FAC_1M 4
+#define CLK_FAC_250K 5
+#define CLK_FAC_RPLL0_26M 6
+#define CLK_FAC_RPLL1_26M 7
+#define CLK_FAC_RCO25M 8
+#define CLK_FAC_RCO4M 9
+#define CLK_FAC_RCO2M 10
+#define CLK_FAC_3K2 11
+#define CLK_FAC_1K 12
+#define CLK_MPLL0_GATE 13
+#define CLK_MPLL1_GATE 14
+#define CLK_DPLL0_GATE 15
+#define CLK_DPLL1_GATE 16
+#define CLK_LTEPLL0_GATE 17
+#define CLK_TWPLL_GATE 18
+#define CLK_LTEPLL1_GATE 19
+#define CLK_RPLL0_GATE 20
+#define CLK_RPLL1_GATE 21
+#define CLK_CPPLL_GATE 22
+#define CLK_GPLL_GATE 23
+#define CLK_PMU_GATE_NUM (CLK_GPLL_GATE + 1)
+
+#define CLK_MPLL0 0
+#define CLK_MPLL1 1
+#define CLK_DPLL0 2
+#define CLK_DPLL1 3
+#define CLK_RPLL0 4
+#define CLK_RPLL1 5
+#define CLK_TWPLL 6
+#define CLK_LTEPLL0 7
+#define CLK_LTEPLL1 8
+#define CLK_GPLL 9
+#define CLK_CPPLL 10
+#define CLK_GPLL_42M5 11
+#define CLK_TWPLL_768M 12
+#define CLK_TWPLL_384M 13
+#define CLK_TWPLL_192M 14
+#define CLK_TWPLL_96M 15
+#define CLK_TWPLL_48M 16
+#define CLK_TWPLL_24M 17
+#define CLK_TWPLL_12M 18
+#define CLK_TWPLL_512M 19
+#define CLK_TWPLL_256M 20
+#define CLK_TWPLL_128M 21
+#define CLK_TWPLL_64M 22
+#define CLK_TWPLL_307M2 23
+#define CLK_TWPLL_153M6 24
+#define CLK_TWPLL_76M8 25
+#define CLK_TWPLL_51M2 26
+#define CLK_TWPLL_38M4 27
+#define CLK_TWPLL_19M2 28
+#define CLK_L0_614M4 29
+#define CLK_L0_409M6 30
+#define CLK_L0_38M 31
+#define CLK_L1_38M 32
+#define CLK_RPLL0_192M 33
+#define CLK_RPLL0_96M 34
+#define CLK_RPLL0_48M 35
+#define CLK_RPLL1_468M 36
+#define CLK_RPLL1_192M 37
+#define CLK_RPLL1_96M 38
+#define CLK_RPLL1_64M 39
+#define CLK_RPLL1_48M 40
+#define CLK_DPLL0_50M 41
+#define CLK_DPLL1_50M 42
+#define CLK_CPPLL_50M 43
+#define CLK_M0_39M 44
+#define CLK_M1_63M 45
+#define CLK_PLL_NUM (CLK_M1_63M + 1)
+
+
+#define CLK_AP_APB 0
+#define CLK_AP_USB3 1
+#define CLK_UART0 2
+#define CLK_UART1 3
+#define CLK_UART2 4
+#define CLK_UART3 5
+#define CLK_UART4 6
+#define CLK_I2C0 7
+#define CLK_I2C1 8
+#define CLK_I2C2 9
+#define CLK_I2C3 10
+#define CLK_I2C4 11
+#define CLK_I2C5 12
+#define CLK_SPI0 13
+#define CLK_SPI1 14
+#define CLK_SPI2 15
+#define CLK_SPI3 16
+#define CLK_IIS0 17
+#define CLK_IIS1 18
+#define CLK_IIS2 19
+#define CLK_IIS3 20
+#define CLK_AP_CLK_NUM (CLK_IIS3 + 1)
+
+#define CLK_AON_APB 0
+#define CLK_AUX0 1
+#define CLK_AUX1 2
+#define CLK_AUX2 3
+#define CLK_PROBE 4
+#define CLK_SP_AHB 5
+#define CLK_CCI 6
+#define CLK_GIC 7
+#define CLK_CSSYS 8
+#define CLK_SDIO0_2X 9
+#define CLK_SDIO1_2X 10
+#define CLK_SDIO2_2X 11
+#define CLK_EMMC_2X 12
+#define CLK_SDIO0_1X 13
+#define CLK_SDIO1_1X 14
+#define CLK_SDIO2_1X 15
+#define CLK_EMMC_1X 16
+#define CLK_ADI 17
+#define CLK_PWM0 18
+#define CLK_PWM1 19
+#define CLK_PWM2 20
+#define CLK_PWM3 21
+#define CLK_EFUSE 22
+#define CLK_CM3_UART0 23
+#define CLK_CM3_UART1 24
+#define CLK_THM 25
+#define CLK_CM3_I2C0 26
+#define CLK_CM3_I2C1 27
+#define CLK_CM4_SPI 28
+#define CLK_AON_I2C 29
+#define CLK_AVS 30
+#define CLK_CA53_DAP 31
+#define CLK_CA53_TS 32
+#define CLK_DJTAG_TCK 33
+#define CLK_PMU 34
+#define CLK_PMU_26M 35
+#define CLK_DEBOUNCE 36
+#define CLK_OTG2_REF 37
+#define CLK_USB3_REF 38
+#define CLK_AP_AXI 39
+#define CLK_AON_PREDIV_NUM (CLK_AP_AXI + 1)
+
+#define CLK_USB3_EB 0
+#define CLK_USB3_SUSPEND_EB 1
+#define CLK_USB3_REF_EB 2
+#define CLK_DMA_EB 3
+#define CLK_SDIO0_EB 4
+#define CLK_SDIO1_EB 5
+#define CLK_SDIO2_EB 6
+#define CLK_EMMC_EB 7
+#define CLK_ROM_EB 8
+#define CLK_BUSMON_EB 9
+#define CLK_CC63S_EB 10
+#define CLK_CC63P_EB 11
+#define CLK_CE0_EB 12
+#define CLK_CE1_EB 13
+#define CLK_APAHB_GATE_NUM (CLK_CE1_EB + 1)
+
+#define CLK_AVS_LIT_EB 0
+#define CLK_AVS_BIG_EB 1
+#define CLK_AP_INTC5_EB 2
+#define CLK_GPIO_EB 3
+#define CLK_PWM0_EB 4
+#define CLK_PWM1_EB 5
+#define CLK_PWM2_EB 6
+#define CLK_PWM3_EB 7
+#define CLK_KPD_EB 8
+#define CLK_AON_SYS_EB 9
+#define CLK_AP_SYS_EB 10
+#define CLK_AON_TMR_EB 11
+#define CLK_AP_TMR0_EB 12
+#define CLK_EFUSE_EB 13
+#define CLK_EIC_EB 14
+#define CLK_PUB1_REG_EB 15
+#define CLK_ADI_EB 16
+#define CLK_AP_INTC0_EB 17
+#define CLK_AP_INTC1_EB 18
+#define CLK_AP_INTC2_EB 19
+#define CLK_AP_INTC3_EB 20
+#define CLK_AP_INTC4_EB 21
+#define CLK_SPLK_EB 22
+#define CLK_MSPI_EB 23
+#define CLK_PUB0_REG_EB 24
+#define CLK_PIN_EB 25
+#define CLK_AON_CKG_EB 26
+#define CLK_GPU_EB 27
+#define CLK_APCPU_TS0_EB 28
+#define CLK_APCPU_TS1_EB 29
+#define CLK_DAP_EB 30
+#define CLK_I2C_EB 31
+#define CLK_PMU_EB 32
+#define CLK_THM_EB 33
+#define CLK_AUX0_EB 34
+#define CLK_AUX1_EB 35
+#define CLK_AUX2_EB 36
+#define CLK_PROBE_EB 37
+#define CLK_GPU0_AVS_EB 38
+#define CLK_GPU1_AVS_EB 39
+#define CLK_APCPU_WDG_EB 40
+#define CLK_AP_TMR1_EB 41
+#define CLK_AP_TMR2_EB 42
+#define CLK_DISP_EMC_EB 43
+#define CLK_ZIP_EMC_EB 44
+#define CLK_GSP_EMC_EB 45
+#define CLK_OSC_AON_EB 46
+#define CLK_LVDS_TRX_EB 47
+#define CLK_LVDS_TCXO_EB 48
+#define CLK_MDAR_EB 49
+#define CLK_RTC4M0_CAL_EB 50
+#define CLK_RCT100M_CAL_EB 51
+#define CLK_DJTAG_EB 52
+#define CLK_MBOX_EB 53
+#define CLK_AON_DMA_EB 54
+#define CLK_DBG_EMC_EB 55
+#define CLK_LVDS_PLL_DIV_EN 56
+#define CLK_DEF_EB 57
+#define CLK_AON_APB_RSV0 58
+#define CLK_ORP_JTAG_EB 59
+#define CLK_VSP_EB 60
+#define CLK_CAM_EB 61
+#define CLK_DISP_EB 62
+#define CLK_DBG_AXI_IF_EB 63
+#define CLK_SDIO0_2X_EN 64
+#define CLK_SDIO1_2X_EN 65
+#define CLK_SDIO2_2X_EN 66
+#define CLK_EMMC_2X_EN 67
+#define CLK_AON_GATE_NUM (CLK_EMMC_2X_EN + 1)
+
+#define CLK_LIT_MCU 0
+#define CLK_BIG_MCU 1
+#define CLK_AONSECURE_NUM (CLK_BIG_MCU + 1)
+
+#define CLK_AGCP_IIS0_EB 0
+#define CLK_AGCP_IIS1_EB 1
+#define CLK_AGCP_IIS2_EB 2
+#define CLK_AGCP_IIS3_EB 3
+#define CLK_AGCP_UART_EB 4
+#define CLK_AGCP_DMACP_EB 5
+#define CLK_AGCP_DMAAP_EB 6
+#define CLK_AGCP_ARC48K_EB 7
+#define CLK_AGCP_SRC44P1K_EB 8
+#define CLK_AGCP_MCDT_EB 9
+#define CLK_AGCP_VBCIFD_EB 10
+#define CLK_AGCP_VBC_EB 11
+#define CLK_AGCP_SPINLOCK_EB 12
+#define CLK_AGCP_ICU_EB 13
+#define CLK_AGCP_AP_ASHB_EB 14
+#define CLK_AGCP_CP_ASHB_EB 15
+#define CLK_AGCP_AUD_EB 16
+#define CLK_AGCP_AUDIF_EB 17
+#define CLK_AGCP_GATE_NUM (CLK_AGCP_AUDIF_EB + 1)
+
+#define CLK_GPU 0
+#define CLK_GPU_NUM (CLK_GPU + 1)
+
+#define CLK_AHB_VSP 0
+#define CLK_VSP 1
+#define CLK_VSP_ENC 2
+#define CLK_VPP 3
+#define CLK_VSP_26M 4
+#define CLK_VSP_NUM (CLK_VSP_26M + 1)
+
+#define CLK_VSP_DEC_EB 0
+#define CLK_VSP_CKG_EB 1
+#define CLK_VSP_MMU_EB 2
+#define CLK_VSP_ENC_EB 3
+#define CLK_VPP_EB 4
+#define CLK_VSP_26M_EB 5
+#define CLK_VSP_AXI_GATE 6
+#define CLK_VSP_ENC_GATE 7
+#define CLK_VPP_AXI_GATE 8
+#define CLK_VSP_BM_GATE 9
+#define CLK_VSP_ENC_BM_GATE 10
+#define CLK_VPP_BM_GATE 11
+#define CLK_VSP_GATE_NUM (CLK_VPP_BM_GATE + 1)
+
+#define CLK_AHB_CAM 0
+#define CLK_SENSOR0 1
+#define CLK_SENSOR1 2
+#define CLK_SENSOR2 3
+#define CLK_MIPI_CSI0_EB 4
+#define CLK_MIPI_CSI1_EB 5
+#define CLK_CAM_NUM (CLK_MIPI_CSI1_EB + 1)
+
+#define CLK_DCAM0_EB 0
+#define CLK_DCAM1_EB 1
+#define CLK_ISP0_EB 2
+#define CLK_CSI0_EB 3
+#define CLK_CSI1_EB 4
+#define CLK_JPG0_EB 5
+#define CLK_JPG1_EB 6
+#define CLK_CAM_CKG_EB 7
+#define CLK_CAM_MMU_EB 8
+#define CLK_ISP1_EB 9
+#define CLK_CPP_EB 10
+#define CLK_MMU_PF_EB 11
+#define CLK_ISP2_EB 12
+#define CLK_DCAM2ISP_IF_EB 13
+#define CLK_ISP2DCAM_IF_EB 14
+#define CLK_ISP_LCLK_EB 15
+#define CLK_ISP_ICLK_EB 16
+#define CLK_ISP_MCLK_EB 17
+#define CLK_ISP_PCLK_EB 18
+#define CLK_ISP_ISP2DCAM_EB 19
+#define CLK_DCAM0_IF_EB 20
+#define CLK_CLK26M_IF_EB 21
+#define CLK_CPHY0_GATE 22
+#define CLK_MIPI_CSI0_GATE 23
+#define CLK_CPHY1_GATE 24
+#define CLK_MIPI_CSI1 25
+#define CLK_DCAM0_AXI_GATE 26
+#define CLK_DCAM1_AXI_GATE 27
+#define CLK_SENSOR0_GATE 28
+#define CLK_SENSOR1_GATE 29
+#define CLK_JPG0_AXI_GATE 30
+#define CLK_GPG1_AXI_GATE 31
+#define CLK_ISP0_AXI_GATE 32
+#define CLK_ISP1_AXI_GATE 33
+#define CLK_ISP2_AXI_GATE 34
+#define CLK_CPP_AXI_GATE 35
+#define CLK_D0_IF_AXI_GATE 36
+#define CLK_D2I_IF_AXI_GATE 37
+#define CLK_I2D_IF_AXI_GATE 38
+#define CLK_SPARE_AXI_GATE 39
+#define CLK_SENSOR2_GATE 40
+#define CLK_D0IF_IN_D_EN 41
+#define CLK_D1IF_IN_D_EN 42
+#define CLK_D0IF_IN_D2I_EN 43
+#define CLK_D1IF_IN_D2I_EN 44
+#define CLK_IA_IN_D2I_EN 45
+#define CLK_IB_IN_D2I_EN 46
+#define CLK_IC_IN_D2I_EN 47
+#define CLK_IA_IN_I_EN 48
+#define CLK_IB_IN_I_EN 49
+#define CLK_IC_IN_I_EN 50
+#define CLK_CAM_GATE_NUM (CLK_IC_IN_I_EN + 1)
+
+#define CLK_AHB_DISP 0
+#define CLK_DISPC0_DPI 1
+#define CLK_DISPC1_DPI 2
+#define CLK_DISP_NUM (CLK_DISPC1_DPI + 1)
+
+#define CLK_DISPC0_EB 0
+#define CLK_DISPC1_EB 1
+#define CLK_DISPC_MMU_EB 2
+#define CLK_GSP0_EB 3
+#define CLK_GSP1_EB 4
+#define CLK_GSP0_MMU_EB 5
+#define CLK_GSP1_MMU_EB 6
+#define CLK_DSI0_EB 7
+#define CLK_DSI1_EB 8
+#define CLK_DISP_CKG_EB 9
+#define CLK_DISP_GPU_EB 10
+#define CLK_GPU_MTX_EB 11
+#define CLK_GSP_MTX_EB 12
+#define CLK_TMC_MTX_EB 13
+#define CLK_DISPC_MTX_EB 14
+#define CLK_DPHY0_GATE 15
+#define CLK_DPHY1_GATE 16
+#define CLK_GSP0_A_GATE 17
+#define CLK_GSP1_A_GATE 18
+#define CLK_GSP0_F_GATE 19
+#define CLK_GSP1_F_GATE 20
+#define CLK_D_MTX_F_GATE 21
+#define CLK_D_MTX_A_GATE 22
+#define CLK_D_NOC_F_GATE 23
+#define CLK_D_NOC_A_GATE 24
+#define CLK_GSP_MTX_F_GATE 25
+#define CLK_GSP_MTX_A_GATE 26
+#define CLK_GSP_NOC_F_GATE 27
+#define CLK_GSP_NOC_A_GATE 28
+#define CLK_DISPM0IDLE_GATE 29
+#define CLK_GSPM0IDLE_GATE 30
+#define CLK_DISP_GATE_NUM (CLK_GSPM0IDLE_GATE + 1)
+
+#define CLK_SIM0_EB 0
+#define CLK_IIS0_EB 1
+#define CLK_IIS1_EB 2
+#define CLK_IIS2_EB 3
+#define CLK_IIS3_EB 4
+#define CLK_SPI0_EB 5
+#define CLK_SPI1_EB 6
+#define CLK_SPI2_EB 7
+#define CLK_I2C0_EB 8
+#define CLK_I2C1_EB 9
+#define CLK_I2C2_EB 10
+#define CLK_I2C3_EB 11
+#define CLK_I2C4_EB 12
+#define CLK_I2C5_EB 13
+#define CLK_UART0_EB 14
+#define CLK_UART1_EB 15
+#define CLK_UART2_EB 16
+#define CLK_UART3_EB 17
+#define CLK_UART4_EB 18
+#define CLK_AP_CKG_EB 19
+#define CLK_SPI3_EB 20
+#define CLK_APAPB_GATE_NUM (CLK_SPI3_EB + 1)
+
+#endif /* _DT_BINDINGS_CLK_SC9860_H_ */
--
2.7.4
^ permalink raw reply related
* [PATCH V6 08/12] dt-bindings: Add Spreadtrum clock binding documentation
From: Chunyan Zhang @ 2017-11-27 10:01 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, Rob Herring, Mark Rutland
Cc: Catalin Marinas, Will Deacon, linux-clk, linux-kernel, devicetree,
linux-arm-kernel, Arnd Bergmann, Mark Brown, Xiaolong Zhang,
Ben Li, Orson Zhai, Chunyan Zhang
In-Reply-To: <20171127100115.20655-1-chunyan.zhang@spreadtrum.com>
Introduce a new binding with its documentation for Spreadtrum clock
sub-framework.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/clock/sprd.txt | 63 ++++++++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/sprd.txt
diff --git a/Documentation/devicetree/bindings/clock/sprd.txt b/Documentation/devicetree/bindings/clock/sprd.txt
new file mode 100644
index 0000000..e9d179e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sprd.txt
@@ -0,0 +1,63 @@
+Spreadtrum Clock Binding
+------------------------
+
+Required properties:
+- compatible: should contain the following compatible strings:
+ - "sprd,sc9860-pmu-gate"
+ - "sprd,sc9860-pll"
+ - "sprd,sc9860-ap-clk"
+ - "sprd,sc9860-aon-prediv"
+ - "sprd,sc9860-apahb-gate"
+ - "sprd,sc9860-aon-gate"
+ - "sprd,sc9860-aonsecure-clk"
+ - "sprd,sc9860-agcp-gate"
+ - "sprd,sc9860-gpu-clk"
+ - "sprd,sc9860-vsp-clk"
+ - "sprd,sc9860-vsp-gate"
+ - "sprd,sc9860-cam-clk"
+ - "sprd,sc9860-cam-gate"
+ - "sprd,sc9860-disp-clk"
+ - "sprd,sc9860-disp-gate"
+ - "sprd,sc9860-apapb-gate"
+
+- #clock-cells: must be 1
+
+- clocks : Should be the input parent clock(s) phandle for the clock, this
+ property here just simply shows which clock group the clocks'
+ parents are in, since each clk node would represent many clocks
+ which are defined in the driver. The detailed dependency
+ relationship (i.e. how many parents and which are the parents)
+ are implemented in driver code.
+
+Optional properties:
+
+- reg: Contain the registers base address and length. It must be configured
+ only if no 'sprd,syscon' under the node.
+
+- sprd,syscon: phandle to the syscon which is in the same address area with
+ the clock, and so we can get regmap for the clocks from the
+ syscon device.
+
+Example:
+
+ pmu_gate: pmu-gate {
+ compatible = "sprd,sc9860-pmu-gate";
+ sprd,syscon = <&pmu_regs>;
+ clocks = <&ext_26m>;
+ #clock-cells = <1>;
+ };
+
+ pll: pll {
+ compatible = "sprd,sc9860-pll";
+ sprd,syscon = <&ana_regs>;
+ clocks = <&pmu_gate 0>;
+ #clock-cells = <1>;
+ };
+
+ ap_clk: clock-controller@20000000 {
+ compatible = "sprd,sc9860-ap-clk";
+ reg = <0 0x20000000 0 0x400>;
+ clocks = <&ext_26m>, <&pll 0>,
+ <&pmu_gate 0>;
+ #clock-cells = <1>;
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH V6 07/12] clk: sprd: add adjustable pll support
From: Chunyan Zhang @ 2017-11-27 10:01 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, Rob Herring, Mark Rutland
Cc: Catalin Marinas, Will Deacon, linux-clk, linux-kernel, devicetree,
linux-arm-kernel, Arnd Bergmann, Mark Brown, Xiaolong Zhang,
Ben Li, Orson Zhai, Chunyan Zhang
In-Reply-To: <20171127100115.20655-1-chunyan.zhang@spreadtrum.com>
Introduced a common adjustable pll clock driver for Spreadtrum SoCs.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
---
drivers/clk/sprd/Makefile | 1 +
drivers/clk/sprd/pll.c | 268 ++++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/sprd/pll.h | 110 +++++++++++++++++++
3 files changed, 379 insertions(+)
create mode 100644 drivers/clk/sprd/pll.c
create mode 100644 drivers/clk/sprd/pll.h
diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile
index 2262e76..d693969 100644
--- a/drivers/clk/sprd/Makefile
+++ b/drivers/clk/sprd/Makefile
@@ -5,3 +5,4 @@ clk-sprd-y += gate.o
clk-sprd-y += mux.o
clk-sprd-y += div.o
clk-sprd-y += composite.o
+clk-sprd-y += pll.o
diff --git a/drivers/clk/sprd/pll.c b/drivers/clk/sprd/pll.c
new file mode 100644
index 0000000..1fd8d32
--- /dev/null
+++ b/drivers/clk/sprd/pll.c
@@ -0,0 +1,268 @@
+/*
+ * Spreadtrum pll clock driver
+ *
+ * Copyright (C) 2015~2017 Spreadtrum, Inc.
+ * Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include "pll.h"
+
+#define CLK_PLL_1M 1000000
+#define CLK_PLL_10M (CLK_PLL_1M * 10)
+
+#define pindex(pll, member) \
+ (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
+
+#define pshift(pll, member) \
+ (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
+
+#define pwidth(pll, member) \
+ pll->factors[member].width
+
+#define pmask(pll, member) \
+ ((pwidth(pll, member)) ? \
+ GENMASK(pwidth(pll, member) + pshift(pll, member) - 1, \
+ pshift(pll, member)) : 0)
+
+#define pinternal(pll, cfg, member) \
+ (cfg[pindex(pll, member)] & pmask(pll, member))
+
+#define pinternal_val(pll, cfg, member) \
+ (pinternal(pll, cfg, member) >> pshift(pll, member))
+
+static inline unsigned int
+sprd_pll_read(const struct sprd_pll *pll, u8 index)
+{
+ const struct sprd_clk_common *common = &pll->common;
+ unsigned int val = 0;
+
+ if (WARN_ON(index >= pll->regs_num))
+ return 0;
+
+ sprd_regmap_read(common->regmap, common->reg + index * 4, &val);
+
+ return val;
+}
+
+static inline void
+sprd_pll_write(const struct sprd_pll *pll, u8 index,
+ u32 msk, u32 val)
+{
+ const struct sprd_clk_common *common = &pll->common;
+ unsigned int offset, reg;
+ int ret = 0;
+
+ if (WARN_ON(index >= pll->regs_num))
+ return;
+
+ offset = common->reg + index * 4;
+ ret = sprd_regmap_read(common->regmap, offset, ®);
+ if (!ret)
+ sprd_regmap_write(common->regmap, offset, (reg & ~msk) | val);
+}
+
+static unsigned long pll_get_refin(const struct sprd_pll *pll)
+{
+ u32 shift, mask, index, refin_id = 3;
+ const unsigned long refin[4] = { 2, 4, 13, 26 };
+
+ if (pwidth(pll, PLL_REFIN)) {
+ index = pindex(pll, PLL_REFIN);
+ shift = pshift(pll, PLL_REFIN);
+ mask = pmask(pll, PLL_REFIN);
+ refin_id = (sprd_pll_read(pll, index) & mask) >> shift;
+ if (refin_id > 3)
+ refin_id = 3;
+ }
+
+ return refin[refin_id];
+}
+
+static u32 pll_get_ibias(u64 rate, const u64 *table)
+{
+ u32 i, num = table[0];
+
+ for (i = 1; i < num + 1; i++)
+ if (rate <= table[i])
+ break;
+
+ return (i == num + 1) ? num : i;
+}
+
+static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll,
+ unsigned long parent_rate)
+{
+ u32 *cfg;
+ u32 i, mask, regs_num = pll->regs_num;
+ unsigned long rate, nint, kint = 0;
+ u64 refin;
+ u16 k1, k2;
+
+ cfg = kcalloc(regs_num, sizeof(*cfg), GFP_KERNEL);
+ if (!cfg)
+ return -ENOMEM;
+
+ for (i = 0; i < regs_num; i++)
+ cfg[i] = sprd_pll_read(pll, i);
+
+ refin = pll_get_refin(pll);
+
+ if (pinternal(pll, cfg, PLL_PREDIV))
+ refin = refin * 2;
+
+ if (pwidth(pll, PLL_POSTDIV) &&
+ ((pll->fflag == 1 && pinternal(pll, cfg, PLL_POSTDIV)) ||
+ (!pll->fflag && !pinternal(pll, cfg, PLL_POSTDIV))))
+ refin = refin / 2;
+
+ if (!pinternal(pll, cfg, PLL_DIV_S)) {
+ rate = refin * pinternal_val(pll, cfg, PLL_N) * CLK_PLL_10M;
+ } else {
+ nint = pinternal_val(pll, cfg, PLL_NINT);
+ if (pinternal(pll, cfg, PLL_SDM_EN))
+ kint = pinternal_val(pll, cfg, PLL_KINT);
+
+ mask = pmask(pll, PLL_KINT);
+
+ k1 = pll->k1;
+ k2 = pll->k2;
+ rate = DIV_ROUND_CLOSEST_ULL(refin * kint * k1,
+ ((mask >> __ffs(mask)) + 1)) *
+ k2 + refin * nint * CLK_PLL_1M;
+ }
+
+ return rate;
+}
+
+#define SPRD_PLL_WRITE_CHECK(pll, i, mask, val) \
+ (((sprd_pll_read(pll, i) & mask) == val) ? 0 : (-EFAULT))
+
+static int _sprd_pll_set_rate(const struct sprd_pll *pll,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct reg_cfg *cfg;
+ int ret = 0;
+ u32 mask, shift, width, ibias_val, index;
+ u32 regs_num = pll->regs_num, i = 0;
+ unsigned long kint, nint;
+ u64 tmp, refin, fvco = rate;
+
+ cfg = kcalloc(regs_num, sizeof(*cfg), GFP_KERNEL);
+ if (!cfg)
+ return -ENOMEM;
+
+ refin = pll_get_refin(pll);
+
+ mask = pmask(pll, PLL_PREDIV);
+ index = pindex(pll, PLL_PREDIV);
+ width = pwidth(pll, PLL_PREDIV);
+ if (width && (sprd_pll_read(pll, index) & mask))
+ refin = refin * 2;
+
+ mask = pmask(pll, PLL_POSTDIV);
+ index = pindex(pll, PLL_POSTDIV);
+ width = pwidth(pll, PLL_POSTDIV);
+ cfg[index].msk = mask;
+ if (width && ((pll->fflag == 1 && fvco <= pll->fvco) ||
+ (pll->fflag == 0 && fvco > pll->fvco)))
+ cfg[index].val |= mask;
+
+ if (width && fvco <= pll->fvco)
+ fvco = fvco * 2;
+
+ mask = pmask(pll, PLL_DIV_S);
+ index = pindex(pll, PLL_DIV_S);
+ cfg[index].val |= mask;
+ cfg[index].msk |= mask;
+
+ mask = pmask(pll, PLL_SDM_EN);
+ index = pindex(pll, PLL_SDM_EN);
+ cfg[index].val |= mask;
+ cfg[index].msk |= mask;
+
+ nint = do_div(fvco, refin * CLK_PLL_1M);
+ mask = pmask(pll, PLL_NINT);
+ index = pindex(pll, PLL_NINT);
+ shift = pshift(pll, PLL_NINT);
+ cfg[index].val |= (nint << shift) & mask;
+ cfg[index].msk |= mask;
+
+ mask = pmask(pll, PLL_KINT);
+ index = pindex(pll, PLL_KINT);
+ width = pwidth(pll, PLL_KINT);
+ shift = pshift(pll, PLL_KINT);
+ tmp = fvco - refin * nint * CLK_PLL_1M;
+ tmp = do_div(tmp, 10000) * ((mask >> shift) + 1);
+ kint = DIV_ROUND_CLOSEST_ULL(tmp, refin * 100);
+ cfg[index].val |= (kint << shift) & mask;
+ cfg[index].msk |= mask;
+
+ ibias_val = pll_get_ibias(fvco, pll->itable);
+
+ mask = pmask(pll, PLL_IBIAS);
+ index = pindex(pll, PLL_IBIAS);
+ shift = pshift(pll, PLL_IBIAS);
+ cfg[index].val |= ibias_val << shift & mask;
+ cfg[index].msk |= mask;
+
+ for (i = 0; i < regs_num; i++) {
+ if (cfg[i].msk) {
+ sprd_pll_write(pll, i, cfg[i].msk, cfg[i].val);
+ ret |= SPRD_PLL_WRITE_CHECK(pll, i, cfg[i].msk,
+ cfg[i].val);
+ }
+ }
+
+ if (!ret)
+ udelay(pll->udelay);
+
+ return ret;
+}
+
+static unsigned long sprd_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct sprd_pll *pll = hw_to_sprd_pll(hw);
+
+ return _sprd_pll_recalc_rate(pll, parent_rate);
+}
+
+static int sprd_pll_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct sprd_pll *pll = hw_to_sprd_pll(hw);
+
+ return _sprd_pll_set_rate(pll, rate, parent_rate);
+}
+
+static int sprd_pll_clk_prepare(struct clk_hw *hw)
+{
+ struct sprd_pll *pll = hw_to_sprd_pll(hw);
+
+ udelay(pll->udelay);
+
+ return 0;
+}
+
+static long sprd_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ return rate;
+}
+
+const struct clk_ops sprd_pll_ops = {
+ .prepare = sprd_pll_clk_prepare,
+ .recalc_rate = sprd_pll_recalc_rate,
+ .round_rate = sprd_pll_round_rate,
+ .set_rate = sprd_pll_set_rate,
+};
+EXPORT_SYMBOL_GPL(sprd_pll_ops);
diff --git a/drivers/clk/sprd/pll.h b/drivers/clk/sprd/pll.h
new file mode 100644
index 0000000..a25b003
--- /dev/null
+++ b/drivers/clk/sprd/pll.h
@@ -0,0 +1,110 @@
+/*
+ * Spreadtrum clock pll configurations
+ *
+ * Copyright (C) 2015~2017 Spreadtrum, Inc.
+ * Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _SPRD_PLL_H_
+#define _SPRD_PLL_H_
+
+#include "common.h"
+
+struct reg_cfg {
+ u32 val;
+ u32 msk;
+};
+
+struct clk_bit_field {
+ u8 shift;
+ u8 width;
+};
+
+enum {
+ PLL_LOCK_DONE,
+ PLL_DIV_S,
+ PLL_MOD_EN,
+ PLL_SDM_EN,
+ PLL_REFIN,
+ PLL_IBIAS,
+ PLL_N,
+ PLL_NINT,
+ PLL_KINT,
+ PLL_PREDIV,
+ PLL_POSTDIV,
+
+ PLL_FACT_MAX
+};
+
+/*
+ * struct sprd_pll - definition of adjustable pll clock
+ *
+ * @reg: registers used to set the configuration of pll clock,
+ * reg[0] shows how many registers this pll clock uses.
+ * @itable: pll ibias table, itable[0] means how many items this
+ * table includes
+ * @udelay delay time after setting rate
+ * @factors used to calculate the pll clock rate
+ * @fvco: fvco threshold rate
+ * @fflag: fvco flag
+ */
+struct sprd_pll {
+ u32 regs_num;
+ const u64 *itable;
+ const struct clk_bit_field *factors;
+ u16 udelay;
+ u16 k1;
+ u16 k2;
+ u16 fflag;
+ u64 fvco;
+
+ struct sprd_clk_common common;
+};
+
+#define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
+ _regs_num, _itable, _factors, \
+ _udelay, _k1, _k2, _fflag, _fvco) \
+ struct sprd_pll _struct = { \
+ .regs_num = _regs_num, \
+ .itable = _itable, \
+ .factors = _factors, \
+ .udelay = _udelay, \
+ .k1 = _k1, \
+ .k2 = _k2, \
+ .fflag = _fflag, \
+ .fvco = _fvco, \
+ .common = { \
+ .regmap = NULL, \
+ .reg = _reg, \
+ .hw.init = CLK_HW_INIT(_name, \
+ _parent, \
+ &sprd_pll_ops, \
+ 0), \
+ }, \
+ }
+
+#define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \
+ _regs_num, _itable, _factors, \
+ _udelay, _k1, _k2) \
+ SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
+ _regs_num, _itable, _factors, \
+ _udelay, _k1, _k2, 0, 0)
+
+#define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \
+ _regs_num, _itable, _factors, _udelay) \
+ SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
+ _regs_num, _itable, _factors, \
+ _udelay, 1000, 1000, 0, 0)
+
+static inline struct sprd_pll *hw_to_sprd_pll(struct clk_hw *hw)
+{
+ struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
+
+ return container_of(common, struct sprd_pll, common);
+}
+
+extern const struct clk_ops sprd_pll_ops;
+
+#endif /* _SPRD_PLL_H_ */
--
2.7.4
^ permalink raw reply related
* [PATCH V6 06/12] clk: sprd: add composite clock support
From: Chunyan Zhang @ 2017-11-27 10:01 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, Rob Herring, Mark Rutland
Cc: Catalin Marinas, Will Deacon, linux-clk, linux-kernel, devicetree,
linux-arm-kernel, Arnd Bergmann, Mark Brown, Xiaolong Zhang,
Ben Li, Orson Zhai, Chunyan Zhang
In-Reply-To: <20171127100115.20655-1-chunyan.zhang@spreadtrum.com>
This patch introduced composite driver for Spreadtrum's SoCs. The
functions of this composite clock simply consist of divider and
mux clocks.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
---
drivers/clk/sprd/Makefile | 1 +
drivers/clk/sprd/composite.c | 62 ++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/sprd/composite.h | 53 +++++++++++++++++++++++++++++++++++++
3 files changed, 116 insertions(+)
create mode 100644 drivers/clk/sprd/composite.c
create mode 100644 drivers/clk/sprd/composite.h
diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile
index 80e6039..2262e76 100644
--- a/drivers/clk/sprd/Makefile
+++ b/drivers/clk/sprd/Makefile
@@ -4,3 +4,4 @@ clk-sprd-y += common.o
clk-sprd-y += gate.o
clk-sprd-y += mux.o
clk-sprd-y += div.o
+clk-sprd-y += composite.o
diff --git a/drivers/clk/sprd/composite.c b/drivers/clk/sprd/composite.c
new file mode 100644
index 0000000..218e17c
--- /dev/null
+++ b/drivers/clk/sprd/composite.c
@@ -0,0 +1,62 @@
+/*
+ * Spreadtrum composite clock driver
+ *
+ * Copyright (C) 2017 Spreadtrum, Inc.
+ * Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <linux/clk-provider.h>
+
+#include "composite.h"
+
+static long sprd_comp_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct sprd_comp *cc = hw_to_sprd_comp(hw);
+
+ return sprd_div_helper_round_rate(&cc->common, &cc->div,
+ rate, parent_rate);
+}
+
+static unsigned long sprd_comp_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct sprd_comp *cc = hw_to_sprd_comp(hw);
+
+ return sprd_div_helper_recalc_rate(&cc->common, &cc->div, parent_rate);
+}
+
+static int sprd_comp_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct sprd_comp *cc = hw_to_sprd_comp(hw);
+
+ return sprd_div_helper_set_rate(&cc->common, &cc->div,
+ rate, parent_rate);
+}
+
+static u8 sprd_comp_get_parent(struct clk_hw *hw)
+{
+ struct sprd_comp *cc = hw_to_sprd_comp(hw);
+
+ return sprd_mux_helper_get_parent(&cc->common, &cc->mux);
+}
+
+static int sprd_comp_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct sprd_comp *cc = hw_to_sprd_comp(hw);
+
+ return sprd_mux_helper_set_parent(&cc->common, &cc->mux, index);
+}
+
+const struct clk_ops sprd_comp_ops = {
+ .get_parent = sprd_comp_get_parent,
+ .set_parent = sprd_comp_set_parent,
+
+ .round_rate = sprd_comp_round_rate,
+ .recalc_rate = sprd_comp_recalc_rate,
+ .set_rate = sprd_comp_set_rate,
+};
+EXPORT_SYMBOL_GPL(sprd_comp_ops);
diff --git a/drivers/clk/sprd/composite.h b/drivers/clk/sprd/composite.h
new file mode 100644
index 0000000..b337bda
--- /dev/null
+++ b/drivers/clk/sprd/composite.h
@@ -0,0 +1,53 @@
+/*
+ * Spreadtrum composite clock driver
+ *
+ * Copyright (C) 2017 Spreadtrum, Inc.
+ * Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _SPRD_COMPOSITE_H_
+#define _SPRD_COMPOSITE_H_
+
+#include "common.h"
+#include "mux.h"
+#include "div.h"
+
+struct sprd_comp {
+ struct sprd_mux_ssel mux;
+ struct sprd_div_internal div;
+ struct sprd_clk_common common;
+};
+
+#define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \
+ _mshift, _mwidth, _dshift, _dwidth, _flags) \
+ struct sprd_comp _struct = { \
+ .mux = _SPRD_MUX_CLK(_mshift, _mwidth, _table), \
+ .div = _SPRD_DIV_CLK(_dshift, _dwidth), \
+ .common = { \
+ .regmap = NULL, \
+ .reg = _reg, \
+ .hw.init = CLK_HW_INIT_PARENTS(_name, \
+ _parent, \
+ &sprd_comp_ops, \
+ _flags), \
+ } \
+ }
+
+#define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \
+ _mwidth, _dshift, _dwidth, _flags) \
+ SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, \
+ NULL, _mshift, _mwidth, \
+ _dshift, _dwidth, _flags)
+
+static inline struct sprd_comp *hw_to_sprd_comp(const struct clk_hw *hw)
+{
+ struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
+
+ return container_of(common, struct sprd_comp, common);
+}
+
+extern const struct clk_ops sprd_comp_ops;
+
+#endif /* _SPRD_COMPOSITE_H_ */
--
2.7.4
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox