* [PATCH v4 04/12] ARM: dts: r8a7793: Update CMT compat strings
From: Geert Uytterhoeven @ 2017-11-28 13:47 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: linux-renesas-soc, linux-arm-kernel, devicetree, Magnus Damm,
Geert Uytterhoeven
In-Reply-To: <1511876856-9495-1-git-send-email-geert+renesas@glider.be>
From: Magnus Damm <damm+renesas@opensource.se>
Use recently updated R-Car Gen2 CMT0 and CMT1 compat strings.
With this change in place we can keep device-specific configuration in
the driver and the driver can be able to support CMT1 specific features.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v4:
- Rebased against renesas-devel-20171127-v4.15-rc1,
v3:
- Take over from Magnus,
- Update compatible values,
- Split in per-SoC patches,
v2:
- Added Acked-by and Tested-by from Geert,
- Added Acked-by from Laurent.
---
arch/arm/boot/dts/r8a7793.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index f3aeed4f6656918e..035b5a7639bc7eb7 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -248,7 +248,7 @@
};
cmt0: timer@ffca0000 {
- compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
+ compatible = "renesas,r8a7793-cmt0", "renesas,rcar-gen2-cmt0";
reg = <0 0xffca0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
@@ -263,7 +263,7 @@
};
cmt1: timer@e6130000 {
- compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
+ compatible = "renesas,r8a7793-cmt1", "renesas,rcar-gen2-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
--
2.7.4
^ permalink raw reply related
* [PATCH v4 03/12] ARM: dts: r8a7791: Update CMT compat strings
From: Geert Uytterhoeven @ 2017-11-28 13:47 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Magnus Damm,
Geert Uytterhoeven
In-Reply-To: <1511876856-9495-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
From: Magnus Damm <damm+renesas-yzvPICuk2ACczHhG9Qg4qA@public.gmane.org>
Use recently updated R-Car Gen2 CMT0 and CMT1 compat strings.
With this change in place we can keep device-specific configuration in
the driver and the driver can be able to support CMT1 specific features.
Signed-off-by: Magnus Damm <damm+renesas-yzvPICuk2ACczHhG9Qg4qA@public.gmane.org>
Acked-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
v4:
- Rebased against renesas-devel-20171127-v4.15-rc1,
v3:
- Take over from Magnus,
- Update compatible values,
- Split in per-SoC patches,
v2:
- Added Acked-by and Tested-by from Geert,
- Added Acked-by from Laurent.
---
arch/arm/boot/dts/r8a7791.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index e888b5b0e1353aba..a69d6f883b34519f 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -257,7 +257,7 @@
};
cmt0: timer@ffca0000 {
- compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
+ compatible = "renesas,r8a7791-cmt0", "renesas,rcar-gen2-cmt0";
reg = <0 0xffca0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
@@ -272,7 +272,7 @@
};
cmt1: timer@e6130000 {
- compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
+ compatible = "renesas,r8a7791-cmt1", "renesas,rcar-gen2-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
--
2.7.4
--
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^ permalink raw reply related
* [PATCH v4 02/12] ARM: dts: r8a7790: Update CMT compat strings
From: Geert Uytterhoeven @ 2017-11-28 13:47 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Magnus Damm,
Geert Uytterhoeven
In-Reply-To: <1511876856-9495-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
From: Magnus Damm <damm+renesas-yzvPICuk2ACczHhG9Qg4qA@public.gmane.org>
Use recently updated R-Car Gen2 CMT0 and CMT1 compat strings.
With this change in place we can keep device-specific configuration in
the driver and the driver can be able to support CMT1 specific features.
Signed-off-by: Magnus Damm <damm+renesas-yzvPICuk2ACczHhG9Qg4qA@public.gmane.org>
Acked-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
v4:
- Rebased against renesas-devel-20171127-v4.15-rc1,
v3:
- Take over from Magnus,
- Update compatible values,
- Split in per-SoC patches,
v2:
- Added Acked-by and Tested-by from Geert,
- Added Acked-by from Laurent.
---
arch/arm/boot/dts/r8a7790.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 5477a62f4642343f..696522da2f99c8e2 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -311,7 +311,7 @@
};
cmt0: timer@ffca0000 {
- compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
+ compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
reg = <0 0xffca0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
@@ -326,7 +326,7 @@
};
cmt1: timer@e6130000 {
- compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
+ compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
--
2.7.4
--
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^ permalink raw reply related
* [PATCH v4 01/12] ARM: dts: r8a73a4: Update CMT compat string
From: Geert Uytterhoeven @ 2017-11-28 13:47 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: linux-renesas-soc, linux-arm-kernel, devicetree, Magnus Damm,
Geert Uytterhoeven
In-Reply-To: <1511876856-9495-1-git-send-email-geert+renesas@glider.be>
From: Magnus Damm <damm+renesas@opensource.se>
Use the recently updated r8a73a4 CMT1 compat string.
With this change in place we can keep device-specific configuration in
the driver and the driver can be able to support CMT1 specific features.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v4:
- Rebased against renesas-devel-20171127-v4.15-rc1,
v3:
- Take over from Magnus,
- Update compatible values,
- Split in per-SoC patches,
v2:
- Added Acked-by and Tested-by from Geert,
- Added Acked-by from Laurent.
---
arch/arm/boot/dts/r8a73a4.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index dd4d09712a2a3a88..805b0fd70f53820d 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -132,7 +132,7 @@
};
cmt1: timer@e6130000 {
- compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
+ compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
--
2.7.4
^ permalink raw reply related
* [PATCH v4 00/12] ARM: dts: renesas: Update DTS for CMT DT binding rework
From: Geert Uytterhoeven @ 2017-11-28 13:47 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Geert Uytterhoeven
Hi Simon, Magnus,
This patch series updates the CMT device nodes in the various Renesas DTS
files sh_cmt clocksource driver for the recent DT binding rework that was
merged in v4.14-rc1 and v4.15-rc1.
This series is an evolutionary improvement of Magnus Damm's series "[PATCH
v2 00/11] clocksource: sh_cmt: DT binding rework V2":
- Patches 1-5 update the compatible values for the CMT0 and CMT1 device
nodes on R-Mobile APE6 and R-Car Gen2,
- Patches 6-12 remove the now obsolete "renesas,channels-mask" properties
from the CMT device nodes on all affected SoCs.
Changes compared to v3:
- Rebase against renesas-devel-20171127-v4.15-rc1,
Changes compared to v2:
- Take over from Magnus,
- Update compatible values,
- Split in per-SoC patches,
Dependencies:
- "[PATCH v3 0/7] clocksource: sh_cmt: Update driver for DT binding
rework" was merged in v4.15-rc1.
This has been part of renesas-drivers for more than two months, and part
of my local development tree for more than two years.
Thanks for applying!
Magnus Damm (12):
ARM: dts: r8a73a4: Update CMT compat string
ARM: dts: r8a7790: Update CMT compat strings
ARM: dts: r8a7791: Update CMT compat strings
ARM: dts: r8a7793: Update CMT compat strings
ARM: dts: r8a7794: Update CMT compat strings
ARM: dts: r8a73a4: Remove CMT renesas,channels-mask
ARM: dts: r8a7740: Remove CMT renesas,channels-mask
ARM: dts: r8a7790: Remove CMT renesas,channels-mask
ARM: dts: r8a7791: Remove CMT renesas,channels-mask
ARM: dts: r8a7793: Remove CMT renesas,channels-mask
ARM: dts: r8a7794: Remove CMT renesas,channels-mask
ARM: dts: sh73a0: Remove CMT renesas,channels-mask
arch/arm/boot/dts/r8a73a4.dtsi | 5 +----
arch/arm/boot/dts/r8a7740.dtsi | 3 ---
arch/arm/boot/dts/r8a7790.dtsi | 8 ++------
arch/arm/boot/dts/r8a7791.dtsi | 8 ++------
arch/arm/boot/dts/r8a7793.dtsi | 8 ++------
arch/arm/boot/dts/r8a7794.dtsi | 8 ++------
arch/arm/boot/dts/sh73a0.dtsi | 3 ---
7 files changed, 9 insertions(+), 34 deletions(-)
--
2.7.4
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply
* Re: [PATCH] media: i2c: adv748x: Restore full DT paths in kernel messages
From: Niklas Söderlund @ 2017-11-28 13:44 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Kieran Bingham, Mauro Carvalho Chehab, Rob Herring, linux-media,
devicetree, linux-renesas-soc, linux-kernel
In-Reply-To: <1511874084-5068-1-git-send-email-geert+renesas@glider.be>
Hi Geert,
Thanks for your patch.
On 2017-11-28 14:01:24 +0100, Geert Uytterhoeven wrote:
> As of_node_full_name() now returns only the basename, the endpoint
> information printed became useless:
>
> adv748x 4-0070: Endpoint endpoint on port 7
> adv748x 4-0070: Endpoint endpoint on port 8
> adv748x 4-0070: Endpoint endpoint on port 10
> adv748x 4-0070: Endpoint endpoint on port 11
>
> Restore the old behavior by using "%pOF" instead:
>
> adv748x 4-0070: Endpoint /soc/i2c@e66d8000/video-receiver@70/port@7/endpoint on port 7
> adv748x 4-0070: Endpoint /soc/i2c@e66d8000/video-receiver@70/port@8/endpoint on port 8
> adv748x 4-0070: Endpoint /soc/i2c@e66d8000/video-receiver@70/port@10/endpoint on port 10
> adv748x 4-0070: Endpoint /soc/i2c@e66d8000/video-receiver@70/port@11/endpoint on port 11
>
> Fixes: a7e4cfb0a7ca4773 ("of/fdt: only store the device node basename in full_name")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> ---
> drivers/media/i2c/adv748x/adv748x-core.c | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/media/i2c/adv748x/adv748x-core.c b/drivers/media/i2c/adv748x/adv748x-core.c
> index 5ee14f2c27478e3a..c1001db6a172e256 100644
> --- a/drivers/media/i2c/adv748x/adv748x-core.c
> +++ b/drivers/media/i2c/adv748x/adv748x-core.c
> @@ -646,14 +646,12 @@ static int adv748x_parse_dt(struct adv748x_state *state)
>
> for_each_endpoint_of_node(state->dev->of_node, ep_np) {
> of_graph_parse_endpoint(ep_np, &ep);
> - adv_info(state, "Endpoint %s on port %d",
> - of_node_full_name(ep.local_node),
> - ep.port);
> + adv_info(state, "Endpoint %pOF on port %d", ep.local_node,
> + ep.port);
>
> if (ep.port >= ADV748X_PORT_MAX) {
> - adv_err(state, "Invalid endpoint %s on port %d",
> - of_node_full_name(ep.local_node),
> - ep.port);
> + adv_err(state, "Invalid endpoint %pOF on port %d",
> + ep.local_node, ep.port);
>
> continue;
> }
> --
> 2.7.4
>
--
Regards,
Niklas Söderlund
^ permalink raw reply
* Re: [PATCH V4 3/6] iommu/arm-smmu: Invoke pm_runtime during probe, add/remove device
From: Vivek Gautam @ 2017-11-28 13:43 UTC (permalink / raw)
To: Rob Clark, Stephen Boyd
Cc: Robin Murphy, Will Deacon, Rafael J. Wysocki, Sricharan R,
Joerg Roedel, Rob Herring, Mark Rutland, Marek Szyprowski,
iommu@lists.linux-foundation.org, devicetree@vger.kernel.org,
Linux Kernel Mailing List, linux-clk, linux-arm-msm,
Stanimir Varbanov, Archit Taneja,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <CAF6AEGtq2_tMBd1U_t19s8Eg7+-RPQ+E_pCZCd75iFs6_bx53A@mail.gmail.com>
On 11/28/2017 05:13 AM, Rob Clark wrote:
> On Mon, Nov 27, 2017 at 5:22 PM, Stephen Boyd<sboyd@codeaurora.org> wrote:
>> On 11/15, Vivek Gautam wrote:
>>> Hi,
>>>
>>>
>>> On Mon, Aug 7, 2017 at 5:59 PM, Rob Clark<robdclark@gmail.com> wrote:
>>>> On Mon, Aug 7, 2017 at 4:27 AM, Vivek Gautam
>>>> <vivek.gautam@codeaurora.org> wrote:
>>>>> On Thu, Jul 13, 2017 at 5:20 PM, Rob Clark<robdclark@gmail.com> wrote:
>>>>>> On Thu, Jul 13, 2017 at 1:35 AM, Sricharan R<sricharan@codeaurora.org> wrote:
>>>>>>> Hi Vivek,
>>>>>>>
>>>>>>> On 7/13/2017 10:43 AM, Vivek Gautam wrote:
>>>>>>>> Hi Stephen,
>>>>>>>>
>>>>>>>>
>>>>>>>> On 07/13/2017 04:24 AM, Stephen Boyd wrote:
>>>>>>>>> On 07/06, Vivek Gautam wrote:
>>>>>>>>>> @@ -1231,12 +1237,18 @@ static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
>>>>>>>>>> static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
>>>>>>>>>> size_t size)
>>>>>>>>>> {
>>>>>>>>>> - struct io_pgtable_ops *ops = to_smmu_domain(domain)->pgtbl_ops;
>>>>>>>>>> + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
>>>>>>>>>> + struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops;
>>>>>>>>>> + size_t ret;
>>>>>>>>>> if (!ops)
>>>>>>>>>> return 0;
>>>>>>>>>> - return ops->unmap(ops, iova, size);
>>>>>>>>>> + pm_runtime_get_sync(smmu_domain->smmu->dev);
>>>>>>>>> Can these map/unmap ops be called from an atomic context? I seem
>>>>>>>>> to recall that being a problem before.
>>>>>>>> That's something which was dropped in the following patch merged in master:
>>>>>>>> 523d7423e21b iommu/arm-smmu: Remove io-pgtable spinlock
>>>>>>>>
>>>>>>>> Looks like we don't need locks here anymore?
>>>>>>> Apart from the locking, wonder why a explicit pm_runtime is needed
>>>>>>> from unmap. Somehow looks like some path in the master using that
>>>>>>> should have enabled the pm ?
>>>>>>>
>>>>>> Yes, there are a bunch of scenarios where unmap can happen with
>>>>>> disabled master (but not in atomic context).
>>>>> I would like to understand whether there is a situation where an unmap is
>>>>> called in atomic context without an enabled master?
>>>>>
>>>>> Let's say we have the case where all the unmap calls in atomic context happen
>>>>> only from the master's context (in which case the device link should
>>>>> take care of
>>>>> the pm state of smmu), and the only unmap that happen in non-atomic context
>>>>> is the one with master disabled. In such a case doesn it make sense to
>>>>> distinguish
>>>>> the atomic/non-atomic context and add pm_runtime_get_sync()/put_sync() only
>>>>> for the non-atomic context since that would be the one with master disabled.
>>>>>
>>>> At least drm/msm needs to hold obj->lock (a mutex) in unmap, so it
>>>> won't unmap anything in atomic ctx (but it can unmap w/ master
>>>> disabled). I can't really comment about other non-gpu drivers. It
>>>> seems like a reasonable constraint that either master is enabled or
>>>> not in atomic ctx.
>>>>
>>>> Currently we actually wrap unmap w/ pm_runtime_get/put_sync(), but I'd
>>>> like to drop that to avoid powering up the gpu.
>>> Since the deferring the TLB maintenance doesn't look like the best approach [1],
>>> how about if we try to power-up only the smmu from different client
>>> devices such as,
>>> GPU in the unmap path. Then we won't need to add pm_runtime_get/put() calls in
>>> arm_smmu_unmap().
>>>
>>> The client device can use something like - pm_runtime_get_supplier() since
>>> we already have the device link in place with this patch series. This should
>>> power-on the supplier (which is smmu) without turning on the consumer
>>> (such as GPU).
>>>
>>> pm_runtime_get_supplier() however is not exported at this moment.
>>> Will it be useful to export this API and use it in the drivers.
>>>
>> I'm not sure pm_runtime_get_supplier() is correct either. That
>> feels like we're relying on the GPU driver knowing the internal
>> details of how the device links are configured.
>>
> what does pm_runtime_get_supplier() do if IOMMU driver hasn't setup
> device-link?
It will be a no-op.
> If it is a no-op, then I guess the GPU driver calling
> pm_runtime_get_supplier() seems reasonable, and less annoying than
> having special cases in pm_resume path.. I don't feel too bad about
> having "just in case" get/put_supplier() calls in the unmap path.
>
> Also, presumably we still want to avoid powering up GPU even if we
> short circuit the firmware loading and rest of "booting up the GPU"..
> since presumably the GPU draws somewhat more power than the IOMMU..
> having the pm_resume/suspend path know about the diff between waking
> up / suspending the iommu and itself doesn't really feel less-bad than
> just doing "just in case" get/put_supplier() calls.
If it sounds okay, then i can send a patch that exports the
pm_runtime_get/put_suppliers() APIs.
Best regards
Vivek
> BR,
> -R
>
>> Is there some way to have the GPU driver know in its runtime PM
>> resume hook that it doesn't need to be powered on because it
>> isn't actively drawing anything or processing commands? I'm
>> thinking of the code calling pm_runtime_get() as proposed around
>> the IOMMU unmap path in the GPU driver and then having the
>> runtime PM resume hook in the GPU driver return some special
>> value to indicate that it didn't really resume because it didn't
>> need to and to treat the device as runtime suspended but not
>> return an error. Then the runtime PM core can keep track of that
>> and try to power the GPU on again when another pm_runtime_get()
>> is called on the GPU device.
>>
>> This keeps the consumer API the same, always pm_runtime_get(),
>> but leaves the device driver logic of what to do when the GPU
>> doesn't need to power on to the runtime PM hook where the driver
>> has all the information.
>>
>> --
>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
>> a Linux Foundation Collaborative Project
> --
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^ permalink raw reply
* [PATCH v4] ARM: dts: r8a7794: Add SMP support
From: Geert Uytterhoeven @ 2017-11-28 13:39 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Sergei Shtylyov,
Geert Uytterhoeven
From: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
Add the device tree node for the Advanced Power Management Unit (APMU).
Use the "enable-method" prop to point out that the APMU should be used
for the SMP support.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
Dependency 3fd45a136ff61bb5 ("ARM: shmobile: rcar-gen2: Make sure
CNTVOFF is initialized on CA7/15") is part of v4.15-rc1.
v4:
- Rebased against renesas-devel-20171127-v4.15-rc1,
v3:
- No changes,
v2:
- No changes.
---
arch/arm/boot/dts/r8a7794.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index ef7fb1d2c3a31a6e..2437598ca2f5b034 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -37,6 +37,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -66,6 +67,12 @@
};
};
+ apmu@e6151000 {
+ compatible = "renesas,r8a7794-apmu", "renesas,apmu";
+ reg = <0 0xe6151000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.7.4
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^ permalink raw reply related
* Re: [PATCH v2 2/4] dt-bindings: media: rcar_vin: add device tree support for r8a774[35]
From: Niklas Söderlund @ 2017-11-28 13:35 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Mauro Carvalho Chehab, Mark Rutland, Rob Herring, linux-media,
linux-renesas-soc, devicetree, Simon Horman, Geert Uytterhoeven,
Chris Paterson, Biju Das
In-Reply-To: <1510856571-30281-3-git-send-email-fabrizio.castro@bp.renesas.com>
On 2017-11-16 18:22:49 +0000, Fabrizio Castro wrote:
> Add compatible strings for r8a7743 and r8a7745. No driver change
> is needed as "renesas,rcar-gen2-vin" will activate the right code.
> However, it is good practice to document compatible strings for the
> specific SoC as this allows SoC specific changes to the driver if
> needed, in addition to document SoC support and therefore allow
> checkpatch.pl to validate compatible string values.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> ---
> v1->v2:
> * Fixed double "change" in changelog
>
> Documentation/devicetree/bindings/media/rcar_vin.txt | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt
> index 98931f5..ff9697e 100644
> --- a/Documentation/devicetree/bindings/media/rcar_vin.txt
> +++ b/Documentation/devicetree/bindings/media/rcar_vin.txt
> @@ -6,6 +6,8 @@ family of devices. The current blocks are always slaves and suppot one input
> channel which can be either RGB, YUYV or BT656.
>
> - compatible: Must be one or more of the following
> + - "renesas,vin-r8a7743" for the R8A7743 device
> + - "renesas,vin-r8a7745" for the R8A7745 device
> - "renesas,vin-r8a7778" for the R8A7778 device
> - "renesas,vin-r8a7779" for the R8A7779 device
> - "renesas,vin-r8a7790" for the R8A7790 device
> @@ -14,7 +16,8 @@ channel which can be either RGB, YUYV or BT656.
> - "renesas,vin-r8a7793" for the R8A7793 device
> - "renesas,vin-r8a7794" for the R8A7794 device
> - "renesas,vin-r8a7795" for the R8A7795 device
> - - "renesas,rcar-gen2-vin" for a generic R-Car Gen2 compatible device.
> + - "renesas,rcar-gen2-vin" for a generic R-Car Gen2 or RZ/G1 compatible
> + device.
> - "renesas,rcar-gen3-vin" for a generic R-Car Gen3 compatible device.
>
> When compatible with the generic version nodes must list the
> --
> 2.7.4
>
--
Regards,
Niklas Söderlund
^ permalink raw reply
* Re: [PATCH v2 1/4] dt-bindings: media: rcar_vin: Reverse SoC part number list
From: Niklas Söderlund @ 2017-11-28 13:34 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Mauro Carvalho Chehab, Mark Rutland, Rob Herring,
linux-media-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Simon Horman,
Geert Uytterhoeven, Chris Paterson, Biju Das
In-Reply-To: <1510856571-30281-2-git-send-email-fabrizio.castro-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
On 2017-11-16 18:22:48 +0000, Fabrizio Castro wrote:
> Change the sorting of the part numbers from descending to ascending to
> match with other documentation.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
> Reviewed-by: Biju Das <biju.das-kTT6dE0pTRh9uiUsa/gSgQ@public.gmane.org>
Acked-by: Niklas Söderlund <niklas.soderlund+renesas-1zkq55x86MTxsAP9Fp7wbw@public.gmane.org>
> ---
> v1->v2:
> * new patch triggered by Geert's comment, see the below link for details:
> https://www.mail-archive.com/linux-media-u79uwXL29TY76Z2rM5mHXA@public.gmane.org/msg121992.html
>
> Documentation/devicetree/bindings/media/rcar_vin.txt | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt
> index 6e4ef8c..98931f5 100644
> --- a/Documentation/devicetree/bindings/media/rcar_vin.txt
> +++ b/Documentation/devicetree/bindings/media/rcar_vin.txt
> @@ -6,14 +6,14 @@ family of devices. The current blocks are always slaves and suppot one input
> channel which can be either RGB, YUYV or BT656.
>
> - compatible: Must be one or more of the following
> - - "renesas,vin-r8a7795" for the R8A7795 device
> - - "renesas,vin-r8a7794" for the R8A7794 device
> - - "renesas,vin-r8a7793" for the R8A7793 device
> - - "renesas,vin-r8a7792" for the R8A7792 device
> - - "renesas,vin-r8a7791" for the R8A7791 device
> - - "renesas,vin-r8a7790" for the R8A7790 device
> - - "renesas,vin-r8a7779" for the R8A7779 device
> - "renesas,vin-r8a7778" for the R8A7778 device
> + - "renesas,vin-r8a7779" for the R8A7779 device
> + - "renesas,vin-r8a7790" for the R8A7790 device
> + - "renesas,vin-r8a7791" for the R8A7791 device
> + - "renesas,vin-r8a7792" for the R8A7792 device
> + - "renesas,vin-r8a7793" for the R8A7793 device
> + - "renesas,vin-r8a7794" for the R8A7794 device
> + - "renesas,vin-r8a7795" for the R8A7795 device
> - "renesas,rcar-gen2-vin" for a generic R-Car Gen2 compatible device.
> - "renesas,rcar-gen3-vin" for a generic R-Car Gen3 compatible device.
>
> --
> 2.7.4
>
--
Regards,
Niklas Söderlund
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^ permalink raw reply
* [PATCH 3/3] ARM64: dts: meson-axg: add the SPICC controller
From: Yixun Lan @ 2017-11-28 13:29 UTC (permalink / raw)
To: Kevin Hilman, devicetree
Cc: Mark Brown, linux-spi, Neil Armstrong, Jerome Brunet, Rob Herring,
Mark Rutland, Carlo Caione, Yixun Lan, Sunny Luo, linux-amlogic,
linux-arm-kernel, linux-kernel
In-Reply-To: <20171128132926.19051-1-yixun.lan@amlogic.com>
From: Sunny Luo <sunny.luo@amlogic.com>
Add DT info for the SPICC controller which found in
the Amlogic's Meson-AXG SoC.
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 92 ++++++++++++++++++++++++++++++
1 file changed, 92 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index fe3878f7718c..021b929d8d6e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -208,6 +208,28 @@
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
+
+ spicc_a: spi@13000 {
+ compatible = "amlogic,meson-axg-spicc";
+ reg = <0x0 0x13000 0x0 0x3c>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLKID_SPICC0>;
+ clock-names = "core";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spicc_b: spi@15000 {
+ compatible = "amlogic,meson-axg-spicc";
+ reg = <0x0 0x15000 0x0 0x3c>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLKID_SPICC1>;
+ clock-names = "core";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
gic: interrupt-controller@ffc01000 {
@@ -470,6 +492,76 @@
function = "pwm_d";
};
};
+
+ spi_a_pins: spi_a {
+ mux {
+ groups = "spi_miso_a",
+ "spi_mosi_a",
+ "spi_clk_a";
+ function = "spi_a";
+ };
+ };
+
+ spi_ss0_a_pins: spi_ss0_a {
+ mux {
+ groups = "spi_ss0_a";
+ function = "spi_a";
+ };
+ };
+
+ spi_ss1_a_pins: spi_ss1_a {
+ mux {
+ groups = "spi_ss1_a";
+ function = "spi_a";
+ };
+ };
+
+ spi_ss2_a_pins: spi_ss2_a {
+ mux {
+ groups = "spi_ss2_a";
+ function = "spi_a";
+ };
+ };
+
+
+ spi_b_a_pins: spi_b_a {
+ mux {
+ groups = "spi_miso_b_a",
+ "spi_mosi_b_a",
+ "spi_clk_b_a";
+ function = "spi_b";
+ };
+ };
+
+ spi_ss0_b_a_pins: spi_ss0_b_a {
+ mux {
+ groups = "spi_ss0_b_a";
+ function = "spi_b";
+ };
+ };
+
+ spi_ss1_b_pins: spi_ss1_b {
+ mux {
+ groups = "spi_ss1_b";
+ function = "spi_b";
+ };
+ };
+
+ spi_b_x_pins: spi_b_x {
+ mux {
+ groups = "spi_miso_b_x",
+ "spi_mosi_b_x",
+ "spi_clk_b_x";
+ function = "spi_b";
+ };
+ };
+
+ spi_ss0_b_x_pins: spi_ss0_b_x {
+ mux {
+ groups = "spi_ss0_b_x";
+ function = "spi_b";
+ };
+ };
};
};
--
2.15.0
^ permalink raw reply related
* [PATCH 2/3] spi: meson-axg: add SPICC driver support
From: Yixun Lan @ 2017-11-28 13:29 UTC (permalink / raw)
To: Kevin Hilman, devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Mark Brown, linux-spi-u79uwXL29TY76Z2rM5mHXA, Neil Armstrong,
Jerome Brunet, Rob Herring, Mark Rutland, Carlo Caione, Yixun Lan,
Sunny Luo, linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171128132926.19051-1-yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>
From: Sunny Luo <sunny.luo-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>
Add new compatible string to support SPICC controller which
found at Amlogic Meson-AXG SoC. This is aiming at adding
a couple of enhanced feature patches.
Signed-off-by: Sunny Luo <sunny.luo-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Yixun Lan <yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>
---
drivers/spi/spi-meson-spicc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index 7f8429635502..5c82910e3480 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -599,6 +599,7 @@ static int meson_spicc_remove(struct platform_device *pdev)
static const struct of_device_id meson_spicc_of_match[] = {
{ .compatible = "amlogic,meson-gx-spicc", },
+ { .compatible = "amlogic,meson-axg-spicc", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
--
2.15.0
--
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^ permalink raw reply related
* [PATCH 1/3] dt-bindings: spicc: update compatible string for the Meson-AXG
From: Yixun Lan @ 2017-11-28 13:29 UTC (permalink / raw)
To: Kevin Hilman, devicetree
Cc: Mark Brown, linux-spi, Neil Armstrong, Jerome Brunet, Rob Herring,
Mark Rutland, Carlo Caione, Yixun Lan, Sunny Luo, linux-amlogic,
linux-arm-kernel, linux-kernel
In-Reply-To: <20171128132926.19051-1-yixun.lan@amlogic.com>
From: Sunny Luo <sunny.luo@amlogic.com>
Update the compatbile string to support Meson-AXG SoCs.
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
Documentation/devicetree/bindings/spi/spi-meson.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-meson.txt b/Documentation/devicetree/bindings/spi/spi-meson.txt
index 825c39cae74a..b7f5e86fed22 100644
--- a/Documentation/devicetree/bindings/spi/spi-meson.txt
+++ b/Documentation/devicetree/bindings/spi/spi-meson.txt
@@ -27,7 +27,9 @@ The Meson SPICC is generic SPI controller for general purpose Full-Duplex
communications with dedicated 16 words RX/TX PIO FIFOs.
Required properties:
- - compatible: should be "amlogic,meson-gx-spicc" on Amlogic GX SoCs.
+ - compatible: should be:
+ "amlogic,meson-gx-spicc" on Amlogic GX and compatible SoCs.
+ "amlogic,meson-axg-spicc" on Amlogic AXG and compatible SoCs
- reg: physical base address and length of the controller registers
- interrupts: The interrupt specifier
- clock-names: Must contain "core"
--
2.15.0
^ permalink raw reply related
* [PATCH 0/3] spicc: meson-axg: add SPICC controller
From: Yixun Lan @ 2017-11-28 13:29 UTC (permalink / raw)
To: Kevin Hilman, devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Mark Brown, linux-spi-u79uwXL29TY76Z2rM5mHXA, Neil Armstrong,
Jerome Brunet, Rob Herring, Mark Rutland, Carlo Caione, Yixun Lan,
Sunny Luo, linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Add the SPICC controller driver to the Amlogic's Meson-AXG SoC.
The new compatible string introduced here is aiming for adding
a few new features which found at the Meson-AXG platform.
Sunny Luo (3):
dt-bindings: spicc: update compatible string for the Meson-AXG
spi: meson-axg: add SPICC driver support
ARM64: dts: meson-axg: add the SPICC controller
.../devicetree/bindings/spi/spi-meson.txt | 4 +-
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 92 ++++++++++++++++++++++
drivers/spi/spi-meson-spicc.c | 1 +
3 files changed, 96 insertions(+), 1 deletion(-)
--
2.15.0
--
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^ permalink raw reply
* Re: [PATCH v2 5/5] of/fdt: only store the device node basename in full_name
From: Rob Herring @ 2017-11-28 13:26 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Michael Ellerman,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Frank Rowand, Benjamin Herrenschmidt, Paul Mackerras,
David Laight
In-Reply-To: <CAMuHMdU-qQWmDi=V-G=r=poQf-F9hqL2SmoKi+SZyUwEj5vBGw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Tue, Nov 28, 2017 at 7:13 AM, Geert Uytterhoeven
<geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org> wrote:
> Hi Rob,
>
> On Mon, Aug 21, 2017 at 5:16 PM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
>> With dependencies on a statically allocated full path name converted to
>> use %pOF format specifier, we can store just the basename of node, and
>> the unflattening of the FDT can be simplified.
>>
>> This commit will affect the remaining users of full_name. After
>> analyzing these users, the remaining cases should only change some print
>> messages. The main users of full_name are providing a name for struct
>> resource. The resource names shouldn't be important other than providing
>> /proc/iomem names.
>
> I guess the plan is to get rid in a subsequent step of all calls to kbasename()
> on a full name, which is now futile?
No. Sparc (PDT) is still the full path and I don't plan to change that.
Rob
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^ permalink raw reply
* Re: [PATCH v2 5/5] of/fdt: only store the device node basename in full_name
From: Geert Uytterhoeven @ 2017-11-28 13:13 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Michael Ellerman,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Frank Rowand, Benjamin Herrenschmidt, Paul Mackerras,
David Laight
In-Reply-To: <20170821151651.25096-6-robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Hi Rob,
On Mon, Aug 21, 2017 at 5:16 PM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> With dependencies on a statically allocated full path name converted to
> use %pOF format specifier, we can store just the basename of node, and
> the unflattening of the FDT can be simplified.
>
> This commit will affect the remaining users of full_name. After
> analyzing these users, the remaining cases should only change some print
> messages. The main users of full_name are providing a name for struct
> resource. The resource names shouldn't be important other than providing
> /proc/iomem names.
I guess the plan is to get rid in a subsequent step of all calls to kbasename()
on a full name, which is now futile?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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^ permalink raw reply
* Re: [PATCH v4 0/4] fix the clock setting for SAR ADC
From: Yixun Lan @ 2017-11-28 13:11 UTC (permalink / raw)
To: Jonathan Cameron, Martin Blumenstingl
Cc: yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Neil Armstrong,
linux-iio-u79uwXL29TY76Z2rM5mHXA, Stephen Boyd, Michael Turquette,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Xingyu Chen,
Kevin Hilman, Carlo Caione,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA, Jonathan Cameron, Jerome Brunet
In-Reply-To: <20171111003737.000038f0-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
On 11/11/17 08:37, Jonathan Cameron wrote:
> On Tue, 7 Nov 2017 22:36:00 +0100
> Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> wrote:
>
>> Hi Yixun,
>>
>> On Tue, Nov 7, 2017 at 3:09 PM, Yixun Lan <yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org> wrote:
>>> patch [1/4]:
>>> Fix wrong SARADC/SANA clock gate bit in Meson-GXBB/GXL,
>>> the published datasheets[4] also has wrong description about this.
>>> This patch should be explicitly merged *before* other patches.
>>>
>>> patch [2-4/4]:
>>> Drop the "sana" clock from SAR ADC module,
>> I agree with Jerome that patch 2/4 should be applied last.
>
> Let me know when I should take this.
>
> Thanks,
>
> Jonathan
>
>> when I wrote the driver I couldn't get it to work on my GXBB board
>> (which unfortunately has died since then) because the clocks were
>> disabled (they weren't enabled by the bootloader). people who are
>> using an old .dtb would get the same problem again until the clock
>> driver is merged
>>
>>> From the hardware perspective, the SAR ADC module doesn't
>>> require "sana" clock to wrok. This should apply to all SoC,
>>> including meson6,8, GXBB, GXL..
>> thank you for clarifying this!
>>
>>> Note: the whole patchset series has been tested at GXL-P212 board,
>>> we haven't got any meson6,8 board to test, so I would appreciate
>>> if someone (Martin?) could help to confirm it works there.
>> I can test this on a Meson8b and a Meson8m2 board on the weekend -
>> I'll let you know about the results
>>
>>
>> Regards
>> Martin
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
>> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
>
> _______________________________________________
> linux-amlogic mailing list
> linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic
>
> .
>
Hi Jonathan Cameron & Kevin Hilman:
since the clk part patch has been applied[1], can we proceed with others?
to Jonathan:
I think the iio part(patch [2/4]) should be merged via your iio tree?
see [2]
to Kevin:
could you take the DTS part? see [3], and the patch [4/4] has a rework
version, see [4], to separate dt64 vs dt32 device tree.
[1]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005472.html
[2]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005264.html
[3]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005265.html
[4]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005304.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005305.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005306.html
Yixun
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^ permalink raw reply
* [PATCH] media: i2c: adv748x: Restore full DT paths in kernel messages
From: Geert Uytterhoeven @ 2017-11-28 13:01 UTC (permalink / raw)
To: Kieran Bingham, Mauro Carvalho Chehab, Rob Herring
Cc: linux-media, devicetree, linux-renesas-soc, linux-kernel,
Geert Uytterhoeven
As of_node_full_name() now returns only the basename, the endpoint
information printed became useless:
adv748x 4-0070: Endpoint endpoint on port 7
adv748x 4-0070: Endpoint endpoint on port 8
adv748x 4-0070: Endpoint endpoint on port 10
adv748x 4-0070: Endpoint endpoint on port 11
Restore the old behavior by using "%pOF" instead:
adv748x 4-0070: Endpoint /soc/i2c@e66d8000/video-receiver@70/port@7/endpoint on port 7
adv748x 4-0070: Endpoint /soc/i2c@e66d8000/video-receiver@70/port@8/endpoint on port 8
adv748x 4-0070: Endpoint /soc/i2c@e66d8000/video-receiver@70/port@10/endpoint on port 10
adv748x 4-0070: Endpoint /soc/i2c@e66d8000/video-receiver@70/port@11/endpoint on port 11
Fixes: a7e4cfb0a7ca4773 ("of/fdt: only store the device node basename in full_name")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/media/i2c/adv748x/adv748x-core.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/media/i2c/adv748x/adv748x-core.c b/drivers/media/i2c/adv748x/adv748x-core.c
index 5ee14f2c27478e3a..c1001db6a172e256 100644
--- a/drivers/media/i2c/adv748x/adv748x-core.c
+++ b/drivers/media/i2c/adv748x/adv748x-core.c
@@ -646,14 +646,12 @@ static int adv748x_parse_dt(struct adv748x_state *state)
for_each_endpoint_of_node(state->dev->of_node, ep_np) {
of_graph_parse_endpoint(ep_np, &ep);
- adv_info(state, "Endpoint %s on port %d",
- of_node_full_name(ep.local_node),
- ep.port);
+ adv_info(state, "Endpoint %pOF on port %d", ep.local_node,
+ ep.port);
if (ep.port >= ADV748X_PORT_MAX) {
- adv_err(state, "Invalid endpoint %s on port %d",
- of_node_full_name(ep.local_node),
- ep.port);
+ adv_err(state, "Invalid endpoint %pOF on port %d",
+ ep.local_node, ep.port);
continue;
}
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v3 2/2] leds: lm3692x: Introduce LM3692x dual string driver
From: Dan Murphy @ 2017-11-28 12:53 UTC (permalink / raw)
To: Jacek Anaszewski, robh+dt, mark.rutland, rpurdie, pavel
Cc: devicetree, linux-kernel, linux-leds
In-Reply-To: <493b722a-a295-26a6-6395-85caf01879e6@gmail.com>
Jacek
Thanks
On 11/18/2017 08:19 AM, Jacek Anaszewski wrote:
> Hi Dan,
>
> Please find my comments below.
>
> On 11/15/2017 08:42 PM, Dan Murphy wrote:
>> Introducing the LM3692x Dual-String white LED driver.
>>
>> Data sheet is located
>> http://www.ti.com/lit/ds/snvsa29/snvsa29.pdf
>>
>> Signed-off-by: Dan Murphy <dmurphy@ti.com>
>> ---
>>
>> v3 - Add missing Makefile and Kconfig from v1 and v2 - https://patchwork.kernel.org/patch/10060075/
>>
>> v2 - Added data sheet link, fixed linuxdoc format, returned on failure in init
>> routine, return on fault_check failure, updated brightness calculation and
>> fixed capitalization issue - https://patchwork.kernel.org/patch/10056675/
>>
>> drivers/leds/Kconfig | 7 +
>> drivers/leds/Makefile | 1 +
>> drivers/leds/leds-lm3692x.c | 390 ++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 398 insertions(+)
>> create mode 100644 drivers/leds/leds-lm3692x.c
>>
>> diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
>> index 318a28fd58fe..1363e77a7d5f 100644
>> --- a/drivers/leds/Kconfig
>> +++ b/drivers/leds/Kconfig
>> @@ -137,6 +137,13 @@ config LEDS_LM3642
>> converter plus 1.5A constant current driver for a high-current
>> white LED.
>>
>> +config LEDS_LM3692X
>> + tristate "LED support for LM3692x Chips"
>> + depends on LEDS_CLASS && I2C
>> + select REGMAP_I2C
>> + help
>> + This option enables support for the TI LM3692x family
>> + of LED drivers.
>>
>> config LEDS_LOCOMO
>> tristate "LED Support for Locomo device"
>> diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
>> index a2a6b5a4f86d..987884a5b9a5 100644
>> --- a/drivers/leds/Makefile
>> +++ b/drivers/leds/Makefile
>> @@ -74,6 +74,7 @@ obj-$(CONFIG_LEDS_PM8058) += leds-pm8058.o
>> obj-$(CONFIG_LEDS_MLXCPLD) += leds-mlxcpld.o
>> obj-$(CONFIG_LEDS_NIC78BX) += leds-nic78bx.o
>> obj-$(CONFIG_LEDS_MT6323) += leds-mt6323.o
>> +obj-$(CONFIG_LEDS_LM3692X) += leds-lm3692x.o
>>
>> # LED SPI Drivers
>> obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o
>> diff --git a/drivers/leds/leds-lm3692x.c b/drivers/leds/leds-lm3692x.c
>> new file mode 100644
>> index 000000000000..9fa7f5a20466
>> --- /dev/null
>> +++ b/drivers/leds/leds-lm3692x.c
>> @@ -0,0 +1,390 @@
>> +/*
>> + * TI lm3692x LED Driver
>> + *
>> + * Copyright (C) 2017 Texas Instruments
>> + *
>> + * Author: Dan Murphy <dmurphy@ti.com>
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>> + * version 2 as published by the Free Software Foundation.
>> + *
>> + * Data sheet is located
>> + * http://www.ti.com/lit/ds/snvsa29/snvsa29.pdf
>> + */
>> +
>> +#include <linux/i2c.h>
>> +#include <linux/init.h>
>> +#include <linux/leds.h>
>> +#include <linux/regmap.h>
>> +#include <linux/regulator/consumer.h>
>> +#include <linux/module.h>
>> +#include <linux/mutex.h>
>> +#include <linux/of.h>
>> +#include <linux/of_gpio.h>
>> +#include <linux/gpio/consumer.h>
>> +#include <linux/slab.h>
>> +
>> +#define LM3692X_LED_NAME "lm3692x_led"
>> +
>> +#define LM3692X_REV 0x0
>> +#define LM3692X_RESET 0x1
>> +#define LM3692X_EN 0x10
>> +#define LM3692X_BRT_CTRL 0x11
>> +#define LM3692X_PWM_CTRL 0x12
>> +#define LM3692X_BOOST_CTRL 0x13
>> +#define LM3692X_AUTO_FREQ_HI 0x15
>> +#define LM3692X_AUTO_FREQ_LO 0x16
>> +#define LM3692X_BL_ADJ_THRESH 0x17
>> +#define LM3692X_BRT_LSB 0x18
>> +#define LM3692X_BRT_MSB 0x19
>> +#define LM3692X_FAULT_CTRL 0x1e
>> +#define LM3692X_FAULT_FLAGS 0x1f
>> +
>> +#define LM3692X_SW_RESET BIT(0)
>> +#define LM3692X_DEVICE_EN BIT(0)
>> +#define LM3692X_LED1_EN BIT(1)
>> +#define LM3692X_LED2_EN BIT(2)
>> +
>> +/* Brightness Control Bits */
>> +#define LM3692X_BL_ADJ_POL BIT(0)
>> +#define LM3692X_RAMP_RATE_125us 0x00
>> +#define LM3692X_RAMP_RATE_250us BIT(1)
>> +#define LM3692X_RAMP_RATE_500us BIT(2)
>> +#define LM3692X_RAMP_RATE_1ms (BIT(1) | BIT(2))
>> +#define LM3692X_RAMP_RATE_2ms BIT(3)
>> +#define LM3692X_RAMP_RATE_4ms (BIT(3) | BIT(1))
>> +#define LM3692X_RAMP_RATE_8ms (BIT(2) | BIT(3))
>> +#define LM3692X_RAMP_RATE_16ms (BIT(1) | BIT(2) | BIT(3))
>> +#define LM3692X_RAMP_EN BIT(4)
>> +#define LM3692X_BRHT_MODE_REG 0x00
>> +#define LM3692X_BRHT_MODE_PWM BIT(5)
>> +#define LM3692X_BRHT_MODE_MULTI_RAMP BIT(6)
>> +#define LM3692X_BRHT_MODE_RAMP_MULTI (BIT(5) | BIT(6))
>> +#define LM3692X_MAP_MODE_EXP BIT(7)
>> +
>> +/* PWM Register Bits */
>> +#define LM3692X_PWM_FILTER_100 BIT(0)
>> +#define LM3692X_PWM_FILTER_150 BIT(1)
>> +#define LM3692X_PWM_FILTER_200 (BIT(0) | BIT(1))
>> +#define LM3692X_PWM_HYSTER_1LSB BIT(2)
>> +#define LM3692X_PWM_HYSTER_2LSB BIT(3)
>> +#define LM3692X_PWM_HYSTER_3LSB (BIT(3) | BIT(2))
>> +#define LM3692X_PWM_HYSTER_4LSB BIT(4)
>> +#define LM3692X_PWM_HYSTER_5LSB (BIT(4) | BIT(2))
>> +#define LM3692X_PWM_HYSTER_6LSB (BIT(4) | BIT(3))
>> +#define LM3692X_PWM_POLARITY BIT(5)
>> +#define LM3692X_PWM_SAMP_4MHZ BIT(6)
>> +#define LM3692X_PWM_SAMP_24MHZ BIT(7)
>> +
>> +/* Boost Control Bits */
>> +#define LM3692X_OCP_PROT_1A BIT(0)
>> +#define LM3692X_OCP_PROT_1_25A BIT(1)
>> +#define LM3692X_OCP_PROT_1_5A (BIT(0) | BIT(1))
>> +#define LM3692X_OVP_21V BIT(2)
>> +#define LM3692X_OVP_25V BIT(3)
>> +#define LM3692X_OVP_29V (BIT(2) | BIT(3))
>> +#define LM3692X_MIN_IND_22UH BIT(4)
>> +#define LM3692X_BOOST_SW_1MHZ BIT(5)
>> +#define LM3692X_BOOST_SW_NO_SHIFT BIT(6)
>> +
>> +/* Fault Control Bits */
>> +#define LM3692X_FAULT_CTRL_OVP BIT(0)
>> +#define LM3692X_FAULT_CTRL_OCP BIT(1)
>> +#define LM3692X_FAULT_CTRL_TSD BIT(2)
>> +#define LM3692X_FAULT_CTRL_OPEN BIT(3)
>> +
>> +/* Fault Flag Bits */
>> +#define LM3692X_FAULT_FLAG_OVP BIT(0)
>> +#define LM3692X_FAULT_FLAG_OCP BIT(1)
>> +#define LM3692X_FAULT_FLAG_TSD BIT(2)
>> +#define LM3692X_FAULT_FLAG_SHRT BIT(3)
>> +#define LM3692X_FAULT_FLAG_OPEN BIT(4)
>> +
>> +/**
>> + * struct lm3692x_led -
>> + * @lock - Lock for reading/writing the device
>> + * @client - Pointer to the I2C client
>> + * @led_dev - led class device pointer
>> + * @regmap - Devices register map
>> + * @enable_gpio - VDDIO/EN gpio to enable communication interface
>> + * @regulator - LED supply regulator pointer
>> + * @label - LED label
>> + */
>> +struct lm3692x_led {
>> + struct mutex lock;
>> + struct i2c_client *client;
>> + struct led_classdev led_dev;
>> + struct regmap *regmap;
>> + struct gpio_desc *enable_gpio;
>> + struct regulator *regulator;
>> + const char *label;
>> +};
>> +
>> +static const struct reg_default lm3692x_reg_defs[] = {
>> + {LM3692X_EN, 0xf},
>> + {LM3692X_BRT_CTRL, 0x61},
>> + {LM3692X_PWM_CTRL, 0x73},
>> + {LM3692X_BOOST_CTRL, 0x6f},
>> + {LM3692X_AUTO_FREQ_HI, 0x0},
>> + {LM3692X_AUTO_FREQ_LO, 0x0},
>> + {LM3692X_BL_ADJ_THRESH, 0x0},
>> + {LM3692X_BRT_LSB, 0x7},
>> + {LM3692X_BRT_MSB, 0xff},
>> + {LM3692X_FAULT_CTRL, 0x7},
>> +};
>> +
>> +static const struct regmap_config lm3692x_regmap_config = {
>> + .reg_bits = 8,
>> + .val_bits = 8,
>> +
>> + .max_register = LM3692X_FAULT_FLAGS,
>> + .reg_defaults = lm3692x_reg_defs,
>> + .num_reg_defaults = ARRAY_SIZE(lm3692x_reg_defs),
>> + .cache_type = REGCACHE_RBTREE,
>> +};
>> +
>> +static int lm3692x_fault_check(struct lm3692x_led *led)
>> +{
>> + int ret, fault;
>> + unsigned int read_buf;
>> +
>> + ret = regmap_read(led->regmap, LM3692X_FAULT_FLAGS, &read_buf);
>> + if (ret)
>> + return ret;
>> +
>> + fault = read_buf;
>> +
>> + if (fault)
>> + dev_err(&led->client->dev, "Detected a fault 0x%X\n",
>> + fault);
>> +
>> + return ret;
>> +}
>> +
>> +static int lm3692x_brightness_set(struct led_classdev *led_cdev,
>> + enum led_brightness brt_val)
>> +{
>> + struct lm3692x_led *led =
>> + container_of(led_cdev, struct lm3692x_led, led_dev);
>> + int ret;
>> + int led_brightness_lsb = (brt_val >> 5);
>> +
>> + mutex_lock(&led->lock);
>> +
>> + ret = lm3692x_fault_check(led);
>> + if (ret) {
>> + dev_err(&led->client->dev, "Cannot read/clear faults\n");
>> + goto out;
>> + }
>> +
>> + ret = regmap_write(led->regmap, LM3692X_BRT_MSB, brt_val);
>> + if (ret) {
>> + dev_err(&led->client->dev, "Cannot write MSB\n");
>> + goto out;
>> + }
>> +
>> + ret = regmap_write(led->regmap, LM3692X_BRT_LSB, led_brightness_lsb);
>> + if (ret) {
>> + dev_err(&led->client->dev, "Cannot write LSB\n");
>> + goto out;
>> + }
>> +out:
>> + mutex_unlock(&led->lock);
>> + return ret;
>> +}
>> +
>> +static int lm3692x_init(struct lm3692x_led *led)
>> +{
>> + int ret;
>> +
>> + if (led->regulator) {
>> + ret = regulator_enable(led->regulator);
>> + if (ret)
>> + dev_err(&led->client->dev,
>> + "Failed to enable regulator\n");
>> + goto out;
>> + }
>> +
>> + if (led->enable_gpio)
>> + gpiod_direction_output(led->enable_gpio, 1);
>> +
>> + ret = lm3692x_fault_check(led);
>> + if (ret) {
>> + dev_err(&led->client->dev, "Cannot read/clear faults\n");
>> + goto out;
>> + }
>> +
>> + ret = regmap_write(led->regmap, LM3692X_BRT_CTRL, 0x00);
>> + if (ret) {
>> + dev_err(&led->client->dev, "Fail writing BRT CTRL\n");
>> + goto out;
>> + }
>> +
>> + /*
>> + * For glitch free operation, the following data should
>> + * only be written while device enable bit is 0
>> + * per Section 7.5.14 of the data sheet
>> + */
>> + ret = regmap_write(led->regmap, LM3692X_PWM_CTRL,
>> + LM3692X_PWM_FILTER_100 | LM3692X_PWM_SAMP_24MHZ);
>> + if (ret) {
>> + dev_err(&led->client->dev, "Failed programming PWM CTRL\n");
>> + goto out;
>> + }
>> +
>> + ret = regmap_write(led->regmap, LM3692X_BOOST_CTRL,
>> + LM3692X_BRHT_MODE_RAMP_MULTI |
>> + LM3692X_BL_ADJ_POL |
>> + LM3692X_RAMP_RATE_250us);
>> + if (ret) {
>> + dev_err(&led->client->dev, "Failed programming BOOST CTRL\n");
>> + goto out;
>> + }
>> +
>> + ret = regmap_write(led->regmap, LM3692X_AUTO_FREQ_HI, 0x00);
>> + if (ret) {
>> + dev_err(&led->client->dev, "Failed programming AUTO HI FREQ\n");
>> + goto out;
>> + }
>> +
>> + ret = regmap_write(led->regmap, LM3692X_AUTO_FREQ_LO, 0x00);
>> + if (ret) {
>> + dev_err(&led->client->dev, "Failed programming AUTO LO FREQ\n");
>> + goto out;
>> + }
>> +
>> + ret = regmap_write(led->regmap, LM3692X_BL_ADJ_THRESH, 0x00);
>> + if (ret) {
>> + dev_err(&led->client->dev, "Failed programming BL Threshold\n");
>> + goto out;
>> + }
>> +
>> + ret = regmap_write(led->regmap, LM3692X_BRT_CTRL,
>> + LM3692X_BL_ADJ_POL | LM3692X_PWM_HYSTER_4LSB);
>> + if (ret)
>> + dev_err(&led->client->dev, "Failed programming BRT CTRL\n");
>> +
>> + return ret;
>> +out:
>> +
>> + if (led->enable_gpio)
>> + gpiod_direction_output(led->enable_gpio, 0);
>> +
>> + if (led->regulator) {
>> + ret = regulator_disable(led->regulator);
>> + if (ret)
>> + dev_err(&led->client->dev,
>> + "Failed to disable regulator\n");
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static int lm3692x_probe(struct i2c_client *client,
>> + const struct i2c_device_id *id)
>> +{
>> + int ret;
>> + struct lm3692x_led *led;
>> + struct device_node *np = client->dev.of_node;
>> +
>> + led = devm_kzalloc(&client->dev, sizeof(*led), GFP_KERNEL);
>> + if (!led)
>> + return -ENOMEM;
>> +
>> + if (client->dev.of_node) {
>
> We should fail in the opposite case.
OK
>
>> + ret = of_property_read_string(np, "label", &led->label);
>> + if (ret)
>> + led->label = LM3692X_LED_NAME;
>
> LED label should be taken from the child node name if label property is
> not present. See Documentation/devicetree/bindings/leds/common.txt.
>
> We have some mess in this area, but I'm going to sort it out soon
> (added you on CC to the related discussion).
>
> Generally LED class device name should be composed by the LED class
> driver by taking label and prefixing it with "[devicename]:" string.
OK
>
>> + }
>> +
>> + led->enable_gpio = devm_gpiod_get_optional(&client->dev,
>> + "enable", GPIOD_OUT_LOW);
>> + if (IS_ERR(led->enable_gpio)) {
>> + ret = PTR_ERR(led->enable_gpio);
>> + dev_err(&client->dev, "Failed to get enable gpio: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + led->regulator = devm_regulator_get(&client->dev, "vled");
>> + if (IS_ERR(led->regulator))
>> + led->regulator = NULL;
>> +
>> + led->client = client;
>> + led->led_dev.name = led->label;
>> + led->led_dev.max_brightness = LED_FULL;
>
> You can skip this line, it will be initialized to LED_FULL
> in of_led_classdev_register in this case.
OK
>
>
>> + led->led_dev.brightness_set_blocking = lm3692x_brightness_set;
>> +
>> + mutex_init(&led->lock);
>> +
>> + i2c_set_clientdata(client, led);
>> +
>> + led->regmap = devm_regmap_init_i2c(client, &lm3692x_regmap_config);
>> + if (IS_ERR(led->regmap)) {
>> + ret = PTR_ERR(led->regmap);
>> + dev_err(&client->dev, "Failed to allocate register map: %d\n",
>> + ret);
>> + return ret;
>> + }
>> +
>> + ret = lm3692x_init(led);
>> + if (ret)
>> + return ret;
>> +
>> + ret = led_classdev_register(&client->dev, &led->led_dev);
>
> Please use devm_* prefixed version.
OK
>
>> + if (ret) {
>> + dev_err(&client->dev, "led register err: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int lm3692x_remove(struct i2c_client *client)
>> +{
>> + struct lm3692x_led *led = i2c_get_clientdata(client);
>> + int ret;
>> +
>> + led_classdev_unregister(&led->led_dev);
>> +
>> + if (led->enable_gpio)
>> + gpiod_direction_output(led->enable_gpio, 0);
>> +
>> + if (led->regulator) {
>> + ret = regulator_disable(led->regulator);
>> + if (ret)
>> + dev_err(&led->client->dev,
>> + "Failed to disable regulator\n");
>> + }
>
> mutex_destroy(&led->lock)
OK
>
>> +
>> + return 0;
>> +}
>> +
>> +static const struct i2c_device_id lm3692x_id[] = {
>> + { "lm3692x", 0 },
>> + { }
>> +};
>> +MODULE_DEVICE_TABLE(i2c, lm3692x_id);
>> +
>> +#ifdef CONFIG_OF
>> +static const struct of_device_id of_lm3692x_leds_match[] = {
>> + { .compatible = "ti,lm3692x", },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, of_lm3692x_leds_match);
>> +#endif
>> +
>> +static struct i2c_driver lm3692x_driver = {
>> + .driver = {
>> + .name = "lm3692x",
>> + .of_match_table = of_match_ptr(of_lm3692x_leds_match),
>> + },
>> + .probe = lm3692x_probe,
>> + .remove = lm3692x_remove,
>> + .id_table = lm3692x_id,
>> +};
>> +module_i2c_driver(lm3692x_driver);
>> +
>> +MODULE_DESCRIPTION("Texas Instruments LM3692X LED driver");
>> +MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
>> +MODULE_LICENSE("GPL");
>
> According to your license info it should be "GPL v2"
>
OK
Dan
--
------------------
Dan Murphy
^ permalink raw reply
* [PATCH v3 3/3] arm64: dts: meson-axg: add clock DT info for Meson AXG SoC
From: Yixun Lan @ 2017-11-28 12:53 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Kevin Hilman
Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd,
Carlo Caione, Yixun Lan, Qiufang Dai, linux-amlogic, devicetree,
linux-clk, linux-arm-kernel, linux-kernel
In-Reply-To: <20171128125330.363-1-yixun.lan@amlogic.com>
From: Qiufang Dai <qiufang.dai@amlogic.com>
Try to add Hiubus DT info, and also enable clock DT info
for the Amlogic's Meson-AXG SoC.
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index b932a784b02a..36a2e98338a8 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/axg-clkc.h>
/ {
compatible = "amlogic,meson-axg";
@@ -148,6 +149,20 @@
#address-cells = <0>;
};
+ hiubus: hiubus@ff63c000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xff63c000 0x0 0x1c00>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
+
+ clkc: clock-controller@0 {
+ compatible = "amlogic,axg-clkc";
+ #clock-cells = <1>;
+ reg = <0x0 0x0 0x0 0x320>;
+ };
+ };
+
mailbox: mailbox@ff63dc00 {
compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
reg = <0 0xff63dc00 0 0x400>;
--
2.15.0
^ permalink raw reply related
* [PATCH v3 2/3] clk: meson-axg: add clock controller drivers
From: Yixun Lan @ 2017-11-28 12:53 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Kevin Hilman
Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd,
Carlo Caione, Yixun Lan, Qiufang Dai, linux-amlogic, devicetree,
linux-clk, linux-arm-kernel, linux-kernel
In-Reply-To: <20171128125330.363-1-yixun.lan@amlogic.com>
From: Qiufang Dai <qiufang.dai@amlogic.com>
Add clock controller drivers for Amlogic Meson-AXG SoC.
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
arch/arm64/Kconfig.platforms | 1 +
drivers/clk/meson/Kconfig | 8 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/axg.c | 948 +++++++++++++++++++++++++++++++++++
drivers/clk/meson/axg.h | 126 +++++
include/dt-bindings/clock/axg-clkc.h | 72 +++
6 files changed, 1156 insertions(+)
create mode 100644 drivers/clk/meson/axg.c
create mode 100644 drivers/clk/meson/axg.h
create mode 100644 include/dt-bindings/clock/axg-clkc.h
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 2401373565ff..fbedbd8f619a 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -105,6 +105,7 @@ config ARCH_MESON
select PINCTRL_MESON
select COMMON_CLK_AMLOGIC
select COMMON_CLK_GXBB
+ select COMMON_CLK_AXG
select MESON_IRQ_GPIO
help
This enables support for the Amlogic S905 SoCs.
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index d2d0174a6eca..7694302c70a4 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -19,3 +19,11 @@ config COMMON_CLK_GXBB
help
Support for the clock controller on AmLogic S905 devices, aka gxbb.
Say Y if you want peripherals and CPU frequency scaling to work.
+
+config COMMON_CLK_AXG
+ bool
+ depends on COMMON_CLK_AMLOGIC
+ select RESET_CONTROLLER
+ help
+ Support for the clock controller on AmLogic A113D devices, aka axg.
+ Say Y if you want peripherals and CPU frequency scaling to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index b139d41b25da..3c03ce583798 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-regmap.o gxbb-aoclk-32k.o
+obj-$(CONFIG_COMMON_CLK_AXG) += axg.o
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
new file mode 100644
index 000000000000..51c5b4062715
--- /dev/null
+++ b/drivers/clk/meson/axg.c
@@ -0,0 +1,948 @@
+/*
+ * AmLogic Meson-AXG Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette <mturquette@baylibre.com>
+ *
+ * Copyright (c) 2017 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+
+#include "clkc.h"
+#include "axg.h"
+
+static DEFINE_SPINLOCK(clk_lock);
+
+static const struct pll_rate_table sys_pll_rate_table[] = {
+ PLL_RATE(24000000, 56, 1, 2),
+ PLL_RATE(48000000, 64, 1, 2),
+ PLL_RATE(72000000, 72, 1, 2),
+ PLL_RATE(96000000, 64, 1, 2),
+ PLL_RATE(120000000, 80, 1, 2),
+ PLL_RATE(144000000, 96, 1, 2),
+ PLL_RATE(168000000, 56, 1, 1),
+ PLL_RATE(192000000, 64, 1, 1),
+ PLL_RATE(216000000, 72, 1, 1),
+ PLL_RATE(240000000, 80, 1, 1),
+ PLL_RATE(264000000, 88, 1, 1),
+ PLL_RATE(288000000, 96, 1, 1),
+ PLL_RATE(312000000, 52, 1, 2),
+ PLL_RATE(336000000, 56, 1, 2),
+ PLL_RATE(360000000, 60, 1, 2),
+ PLL_RATE(384000000, 64, 1, 2),
+ PLL_RATE(408000000, 68, 1, 2),
+ PLL_RATE(432000000, 72, 1, 2),
+ PLL_RATE(456000000, 76, 1, 2),
+ PLL_RATE(480000000, 80, 1, 2),
+ PLL_RATE(504000000, 84, 1, 2),
+ PLL_RATE(528000000, 88, 1, 2),
+ PLL_RATE(552000000, 92, 1, 2),
+ PLL_RATE(576000000, 96, 1, 2),
+ PLL_RATE(600000000, 50, 1, 1),
+ PLL_RATE(624000000, 52, 1, 1),
+ PLL_RATE(648000000, 54, 1, 1),
+ PLL_RATE(672000000, 56, 1, 1),
+ PLL_RATE(696000000, 58, 1, 1),
+ PLL_RATE(720000000, 60, 1, 1),
+ PLL_RATE(744000000, 62, 1, 1),
+ PLL_RATE(768000000, 64, 1, 1),
+ PLL_RATE(792000000, 66, 1, 1),
+ PLL_RATE(816000000, 68, 1, 1),
+ PLL_RATE(840000000, 70, 1, 1),
+ PLL_RATE(864000000, 72, 1, 1),
+ PLL_RATE(888000000, 74, 1, 1),
+ PLL_RATE(912000000, 76, 1, 1),
+ PLL_RATE(936000000, 78, 1, 1),
+ PLL_RATE(960000000, 80, 1, 1),
+ PLL_RATE(984000000, 82, 1, 1),
+ PLL_RATE(1008000000, 84, 1, 1),
+ PLL_RATE(1032000000, 86, 1, 1),
+ PLL_RATE(1056000000, 88, 1, 1),
+ PLL_RATE(1080000000, 90, 1, 1),
+ PLL_RATE(1104000000, 92, 1, 1),
+ PLL_RATE(1128000000, 94, 1, 1),
+ PLL_RATE(1152000000, 96, 1, 1),
+ PLL_RATE(1176000000, 98, 1, 1),
+ PLL_RATE(1200000000, 50, 1, 0),
+ PLL_RATE(1224000000, 51, 1, 0),
+ PLL_RATE(1248000000, 52, 1, 0),
+ PLL_RATE(1272000000, 53, 1, 0),
+ PLL_RATE(1296000000, 54, 1, 0),
+ PLL_RATE(1320000000, 55, 1, 0),
+ PLL_RATE(1344000000, 56, 1, 0),
+ PLL_RATE(1368000000, 57, 1, 0),
+ PLL_RATE(1392000000, 58, 1, 0),
+ PLL_RATE(1416000000, 59, 1, 0),
+ PLL_RATE(1440000000, 60, 1, 0),
+ PLL_RATE(1464000000, 61, 1, 0),
+ PLL_RATE(1488000000, 62, 1, 0),
+ PLL_RATE(1512000000, 63, 1, 0),
+ PLL_RATE(1536000000, 64, 1, 0),
+ PLL_RATE(1560000000, 65, 1, 0),
+ PLL_RATE(1584000000, 66, 1, 0),
+ PLL_RATE(1608000000, 67, 1, 0),
+ PLL_RATE(1632000000, 68, 1, 0),
+ PLL_RATE(1656000000, 68, 1, 0),
+ PLL_RATE(1680000000, 68, 1, 0),
+ PLL_RATE(1704000000, 68, 1, 0),
+ PLL_RATE(1728000000, 69, 1, 0),
+ PLL_RATE(1752000000, 69, 1, 0),
+ PLL_RATE(1776000000, 69, 1, 0),
+ PLL_RATE(1800000000, 69, 1, 0),
+ PLL_RATE(1824000000, 70, 1, 0),
+ PLL_RATE(1848000000, 70, 1, 0),
+ PLL_RATE(1872000000, 70, 1, 0),
+ PLL_RATE(1896000000, 70, 1, 0),
+ PLL_RATE(1920000000, 71, 1, 0),
+ PLL_RATE(1944000000, 71, 1, 0),
+ PLL_RATE(1968000000, 71, 1, 0),
+ PLL_RATE(1992000000, 71, 1, 0),
+ PLL_RATE(2016000000, 72, 1, 0),
+ PLL_RATE(2040000000, 72, 1, 0),
+ PLL_RATE(2064000000, 72, 1, 0),
+ PLL_RATE(2088000000, 72, 1, 0),
+ PLL_RATE(2112000000, 73, 1, 0),
+ { /* sentinel */ },
+};
+
+static struct meson_clk_pll axg_fixed_pll = {
+ .m = {
+ .reg_off = HHI_MPLL_CNTL,
+ .shift = 0,
+ .width = 9,
+ },
+ .n = {
+ .reg_off = HHI_MPLL_CNTL,
+ .shift = 9,
+ .width = 5,
+ },
+ .od = {
+ .reg_off = HHI_MPLL_CNTL,
+ .shift = 16,
+ .width = 2,
+ },
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll",
+ .ops = &meson_clk_pll_ro_ops,
+ .parent_names = (const char *[]){ "xtal" },
+ .num_parents = 1,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
+static struct meson_clk_pll axg_sys_pll = {
+ .m = {
+ .reg_off = HHI_SYS_PLL_CNTL,
+ .shift = 0,
+ .width = 9,
+ },
+ .n = {
+ .reg_off = HHI_SYS_PLL_CNTL,
+ .shift = 9,
+ .width = 5,
+ },
+ .od = {
+ .reg_off = HHI_SYS_PLL_CNTL,
+ .shift = 10,
+ .width = 2,
+ },
+ .rate_table = sys_pll_rate_table,
+ .rate_count = ARRAY_SIZE(sys_pll_rate_table),
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sys_pll",
+ .ops = &meson_clk_pll_ro_ops,
+ .parent_names = (const char *[]){ "xtal" },
+ .num_parents = 1,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
+static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
+ PLL_RATE(240000000, 40, 1, 2),
+ PLL_RATE(246000000, 41, 1, 2),
+ PLL_RATE(252000000, 42, 1, 2),
+ PLL_RATE(258000000, 43, 1, 2),
+ PLL_RATE(264000000, 44, 1, 2),
+ PLL_RATE(270000000, 45, 1, 2),
+ PLL_RATE(276000000, 46, 1, 2),
+ PLL_RATE(282000000, 47, 1, 2),
+ PLL_RATE(288000000, 48, 1, 2),
+ PLL_RATE(294000000, 49, 1, 2),
+ PLL_RATE(300000000, 50, 1, 2),
+ PLL_RATE(306000000, 51, 1, 2),
+ PLL_RATE(312000000, 52, 1, 2),
+ PLL_RATE(318000000, 53, 1, 2),
+ PLL_RATE(324000000, 54, 1, 2),
+ PLL_RATE(330000000, 55, 1, 2),
+ PLL_RATE(336000000, 56, 1, 2),
+ PLL_RATE(342000000, 57, 1, 2),
+ PLL_RATE(348000000, 58, 1, 2),
+ PLL_RATE(354000000, 59, 1, 2),
+ PLL_RATE(360000000, 60, 1, 2),
+ PLL_RATE(366000000, 61, 1, 2),
+ PLL_RATE(372000000, 62, 1, 2),
+ PLL_RATE(378000000, 63, 1, 2),
+ PLL_RATE(384000000, 64, 1, 2),
+ PLL_RATE(390000000, 65, 1, 3),
+ PLL_RATE(396000000, 66, 1, 3),
+ PLL_RATE(402000000, 67, 1, 3),
+ PLL_RATE(408000000, 68, 1, 3),
+ PLL_RATE(480000000, 40, 1, 1),
+ PLL_RATE(492000000, 41, 1, 1),
+ PLL_RATE(504000000, 42, 1, 1),
+ PLL_RATE(516000000, 43, 1, 1),
+ PLL_RATE(528000000, 44, 1, 1),
+ PLL_RATE(540000000, 45, 1, 1),
+ PLL_RATE(552000000, 46, 1, 1),
+ PLL_RATE(564000000, 47, 1, 1),
+ PLL_RATE(576000000, 48, 1, 1),
+ PLL_RATE(588000000, 49, 1, 1),
+ PLL_RATE(600000000, 50, 1, 1),
+ PLL_RATE(612000000, 51, 1, 1),
+ PLL_RATE(624000000, 52, 1, 1),
+ PLL_RATE(636000000, 53, 1, 1),
+ PLL_RATE(648000000, 54, 1, 1),
+ PLL_RATE(660000000, 55, 1, 1),
+ PLL_RATE(672000000, 56, 1, 1),
+ PLL_RATE(684000000, 57, 1, 1),
+ PLL_RATE(696000000, 58, 1, 1),
+ PLL_RATE(708000000, 59, 1, 1),
+ PLL_RATE(720000000, 60, 1, 1),
+ PLL_RATE(732000000, 61, 1, 1),
+ PLL_RATE(744000000, 62, 1, 1),
+ PLL_RATE(756000000, 63, 1, 1),
+ PLL_RATE(768000000, 64, 1, 1),
+ PLL_RATE(780000000, 65, 1, 1),
+ PLL_RATE(792000000, 66, 1, 1),
+ PLL_RATE(804000000, 67, 1, 1),
+ PLL_RATE(816000000, 68, 1, 1),
+ PLL_RATE(960000000, 40, 1, 0),
+ PLL_RATE(984000000, 41, 1, 0),
+ PLL_RATE(1008000000, 42, 1, 0),
+ PLL_RATE(1032000000, 43, 1, 0),
+ PLL_RATE(1056000000, 44, 1, 0),
+ PLL_RATE(1080000000, 45, 1, 0),
+ PLL_RATE(1104000000, 46, 1, 0),
+ PLL_RATE(1128000000, 47, 1, 0),
+ PLL_RATE(1152000000, 48, 1, 0),
+ PLL_RATE(1176000000, 49, 1, 0),
+ PLL_RATE(1200000000, 50, 1, 0),
+ PLL_RATE(1224000000, 51, 1, 0),
+ PLL_RATE(1248000000, 52, 1, 0),
+ PLL_RATE(1272000000, 53, 1, 0),
+ PLL_RATE(1296000000, 54, 1, 0),
+ PLL_RATE(1320000000, 55, 1, 0),
+ PLL_RATE(1344000000, 56, 1, 0),
+ PLL_RATE(1368000000, 57, 1, 0),
+ PLL_RATE(1392000000, 58, 1, 0),
+ PLL_RATE(1416000000, 59, 1, 0),
+ PLL_RATE(1440000000, 60, 1, 0),
+ PLL_RATE(1464000000, 61, 1, 0),
+ PLL_RATE(1488000000, 62, 1, 0),
+ PLL_RATE(1512000000, 63, 1, 0),
+ PLL_RATE(1536000000, 64, 1, 0),
+ PLL_RATE(1560000000, 65, 1, 0),
+ PLL_RATE(1584000000, 66, 1, 0),
+ PLL_RATE(1608000000, 67, 1, 0),
+ PLL_RATE(1632000000, 68, 1, 0),
+ { /* sentinel */ },
+};
+
+struct pll_params_table axg_gp0_params_table[] = {
+ PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250),
+ PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000),
+ PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be),
+ PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288),
+ PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d),
+ PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000),
+};
+
+static struct meson_clk_pll axg_gp0_pll = {
+ .m = {
+ .reg_off = HHI_GP0_PLL_CNTL,
+ .shift = 0,
+ .width = 9,
+ },
+ .n = {
+ .reg_off = HHI_GP0_PLL_CNTL,
+ .shift = 9,
+ .width = 5,
+ },
+ .od = {
+ .reg_off = HHI_GP0_PLL_CNTL,
+ .shift = 16,
+ .width = 2,
+ },
+ .params = {
+ .params_table = axg_gp0_params_table,
+ .params_count = ARRAY_SIZE(axg_gp0_params_table),
+ .no_init_reset = true,
+ .reset_lock_loop = true,
+ },
+ .rate_table = axg_gp0_pll_rate_table,
+ .rate_count = ARRAY_SIZE(axg_gp0_pll_rate_table),
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "gp0_pll",
+ .ops = &meson_clk_pll_ops,
+ .parent_names = (const char *[]){ "xtal" },
+ .num_parents = 1,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
+
+static struct clk_fixed_factor axg_fclk_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div2",
+ .ops = &clk_fixed_factor_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor axg_fclk_div3 = {
+ .mult = 1,
+ .div = 3,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div3",
+ .ops = &clk_fixed_factor_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor axg_fclk_div4 = {
+ .mult = 1,
+ .div = 4,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div4",
+ .ops = &clk_fixed_factor_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor axg_fclk_div5 = {
+ .mult = 1,
+ .div = 5,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div5",
+ .ops = &clk_fixed_factor_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor axg_fclk_div7 = {
+ .mult = 1,
+ .div = 7,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div7",
+ .ops = &clk_fixed_factor_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+static struct meson_clk_mpll axg_mpll0 = {
+ .sdm = {
+ .reg_off = HHI_MPLL_CNTL7,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = HHI_MPLL_CNTL7,
+ .shift = 15,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = HHI_MPLL_CNTL7,
+ .shift = 16,
+ .width = 9,
+ },
+ .en = {
+ .reg_off = HHI_MPLL_CNTL7,
+ .shift = 14,
+ .width = 1,
+ },
+ .ssen = {
+ .reg_off = HHI_MPLL_CNTL,
+ .shift = 25,
+ .width = 1,
+ },
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll0",
+ .ops = &meson_clk_mpll_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+static struct meson_clk_mpll axg_mpll1 = {
+ .sdm = {
+ .reg_off = HHI_MPLL_CNTL8,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = HHI_MPLL_CNTL8,
+ .shift = 15,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = HHI_MPLL_CNTL8,
+ .shift = 16,
+ .width = 9,
+ },
+ .en = {
+ .reg_off = HHI_MPLL_CNTL8,
+ .shift = 14,
+ .width = 1,
+ },
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll1",
+ .ops = &meson_clk_mpll_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+static struct meson_clk_mpll axg_mpll2 = {
+ .sdm = {
+ .reg_off = HHI_MPLL_CNTL9,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = HHI_MPLL_CNTL9,
+ .shift = 15,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = HHI_MPLL_CNTL9,
+ .shift = 16,
+ .width = 9,
+ },
+ .en = {
+ .reg_off = HHI_MPLL_CNTL9,
+ .shift = 14,
+ .width = 1,
+ },
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll2",
+ .ops = &meson_clk_mpll_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+static struct meson_clk_mpll axg_mpll3 = {
+ .sdm = {
+ .reg_off = HHI_MPLL3_CNTL0,
+ .shift = 12,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = HHI_MPLL3_CNTL0,
+ .shift = 11,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = HHI_MPLL3_CNTL0,
+ .shift = 2,
+ .width = 9,
+ },
+ .en = {
+ .reg_off = HHI_MPLL3_CNTL0,
+ .shift = 0,
+ .width = 1,
+ },
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll3",
+ .ops = &meson_clk_mpll_ops,
+ .parent_names = (const char *[]){ "fixed_pll" },
+ .num_parents = 1,
+ },
+};
+
+/*
+ * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers
+ * and should be modeled with their respective PLLs via the forthcoming
+ * coordinated clock rates feature
+ */
+static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
+static const char * const clk81_parent_names[] = {
+ "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
+ "fclk_div3", "fclk_div5"
+};
+
+static struct clk_mux axg_mpeg_clk_sel = {
+ .reg = (void *)HHI_MPEG_CLK_CNTL,
+ .mask = 0x7,
+ .shift = 12,
+ .flags = CLK_MUX_READ_ONLY,
+ .table = mux_table_clk81,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpeg_clk_sel",
+ .ops = &clk_mux_ro_ops,
+ /*
+ * bits 14:12 selects from 8 possible parents:
+ * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
+ * fclk_div4, fclk_div3, fclk_div5
+ */
+ .parent_names = clk81_parent_names,
+ .num_parents = ARRAY_SIZE(clk81_parent_names),
+ .flags = CLK_SET_RATE_NO_REPARENT,
+ },
+};
+
+static struct clk_divider axg_mpeg_clk_div = {
+ .reg = (void *)HHI_MPEG_CLK_CNTL,
+ .shift = 0,
+ .width = 7,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpeg_clk_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "mpeg_clk_sel" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_gate axg_clk81 = {
+ .reg = (void *)HHI_MPEG_CLK_CNTL,
+ .bit_idx = 7,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "clk81",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "mpeg_clk_div" },
+ .num_parents = 1,
+ .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
+ },
+};
+
+static const char * const axg_sd_emmc_clk0_parent_names[] = {
+ "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
+
+ /*
+ * Following these parent clocks, we should also have had mpll2, mpll3
+ * and gp0_pll but these clocks are too precious to be used here. All
+ * the necessary rates for MMC and NAND operation can be acheived using
+ * xtal or fclk_div clocks
+ */
+};
+
+/* SDcard clock */
+static struct clk_mux axg_sd_emmc_b_clk0_sel = {
+ .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
+ .mask = 0x7,
+ .shift = 25,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc_b_clk0_sel",
+ .ops = &clk_mux_ops,
+ .parent_names = axg_sd_emmc_clk0_parent_names,
+ .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_divider axg_sd_emmc_b_clk0_div = {
+ .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
+ .shift = 16,
+ .width = 7,
+ .lock = &clk_lock,
+ .flags = CLK_DIVIDER_ROUND_CLOSEST,
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc_b_clk0_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_gate axg_sd_emmc_b_clk0 = {
+ .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
+ .bit_idx = 23,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sd_emmc_b_clk0",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/* EMMC/NAND clock */
+static struct clk_mux axg_sd_emmc_c_clk0_sel = {
+ .reg = (void *)HHI_NAND_CLK_CNTL,
+ .mask = 0x7,
+ .shift = 9,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc_c_clk0_sel",
+ .ops = &clk_mux_ops,
+ .parent_names = axg_sd_emmc_clk0_parent_names,
+ .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_divider axg_sd_emmc_c_clk0_div = {
+ .reg = (void *)HHI_NAND_CLK_CNTL,
+ .shift = 0,
+ .width = 7,
+ .lock = &clk_lock,
+ .flags = CLK_DIVIDER_ROUND_CLOSEST,
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc_c_clk0_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_gate axg_sd_emmc_c_clk0 = {
+ .reg = (void *)HHI_NAND_CLK_CNTL,
+ .bit_idx = 7,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "sd_emmc_c_clk0",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/* Everything Else (EE) domain gates */
+static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
+static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
+static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
+static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
+static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
+static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
+static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
+static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
+static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
+static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
+static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
+static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
+static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
+static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
+static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
+static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
+static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
+static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
+static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
+static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
+
+static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
+static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
+static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
+static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
+static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
+static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
+static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
+static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
+static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
+static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
+static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
+
+static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
+static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
+static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
+static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
+static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
+static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
+static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
+static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
+
+/* Always On (AO) domain gates */
+
+static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
+static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
+static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
+static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
+static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
+
+/* Array of all clocks provided by this provider */
+
+static struct clk_hw_onecell_data axg_hw_onecell_data = {
+ .hws = {
+ [CLKID_SYS_PLL] = &axg_sys_pll.hw,
+ [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
+ [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
+ [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
+ [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &axg_clk81.hw,
+ [CLKID_MPLL0] = &axg_mpll0.hw,
+ [CLKID_MPLL1] = &axg_mpll1.hw,
+ [CLKID_MPLL2] = &axg_mpll2.hw,
+ [CLKID_MPLL3] = &axg_mpll3.hw,
+ [CLKID_DDR] = &axg_ddr.hw,
+ [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
+ [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
+ [CLKID_ISA] = &axg_isa.hw,
+ [CLKID_PL301] = &axg_pl301.hw,
+ [CLKID_PERIPHS] = &axg_periphs.hw,
+ [CLKID_SPICC0] = &axg_spicc_0.hw,
+ [CLKID_I2C] = &axg_i2c.hw,
+ [CLKID_RNG0] = &axg_rng0.hw,
+ [CLKID_UART0] = &axg_uart0.hw,
+ [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
+ [CLKID_SPICC1] = &axg_spicc_1.hw,
+ [CLKID_PCIE_A] = &axg_pcie_a.hw,
+ [CLKID_PCIE_B] = &axg_pcie_b.hw,
+ [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
+ [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
+ [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
+ [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
+ [CLKID_DMA] = &axg_dma.hw,
+ [CLKID_SPI] = &axg_spi.hw,
+ [CLKID_AUDIO] = &axg_audio.hw,
+ [CLKID_ETH] = &axg_eth_core.hw,
+ [CLKID_UART1] = &axg_uart1.hw,
+ [CLKID_G2D] = &axg_g2d.hw,
+ [CLKID_USB0] = &axg_usb0.hw,
+ [CLKID_USB1] = &axg_usb1.hw,
+ [CLKID_RESET] = &axg_reset.hw,
+ [CLKID_USB] = &axg_usb_general.hw,
+ [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
+ [CLKID_EFUSE] = &axg_efuse.hw,
+ [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
+ [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
+ [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
+ [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
+ [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
+ [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
+ [CLKID_GIC] = &axg_gic.hw,
+ [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
+ [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
+ [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
+ [CLKID_AO_IFACE] = &axg_ao_iface.hw,
+ [CLKID_AO_I2C] = &axg_ao_i2c.hw,
+ [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
+ [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
+ [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
+ [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
+ [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
+ [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
+ [NR_CLKS] = NULL,
+ },
+ .num = NR_CLKS,
+};
+
+/* Convenience tables to populate base addresses in .probe */
+
+static struct meson_clk_pll *const axg_clk_plls[] = {
+ &axg_fixed_pll,
+ &axg_sys_pll,
+ &axg_gp0_pll,
+};
+
+static struct meson_clk_mpll *const axg_clk_mplls[] = {
+ &axg_mpll0,
+ &axg_mpll1,
+ &axg_mpll2,
+ &axg_mpll3,
+};
+
+static struct clk_gate *const axg_clk_gates[] = {
+ &axg_clk81,
+ &axg_ddr,
+ &axg_audio_locker,
+ &axg_mipi_dsi_host,
+ &axg_isa,
+ &axg_pl301,
+ &axg_periphs,
+ &axg_spicc_0,
+ &axg_i2c,
+ &axg_rng0,
+ &axg_uart0,
+ &axg_mipi_dsi_phy,
+ &axg_spicc_1,
+ &axg_pcie_a,
+ &axg_pcie_b,
+ &axg_hiu_reg,
+ &axg_assist_misc,
+ &axg_emmc_b,
+ &axg_emmc_c,
+ &axg_dma,
+ &axg_spi,
+ &axg_audio,
+ &axg_eth_core,
+ &axg_uart1,
+ &axg_g2d,
+ &axg_usb0,
+ &axg_usb1,
+ &axg_reset,
+ &axg_usb_general,
+ &axg_ahb_arb0,
+ &axg_efuse,
+ &axg_boot_rom,
+ &axg_ahb_data_bus,
+ &axg_ahb_ctrl_bus,
+ &axg_usb1_to_ddr,
+ &axg_usb0_to_ddr,
+ &axg_mmc_pclk,
+ &axg_vpu_intr,
+ &axg_sec_ahb_ahb3_bridge,
+ &axg_gic,
+ &axg_ao_media_cpu,
+ &axg_ao_ahb_sram,
+ &axg_ao_ahb_bus,
+ &axg_ao_iface,
+ &axg_ao_i2c,
+ &axg_sd_emmc_b_clk0,
+ &axg_sd_emmc_c_clk0,
+};
+
+static struct clk_mux *const axg_clk_muxes[] = {
+ &axg_mpeg_clk_sel,
+ &axg_sd_emmc_b_clk0_sel,
+ &axg_sd_emmc_c_clk0_sel,
+};
+
+static struct clk_divider *const axg_clk_dividers[] = {
+ &axg_mpeg_clk_div,
+ &axg_sd_emmc_b_clk0_div,
+ &axg_sd_emmc_c_clk0_div,
+};
+
+struct clkc_data {
+ struct clk_gate *const *clk_gates;
+ unsigned int clk_gates_count;
+ struct meson_clk_mpll *const *clk_mplls;
+ unsigned int clk_mplls_count;
+ struct meson_clk_pll *const *clk_plls;
+ unsigned int clk_plls_count;
+ struct clk_mux *const *clk_muxes;
+ unsigned int clk_muxes_count;
+ struct clk_divider *const *clk_dividers;
+ unsigned int clk_dividers_count;
+ struct clk_hw_onecell_data *hw_onecell_data;
+};
+
+static const struct clkc_data axg_clkc_data = {
+ .clk_gates = axg_clk_gates,
+ .clk_gates_count = ARRAY_SIZE(axg_clk_gates),
+ .clk_mplls = axg_clk_mplls,
+ .clk_mplls_count = ARRAY_SIZE(axg_clk_mplls),
+ .clk_plls = axg_clk_plls,
+ .clk_plls_count = ARRAY_SIZE(axg_clk_plls),
+ .clk_muxes = axg_clk_muxes,
+ .clk_muxes_count = ARRAY_SIZE(axg_clk_muxes),
+ .clk_dividers = axg_clk_dividers,
+ .clk_dividers_count = ARRAY_SIZE(axg_clk_dividers),
+ .hw_onecell_data = &axg_hw_onecell_data,
+};
+
+static const struct of_device_id clkc_match_table[] = {
+ { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
+ {},
+};
+
+static int axg_clkc_probe(struct platform_device *pdev)
+{
+ const struct clkc_data *clkc_data;
+ void __iomem *clk_base;
+ int ret, clkid, i;
+ struct device *dev = &pdev->dev;
+
+ clkc_data = of_device_get_match_data(&pdev->dev);
+ if (!clkc_data)
+ return -EINVAL;
+
+ /* Generic clocks and PLLs */
+ clk_base = of_iomap(dev->of_node, 0);
+ if (!clk_base) {
+ pr_err("%s: Unable to map clk base\n", __func__);
+ return -ENXIO;
+ }
+
+ /* Populate base address for PLLs */
+ for (i = 0; i < clkc_data->clk_plls_count; i++)
+ clkc_data->clk_plls[i]->base = clk_base;
+
+ /* Populate base address for MPLLs */
+ for (i = 0; i < clkc_data->clk_mplls_count; i++)
+ clkc_data->clk_mplls[i]->base = clk_base;
+
+ /* Populate base address for gates */
+ for (i = 0; i < clkc_data->clk_gates_count; i++)
+ clkc_data->clk_gates[i]->reg = clk_base +
+ (u64)clkc_data->clk_gates[i]->reg;
+
+ /* Populate base address for muxes */
+ for (i = 0; i < clkc_data->clk_muxes_count; i++)
+ clkc_data->clk_muxes[i]->reg = clk_base +
+ (u64)clkc_data->clk_muxes[i]->reg;
+
+ /* Populate base address for dividers */
+ for (i = 0; i < clkc_data->clk_dividers_count; i++)
+ clkc_data->clk_dividers[i]->reg = clk_base +
+ (u64)clkc_data->clk_dividers[i]->reg;
+
+ /*
+ * register all clks
+ */
+ for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) {
+ /* array might be sparse */
+ if (!clkc_data->hw_onecell_data->hws[clkid])
+ continue;
+
+ ret = devm_clk_hw_register(dev,
+ clkc_data->hw_onecell_data->hws[clkid]);
+ if (ret)
+ goto iounmap;
+ }
+
+ return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
+ clkc_data->hw_onecell_data);
+
+iounmap:
+ iounmap(clk_base);
+ return ret;
+}
+
+static struct platform_driver axg_driver = {
+ .probe = axg_clkc_probe,
+ .driver = {
+ .name = "axg-clkc",
+ .of_match_table = clkc_match_table,
+ },
+};
+
+builtin_platform_driver(axg_driver);
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
new file mode 100644
index 000000000000..04c904cc3c3a
--- /dev/null
+++ b/drivers/clk/meson/axg.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2016 AmLogic, Inc.
+ * Author: Michael Turquette <mturquette@baylibre.com>
+ *
+ * Copyright (c) 2017 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+#ifndef __AXG_H
+#define __AXG_H
+
+/*
+ * Clock controller register offsets
+ *
+ * Register offsets from the data sheet must be multiplied by 4 before
+ * adding them to the base address to get the right value.
+ */
+#define HHI_GP0_PLL_CNTL 0x40
+#define HHI_GP0_PLL_CNTL2 0x44
+#define HHI_GP0_PLL_CNTL3 0x48
+#define HHI_GP0_PLL_CNTL4 0x4c
+#define HHI_GP0_PLL_CNTL5 0x50
+#define HHI_GP0_PLL_STS 0x54
+#define HHI_GP0_PLL_CNTL1 0x58
+#define HHI_HIFI_PLL_CNTL 0x80
+#define HHI_HIFI_PLL_CNTL2 0x84
+#define HHI_HIFI_PLL_CNTL3 0x88
+#define HHI_HIFI_PLL_CNTL4 0x8C
+#define HHI_HIFI_PLL_CNTL5 0x90
+#define HHI_HIFI_PLL_STS 0x94
+#define HHI_HIFI_PLL_CNTL1 0x98
+
+#define HHI_XTAL_DIVN_CNTL 0xbc
+#define HHI_GCLK2_MPEG0 0xc0
+#define HHI_GCLK2_MPEG1 0xc4
+#define HHI_GCLK2_MPEG2 0xc8
+#define HHI_GCLK2_OTHER 0xd0
+#define HHI_GCLK2_AO 0xd4
+#define HHI_PCIE_PLL_CNTL 0xd8
+#define HHI_PCIE_PLL_CNTL1 0xdC
+#define HHI_PCIE_PLL_CNTL2 0xe0
+#define HHI_PCIE_PLL_CNTL3 0xe4
+#define HHI_PCIE_PLL_CNTL4 0xe8
+#define HHI_PCIE_PLL_CNTL5 0xec
+#define HHI_PCIE_PLL_CNTL6 0xf0
+#define HHI_PCIE_PLL_STS 0xf4
+
+#define HHI_MEM_PD_REG0 0x100
+#define HHI_VPU_MEM_PD_REG0 0x104
+#define HHI_VIID_CLK_DIV 0x128
+#define HHI_VIID_CLK_CNTL 0x12c
+
+#define HHI_GCLK_MPEG0 0x140
+#define HHI_GCLK_MPEG1 0x144
+#define HHI_GCLK_MPEG2 0x148
+#define HHI_GCLK_OTHER 0x150
+#define HHI_GCLK_AO 0x154
+#define HHI_SYS_CPU_CLK_CNTL1 0x15c
+#define HHI_SYS_CPU_RESET_CNTL 0x160
+#define HHI_VID_CLK_DIV 0x164
+#define HHI_SPICC_HCLK_CNTL 0x168
+
+#define HHI_MPEG_CLK_CNTL 0x174
+#define HHI_VID_CLK_CNTL 0x17c
+#define HHI_TS_CLK_CNTL 0x190
+#define HHI_VID_CLK_CNTL2 0x194
+#define HHI_SYS_CPU_CLK_CNTL0 0x19c
+#define HHI_VID_PLL_CLK_DIV 0x1a0
+#define HHI_VPU_CLK_CNTL 0x1bC
+
+#define HHI_VAPBCLK_CNTL 0x1F4
+
+#define HHI_GEN_CLK_CNTL 0x228
+
+#define HHI_VDIN_MEAS_CLK_CNTL 0x250
+#define HHI_NAND_CLK_CNTL 0x25C
+#define HHI_SD_EMMC_CLK_CNTL 0x264
+
+#define HHI_MPLL_CNTL 0x280
+#define HHI_MPLL_CNTL2 0x284
+#define HHI_MPLL_CNTL3 0x288
+#define HHI_MPLL_CNTL4 0x28C
+#define HHI_MPLL_CNTL5 0x290
+#define HHI_MPLL_CNTL6 0x294
+#define HHI_MPLL_CNTL7 0x298
+#define HHI_MPLL_CNTL8 0x29C
+#define HHI_MPLL_CNTL9 0x2A0
+#define HHI_MPLL_CNTL10 0x2A4
+
+#define HHI_MPLL3_CNTL0 0x2E0
+#define HHI_MPLL3_CNTL1 0x2E4
+#define HHI_PLL_TOP_MISC 0x2E8
+
+#define HHI_SYS_PLL_CNTL1 0x2FC
+#define HHI_SYS_PLL_CNTL 0x300
+#define HHI_SYS_PLL_CNTL2 0x304
+#define HHI_SYS_PLL_CNTL3 0x308
+#define HHI_SYS_PLL_CNTL4 0x30c
+#define HHI_SYS_PLL_CNTL5 0x310
+#define HHI_SYS_PLL_STS 0x314
+#define HHI_DPLL_TOP_I 0x318
+#define HHI_DPLL_TOP2_I 0x31C
+
+/*
+ * CLKID index values
+ *
+ * These indices are entirely contrived and do not map onto the hardware.
+ * It has now been decided to expose everything by default in the DT header:
+ * include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want
+ * to expose, such as the internal muxes and dividers of composite clocks,
+ * will remain defined here.
+ */
+#define CLKID_MPEG_SEL 8
+#define CLKID_MPEG_DIV 9
+#define CLKID_SD_EMMC_B_CLK0_SEL 61
+#define CLKID_SD_EMMC_B_CLK0_DIV 62
+#define CLKID_SD_EMMC_C_CLK0_SEL 63
+#define CLKID_SD_EMMC_C_CLK0_DIV 64
+
+#define NR_CLKS 65
+
+/* include the CLKIDs that have been made part of the DT binding */
+#include <dt-bindings/clock/axg-clkc.h>
+
+#endif /* __AXG_H */
diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
new file mode 100644
index 000000000000..d2c0f49ba0df
--- /dev/null
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -0,0 +1,72 @@
+/*
+ * Meson-AXG clock tree IDs
+ *
+ * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef __AXG_CLKC_H
+#define __AXG_CLKC_H
+
+#define CLKID_SYS_PLL 0
+#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_DIV2 2
+#define CLKID_FCLK_DIV3 3
+#define CLKID_FCLK_DIV4 4
+#define CLKID_FCLK_DIV5 5
+#define CLKID_FCLK_DIV7 6
+#define CLKID_GP0_PLL 7
+#define CLKID_CLK81 10
+#define CLKID_MPLL0 11
+#define CLKID_MPLL1 12
+#define CLKID_MPLL2 13
+#define CLKID_MPLL3 14
+#define CLKID_DDR 15
+#define CLKID_AUDIO_LOCKER 16
+#define CLKID_MIPI_DSI_HOST 17
+#define CLKID_ISA 18
+#define CLKID_PL301 19
+#define CLKID_PERIPHS 20
+#define CLKID_SPICC0 21
+#define CLKID_I2C 22
+#define CLKID_RNG0 23
+#define CLKID_UART0 24
+#define CLKID_MIPI_DSI_PHY 25
+#define CLKID_SPICC1 26
+#define CLKID_PCIE_A 27
+#define CLKID_PCIE_B 28
+#define CLKID_HIU_IFACE 29
+#define CLKID_ASSIST_MISC 30
+#define CLKID_SD_EMMC_B 31
+#define CLKID_SD_EMMC_C 32
+#define CLKID_DMA 33
+#define CLKID_SPI 34
+#define CLKID_AUDIO 35
+#define CLKID_ETH 36
+#define CLKID_UART1 37
+#define CLKID_G2D 38
+#define CLKID_USB0 39
+#define CLKID_USB1 40
+#define CLKID_RESET 41
+#define CLKID_USB 42
+#define CLKID_AHB_ARB0 43
+#define CLKID_EFUSE 44
+#define CLKID_BOOT_ROM 45
+#define CLKID_AHB_DATA_BUS 46
+#define CLKID_AHB_CTRL_BUS 47
+#define CLKID_USB1_DDR_BRIDGE 48
+#define CLKID_USB0_DDR_BRIDGE 49
+#define CLKID_MMC_PCLK 50
+#define CLKID_VPU_INTR 51
+#define CLKID_SEC_AHB_AHB3_BRIDGE 52
+#define CLKID_GIC 53
+#define CLKID_AO_MEDIA_CPU 54
+#define CLKID_AO_AHB_SRAM 55
+#define CLKID_AO_AHB_BUS 56
+#define CLKID_AO_IFACE 57
+#define CLKID_AO_I2C 58
+#define CLKID_SD_EMMC_B_CLK0 59
+#define CLKID_SD_EMMC_C_CLK0 60
+
+#endif /* __AXG_CLKC_H */
--
2.15.0
^ permalink raw reply related
* [PATCH v3 1/3] dt-bindings: clock: add compatible variant for the Meson-AXG
From: Yixun Lan @ 2017-11-28 12:53 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Kevin Hilman
Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd,
Carlo Caione, Yixun Lan, Qiufang Dai, linux-amlogic, devicetree,
linux-clk, linux-arm-kernel, linux-kernel
In-Reply-To: <20171128125330.363-1-yixun.lan@amlogic.com>
Update the documentation to support clock driver for the Amlogic's
Meson-AXG SoC.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
index 924040769186..e2b377ed6f91 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
@@ -5,8 +5,11 @@ controllers within the SoC.
Required Properties:
-- compatible: should be "amlogic,gxbb-clkc" for GXBB SoC,
- or "amlogic,gxl-clkc" for GXL and GXM SoC.
+- compatible: should be:
+ "amlogic,gxbb-clkc" for GXBB SoC,
+ "amlogic,gxl-clkc" for GXL and GXM SoC,
+ "amlogic,axg-clkc" for AXG SoC.
+
- reg: physical base address of the clock controller and length of memory
mapped region.
--
2.15.0
^ permalink raw reply related
* [PATCH v3 0/3] add clk controller driver for Meson-AXG SoC
From: Yixun Lan @ 2017-11-28 12:53 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Kevin Hilman
Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd,
Carlo Caione, Yixun Lan, Qiufang Dai, linux-amlogic, devicetree,
linux-clk, linux-arm-kernel, linux-kernel
Add driver for the clk controller which found in Meson AXG SoC
Note, we deliberately create a seperate source file for the Meson AXG
series, instead of sharing code with previous GXBB/GXL - the file axg.c
It would help us maintaining the code more easily.
Changes since v2 [2]:
- drop register offset calculation
- update dt-bindings for new compatible variant
Changes since v1 [1]:
- rework register definion, use '(offset << 2)' to better match
the description from data sheet
- drop "#include dt-bindings/clock/gxbb-aoclkc.h" from dts
- rebase code to v4.15-rc1
[2]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005468.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005469.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005470.html
[1]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005239.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005240.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005241.html
Qiufang Dai (2):
clk: meson-axg: add clock controller drivers
arm64: dts: meson-axg: add clock DT info for Meson AXG SoC
Yixun Lan (1):
dt-bindings: clock: add compatible variant for the Meson-AXG
.../bindings/clock/amlogic,gxbb-clkc.txt | 7 +-
arch/arm64/Kconfig.platforms | 1 +
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 15 +
drivers/clk/meson/Kconfig | 8 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/axg.c | 948 +++++++++++++++++++++
drivers/clk/meson/axg.h | 126 +++
include/dt-bindings/clock/axg-clkc.h | 72 ++
8 files changed, 1176 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/meson/axg.c
create mode 100644 drivers/clk/meson/axg.h
create mode 100644 include/dt-bindings/clock/axg-clkc.h
--
2.15.0
^ permalink raw reply
* Re: [PATCH v2 0/2] add clk controller driver for Meson-AXG SoC
From: Yixun Lan @ 2017-11-28 12:47 UTC (permalink / raw)
To: Jerome Brunet, Neil Armstrong, Kevin Hilman
Cc: yixun.lan, Rob Herring, Mark Rutland, Michael Turquette,
Stephen Boyd, Carlo Caione, Qiufang Dai, linux-amlogic,
devicetree, linux-clk, linux-arm-kernel, linux-kernel
In-Reply-To: <1511790489.30519.11.camel@baylibre.com>
Hi jerome:
On 11/27/17 21:48, Jerome Brunet wrote:
> On Mon, 2017-11-27 at 17:48 +0800, Yixun Lan wrote:
>> Add driver for the clk controller which found in Meson AXG SoC
>>
>> Note, we deliberately create a seperate source file for the Meson AXG
>> series, instead of sharing code with previous GXBB/GXL - the file axg.c
>> It would help us maintaining the code more easily.
>
> But this will be the last meson SoC added this way. We need factor the code the
> between meson8, gx and axg series since there is a lot of duplication there.
>
>>
>> Changes since v1 [1]:
>> - rework register definion, use '(offset << 2)' to better match
>
> As previously discussed, please drop these calculations and just write what the
> offset actually are. Putting one comment at the top, explaining the translation,
> would be nice though.
>
can drop the calculations, but there is already a comment at top here..
>> the description from data sheet
>> - drop "#include dt-bindings/clock/gxbb-aoclkc.h" from dts
>> - rebase code to v4.15-rc1
>>
>> [1]
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005239.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005240.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005241.html
>>
>>
>> Qiufang Dai (2):
>
> First patch of the series should be adding the compatible documentation, which
> is missing here (unless it has gone through another channel and I missed it)
>
I missed the dt-binding, will fix in next version
>> clk: meson-axg: add clock controller drivers
>> arm64: dts: meson-axg: add clock DT info for Meson AXG SoC
>>
>> arch/arm64/Kconfig.platforms | 1 +
>> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 15 +
>> drivers/clk/meson/Kconfig | 8 +
>> drivers/clk/meson/Makefile | 1 +
>> drivers/clk/meson/axg.c | 948
>> +++++++++++++++++++++++++++++
>> drivers/clk/meson/axg.h | 126 ++++
>> include/dt-bindings/clock/axg-clkc.h | 72 +++
>> 7 files changed, 1171 insertions(+)
>> create mode 100644 drivers/clk/meson/axg.c
>> create mode 100644 drivers/clk/meson/axg.h
>> create mode 100644 include/dt-bindings/clock/axg-clkc.h
>>
>
> .
>
^ permalink raw reply
* Re: [PATCH] pinctrl: sunxi: add support for Allwinner H6 main pin controller
From: Maxime Ripard @ 2017-11-28 12:13 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Linus Walleij, Chen-Yu Tsai, linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20171128110614.9303-1-icenowy-h8G6r0blFSE@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 764 bytes --]
Hi,
On Tue, Nov 28, 2017 at 07:06:14PM +0800, Icenowy Zheng wrote:
> Allwinner H6 SoC has two pin controllers like other Allwinner SoCs with
> ARISC: one main pin controller (called CPUX-PORT in user manual) and one
> pin controller in the CPUs power domain (called CPUS-PORT in user
> manual).
>
> This commit adds support for the main pin controller in the H6 SoC.
>
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
This looks mostly fine, but we've had issues in the past with pinctrl
drivers submitted without SoC support, and we'll have to support them
forever.
Please resend this as part your upcoming serie to enable the H6.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
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