* [PATCH 12/20] ARM: dts: am43xx: add bus functionality to base PRCM node
From: Tero Kristo @ 2017-12-07 8:46 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512636413-25243-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
Add simple-bus compatibility and ranges properties to prcm node. This is
done in preparation of adding the support for clkctrl nodes.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/am4372.dtsi | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 549b9f4..bf4e58e 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -163,9 +163,12 @@
};
prcm: prcm@1f0000 {
- compatible = "ti,am4-prcm";
+ compatible = "ti,am4-prcm", "simple-bus";
reg = <0x1f0000 0x11000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1f0000 0x11000>;
prcm_clocks: clocks {
#address-cells = <1>;
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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* [PATCH 11/20] ARM: dts: am33xx: add bus functionality to base PRCM node
From: Tero Kristo @ 2017-12-07 8:46 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512636413-25243-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
Add simple-bus compatibility and ranges properties to prcm node. This is
done in preparation of adding the support for clkctrl nodes.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/am33xx.dtsi | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index a0eb537..bd10ba7 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -179,8 +179,11 @@
};
prcm: prcm@200000 {
- compatible = "ti,am3-prcm";
+ compatible = "ti,am3-prcm", "simple-bus";
reg = <0x200000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x200000 0x4000>;
prcm_clocks: clocks {
#address-cells = <1>;
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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* [PATCH 10/20] ARM: dts: dra7: add bus functionality to base PRCM nodes
From: Tero Kristo @ 2017-12-07 8:46 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512636413-25243-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
Add simple-bus compatibility and ranges properties to cm1, cm2 and prm
nodes. This is done in preparation of adding the support for clkctrl
nodes.
SPLIT: timer1 fck setup
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/dra7.dtsi | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index c538e2f..5e24cea 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -224,8 +224,12 @@
};
cm_core_aon: cm_core_aon@5000 {
- compatible = "ti,dra7-cm-core-aon";
+ compatible = "ti,dra7-cm-core-aon",
+ "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
reg = <0x5000 0x2000>;
+ ranges = <0 0x5000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
@@ -237,8 +241,11 @@
};
cm_core: cm_core@8000 {
- compatible = "ti,dra7-cm-core";
+ compatible = "ti,dra7-cm-core", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
reg = <0x8000 0x3000>;
+ ranges = <0 0x8000 0x3000>;
cm_core_clocks: clocks {
#address-cells = <1>;
@@ -263,9 +270,12 @@
};
prm: prm@6000 {
- compatible = "ti,dra7-prm";
+ compatible = "ti,dra7-prm", "simple-bus";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x6000 0x3000>;
prm_clocks: clocks {
#address-cells = <1>;
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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* [PATCH 09/20] ARM: dts: omap4: add bus functionality to base PRCM nodes
From: Tero Kristo @ 2017-12-07 8:46 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512636413-25243-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
Add simple-bus compatibility and ranges properties to cm1, cm2 and prm
nodes. This is done in preparation of adding the support for clkctrl
nodes.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/omap4.dtsi | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 56fdde3..787ea2a 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -143,8 +143,11 @@
ranges = <0 0x4a000000 0x1000000>;
cm1: cm1@4000 {
- compatible = "ti,omap4-cm1";
+ compatible = "ti,omap4-cm1", "simple-bus";
reg = <0x4000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4000 0x2000>;
cm1_clocks: clocks {
#address-cells = <1>;
@@ -156,8 +159,11 @@
};
cm2: cm2@8000 {
- compatible = "ti,omap4-cm2";
+ compatible = "ti,omap4-cm2", "simple-bus";
reg = <0x8000 0x3000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x8000 0x3000>;
cm2_clocks: clocks {
#address-cells = <1>;
@@ -243,6 +249,9 @@
compatible = "ti,omap4-prm";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x6000 0x3000>;
prm_clocks: clocks {
#address-cells = <1>;
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply related
* [PATCH 08/20] ARM: dts: omap5: add bus functionality to base PRCM nodes
From: Tero Kristo @ 2017-12-07 8:46 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512636413-25243-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
Add simple-bus compatibility and ranges properties to cm_core_aon, cm_core
and prm nodes. This is done in preparation of adding the support for
clkctrl nodes.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/omap5.dtsi | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 404c78f..b0992b8 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -201,8 +201,12 @@
};
cm_core_aon: cm_core_aon@4000 {
- compatible = "ti,omap5-cm-core-aon";
+ compatible = "ti,omap5-cm-core-aon",
+ "simple-bus";
reg = <0x4000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
@@ -214,8 +218,11 @@
};
cm_core: cm_core@8000 {
- compatible = "ti,omap5-cm-core";
+ compatible = "ti,omap5-cm-core", "simple-bus";
reg = <0x8000 0x3000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x8000 0x3000>;
cm_core_clocks: clocks {
#address-cells = <1>;
@@ -240,9 +247,12 @@
};
prm: prm@6000 {
- compatible = "ti,omap5-prm";
+ compatible = "ti,omap5-prm", "simple-bus";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x6000 0x3000>;
prm_clocks: clocks {
#address-cells = <1>;
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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* [PATCH 07/20] ARM: dts: dm816x: add fck under timers1/2
From: Tero Kristo @ 2017-12-07 8:46 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512636413-25243-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
Add the functional clock definition for timers1/2. This is needed so that
the clock rate claculations continue to function properly once dm816x
transitions away from hwmod data and towards the clkctrl clocks.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/dm816x.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index 566b2a8..12edb8f 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -331,6 +331,8 @@
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
+ clocks = <&timer1_fck>;
+ clock-names = "fck";
};
timer2: timer@48040000 {
@@ -338,6 +340,8 @@
reg = <0x48040000 0x2000>;
interrupts = <68>;
ti,hwmods = "timer2";
+ clocks = <&timer2_fck>;
+ clock-names = "fck";
};
timer3: timer@48042000 {
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply related
* [PATCH 06/20] ARM: dts: dm814x: add fck under timers1/2
From: Tero Kristo @ 2017-12-07 8:46 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512636413-25243-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
Add the functional clock definition for timers1/2. This is needed so that
the clock rate claculations continue to function properly once dm814x
transitions away from hwmod data and towards the clkctrl clocks.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/dm814x.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi
index 9708157..82fbcf1 100644
--- a/arch/arm/boot/dts/dm814x.dtsi
+++ b/arch/arm/boot/dts/dm814x.dtsi
@@ -249,6 +249,8 @@
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
+ clocks = <&timer1_fck>;
+ clock-names = "fck";
};
uart1: uart@20000 {
@@ -286,6 +288,8 @@
reg = <0x40000 0x2000>;
interrupts = <68>;
ti,hwmods = "timer2";
+ clocks = <&timer2_fck>;
+ clock-names = "fck";
};
timer3: timer@42000 {
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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* [PATCH 05/20] ARM: dts: dra7: add fck under timer1
From: Tero Kristo @ 2017-12-07 8:46 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512636413-25243-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
Add the functional clock definition for timer1. This is needed so that
the clock rate calculations continue to function properly once dra7
transitions away from hwmod data and towards the clkctrl clocks.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/dra7.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index ac92162..c538e2f 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -876,6 +876,8 @@
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
ti,timer-alwon;
+ clock-names = "fck";
+ clocks = <&timer1_gfclk_mux>;
};
timer2: timer@48032000 {
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply related
* [PATCH 04/20] ARM: dts: am43xx: add fck under timers1/2
From: Tero Kristo @ 2017-12-07 8:46 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512636413-25243-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
Add the functional clock definition for timers1/2. This is needed so that
the clock rate calculations continue to function properly once am33xx
transitions away from hwmod data and towards the clkctrl clocks.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/am4372.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index e5b0614..549b9f4 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -346,6 +346,8 @@
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-alwon;
ti,hwmods = "timer1";
+ clocks = <&timer1_fck>;
+ clock-names = "fck";
};
timer2: timer@48040000 {
@@ -353,6 +355,8 @@
reg = <0x48040000 0x400>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer2";
+ clocks = <&timer2_fck>;
+ clock-names = "fck";
};
timer3: timer@48042000 {
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply related
* [PATCH 03/20] ARM: dts: am33xx: add fck under timers1/2
From: Tero Kristo @ 2017-12-07 8:46 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512636413-25243-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
Add the functional clock definition for timers1/2. This is needed so that
the clock rate calculations continue to function properly once am33xx
transitions away from hwmod data and towards the clkctrl clocks.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/am33xx.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 1b81c4e..a0eb537 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -517,6 +517,8 @@
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
+ clocks = <&timer1_fck>;
+ clock-names = "fck";
};
timer2: timer@48040000 {
@@ -524,6 +526,8 @@
reg = <0x48040000 0x400>;
interrupts = <68>;
ti,hwmods = "timer2";
+ clocks = <&timer2_fck>;
+ clock-names = "fck";
};
timer3: timer@48042000 {
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply related
* [PATCH 02/20] ARM: dts: omap4: add fck under timer1
From: Tero Kristo @ 2017-12-07 8:46 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512636413-25243-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
Add the functional clock definition for timer1. This is needed so that
the clock rate calculations continue to function properly once omap4
transitions away from hwmod data and towards the clkctrl clocks.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/omap4.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 1dc5a76..56fdde3 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -973,6 +973,8 @@
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
ti,timer-alwon;
+ clocks = <&dmt1_clk_mux>;
+ clock-names = "fck";
};
timer2: timer@48032000 {
--
1.9.1
--
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^ permalink raw reply related
* [PATCH 01/20] ARM: dts: omap5: add fck under timer1
From: Tero Kristo @ 2017-12-07 8:46 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512636413-25243-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
Add the functional clock definition for timer1. This is needed so that
the clock rate calculations continue to function properly once omap5
transitions away from hwmod data and towards the clkctrl clocks.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/omap5.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 4cd0005..404c78f 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -734,6 +734,8 @@
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
ti,timer-alwon;
+ clocks = <&timer1_gfclk_mux>;
+ clock-names = "fck";
};
timer2: timer@48032000 {
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply related
* [PATCH 00/20] ARM: dts: add omap clkctrl support
From: Tero Kristo @ 2017-12-07 8:46 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
Hi,
This series adds the clkctrl support for omap2 family SoCs for am33xx,
am43xx, omap4, omap5, dra7 and dm81xx. This series depends on the
previously posted drivers/clk [1] + mach-omap2 [2] series for the same.
Branch pushed to my public tree:
tree: https://github.com/t-kristo/linux-pm.git
branch: 4.15-rc1-clkctrl-dts
-Tero
[1] https://www.spinics.net/lists/linux-omap/msg140587.html
[2] https://www.spinics.net/lists/linux-omap/msg140588.html
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply
* Re: [PATCH 1/2] arm64: defconfig: enable MUSB HDRC along with Allwinner glue
From: Maxime Ripard @ 2017-12-07 8:46 UTC (permalink / raw)
To: Jagan Teki
Cc: Catalin Marinas, Will Deacon, Chen-Yu Tsai, Icenowy Zheng,
Rob Herring, Mark Rutland, Michael Trimarchi,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Jagan Teki
In-Reply-To: <1512582598-24806-1-git-send-email-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 514 bytes --]
On Wed, Dec 06, 2017 at 11:19:58PM +0530, Jagan Teki wrote:
> Allwinner SoCs typically have a Mentor Graphics Inventra MUSB
> dual role controller for USB OTG. This is need for verifying
> gadget functions, so enable them by default.
>
> Tested 'otg' mode with mass storage function.
>
> Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH v2 33/35] clocksource/drivers/atcpit100: Add andestech atcpit100 timer
From: Daniel Lezcano @ 2017-12-07 8:44 UTC (permalink / raw)
To: Greentime Hu, greentime, linux-kernel, arnd, linux-arch, tglx,
jason, marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, linux-serial
Cc: Rick Chen
In-Reply-To: <672e0b3843953d1ab69bc19baf1a0f217ec1b1fa.1511785528.git.green.hu@gmail.com>
On 27/11/2017 13:28, Greentime Hu wrote:
> From: Rick Chen <rickchen36@gmail.com>
>
> ATCPIT100 is often used on the Andes architecture,
> This timer provide 4 PIT channels. Each PIT channel is a
> multi-function timer, can be configured as 32,16,8 bit timers
> or PWM as well.
>
> For system timer it will set channel 1 32-bit timer0 as clock
> source and count downwards until underflow and restart again.
>
> It also set channel 0 32-bit timer0 as clock event and count
> downwards until condition match. It will generate an interrupt
> for handling periodically.
>
> Signed-off-by: Rick Chen <rickchen36@gmail.com>
> Signed-off-by: Greentime Hu <green.hu@gmail.com>
> ---
Looks good.
Please resend this patch folded with the Makefile change and the DT
binding (fixed) as suggested by Arnd. I will merge them.
Thanks
-- Daniel
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* Re: [PATCH v2 34/35] clocksource/drivers/Kconfig: Support andestech atcpit100 timer
From: Daniel Lezcano @ 2017-12-07 8:40 UTC (permalink / raw)
To: Greentime Hu, Arnd Bergmann
Cc: Greentime, Linux Kernel Mailing List, linux-arch, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Networking, Vincent Chen,
DTML, Al Viro, David Howells, Will Deacon, linux-serial,
Rick Chen
In-Reply-To: <CAEbi=3f6YZJySA5A2+y1hiPHwfkq+05cisnRwyhKYDXQdnFzWA@mail.gmail.com>
On 28/11/2017 03:53, Greentime Hu wrote:
> 2017-11-27 22:11 GMT+08:00 Arnd Bergmann <arnd@arndb.de>:
>> On Mon, Nov 27, 2017 at 1:28 PM, Greentime Hu <green.hu@gmail.com> wrote:
>>> From: Rick Chen <rickchen36@gmail.com>
>>>
>>> Add CLKSRC_ATCPIT100 for Andestech atcpit100 timer selection.
>>> It often be used in Andestech AE3XX platform.
>>>
>>> Signed-off-by: Rick Chen <rickchen36@gmail.com>
>>> Signed-off-by: Greentime Hu <green.hu@gmail.com>
>>
>> No need to split out the Makefile patch from the actual driver, they
>> clearly belong together.
>> The binding change should be a separate patch, as you did.
>>
>> It's probably best to separate the driver patches from the
>> architecture submission
>> in the future, they can simply get merged by the respective subsystem
>> maintainers,
>> with a smaller Cc list.
>>
>
> Hi, Arnd:
>
> Thanks.
> We will merge these 2 patches together in the next version patch.
> We will sent to clocksource subsystem with a seperate patchset.
Sounds good.
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* Re: [PATCH v4 3/4] clk: meson-axg: add clock controller drivers
From: Neil Armstrong @ 2017-12-07 8:40 UTC (permalink / raw)
To: Yixun Lan, Jerome Brunet, Kevin Hilman
Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd,
Carlo Caione, Qiufang Dai, linux-amlogic, devicetree, linux-clk,
linux-arm-kernel, linux-kernel
In-Reply-To: <20171201012452.27086-4-yixun.lan@amlogic.com>
On 01/12/2017 02:24, Yixun Lan wrote:
> From: Qiufang Dai <qiufang.dai@amlogic.com>
>
> Add clock controller drivers for Amlogic Meson-AXG SoC.
>
> Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
> arch/arm64/Kconfig.platforms | 1 +
> drivers/clk/meson/Kconfig | 8 +
> drivers/clk/meson/Makefile | 1 +
> drivers/clk/meson/axg.c | 944 +++++++++++++++++++++++++++++++++++++++++++
> drivers/clk/meson/axg.h | 126 ++++++
> 5 files changed, 1080 insertions(+)
> create mode 100644 drivers/clk/meson/axg.c
> create mode 100644 drivers/clk/meson/axg.h
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 2401373565ff..fbedbd8f619a 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -105,6 +105,7 @@ config ARCH_MESON
> select PINCTRL_MESON
> select COMMON_CLK_AMLOGIC
> select COMMON_CLK_GXBB
> + select COMMON_CLK_AXG
> select MESON_IRQ_GPIO
> help
> This enables support for the Amlogic S905 SoCs.
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index d2d0174a6eca..7694302c70a4 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -19,3 +19,11 @@ config COMMON_CLK_GXBB
> help
> Support for the clock controller on AmLogic S905 devices, aka gxbb.
> Say Y if you want peripherals and CPU frequency scaling to work.
> +
> +config COMMON_CLK_AXG
> + bool
> + depends on COMMON_CLK_AMLOGIC
> + select RESET_CONTROLLER
> + help
> + Support for the clock controller on AmLogic A113D devices, aka axg.
> + Say Y if you want peripherals and CPU frequency scaling to work.
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index b139d41b25da..3c03ce583798 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -5,3 +5,4 @@
> obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-regmap.o gxbb-aoclk-32k.o
> +obj-$(CONFIG_COMMON_CLK_AXG) += axg.o
> diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
> new file mode 100644
> index 000000000000..03f57541bc1e
> --- /dev/null
> +++ b/drivers/clk/meson/axg.c
> @@ -0,0 +1,944 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * AmLogic Meson-AXG Clock Controller Driver
> + *
> + * Copyright (c) 2016 Baylibre SAS.
> + * Author: Michael Turquette <mturquette@baylibre.com>
> + *
> + * Copyright (c) 2017 Amlogic, inc.
> + * Author: Qiufang Dai <qiufang.dai@amlogic.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/init.h>
> +
> +#include "clkc.h"
> +#include "axg.h"
> +
> +static DEFINE_SPINLOCK(clk_lock);
> +
> +static const struct pll_rate_table sys_pll_rate_table[] = {
> + PLL_RATE(24000000, 56, 1, 2),
> + PLL_RATE(48000000, 64, 1, 2),
> + PLL_RATE(72000000, 72, 1, 2),
> + PLL_RATE(96000000, 64, 1, 2),
> + PLL_RATE(120000000, 80, 1, 2),
> + PLL_RATE(144000000, 96, 1, 2),
> + PLL_RATE(168000000, 56, 1, 1),
> + PLL_RATE(192000000, 64, 1, 1),
> + PLL_RATE(216000000, 72, 1, 1),
> + PLL_RATE(240000000, 80, 1, 1),
> + PLL_RATE(264000000, 88, 1, 1),
> + PLL_RATE(288000000, 96, 1, 1),
> + PLL_RATE(312000000, 52, 1, 2),
> + PLL_RATE(336000000, 56, 1, 2),
> + PLL_RATE(360000000, 60, 1, 2),
> + PLL_RATE(384000000, 64, 1, 2),
> + PLL_RATE(408000000, 68, 1, 2),
> + PLL_RATE(432000000, 72, 1, 2),
> + PLL_RATE(456000000, 76, 1, 2),
> + PLL_RATE(480000000, 80, 1, 2),
> + PLL_RATE(504000000, 84, 1, 2),
> + PLL_RATE(528000000, 88, 1, 2),
> + PLL_RATE(552000000, 92, 1, 2),
> + PLL_RATE(576000000, 96, 1, 2),
> + PLL_RATE(600000000, 50, 1, 1),
> + PLL_RATE(624000000, 52, 1, 1),
> + PLL_RATE(648000000, 54, 1, 1),
> + PLL_RATE(672000000, 56, 1, 1),
> + PLL_RATE(696000000, 58, 1, 1),
> + PLL_RATE(720000000, 60, 1, 1),
> + PLL_RATE(744000000, 62, 1, 1),
> + PLL_RATE(768000000, 64, 1, 1),
> + PLL_RATE(792000000, 66, 1, 1),
> + PLL_RATE(816000000, 68, 1, 1),
> + PLL_RATE(840000000, 70, 1, 1),
> + PLL_RATE(864000000, 72, 1, 1),
> + PLL_RATE(888000000, 74, 1, 1),
> + PLL_RATE(912000000, 76, 1, 1),
> + PLL_RATE(936000000, 78, 1, 1),
> + PLL_RATE(960000000, 80, 1, 1),
> + PLL_RATE(984000000, 82, 1, 1),
> + PLL_RATE(1008000000, 84, 1, 1),
> + PLL_RATE(1032000000, 86, 1, 1),
> + PLL_RATE(1056000000, 88, 1, 1),
> + PLL_RATE(1080000000, 90, 1, 1),
> + PLL_RATE(1104000000, 92, 1, 1),
> + PLL_RATE(1128000000, 94, 1, 1),
> + PLL_RATE(1152000000, 96, 1, 1),
> + PLL_RATE(1176000000, 98, 1, 1),
> + PLL_RATE(1200000000, 50, 1, 0),
> + PLL_RATE(1224000000, 51, 1, 0),
> + PLL_RATE(1248000000, 52, 1, 0),
> + PLL_RATE(1272000000, 53, 1, 0),
> + PLL_RATE(1296000000, 54, 1, 0),
> + PLL_RATE(1320000000, 55, 1, 0),
> + PLL_RATE(1344000000, 56, 1, 0),
> + PLL_RATE(1368000000, 57, 1, 0),
> + PLL_RATE(1392000000, 58, 1, 0),
> + PLL_RATE(1416000000, 59, 1, 0),
> + PLL_RATE(1440000000, 60, 1, 0),
> + PLL_RATE(1464000000, 61, 1, 0),
> + PLL_RATE(1488000000, 62, 1, 0),
> + PLL_RATE(1512000000, 63, 1, 0),
> + PLL_RATE(1536000000, 64, 1, 0),
> + PLL_RATE(1560000000, 65, 1, 0),
> + PLL_RATE(1584000000, 66, 1, 0),
> + PLL_RATE(1608000000, 67, 1, 0),
> + PLL_RATE(1632000000, 68, 1, 0),
> + PLL_RATE(1656000000, 68, 1, 0),
> + PLL_RATE(1680000000, 68, 1, 0),
> + PLL_RATE(1704000000, 68, 1, 0),
> + PLL_RATE(1728000000, 69, 1, 0),
> + PLL_RATE(1752000000, 69, 1, 0),
> + PLL_RATE(1776000000, 69, 1, 0),
> + PLL_RATE(1800000000, 69, 1, 0),
> + PLL_RATE(1824000000, 70, 1, 0),
> + PLL_RATE(1848000000, 70, 1, 0),
> + PLL_RATE(1872000000, 70, 1, 0),
> + PLL_RATE(1896000000, 70, 1, 0),
> + PLL_RATE(1920000000, 71, 1, 0),
> + PLL_RATE(1944000000, 71, 1, 0),
> + PLL_RATE(1968000000, 71, 1, 0),
> + PLL_RATE(1992000000, 71, 1, 0),
> + PLL_RATE(2016000000, 72, 1, 0),
> + PLL_RATE(2040000000, 72, 1, 0),
> + PLL_RATE(2064000000, 72, 1, 0),
> + PLL_RATE(2088000000, 72, 1, 0),
> + PLL_RATE(2112000000, 73, 1, 0),
> + { /* sentinel */ },
> +};
> +
> +static struct meson_clk_pll axg_fixed_pll = {
> + .m = {
> + .reg_off = HHI_MPLL_CNTL,
> + .shift = 0,
> + .width = 9,
> + },
> + .n = {
> + .reg_off = HHI_MPLL_CNTL,
> + .shift = 9,
> + .width = 5,
> + },
> + .od = {
> + .reg_off = HHI_MPLL_CNTL,
> + .shift = 16,
> + .width = 2,
> + },
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "fixed_pll",
> + .ops = &meson_clk_pll_ro_ops,
> + .parent_names = (const char *[]){ "xtal" },
> + .num_parents = 1,
> + .flags = CLK_GET_RATE_NOCACHE,
> + },
> +};
> +
> +static struct meson_clk_pll axg_sys_pll = {
> + .m = {
> + .reg_off = HHI_SYS_PLL_CNTL,
> + .shift = 0,
> + .width = 9,
> + },
> + .n = {
> + .reg_off = HHI_SYS_PLL_CNTL,
> + .shift = 9,
> + .width = 5,
> + },
> + .od = {
> + .reg_off = HHI_SYS_PLL_CNTL,
> + .shift = 10,
> + .width = 2,
> + },
> + .rate_table = sys_pll_rate_table,
> + .rate_count = ARRAY_SIZE(sys_pll_rate_table),
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "sys_pll",
> + .ops = &meson_clk_pll_ro_ops,
> + .parent_names = (const char *[]){ "xtal" },
> + .num_parents = 1,
> + .flags = CLK_GET_RATE_NOCACHE,
> + },
> +};
> +
> +static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
> + PLL_RATE(240000000, 40, 1, 2),
> + PLL_RATE(246000000, 41, 1, 2),
> + PLL_RATE(252000000, 42, 1, 2),
> + PLL_RATE(258000000, 43, 1, 2),
> + PLL_RATE(264000000, 44, 1, 2),
> + PLL_RATE(270000000, 45, 1, 2),
> + PLL_RATE(276000000, 46, 1, 2),
> + PLL_RATE(282000000, 47, 1, 2),
> + PLL_RATE(288000000, 48, 1, 2),
> + PLL_RATE(294000000, 49, 1, 2),
> + PLL_RATE(300000000, 50, 1, 2),
> + PLL_RATE(306000000, 51, 1, 2),
> + PLL_RATE(312000000, 52, 1, 2),
> + PLL_RATE(318000000, 53, 1, 2),
> + PLL_RATE(324000000, 54, 1, 2),
> + PLL_RATE(330000000, 55, 1, 2),
> + PLL_RATE(336000000, 56, 1, 2),
> + PLL_RATE(342000000, 57, 1, 2),
> + PLL_RATE(348000000, 58, 1, 2),
> + PLL_RATE(354000000, 59, 1, 2),
> + PLL_RATE(360000000, 60, 1, 2),
> + PLL_RATE(366000000, 61, 1, 2),
> + PLL_RATE(372000000, 62, 1, 2),
> + PLL_RATE(378000000, 63, 1, 2),
> + PLL_RATE(384000000, 64, 1, 2),
> + PLL_RATE(390000000, 65, 1, 3),
> + PLL_RATE(396000000, 66, 1, 3),
> + PLL_RATE(402000000, 67, 1, 3),
> + PLL_RATE(408000000, 68, 1, 3),
> + PLL_RATE(480000000, 40, 1, 1),
> + PLL_RATE(492000000, 41, 1, 1),
> + PLL_RATE(504000000, 42, 1, 1),
> + PLL_RATE(516000000, 43, 1, 1),
> + PLL_RATE(528000000, 44, 1, 1),
> + PLL_RATE(540000000, 45, 1, 1),
> + PLL_RATE(552000000, 46, 1, 1),
> + PLL_RATE(564000000, 47, 1, 1),
> + PLL_RATE(576000000, 48, 1, 1),
> + PLL_RATE(588000000, 49, 1, 1),
> + PLL_RATE(600000000, 50, 1, 1),
> + PLL_RATE(612000000, 51, 1, 1),
> + PLL_RATE(624000000, 52, 1, 1),
> + PLL_RATE(636000000, 53, 1, 1),
> + PLL_RATE(648000000, 54, 1, 1),
> + PLL_RATE(660000000, 55, 1, 1),
> + PLL_RATE(672000000, 56, 1, 1),
> + PLL_RATE(684000000, 57, 1, 1),
> + PLL_RATE(696000000, 58, 1, 1),
> + PLL_RATE(708000000, 59, 1, 1),
> + PLL_RATE(720000000, 60, 1, 1),
> + PLL_RATE(732000000, 61, 1, 1),
> + PLL_RATE(744000000, 62, 1, 1),
> + PLL_RATE(756000000, 63, 1, 1),
> + PLL_RATE(768000000, 64, 1, 1),
> + PLL_RATE(780000000, 65, 1, 1),
> + PLL_RATE(792000000, 66, 1, 1),
> + PLL_RATE(804000000, 67, 1, 1),
> + PLL_RATE(816000000, 68, 1, 1),
> + PLL_RATE(960000000, 40, 1, 0),
> + PLL_RATE(984000000, 41, 1, 0),
> + PLL_RATE(1008000000, 42, 1, 0),
> + PLL_RATE(1032000000, 43, 1, 0),
> + PLL_RATE(1056000000, 44, 1, 0),
> + PLL_RATE(1080000000, 45, 1, 0),
> + PLL_RATE(1104000000, 46, 1, 0),
> + PLL_RATE(1128000000, 47, 1, 0),
> + PLL_RATE(1152000000, 48, 1, 0),
> + PLL_RATE(1176000000, 49, 1, 0),
> + PLL_RATE(1200000000, 50, 1, 0),
> + PLL_RATE(1224000000, 51, 1, 0),
> + PLL_RATE(1248000000, 52, 1, 0),
> + PLL_RATE(1272000000, 53, 1, 0),
> + PLL_RATE(1296000000, 54, 1, 0),
> + PLL_RATE(1320000000, 55, 1, 0),
> + PLL_RATE(1344000000, 56, 1, 0),
> + PLL_RATE(1368000000, 57, 1, 0),
> + PLL_RATE(1392000000, 58, 1, 0),
> + PLL_RATE(1416000000, 59, 1, 0),
> + PLL_RATE(1440000000, 60, 1, 0),
> + PLL_RATE(1464000000, 61, 1, 0),
> + PLL_RATE(1488000000, 62, 1, 0),
> + PLL_RATE(1512000000, 63, 1, 0),
> + PLL_RATE(1536000000, 64, 1, 0),
> + PLL_RATE(1560000000, 65, 1, 0),
> + PLL_RATE(1584000000, 66, 1, 0),
> + PLL_RATE(1608000000, 67, 1, 0),
> + PLL_RATE(1632000000, 68, 1, 0),
> + { /* sentinel */ },
> +};
> +
> +struct pll_params_table axg_gp0_params_table[] = {
> + PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250),
> + PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000),
> + PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be),
> + PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288),
> + PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d),
> + PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000),
> +};
> +
> +static struct meson_clk_pll axg_gp0_pll = {
> + .m = {
> + .reg_off = HHI_GP0_PLL_CNTL,
> + .shift = 0,
> + .width = 9,
> + },
> + .n = {
> + .reg_off = HHI_GP0_PLL_CNTL,
> + .shift = 9,
> + .width = 5,
> + },
> + .od = {
> + .reg_off = HHI_GP0_PLL_CNTL,
> + .shift = 16,
> + .width = 2,
> + },
> + .params = {
> + .params_table = axg_gp0_params_table,
> + .params_count = ARRAY_SIZE(axg_gp0_params_table),
> + .no_init_reset = true,
> + .reset_lock_loop = true,
> + },
> + .rate_table = axg_gp0_pll_rate_table,
> + .rate_count = ARRAY_SIZE(axg_gp0_pll_rate_table),
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "gp0_pll",
> + .ops = &meson_clk_pll_ops,
> + .parent_names = (const char *[]){ "xtal" },
> + .num_parents = 1,
> + .flags = CLK_GET_RATE_NOCACHE,
> + },
> +};
> +
> +
> +static struct clk_fixed_factor axg_fclk_div2 = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2",
> + .ops = &clk_fixed_factor_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor axg_fclk_div3 = {
> + .mult = 1,
> + .div = 3,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div3",
> + .ops = &clk_fixed_factor_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor axg_fclk_div4 = {
> + .mult = 1,
> + .div = 4,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div4",
> + .ops = &clk_fixed_factor_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor axg_fclk_div5 = {
> + .mult = 1,
> + .div = 5,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div5",
> + .ops = &clk_fixed_factor_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor axg_fclk_div7 = {
> + .mult = 1,
> + .div = 7,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div7",
> + .ops = &clk_fixed_factor_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct meson_clk_mpll axg_mpll0 = {
> + .sdm = {
> + .reg_off = HHI_MPLL_CNTL7,
> + .shift = 0,
> + .width = 14,
> + },
> + .sdm_en = {
> + .reg_off = HHI_MPLL_CNTL7,
> + .shift = 15,
> + .width = 1,
> + },
> + .n2 = {
> + .reg_off = HHI_MPLL_CNTL7,
> + .shift = 16,
> + .width = 9,
> + },
> + .en = {
> + .reg_off = HHI_MPLL_CNTL7,
> + .shift = 14,
> + .width = 1,
> + },
> + .ssen = {
> + .reg_off = HHI_MPLL_CNTL,
> + .shift = 25,
> + .width = 1,
> + },
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll0",
> + .ops = &meson_clk_mpll_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct meson_clk_mpll axg_mpll1 = {
> + .sdm = {
> + .reg_off = HHI_MPLL_CNTL8,
> + .shift = 0,
> + .width = 14,
> + },
> + .sdm_en = {
> + .reg_off = HHI_MPLL_CNTL8,
> + .shift = 15,
> + .width = 1,
> + },
> + .n2 = {
> + .reg_off = HHI_MPLL_CNTL8,
> + .shift = 16,
> + .width = 9,
> + },
> + .en = {
> + .reg_off = HHI_MPLL_CNTL8,
> + .shift = 14,
> + .width = 1,
> + },
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll1",
> + .ops = &meson_clk_mpll_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct meson_clk_mpll axg_mpll2 = {
> + .sdm = {
> + .reg_off = HHI_MPLL_CNTL9,
> + .shift = 0,
> + .width = 14,
> + },
> + .sdm_en = {
> + .reg_off = HHI_MPLL_CNTL9,
> + .shift = 15,
> + .width = 1,
> + },
> + .n2 = {
> + .reg_off = HHI_MPLL_CNTL9,
> + .shift = 16,
> + .width = 9,
> + },
> + .en = {
> + .reg_off = HHI_MPLL_CNTL9,
> + .shift = 14,
> + .width = 1,
> + },
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll2",
> + .ops = &meson_clk_mpll_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct meson_clk_mpll axg_mpll3 = {
> + .sdm = {
> + .reg_off = HHI_MPLL3_CNTL0,
> + .shift = 12,
> + .width = 14,
> + },
> + .sdm_en = {
> + .reg_off = HHI_MPLL3_CNTL0,
> + .shift = 11,
> + .width = 1,
> + },
> + .n2 = {
> + .reg_off = HHI_MPLL3_CNTL0,
> + .shift = 2,
> + .width = 9,
> + },
> + .en = {
> + .reg_off = HHI_MPLL3_CNTL0,
> + .shift = 0,
> + .width = 1,
> + },
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll3",
> + .ops = &meson_clk_mpll_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +/*
> + * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers
> + * and should be modeled with their respective PLLs via the forthcoming
> + * coordinated clock rates feature
> + */
> +static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
> +static const char * const clk81_parent_names[] = {
> + "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
> + "fclk_div3", "fclk_div5"
> +};
> +
> +static struct clk_mux axg_mpeg_clk_sel = {
> + .reg = (void *)HHI_MPEG_CLK_CNTL,
> + .mask = 0x7,
> + .shift = 12,
> + .flags = CLK_MUX_READ_ONLY,
> + .table = mux_table_clk81,
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "mpeg_clk_sel",
> + .ops = &clk_mux_ro_ops,
> + /*
> + * bits 14:12 selects from 8 possible parents:
> + * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
> + * fclk_div4, fclk_div3, fclk_div5
> + */
> + .parent_names = clk81_parent_names,
> + .num_parents = ARRAY_SIZE(clk81_parent_names),
> + .flags = CLK_SET_RATE_NO_REPARENT,
> + },
> +};
> +
> +static struct clk_divider axg_mpeg_clk_div = {
> + .reg = (void *)HHI_MPEG_CLK_CNTL,
> + .shift = 0,
> + .width = 7,
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "mpeg_clk_div",
> + .ops = &clk_divider_ops,
> + .parent_names = (const char *[]){ "mpeg_clk_sel" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_gate axg_clk81 = {
> + .reg = (void *)HHI_MPEG_CLK_CNTL,
> + .bit_idx = 7,
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "clk81",
> + .ops = &clk_gate_ops,
> + .parent_names = (const char *[]){ "mpeg_clk_div" },
> + .num_parents = 1,
> + .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
> + },
> +};
> +
> +static const char * const axg_sd_emmc_clk0_parent_names[] = {
> + "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
> +
> + /*
> + * Following these parent clocks, we should also have had mpll2, mpll3
> + * and gp0_pll but these clocks are too precious to be used here. All
> + * the necessary rates for MMC and NAND operation can be acheived using
> + * xtal or fclk_div clocks
> + */
> +};
> +
> +/* SDcard clock */
> +static struct clk_mux axg_sd_emmc_b_clk0_sel = {
> + .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
> + .mask = 0x7,
> + .shift = 25,
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data) {
> + .name = "sd_emmc_b_clk0_sel",
> + .ops = &clk_mux_ops,
> + .parent_names = axg_sd_emmc_clk0_parent_names,
> + .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_divider axg_sd_emmc_b_clk0_div = {
> + .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
> + .shift = 16,
> + .width = 7,
> + .lock = &clk_lock,
> + .flags = CLK_DIVIDER_ROUND_CLOSEST,
> + .hw.init = &(struct clk_init_data) {
> + .name = "sd_emmc_b_clk0_div",
> + .ops = &clk_divider_ops,
> + .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_gate axg_sd_emmc_b_clk0 = {
> + .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
> + .bit_idx = 23,
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "sd_emmc_b_clk0",
> + .ops = &clk_gate_ops,
> + .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +/* EMMC/NAND clock */
> +static struct clk_mux axg_sd_emmc_c_clk0_sel = {
> + .reg = (void *)HHI_NAND_CLK_CNTL,
> + .mask = 0x7,
> + .shift = 9,
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data) {
> + .name = "sd_emmc_c_clk0_sel",
> + .ops = &clk_mux_ops,
> + .parent_names = axg_sd_emmc_clk0_parent_names,
> + .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_divider axg_sd_emmc_c_clk0_div = {
> + .reg = (void *)HHI_NAND_CLK_CNTL,
> + .shift = 0,
> + .width = 7,
> + .lock = &clk_lock,
> + .flags = CLK_DIVIDER_ROUND_CLOSEST,
> + .hw.init = &(struct clk_init_data) {
> + .name = "sd_emmc_c_clk0_div",
> + .ops = &clk_divider_ops,
> + .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_gate axg_sd_emmc_c_clk0 = {
> + .reg = (void *)HHI_NAND_CLK_CNTL,
> + .bit_idx = 7,
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "sd_emmc_c_clk0",
> + .ops = &clk_gate_ops,
> + .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +/* Everything Else (EE) domain gates */
> +static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
> +static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
> +static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
> +static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
> +static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
> +static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
> +static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
> +static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
> +static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
> +static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
> +static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
> +static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
> +static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
> +static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
> +static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
> +static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
> +static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
> +static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
> +static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
> +static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
> +
> +static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
> +static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
> +static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
> +static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
> +static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
> +static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
> +static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
> +static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
> +static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
> +static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
> +static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
> +
> +static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
> +static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
> +static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
> +static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
> +static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
> +static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
> +static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
> +static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
> +
> +/* Always On (AO) domain gates */
> +
> +static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
> +static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
> +static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
> +static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
> +static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
> +
> +/* Array of all clocks provided by this provider */
> +
> +static struct clk_hw_onecell_data axg_hw_onecell_data = {
> + .hws = {
> + [CLKID_SYS_PLL] = &axg_sys_pll.hw,
> + [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
> + [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
> + [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
> + [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
> + [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
> + [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
> + [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
> + [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
> + [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
> + [CLKID_CLK81] = &axg_clk81.hw,
> + [CLKID_MPLL0] = &axg_mpll0.hw,
> + [CLKID_MPLL1] = &axg_mpll1.hw,
> + [CLKID_MPLL2] = &axg_mpll2.hw,
> + [CLKID_MPLL3] = &axg_mpll3.hw,
> + [CLKID_DDR] = &axg_ddr.hw,
> + [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
> + [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
> + [CLKID_ISA] = &axg_isa.hw,
> + [CLKID_PL301] = &axg_pl301.hw,
> + [CLKID_PERIPHS] = &axg_periphs.hw,
> + [CLKID_SPICC0] = &axg_spicc_0.hw,
> + [CLKID_I2C] = &axg_i2c.hw,
> + [CLKID_RNG0] = &axg_rng0.hw,
> + [CLKID_UART0] = &axg_uart0.hw,
> + [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
> + [CLKID_SPICC1] = &axg_spicc_1.hw,
> + [CLKID_PCIE_A] = &axg_pcie_a.hw,
> + [CLKID_PCIE_B] = &axg_pcie_b.hw,
> + [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
> + [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
> + [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
> + [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
> + [CLKID_DMA] = &axg_dma.hw,
> + [CLKID_SPI] = &axg_spi.hw,
> + [CLKID_AUDIO] = &axg_audio.hw,
> + [CLKID_ETH] = &axg_eth_core.hw,
> + [CLKID_UART1] = &axg_uart1.hw,
> + [CLKID_G2D] = &axg_g2d.hw,
> + [CLKID_USB0] = &axg_usb0.hw,
> + [CLKID_USB1] = &axg_usb1.hw,
> + [CLKID_RESET] = &axg_reset.hw,
> + [CLKID_USB] = &axg_usb_general.hw,
> + [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
> + [CLKID_EFUSE] = &axg_efuse.hw,
> + [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
> + [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
> + [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
> + [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
> + [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
> + [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
> + [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
> + [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
> + [CLKID_GIC] = &axg_gic.hw,
> + [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
> + [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
> + [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
> + [CLKID_AO_IFACE] = &axg_ao_iface.hw,
> + [CLKID_AO_I2C] = &axg_ao_i2c.hw,
> + [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
> + [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
> + [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
> + [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
> + [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
> + [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
> + [NR_CLKS] = NULL,
> + },
> + .num = NR_CLKS,
> +};
> +
> +/* Convenience tables to populate base addresses in .probe */
> +
> +static struct meson_clk_pll *const axg_clk_plls[] = {
> + &axg_fixed_pll,
> + &axg_sys_pll,
> + &axg_gp0_pll,
> +};
> +
> +static struct meson_clk_mpll *const axg_clk_mplls[] = {
> + &axg_mpll0,
> + &axg_mpll1,
> + &axg_mpll2,
> + &axg_mpll3,
> +};
> +
> +static struct clk_gate *const axg_clk_gates[] = {
> + &axg_clk81,
> + &axg_ddr,
> + &axg_audio_locker,
> + &axg_mipi_dsi_host,
> + &axg_isa,
> + &axg_pl301,
> + &axg_periphs,
> + &axg_spicc_0,
> + &axg_i2c,
> + &axg_rng0,
> + &axg_uart0,
> + &axg_mipi_dsi_phy,
> + &axg_spicc_1,
> + &axg_pcie_a,
> + &axg_pcie_b,
> + &axg_hiu_reg,
> + &axg_assist_misc,
> + &axg_emmc_b,
> + &axg_emmc_c,
> + &axg_dma,
> + &axg_spi,
> + &axg_audio,
> + &axg_eth_core,
> + &axg_uart1,
> + &axg_g2d,
> + &axg_usb0,
> + &axg_usb1,
> + &axg_reset,
> + &axg_usb_general,
> + &axg_ahb_arb0,
> + &axg_efuse,
> + &axg_boot_rom,
> + &axg_ahb_data_bus,
> + &axg_ahb_ctrl_bus,
> + &axg_usb1_to_ddr,
> + &axg_usb0_to_ddr,
> + &axg_mmc_pclk,
> + &axg_vpu_intr,
> + &axg_sec_ahb_ahb3_bridge,
> + &axg_gic,
> + &axg_ao_media_cpu,
> + &axg_ao_ahb_sram,
> + &axg_ao_ahb_bus,
> + &axg_ao_iface,
> + &axg_ao_i2c,
> + &axg_sd_emmc_b_clk0,
> + &axg_sd_emmc_c_clk0,
> +};
> +
> +static struct clk_mux *const axg_clk_muxes[] = {
> + &axg_mpeg_clk_sel,
> + &axg_sd_emmc_b_clk0_sel,
> + &axg_sd_emmc_c_clk0_sel,
> +};
> +
> +static struct clk_divider *const axg_clk_dividers[] = {
> + &axg_mpeg_clk_div,
> + &axg_sd_emmc_b_clk0_div,
> + &axg_sd_emmc_c_clk0_div,
> +};
> +
> +struct clkc_data {
> + struct clk_gate *const *clk_gates;
> + unsigned int clk_gates_count;
> + struct meson_clk_mpll *const *clk_mplls;
> + unsigned int clk_mplls_count;
> + struct meson_clk_pll *const *clk_plls;
> + unsigned int clk_plls_count;
> + struct clk_mux *const *clk_muxes;
> + unsigned int clk_muxes_count;
> + struct clk_divider *const *clk_dividers;
> + unsigned int clk_dividers_count;
> + struct clk_hw_onecell_data *hw_onecell_data;
> +};
> +
> +static const struct clkc_data axg_clkc_data = {
> + .clk_gates = axg_clk_gates,
> + .clk_gates_count = ARRAY_SIZE(axg_clk_gates),
> + .clk_mplls = axg_clk_mplls,
> + .clk_mplls_count = ARRAY_SIZE(axg_clk_mplls),
> + .clk_plls = axg_clk_plls,
> + .clk_plls_count = ARRAY_SIZE(axg_clk_plls),
> + .clk_muxes = axg_clk_muxes,
> + .clk_muxes_count = ARRAY_SIZE(axg_clk_muxes),
> + .clk_dividers = axg_clk_dividers,
> + .clk_dividers_count = ARRAY_SIZE(axg_clk_dividers),
> + .hw_onecell_data = &axg_hw_onecell_data,
> +};
> +
> +static const struct of_device_id clkc_match_table[] = {
> + { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
> + {}
> +};
> +
> +static int axg_clkc_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + const struct clkc_data *clkc_data;
> + struct resource *res;
> + void __iomem *clk_base;
> + int ret, clkid, i;
> +
> + clkc_data = of_device_get_match_data(&pdev->dev);
> + if (!clkc_data)
> + return -EINVAL;
> +
> + /* Generic clocks and PLLs */
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + clk_base = devm_ioremap_resource(&pdev->dev, res);
Please use here devm_ioremap(&pdev->dev, res->start, resource_size(res))
since the HHI zone is shared with non clock related registers like the
memory power domains controls.
> + if (IS_ERR(clk_base)) {
> + dev_err(&pdev->dev, "Unable to map clk base\n");
> + return -ENXIO;
> + }
> +
> + /* Populate base address for PLLs */
> + for (i = 0; i < clkc_data->clk_plls_count; i++)
> + clkc_data->clk_plls[i]->base = clk_base;
> +
> + /* Populate base address for MPLLs */
> + for (i = 0; i < clkc_data->clk_mplls_count; i++)
> + clkc_data->clk_mplls[i]->base = clk_base;
> +
> + /* Populate base address for gates */
> + for (i = 0; i < clkc_data->clk_gates_count; i++)
> + clkc_data->clk_gates[i]->reg = clk_base +
> + (u64)clkc_data->clk_gates[i]->reg;
> +
> + /* Populate base address for muxes */
> + for (i = 0; i < clkc_data->clk_muxes_count; i++)
> + clkc_data->clk_muxes[i]->reg = clk_base +
> + (u64)clkc_data->clk_muxes[i]->reg;
> +
> + /* Populate base address for dividers */
> + for (i = 0; i < clkc_data->clk_dividers_count; i++)
> + clkc_data->clk_dividers[i]->reg = clk_base +
> + (u64)clkc_data->clk_dividers[i]->reg;
> +
> + for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) {
> + /* array might be sparse */
> + if (!clkc_data->hw_onecell_data->hws[clkid])
> + continue;
> +
> + ret = devm_clk_hw_register(dev,
> + clkc_data->hw_onecell_data->hws[clkid]);
> + if (ret) {
> + dev_err(&pdev->dev, "Clock registration failed\n");
> + return ret;
> + }
> + }
> +
> + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
> + clkc_data->hw_onecell_data);
> +}
> +
> +static struct platform_driver axg_driver = {
> + .probe = axg_clkc_probe,
> + .driver = {
> + .name = "axg-clkc",
> + .of_match_table = clkc_match_table,
> + },
> +};
> +
> +builtin_platform_driver(axg_driver);
> diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
> new file mode 100644
> index 000000000000..ce0bafdb6b28
> --- /dev/null
> +++ b/drivers/clk/meson/axg.h
> @@ -0,0 +1,126 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2016 AmLogic, Inc.
> + * Author: Michael Turquette <mturquette@baylibre.com>
> + *
> + * Copyright (c) 2017 Amlogic, inc.
> + * Author: Qiufang Dai <qiufang.dai@amlogic.com>
> + *
> + */
> +#ifndef __AXG_H
> +#define __AXG_H
> +
> +/*
> + * Clock controller register offsets
> + *
> + * Register offsets from the data sheet must be multiplied by 4 before
> + * adding them to the base address to get the right value.
> + */
> +#define HHI_GP0_PLL_CNTL 0x40
> +#define HHI_GP0_PLL_CNTL2 0x44
> +#define HHI_GP0_PLL_CNTL3 0x48
> +#define HHI_GP0_PLL_CNTL4 0x4c
> +#define HHI_GP0_PLL_CNTL5 0x50
> +#define HHI_GP0_PLL_STS 0x54
> +#define HHI_GP0_PLL_CNTL1 0x58
> +#define HHI_HIFI_PLL_CNTL 0x80
> +#define HHI_HIFI_PLL_CNTL2 0x84
> +#define HHI_HIFI_PLL_CNTL3 0x88
> +#define HHI_HIFI_PLL_CNTL4 0x8C
> +#define HHI_HIFI_PLL_CNTL5 0x90
> +#define HHI_HIFI_PLL_STS 0x94
> +#define HHI_HIFI_PLL_CNTL1 0x98
> +
> +#define HHI_XTAL_DIVN_CNTL 0xbc
> +#define HHI_GCLK2_MPEG0 0xc0
> +#define HHI_GCLK2_MPEG1 0xc4
> +#define HHI_GCLK2_MPEG2 0xc8
> +#define HHI_GCLK2_OTHER 0xd0
> +#define HHI_GCLK2_AO 0xd4
> +#define HHI_PCIE_PLL_CNTL 0xd8
> +#define HHI_PCIE_PLL_CNTL1 0xdC
> +#define HHI_PCIE_PLL_CNTL2 0xe0
> +#define HHI_PCIE_PLL_CNTL3 0xe4
> +#define HHI_PCIE_PLL_CNTL4 0xe8
> +#define HHI_PCIE_PLL_CNTL5 0xec
> +#define HHI_PCIE_PLL_CNTL6 0xf0
> +#define HHI_PCIE_PLL_STS 0xf4
> +
> +#define HHI_MEM_PD_REG0 0x100
> +#define HHI_VPU_MEM_PD_REG0 0x104
> +#define HHI_VIID_CLK_DIV 0x128
> +#define HHI_VIID_CLK_CNTL 0x12c
> +
> +#define HHI_GCLK_MPEG0 0x140
> +#define HHI_GCLK_MPEG1 0x144
> +#define HHI_GCLK_MPEG2 0x148
> +#define HHI_GCLK_OTHER 0x150
> +#define HHI_GCLK_AO 0x154
> +#define HHI_SYS_CPU_CLK_CNTL1 0x15c
> +#define HHI_SYS_CPU_RESET_CNTL 0x160
> +#define HHI_VID_CLK_DIV 0x164
> +#define HHI_SPICC_HCLK_CNTL 0x168
> +
> +#define HHI_MPEG_CLK_CNTL 0x174
> +#define HHI_VID_CLK_CNTL 0x17c
> +#define HHI_TS_CLK_CNTL 0x190
> +#define HHI_VID_CLK_CNTL2 0x194
> +#define HHI_SYS_CPU_CLK_CNTL0 0x19c
> +#define HHI_VID_PLL_CLK_DIV 0x1a0
> +#define HHI_VPU_CLK_CNTL 0x1bC
> +
> +#define HHI_VAPBCLK_CNTL 0x1F4
> +
> +#define HHI_GEN_CLK_CNTL 0x228
> +
> +#define HHI_VDIN_MEAS_CLK_CNTL 0x250
> +#define HHI_NAND_CLK_CNTL 0x25C
> +#define HHI_SD_EMMC_CLK_CNTL 0x264
> +
> +#define HHI_MPLL_CNTL 0x280
> +#define HHI_MPLL_CNTL2 0x284
> +#define HHI_MPLL_CNTL3 0x288
> +#define HHI_MPLL_CNTL4 0x28C
> +#define HHI_MPLL_CNTL5 0x290
> +#define HHI_MPLL_CNTL6 0x294
> +#define HHI_MPLL_CNTL7 0x298
> +#define HHI_MPLL_CNTL8 0x29C
> +#define HHI_MPLL_CNTL9 0x2A0
> +#define HHI_MPLL_CNTL10 0x2A4
> +
> +#define HHI_MPLL3_CNTL0 0x2E0
> +#define HHI_MPLL3_CNTL1 0x2E4
> +#define HHI_PLL_TOP_MISC 0x2E8
> +
> +#define HHI_SYS_PLL_CNTL1 0x2FC
> +#define HHI_SYS_PLL_CNTL 0x300
> +#define HHI_SYS_PLL_CNTL2 0x304
> +#define HHI_SYS_PLL_CNTL3 0x308
> +#define HHI_SYS_PLL_CNTL4 0x30c
> +#define HHI_SYS_PLL_CNTL5 0x310
> +#define HHI_SYS_PLL_STS 0x314
> +#define HHI_DPLL_TOP_I 0x318
> +#define HHI_DPLL_TOP2_I 0x31C
> +
> +/*
> + * CLKID index values
> + *
> + * These indices are entirely contrived and do not map onto the hardware.
> + * It has now been decided to expose everything by default in the DT header:
> + * include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want
> + * to expose, such as the internal muxes and dividers of composite clocks,
> + * will remain defined here.
> + */
> +#define CLKID_MPEG_SEL 8
> +#define CLKID_MPEG_DIV 9
> +#define CLKID_SD_EMMC_B_CLK0_SEL 61
> +#define CLKID_SD_EMMC_B_CLK0_DIV 62
> +#define CLKID_SD_EMMC_C_CLK0_SEL 63
> +#define CLKID_SD_EMMC_C_CLK0_DIV 64
> +
> +#define NR_CLKS 65
> +
> +/* include the CLKIDs that have been made part of the DT binding */
> +#include <dt-bindings/clock/axg-clkc.h>
> +
> +#endif /* __AXG_H */
>
Apart the devm_ioremap,
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
^ permalink raw reply
* Re: [PATCH v2 34/35] clocksource/drivers/Kconfig: Support andestech atcpit100 timer
From: Daniel Lezcano @ 2017-12-07 8:39 UTC (permalink / raw)
To: Greentime Hu, greentime-MUIXKm3Oiri1Z/+hSey0Gg,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
linux-arch-u79uwXL29TY76Z2rM5mHXA, tglx-hfZtesqFncYOwBW4kG4KsQ,
jason-NLaQJdtUoK4Be96aLqz0jA, marc.zyngier-5wv7dgnIgG8,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, netdev-u79uwXL29TY76Z2rM5mHXA,
deanbo422-Re5JQEeQqe8AvxtiuMwx3w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
viro-RmSDqhL/yNMiFSDQTTA3OLVCufUGDwFn,
dhowells-H+wXaHxf7aLQT0dZR+AlfA, will.deacon-5wv7dgnIgG8,
linux-serial-u79uwXL29TY76Z2rM5mHXA
Cc: Rick Chen
In-Reply-To: <1a22db002413ff60851737736a86b40c38877220.1511785528.git.green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On 27/11/2017 13:28, Greentime Hu wrote:
> From: Rick Chen <rickchen36-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> Add CLKSRC_ATCPIT100 for Andestech atcpit100 timer selection.
> It often be used in Andestech AE3XX platform.
>
> Signed-off-by: Rick Chen <rickchen36-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Greentime Hu <green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> drivers/clocksource/Kconfig | 6 ++++++
> drivers/clocksource/Makefile | 1 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index cc60620..591362a 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -615,4 +615,10 @@ config CLKSRC_ST_LPC
> Enable this option to use the Low Power controller timer
> as clocksource.
>
> +config CLKSRC_ATCPIT100
> + bool "Clocksource for AE3XX platform" if COMPILE_TEST
> + depends on GENERIC_CLOCKEVENTS && HAS_IOMEM
You can remove the GENERIC_CLOCKEVENTS as now it is factored out in the
higher menuconfig option.
--
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^ permalink raw reply
* Re: [PATCH] ARM64: dts: amlogic: use generic bus node names
From: Neil Armstrong @ 2017-12-07 8:35 UTC (permalink / raw)
To: Kevin Hilman, linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Stephen Boyd,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20171206193005.24171-1-khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
On 06/12/2017 20:30, Kevin Hilman wrote:
> The DT spec recommends that node-names have generic names like "bus".
> Fix that in the Amlogic DTs, while leaving the label names to have more
> SoC-specific names that match with the HW documentation.
>
> Suggested-by: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> Signed-off-by: Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> ---
> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 6 +++---
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index b932a784b02a..e7213eb53958 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -113,7 +113,7 @@
> #size-cells = <2>;
> ranges;
>
> - cbus: cbus@ffd00000 {
> + cbus: bus@ffd00000 {
> compatible = "simple-bus";
> reg = <0x0 0xffd00000 0x0 0x25000>;
> #address-cells = <2>;
> @@ -175,7 +175,7 @@
> };
> };
>
> - aobus: aobus@ff800000 {
> + aobus: bus@ff800000 {
> compatible = "simple-bus";
> reg = <0x0 0xff800000 0x0 0x100000>;
> #address-cells = <2>;
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> index 7cdbf58a062f..6cb3c2a52baf 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> @@ -211,7 +211,7 @@
> #size-cells = <2>;
> ranges;
>
> - cbus: cbus@c1100000 {
> + cbus: bus@c1100000 {
> compatible = "simple-bus";
> reg = <0x0 0xc1100000 0x0 0x100000>;
> #address-cells = <2>;
> @@ -366,7 +366,7 @@
> };
> };
>
> - aobus: aobus@c8100000 {
> + aobus: bus@c8100000 {
> compatible = "simple-bus";
> reg = <0x0 0xc8100000 0x0 0x100000>;
> #address-cells = <2>;
> @@ -453,7 +453,7 @@
> };
> };
>
> - hiubus: hiubus@c883c000 {
> + hiubus: bus@c883c000 {
> compatible = "simple-bus";
> reg = <0x0 0xc883c000 0x0 0x2000>;
> #address-cells = <2>;
>
Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH] video: hd44780: Add hd44780 lcd display driver
From: Lars Poeschel @ 2017-12-07 8:33 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: David Airlie, Rob Herring, Mark Rutland,
Bartlomiej Zolnierkiewicz, Manuel Schölling,
Greg Kroah-Hartman, Daniel Vetter, Stafford Horne,
Christophe Leroy, Randy Dunlap, Kate Stewart, Philippe Ombredanne,
Sean Paul, Thomas Gleixner, DRI Development,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <CAMuHMdUn-wx7YC=QWazb4e-vJGts8iXbkC64NYiEjha-kQPKLg@mail.gmail.com>
On Wed, Dec 6, 2017 at 16:04:10 CET Geert Uytterhoeven wrote:
> Hi Lars,
>
> On Wed, Dec 6, 2017 at 2:52 PM, Lars Poeschel <poeschel@lemonage.de> wrote:
> > This adds a console driver for hd44780 based character lcd displays and
> > clones. The driver currently supports 20x4 character displays with
> > character ROMs A00 and A02.
> > The hardware wirings to the display have to be supplied to the kernel in
> > the devicetree. The binding doc has the necessary information.
> > There are also tons of these cheap displays sold with a serial
> > interface. Many of them use a simple pcf8574 gpio expanders. An example
> > for using that kind of display is also in the binding doc.
> >
> > Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
>
> Thanks for your patch!
>
> > ---
> >
> > .../bindings/video/console/hd44780con.txt | 42 ++
> > drivers/video/console/Kconfig | 13 +
> > drivers/video/console/Makefile | 1 +
> > drivers/video/console/hd44780con.c | 676
> > +++++++++++++++++++++
> I'm wondering if you could implement this on top of the existing charlcd
> framework:
>
> drivers/auxdisplay/charlcd.c
> include/misc/charlcd.h
>
> which can use the existing hd44780 backend:
>
> Documentation/devicetree/bindings/auxdisplay/hit,hd44780.txt
> drivers/auxdisplay/hd44780.c
>
> That way it can be used on other character LCDs, like the one supported by
> drivers/auxdisplay/panel.c.
Oh! Yes, this is a very interesting idea! This would involve multiple steps
until this would be useful for me, but I will definitely have a look at this!
So, please drop my patch for now. If for some reason in the future I find,
that it should go upstream, I will submit it again.
BTW thanks for the hint about the hd44780 charlcd backend. I did not know
about this. My hd44780 console driver is quite a bit old. I just found time to
clean up, rebase, test and submit it now.
Regards,
Lars
^ permalink raw reply
* [RESEND PATCH V2] ARM: dts: introduce the sama5d2 ptc ek board
From: Ludovic Desroches @ 2017-12-07 8:24 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: nicolas.ferre-UWL1GkI3JZL3oGB3hsPCZA,
alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Ludovic Desroches
In-Reply-To: <20171206065844.27689-1-ludovic.desroches-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
Add the official SAMA5D2 Peripheral Touch Controller Evaluation
Kit board.
Signed-off-by: Ludovic Desroches <ludovic.desroches-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
---
Resend: Put SPDX-License-Identifier at the beginning of the file.
Changes:
- v2:
- remove memory node
- use SPDX-License-Identifier
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 401 ++++++++++++++++++++++++++++++
2 files changed, 402 insertions(+)
create mode 100644 arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 043d7c720d0c..ed60582eb1da 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -48,6 +48,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
dtb-$(CONFIG_SOC_SAM_V7) += \
at91-kizbox2.dtb \
at91-sama5d27_som1_ek.dtb \
+ at91-sama5d2_ptc_ek.dtb \
at91-sama5d2_xplained.dtb \
at91-sama5d3_xplained.dtb \
at91-tse850-3.dtb \
diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
new file mode 100644
index 000000000000..186cb03e2672
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
@@ -0,0 +1,401 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * at91-sama5d2_ptc_ek.dts - Device Tree file for SAMA5D2 PTC EK board
+ *
+ * Copyright (C) 2017 Microchip/Atmel,
+ * 2017 Wenyou Yang <wenyou.yang-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
+ * 2017 Ludovic Desroches <ludovic.desroches-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
+ */
+/dts-v1/;
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+#include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Atmel SAMA5D2 PTC EK";
+ compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5";
+
+ aliases {
+ serial0 = &uart0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <24000000>;
+ };
+ };
+
+ ahb {
+ usb0: gadget@300000 {
+ atmel,vbus-gpio = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usba_vbus>;
+ status = "okay";
+ };
+
+ usb1: ohci@400000 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <0
+ &pioA PIN_PB12 GPIO_ACTIVE_HIGH
+ 0
+ >;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ status = "okay";
+ };
+
+ usb2: ehci@500000 {
+ status = "okay";
+ };
+
+ ebi: ebi@10000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand_default>;
+ status = "okay"; /* conflicts with sdmmc1 and qspi0 */
+
+ nand_controller: nand-controller {
+ status = "okay";
+
+ nand@3 {
+ reg = <0x3 0x0 0x2>;
+ atmel,rb = <0>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader@40000 {
+ label = "bootloader";
+ reg = <0x40000 0xc0000>;
+ };
+
+ bootloaderenv@0x100000 {
+ label = "bootloader env";
+ reg = <0x100000 0x40000>;
+ };
+
+ bootloaderenvred@0x140000 {
+ label = "bootloader env redundant";
+ reg = <0x140000 0x40000>;
+ };
+
+ dtb@180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x1f800000>;
+ };
+ };
+ };
+ };
+ };
+
+ sdmmc0: sdio-host@a0000000 {
+ bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_default>;
+ non-removable;
+ mmc-ddr-1_8v;
+ status = "okay";
+ };
+
+ apb {
+ spi0: spi@f8000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0_default>;
+ status = "okay";
+ };
+
+ macb0: ethernet@f8008000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>;
+ phy-mode = "rmii";
+ status = "okay";
+
+ ethernet-phy@1 {
+ reg = <0x1>;
+ interrupt-parent = <&pioA>;
+ interrupts = <56 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+
+ uart0: serial@f801c000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+ };
+
+ uart2: serial@f8024000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_default>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+ };
+
+ i2c0: i2c@f8028000 {
+ dmas = <0>, <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ status = "okay";
+ };
+
+ flx0: flexcom@f8034000 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+
+ i2c2: i2c@600 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <0>, <0>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&flx0_clk>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx0_default>;
+ atmel,fifo-size = <16>;
+ status = "okay";
+ };
+ };
+
+ shdwc@f8048010 {
+ atmel,shdwc-debouncer = <976>;
+
+ input@0 {
+ reg = <0>;
+ atmel,wakeup-type = "low";
+ };
+ };
+
+ watchdog@f8048040 {
+ status = "okay";
+ };
+
+ spi1: spi@fc000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+ status = "okay";
+ };
+
+ i2c1: i2c@fc028000 {
+ dmas = <0>, <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ status = "okay";
+
+ at24@50 {
+ compatible = "24c02";
+ reg = <0x50>;
+ pagesize = <8>;
+ };
+ };
+
+ pinctrl@fc038000 {
+ pinctrl_flx0_default: flx0_default {
+ pinmux = <PIN_PB28__FLEXCOM0_IO0>,
+ <PIN_PB29__FLEXCOM0_IO1>;
+ bias-disable;
+ };
+
+ pinctrl_i2c0_default: i2c0_default {
+ pinmux = <PIN_PD21__TWD0>,
+ <PIN_PD22__TWCK0>;
+ bias-disable;
+ };
+
+ pinctrl_i2c1_default: i2c1_default {
+ pinmux = <PIN_PC6__TWD1>,
+ <PIN_PC7__TWCK1>;
+ bias-disable;
+ };
+
+ pinctrl_key_gpio_default: key_gpio_default {
+ pinmux = <PIN_PA10__GPIO>;
+ bias-pull-up;
+ };
+
+ pinctrl_led_gpio_default: led_gpio_default {
+ pinmux = <PIN_PB6__GPIO>,
+ <PIN_PB8__GPIO>,
+ <PIN_PB10__GPIO>;
+ bias-pull-up;
+ };
+
+ pinctrl_macb0_default: macb0_default {
+ pinmux = <PIN_PB14__GTXCK>,
+ <PIN_PB15__GTXEN>,
+ <PIN_PB16__GRXDV>,
+ <PIN_PB17__GRXER>,
+ <PIN_PB18__GRX0>,
+ <PIN_PB19__GRX1>,
+ <PIN_PB20__GTX0>,
+ <PIN_PB21__GTX1>,
+ <PIN_PB22__GMDC>,
+ <PIN_PB23__GMDIO>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_phy_irq: macb0_phy_irq {
+ pinmux = <PIN_PB24__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_nand_default: nand_default {
+ re_we_data {
+ pinmux = <PIN_PA22__D0>,
+ <PIN_PA23__D1>,
+ <PIN_PA24__D2>,
+ <PIN_PA25__D3>,
+ <PIN_PA26__D4>,
+ <PIN_PA27__D5>,
+ <PIN_PA28__D6>,
+ <PIN_PA29__D7>,
+ <PIN_PA30__NWE_NANDWE>,
+ <PIN_PB2__NRD_NANDOE>;
+ bias-pull-up;
+ };
+
+ ale_cle_rdy_cs {
+ pinmux = <PIN_PB0__A21_NANDALE>,
+ <PIN_PB1__A22_NANDCLE>,
+ <PIN_PC8__NANDRDY>,
+ <PIN_PA31__NCS3>;
+ bias-pull-up;
+ };
+ };
+
+ pinctrl_sdmmc0_default: sdmmc0_default {
+ cmd_data {
+ pinmux = <PIN_PA1__SDMMC0_CMD>,
+ <PIN_PA2__SDMMC0_DAT0>,
+ <PIN_PA3__SDMMC0_DAT1>,
+ <PIN_PA4__SDMMC0_DAT2>,
+ <PIN_PA5__SDMMC0_DAT3>,
+ <PIN_PA6__SDMMC0_DAT4>,
+ <PIN_PA7__SDMMC0_DAT5>,
+ <PIN_PA8__SDMMC0_DAT6>,
+ <PIN_PA9__SDMMC0_DAT7>;
+ bias-pull-up;
+ };
+
+ ck_cd_vddsel {
+ pinmux = <PIN_PA0__SDMMC0_CK>,
+ <PIN_PA11__SDMMC0_VDDSEL>,
+ <PIN_PA13__SDMMC0_CD>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_spi0_default: spi0_default {
+ pinmux = <PIN_PA14__SPI0_SPCK>,
+ <PIN_PA15__SPI0_MOSI>,
+ <PIN_PA16__SPI0_MISO>,
+ <PIN_PA17__SPI0_NPCS0>;
+ bias-disable;
+ };
+
+ pinctrl_spi1_default: spi1_default {
+ pinmux = <PIN_PC1__SPI1_SPCK>,
+ <PIN_PC2__SPI1_MOSI>,
+ <PIN_PC3__SPI1_MISO>,
+ <PIN_PC4__SPI1_NPCS0>;
+ bias-disable;
+ };
+
+ pinctrl_uart0_default: uart0_default {
+ pinmux = <PIN_PB26__URXD0>,
+ <PIN_PB27__UTXD0>;
+ bias-disable;
+ };
+
+ pinctrl_uart2_default: uart2_default {
+ pinmux = <PIN_PD23__URXD2>,
+ <PIN_PD24__UTXD2>;
+ bias-disable;
+ };
+
+ pinctrl_usb_default: usb_default {
+ pinmux = <PIN_PB12__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_usba_vbus: usba_vbus {
+ pinmux = <PIN_PB11__GPIO>;
+ bias-disable;
+ };
+
+ };
+
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_key_gpio_default>;
+
+ bp1 {
+ label = "PB_USER";
+ gpios = <&pioA PIN_PA10 GPIO_ACTIVE_LOW>;
+ linux,code = <0x104>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led_gpio_default>;
+ status = "okay";
+
+ red {
+ label = "red";
+ gpios = <&pioA PIN_PB10 GPIO_ACTIVE_HIGH>;
+ };
+
+ green {
+ label = "green";
+ gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>;
+ };
+
+ blue {
+ label = "blue";
+ gpios = <&pioA PIN_PB6 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
--
2.12.2
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^ permalink raw reply related
* Re: [PATCH V6 01/12] drivers: move clock common macros out from vendor directories
From: Chunyan Zhang @ 2017-12-07 8:08 UTC (permalink / raw)
To: Stephen Boyd
Cc: Chunyan Zhang, Michael Turquette, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, linux-clk,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Arnd Bergmann, Mark Brown, Xiaolong Zhang, Ben Li, Orson Zhai
In-Reply-To: <20171207064723.GV4283-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On 7 December 2017 at 14:47, Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> wrote:
> On 11/27, Chunyan Zhang wrote:
>> These macros are used by more than one SoC vendor platforms, avoid to
>> have many copies of these code, this patch moves them to the common
>> clock directory which every clock drivers can access to.
>>
>> Signed-off-by: Chunyan Zhang <chunyan.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>
>> ---
>> drivers/clk/clk_common.h | 60 ++++++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 60 insertions(+)
>> create mode 100644 drivers/clk/clk_common.h
>>
>> diff --git a/drivers/clk/clk_common.h b/drivers/clk/clk_common.h
>> new file mode 100644
>> index 0000000..21e93d2
>> --- /dev/null
>> +++ b/drivers/clk/clk_common.h
>> @@ -0,0 +1,60 @@
>> +/*
>> + * drivers/clk/clk_common.h
>
> We don't need this in the file too. Please remove this line.
>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0
>> + */
>> +
>> +#ifndef _CLK_COMMON_H_
>> +#define _CLK_COMMON_H_
>> +
>> +#include <linux/clk-provider.h>
>
> Maybe these macros should just go into clk-provider.h?
Ok. And I will also remove the same macros from sunxi-ng/ccu_common.h
and zte/clk.h.
>
>> +
>> +#define CLK_HW_INIT(_name, _parent, _ops, _flags) \
>> + (&(struct clk_init_data) { \
>> + .flags = _flags, \
>> + .name = _name, \
>> + .parent_names = (const char *[]) { _parent }, \
>> + .num_parents = 1, \
>> + .ops = _ops, \
>> + })
>
> Hopefully we don't extend the init structure anymore to have
> something else. I guess we'll do something if that happens.
>
>> +
>> +#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
>> + (&(struct clk_init_data) { \
>> + .flags = _flags, \
>> + .name = _name, \
>> + .parent_names = _parents, \
>> + .num_parents = ARRAY_SIZE(_parents), \
>> + .ops = _ops, \
>> + })
>> +
>> +#define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
>> + (&(struct clk_init_data) { \
>> + .flags = _flags, \
>> + .name = _name, \
>> + .parent_names = NULL, \
>> + .num_parents = 0, \
>> + .ops = _ops, \
>> + })
>> +
>> +#define CLK_FIXED_FACTOR(_struct, _name, _parent, \
>> + _div, _mult, _flags) \
>> + struct clk_fixed_factor _struct = { \
>> + .div = _div, \
>> + .mult = _mult, \
>> + .hw.init = CLK_HW_INIT(_name, \
>> + _parent, \
>> + &clk_fixed_factor_ops, \
>> + _flags), \
>> + }
>> +
>> +#define CLK_FIXED_RATE(_struct, _name, _flags, \
>> + _fixed_rate, _fixed_accuracy) \
>> + struct clk_fixed_rate _struct = { \
>> + .fixed_rate = _fixed_rate, \
>> + .fixed_accuracy = _fixed_accuracy, \
>> + .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
>> + &clk_fixed_rate_ops, \
>> + _flags), \
>> + }
>
> Maybe don't add this one? Usually fixed rate clks come from DT.
Ok, will also move the fixed rate clks from our driver to DT.
Thanks,
Chunyan
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
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^ permalink raw reply
* [PATCH] ARM: dts: sunxi: add H3/H5 uart2 rts/cts bindings
From: Nuno Gonçalves @ 2017-12-07 8:07 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Currently there are already bindings for uart1 and uart3 but uart2 was
lacking.
Tested on H2+ (H3) and confirmed to be identical on H3 and H5 datasheets.
Signed-off-by: Nuno Goncalves <nunojpg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 8d40c00d64bb..e0e0551b3f05 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -377,6 +377,11 @@
function = "uart2";
};
+ uart2_rts_cts_pins: uart2_rts_cts {
+ pins = "PA2", "PA3";
+ function = "uart2";
+ };
+
uart3_pins: uart3 {
pins = "PA13", "PA14";
function = "uart3";
--
2.11.0
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^ permalink raw reply related
* Re: [PATCH v3 2/3] clk: hisilicon: Add support for Hi3660 stub clocks
From: Leo Yan @ 2017-12-07 8:04 UTC (permalink / raw)
To: Stephen Boyd
Cc: Xu YiPing, mturquette, robh+dt, mark.rutland, xuwei5,
catalin.marinas, will.deacon, xuejiancheng, wenpan, zhangfei.gao,
guodong.xu, zhongkaihua, chenjun14, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, suzhuangluan, xuezhiliang,
kevin.wangtao
In-Reply-To: <20171207070550.GY4283@codeaurora.org>
On Wed, Dec 06, 2017 at 11:05:50PM -0800, Stephen Boyd wrote:
> On 11/17, Xu YiPing wrote:
> > From: Kaihua Zhong <zhongkaihua@huawei.com>
> > +
> > +static struct clk_hw *hi3660_stub_clk_hw_get(struct of_phandle_args *clkspec,
> > + void *data)
> > +{
> > + unsigned int idx = clkspec->args[0];
> > +
> > + if (idx > HI3660_CLK_STUB_NUM) {
>
> This should be >=
>
> > + }
> > +
> > + return &hi3660_stub_clks[idx].hw;
> > +}
> > +
> > +static int hi3660_stub_clk_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct resource *res;
> > + unsigned int i;
> > + int ret;
> > +
> > + /* Use mailbox client without blocking */
> > + stub_clk_chan.cl.dev = dev;
> > + stub_clk_chan.cl.tx_done = NULL;
> > + stub_clk_chan.cl.tx_block = false;
> > + stub_clk_chan.cl.knows_txdone = false;
> > +
> > + /* Allocate mailbox channel */
> > + stub_clk_chan.mbox = mbox_request_channel(&stub_clk_chan.cl, 0);
> > + if (IS_ERR(stub_clk_chan.mbox))
> > + return PTR_ERR(stub_clk_chan.mbox);
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + freq_reg = devm_ioremap(dev, res->start, resource_size(res));
> > + if (IS_ERR(freq_reg))
>
> Pretty sure this returns NULL on failure, not an error pointer.
>
> > + return -ENOMEM;
> > +
> > + freq_reg += HI3660_STUB_CLOCK_DATA;
> > +
> > + for (i = 0; i < HI3660_CLK_STUB_NUM; i++) {
> > + ret = devm_clk_hw_register(&pdev->dev, &hi3660_stub_clks[i].hw);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + ret = of_clk_add_hw_provider(pdev->dev.of_node, hi3660_stub_clk_hw_get,
> > + hi3660_stub_clks);
>
> This can use devm
>
> > + return ret;
> > +}
> > +
>
> I fixed it all and merged into clk-next.
Ah, very appreciate your help, Stephen.
Thanks,
Leo Yan
^ permalink raw reply
* RE: [PATCH v2] arm64: dts: ls1088a: Add USB support
From: Yinbo Zhu @ 2017-12-07 7:33 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Mark Rutland, Catalin Marinas ), Will Deacon ),
Harninder Rai, Raghav Dogra, Ashish Kumar, Andy Tang,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
open list
In-Reply-To: <VI1PR04MB1262DD3C6A18257DEE2E907DE9200-mr6QIVyDiCGbtYzA8xQqo89NdZoXdze2vxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
Hi shawn guo,
If my patch has no other issue,
Can you help me push it to upstream.
Thanks.
BRs.
-----Original Message-----
From: Yinbo Zhu
Sent: Wednesday, November 22, 2017 9:32 AM
To: 'Shawn Guo' <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: 'Rob Herring' <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>; 'Mark Rutland' <mark.rutland-AbSShOkvfpQ@public.gmane.orgm>; 'Catalin Marinas )' <catalin.marinas-5wv7dgnIgG8@public.gmane.org>; 'Will Deacon )' <will.deacon-5wv7dgnIgG8@public.gmane.org>; Harninder Rai <harninder.rai-3arQi8VN3Tc@public.gmane.org>; 'Raghav Dogra' <raghav.dogra-3arQi8VN3Tc@public.gmane.org>; Ashish Kumar <ashish.kumar-3arQi8VN3Tc@public.gmane.org>; Andy Tang <andy.tang@nxp.com>; 'open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS' <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; 'linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org' <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>; 'open list' <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Subject: RE: [PATCH v2] arm64: dts: ls1088a: Add USB support
Hi
-----Original Message-----
From: Yinbo Zhu
Sent: Tuesday, November 14, 2017 4:00 PM
To: 'Shawn Guo' <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: 'Rob Herring' <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>; 'Mark Rutland' <mark.rutland-AbSShOkvfpQ@public.gmane.orgm>; 'Catalin Marinas )' <catalin.marinas-5wv7dgnIgG8@public.gmane.org>; 'Will Deacon )' <will.deacon-5wv7dgnIgG8@public.gmane.org>; Harninder Rai <harninder.rai-3arQi8VN3Tc@public.gmane.org>; 'Raghav Dogra' <raghav.dogra-3arQi8VN3Tc@public.gmane.org>; Ashish Kumar <ashish.kumar-3arQi8VN3Tc@public.gmane.org>; Andy Tang <andy.tang@nxp.com>; 'open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS' <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; 'linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org' <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>; 'open list' <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Subject: RE: [PATCH v2] arm64: dts: ls1088a: Add USB support
-----Original Message-----
From: Yinbo Zhu
Sent: Tuesday, October 24, 2017 5:15 PM
To: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>; Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>; Catalin Marinas ) <catalin.marinas-5wv7dgnIgG8@public.gmane.org>; Will Deacon ) <will.deacon@arm.com>; Harninder Rai <harninder.rai-3arQi8VN3Tc@public.gmane.org>; Raghav Dogra <raghav.dogra@nxp.com>; Ashish Kumar <ashish.kumar-3arQi8VN3Tc@public.gmane.org>; Andy Tang <andy.tang-3arQi8VN3Tc@public.gmane.org>; open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; open list <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH v2] arm64: dts: ls1088a: Add USB support
-----Original Message-----
From: Shawn Guo [mailto:shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
Sent: Friday, September 22, 2017 2:55 PM
To: Yinbo Zhu <yinbo.zhu-3arQi8VN3Tc@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>; Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>; Catalin Marinas ) <catalin.marinas-5wv7dgnIgG8@public.gmane.org>; Will Deacon ) <will.deacon@arm.com>; Harninder Rai <harninder.rai-3arQi8VN3Tc@public.gmane.org>; Raghav Dogra <raghav.dogra@nxp.com>; Ashish Kumar <ashish.kumar-3arQi8VN3Tc@public.gmane.org>; Andy Tang <andy.tang-3arQi8VN3Tc@public.gmane.org>; open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] arm64: dts: ls1088a: Add USB support
On Wed, Sep 13, 2017 at 05:10:09PM +0800, yinbo.zhu-3arQi8VN3Tc@public.gmane.org wrote:
> From: "yinbo.zhu" <yinbo.zhu-3arQi8VN3Tc@public.gmane.org>
>
> Fix the issue that usb is not detected on ls1088ardb
>It's not really about fixing issue but adding support.
The patch had been tested on upstream 4.14 code, it can fix the issue.
>
> Signed-off-by: yinbo.zhu <yinbo.zhu-3arQi8VN3Tc@public.gmane.org>
> Signed-off-by: Ran Wang <ran.wang_1-3arQi8VN3Tc@public.gmane.org>
> ---
>You should better have a version history here to tell what's changed between version.
>I will add a version history on next v3 patch
Hi,
I had modified the code as v4 version,
https://patchwork.kernel.org/patch/10027393/
please check.
Thanks,
BRs
> arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 8 ++++++++
> arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 20 ++++++++++++++++++++
> 2 files changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
> index 213abb72de93..6c3c3bc4b681 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
> @@ -118,6 +118,14 @@
> status = "okay";
> };
>
> +&usb0 {
> + status = "okay";
> +};
> +
> +&usb1 {
> + status = "okay";
> +};
> +
> &esdhc {
>Please sort these labeled nodes alphabetically.
>Shawn
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> index c144d06a6e33..c23fede8cf5d 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> @@ -359,6 +359,26 @@
> status = "disabled";
> };
>
> + usb0: usb3@3100000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0x3100000 0x0 0x10000>;
> + interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
> + dr_mode = "host";
> + snps,quirk-frame-length-adjustment = <0x20>;
> + snps,dis_rxdet_inp3_quirk;
> + status = "disabled";
> + };
> +
> + usb1: usb3@3110000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0x3110000 0x0 0x10000>;
> + interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
> + dr_mode = "host";
> + snps,quirk-frame-length-adjustment = <0x20>;
> + snps,dis_rxdet_inp3_quirk;
> + status = "disabled";
> + };
> +
> sata: sata@3200000 {
> compatible = "fsl,ls1088a-ahci";
> reg = <0x0 0x3200000 0x0 0x10000>,
> --
> 2.14.1
>
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