* Re: [PATCH v4.1] phylib: Add device reset GPIO support
From: Sergei Shtylyov @ 2017-12-07 17:40 UTC (permalink / raw)
To: Geert Uytterhoeven, David S . Miller, Andrew Lunn,
Florian Fainelli, Simon Horman, Magnus Damm
Cc: Rob Herring, Mark Rutland, Nicolas Ferre, Richard Leitner,
netdev-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <69fe9a6d-4039-6f80-b80d-7dc0de31e5bf-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
On 12/07/2017 08:20 PM, Sergei Shtylyov wrote:
>> The PHY devices sometimes do have their reset signal (maybe even power
>> supply?) tied to some GPIO and sometimes it also does happen that a boot
>> loader does not leave it deasserted. So far this issue has been attacked
>> from (as I believe) a wrong angle: by teaching the MAC driver to manipulate
>> the GPIO in question; that solution, when applied to the device trees, led
>> to adding the PHY reset GPIO properties to the MAC device node, with one
>> exception: Cadence MACB driver which could handle the "reset-gpios" prop
>> in a PHY device subnode. I believe that the correct approach is to teach
>> the 'phylib' to get the MDIO device reset GPIO from the device tree node
>> corresponding to this device -- which this patch is doing...
>>
>> Note that I had to modify the AT803x PHY driver as it would stop working
>> otherwise -- it made use of the reset GPIO for its own purposes...
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
>> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> [geert: Propagate actual errors from fwnode_get_named_gpiod()]
>> [geert: Avoid destroying initial setup]
>> [geert: Consolidate GPIO descriptor acquiring code]
>> Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
> [...]
>> diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
>> index 2df7b62c1a36811e..8f8b7747c54bc478 100644
>> --- a/drivers/net/phy/mdio_bus.c
>> +++ b/drivers/net/phy/mdio_bus.c
> [...]
>> @@ -48,9 +49,26 @@
>> int mdiobus_register_device(struct mdio_device *mdiodev)
>> {
>> + struct gpio_desc *gpiod = NULL;
>> +
>> if (mdiodev->bus->mdio_map[mdiodev->addr])
>> return -EBUSY;
>> + /* Deassert the optional reset signal */
>
> Umm, but why deassert it here for such a short time?
>
>> + if (mdiodev->dev.of_node)
>> + gpiod = fwnode_get_named_gpiod(&mdiodev->dev.of_node->fwnode,
>> + "reset-gpios", 0, GPIOD_OUT_LOW,
>> + "PHY reset");
>> + if (PTR_ERR(gpiod) == -ENOENT)
>> + gpiod = NULL;
>> + else if (IS_ERR(gpiod))
>> + return PTR_ERR(gpiod);
>
> Hm, returning on error with reset deasserted?
Oops, error means we couldn't drive the GPIO at all...
The 1st question remains though...
[...]
MBR, Sergei
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^ permalink raw reply
* Re: [PATCH v9 01/13] Documentation: Add SLIMbus summary
From: Jonathan Corbet @ 2017-12-07 17:32 UTC (permalink / raw)
To: srinivas.kandagatla
Cc: Mark Brown, Greg Kroah-Hartman, alsa-devel, sdharia, Rob Herring,
Mark Rutland, pombredanne, j.neuschaefer, linux-arm-msm,
devicetree, linux-kernel, linux-doc
In-Reply-To: <20171207102720.21071-2-srinivas.kandagatla@linaro.org>
On Thu, 7 Dec 2017 10:27:08 +0000
srinivas.kandagatla@linaro.org wrote:
A couple of overall comments...
> Documentation/driver-api/index.rst | 1 +
> Documentation/driver-api/slimbus/index.rst | 15 ++++
> Documentation/driver-api/slimbus/summary.rst | 106 +++++++++++++++++++++++++++
> 3 files changed, 122 insertions(+)
> create mode 100644 Documentation/driver-api/slimbus/index.rst
> create mode 100644 Documentation/driver-api/slimbus/summary.rst
Do we really need a separate subdirectory for a single file?
It seems you have kerneldoc comments for your data structures and at least
some of your exported symbols. If you really want to document this stuff
well, I'd suggest finishing out those comments, then pulling them into the
documentation in the appropriate places.
Thanks,
jon
^ permalink raw reply
* Re: [PATCH v2 16/19] ASoC: tlv320aic31xx: Add short circuit detection support
From: Mark Brown @ 2017-12-07 17:23 UTC (permalink / raw)
To: Andrew F. Davis
Cc: Mark Rutland, devicetree, alsa-devel, Tony Lindgren,
Liam Girdwood, linux-kernel, Rob Herring, Benoît Cousson
In-Reply-To: <83e40a88-2c3d-416a-6e19-56c6f96d3af3@ti.com>
[-- Attachment #1.1: Type: text/plain, Size: 728 bytes --]
On Thu, Dec 07, 2017 at 09:37:36AM -0600, Andrew F. Davis wrote:
> On 12/07/2017 06:03 AM, Mark Brown wrote:
> >> As for your other suggestion of "log other interrupt sources
> >> numerically", could you explain this or point to an example of what you
> >> mean?
> > Just print out the bits that were set.
> I don't see anyone else doing this, what would that solve? Maybe I still
> don't get what you mean here. :(
A good proportion of devices require explicit acks for interrupts and
only ack things they handled so don't have this issue, and otherwise
it's common to just handle all the interrupts that the device might
fire. The goal is to not silently eat interrupts if the device starts
interrupting for some reason.
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^ permalink raw reply
* Re: [PATCH v4.1] phylib: Add device reset GPIO support
From: Sergei Shtylyov @ 2017-12-07 17:20 UTC (permalink / raw)
To: Geert Uytterhoeven, David S . Miller, Andrew Lunn,
Florian Fainelli, Simon Horman, Magnus Damm
Cc: Rob Herring, Mark Rutland, Nicolas Ferre, Richard Leitner, netdev,
devicetree, linux-renesas-soc, linux-kernel
In-Reply-To: <1512390905-28094-1-git-send-email-geert+renesas@glider.be>
Hello!
On 12/04/2017 03:35 PM, Geert Uytterhoeven wrote:
> From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> The PHY devices sometimes do have their reset signal (maybe even power
> supply?) tied to some GPIO and sometimes it also does happen that a boot
> loader does not leave it deasserted. So far this issue has been attacked
> from (as I believe) a wrong angle: by teaching the MAC driver to manipulate
> the GPIO in question; that solution, when applied to the device trees, led
> to adding the PHY reset GPIO properties to the MAC device node, with one
> exception: Cadence MACB driver which could handle the "reset-gpios" prop
> in a PHY device subnode. I believe that the correct approach is to teach
> the 'phylib' to get the MDIO device reset GPIO from the device tree node
> corresponding to this device -- which this patch is doing...
>
> Note that I had to modify the AT803x PHY driver as it would stop working
> otherwise -- it made use of the reset GPIO for its own purposes...
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Acked-by: Rob Herring <robh@kernel.org>
> [geert: Propagate actual errors from fwnode_get_named_gpiod()]
> [geert: Avoid destroying initial setup]
> [geert: Consolidate GPIO descriptor acquiring code]
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[...]
> diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
> index 2df7b62c1a36811e..8f8b7747c54bc478 100644
> --- a/drivers/net/phy/mdio_bus.c
> +++ b/drivers/net/phy/mdio_bus.c
[...]
> @@ -48,9 +49,26 @@
>
> int mdiobus_register_device(struct mdio_device *mdiodev)
> {
> + struct gpio_desc *gpiod = NULL;
> +
> if (mdiodev->bus->mdio_map[mdiodev->addr])
> return -EBUSY;
>
> + /* Deassert the optional reset signal */
Umm, but why deassert it here for such a short time?
> + if (mdiodev->dev.of_node)
> + gpiod = fwnode_get_named_gpiod(&mdiodev->dev.of_node->fwnode,
> + "reset-gpios", 0, GPIOD_OUT_LOW,
> + "PHY reset");
> + if (PTR_ERR(gpiod) == -ENOENT)
> + gpiod = NULL;
> + else if (IS_ERR(gpiod))
> + return PTR_ERR(gpiod);
Hm, returning on error with reset deasserted?
> +
> + mdiodev->reset = gpiod;
> +
> + /* Assert the reset signal again */
> + mdio_device_reset(mdiodev, 1);
> +
> mdiodev->bus->mdio_map[mdiodev->addr] = mdiodev;
>
> return 0;
[...]
MBR, Sergei
^ permalink raw reply
* Re: [PATCH v9 2/2] ARM: dts: TS-4600: add basic device tree
From: Fabio Estevam @ 2017-12-07 17:19 UTC (permalink / raw)
To: Sebastien Bourdelin
Cc: linux-kernel, linux-arm-kernel@lists.infradead.org, kernel,
Fabio Estevam, Sascha Hauer, Shawn Guo, Russell King - ARM Linux,
Mark Rutland, robh+dt@kernel.org, devicetree@vger.kernel.org,
Mark Featherston, kris
In-Reply-To: <20171207171118.5448-2-sebastien.bourdelin@savoirfairelinux.com>
On Thu, Dec 7, 2017 at 3:11 PM, Sebastien Bourdelin
<sebastien.bourdelin@savoirfairelinux.com> wrote:
> These device trees add support for the TS-4600 by Technologic Systems.
>
> More details here:
> http://wiki.embeddedarm.com/wiki/TS-4600
>
> Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* Re: [PATCH v2 0/7] Add CPU Frequency scaling support on Armada 37xx
From: Rafael J. Wysocki @ 2017-12-07 17:14 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Viresh Kumar, linux-pm-u79uwXL29TY76Z2rM5mHXA, Jason Cooper,
Andrew Lunn, Sebastian Hesselbarth, Rob Herring,
devicetree-u79uwXL29TY76Z2rM5mHXA, Thomas Petazzoni,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Antoine Tenart,
Miquèl Raynal, Nadav Haklai, Victor Gu, Marcin Wojtas,
Wilson Ding, Hua Jing, Neta Zur Hershkovits, Evan Wang,
Andre Heider
In-Reply-To: <20171207135616.23670-1-gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On Thursday, December 7, 2017 2:56:09 PM CET Gregory CLEMENT wrote:
> Hi,
>
> This is the second version of a series adding the CPU Frequency
> support on Armada 37xx using DVFS. It is based on the initial work of
> Evan Wang and Victor Gu.
>
> The main change since the first version was a bug fixed in the
> "cpufreq: Add DVFS support for Armada 37xx" patch which was preventing
> to register the opp. An other noticeable change is the 4th patch which
> is new adding the use of dev_pm_opp_remove and removing an comment
> became wrong. The other changes are described in the change log.
>
> DVFS control is done by a set of registers from the North Bridge Power
> Management block. The binding for this block is documented in patch 1.
>
> While adding a new cpufreq driver I found that the Kconfig and
> Makefile were no more in order, so it is fixed by patch 2 and 3.
>
> The 5th patch is just about updating the MAINTAINERS file with the new
> driver.
>
> The next patch is the real purpose of the series. The main goal of
> this driver is to setup the CPU load level in the hardware to
> associate them to CPU frequencies and register a standard cpufreq
> driver. Note that the hardware also capable of doing AVS (Adaptive
> Voltage Scaling), by associating a voltage on each level beside the
> CPU frequency. However, this support is not yet ready, so it is not
> part of this series.
>
> Finally, the last patch is for arm-soc the arm-soc subsystem through
> mvebu and update the device tree to support the CPU frequency scaling.
>
> An update on the CPU clock driver is needed in order to take into
> account the DVFS setting. It's the purpose of an other series already
> sent, but is no dependencies between the series (for building or at
> runtime).
>
> Thanks,
>
> Gregory
>
> Changelog:
>
> v1 -> v2:
>
> - using syscon instead of nb_pm for the binding of the North bridge
> power management unit: reported by Rob Herring
>
> - fix sorting inside the big LITTLE section for the Kconfig: reported
> by Viresh Kumar
>
> - fix the bogus freq calculation in armada37xx_cpufreq_driver_init,
> bug reported by Andre Heider
>
> - use dev_pm_opp_remove() on the previous opp if dev_pm_opp_add()
> failed, reported by Viresh Kumar
>
> - add the Tested-by flag from Andre Heider on "cpufreq: Add DVFS
> support for Armada 37xx" patch
>
> Gregory CLEMENT (7):
> dt-bindings: marvell: Add documentation for the North Bridge PM on
> Armada 37xx
> cpufreq: ARM: sort the Kconfig menu
> cpufreq: sort the drivers in ARM part
> cpufreq: mvebu: Use dev_pm_opp_remove()
> MAINTAINERS: add new entries for Armada 37xx cpufreq driver
> cpufreq: Add DVFS support for Armada 37xx
> arm64: dts: marvell: armada-37xx: add nodes allowing cpufreq support
>
> .../bindings/arm/marvell/armada-37xx.txt | 19 ++
> MAINTAINERS | 1 +
> arch/arm64/boot/dts/marvell/armada-372x.dtsi | 1 +
> arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 7 +
> drivers/cpufreq/Kconfig.arm | 89 ++++----
> drivers/cpufreq/Makefile | 9 +-
> drivers/cpufreq/armada-37xx-cpufreq.c | 241 +++++++++++++++++++++
> drivers/cpufreq/mvebu-cpufreq.c | 11 +-
> 8 files changed, 327 insertions(+), 51 deletions(-)
> create mode 100644 drivers/cpufreq/armada-37xx-cpufreq.c
I'd like you to split patches [2-3/7] off this series as they aren't
exactly related to the other changes in it.
Thanks,
Rafael
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^ permalink raw reply
* [PATCH v9 2/2] ARM: dts: TS-4600: add basic device tree
From: Sebastien Bourdelin @ 2017-12-07 17:11 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, kernel, fabio.estevam, kernel,
shawnguo, linux, mark.rutland, robh+dt, devicetree
Cc: mark, kris, Sebastien Bourdelin
In-Reply-To: <20171207171118.5448-1-sebastien.bourdelin@savoirfairelinux.com>
These device trees add support for the TS-4600 by Technologic Systems.
More details here:
http://wiki.embeddedarm.com/wiki/TS-4600
Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
---
Changes v8 -> v9:
- rebase on master
- fix gpio active direction (suggested by Fabio Estevam)
Changes v7 -> v8:
- rebase on master
- merge the rev A and B into one device tree based on the last rev B
because only the memory size change between the two rev currently
(suggested by Shawn Guo)
Changes v6 -> v7:
- rebase on master
- remove unneeded pinctrl-name (suggested by Shawn Guo)
- add reg to the node en-sd-pwr (suggested by Shawn Guo)
- use define for gpio polarity (suggested by Shawn Guo)
- remove the fake bus container for regulator (suggested by Shawn Guo)
Changes v5 -> v6:
- rebase on master
- split the previous patch series into series by subsystem
Changes v4 -> v5:
- fix missing signed off
Changes v3 -> v4:
- rebase on master
Changes v2 -> v3:
- rebase on master
Changes v1 -> v2:
- rebase on master
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx28-ts4600.dts | 79 ++++++++++++++++++++++++++++++++++++++
2 files changed, 80 insertions(+)
create mode 100644 arch/arm/boot/dts/imx28-ts4600.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d0381e9caf21..678373d299d8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -558,6 +558,7 @@ dtb-$(CONFIG_ARCH_MXS) += \
imx28-m28cu3.dtb \
imx28-m28evk.dtb \
imx28-sps1.dtb \
+ imx28-ts4600.dtb \
imx28-tx28.dtb
dtb-$(CONFIG_ARCH_NOMADIK) += \
ste-nomadik-s8815.dtb \
diff --git a/arch/arm/boot/dts/imx28-ts4600.dts b/arch/arm/boot/dts/imx28-ts4600.dts
new file mode 100644
index 000000000000..1e391c9f1b7a
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-ts4600.dts
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2016 Savoir-Faire Linux
+ * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx28.dtsi"
+#include "dt-bindings/gpio/gpio.h"
+
+/ {
+
+ model = "Technologic Systems i.MX28 TS-4600";
+ compatible = "technologic,imx28-ts4600", "fsl,imx28";
+
+ memory {
+ reg = <0x40000000 0x10000000>; /* 256MB */
+ };
+
+ apb@80000000 {
+ apbh@80000000 {
+ ssp0: ssp@80010000 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_4bit_pins_a
+ &mmc0_sck_cfg
+ &en_sd_pwr>;
+ broken-cd = <1>;
+ bus-width = <4>;
+ vmmc-supply = <®_vddio_sd0>;
+ status = "okay";
+ };
+
+ pinctrl@80018000 {
+
+ en_sd_pwr: en-sd-pwr@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_PWM3__GPIO_3_28
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ };
+ };
+
+ apbx@80040000 {
+ pwm: pwm@80064000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_pins_a>;
+ status = "okay";
+ };
+
+ duart: serial@80074000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_a>;
+ status = "okay";
+ };
+ };
+ };
+
+ reg_vddio_sd0: regulator-vddio-sd0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vddio-sd0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ gpio = <&gpio3 28 GPIO_ACTIVE_LOW>;
+ };
+
+};
--
2.15.0
^ permalink raw reply related
* [PATCH v9 1/2] of: documentation: add bindings documentation for TS-4600
From: Sebastien Bourdelin @ 2017-12-07 17:11 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, kernel, fabio.estevam, kernel,
shawnguo, linux, mark.rutland, robh+dt, devicetree
Cc: mark, kris, Sebastien Bourdelin
This adds the documentation for the TS-4600 by Technologic Systems.
Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes v8 -> v9:
- rebase on master
Changes v7 -> v8:
- rebase on master
Changes v6 -> v7:
- rebase on master
Changes v5 -> v6:
- rebase on master
- split the previous patch series into series by subsystem
Changes v4 -> v5:
- fix missing signed off
Changes v3 -> v4:
- rebase on master
Changes v2 -> v3:
- rebase on master
Changes v1 -> v2:
- rebase on master
- add ack by Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/technologic.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/technologic.txt b/Documentation/devicetree/bindings/arm/technologic.txt
index 33797acad846..e9d6d6575566 100644
--- a/Documentation/devicetree/bindings/arm/technologic.txt
+++ b/Documentation/devicetree/bindings/arm/technologic.txt
@@ -1,6 +1,11 @@
Technologic Systems Platforms Device Tree Bindings
--------------------------------------------------
+TS-4600 is a System-on-Module based on the Freescale i.MX28 System-on-Chip.
+It can be mounted on a carrier board providing additional peripheral connectors.
+Required root node properties:
+ - compatible = "technologic,imx28-ts4600", "fsl,imx28"
+
TS-4800 board
Required root node properties:
- compatible = "technologic,imx51-ts4800", "fsl,imx51";
--
2.15.0
^ permalink raw reply related
* Re: [PATCH v8 2/2] ARM: dts: TS-4600: add basic device tree
From: Sebastien Bourdelin @ 2017-12-07 17:06 UTC (permalink / raw)
To: Fabio Estevam
Cc: linux-kernel, kernel, linux-arm-kernel@lists.infradead.org,
Fabio Estevam, Sascha Hauer, Shawn Guo,
devicetree@vger.kernel.org, Mark Rutland, robh+dt@kernel.org,
Mark Featherston, kris
In-Reply-To: <CAOMZO5DcM0u9+DZjywsqadu834++rXAckqnkMqzZOo-vgFVs_w@mail.gmail.com>
Hi Fabio
On 11/26/2017 02:39 PM, Fabio Estevam wrote:
> Hi Sebastien,
>
> On Thu, Nov 23, 2017 at 7:04 PM, Sebastien Bourdelin
> <sebastien.bourdelin@savoirfairelinux.com> wrote:
>
>> + reg_vddio_sd0: regulator-vddio-sd0 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vddio-sd0";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-boot-on;
>> + gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
>
> It seems this should be GPIO_ACTIVE_LOW instead, as you don't pass
> 'enable-active-high' here.
>
Yes! you are right, thanks for the catch!
Regards,
Sebastien.
^ permalink raw reply
* Re: [PATCH] ARM: dts: imx6: RDU2: correct RTC compatible
From: Fabio Estevam @ 2017-12-07 17:00 UTC (permalink / raw)
To: Lucas Stach
Cc: Shawn Guo, Fabio Estevam, Chris Healy, Sascha Hauer,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
patchwork-lst-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <20171207150923.25024-1-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Hi Lucas,
+ Rob and device tree list
On Thu, Dec 7, 2017 at 1:09 PM, Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> The RTC is manufactured by Maxim. This is a cosmetic fix, as Linux
> doesn't match the vendor string for i2c devices.
>
> Signed-off-by: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
> arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
> index eef737bd52d9..6bef9a98678e 100644
> --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
> @@ -581,7 +581,7 @@
> };
>
> ds1341: rtc@68 {
> - compatible = "dallas,ds1341";
> + compatible = "maxim,ds1341";
Dallas has been acquired by Maxim and
Documentation/devicetree/bindings/rtc/rtc-ds1307.txt
mentions "dallas,ds1341", so better keep the existing notation.
Regards,
Fabio Estevam
--
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^ permalink raw reply
* Re: [PATCH] arm64: allwinner: a64: orangepi-zero-plus2: add usb otg
From: Jagan Teki @ 2017-12-07 16:53 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Icenowy Zheng, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Michael Trimarchi,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-sunxi, Jagan Teki
In-Reply-To: <20171207133409.cpp7wxx4yflkgavp-ZC1Zs529Oq4@public.gmane.org>
On Thu, Dec 7, 2017 at 7:04 PM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> Hi,
>
> On Thu, Dec 07, 2017 at 04:35:48PM +0530, Jagan Teki wrote:
>> Add usb otg support for orangepi-zero-plus2 board:
>> - Add usb_otg node with dr_mode as 'otg'
>> - USB0-IDDET connected to PA21
>> - VBUS connected through DCIN which always on
>>
>> Tested mass storage function.
>>
>> Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
>
> Did you test the OTG or peripheral modes?
dr_mode with otg and I've tested mas storage gadget with mmc disk emulation.
>
>> Note: Anyone please check vbus connection [1]
>> Since it is connected through DCIN of vcc-5v, I've added vcc-5v0
>> regulator for the same and attached to usb0_vbus-supply but it is
>> disabling during kernel boot.
>> [ 1.887854] vcc5v0: disabling
>
> VBUS is the power line that is provided on the USB connector. In
> peripheral, that power is provided by the host, therefore it needs to
> be shutdown on the peripheral end. This is the expected behaviour.
So, in my test with 'otg' host drive the vbus so-it is disabling at
target end is it?
thanks!
--
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
^ permalink raw reply
* Re: [PATCH v8 4/6] clocksource: stm32: only use 32 bits timers
From: Daniel Lezcano @ 2017-12-07 16:49 UTC (permalink / raw)
To: Benjamin Gaignard
Cc: Rob Herring, Mark Rutland, Russell King - ARM Linux,
Maxime Coquelin, Alexandre Torgue, Thomas Gleixner, Ludovic Barre,
Julien Thierry, Sudeep Holla, Arnd Bergmann, devicetree,
Linux ARM, Linux Kernel Mailing List
In-Reply-To: <CA+M3ks5Q_ZUHODV=eA4caT9NdrxKw1qiaWwc87w9FiC_uqwfBQ@mail.gmail.com>
On 07/12/2017 17:33, Benjamin Gaignard wrote:
> 2017-12-07 16:27 GMT+01:00 Daniel Lezcano <daniel.lezcano@linaro.org>:
>> On 14/11/2017 09:52, Benjamin Gaignard wrote:
>>> The clock driving counters is at 90MHz so the maximum period
>>> for 16 bis counters is around 750 ms which is a short period
>>> for a clocksource.
>>
>> Isn't it 728us ?
>
> yes it is: 2^16 / 90.000.000 => 728us
Ok, now I can do the connection with the previous patch.
So, the real issue of all this is the 16bits clocksource is wrapping up
every 728us, hence the clockevent periodically expires every ~728us to
keep the timekeeping consistent. Unfortunately, the kernel has a too
high overhead for this as the system is consistently processing this
timer leading to a CPU time resource starvation.
Is that correct ?
>>> For 32 bits counters this period is close
>>> 47 secondes which is more acceptable.
>>>
>>> This patch remove 16 bits counters support and makes sure that
>>> they won't be probed anymore.
>>>
>>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
>>> ---
>>> drivers/clocksource/timer-stm32.c | 26 ++++++++++++--------------
>>> 1 file changed, 12 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c
>>> index ae41a19..8173bcf 100644
>>> --- a/drivers/clocksource/timer-stm32.c
>>> +++ b/drivers/clocksource/timer-stm32.c
>>> @@ -83,9 +83,9 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id)
>>> static int __init stm32_clockevent_init(struct device_node *node)
>>> {
>>> struct reset_control *rstc;
>>> - unsigned long max_delta;
>>> - int ret, bits, prescaler = 1;
>>> + unsigned long max_arr;
>>> struct timer_of *to;
>>> + int ret;
>>>
>>> to = kzalloc(sizeof(*to), GFP_KERNEL);
>>> if (!to)
>>> @@ -115,29 +115,27 @@ static int __init stm32_clockevent_init(struct device_node *node)
>>>
>>> /* Detect whether the timer is 16 or 32 bits */
>>> writel_relaxed(~0U, timer_of_base(to) + TIM_ARR);
>>> - max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR);
>>> - if (max_delta == ~0U) {
>>> - prescaler = 1;
>>> - bits = 32;
>>> - } else {
>>> - prescaler = 1024;
>>> - bits = 16;
>>> + max_arr = readl_relaxed(timer_of_base(to) + TIM_ARR);
>>> + if (max_arr != ~0U) {
>>> + pr_err("32 bits timer is needed\n");
>>> + ret = -EINVAL;
>>> + goto deinit;
>>> }
>>> +
>>> writel_relaxed(0, timer_of_base(to) + TIM_ARR);
>>>
>>> - writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC);
>>> + writel_relaxed(0, timer_of_base(to) + TIM_PSC);
>>> writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR);
>>> writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER);
>>> writel_relaxed(0, timer_of_base(to) + TIM_SR);
>>>
>>> clockevents_config_and_register(&to->clkevt,
>>> - timer_of_period(to), MIN_DELTA, max_delta);
>>> -
>>> - pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n",
>>> - node, bits);
>>> + timer_of_period(to), MIN_DELTA, ~0U);
>>>
>>> return 0;
>>>
>>> +deinit:
>>> + timer_of_exit(to);
>>> err:
>>> kfree(to);
>>> return ret;
>>>
>>
>>
>> --
>> <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>>
>> Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
>> <http://twitter.com/#!/linaroorg> Twitter |
>> <http://www.linaro.org/linaro-blog/> Blog
>>
>
>
>
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* Re: [PATCH v2 08/35] nds32: Process management
From: Al Viro @ 2017-12-07 16:45 UTC (permalink / raw)
To: Greentime Hu
Cc: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, dhowells,
will.deacon, daniel.lezcano, linux-serial, Vincent Chen
In-Reply-To: <53789f9af98217d24580479c55e550301651d4a8.1511785528.git.green.hu@gmail.com>
On Mon, Nov 27, 2017 at 08:27:55PM +0800, Greentime Hu wrote:
> +#define start_thread(regs,pc,stack) \
> +({ \
> + set_fs(USER_DS); \
Not the job of start_thread() - its users (->load_binary() methods of
assorted binfmt) must (and do) call flush_old_exec() first. And
that will switch to USER_DS just fine.
^ permalink raw reply
* Re: [PATCH v2 06/35] nds32: MMU fault handling and page table management
From: Al Viro @ 2017-12-07 16:40 UTC (permalink / raw)
To: Greentime Hu
Cc: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, dhowells,
will.deacon, daniel.lezcano, linux-serial, Vincent Chen
In-Reply-To: <ba92adae5d20d99c7c18e75146642a2ccbd5d047.1511785528.git.green.hu@gmail.com>
On Mon, Nov 27, 2017 at 08:27:53PM +0800, Greentime Hu wrote:
> +void do_page_fault(unsigned long entry, unsigned long addr,
> + unsigned int error_code, struct pt_regs *regs)
[snip]
> + /*
> + * If we're in an interrupt or have no user
> + * context, we must not take the fault..
> + */
> + if (unlikely(in_atomic() || !mm))
Broken. in_atomic() is wrong here - it should be faulthandler_disabled().
^ permalink raw reply
* Re: [PATCH v8 4/6] clocksource: stm32: only use 32 bits timers
From: Benjamin Gaignard @ 2017-12-07 16:33 UTC (permalink / raw)
To: Daniel Lezcano
Cc: Rob Herring, Mark Rutland, Russell King - ARM Linux,
Maxime Coquelin, Alexandre Torgue, Thomas Gleixner, Ludovic Barre,
Julien Thierry, Sudeep Holla, Arnd Bergmann, devicetree,
Linux ARM, Linux Kernel Mailing List
In-Reply-To: <44bb54e6-c9e8-4b54-d490-a1800bf6d74c@linaro.org>
2017-12-07 16:27 GMT+01:00 Daniel Lezcano <daniel.lezcano@linaro.org>:
> On 14/11/2017 09:52, Benjamin Gaignard wrote:
>> The clock driving counters is at 90MHz so the maximum period
>> for 16 bis counters is around 750 ms which is a short period
>> for a clocksource.
>
> Isn't it 728us ?
yes it is: 2^16 / 90.000.000 => 728us
>
>> For 32 bits counters this period is close
>> 47 secondes which is more acceptable.
>>
>> This patch remove 16 bits counters support and makes sure that
>> they won't be probed anymore.
>>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
>> ---
>> drivers/clocksource/timer-stm32.c | 26 ++++++++++++--------------
>> 1 file changed, 12 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c
>> index ae41a19..8173bcf 100644
>> --- a/drivers/clocksource/timer-stm32.c
>> +++ b/drivers/clocksource/timer-stm32.c
>> @@ -83,9 +83,9 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id)
>> static int __init stm32_clockevent_init(struct device_node *node)
>> {
>> struct reset_control *rstc;
>> - unsigned long max_delta;
>> - int ret, bits, prescaler = 1;
>> + unsigned long max_arr;
>> struct timer_of *to;
>> + int ret;
>>
>> to = kzalloc(sizeof(*to), GFP_KERNEL);
>> if (!to)
>> @@ -115,29 +115,27 @@ static int __init stm32_clockevent_init(struct device_node *node)
>>
>> /* Detect whether the timer is 16 or 32 bits */
>> writel_relaxed(~0U, timer_of_base(to) + TIM_ARR);
>> - max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR);
>> - if (max_delta == ~0U) {
>> - prescaler = 1;
>> - bits = 32;
>> - } else {
>> - prescaler = 1024;
>> - bits = 16;
>> + max_arr = readl_relaxed(timer_of_base(to) + TIM_ARR);
>> + if (max_arr != ~0U) {
>> + pr_err("32 bits timer is needed\n");
>> + ret = -EINVAL;
>> + goto deinit;
>> }
>> +
>> writel_relaxed(0, timer_of_base(to) + TIM_ARR);
>>
>> - writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC);
>> + writel_relaxed(0, timer_of_base(to) + TIM_PSC);
>> writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR);
>> writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER);
>> writel_relaxed(0, timer_of_base(to) + TIM_SR);
>>
>> clockevents_config_and_register(&to->clkevt,
>> - timer_of_period(to), MIN_DELTA, max_delta);
>> -
>> - pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n",
>> - node, bits);
>> + timer_of_period(to), MIN_DELTA, ~0U);
>>
>> return 0;
>>
>> +deinit:
>> + timer_of_exit(to);
>> err:
>> kfree(to);
>> return ret;
>>
>
>
> --
> <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>
> Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter |
> <http://www.linaro.org/linaro-blog/> Blog
>
--
Benjamin Gaignard
Graphic Study Group
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v14 5/5] dt-bindings: watchdog: Add bindings for RAVE SP watchdog driver
From: Andrey Smirnov @ 2017-12-07 16:27 UTC (permalink / raw)
To: Lee Jones
Cc: Andrey Smirnov, linux-kernel, devicetree, linux-watchdog, cphealy,
Lucas Stach, Nikita Yushchenko, Greg Kroah-Hartman, Pavel Machek,
Andy Shevchenko, Guenter Roeck, Rob Herring, Johan Hovold,
Mark Rutland, Sebastian Reichel
In-Reply-To: <20171207162735.25873-1-andrew.smirnov@gmail.com>
Add Device Tree bindings for RAVE SP watchdog drvier - an MFD cell of
parent RAVE SP driver (documented in
Documentation/devicetree/bindings/mfd/zii,rave-sp.txt).
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-watchdog@vger.kernel.org
Cc: cphealy@gmail.com
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Rob Herring <robh@kernel.org>
Cc: Johan Hovold <johan@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
.../bindings/watchdog/zii,rave-sp-wdt.txt | 39 ++++++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt
diff --git a/Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt b/Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt
new file mode 100644
index 000000000000..ab16659e781d
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt
@@ -0,0 +1,39 @@
+Zodiac Inflight Innovations RAVE Supervisory Processor Watchdog Bindings
+
+RAVE SP watchdog device is a "MFD cell" device corresponding to
+watchdog functionality of RAVE Supervisory Processor. It is expected
+that its Device Tree node is specified as a child of the node
+corresponding to the parent RAVE SP device (as documented in
+Documentation/devicetree/bindings/mfd/zii,rave-sp.txt)
+
+Required properties:
+- compatible: Should be "zii,rave-sp-watchdog"
+
+Optional properties:
+
+- wdt-timeout: Two byte nvmem cell specified as per
+ Documentation/devicetree/bindings/nvmem/nvmem.txt
+
+Example:
+
+ rave-sp {
+ compatible = "zii,rave-sp-rdu1";
+ current-speed = <38400>;
+
+ eeprom {
+ compatible = "zii,pic-main-eeprom";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ wdt_timeout: wdt-timeout@8E {
+ reg = <0x8E 2>;
+ };
+ };
+
+ watchdog {
+ compatible = "zii,rave-sp-watchdog";
+ nvmem-cells = <&wdt_timeout>;
+ nvmem-cell-names = "wdt-timeout";
+ };
+ }
+
--
2.14.3
^ permalink raw reply related
* [PATCH v14 0/5] ZII RAVE platform driver
From: Andrey Smirnov @ 2017-12-07 16:27 UTC (permalink / raw)
To: Lee Jones
Cc: Andrey Smirnov, Pavel Machek, Greg Kroah-Hartman,
cphealy-Re5JQEeQqe8AvxtiuMwx3w, Andy Shevchenko, Lucas Stach,
Nikita Yushchenko, Guenter Roeck, Rob Herring, Mark Rutland,
Johan Hovold, devicetree-u79uwXL29TY76Z2rM5mHXA,
Sebastian Reichel
Lee:
This patch set has been marinating out there for a while now and
yours, I belive, is that last signature I need to start pushing it for
inclusion. I'd really appreciate if you could spare some of your time
to give it a look. Thanks!
Everyone:
This patch series is v14 of the driver for supervisory processor found
on RAVE series of devices from ZII. Supervisory processor is a PIC
microcontroller connected to various electrical subsystems on RAVE
devices whose firmware implements protocol to command/qery them.
NOTE:
* This driver dependends on crc_ccitt_false(), added by
2da9378d531f8cc6670c7497f20d936b706ab80b in 'linux-next', the patch
was pulled in by Andrew Morton and is currently avaiting users, so
this series might have to go in through Andrew's tree
Changes since [v13]:
- Fixed incorrect MFD driver menuconfig entry placement
Changes since [v12]:
- Minor comment inconsistencies fixes in rave-sp.c
Changes since [v11]:
- Fix incorrect include in rave-sp-wdt.c as uncovered by kernel
test robot
Changes since [v10]:
- Collected Acked-by from Rob and Reviewed-by from Guenter
- Incorporated watchdog driver feedback from Gunter and Johan
- Incorporated Johan's feedback for the rest of the code
Changes since [v9]:
- Converted watchdog driver to use watchdog_active() instead of
watchdog_hw_running() and replaced WARN_ON with a regular error
message as per feedback from Guenter
- Changed rave_sp_wdt_start() to set WDOG_HW_RUNNING only if
communicating with hardware was sucessful
- Collected Reviewd-by from Sebastian (for serdev related patches)
- Collected Acked-by from Rob (for watchdog DT bindings)
Changes since [v8]:
- Driver moved from drivers/platform to drivers/mfd
- Collected Reviewed-by from Guenter (for patches 1, 2 and 3)
- Incorporated feedback from Guenter into watchdog driver
- Incorporated feedback from Rob into watchdog DT bindings
- Removed struct rave_sp_rsp_status, which was a leftover from v5
-> v6 code removal.
- Fixed minor problems reported by checkpatch
Changes since [v7]:
- Added watchdog driver to the patchset, so it would be easier to
understand how parent/children drivers are tied together
- Added serdev patches to implement devm_serdev_device_open() and make .remove optional
- "Added" missing serdev_device_close() by converting the driver
to use devm_serdev_device_open()
- Converted the driver to use devm_of_platform_populate()
- Removed needless dependency on MFD_CORE
- Removed dependency on SERIAL_DEV_CTRL_TTYPORT
Changes since [v6]:
- Patch 2/2 has been applied by Lee so it is no longer a part of the series
- Removed all sysfs and debugfs attribute to reduce the scope of
the driver propsed for inclusion. This is not a critical to have
feature and can be added/discussed later.
Changes since [v5]:
- Fixed a build break, introduced by a last minute change in [v5]
- Moved majority of attributes that were exposed over sysfs to debugfs
- Document remaining sysfs attributes in Documentation/ABI/testing/sysfs-platform-rave-sp
Changes since [v4]:
- Replaced usage of DEVICE_ATTR with DEVICE_ATTR_RW
- Fixed a number of warnings produces by sparse tool
- Incorporated event more feedback from Andy Shevchenko
- Collected Reviewed-by from Andy
Changes since [v3]:
- Re-collected lost Acked-by from Rob
- Incorporated further feedback from Andy Shevchenko
- Dropped useless change (stray newline) to drivers/mfd/Makefile
Changes since [v2]:
- Fixed swapped command codes in rave_sp_common_get_boot_source()
and rave_sp_common_set_boot_source() revealed by further testing
of the code
- Incorporated feedback from Andy Shevchenko
Changes since [v1]:
- Updated wording in DT-bindings as per Rob's request.
- Collected Rob's Acked-by for patch 2/2
Feedback is greatly appreciated!
Thanks,
Andrey Smirnov
[v13] lkml.kernel.org/r/20171204161118.19558-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v12] lkml.kernel.org/r/20171109160556.17018-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v11] lkml.kernel.org/r/20171106152935.16920-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v10] lkml.kernel.org/r/20171031163656.24552-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v9] lkml.kernel.org/r/20171025190421.18415-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v8] lkml.kernel.org/r/20171018170136.12347-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v7] lkml.kernel.org/r/20171013061321.31252-2-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v6] lkml.kernel.org/r/20170828163131.24815-2-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v5] lkml.kernel.org/r/20170728142704.11156-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v4] lkml.kernel.org/r/20170725184450.13171-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v3] lkml.kernel.org/r/20170724150915.4824-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v2] lkml.kernel.org/r/20170718175604.11735-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v1] lkml.kernel.org/r/20170710170449.4544-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Andrey Smirnov (5):
serdev: Make .remove in struct serdev_device_driver optional
serdev: Introduce devm_serdev_device_open()
mfd: Add driver for RAVE Supervisory Processor
watchdog: Add RAVE SP watchdog driver
dt-bindings: watchdog: Add bindings for RAVE SP watchdog driver
.../bindings/watchdog/zii,rave-sp-wdt.txt | 39 ++
Documentation/driver-model/devres.txt | 3 +
drivers/mfd/Kconfig | 8 +
drivers/mfd/Makefile | 2 +
drivers/mfd/rave-sp.c | 660 +++++++++++++++++++++
drivers/tty/serdev/core.c | 31 +-
drivers/watchdog/Kconfig | 7 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/rave-sp-wdt.c | 357 +++++++++++
include/linux/mfd/rave-sp.h | 56 ++
include/linux/serdev.h | 1 +
11 files changed, 1163 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt
create mode 100644 drivers/mfd/rave-sp.c
create mode 100644 drivers/watchdog/rave-sp-wdt.c
create mode 100644 include/linux/mfd/rave-sp.h
--
2.14.3
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* Re: [PATCH v5 1/2] at24: support eeproms that do not auto-rollover reads.
From: Bartosz Golaszewski @ 2017-12-07 16:26 UTC (permalink / raw)
To: Sven Van Asbroeck
Cc: Rob Herring, Mark Rutland, Wolfram Sang, nsekhar-l0cyMroinI0,
Sakari Ailus, David Lechner, Javier Martinez Canillas,
Divagar Mohandass, devicetree-u79uwXL29TY76Z2rM5mHXA,
Linux Kernel Mailing List, linux-i2c
In-Reply-To: <1512657378-5221-2-git-send-email-svendev-fuHqz3Nb1YI@public.gmane.org>
2017-12-07 15:36 GMT+01:00 Sven Van Asbroeck <svendev-fuHqz3Nb1YI@public.gmane.org>:
> Some multi-address eeproms in the at24 family may not automatically
> roll-over reads to the next slave address. On those eeproms, reads
> that straddle slave boundaries will not work correctly.
>
> Solution:
> Mark such eeproms with a flag that prevents reads straddling
> slave boundaries. Add the AT24_FLAG_NO_RDROL flag to the eeprom
> entry in the device_id table, or add 'no-read-rollover' to the
> eeprom devicetree entry.
>
> Note that I have not personally enountered an at24 chip that
> does not support read rollovers. They may or may not exist.
> However, my hardware requires this functionality because of
> a quirk.
>
> It's up to the Linux community to decide if this patch is useful/
> general enough to warrant merging.
>
> Signed-off-by: Sven Van Asbroeck <svendev-fuHqz3Nb1YI@public.gmane.org>
> ---
> drivers/misc/eeprom/at24.c | 37 +++++++++++++++++++++++++------------
> include/linux/platform_data/at24.h | 2 ++
> 2 files changed, 27 insertions(+), 12 deletions(-)
>
Hi Sven,
looks good in general, just a couple nits to fix below and it can be applied.
> diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c
> index 625b001..8c93ed0 100644
> --- a/drivers/misc/eeprom/at24.c
> +++ b/drivers/misc/eeprom/at24.c
> @@ -251,15 +251,6 @@ struct at24_data {
> * Slave address and byte offset derive from the offset. Always
> * set the byte address; on a multi-master board, another master
> * may have changed the chip's "current" address pointer.
> - *
> - * REVISIT some multi-address chips don't rollover page reads to
> - * the next slave address, so we may need to truncate the count.
> - * Those chips might need another quirk flag.
> - *
> - * If the real hardware used four adjacent 24c02 chips and that
> - * were misconfigured as one 24c08, that would be a similar effect:
> - * one "eeprom" file not four, but larger reads would fail when
> - * they crossed certain pages.
> */
> static struct at24_client *at24_translate_offset(struct at24_data *at24,
> unsigned int *offset)
> @@ -277,6 +268,28 @@ static struct at24_client *at24_translate_offset(struct at24_data *at24,
> return &at24->client[i];
> }
>
> +static size_t at24_adjust_read_count(struct at24_data *at24,
> + unsigned int offset, size_t count)
> +{
> + unsigned int bits;
> + size_t remainder;
Add a newline here.
> + /*
> + * In case of multi-address chips that don't rollover reads to
> + * the next slave address: truncate the count to the slave boundary,
> + * so that the read never straddles slaves.
> + */
> + if (at24->chip.flags & AT24_FLAG_NO_RDROL) {
> + bits = (at24->chip.flags & AT24_FLAG_ADDR16) ? 16 : 8;
There's no need for braces around the ternary operator's condition.
> + remainder = BIT(bits) - offset;
> + if (count > remainder)
> + count = remainder;
> + }
Another newline here.
> + if (count > io_limit)
> + count = io_limit;
> +
> + return count;
> +}
> +
> static ssize_t at24_regmap_read(struct at24_data *at24, char *buf,
> unsigned int offset, size_t count)
> {
> @@ -289,9 +302,7 @@ static ssize_t at24_regmap_read(struct at24_data *at24, char *buf,
> at24_client = at24_translate_offset(at24, &offset);
> regmap = at24_client->regmap;
> client = at24_client->client;
> -
> - if (count > io_limit)
> - count = io_limit;
> + count = at24_adjust_read_count(at24, offset, count);
>
> /* adjust offset for mac and serial read ops */
> offset += at24->offset_adj;
> @@ -457,6 +468,8 @@ static void at24_get_pdata(struct device *dev, struct at24_platform_data *chip)
>
> if (device_property_present(dev, "read-only"))
> chip->flags |= AT24_FLAG_READONLY;
> + if (device_property_present(dev, "no-read-rollover"))
> + chip->flags |= AT24_FLAG_NO_RDROL;
>
> err = device_property_read_u32(dev, "size", &val);
> if (!err)
> diff --git a/include/linux/platform_data/at24.h b/include/linux/platform_data/at24.h
> index 271a4e2..841bb28 100644
> --- a/include/linux/platform_data/at24.h
> +++ b/include/linux/platform_data/at24.h
> @@ -50,6 +50,8 @@ struct at24_platform_data {
> #define AT24_FLAG_TAKE8ADDR BIT(4) /* take always 8 addresses (24c00) */
> #define AT24_FLAG_SERIAL BIT(3) /* factory-programmed serial number */
> #define AT24_FLAG_MAC BIT(2) /* factory-programmed mac address */
> +#define AT24_FLAG_NO_RDROL BIT(1) /* does not auto-rollover reads to */
> + /* the next slave address */
>
> void (*setup)(struct nvmem_device *nvmem, void *context);
> void *context;
> --
> 1.9.1
>
Thanks,
Bartosz
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^ permalink raw reply
* [PATCH v4 2/2] ARM: dts: TS-7970: add basic device tree
From: Sebastien Bourdelin @ 2017-12-07 16:05 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, kernel, fabio.estevam, kernel,
shawnguo, linux, mark.rutland, robh+dt, devicetree
Cc: mark, kris, Sebastien Bourdelin
In-Reply-To: <20171207160550.2782-1-sebastien.bourdelin@savoirfairelinux.com>
These device trees add support for TS-7970 by Technologic Systems.
More details here:
https://wiki.embeddedarm.com/wiki/TS-7970
Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
---
Changes v3 -> v4:
- rebase on master
- comestic changes (suggested by Shawn Guo)
Changes v2 -> v3:
- fix typo in imx6q-ts7970.dts (suggested by Fabio Estevam)
- add enable-active-high on regulator (suggested by Fabio Estevam)
- rework the interrupts-extended option in fec and add the
fsl,err006687 workaround (suggested by Fabio Estevam)
- remove the reset-gpio option in the pcie node as i can't confirm the
value right now
Changes v1 -> v2:
- rebase on master
- remove spidev devices (suggested by Fabio Estevam)
- remove inexistant sata node on imx6dl-ts7970.dts
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/imx6dl-ts7970.dts | 50 +++
arch/arm/boot/dts/imx6q-ts7970.dts | 54 ++++
arch/arm/boot/dts/imx6qdl-ts7970.dtsi | 594 ++++++++++++++++++++++++++++++++++
4 files changed, 700 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6dl-ts7970.dts
create mode 100644 arch/arm/boot/dts/imx6q-ts7970.dts
create mode 100644 arch/arm/boot/dts/imx6qdl-ts7970.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d0381e9caf21..06d7724d5f70 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -396,6 +396,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-sabresd.dtb \
imx6dl-savageboard.dtb \
imx6dl-ts4900.dtb \
+ imx6dl-ts7970.dtb \
imx6dl-tx6dl-comtft.dtb \
imx6dl-tx6s-8034.dtb \
imx6dl-tx6s-8034-mb7.dtb \
@@ -459,6 +460,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-sbc6x.dtb \
imx6q-tbs2910.dtb \
imx6q-ts4900.dtb \
+ imx6q-ts7970.dtb \
imx6q-tx6q-1010.dtb \
imx6q-tx6q-1010-comtft.dtb \
imx6q-tx6q-1020.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-ts7970.dts b/arch/arm/boot/dts/imx6dl-ts7970.dts
new file mode 100644
index 000000000000..d104daf305d9
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-ts7970.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2015 Technologic Systems
+ * Copyright 2017 Savoir-faire Linux
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-ts7970.dtsi"
+
+/ {
+ model = "Technologic Systems i.MX6 Solo/DualLite TS-7970 (Default Device Tree)";
+ compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6q-ts7970.dts b/arch/arm/boot/dts/imx6q-ts7970.dts
new file mode 100644
index 000000000000..f19e18995e68
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-ts7970.dts
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2015 Technologic Systems
+ * Copyright 2017 Savoir-faire Linux
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-ts7970.dtsi"
+
+/ {
+ model = "Technologic Systems i.MX6 Quad TS-7970 (Default Device Tree)";
+ compatible = "technologic,imx6q-ts7970", "fsl,imx6q";
+};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/imx6qdl-ts7970.dtsi
new file mode 100644
index 000000000000..f0be516dc28e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-ts7970.dtsi
@@ -0,0 +1,594 @@
+/*
+ * Copyright 2015 Technologic Systems
+ * Copyright 2017 Savoir-Faire Linux
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds1>;
+ compatible = "gpio-leds";
+
+ green-led {
+ label = "green-led";
+ gpios = <&gpio3 27 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+
+ red-led {
+ label = "red-led";
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ yel-led {
+ label = "yellow-led";
+ gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ blue-led {
+ label = "blue-led";
+ gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ en-usb-5v {
+ label = "en-usb-5v";
+ gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ sel_dc_usb {
+ label = "sel_dc_usb";
+ gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3p3v";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_can1_3v3: reg_can1_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_can1_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_can2_3v3: en-reg_can2_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_can2_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_wlan_vmmc: regulator_wlan_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "wlan_vmmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio8 14 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ sound-sgtl5000 {
+ audio-codec = <&sgtl5000>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+ compatible = "fsl,imx-audio-sgtl5000";
+ model = "On-board Codec";
+ mux-ext-port = <3>;
+ mux-int-port = <1>;
+ ssi-controller = <&ssi1>;
+ };
+};
+
+&audmux {
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <®_can1_3v3>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <®_can2_3v3>;
+ status = "okay";
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ n25q064: flash@0 {
+ compatible = "micron,n25q064", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
+&ecspi2 {
+ cs-gpios = <
+ &gpio5 31 GPIO_ACTIVE_HIGH
+ &gpio7 12 GPIO_ACTIVE_HIGH
+ &gpio5 18 GPIO_ACTIVE_HIGH
+ >;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,err006687-workaround-present;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ m41t00s: rtc@68 {
+ compatible = "m41t00";
+ reg = <0x68>;
+ };
+
+ isl12022: rtc@6f {
+ compatible = "isl,isl12022";
+ reg = <0x6f>;
+ };
+
+ gpio8: gpio@28 {
+ compatible = "technologic,ts7970-gpio";
+ reg = <0x28>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpio = <32>;
+ };
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgtl5000>;
+ reg = <0x0a>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ VDDA-supply = <®_3p3v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard Flash CS */
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2 {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
+ MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
+ MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
+ MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x100b1 /* FPGA_SPI_CS0 */
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x100b1 /* FPGA_SPI_CS1 */
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 /* HD1_SPI_CS */
+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b088 /* FPGA_RESET */
+ MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */
+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b088 /* FPGA_IRQ_0 */
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b088 /* FPGA_IRQ_1 */
+ >;
+ };
+
+ pinctrl_enet: enet {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b088
+ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b088 /* ETH_PHY_RESET */
+ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b088
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b088
+ MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b088 /* EN_CAN_1 */
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b088
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b088
+ MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b088 /* EN_CAN_2 */
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ /* Onboard */
+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b088 /* USB_HUB_RESET */
+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b088 /* SEL_DC_USB */
+ MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b088 /* EN_USB_5V */
+ MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b088 /* JTAG_FPGA_TMS */
+ MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b088 /* JTAG_FPGA_TCK */
+ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b088 /* JTAG_FPGA_TDO */
+ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b088 /* JTAG_FPGA_TDI */
+ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b088 /* GYRO_INT */
+ MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b088 /* MODBUS_FAULT */
+ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b088 /* BUS_DIR/JP_SD_BOOT */
+ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b088 /* EN_MODBUS_24V */
+ MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b088 /* EN_MODBUS_3V */
+ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b088 /* I210_RESET */
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b088 /* EN_RTC_PWR */
+ MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b088 /* REVSTRAP1 */
+
+ /* Offboard */
+ MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b088 /* LCD_D09 */
+ MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b088 /* HD1_IRQ */
+ MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b088 /* LCD_D10 */
+ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b088 /* LCD_D11 */
+ MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b088 /* BUS_BHE */
+ MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b088 /* BUS_ALE */
+ MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b088 /* BUS_CS */
+ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b088 /* DIO_20 */
+ MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b088 /* BUS_WAIT */
+ MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b088 /* MUX_AD_00 */
+ MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b088 /* MUX_AD_01 */
+ MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b088 /* MUX_AD_02 */
+ MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b088 /* MUX_AD_03 */
+ MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b088 /* MUX_AD_04 */
+ MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b088 /* MUX_AD_05 */
+ MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b088 /* MUX_AD_06 */
+ MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b088 /* MUX_AD_07 */
+ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b088 /* MUX_AD_08 */
+ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b088 /* MUX_AD_09 */
+ MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b088 /* MUX_AD_10 */
+ MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b088 /* MUX_AD_11 */
+ MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b088 /* MUX_AD_12 */
+ MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b088 /* MUX_AD_13 */
+ MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b088 /* MUX_AD_14 */
+ MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b088 /* MUX_AD_15 */
+
+ /* Strapping only */
+ MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b088
+ MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b088
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
+ >;
+ };
+
+ pinctrl_leds1: leds1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b088 /* GREEN_LED */
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b088 /* RED_LED */
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b088 /* YEL_LED */
+ MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b088 /* IMX6_BLUE_LED */
+ >;
+ };
+
+ pinctrl_sgtl5000: sgtl5000grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b088
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b088
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b088
+ MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b088
+ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b088
+ MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b088
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b088
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b088
+ MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b088
+ MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b088
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b088
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b088
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b088
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b088
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b088 /* EN_SD_POWER */
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ >;
+ };
+};
+
+&pcie {
+ status = "okay";
+};
+
+&snvs_rtc {
+ status = "disabled";
+};
+
+&ssi1 {
+ fsl,mode = "i2s-slave";
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+/* WIFI */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ vmmc-supply = <®_wlan_vmmc>;
+ bus-width = <4>;
+ non-removable;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1271";
+ reg = <2>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
+ ref-clock-frequency = <38400000>;
+ };
+};
+
+/* SD */
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ vmmc-supply = <®_3p3v>;
+ bus-width = <4>;
+ fsl,wp-controller;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ vmmc-supply = <®_3p3v>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
--
2.15.0
^ permalink raw reply related
* [PATCH v4 1/2] of: documentation: add bindings documentation for TS-7970
From: Sebastien Bourdelin @ 2017-12-07 16:05 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, kernel, fabio.estevam, kernel,
shawnguo, linux, mark.rutland, robh+dt, devicetree
Cc: mark, kris, Sebastien Bourdelin
This adds the documentation for the TS-7970 by Technologic Systems.
Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
---
Changes v3 -> v4:
- rebase on master
Changes v1 -> v2:
- rebase on master
---
Documentation/devicetree/bindings/arm/technologic.txt | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/technologic.txt b/Documentation/devicetree/bindings/arm/technologic.txt
index 33797acad846..187830bd4f51 100644
--- a/Documentation/devicetree/bindings/arm/technologic.txt
+++ b/Documentation/devicetree/bindings/arm/technologic.txt
@@ -10,3 +10,9 @@ It can be mounted on a carrier board providing additional peripheral connectors.
Required root node properties:
- compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"
- compatible = "technologic,imx6q-ts4900", "fsl,imx6q"
+
+TS-7970 is a System-on-Module based on the Freescale i.MX6 System-on-Chip.
+It can be mounted on a carrier board providing additional peripheral connectors.
+Required root node properties:
+ - compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl"
+ - compatible = "technologic,imx6q-ts7970", "fsl,imx6q"
--
2.15.0
^ permalink raw reply related
* Re: [PATCH v11 0/6] Add support for Qualcomm A53 CPU clock
From: Georgi Djakov @ 2017-12-07 16:02 UTC (permalink / raw)
To: Rob Herring
Cc: sboyd, jassisinghbrar, bjorn.andersson, mturquette, linux-clk,
linux-kernel, linux-arm-msm, devicetree
In-Reply-To: <20171206210847.mhrsxgytl4ihwgyq@rob-hp-laptop>
On 12/06/2017 11:08 PM, Rob Herring wrote:
> On Tue, Dec 05, 2017 at 05:46:55PM +0200, Georgi Djakov wrote:
>> This patchset adds support for the A53 CPU clock on MSM8916 platforms
>> and allows scaling of the CPU frequency on msm8916 based platforms.
>>
>> Changes since v10 (https://lkml.org/lkml/2017/12/1/577)
>> * Addressed Bjorn's comments on APCS clock driver.
>> * Picked Acks from Rob and Bjorn.
>
> Errr, really?
Oops sorry, it was a Reviewed-by for the mailbox binding change and not
an Ack. Thank you for reviewing the constantly changing binding in this
patchset. I hope that it will not change anymore.
BR,
Georgi
^ permalink raw reply
* Re: [PATCH v11 0/6] Add support for Qualcomm A53 CPU clock
From: Georgi Djakov @ 2017-12-07 16:00 UTC (permalink / raw)
To: Amit Kucheria
Cc: Stephen Boyd, jassisinghbrar, bjorn.andersson, Michael Turquette,
Rob Herring, linux-clk, LKML, linux-arm-msm, devicetree
In-Reply-To: <CAHLCerMok=-0hFLm27_VzSWzC7nArmTz+shQH05DAuBr3An9qw@mail.gmail.com>
Hi Amit,
On 12/06/2017 07:51 AM, Amit Kucheria wrote:
> On Tue, Dec 5, 2017 at 9:16 PM, Georgi Djakov <georgi.djakov@linaro.org> wrote:
>> This patchset adds support for the A53 CPU clock on MSM8916 platforms
>> and allows scaling of the CPU frequency on msm8916 based platforms.
>
> Though it currently needs some additional patches (that'll follow
> soon), FWIW, Tested-by: Amit Kucheria <amit.kucheria@linaro.org>
Thanks for testing! I will submit the platform specific dts changes as
separate follow-up patches when this is merged.
BR,
Georgi
^ permalink raw reply
* [PATCH v4 15/15] ARM: dts: sun8i: a711: Enable the LCD
From: Maxime Ripard @ 2017-12-07 15:59 UTC (permalink / raw)
To: Daniel Vetter, David Airlie, Chen-Yu Tsai, Maxime Ripard
Cc: Mark Rutland, Thomas Petazzoni, jernej.skrabec, plaes, devicetree,
linux-kernel, dri-devel, Rob Herring, thierry.reding,
linux-arm-kernel, icenowy
In-Reply-To: <cover.e46a07c0e181d735c807dc94fe0ce0ea013788be.1512662253.git-series.maxime.ripard@free-electrons.com>
The A711 has 1024x600 LVDS panel, with a PWM-based backlight. Add it to our
DT.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 61 ++++++++++++++++++++++++-
1 file changed, 61 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index a021ee6da396..511fca491fe8 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -45,6 +45,7 @@
#include "sun8i-a83t.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
/ {
model = "TBS A711 Tablet";
@@ -59,6 +60,44 @@
stdout-path = "serial0:115200n8";
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ enable-gpios = <&pio 3 29 GPIO_ACTIVE_HIGH>;
+
+ brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
+ default-brightness-level = <9>;
+ };
+
+ panel {
+ compatible = "tbs,a711-panel", "panel-lvds";
+ backlight = <&backlight>;
+ power-supply = <®_sw>;
+
+ width-mm = <153>;
+ height-mm = <90>;
+ data-mapping = "vesa-24";
+
+ panel-timing {
+ /* 1024x600 @60Hz */
+ clock-frequency = <52000000>;
+ hactive = <1024>;
+ vactive = <600>;
+ hsync-len = <20>;
+ hfront-porch = <180>;
+ hback-porch = <160>;
+ vfront-porch = <12>;
+ vback-porch = <23>;
+ vsync-len = <5>;
+ };
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&tcon0_out_lcd>;
+ };
+ };
+ };
+
reg_vbat: reg-vbat {
compatible = "regulator-fixed";
regulator-name = "vbat";
@@ -89,6 +128,10 @@
};
};
+&de {
+ status = "okay";
+};
+
/*
* An USB-2 hub is connected here, which also means we don't need to
* enable the OHCI controller.
@@ -142,6 +185,12 @@
status = "okay";
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pin>;
+ status = "okay";
+};
+
&r_rsb {
status = "okay";
@@ -323,6 +372,18 @@
regulator-name = "vcc-lcd";
};
+&tcon0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_lvds_pins>;
+};
+
+&tcon0_out {
+ tcon0_out_lcd: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_input>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
--
git-series 0.9.1
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dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH v4 14/15] ARM: dts: sun8i: a711: Reinstate the PMIC compatible
From: Maxime Ripard @ 2017-12-07 15:58 UTC (permalink / raw)
To: Daniel Vetter, David Airlie, Chen-Yu Tsai, Maxime Ripard
Cc: Mark Rutland, Thomas Petazzoni, jernej.skrabec, plaes, devicetree,
linux-kernel, dri-devel, Rob Herring, thierry.reding,
linux-arm-kernel, icenowy
In-Reply-To: <cover.e46a07c0e181d735c807dc94fe0ce0ea013788be.1512662253.git-series.maxime.ripard@free-electrons.com>
When we added the regulator support in commit 90c5d7cdae64 ("ARM: dts:
sun8i: a711: Add regulator support"), we also dropped the PMIC's
compatible. Since it's not in the PMIC DTSI, unlike most other PMIC
DTSI, it obviously wasn't probing anymore.
Re-add it so that everything works again.
Fixes: 90c5d7cdae64 ("ARM: dts: sun8i: a711: Add regulator support")
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 98715538932f..a021ee6da396 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -146,6 +146,7 @@
status = "okay";
axp81x: pmic@3a3 {
+ compatible = "x-powers,axp813";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
--
git-series 0.9.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH v4 13/15] ARM: dts: sun8i: a83t: Add the PWM pin group
From: Maxime Ripard @ 2017-12-07 15:58 UTC (permalink / raw)
To: Daniel Vetter, David Airlie, Chen-Yu Tsai, Maxime Ripard
Cc: dri-devel, linux-kernel, Mark Rutland, Rob Herring,
linux-arm-kernel, plaes, icenowy, Thomas Petazzoni,
jernej.skrabec, devicetree, thierry.reding
In-Reply-To: <cover.e46a07c0e181d735c807dc94fe0ce0ea013788be.1512662253.git-series.maxime.ripard@free-electrons.com>
The A83T has a PWM that can be output from the SoC. Let's add a pinctrl
group for it.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index e200df5a9058..a37517d4472a 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -446,6 +446,11 @@
bias-pull-up;
};
+ pwm_pin: pwm-pin {
+ pins = "PD28";
+ function = "pwm";
+ };
+
spdif_tx_pin: spdif-tx-pin {
pins = "PE18";
function = "spdif";
--
git-series 0.9.1
^ permalink raw reply related
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