* Re: [PATCH 02/20] dt-bindings: gpio: Add ASPEED constants
From: Joel Stanley @ 2017-12-11 10:43 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Rob Herring, Mark Rutland, Andrew Jeffery, Patrick Venture,
Xo Wang, Lei YU, Cédric Le Goater, Benjamin Herrenschmidt,
Jeremy Kerr, DTML, Linux ARM, Linux Kernel Mailing List,
linux-aspeed-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <CAK8P3a17iWxJVv=f+=w+4sS7zWimxMSD5+Gz9qC5ms-RrcQneg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Mon, Dec 11, 2017 at 6:26 PM, Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> wrote:
> On Mon, Dec 11, 2017 at 6:06 AM, Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org> wrote:
>> These are used to by the device tree to map pin numbers to constants
>> required by the GPIO bindings.
>> +
>> +#define ASPEED_GPIO_PORT_A 0
>> +#define ASPEED_GPIO_PORT_B 1
>> +#define ASPEED_GPIO_PORT_C 2
>> +#define ASPEED_GPIO_PORT_D 3
>> +#define ASPEED_GPIO_PORT_E 4
>> +#define ASPEED_GPIO_PORT_F 5
>> +#define ASPEED_GPIO_PORT_G 6
>> +#define ASPEED_GPIO_PORT_H 7
>> +#define ASPEED_GPIO_PORT_I 8
>> +#define ASPEED_GPIO_PORT_J 9
>> +#define ASPEED_GPIO_PORT_K 10
>> +#define ASPEED_GPIO_PORT_L 11
>> +#define ASPEED_GPIO_PORT_M 12
>> +#define ASPEED_GPIO_PORT_N 13
>> +#define ASPEED_GPIO_PORT_O 14
>> +#define ASPEED_GPIO_PORT_P 15
>> +#define ASPEED_GPIO_PORT_Q 16
>> +#define ASPEED_GPIO_PORT_R 17
>> +#define ASPEED_GPIO_PORT_S 18
>> +#define ASPEED_GPIO_PORT_T 19
>> +#define ASPEED_GPIO_PORT_U 20
>> +#define ASPEED_GPIO_PORT_V 21
>> +#define ASPEED_GPIO_PORT_W 22
>> +#define ASPEED_GPIO_PORT_X 23
>> +#define ASPEED_GPIO_PORT_Y 24
>> +#define ASPEED_GPIO_PORT_Z 25
>> +#define ASPEED_GPIO_PORT_AA 26
>> +#define ASPEED_GPIO_PORT_AB 27
>> +#define ASPEED_GPIO_PORT_AC 28
>
> This looks like a 1:1 mapping, wouldn't it be easier to just describe
> it in the binding document?
You're right, it is a linear mapping. We use it so references to GPIO
numbers are human readable in the device tree:
#define ASPEED_GPIO(port, offset) \
((ASPEED_GPIO_PORT_##port * 8) + offset)
can be used:
identify {
gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
};
We find that has cut down on mistakes in calculating offsets into GPIO banks.
Cheers,
Joel
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* Re: [PATCH 03/20] ARM: dts: aspeed-g4: Correct VUART IRQ number
From: Joel Stanley @ 2017-12-11 10:44 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Rob Herring, Mark Rutland, Andrew Jeffery, Patrick Venture,
Xo Wang, Lei YU, Cédric Le Goater, Benjamin Herrenschmidt,
Jeremy Kerr, DTML, Linux ARM, Linux Kernel Mailing List,
linux-aspeed
In-Reply-To: <CAK8P3a2psgOYZEgO8O3H_xxpDTNd=ESJpSf4bs9kf0nPvKYqtQ@mail.gmail.com>
On Mon, Dec 11, 2017 at 6:28 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Mon, Dec 11, 2017 at 6:06 AM, Joel Stanley <joel@jms.id.au> wrote:
>> This should have always been 8.
>>
>> Signed-off-by: Joel Stanley <joel@jms.id.au>
>
> As this is a bugfix, should we backport it to stable kernels? When you
> fix a bug,
> I generally recommend including a 'Fixes' tag with the commit ID of the patch
> that introduced the problem, and either a 'Cc: stable@vger.kernel.org' tag
> if you want it backported, or an explanation in the changelog why it should
> not get backported. This really helps Greg and the other stable maintainers
> trying to make a decision what to backport and what not.
We could do this, and I generally follow the practice of adding Fixes
tags. I hadn't because without an upstream clock driver, the Aspeed
port is not usable by anyone without making modifications. We're
really depending on getting that code merged.
I will send it as a fix to 4.15. Do you mind taking individual patches
for the arm dt tree, or would you prefer a pull request?
Cheers,
Joel
^ permalink raw reply
* Re: [PATCH 05/20] ARM: dts: aspeed: Add proper clock references
From: Joel Stanley @ 2017-12-11 10:44 UTC (permalink / raw)
To: Arnd Bergmann, Andrew Jeffery
Cc: Rob Herring, Mark Rutland, Patrick Venture, Xo Wang, Lei YU,
Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr, DTML,
Linux ARM, Linux Kernel Mailing List, linux-aspeed
In-Reply-To: <CAK8P3a10wjXvFpE5zbwCfQNC-UiRCzKE+9-ENg-Sr577ZCF+Xw@mail.gmail.com>
On Mon, Dec 11, 2017 at 6:39 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Mon, Dec 11, 2017 at 6:06 AM, Joel Stanley <joel@jms.id.au> wrote:
>> The existing device trees use fixed-clocks in order to boot without a
>> clk driver. The newly added clk driver provides proper clock support,
>> including gating, so we move the device trees over to properly request
>> clocks.
>>
>> Signed-off-by: Joel Stanley <joel@jms.id.au>
>
> Can you clarify here whether this will break running old kernels with
> new DT files or vice versa, and why this is ok here?
This device tree will break kernels that do not have the clk patches
applied (no clocksource, as we don't know the speed of the APB clock.
You can boot if you pass a lpj value on the command line, but won't
have a uart).
Older device trees running with the newer kernel will function as well
as pre-4.16 kernels. That is, that some IP blocks (i2c, pwm/tach, adc)
will not work as the kernel lacks reset controller and clock enabling.
> I assume you have thought about it carefully, but I'd still like to document
> every time we intentionally break compatibility like this. It looks like
> you too care to merge the driver changes and the DT binding change first,
> so we don't get any bisection problems.
Thanks for calling it out. I will modify the commit message to say
that this device tree change depends on the newer driver, and it will
not boot with kernels that lack the driver.
>
> What I'm not completely clear about is the difference between the
> "aspeed,g4-scu" binding and the "aspeed,ast2400-scu" binding.
> They are listed as equal in
> Documentation/devicetree/bindings/mfd/aspeed-scu.txt, so why do you
> change it here?
The g4-scu string made it into the tree before we had decided that we
would settle on aspeed,astX000-<ip> as the format for the strings. We
list both in the docs, but I would like to deprecate the old one.
If I was doing this again, I would make sure we had the clock driver
upstream before completing the other driver. It's caused a lot of
pain. Thanks for your help getting us there.
Cheers,
Joel
^ permalink raw reply
* Re: [PATCH V3 0/2] Tegra PCIe end point config space map code refactoring
From: Thierry Reding @ 2017-12-11 10:54 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Vidya Sagar, treding-DDmLM1+adcrQT0dZR+AlfA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-pci-u79uwXL29TY76Z2rM5mHXA, kthota-DDmLM1+adcrQT0dZR+AlfA,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512410030-21038-1-git-send-email-vidyas-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1968 bytes --]
On Mon, Dec 04, 2017 at 11:23:48PM +0530, Vidya Sagar wrote:
> PCIe host controller in Tegra SoCs has 1GB of aperture available
> for mapping end points config space, IO and BARs. In that, currently
> 256MB is being reserved for mapping end points configuration space
> which leaves less memory space available for mapping end points BARs
> on some of the platforms.
> This patch series attempts to map only 4K space from 1GB aperture to
> access end points configuration space.
>
> Currently, this change can benefit T20 and T186 in saving (i.e. repurposed
> to use for BAR mapping) physical space as well as kernel virtual mapping space,
> it saves only kernel virtual address space in T30, T124, T132 and T210.
>
> NOTE: Since T186 PCIe DT entry is not yet present in main line (it is currently
> merged to 'for-4.15/arm64/dt' branch), nothing gets broken with this change for T186.
> For older platforms (T20, T30, T124, T132, T210), this change works fine without any
> DT modifications
>
> Testing Done on T124, T210 & T186:
> Enumeration and basic functionality of immediate devices
> Enumeration of devices behind a PCIe switch
> Complete 4K configuration space access
>
> Vidya Sagar (2):
> PCI: tegra: refactor config space mapping code
> ARM64: tegra: limit PCIe config space mapping to 4K for T186
>
> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 +-
> drivers/pci/host/pci-tegra.c | 125 ++++++++++---------------------
> 2 files changed, 44 insertions(+), 89 deletions(-)
Hi Bjorn,
there's a bunch of PCI related patches for Tegra floating around on the
lists. I'm wondering if you'd be okay if I pick those up into the Tegra
tree after they've been reviewed and send you a pull request later on
(say around v4.15-rc6). That would allow me to get things cooking in
linux-next for a bit and get broader testing in addition to the
flexibility to patch things up if they break.
Thierry
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* [PATCH v3 0/4] rtc: add mxc driver for i.MX53 SRTC
From: linux-kernel-dev-QonKdJ6Bx35Wk0Htik3J/w @ 2017-12-11 10:56 UTC (permalink / raw)
Cc: Patrick Bruenn, Alexandre Belloni, Rob Herring, Mark Rutland,
open list:REAL TIME CLOCK (RTC) SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Fabio Estevam, Juergen Borleis, Noel Vellemans,
Shawn Guo, Sascha Hauer, Russell King,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Philippe Ombredanne
From: Patrick Bruenn <p.bruenn-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
Neither rtc-imxdi, rtc-mxc nor rtc-snvs are compatible with i.MX53.
This is driver enables support for the low power domain SRTC features:
- 32-bit MSB of non-rollover time counter
- 32-bit alarm register
Select the new config option RTC_DRV_MXC_V2 to build this driver
Based on:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/drivers/rtc/rtc-mxc_v2.c?h=imx_2.6.35_11.09.01
Signed-off-by: Patrick Bruenn <p.bruenn-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
---
Open issue:
- naming of the device tree node "rtc" vs. "srtc"
v3:
- introduce new config option with the same patch, which adds the driver
- call rtc_update_irq() only if necessary
- merge mxc_rtc_write_alarm_locked() with mxc_rtc_set_alarm()
- only use clk_enable/disable (without "prepare") during operation
- rebase on v4.15-rc3
- consistently use rtc_tm_to_time64() and time64_t
- refactor mxc_rtc_read_time(): don't lock for readl() only;
don't rtc_valid_tm(); use time64_t
- check returncode of mxc_rtc_wait_for_flag()
- restructure mxc_rtc_sync_lp_locked() to replace pr_err() with
dev_err_once(); remove explicit 'inline'
- don't touch imx_v4_v5_defconfig, instead add to imx_v6_v7_defconfig
v2:
- have seperate patches for dt-binding, CONFIG option, imx53.dtsi and driver
- add SPDX-License-Identifier and cleanup copyright notice
- replace __raw_readl/writel() with readl/writel()
- fix PM_SLEEP callbacks
- add CONFIG_RTC_DRV_MXC_V2 to build rtc-mxc_v2.c
- remove misleading or obvious comments and fix style of the remaining
- avoid endless loop while waiting for hw
- implement consistent locking; make spinlock a member of dev struct
- enable clk only for register accesses
- remove all udelay() calls since they are obsolete or redundant
(we are already waiting for register flags to change)
- init platform_data before registering irq callback
- let set_time() fail, when 32 bit rtc counter exceeded
- make names more consistent
- cleanup and reorder includes
- cleanup and remove unused defines
To: Alessandro Zummo <a.zummo-BfzFCNDTiLLj+vYz1yj4TQ@public.gmane.org>
Cc: Alexandre Belloni <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-rtc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM)
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list)
Cc: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
Cc: Juergen Borleis <jbe-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Cc: Noel Vellemans <Noel.Vellemans-8UENEgx6w+makBO8gow8eQ@public.gmane.org>
Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> (maintainer:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org> (maintainer:ARM PORT)
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Philippe Ombredanne <pombredanne-od1rfyK75/E@public.gmane.org>
Cc: Lothar Waßmann <LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org>
Patrick Bruenn (4):
dt-bindings: rtc: add bindings for i.MX53 SRTC
ARM: dts: imx53: add srtc node
rtc: add mxc driver for i.MX53 SRTC
ARM: imx_v6_v7_defconfig: enable RTC_DRV_MXC_V2
.../devicetree/bindings/rtc/rtc-mxc_v2.txt | 17 +
arch/arm/boot/dts/imx53.dtsi | 7 +
arch/arm/configs/imx_v6_v7_defconfig | 1 +
drivers/rtc/Kconfig | 10 +
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-mxc_v2.c | 422 +++++++++++++++++++++
6 files changed, 458 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt
create mode 100644 drivers/rtc/rtc-mxc_v2.c
--
2.11.0
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^ permalink raw reply
* [PATCH v3 1/4] dt-bindings: rtc: add bindings for i.MX53 SRTC
From: linux-kernel-dev-QonKdJ6Bx35Wk0Htik3J/w @ 2017-12-11 10:56 UTC (permalink / raw)
Cc: Patrick Bruenn, Patrick Bruenn, Alessandro Zummo,
Alexandre Belloni, Rob Herring, Mark Rutland,
open list:REAL TIME CLOCK (RTC) SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Fabio Estevam, Juergen Borleis, Noel Vellemans,
Shawn Guo, Sascha Hauer, Russell King, ARM/FREESCALE
In-Reply-To: <20171211105657.20251-1-linux-kernel-dev-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
From: Patrick Bruenn <p.bruenn-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
Document the binding for i.MX53 SRTC implemented by rtc-mxc_v2
Signed-off-by: Patrick Bruenn <p.bruenn-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org><Paste>
---
v2:
- added "Secure" and (SRTC) to the description
Cc: Alessandro Zummo <a.zummo-BfzFCNDTiLLj+vYz1yj4TQ@public.gmane.org>
Cc: Alexandre Belloni <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-rtc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM)
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list)
Cc: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
Cc: Juergen Borleis <jbe-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Cc: Noel Vellemans <Noel.Vellemans-8UENEgx6w+makBO8gow8eQ@public.gmane.org>
Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> (maintainer:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org> (maintainer:ARM PORT)
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Philippe Ombredanne <pombredanne-od1rfyK75/E@public.gmane.org>
Cc: Lothar Waßmann <LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org>
---
Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt
diff --git a/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt b/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt
new file mode 100644
index 000000000000..454a08918cc3
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt
@@ -0,0 +1,17 @@
+* i.MX53 Secure Real Time Clock (SRTC)
+
+Required properties:
+- compatible: should be: "fsl,imx53-rtc"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- clocks: should contain the phandle for the rtc clock
+- interrupts: rtc alarm interrupt
+
+Example:
+
+srtc@53fa4000 {
+ compatible = "fsl,imx53-rtc";
+ reg = <0x53fa4000 0x4000>;
+ interrupts = <24>;
+ clocks = <&clks IMX5_CLK_SRTC_GATE>;
+};
--
2.11.0
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* [PATCH v3 2/4] ARM: dts: imx53: add srtc node
From: linux-kernel-dev @ 2017-12-11 10:56 UTC (permalink / raw)
Cc: Patrick Bruenn, Shawn Guo, Sascha Hauer, Alessandro Zummo,
Alexandre Belloni, Rob Herring, Mark Rutland,
open list:REAL TIME CLOCK (RTC) SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Fabio Estevam, Juergen Borleis, Noel Vellemans,
Russell King,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Ph
In-Reply-To: <20171211105657.20251-1-linux-kernel-dev@beckhoff.com>
From: Patrick Bruenn <p.bruenn@beckhoff.com>
rtc-mxc_v2 driver will add support for the i.MX53 SRTC
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
---
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de> (maintainer:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-rtc@vger.kernel.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM)
Cc: devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-kernel@vger.kernel.org (open list)
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Juergen Borleis <jbe@pengutronix.de>
Cc: Noel Vellemans <Noel.Vellemans@visionbms.com>
Cc: Russell King <linux@armlinux.org.uk> (maintainer:ARM PORT)
Cc: linux-arm-kernel@lists.infradead.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Philippe Ombredanne <pombredanne@nexb.com>
Cc: Lothar Waßmann <LW@KARO-electronics.de>
---
arch/arm/boot/dts/imx53.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 84f17f7abb71..e4ca9d9ba2fe 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -433,6 +433,13 @@
clock-names = "ipg", "per";
};
+ srtc: srtc@53fa4000 {
+ compatible = "fsl,imx53-rtc";
+ reg = <0x53fa4000 0x4000>;
+ interrupts = <24>;
+ clocks = <&clks IMX5_CLK_SRTC_GATE>;
+ };
+
iomuxc: iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc";
reg = <0x53fa8000 0x4000>;
--
2.11.0
^ permalink raw reply related
* [PATCH v3 3/4] rtc: add mxc driver for i.MX53 SRTC
From: linux-kernel-dev-QonKdJ6Bx35Wk0Htik3J/w @ 2017-12-11 10:56 UTC (permalink / raw)
Cc: Patrick Bruenn, Alessandro Zummo, Alexandre Belloni, Rob Herring,
Mark Rutland, open list:REAL TIME CLOCK (RTC) SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Fabio Estevam, Juergen Borleis, Noel Vellemans,
Shawn Guo, Sascha Hauer, Russell King,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Ph
In-Reply-To: <20171211105657.20251-1-linux-kernel-dev-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
From: Patrick Bruenn <p.bruenn-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
Neither rtc-imxdi, rtc-mxc nor rtc-snvs are compatible with i.MX53.
This is driver enables support for the low power domain SRTC features:
- 32-bit MSB of non-rollover time counter
- 32-bit alarm register
Select the new config option RTC_DRV_MXC_V2 to build this driver
Based on:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/drivers/rtc/rtc-mxc_v2.c?h=imx_2.6.35_11.09.01
Signed-off-by: Patrick Bruenn <p.bruenn-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
---
Open issue:
- naming of the device tree node "rtc" vs. "srtc"
v3:
- introduce new config option with the same patch, which adds the driver
- call rtc_update_irq() only if necessary
- merge mxc_rtc_write_alarm_locked() with mxc_rtc_set_alarm()
- only use clk_enable/disable (without "prepare") during operation
- rebase on v4.15-rc3
- consistently use rtc_tm_to_time64() and time64_t
- refactor mxc_rtc_read_time(): don't lock for readl() only;
don't rtc_valid_tm(); use time64_t
- check returncode of mxc_rtc_wait_for_flag()
- restructure mxc_rtc_sync_lp_locked() to replace pr_err() with
dev_err_once(); remove explicit 'inline'
- don't touch imx_v4_v5_defconfig, instead add to imx_v6_v7_defconfig
v2:
- have seperate patches for dt-binding, CONFIG option, imx53.dtsi and driver
- add SPDX-License-Identifier and cleanup copyright notice
- replace __raw_readl/writel() with readl/writel()
- fix PM_SLEEP callbacks
- add CONFIG_RTC_DRV_MXC_V2 to build rtc-mxc_v2.c
- remove misleading or obvious comments and fix style of the remaining
- avoid endless loop while waiting for hw
- implement consistent locking; make spinlock a member of dev struct
- enable clk only for register accesses
- remove all udelay() calls since they are obsolete or redundant
(we are already waiting for register flags to change)
- init platform_data before registering irq callback
- let set_time() fail, when 32 bit rtc counter exceeded
- make names more consistent
- cleanup and reorder includes
- cleanup and remove unused defines
Cc: Alessandro Zummo <a.zummo-BfzFCNDTiLLj+vYz1yj4TQ@public.gmane.org>
Cc: Alexandre Belloni <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-rtc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM)
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list)
Cc: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
Cc: Juergen Borleis <jbe-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Cc: Noel Vellemans <Noel.Vellemans-8UENEgx6w+makBO8gow8eQ@public.gmane.org>
Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> (maintainer:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org> (maintainer:ARM PORT)
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Philippe Ombredanne <pombredanne-od1rfyK75/E@public.gmane.org>
Cc: Lothar Waßmann <LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org>
---
drivers/rtc/Kconfig | 10 ++
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-mxc_v2.c | 422 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 433 insertions(+)
create mode 100644 drivers/rtc/rtc-mxc_v2.c
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index b59a31b079a5..440edebf5c71 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1689,6 +1689,16 @@ config RTC_DRV_MXC
This driver can also be built as a module, if so, the module
will be called "rtc-mxc".
+config RTC_DRV_MXC_V2
+ tristate "Freescale MXC Real Time Clock for i.MX53"
+ depends on ARCH_MXC
+ help
+ If you say yes here you get support for the Freescale MXC
+ SRTC module in i.MX53 processor.
+
+ This driver can also be built as a module, if so, the module
+ will be called "rtc-mxc_v2".
+
config RTC_DRV_SNVS
tristate "Freescale SNVS RTC support"
select REGMAP_MMIO
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index f2f50c11dc38..dcf60e61ae5c 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -106,6 +106,7 @@ obj-$(CONFIG_RTC_DRV_MT6397) += rtc-mt6397.o
obj-$(CONFIG_RTC_DRV_MT7622) += rtc-mt7622.o
obj-$(CONFIG_RTC_DRV_MV) += rtc-mv.o
obj-$(CONFIG_RTC_DRV_MXC) += rtc-mxc.o
+obj-$(CONFIG_RTC_DRV_MXC_V2) += rtc-mxc_v2.o
obj-$(CONFIG_RTC_DRV_NUC900) += rtc-nuc900.o
obj-$(CONFIG_RTC_DRV_OMAP) += rtc-omap.o
obj-$(CONFIG_RTC_DRV_OPAL) += rtc-opal.o
diff --git a/drivers/rtc/rtc-mxc_v2.c b/drivers/rtc/rtc-mxc_v2.c
new file mode 100644
index 000000000000..b637095b0716
--- /dev/null
+++ b/drivers/rtc/rtc-mxc_v2.c
@@ -0,0 +1,422 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Real Time Clock (RTC) Driver for i.MX53
+ * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
+ * Copyright (c) 2017 Beckhoff Automation GmbH & Co. KG
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/rtc.h>
+
+#define SRTC_LPPDR_INIT 0x41736166 /* init for glitch detect */
+
+#define SRTC_LPCR_EN_LP BIT(3) /* lp enable */
+#define SRTC_LPCR_WAE BIT(4) /* lp wakeup alarm enable */
+#define SRTC_LPCR_ALP BIT(7) /* lp alarm flag */
+#define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
+#define SRTC_LPCR_NVE BIT(14) /* lp non valid state exit bit */
+#define SRTC_LPCR_IE BIT(15) /* lp init state exit bit */
+
+#define SRTC_LPSR_ALP BIT(3) /* lp alarm flag */
+#define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
+#define SRTC_LPSR_IES BIT(15) /* lp init state exit status */
+
+#define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
+#define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
+#define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
+#define SRTC_LPCR 0x10 /* LP Control Reg */
+#define SRTC_LPSR 0x14 /* LP Status Reg */
+#define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
+
+/* max. number of retries to read registers, 120 was max during test */
+#define REG_READ_TIMEOUT 2000
+
+struct mxc_rtc_data {
+ struct rtc_device *rtc;
+ void __iomem *ioaddr;
+ struct clk *clk;
+ spinlock_t lock; /* protects register access */
+ int irq;
+};
+
+/*
+ * This function does write synchronization for writes to the lp srtc block.
+ * To take care of the asynchronous CKIL clock, all writes from the IP domain
+ * will be synchronized to the CKIL domain.
+ * The caller should hold the pdata->lock
+ */
+static void mxc_rtc_sync_lp_locked(struct device *dev, void __iomem *ioaddr)
+{
+ unsigned int i;
+
+ /* Wait for 3 CKIL cycles */
+ for (i = 0; i < 3; i++) {
+ const u32 count = readl(ioaddr + SRTC_LPSCLR);
+ unsigned int timeout = REG_READ_TIMEOUT;
+
+ while ((readl(ioaddr + SRTC_LPSCLR)) == count) {
+ if (!--timeout) {
+ dev_err_once(dev, "SRTC_LPSCLR stuck! Check your hw.\n");
+ return;
+ }
+ }
+ }
+}
+
+/* This function is the RTC interrupt service routine. */
+static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
+{
+ struct device *dev = dev_id;
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+ void __iomem *ioaddr = pdata->ioaddr;
+ unsigned long flags;
+ u32 lp_status;
+ u32 lp_cr;
+
+ spin_lock_irqsave(&pdata->lock, flags);
+ if (clk_enable(pdata->clk)) {
+ spin_unlock_irqrestore(&pdata->lock, flags);
+ return IRQ_NONE;
+ }
+
+ lp_status = readl(ioaddr + SRTC_LPSR);
+ lp_cr = readl(ioaddr + SRTC_LPCR);
+
+ /* update irq data & counter */
+ if (lp_status & SRTC_LPSR_ALP) {
+ if (lp_cr & SRTC_LPCR_ALP)
+ rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF);
+
+ /* disable further lp alarm interrupts */
+ lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+ }
+
+ /* Update interrupt enables */
+ writel(lp_cr, ioaddr + SRTC_LPCR);
+
+ /* clear interrupt status */
+ writel(lp_status, ioaddr + SRTC_LPSR);
+
+ mxc_rtc_sync_lp_locked(dev, ioaddr);
+ clk_disable(pdata->clk);
+ spin_unlock_irqrestore(&pdata->lock, flags);
+ return IRQ_HANDLED;
+}
+
+/*
+ * Enable clk and aquire spinlock
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_lock(struct mxc_rtc_data *const pdata)
+{
+ int ret;
+
+ spin_lock_irq(&pdata->lock);
+ ret = clk_enable(pdata->clk);
+ if (ret) {
+ spin_unlock_irq(&pdata->lock);
+ return ret;
+ }
+ return 0;
+}
+
+static int mxc_rtc_unlock(struct mxc_rtc_data *const pdata)
+{
+ clk_disable(pdata->clk);
+ spin_unlock_irq(&pdata->lock);
+ return 0;
+}
+
+/*
+ * This function reads the current RTC time into tm in Gregorian date.
+ *
+ * @param tm contains the RTC time value upon return
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+ const int clk_failed = clk_enable(pdata->clk);
+
+ if (!clk_failed) {
+ const time64_t now = readl(pdata->ioaddr + SRTC_LPSCMR);
+
+ rtc_time64_to_tm(now, tm);
+ clk_disable(pdata->clk);
+ return 0;
+ }
+ return clk_failed;
+}
+
+/*
+ * This function sets the internal RTC time based on tm in Gregorian date.
+ *
+ * @param tm the time value to be set in the RTC
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+ time64_t time = rtc_tm_to_time64(tm);
+ int ret;
+
+ if (time > U32_MAX) {
+ dev_err(dev, "RTC exceeded by %llus\n", time - U32_MAX);
+ return -EINVAL;
+ }
+
+ ret = mxc_rtc_lock(pdata);
+ if (ret)
+ return ret;
+
+ writel(time, pdata->ioaddr + SRTC_LPSCMR);
+ mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
+ return mxc_rtc_unlock(pdata);
+}
+
+/*
+ * This function reads the current alarm value into the passed in \b alrm
+ * argument. It updates the \b alrm's pending field value based on the whether
+ * an alarm interrupt occurs or not.
+ *
+ * @param alrm contains the RTC alarm value upon return
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+ void __iomem *ioaddr = pdata->ioaddr;
+ int ret;
+
+ ret = mxc_rtc_lock(pdata);
+ if (ret)
+ return ret;
+
+ rtc_time_to_tm(readl(ioaddr + SRTC_LPSAR), &alrm->time);
+ alrm->pending = !!(readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_ALP);
+ return mxc_rtc_unlock(pdata);
+}
+
+/*
+ * Enable/Disable alarm interrupt
+ * The caller should hold the pdata->lock
+ */
+static void mxc_rtc_alarm_irq_enable_locked(struct mxc_rtc_data *pdata,
+ unsigned int enable)
+{
+ u32 lp_cr = readl(pdata->ioaddr + SRTC_LPCR);
+
+ if (enable)
+ lp_cr |= (SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+ else
+ lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+
+ writel(lp_cr, pdata->ioaddr + SRTC_LPCR);
+}
+
+static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+ int ret = mxc_rtc_lock(pdata);
+
+ if (ret)
+ return ret;
+
+ mxc_rtc_alarm_irq_enable_locked(pdata, enable);
+ return mxc_rtc_unlock(pdata);
+}
+
+/*
+ * This function sets the RTC alarm based on passed in alrm.
+ *
+ * @param alrm the alarm value to be set in the RTC
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ const time64_t time = rtc_tm_to_time64(&alrm->time);
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+ int ret = mxc_rtc_lock(pdata);
+
+ if (ret)
+ return ret;
+
+ if (time > U32_MAX) {
+ dev_err(dev, "Hopefully I am out of service by then :-(\n");
+ return -EINVAL;
+ }
+
+ writel((u32)time, pdata->ioaddr + SRTC_LPSAR);
+
+ /* clear alarm interrupt status bit */
+ writel(SRTC_LPSR_ALP, pdata->ioaddr + SRTC_LPSR);
+ mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
+
+ mxc_rtc_alarm_irq_enable_locked(pdata, alrm->enabled);
+ mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
+ mxc_rtc_unlock(pdata);
+ return ret;
+}
+
+static const struct rtc_class_ops mxc_rtc_ops = {
+ .read_time = mxc_rtc_read_time,
+ .set_time = mxc_rtc_set_time,
+ .read_alarm = mxc_rtc_read_alarm,
+ .set_alarm = mxc_rtc_set_alarm,
+ .alarm_irq_enable = mxc_rtc_alarm_irq_enable,
+};
+
+static int mxc_rtc_wait_for_flag(void *__iomem ioaddr, int flag)
+{
+ unsigned int timeout = REG_READ_TIMEOUT;
+
+ while (!(readl(ioaddr) & flag)) {
+ if (!--timeout)
+ return -EBUSY;
+ }
+ return 0;
+}
+
+static int mxc_rtc_probe(struct platform_device *pdev)
+{
+ struct mxc_rtc_data *pdata;
+ struct resource *res;
+ void __iomem *ioaddr;
+ int ret = 0;
+
+ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
+
+ pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(pdata->ioaddr))
+ return PTR_ERR(pdata->ioaddr);
+
+ ioaddr = pdata->ioaddr;
+
+ pdata->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(pdata->clk)) {
+ dev_err(&pdev->dev, "unable to get rtc clock!\n");
+ return PTR_ERR(pdata->clk);
+ }
+
+ spin_lock_init(&pdata->lock);
+ pdata->irq = platform_get_irq(pdev, 0);
+ if (pdata->irq < 0)
+ return pdata->irq;
+
+ device_init_wakeup(&pdev->dev, 1);
+
+ ret = clk_prepare_enable(pdata->clk);
+ if (ret)
+ return ret;
+ /* initialize glitch detect */
+ writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR);
+
+ /* clear lp interrupt status */
+ writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
+
+ /* move out of init state */
+ writel((SRTC_LPCR_IE | SRTC_LPCR_NSA), ioaddr + SRTC_LPCR);
+ ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_IES);
+ if (ret) {
+ dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_IES\n");
+ clk_disable_unprepare(pdata->clk);
+ return ret;
+ }
+
+ /* move out of non-valid state */
+ writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA |
+ SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR);
+ ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_NVES);
+ if (ret) {
+ dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_NVES\n");
+ clk_disable_unprepare(pdata->clk);
+ return ret;
+ }
+
+ clk_disable(pdata->clk);
+ platform_set_drvdata(pdev, pdata);
+ ret =
+ devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt, 0,
+ pdev->name, &pdev->dev);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "interrupt not available.\n");
+ clk_unprepare(pdata->clk);
+ return ret;
+ }
+
+ pdata->rtc =
+ devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops,
+ THIS_MODULE);
+ if (IS_ERR(pdata->rtc)) {
+ clk_unprepare(pdata->clk);
+ return PTR_ERR(pdata->rtc);
+ }
+
+ return 0;
+}
+
+static int __exit mxc_rtc_remove(struct platform_device *pdev)
+{
+ struct mxc_rtc_data *pdata = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(pdata->clk);
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int mxc_rtc_suspend(struct device *dev)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+
+ if (device_may_wakeup(dev))
+ enable_irq_wake(pdata->irq);
+
+ return 0;
+}
+
+static int mxc_rtc_resume(struct device *dev)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+
+ if (device_may_wakeup(dev))
+ disable_irq_wake(pdata->irq);
+
+ return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume);
+
+static const struct of_device_id mxc_ids[] = {
+ { .compatible = "fsl,imx53-rtc", },
+ {}
+};
+
+static struct platform_driver mxc_rtc_driver = {
+ .driver = {
+ .name = "mxc_rtc_v2",
+ .of_match_table = mxc_ids,
+ .pm = &mxc_rtc_pm_ops,
+ },
+ .probe = mxc_rtc_probe,
+ .remove = mxc_rtc_remove,
+};
+
+module_platform_driver(mxc_rtc_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Real Time Clock (RTC) Driver for i.MX53");
+MODULE_LICENSE("GPL");
--
2.11.0
--
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^ permalink raw reply related
* [PATCH v3 4/4] ARM: imx_v6_v7_defconfig: enable RTC_DRV_MXC_V2
From: linux-kernel-dev-QonKdJ6Bx35Wk0Htik3J/w @ 2017-12-11 10:56 UTC (permalink / raw)
Cc: Patrick Bruenn, Shawn Guo, Sascha Hauer, Alessandro Zummo,
Alexandre Belloni, Rob Herring, Mark Rutland,
open list:REAL TIME CLOCK (RTC) SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Fabio Estevam, Juergen Borleis, Noel Vellemans,
Russell King,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Ph
In-Reply-To: <20171211105657.20251-1-linux-kernel-dev-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
From: Patrick Bruenn <p.bruenn-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
Enable SRTC driver for i.MX53 in default config
Signed-off-by: Patrick Bruenn <p.bruenn-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
---
v3:
- imx_v4_v5_defconfig was the wrong default config for i.MX53
Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> (maintainer:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Alessandro Zummo <a.zummo-BfzFCNDTiLLj+vYz1yj4TQ@public.gmane.org>
Cc: Alexandre Belloni <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-rtc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM)
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list)
Cc: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
Cc: Juergen Borleis <jbe-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Cc: Noel Vellemans <Noel.Vellemans-8UENEgx6w+makBO8gow8eQ@public.gmane.org>
Cc: Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org> (maintainer:ARM PORT)
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Philippe Ombredanne <pombredanne-od1rfyK75/E@public.gmane.org>
Cc: Lothar Waßmann <LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org>
---
arch/arm/configs/imx_v6_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 0d4494922561..548c11142a4e 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -349,6 +349,7 @@ CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_M41T80=y
CONFIG_RTC_DRV_MC13XXX=y
CONFIG_RTC_DRV_MXC=y
+CONFIG_RTC_DRV_MXC_V2=y
CONFIG_RTC_DRV_SNVS=y
CONFIG_DMADEVICES=y
CONFIG_FSL_EDMA=y
--
2.11.0
--
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^ permalink raw reply related
* Re: [PATCH v6 4/6] clk: meson: make the spinlock naming more specific
From: Jerome Brunet @ 2017-12-11 11:27 UTC (permalink / raw)
To: Yixun Lan, Neil Armstrong, Kevin Hilman
Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd,
Carlo Caione, Qiufang Dai, Jian Hu, linux-amlogic, devicetree,
linux-clk, linux-arm-kernel, linux-kernel
In-Reply-To: <20171211064853.32111-5-yixun.lan@amlogic.com>
On Mon, 2017-12-11 at 14:48 +0800, Yixun Lan wrote:
> .ops = &clk_gate_ops,
> diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
> index 1629da9b4141..87f06a801a4d 100644
> --- a/drivers/clk/meson/clkc.h
> +++ b/drivers/clk/meson/clkc.h
> @@ -134,7 +134,7 @@ struct meson_clk_audio_divider {
> struct clk_gate _name = { \
> .reg = (void __iomem *) _reg, \
> .bit_idx = (_bit), \
> - .lock = &clk_lock, \
> + .lock = &meson_clk_lock, \
Something is not right here, line is over 80 characters
Remember to run checkpatch on your series please.
> .hw.init = &(struct clk_init_data) { \
> .name = #_name, \
> .ops = &clk_gate_ops, \
^ permalink raw reply
* Re: [PATCH v3 3/4] rtc: add mxc driver for i.MX53 SRTC
From: Philippe Ombredanne @ 2017-12-11 11:28 UTC (permalink / raw)
To: linux-kernel-dev
Cc: Patrick Bruenn, Alessandro Zummo, Alexandre Belloni, Rob Herring,
Mark Rutland, open list:REAL TIME CLOCK (RTC) SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Fabio Estevam, Juergen Borleis, Noel Vellemans,
Shawn Guo, Sascha Hauer, Russell King,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20171211105657.20251-4-linux-kernel-dev-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
On Mon, Dec 11, 2017 at 11:56 AM, <linux-kernel-dev-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org> wrote:
> From: Patrick Bruenn <p.bruenn-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
>
> Neither rtc-imxdi, rtc-mxc nor rtc-snvs are compatible with i.MX53.
>
> This is driver enables support for the low power domain SRTC features:
> - 32-bit MSB of non-rollover time counter
> - 32-bit alarm register
>
> Select the new config option RTC_DRV_MXC_V2 to build this driver
>
> Based on:
> http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/drivers/rtc/rtc-mxc_v2.c?h=imx_2.6.35_11.09.01
>
> Signed-off-by: Patrick Bruenn <p.bruenn-QonKdJ6Bx35Wk0Htik3J/w@public.gmane.org>
[...]
> v2:
[...]
> - add SPDX-License-Identifier and cleanup copyright notice
Thank you for using the SPDX ids in this patch series.
Acked-by: Philippe Ombredanne <pombredanne-od1rfyK75/E@public.gmane.org>
--
Cordially
Philippe Ombredanne
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^ permalink raw reply
* Re: [PATCH 03/20] ARM: dts: aspeed-g4: Correct VUART IRQ number
From: Arnd Bergmann @ 2017-12-11 11:38 UTC (permalink / raw)
To: Joel Stanley
Cc: Rob Herring, Mark Rutland, Andrew Jeffery, Patrick Venture,
Xo Wang, Lei YU, Cédric Le Goater, Benjamin Herrenschmidt,
Jeremy Kerr, DTML, Linux ARM, Linux Kernel Mailing List,
linux-aspeed
In-Reply-To: <CACPK8XfSxxVFT7y6M17LZhVO0GHuL1L=6KET75Qojg8rpgD9iw@mail.gmail.com>
On Mon, Dec 11, 2017 at 11:44 AM, Joel Stanley <joel@jms.id.au> wrote:
> On Mon, Dec 11, 2017 at 6:28 PM, Arnd Bergmann <arnd@arndb.de> wrote:
>> On Mon, Dec 11, 2017 at 6:06 AM, Joel Stanley <joel@jms.id.au> wrote:
>>> This should have always been 8.
>>>
>>> Signed-off-by: Joel Stanley <joel@jms.id.au>
>>
>> As this is a bugfix, should we backport it to stable kernels? When you
>> fix a bug,
>> I generally recommend including a 'Fixes' tag with the commit ID of the patch
>> that introduced the problem, and either a 'Cc: stable@vger.kernel.org' tag
>> if you want it backported, or an explanation in the changelog why it should
>> not get backported. This really helps Greg and the other stable maintainers
>> trying to make a decision what to backport and what not.
>
> We could do this, and I generally follow the practice of adding Fixes
> tags. I hadn't because without an upstream clock driver, the Aspeed
> port is not usable by anyone without making modifications. We're
> really depending on getting that code merged.
>
> I will send it as a fix to 4.15. Do you mind taking individual patches
> for the arm dt tree, or would you prefer a pull request?
For bugfixes, we don't distinguish between DT and other fixes. If it's
a single patch, a pull request works just as well as a emailed patch,
your choice.
Arnd
^ permalink raw reply
* [PATCH v2] ARM: dts: ls1021a: add support for Moxa UC-8410A open platform
From: SZ Lin @ 2017-12-11 11:51 UTC (permalink / raw)
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, SZ Lin, Jimmy Chen,
Harry YJ Jhou, Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Add support for Moxa UC-8410A open platform
The UC-8410A computing platform is designed
for embedded communication-centric industrial applications
The features of UC-8410A are:
* QSPI flash
* SD slot
* 3x LAN
* 8x RS-232/422/485 ports, software-selectable
* Mini PCIe form factor with PCIe/USB signal
* 2x USB host
* TPM
* Watchdog
* RTC
* User LEDs
* Beeper
* Push button
Signed-off-by: Jimmy Chen <jimmy.chen-D4fb9hXD9d4@public.gmane.org>
Signed-off-by: Harry YJ Jhou <harryyj.jhou-D4fb9hXD9d4@public.gmane.org>
Signed-off-by: SZ Lin <sz.lin-D4fb9hXD9d4@public.gmane.org>
--
Changes from v1:
- Add newline between nodes
- Add push button node
- Insert newline between property list and child node
- Include file of "include/dt-bindings/gpio/gpio.h"
- Include file of "include/dt-bindings/input/input.h"
- Use polartiy defines for gpios to make it more readable
- Put 'status' at the end of property list
- Change GPIO pin number in cel_pwr and cel_reset
- Sort the labeled node alphabetically
- Drop container node of regulator and put fixed regulator directly
under root
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 241 ++++++++++++++++++++++++++++
2 files changed, 242 insertions(+)
create mode 100644 arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d0381e9caf21..62ce9b27ad30 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -520,6 +520,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7s-colibri-eval-v3.dtb \
imx7s-warp.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
+ ls1021a-moxa-uc-8410a.dtb \
ls1021a-qds.dtb \
ls1021a-twr.dtb
dtb-$(CONFIG_SOC_VF610) += \
diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
new file mode 100644
index 000000000000..bc73b5187990
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2017 Moxa Inc. - https://www.moxa.com/
+ *
+ * Author: Harry YJ Jhou (周亞諄) <harryyj.jhou-D4fb9hXD9d4@public.gmane.org>
+ * Jimmy Chen (陳永達) <jimmy.chen-D4fb9hXD9d4@public.gmane.org>
+ * SZ Lin (林上智) <sz.lin-D4fb9hXD9d4@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "ls1021a.dtsi"
+
+/ {
+ model = "Moxa UC-8410A";
+
+ aliases {
+ enet0_rgmii_phy = &rgmii_phy0;
+ enet1_rgmii_phy = &rgmii_phy1;
+ enet2_rgmii_phy = &rgmii_phy2;
+ };
+
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ cel_pwr {
+ label = "UC8410A:CEL-PWR";
+ gpios = <&gpio3 27 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ cel_reset {
+ label = "UC8410A:CEL-RESET";
+ gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ str_led {
+ label = "UC8410A:RED:PROG";
+ gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+
+ sw_ready {
+ label = "UC8410A:GREEN:SWRDY";
+ gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ beeper {
+ label = "UC8410A:BEEP";
+ gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ prog_led0 {
+ label = "UC8410A:GREEN:PROG2";
+ gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ prog_led1 {
+ label = "UC8410A:GREEN:PROG1";
+ gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ prog_led2 {
+ label = "UC8410A:GREEN:PROG0";
+ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ wifi_signal0 {
+ label = "UC8410A:GREEN:CEL2";
+ gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ wifi_signal1 {
+ label = "UC8410A:GREEN:CEL1";
+ gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ wifi_signal2 {
+ label = "UC8410A:GREEN:CEL0";
+ gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ cpu_diag_red {
+ label = "UC8410A:RED:DIA";
+ gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ cpu_diag_green {
+ label = "UC8410A:GREEN:DIA";
+ gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ cpu_diag_yellow {
+ label = "UC8410A:YELLOW:DIA";
+ gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pushbtn-key {
+ label = "push button key";
+ gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_MISC>;
+ default-state = "on";
+ };
+ };
+};
+
+&enet0 {
+ phy-handle = <&rgmii_phy0>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
+&enet1 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
+&enet2 {
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ rtc {
+ compatible = "dallas,ds1374";
+ reg = <0x68>;
+ };
+
+ tpm {
+ compatible = "infineon,slb9635tt";
+ reg = <0x20>;
+ };
+};
+
+&lpuart0 {
+ status = "okay";
+};
+
+&mdio0 {
+ rgmii_phy0: ethernet-phy@0 {
+ compatible = "marvell,88e1118";
+ reg = <0x0>;
+ marvell,reg-init =
+ <3 0x11 0 0x4415>, /* Reg 3,17 */
+ <3 0x10 0 0x77>; /* Reg 3,16 */
+ };
+
+ rgmii_phy1: ethernet-phy@1 {
+ compatible = "marvell,88e1118";
+ reg = <0x1>;
+ marvell,reg-init =
+ <3 0x11 0 0x4415>, /* Reg 3,17 */
+ <3 0x10 0 0x77>; /* Reg 3,16 */
+ };
+
+ rgmii_phy2: ethernet-phy@2 {
+ compatible = "marvell,88e1118";
+ reg = <0x2>;
+ marvell,reg-init =
+ <3 0x11 0 0x4415>, /* Reg 3,17 */
+ <3 0x10 0 0x77>; /* Reg 3,16 */
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ fsl,spi-num-chipselects = <2>;
+ fsl,spi-flash-chipselects = <0>;
+ fsl,qspi-has-second-chip;
+ status = "okay";
+
+ flash: flash@0 {
+ compatible = "spansion,s25fl064l", "spansion,s25fl164k";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+
+ partitions@0 {
+ label = "U-Boot";
+ reg = <0x0 0x180000>;
+ };
+
+ partitions@1 {
+ label = "U-Boot Env";
+ reg = <0x180000 0x680000>;
+ };
+ };
+};
+
+&sata {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
--
2.15.1
--
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^ permalink raw reply related
* Re: [PATCH net-next v5 2/2] net: ethernet: socionext: add AVE ethernet driver
From: Kunihiko Hayashi @ 2017-12-11 12:04 UTC (permalink / raw)
To: Philippe Ombredanne
Cc: David S. Miller, netdev-u79uwXL29TY76Z2rM5mHXA, Andrew Lunn,
Florian Fainelli, Rob Herring, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Masahiro Yamada,
Masami Hiramatsu, Jassi Brar
In-Reply-To: <CAOFm3uELNTgenR91-QGL1QQ08zA0N0rQbH4hzCzFKtRw6TckLw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Mon, 11 Dec 2017 10:19:15 +0100 Phlippe Ombredanne <pombredanne-od1rfyK75/E@public.gmane.org> wrote:
> Dear Kunihiko-san,
>
> On Mon, Dec 11, 2017 at 8:57 AM, Kunihiko Hayashi
> <hayashi.kunihiko-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org> wrote:
> > The UniPhier platform from Socionext provides the AVE ethernet
> > controller that includes MAC and MDIO bus supporting RGMII/RMII
> > modes. The controller is named AVE.
> >
> > Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
> > Signed-off-by: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> > Reviewed-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
> [...]
> > --- /dev/null
> > +++ b/drivers/net/ethernet/socionext/Makefile
> > @@ -0,0 +1,5 @@
> > +# SPDX-License-Identifier: GPL-2.0
>
> You are correctly using SPDX ids here....
>
> > +obj-$(CONFIG_SNI_AVE) += sni_ave.o
> > diff --git a/drivers/net/ethernet/socionext/sni_ave.c b/drivers/net/ethernet/socionext/sni_ave.c
> > new file mode 100644
> > index 0000000..7b293c2
> > --- /dev/null
> > +++ b/drivers/net/ethernet/socionext/sni_ave.c
> > @@ -0,0 +1,1744 @@
> > +/**
> > + * sni_ave.c - Socionext UniPhier AVE ethernet driver
> > + *
> > + * Copyright 2014 Panasonic Corporation
> > + * Copyright 2015-2017 Socionext Inc.
> > + *
> > + * This program is free software: you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 of
> > + * the License as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
>
> ... then I guess you could also use them here, replacing at least 7
> lines of boilerplate by a single id line?
>
> > +// SDPX-License-Identifier: GPL-2.0
Thank you for your kindly comment.
It seems there are few ethernet drivers applying SPDX-License-Identifier
to C source, then it has been difficult for me to decide whether to replace
boilerplate.
If it's no problem to apply SPDX to sources of ethernet drivers,
I'll replace it with the single line.
> And if you go C++ style all the way, this could be even more compact:
>
> > +// SDPX-License-Identifier: GPL-2.0
> > +// sni_ave.c - Socionext UniPhier AVE ethernet driver
> > +// Copyright 2014 Panasonic Corporation
> > +// Copyright 2015-2017 Socionext Inc.
It's much simpler.
If it's reasonable to apply this style here, I can replace it, too.
Thank you,
---
Best Regards,
Kunihiko Hayashi
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^ permalink raw reply
* [PATCH net-next v5 0/4] net: fec: fix refclk enable for SMSC LAN8710/20
From: Richard Leitner @ 2017-12-11 12:16 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
fugang.duan-3arQi8VN3Tc, andrew-g2DYL2Zd6BY,
f.fainelli-Re5JQEeQqe8AvxtiuMwx3w,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w
Cc: davem-fT/PcQaiUtIeIZ0/mPfg9Q,
geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ,
sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8,
baruch-NswTu9S1W3P6gbPvEgmw2w, david.wu-TNX95d0MmH7DzftRWevZcw,
lukma-ynQEQJNshbs, netdev-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
richard.leitner-WcANXNA0UjBBDgjK7y7TUQ
From: Richard Leitner <richard.leitner-WcANXNA0UjBBDgjK7y7TUQ@public.gmane.org>
This patch series fixes the use of the SMSC LAN8710/20 with a Freescale ETH
when the refclk is generated by the FSL.
This patchset depends on the "phylib: Add device reset GPIO support" patch
submitted by Geert Uytterhoeven/Sergei Shtylyov, which was merged to
net-next as commit bafbdd527d56 ("phylib: Add device reset GPIO support").
Changes v5:
- fix reset delay calculation (max_t instead of min_t)
Changes v4:
- simplify dts parsing
- simplify reset delay evaluation and execution
- fec: ensure to only reset once during fec_enet_open()
- remove dependency notes from commit message
- add reviews and acks
Changes v3:
- use phylib to hard-reset the PHY
- implement reset delays in phylib
- add new phylib API & flag (PHY_RST_AFTER_CLK_EN) to determine if
a PHY is affected
Changes v2:
- simplify and fix fec_reset_phy function to support multiple calls
- include: linux: phy: harmonize phy_id{,_mask} type
- reset the phy instead of not turning the clock on and off
(which would have caused a power consumption regression)
Richard Leitner (4):
phylib: Add device reset delay support
phylib: add reset after clk enable support
net: phy: smsc: LAN8710/20: add PHY_RST_AFTER_CLK_EN flag
net: fec: add phy_reset_after_clk_enable() support
Documentation/devicetree/bindings/net/phy.txt | 10 ++++++++++
drivers/net/ethernet/freescale/fec_main.c | 20 ++++++++++++++++++++
drivers/net/phy/mdio_device.c | 13 +++++++++++--
drivers/net/phy/phy_device.c | 24 ++++++++++++++++++++++++
drivers/net/phy/smsc.c | 2 +-
drivers/of/of_mdio.c | 4 ++++
include/linux/mdio.h | 2 ++
include/linux/phy.h | 2 ++
8 files changed, 74 insertions(+), 3 deletions(-)
--
2.11.0
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^ permalink raw reply
* [PATCH net-next v5 1/4] phylib: Add device reset delay support
From: Richard Leitner @ 2017-12-11 12:16 UTC (permalink / raw)
To: robh+dt, mark.rutland, fugang.duan, andrew, f.fainelli,
frowand.list
Cc: davem, geert+renesas, sergei.shtylyov, baruch, david.wu, lukma,
netdev, devicetree, linux-kernel, richard.leitner
In-Reply-To: <20171211121700.10200-1-dev@g0hl1n.net>
From: Richard Leitner <richard.leitner@skidata.com>
Some PHYs need a minimum time after the reset gpio was asserted and/or
deasserted. To ensure we meet these timing requirements add two new
optional devicetree parameters for the phy: reset-delay-us and
reset-post-delay-us.
Signed-off-by: Richard Leitner <richard.leitner@skidata.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Documentation/devicetree/bindings/net/phy.txt | 10 ++++++++++
drivers/net/phy/mdio_device.c | 13 +++++++++++--
drivers/of/of_mdio.c | 4 ++++
include/linux/mdio.h | 2 ++
4 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt
index c05479f5ac7c..72860ce7f610 100644
--- a/Documentation/devicetree/bindings/net/phy.txt
+++ b/Documentation/devicetree/bindings/net/phy.txt
@@ -55,6 +55,12 @@ Optional Properties:
- reset-gpios: The GPIO phandle and specifier for the PHY reset signal.
+- reset-delay-us: Delay after the reset was asserted in microseconds.
+ If this property is missing the delay will be skipped.
+
+- reset-post-delay-us: Delay after the reset was deasserted in microseconds.
+ If this property is missing the delay will be skipped.
+
Example:
ethernet-phy@0 {
@@ -62,4 +68,8 @@ ethernet-phy@0 {
interrupt-parent = <&PIC>;
interrupts = <35 IRQ_TYPE_EDGE_RISING>;
reg = <0>;
+
+ reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <1000>;
+ reset-post-delay-us = <2000>;
};
diff --git a/drivers/net/phy/mdio_device.c b/drivers/net/phy/mdio_device.c
index 75d97dd9fb28..843c1dde93e4 100644
--- a/drivers/net/phy/mdio_device.c
+++ b/drivers/net/phy/mdio_device.c
@@ -24,6 +24,7 @@
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/unistd.h>
+#include <linux/delay.h>
void mdio_device_free(struct mdio_device *mdiodev)
{
@@ -118,8 +119,16 @@ EXPORT_SYMBOL(mdio_device_remove);
void mdio_device_reset(struct mdio_device *mdiodev, int value)
{
- if (mdiodev->reset)
- gpiod_set_value(mdiodev->reset, value);
+ unsigned int d;
+
+ if (!mdiodev->reset)
+ return;
+
+ gpiod_set_value(mdiodev->reset, value);
+
+ d = value ? mdiodev->reset_delay : mdiodev->reset_post_delay;
+ if (d)
+ usleep_range(d, d + max_t(unsigned int, d / 10, 100));
}
EXPORT_SYMBOL(mdio_device_reset);
diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
index 98258583abb0..7c8767176315 100644
--- a/drivers/of/of_mdio.c
+++ b/drivers/of/of_mdio.c
@@ -77,6 +77,10 @@ static int of_mdiobus_register_phy(struct mii_bus *mdio,
if (of_property_read_bool(child, "broken-turn-around"))
mdio->phy_ignore_ta_mask |= 1 << addr;
+ of_property_read_u32(child, "reset-delay-us", &phy->mdio.reset_delay);
+ of_property_read_u32(child, "reset-post-delay-us",
+ &phy->mdio.reset_post_delay);
+
/* Associate the OF node with the device structure so it
* can be looked up later */
of_node_get(child);
diff --git a/include/linux/mdio.h b/include/linux/mdio.h
index 92d4e55ffe67..e37c21d8eb19 100644
--- a/include/linux/mdio.h
+++ b/include/linux/mdio.h
@@ -41,6 +41,8 @@ struct mdio_device {
int addr;
int flags;
struct gpio_desc *reset;
+ unsigned int reset_delay;
+ unsigned int reset_post_delay;
};
#define to_mdio_device(d) container_of(d, struct mdio_device, dev)
--
2.11.0
^ permalink raw reply related
* [PATCH net-next v5 2/4] phylib: add reset after clk enable support
From: Richard Leitner @ 2017-12-11 12:16 UTC (permalink / raw)
To: robh+dt, mark.rutland, fugang.duan, andrew, f.fainelli,
frowand.list
Cc: davem, geert+renesas, sergei.shtylyov, baruch, david.wu, lukma,
netdev, devicetree, linux-kernel, richard.leitner
In-Reply-To: <20171211121700.10200-1-dev@g0hl1n.net>
From: Richard Leitner <richard.leitner@skidata.com>
Some PHYs need the refclk to be a continuous clock. Therefore they don't
allow turning it off and on again during operation. Nonetheless such a
clock switching is performed by some ETH drivers (namely FEC [1]) for
power saving reasons. An example for an affected PHY is the
SMSC/Microchip LAN8720 in "REF_CLK In Mode".
In order to provide a uniform method to overcome this problem this patch
adds a new phy_driver flag (PHY_RST_AFTER_CLK_EN) and corresponding
function phy_reset_after_clk_enable() to the phylib. These should be
used to trigger reset of the PHY after the refclk is switched on again.
[1] commit e8fcfcd5684a ("net: fec: optimize the clock management to save power")
Signed-off-by: Richard Leitner <richard.leitner@skidata.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/net/phy/phy_device.c | 24 ++++++++++++++++++++++++
include/linux/phy.h | 2 ++
2 files changed, 26 insertions(+)
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 1de5e242b8b4..462c17ed87b8 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -1218,6 +1218,30 @@ int phy_loopback(struct phy_device *phydev, bool enable)
}
EXPORT_SYMBOL(phy_loopback);
+/**
+ * phy_reset_after_clk_enable - perform a PHY reset if needed
+ * @phydev: target phy_device struct
+ *
+ * Description: Some PHYs are known to need a reset after their refclk was
+ * enabled. This function evaluates the flags and perform the reset if it's
+ * needed. Returns < 0 on error, 0 if the phy wasn't reset and 1 if the phy
+ * was reset.
+ */
+int phy_reset_after_clk_enable(struct phy_device *phydev)
+{
+ if (!phydev || !phydev->drv)
+ return -ENODEV;
+
+ if (phydev->drv->flags & PHY_RST_AFTER_CLK_EN) {
+ phy_device_reset(phydev, 1);
+ phy_device_reset(phydev, 0);
+ return 1;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_reset_after_clk_enable);
+
/* Generic PHY support and helper functions */
/**
diff --git a/include/linux/phy.h b/include/linux/phy.h
index d3037e2ffbc4..c4b4715caa21 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -59,6 +59,7 @@
#define PHY_HAS_INTERRUPT 0x00000001
#define PHY_IS_INTERNAL 0x00000002
+#define PHY_RST_AFTER_CLK_EN 0x00000004
#define MDIO_DEVICE_IS_PHY 0x80000000
/* Interface Mode definitions */
@@ -853,6 +854,7 @@ int phy_aneg_done(struct phy_device *phydev);
int phy_stop_interrupts(struct phy_device *phydev);
int phy_restart_aneg(struct phy_device *phydev);
+int phy_reset_after_clk_enable(struct phy_device *phydev);
static inline void phy_device_reset(struct phy_device *phydev, int value)
{
--
2.11.0
^ permalink raw reply related
* [PATCH net-next v5 3/4] net: phy: smsc: LAN8710/20: add PHY_RST_AFTER_CLK_EN flag
From: Richard Leitner @ 2017-12-11 12:16 UTC (permalink / raw)
To: robh+dt, mark.rutland, fugang.duan, andrew, f.fainelli,
frowand.list
Cc: davem, geert+renesas, sergei.shtylyov, baruch, david.wu, lukma,
netdev, devicetree, linux-kernel, richard.leitner
In-Reply-To: <20171211121700.10200-1-dev@g0hl1n.net>
From: Richard Leitner <richard.leitner@skidata.com>
The Microchip/SMSC LAN8710/LAN8720 PHYs need (according to their
datasheet [1]) a continuous REF_CLK when configured to "REF_CLK In Mode".
Therefore set the PHY_RST_AFTER_CLK_EN flag for those PHYs to let the
ETH driver reset them after the REF_CLK is enabled.
[1] http://ww1.microchip.com/downloads/en/DeviceDoc/00002165B.pdf
Signed-off-by: Richard Leitner <richard.leitner@skidata.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/net/phy/smsc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index a1961ba87e2b..be399d645224 100644
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -312,7 +312,7 @@ static struct phy_driver smsc_phy_driver[] = {
.name = "SMSC LAN8710/LAN8720",
.features = PHY_BASIC_FEATURES,
- .flags = PHY_HAS_INTERRUPT,
+ .flags = PHY_HAS_INTERRUPT | PHY_RST_AFTER_CLK_EN,
.probe = smsc_phy_probe,
--
2.11.0
^ permalink raw reply related
* [PATCH net-next v5 4/4] net: fec: add phy_reset_after_clk_enable() support
From: Richard Leitner @ 2017-12-11 12:17 UTC (permalink / raw)
To: robh+dt, mark.rutland, fugang.duan, andrew, f.fainelli,
frowand.list
Cc: davem, geert+renesas, sergei.shtylyov, baruch, david.wu, lukma,
netdev, devicetree, linux-kernel, richard.leitner
In-Reply-To: <20171211121700.10200-1-dev@g0hl1n.net>
From: Richard Leitner <richard.leitner@skidata.com>
Some PHYs (for example the SMSC LAN8710/LAN8720) doesn't allow turning
the refclk on and off again during operation (according to their
datasheet). Nonetheless exactly this behaviour was introduced for power
saving reasons by commit e8fcfcd5684a ("net: fec: optimize the clock management to save power").
Therefore add support for the phy_reset_after_clk_enable function from
phylib to mitigate this issue.
Generally speaking this issue is only relevant if the ref clk for the
PHY is generated by the SoC and therefore the PHY is configured to
"REF_CLK In Mode". In our specific case (PCB) this problem does occur at
about every 10th to 50th POR of an LAN8710 connected to an i.MX6SOLO
SoC. The typical symptom of this problem is a "swinging" ethernet link.
Similar issues were reported by users of the NXP forum:
https://community.nxp.com/thread/389902
https://community.nxp.com/message/309354
With this patch applied the issue didn't occur for at least a few
hundret PORs of our board.
Fixes: e8fcfcd5684a ("net: fec: optimize the clock management to save power")
Signed-off-by: Richard Leitner <richard.leitner@skidata.com>
---
drivers/net/ethernet/freescale/fec_main.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
index 610573855213..2d1b06579c1a 100644
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -1862,6 +1862,8 @@ static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
ret = clk_prepare_enable(fep->clk_ref);
if (ret)
goto failed_clk_ref;
+
+ phy_reset_after_clk_enable(ndev->phydev);
} else {
clk_disable_unprepare(fep->clk_ahb);
clk_disable_unprepare(fep->clk_enet_out);
@@ -2834,6 +2836,7 @@ fec_enet_open(struct net_device *ndev)
{
struct fec_enet_private *fep = netdev_priv(ndev);
int ret;
+ bool reset_again;
ret = pm_runtime_get_sync(&fep->pdev->dev);
if (ret < 0)
@@ -2844,6 +2847,17 @@ fec_enet_open(struct net_device *ndev)
if (ret)
goto clk_enable;
+ /* During the first fec_enet_open call the PHY isn't probed at this
+ * point. Therefore the phy_reset_after_clk_enable() call within
+ * fec_enet_clk_enable() fails. As we need this reset in order to be
+ * sure the PHY is working correctly we check if we need to reset again
+ * later when the PHY is probed
+ */
+ if (ndev->phydev && ndev->phydev->drv)
+ reset_again = false;
+ else
+ reset_again = true;
+
/* I should reset the ring buffers here, but I don't yet know
* a simple way to do that.
*/
@@ -2860,6 +2874,12 @@ fec_enet_open(struct net_device *ndev)
if (ret)
goto err_enet_mii_probe;
+ /* Call phy_reset_after_clk_enable() again if it failed during
+ * phy_reset_after_clk_enable() before because the PHY wasn't probed.
+ */
+ if (reset_again)
+ phy_reset_after_clk_enable(ndev->phydev);
+
if (fep->quirks & FEC_QUIRK_ERR006687)
imx6q_cpuidle_fec_irqs_used();
--
2.11.0
^ permalink raw reply related
* Re: [PATCH v4 11/12] cpufreq: Add module to register cpufreq on Krait CPUs
From: Sricharan R @ 2017-12-11 13:22 UTC (permalink / raw)
To: Viresh Kumar
Cc: devicetree, linux-pm, linux-arm-msm, mturquette, sboyd,
linux-kernel, linux-arm-kernel
In-Reply-To: <20171211083905.GF25177@vireshk-i7>
Hi Viresh,
On 12/11/2017 2:09 PM, Viresh Kumar wrote:
> On 08-12-17, 15:12, Sricharan R wrote:
>> From: Stephen Boyd <sboyd@codeaurora.org>
>>
>> Register a cpufreq-generic device whenever we detect that a
>> "qcom,krait" compatible CPU is present in DT.
>>
>> Cc: <devicetree@vger.kernel.org>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>> ---
>> .../devicetree/bindings/arm/msm/qcom,pvs.txt | 38 ++++
>> drivers/cpufreq/Kconfig.arm | 9 +
>> drivers/cpufreq/Makefile | 1 +
>> drivers/cpufreq/qcom-cpufreq.c | 204 +++++++++++++++++++++
>> 4 files changed, 252 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,pvs.txt
>> create mode 100644 drivers/cpufreq/qcom-cpufreq.c
>
> This must be done differently as we have enhanced OPP core to support such
> hardware. Look at: dev_pm_opp_set_prop_name() and the binding around it
> (opp-microvolt-<name>). Talk to Stephen, he was part of all those discussions.
>
Thanks. Using opp-microvolt-<name> and setting the right name
extension(dev_pm_opp_set_prop_name) after reading the version
from efuse, makes it to work with proper opp-v2 bindings.
Will repost with the updates. Also with opp-v2, just not having
opp-shared property is enough to scale the cpu independently.
As you have Nacked the other patch (correctly), will drop that
patch to reintroduce the platform data. Testing this on ipq8064.
Will check with Stephen once to make sure changes hold
good for rest of the krait cores as well.
Regards,
Sricharan
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^ permalink raw reply
* Re: [PATCH v4 12/12] cpufreq: dt: Reintroduce independent_clocks platform data
From: Sricharan R @ 2017-12-11 13:24 UTC (permalink / raw)
To: Viresh Kumar
Cc: mturquette, sboyd, devicetree, linux-pm, linux-arm-msm,
linux-kernel, linux-arm-kernel
In-Reply-To: <20171211083328.GE25177@vireshk-i7>
Hi Viresh,
On 12/11/2017 2:03 PM, Viresh Kumar wrote:
> On 08-12-17, 15:12, Sricharan R wrote:
>> The Platform data was removed earlier by,
>> 'commit eb96924acddc ("cpufreq: dt: Kill platform-data")'
>> since there were no users at that time.
>> Now this is required when the each of the cpu clocks
>> can be scaled independently, which is the case
>> for krait cores. So reintroduce it.
>>
>> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
>> ---
>> drivers/cpufreq/cpufreq-dt.c | 7 ++++++-
>> drivers/cpufreq/cpufreq-dt.h | 6 ++++++
>> 2 files changed, 12 insertions(+), 1 deletion(-)
>
> Nack. This information should come from the OPP layer (Hint:
> dev_pm_opp_of_get_sharing_cpus()).
>
Thanks. Understand. As replied on the other patch, after using
dev_pm_opp_set_prop_name and opp-v2 bindings, this patch is no more
required.
Regards,
Sricharan
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^ permalink raw reply
* Re: [PATCH net-next v5 2/2] net: ethernet: socionext: add AVE ethernet driver
From: Masami Hiramatsu @ 2017-12-11 13:34 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: Philippe Ombredanne, David S. Miller,
netdev-u79uwXL29TY76Z2rM5mHXA, Andrew Lunn, Florian Fainelli,
Rob Herring, Mark Rutland, linux-arm-kernel,
Linux kernel mailing list, devicetree-u79uwXL29TY76Z2rM5mHXA,
Masahiro Yamada, Jassi Brar
In-Reply-To: <20171211210455.170A.4A936039-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
Hello,
2017-12-11 21:04 GMT+09:00 Kunihiko Hayashi <hayashi.kunihiko-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>:
> On Mon, 11 Dec 2017 10:19:15 +0100 Phlippe Ombredanne <pombredanne-od1rfyK75/E@public.gmane.org> wrote:
>
>> Dear Kunihiko-san,
>>
>> On Mon, Dec 11, 2017 at 8:57 AM, Kunihiko Hayashi
>> <hayashi.kunihiko-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org> wrote:
>> > The UniPhier platform from Socionext provides the AVE ethernet
>> > controller that includes MAC and MDIO bus supporting RGMII/RMII
>> > modes. The controller is named AVE.
>> >
>> > Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
>> > Signed-off-by: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>> > Reviewed-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
>> [...]
>> > --- /dev/null
>> > +++ b/drivers/net/ethernet/socionext/Makefile
>> > @@ -0,0 +1,5 @@
>> > +# SPDX-License-Identifier: GPL-2.0
>>
>> You are correctly using SPDX ids here....
>>
>> > +obj-$(CONFIG_SNI_AVE) += sni_ave.o
>> > diff --git a/drivers/net/ethernet/socionext/sni_ave.c b/drivers/net/ethernet/socionext/sni_ave.c
>> > new file mode 100644
>> > index 0000000..7b293c2
>> > --- /dev/null
>> > +++ b/drivers/net/ethernet/socionext/sni_ave.c
>> > @@ -0,0 +1,1744 @@
>> > +/**
>> > + * sni_ave.c - Socionext UniPhier AVE ethernet driver
>> > + *
>> > + * Copyright 2014 Panasonic Corporation
>> > + * Copyright 2015-2017 Socionext Inc.
>> > + *
>> > + * This program is free software: you can redistribute it and/or modify
>> > + * it under the terms of the GNU General Public License version 2 of
>> > + * the License as published by the Free Software Foundation.
>> > + *
>> > + * This program is distributed in the hope that it will be useful,
>> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> > + * GNU General Public License for more details.
>> > + */
>>
>> ... then I guess you could also use them here, replacing at least 7
>> lines of boilerplate by a single id line?
>>
>> > +// SDPX-License-Identifier: GPL-2.0
>
> Thank you for your kindly comment.
>
> It seems there are few ethernet drivers applying SPDX-License-Identifier
> to C source, then it has been difficult for me to decide whether to replace
> boilerplate.
>
> If it's no problem to apply SPDX to sources of ethernet drivers,
> I'll replace it with the single line.
>
>> And if you go C++ style all the way, this could be even more compact:
>>
>> > +// SDPX-License-Identifier: GPL-2.0
>> > +// sni_ave.c - Socionext UniPhier AVE ethernet driver
>> > +// Copyright 2014 Panasonic Corporation
>> > +// Copyright 2015-2017 Socionext Inc.
>
> It's much simpler.
> If it's reasonable to apply this style here, I can replace it, too.
IMHO, even if we use SPDX license identifier, I recommend to use
C-style comments as many other files do, since it is C code.
If SPDX identifier requires C++ style, that is SPDX parser's issue
and should be fixed to get it from C-style comment.
https://spdx.org/sites/cpstandard/files/pages/files/using_spdx_license_list_short_identifiers.pdf
Anyway, SPDX.org itself shows C-style (short header) example. See page 6.
Thank you,
>
> Thank you,
>
> ---
> Best Regards,
> Kunihiko Hayashi
>
>
--
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^ permalink raw reply
* Re: [PATCH net-next v5 1/4] phylib: Add device reset delay support
From: Andrew Lunn @ 2017-12-11 13:40 UTC (permalink / raw)
To: Richard Leitner
Cc: robh+dt, mark.rutland, fugang.duan, f.fainelli, frowand.list,
davem, geert+renesas, sergei.shtylyov, baruch, david.wu, lukma,
netdev, devicetree, linux-kernel, richard.leitner
In-Reply-To: <20171211121700.10200-2-dev@g0hl1n.net>
On Mon, Dec 11, 2017 at 01:16:57PM +0100, Richard Leitner wrote:
> From: Richard Leitner <richard.leitner@skidata.com>
>
> Some PHYs need a minimum time after the reset gpio was asserted and/or
> deasserted. To ensure we meet these timing requirements add two new
> optional devicetree parameters for the phy: reset-delay-us and
> reset-post-delay-us.
>
> Signed-off-by: Richard Leitner <richard.leitner@skidata.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* Re: [PATCH 1/6] ARM: stm32: prepare stm32 family to welcome armv7 architecture
From: Arnd Bergmann @ 2017-12-11 13:40 UTC (permalink / raw)
To: Linus Walleij
Cc: Ludovic Barre, Russell King, Rob Herring, Maxime Coquelin,
Alexandre Torgue, Linux ARM,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
In-Reply-To: <CACRpkdaKZk5N9F=_nYSzKWyXgW4xQ9Ltft7-UNM+a-nOpqq2xg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Mon, Dec 11, 2017 at 11:25 AM, Linus Walleij
<linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> On Fri, Dec 8, 2017 at 3:11 PM, Ludovic Barre <ludovic.Barre-qxv4g6HH51o@public.gmane.org> wrote:
>
>> From: Ludovic Barre <ludovic.barre-qxv4g6HH51o@public.gmane.org>
>>
>> This patch prepares the STM32 machine for the integration of Cortex-A
>> based microprocessor (MPU), on top of the existing Cortex-M
>> microcontroller family (MCU). Since both MCUs and MPUs are sharing
>> common hardware blocks we can keep using ARCH_STM32 flag for most of
>> them. If a hardware block is specific to one family we can use either
>> ARCH_STM32_MCU or ARCH_STM32_MPU flag.
>>
>> Signed-off-by: Ludovic Barre <ludovic.barre-qxv4g6HH51o@public.gmane.org>
To what degree do we need to treat them as separate families
at all then? I wonder if the MCU/MPU distinction is always that
clear along the Cortex-M/Cortex-A separation, especially if
we ever get to a chip that has both types of cores. What
exactly would we miss if we do away with the ARCH_STM32_MCU
symbol here?
> So yesterdays application processors are todays MCU processors.
>
> I said this on a lecture for control systems a while back and
> stated it as a reason I think RTOSes are not really seeing a bright
> future compared to Linux.
>
> It happened quicker than I thought though, interesting.
I think there is still lots of room for smaller RTOS in the long run,
but it's likely that the 'MPU + external DRAM' design point will
shift further to Linux, as there isn't really a benefit in squeezing
in anything smaller when the minimum is 32MB or 128MB of
RAM, depending on the interface.
For on-chip eDRAM or SRAM based MPUs, that doesn't hold
true, the memory size is what drives the cost here.
Arnd
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^ permalink raw reply
* Re: [RFC] irqchip: add support for LS1021A external interrupt lines
From: Rasmus Villemoes @ 2017-12-11 13:45 UTC (permalink / raw)
To: Alexander Stein
Cc: Marc Zyngier, Thomas Gleixner, Jason Cooper, Rob Herring,
Mark Rutland, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <2475814.YIHTfursNv@ws-stein>
On 2017-12-11 11:02, Alexander Stein wrote:
> Oh, and what is the content of register SCFG_SCFGREVCR?
Good point. On my board it's 0xffffffff, set even before U-boot starts,
and lots board support code in U-boot expects this. I can't immediately
find examples in the linux source code that actually writes to the scfg,
so I don't know if we already have that as an implicit assumption as
well. But it would be kind of nasty to have to make the code read
SCFG_SCFGREVCR and decide the bit pattern to use based on that -
especially since I wouldn't be able to test it.
Who thought such a magic switch could ever be a good idea?
--
Rasmus Villemoes
Software Developer
Prevas A/S
Hedeager 3
DK-8200 Aarhus N
+45 51210274
rasmus.villemoes-rjjw5hvvQKZaa/9Udqfwiw@public.gmane.org
www.prevas.dk
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