* Re: [PATCH 4/4] PM / OPP: Add ti-opp-supply driver
From: Viresh Kumar @ 2017-12-14 4:34 UTC (permalink / raw)
To: Dave Gerlach
Cc: Rob Herring, Rafael J . Wysocki, linux-arm-kernel, linux-omap,
linux-pm, devicetree, Tony Lindgren, Nishanth Menon
In-Reply-To: <20171213203358.20839-5-d-gerlach@ti.com>
On 13-12-17, 14:33, Dave Gerlach wrote:
> Introduce a ti-opp-supply driver that will use new multiple regulator
> support that is part of the OPP core This is needed on TI platforms like
> DRA7/AM57 in order to control both CPU regulator and Adaptive Body Bias
> (ABB) regulator. These regulators must be scaled in sequence during an
> OPP transition depending on whether or not the frequency is being scaled
> up or down.
>
> This driver also implements AVS Class0 for these parts by looking up the
> required values from registers in the SoC and programming adjusted
> optimal voltage values for each OPP.
>
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
> ---
> drivers/opp/Makefile | 1 +
> drivers/opp/ti-opp-supply.c | 428 ++++++++++++++++++++++++++++++++++++++++++++
Why is this added as a separate driver and not part of the same ti-cpufreq.c
file?
> 2 files changed, 429 insertions(+)
> create mode 100644 drivers/opp/ti-opp-supply.c
>
> diff --git a/drivers/opp/Makefile b/drivers/opp/Makefile
> index e70ceb406fe9..6ce6aefacc81 100644
> --- a/drivers/opp/Makefile
> +++ b/drivers/opp/Makefile
> @@ -2,3 +2,4 @@ ccflags-$(CONFIG_DEBUG_DRIVER) := -DDEBUG
> obj-y += core.o cpu.o
> obj-$(CONFIG_OF) += of.o
> obj-$(CONFIG_DEBUG_FS) += debugfs.o
> +obj-$(CONFIG_ARM_TI_CPUFREQ) += ti-opp-supply.o
> diff --git a/drivers/opp/ti-opp-supply.c b/drivers/opp/ti-opp-supply.c
> new file mode 100644
> index 000000000000..73d795c90b79
> --- /dev/null
> +++ b/drivers/opp/ti-opp-supply.c
> @@ -0,0 +1,428 @@
> +/*
> + * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
> + * Nishanth Menon <nm@ti.com>
> + * Dave Gerlach <d-gerlach@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
Please use the new SPDX format for licenses.
> + * TI OPP supply driver that provides override into the regulator control
> + * for generic opp core to handle devices with ABB regulator and/or
> + * SmartReflex Class0.
> + */
> +#include <linux/clk.h>
> +#include <linux/cpufreq.h>
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/notifier.h>
> +#include <linux/of_device.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/slab.h>
> +
> +/**
> + * struct ti_opp_supply_optimum_voltage_table - optimized voltage table
> + * @reference_uv: reference voltage (usually Nominal voltage)
> + * @optimized_uv: Optimized voltage from efuse
> + */
> +struct ti_opp_supply_optimum_voltage_table {
> + unsigned int reference_uv;
> + unsigned int optimized_uv;
> +};
> +
> +/**
> + * struct ti_opp_supply_data - OMAP specific opp supply data
> + * @vdd_table: Optimized voltage mapping table
> + * @num_vdd_table: number of entries in vdd_table
> + * @vdd_absolute_max_voltage_uv: absolute maximum voltage in UV for the supply
> + */
> +struct ti_opp_supply_data {
> + struct ti_opp_supply_optimum_voltage_table *vdd_table;
> + u32 num_vdd_table;
> + u32 vdd_absolute_max_voltage_uv;
> +};
> +
> +static struct ti_opp_supply_data opp_data;
> +
> +/**
> + * struct ti_opp_supply_of_data - device tree match data
> + * @flags: specific type of opp supply
> + * @efuse_voltage_mask: mask required for efuse register representing voltage
> + * @efuse_voltage_uv: Are the efuse entries in micro-volts? if not, assume
> + * milli-volts.
> + */
> +struct ti_opp_supply_of_data {
> +#define OPPDM_EFUSE_CLASS0_OPTIMIZED_VOLTAGE BIT(1)
> +#define OPPDM_HAS_NO_ABB BIT(2)
> + const u8 flags;
> + const u32 efuse_voltage_mask;
> + const bool efuse_voltage_uv;
> +};
> +
> +/**
> + * _store_optimized_voltages() - store optimized voltages
> + * @dev: ti opp supply device for which we need to store info
> + * @data: data specific to the device
> + *
> + * Picks up efuse based optimized voltages for VDD unique per device and
> + * stores it in internal data structure for use during transition requests.
> + *
> + * Return: If successful, 0, else appropriate error value.
> + */
> +static int _store_optimized_voltages(struct device *dev,
> + struct ti_opp_supply_data *data)
> +{
> + void __iomem *base;
> + struct property *prop;
> + struct resource *res;
> + const __be32 *val;
> + int proplen, i;
> + int ret = 0;
> + struct ti_opp_supply_optimum_voltage_table *table;
> + const struct ti_opp_supply_of_data *of_data = dev_get_drvdata(dev);
> +
> + /* pick up Efuse based voltages */
> + res = platform_get_resource(to_platform_device(dev), IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "Unable to get IO resource\n");
> + ret = -ENODEV;
> + goto out_map;
> + }
> +
> + base = ioremap_nocache(res->start, resource_size(res));
> + if (!base) {
> + dev_err(dev, "Unable to map Efuse registers\n");
> + ret = -ENOMEM;
> + goto out_map;
> + }
> +
> + /* Fetch efuse-settings. */
> + prop = of_find_property(dev->of_node, "ti,efuse-settings", NULL);
> + if (!prop) {
> + dev_err(dev, "No 'ti,efuse-settings' property found\n");
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + proplen = prop->length / sizeof(int);
> + data->num_vdd_table = proplen / 2;
> + /* Verify for corrupted OPP entries in dt */
> + if (data->num_vdd_table * 2 * sizeof(int) != prop->length) {
> + dev_err(dev, "Invalid 'ti,efuse-settings'\n");
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + ret = of_property_read_u32(dev->of_node, "ti,absolute-max-voltage-uv",
> + &data->vdd_absolute_max_voltage_uv);
> + if (ret) {
> + dev_err(dev, "ti,absolute-max-voltage-uv is missing\n");
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + table = kzalloc(sizeof(*data->vdd_table) *
> + data->num_vdd_table, GFP_KERNEL);
> + if (!table) {
> + ret = -ENOMEM;
> + goto out;
> + }
> + data->vdd_table = table;
> +
> + val = prop->value;
> + for (i = 0; i < data->num_vdd_table; i++, table++) {
> + u32 efuse_offset;
> + u32 tmp;
> +
> + table->reference_uv = be32_to_cpup(val++);
> + efuse_offset = be32_to_cpup(val++);
> +
> + tmp = readl(base + efuse_offset);
> + tmp &= of_data->efuse_voltage_mask;
> + tmp >>= __ffs(of_data->efuse_voltage_mask);
> +
> + table->optimized_uv = of_data->efuse_voltage_uv ? tmp :
> + tmp * 1000;
> +
> + dev_dbg(dev, "[%d] efuse=0x%08x volt_table=%d vset=%d\n",
> + i, efuse_offset, table->reference_uv,
> + table->optimized_uv);
> +
> + /*
> + * Some older samples might not have optimized efuse
> + * Use reference voltage for those - just add debug message
> + * for them.
> + */
> + if (!table->optimized_uv) {
> + dev_dbg(dev, "[%d] efuse=0x%08x volt_table=%d:vset0\n",
> + i, efuse_offset, table->reference_uv);
> + table->optimized_uv = table->reference_uv;
> + }
> + }
> +out:
> + iounmap(base);
> +out_map:
> + return ret;
> +}
> +
> +/**
> + * _free_optimized_voltages() - free resources for optvoltages
> + * @dev: device for which we need to free info
> + * @data: data specific to the device
> + */
> +static void _free_optimized_voltages(struct device *dev,
> + struct ti_opp_supply_data *data)
> +{
> + kfree(data->vdd_table);
> + data->vdd_table = NULL;
> + data->num_vdd_table = 0;
> +}
> +
> +/**
> + * _get_optimal_vdd_voltage() - Finds optimal voltage for the supply
> + * @dev: device for which we need to find info
> + * @data: data specific to the device
> + * @reference_uv: reference voltage (OPP voltage) for which we need value
> + *
> + * Return: if a match is found, return optimized voltage, else return
> + * reference_uv, also return reference_uv if no optimization is needed.
> + */
> +static int _get_optimal_vdd_voltage(struct device *dev,
> + struct ti_opp_supply_data *data,
> + int reference_uv)
> +{
> + int i;
> + struct ti_opp_supply_optimum_voltage_table *table;
> +
> + if (!data->num_vdd_table)
> + return reference_uv;
> +
> + table = data->vdd_table;
> + if (!table)
> + return -EINVAL;
> +
> + /* Find a exact match - this list is usually very small */
> + for (i = 0; i < data->num_vdd_table; i++, table++)
> + if (table->reference_uv == reference_uv)
> + return table->optimized_uv;
> +
> + /* IF things are screwed up, we'd make a mess on console.. ratelimit */
> + dev_err_ratelimited(dev, "%s: Failed optimized voltage match for %d\n",
> + __func__, reference_uv);
> + return reference_uv;
> +}
> +
> +static int _opp_set_voltage(struct device *dev,
> + struct dev_pm_opp_supply *supply,
> + int new_target_uv, struct regulator *reg,
> + char *reg_name)
> +{
> + int ret;
> + unsigned long vdd_uv, uv_max;
> +
> + if (new_target_uv)
> + vdd_uv = new_target_uv;
> + else
> + vdd_uv = supply->u_volt;
> +
> + /*
> + * If we do have an absolute max voltage specified, then we should
> + * use that voltage instead to allow for cases where the voltage rails
> + * are ganged (example if we set the max for an opp as 1.12v, and
> + * the absolute max is 1.5v, for another rail to get 1.25v, it cannot
> + * be achieved if the regulator is constrainted to max of 1.12v, even
> + * if it can function at 1.25v
> + */
> + if (opp_data.vdd_absolute_max_voltage_uv)
> + uv_max = opp_data.vdd_absolute_max_voltage_uv;
> + else
> + uv_max = supply->u_volt_max;
> +
> + if (vdd_uv > uv_max ||
> + vdd_uv < supply->u_volt_min ||
> + supply->u_volt_min > uv_max) {
> + dev_warn(dev,
> + "Invalid range voltages [Min:%lu target:%lu Max:%lu]\n",
> + supply->u_volt_min, vdd_uv, uv_max);
> + return -EINVAL;
> + }
> +
> + dev_dbg(dev, "%s scaling to %luuV[min %luuV max %luuV]\n", reg_name,
> + vdd_uv, supply->u_volt_min,
> + uv_max);
> +
> + ret = regulator_set_voltage_triplet(reg,
> + supply->u_volt_min,
> + vdd_uv,
> + uv_max);
> + if (ret) {
> + dev_err(dev, "%s failed for %luuV[min %luuV max %luuV]\n",
> + reg_name, vdd_uv, supply->u_volt_min,
> + uv_max);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * ti_opp_supply_set_opp() - do the opp supply transition
> + * @data: information on regulators and new and old opps provided by
> + * opp core to use in transition
> + *
> + * Return: If successful, 0, else appropriate error value.
> + */
> +int ti_opp_supply_set_opp(struct dev_pm_set_opp_data *data)
> +{
> + struct dev_pm_opp_supply *old_supply_vdd = &data->old_opp.supplies[0];
> + struct dev_pm_opp_supply *old_supply_vbb = &data->old_opp.supplies[1];
> + struct dev_pm_opp_supply *new_supply_vdd = &data->new_opp.supplies[0];
> + struct dev_pm_opp_supply *new_supply_vbb = &data->new_opp.supplies[1];
> + struct device *dev = data->dev;
> + unsigned long old_freq = data->old_opp.rate, freq = data->new_opp.rate;
> + struct clk *clk = data->clk;
> + struct regulator *vdd_reg = data->regulators[0];
> + struct regulator *vbb_reg = data->regulators[1];
> + int vdd_uv;
> + int ret;
> +
> + vdd_uv = _get_optimal_vdd_voltage(dev, &opp_data,
> + new_supply_vbb->u_volt);
> +
> + /* Scaling up? Scale voltage before frequency */
> + if (freq > old_freq) {
> + ret = _opp_set_voltage(dev, new_supply_vdd, vdd_uv, vdd_reg,
> + "vdd");
> + if (ret)
> + goto restore_voltage;
> +
> + ret = _opp_set_voltage(dev, new_supply_vbb, 0, vbb_reg, "vbb");
> + if (ret)
> + goto restore_voltage;
> + }
> +
> + /* Change frequency */
> + dev_dbg(dev, "%s: switching OPP: %lu Hz --> %lu Hz\n",
> + __func__, old_freq, freq);
> +
> + ret = clk_set_rate(clk, freq);
> + if (ret) {
> + dev_err(dev, "%s: failed to set clock rate: %d\n", __func__,
> + ret);
> + goto restore_voltage;
> + }
> +
> + /* Scaling down? Scale voltage after frequency */
> + if (freq < old_freq) {
> + ret = _opp_set_voltage(dev, new_supply_vbb, 0, vbb_reg, "vbb");
> + if (ret)
> + goto restore_freq;
> +
> + ret = _opp_set_voltage(dev, new_supply_vdd, vdd_uv, vdd_reg,
> + "vdd");
> + if (ret)
> + goto restore_freq;
> + }
> +
> + return 0;
> +
> +restore_freq:
> + ret = clk_set_rate(clk, old_freq);
> + if (ret)
> + dev_err(dev, "%s: failed to restore old-freq (%lu Hz)\n",
> + __func__, old_freq);
> +restore_voltage:
> + /* This shouldn't harm even if the voltages weren't updated earlier */
> + if (old_supply_vdd->u_volt) {
> + ret = _opp_set_voltage(dev, old_supply_vbb, 0, vbb_reg, "vbb");
> + if (ret)
> + return ret;
> +
> + ret = _opp_set_voltage(dev, old_supply_vdd, 0, vdd_reg,
> + "vdd");
> + if (ret)
> + return ret;
> + }
> +
> + return ret;
> +}
> +
> +static const struct ti_opp_supply_of_data omap_generic_of_data = {
> +};
> +
> +static const struct ti_opp_supply_of_data omap_omap5_of_data = {
> + .flags = OPPDM_EFUSE_CLASS0_OPTIMIZED_VOLTAGE,
> + .efuse_voltage_mask = 0xFFF,
> + .efuse_voltage_uv = false,
> +};
> +
> +static const struct ti_opp_supply_of_data omap_omap5core_of_data = {
> + .flags = OPPDM_EFUSE_CLASS0_OPTIMIZED_VOLTAGE | OPPDM_HAS_NO_ABB,
> + .efuse_voltage_mask = 0xFFF,
> + .efuse_voltage_uv = false,
> +};
> +
> +static const struct of_device_id ti_opp_supply_of_match[] = {
> + {.compatible = "ti,omap-opp-supply", .data = &omap_generic_of_data},
> + {.compatible = "ti,omap5-opp-supply", .data = &omap_omap5_of_data},
> + {.compatible = "ti,omap5-core-opp-supply",
> + .data = &omap_omap5core_of_data},
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, ti_opp_supply_of_match);
> +
> +static int ti_opp_supply_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device *cpu_dev = get_cpu_device(0);
> + const struct of_device_id *match;
> + const struct ti_opp_supply_of_data *of_data;
> + int ret = 0;
> +
> + match = of_match_device(ti_opp_supply_of_match, dev);
> + if (!match) {
> + /* We do not expect this to happen */
> + dev_err(dev, "%s: Unable to match device\n", __func__);
> + return -ENODEV;
> + }
> + if (!match->data) {
> + /* Again, unlikely.. but mistakes do happen */
> + dev_err(dev, "%s: Bad data in match\n", __func__);
> + return -EINVAL;
> + }
> + of_data = match->data;
> +
> + dev_set_drvdata(dev, (void *)of_data);
> +
> + /* If we need optimized voltage */
> + if (of_data->flags & OPPDM_EFUSE_CLASS0_OPTIMIZED_VOLTAGE) {
> + ret = _store_optimized_voltages(dev, &opp_data);
> + if (ret)
> + return ret;
> + }
> +
> + ret = PTR_ERR_OR_ZERO(dev_pm_opp_register_set_opp_helper(cpu_dev,
> + ti_opp_supply_set_opp));
> + if (ret)
> + _free_optimized_voltages(dev, &opp_data);
> +
> + return ret;
> +}
> +
> +static struct platform_driver ti_opp_supply_driver = {
> + .probe = ti_opp_supply_probe,
> + .driver = {
> + .name = "ti_opp_supply",
> + .owner = THIS_MODULE,
> + .of_match_table = of_match_ptr(ti_opp_supply_of_match),
> + },
> +};
> +module_platform_driver(ti_opp_supply_driver);
> +
> +MODULE_DESCRIPTION("Texas Instruments OMAP OPP Supply driver");
> +MODULE_AUTHOR("Texas Instruments Inc.");
> +MODULE_LICENSE("GPL v2");
Looks fine otherwise.
--
viresh
^ permalink raw reply
* Re: [PATCH 2/4] cpufreq: ti-cpufreq: Add support for multiple regulators
From: Viresh Kumar @ 2017-12-14 4:31 UTC (permalink / raw)
To: Dave Gerlach
Cc: Rob Herring, Rafael J . Wysocki, linux-arm-kernel, linux-omap,
linux-pm, devicetree, Tony Lindgren, Nishanth Menon
In-Reply-To: <20171213203358.20839-3-d-gerlach@ti.com>
On 13-12-17, 14:33, Dave Gerlach wrote:
> Some platforms, like those in the DRA7 and AM57 families, require the
> scaling of multiple regulators in order to properly support higher OPPs.
> Let the ti-cpufreq driver determine when this is required and pass the
> appropriate regulator names to the OPP core so that they can be properly
> managed.
>
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
> ---
> drivers/cpufreq/ti-cpufreq.c | 28 ++++++++++++++++++++++++----
> 1 file changed, 24 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c
> index b1c230a1e2aa..a099b7bf74cd 100644
> --- a/drivers/cpufreq/ti-cpufreq.c
> +++ b/drivers/cpufreq/ti-cpufreq.c
> @@ -51,6 +51,7 @@ struct ti_cpufreq_soc_data {
> unsigned long efuse_mask;
> unsigned long efuse_shift;
> unsigned long rev_offset;
> + bool multi_regulator;
> };
>
> struct ti_cpufreq_data {
> @@ -58,6 +59,7 @@ struct ti_cpufreq_data {
> struct device_node *opp_node;
> struct regmap *syscon;
> const struct ti_cpufreq_soc_data *soc_data;
> + struct opp_table *opp_table;
> };
>
> static unsigned long amx3_efuse_xlate(struct ti_cpufreq_data *opp_data,
> @@ -96,6 +98,7 @@ static struct ti_cpufreq_soc_data am3x_soc_data = {
> .efuse_offset = 0x07fc,
> .efuse_mask = 0x1fff,
> .rev_offset = 0x600,
> + .multi_regulator = false,
> };
>
> static struct ti_cpufreq_soc_data am4x_soc_data = {
> @@ -104,6 +107,7 @@ static struct ti_cpufreq_soc_data am4x_soc_data = {
> .efuse_offset = 0x0610,
> .efuse_mask = 0x3f,
> .rev_offset = 0x600,
> + .multi_regulator = false,
> };
>
> static struct ti_cpufreq_soc_data dra7_soc_data = {
> @@ -112,6 +116,7 @@ static struct ti_cpufreq_soc_data dra7_soc_data = {
> .efuse_mask = 0xf80000,
> .efuse_shift = 19,
> .rev_offset = 0x204,
> + .multi_regulator = true,
> };
>
> /**
> @@ -201,7 +206,9 @@ static int ti_cpufreq_probe(struct platform_device *pdev)
> u32 version[VERSION_COUNT];
> struct device_node *np;
> const struct of_device_id *match;
> + struct opp_table *ti_opp_table;
> struct ti_cpufreq_data *opp_data;
> + const char * const reg_names[] = {"vdd", "vbb"};
> int ret;
>
> np = of_find_node_by_path("/");
> @@ -248,16 +255,29 @@ static int ti_cpufreq_probe(struct platform_device *pdev)
> if (ret)
> goto fail_put_node;
>
> - ret = PTR_ERR_OR_ZERO(dev_pm_opp_set_supported_hw(opp_data->cpu_dev,
> - version, VERSION_COUNT));
> - if (ret) {
> + ti_opp_table = dev_pm_opp_set_supported_hw(opp_data->cpu_dev,
> + version, VERSION_COUNT);
> + if (IS_ERR(ti_opp_table)) {
> dev_err(opp_data->cpu_dev,
> "Failed to set supported hardware\n");
> + ret = PTR_ERR(ti_opp_table);
> goto fail_put_node;
> }
>
> - of_node_put(opp_data->opp_node);
> + opp_data->opp_table = ti_opp_table;
> +
> + if (opp_data->soc_data->multi_regulator) {
> + ti_opp_table = dev_pm_opp_set_regulators(opp_data->cpu_dev,
> + reg_names,
> + ARRAY_SIZE(reg_names));
> + if (IS_ERR(ti_opp_table)) {
> + dev_pm_opp_put_supported_hw(opp_data->opp_table);
> + ret = PTR_ERR(ti_opp_table);
> + goto fail_put_node;
> + }
> + }
>
> + of_node_put(opp_data->opp_node);
> register_cpufreq_dt:
> platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply
* Re: [PATCH 1/4] cpufreq: ti-cpufreq: Convert to module_platform_driver
From: Viresh Kumar @ 2017-12-14 4:29 UTC (permalink / raw)
To: Dave Gerlach
Cc: Rob Herring, Rafael J . Wysocki, linux-arm-kernel, linux-omap,
linux-pm, devicetree, Tony Lindgren, Nishanth Menon
In-Reply-To: <20171213203358.20839-2-d-gerlach@ti.com>
On 13-12-17, 14:33, Dave Gerlach wrote:
> ti-cpufreq will be responsible for calling dev_pm_opp_set_regulators on
> platforms that require AVS and ABB regulator support so we must be
> able to defer probe if regulators are not yet available, so change
> ti-cpufreq to be a module_platform_driver to allow for probe defer.
>
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
> ---
> drivers/cpufreq/ti-cpufreq.c | 23 +++++++++++++++++++++--
> 1 file changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c
> index 923317f03b4b..b1c230a1e2aa 100644
> --- a/drivers/cpufreq/ti-cpufreq.c
> +++ b/drivers/cpufreq/ti-cpufreq.c
> @@ -17,6 +17,7 @@
> #include <linux/cpu.h>
> #include <linux/io.h>
> #include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> #include <linux/init.h>
> #include <linux/of.h>
> #include <linux/of_platform.h>
> @@ -195,7 +196,7 @@ static const struct of_device_id ti_cpufreq_of_match[] = {
> {},
> };
>
> -static int ti_cpufreq_init(void)
> +static int ti_cpufreq_probe(struct platform_device *pdev)
> {
> u32 version[VERSION_COUNT];
> struct device_node *np;
> @@ -269,4 +270,22 @@ static int ti_cpufreq_init(void)
>
> return ret;
> }
> -device_initcall(ti_cpufreq_init);
> +
> +static int ti_cpufreq_init(void)
> +{
> + platform_device_register_simple("ti-cpufreq", -1, NULL, 0);
> + return 0;
> +}
> +module_init(ti_cpufreq_init);
> +
> +static struct platform_driver ti_cpufreq_driver = {
> + .probe = ti_cpufreq_probe,
> + .driver = {
> + .name = "ti-cpufreq",
> + },
> +};
> +module_platform_driver(ti_cpufreq_driver);
> +
> +MODULE_DESCRIPTION("TI CPUFreq/OPP hw-supported driver");
> +MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>");
> +MODULE_LICENSE("GPL v2");
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply
* [PATCH v2 3/3] [DO NOT MERGE] ARM: dts: sun8i: a83t: bpi-m3: Enable PCM5122 codec with I2S1
From: Chen-Yu Tsai @ 2017-12-14 4:23 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171214042350.29469-1-wens-jdAy2FN1RRM@public.gmane.org>
This patch enables a PiFi DAC+ V2.0, which is a PCM5122-based audio
output DAC add-on board for the Raspberry Pi B+ and later, connected
to the GPIO header of the Bananapi M3 via jumper cables. The power,
ground, and I2C pins are in the same position, but the I2S ones are
not.
The I2C controller used is I2C2, while the I2S controller is I2S1.
Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 33 ++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 6550bf0e594b..a9a208ebda12 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -70,6 +70,23 @@
gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
};
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "PiFi DAC+ v2.0";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <512>;
+ simple-audio-card,frame-master = <&link_cpu>;
+ simple-audio-card,bitclock-master = <&link_cpu>;
+
+ link_cpu: simple-audio-card,cpu {
+ sound-dai = <&i2s1>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&pcm5122>;
+ };
+ };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&ac100_rtc 1>;
@@ -100,6 +117,22 @@
status = "okay";
};
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_ph_pins>;
+ status = "okay";
+
+ pcm5122: pcm5122@4d {
+ #sound-dai-cells = <0>;
+ compatible = "ti,pcm5122";
+ reg = <0x4d>;
+ };
+};
+
+&i2s1 {
+ status = "okay";
+};
+
&mdio {
rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
--
2.15.0
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^ permalink raw reply related
* [PATCH v2 2/3] ARM: dts: sun8i: a83t: Add I2C device nodes and pinmux settings
From: Chen-Yu Tsai @ 2017-12-14 4:23 UTC (permalink / raw)
To: Maxime Ripard; +Cc: Chen-Yu Tsai, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20171214042350.29469-1-wens@csie.org>
The A83T has 3 I2C controllers under the standard bus. There is one
more in the R_ block section. The pin functions for the 3 controllers
are on PH 0~6. I2C2 can also be used on pins PE14 and PE15, but these
pins can also mux the CSI (camera sensor interface) controller's
embedded I2C controller. The latter seems to be preferred in the
reference designs for I2C camera sensor access, freeing I2C2 for other
uses.
This patch adds device nodes for the three standard I2C controllers,
as well as pinmux settings for the PH pins. For I2C0 and I2C1, since
they only have one possible setting, just set them by default.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 55 +++++++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 354cb4b48f47..de5119a2a91c 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -348,6 +348,21 @@
drive-strength = <40>;
};
+ i2c0_pins: i2c0-pins {
+ pins = "PH0", "PH1";
+ function = "i2c0";
+ };
+
+ i2c1_pins: i2c1-pins {
+ pins = "PH2", "PH3";
+ function = "i2c1";
+ };
+
+ i2c2_ph_pins: i2c2-ph-pins {
+ pins = "PH4", "PH5";
+ function = "i2c2";
+ };
+
i2s1_pins: i2s1-pins {
/* I2S1 does not have external MCLK pin */
pins = "PG10", "PG11", "PG12", "PG13";
@@ -499,6 +514,46 @@
status = "disabled";
};
+ i2c0: i2c@1c2ac00 {
+ compatible = "allwinner,sun8i-a83t-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@1c2b000 {
+ compatible = "allwinner,sun8i-a83t-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@1c2b400 {
+ compatible = "allwinner,sun8i-a83t-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
emac: ethernet@1c30000 {
compatible = "allwinner,sun8i-a83t-emac";
syscon = <&syscon>;
--
2.15.0
^ permalink raw reply related
* [PATCH v2 1/3] ARM: dts: sun8i: a83t: Add I2S controller device nodes
From: Chen-Yu Tsai @ 2017-12-14 4:23 UTC (permalink / raw)
To: Maxime Ripard; +Cc: Chen-Yu Tsai, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20171214042350.29469-1-wens@csie.org>
The A83T has 3 I2S controllers. The first is multiplexed with the TDM
controller. The pins are generally connected to the codec side of the
AXP81x PMIC/codec/RTC chip. The second is free for other uses. The
third only supports output, and is connected internally to the HDMI
controller for HDMI audio output.
This patch adds device nodes for the controllers, and a default pinmux
setting for the second controller.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 47 +++++++++++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index a384b766f3dc..354cb4b48f47 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -348,6 +348,12 @@
drive-strength = <40>;
};
+ i2s1_pins: i2s1-pins {
+ /* I2S1 does not have external MCLK pin */
+ pins = "PG10", "PG11", "PG12", "PG13";
+ function = "i2s1";
+ };
+
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
@@ -430,6 +436,47 @@
status = "disabled";
};
+ i2s0: i2s@1c22000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-a83t-i2s";
+ reg = <0x01c22000 0x400>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 3>, <&dma 3>;
+ resets = <&ccu RST_BUS_I2S0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s1: i2s@1c22400 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-a83t-i2s";
+ reg = <0x01c22400 0x400>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 4>, <&dma 4>;
+ resets = <&ccu RST_BUS_I2S1>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1_pins>;
+ status = "disabled";
+ };
+
+ i2s2: i2s@1c22800 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-a83t-i2s";
+ reg = <0x01c22800 0x400>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 27>;
+ resets = <&ccu RST_BUS_I2S2>;
+ dma-names = "tx";
+ status = "disabled";
+ };
+
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
--
2.15.0
^ permalink raw reply related
* [PATCH v2 0/3] ARM: sun8i: a83t: Add support for I2S and I2C
From: Chen-Yu Tsai @ 2017-12-14 4:23 UTC (permalink / raw)
To: Maxime Ripard; +Cc: Chen-Yu Tsai, linux-arm-kernel, devicetree, linux-kernel
Hi everyone,
This is v2 of my A83T I2S and I2C support series.
Changes since v1:
- Dropped ASoC patch that was merged
- Added SoC-specific compatible strings for I2C controllers
- Added Maxime's Acked-by
This series adds support for I2S and I2C on the Allwinner A83T SoC.
The I2S controllers are similar to the ones found on the A31. However
the TX FIFO and interrupt status registers were swapped around. This
seems to be a recurring theme for the audio related hardware blocks.
Patch 1 adds device nodes and default pinmux settings for the I2S
controllers.
Patch 2 adds device nodes and default pinmux settings for the I2C
controllers.
Patch 3 is an example of a PCM5122 codec tied to I2C2 and I2S1 over
the GPIO header of the Banana Pi M3. This patch should not be merged.
Please have a look.
Regards
ChenYu
Chen-Yu Tsai (3):
ARM: dts: sun8i: a83t: Add I2S controller device nodes
ARM: dts: sun8i: a83t: Add I2C device nodes and pinmux settings
[DO NOT MERGE] ARM: dts: sun8i: a83t: bpi-m3: Enable PCM5122 codec
with I2S1
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 33 +++++++++
arch/arm/boot/dts/sun8i-a83t.dtsi | 102 +++++++++++++++++++++++++++
2 files changed, 135 insertions(+)
--
2.15.0
^ permalink raw reply
* Re: [PATCH v4 13/15] ARM: dts: sun8i: a83t: Add the PWM pin group
From: Chen-Yu Tsai @ 2017-12-14 3:44 UTC (permalink / raw)
To: Maxime Ripard
Cc: Daniel Vetter, David Airlie, Chen-Yu Tsai, dri-devel,
linux-kernel, Mark Rutland, Rob Herring, linux-arm-kernel,
Priit Laes, Icenowy Zheng, Thomas Petazzoni, Jernej Skrabec,
devicetree, Thierry Reding
In-Reply-To: <b58547cd03f88c65162f362361023b44a4b6fc89.1512662253.git-series.maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On Thu, Dec 7, 2017 at 11:58 PM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> The A83T has a PWM that can be output from the SoC. Let's add a pinctrl
> group for it.
>
> Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Might as well just squash this with patch 11, and enforce it by default.
ChenYu
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^ permalink raw reply
* Re: [PATCH v4 08/15] drm/sun4i: Add LVDS support
From: Chen-Yu Tsai @ 2017-12-14 3:42 UTC (permalink / raw)
To: Maxime Ripard
Cc: Daniel Vetter, David Airlie, Chen-Yu Tsai, dri-devel,
linux-kernel, Mark Rutland, Rob Herring, linux-arm-kernel,
Priit Laes, Icenowy Zheng, Thomas Petazzoni, Jernej Skrabec,
devicetree, Thierry Reding
In-Reply-To: <b64644e9397ec437ec4d3d16be585b22086cf615.1512662253.git-series.maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On Thu, Dec 7, 2017 at 11:58 PM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> The TCON supports the LVDS interface to output to a panel or a bridge.
> Let's add support for it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> ---
> drivers/gpu/drm/sun4i/Makefile | 1 +-
> drivers/gpu/drm/sun4i/sun4i_lvds.c | 177 ++++++++++++++++++++++-
> drivers/gpu/drm/sun4i/sun4i_lvds.h | 18 ++-
> drivers/gpu/drm/sun4i/sun4i_tcon.c | 242 +++++++++++++++++++++++++++++-
> drivers/gpu/drm/sun4i/sun4i_tcon.h | 29 ++++-
> 5 files changed, 465 insertions(+), 2 deletions(-)
> create mode 100644 drivers/gpu/drm/sun4i/sun4i_lvds.c
> create mode 100644 drivers/gpu/drm/sun4i/sun4i_lvds.h
>
[...]
> diff --git a/drivers/gpu/drm/sun4i/sun4i_lvds.h b/drivers/gpu/drm/sun4i/sun4i_lvds.h
> new file mode 100644
> index 000000000000..1b8fad4b82c3
> --- /dev/null
> +++ b/drivers/gpu/drm/sun4i/sun4i_lvds.h
> @@ -0,0 +1,18 @@
> +/*
> + * Copyright (C) 2015 NextThing Co
> + * Copyright (C) 2015-2017 Free Electrons
> + *
> + * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
SPDX?
> +
> +#ifndef _SUN4I_LVDS_H_
> +#define _SUN4I_LVDS_H_
> +
> +int sun4i_lvds_init(struct drm_device *drm, struct sun4i_tcon *tcon);
> +
> +#endif /* _SUN4I_LVDS_H_ */
> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> index 46e28ca1f676..777c7348d0cf 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
[...]
> @@ -698,6 +873,54 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
> return ret;
> }
>
> + /*
> + * This can only be made optional since we've had DT nodes
> + * without the LVDS reset properties.
> + *
> + * If the property is missing, just disable LVDS, and print a
> + * warning.
> + */
> + tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds");
> + if (IS_ERR(tcon->lvds_rst)) {
> + dev_err(dev, "Couldn't get our reset line\n");
> + return PTR_ERR(tcon->lvds_rst);
> + } else if (tcon->lvds_rst) {
> + has_lvds_rst = true;
> + reset_control_reset(tcon->lvds_rst);
> + } else {
> + has_lvds_rst = false;
> + }
> +
> + /*
> + * This can only be made optional since we've had DT nodes
> + * without the LVDS reset properties.
> + *
> + * If the property is missing, just disable LVDS, and print a
> + * warning.
> + */
> + if (tcon->quirks->has_lvds_pll) {
Care to change these names to match the DT property as well?
[...]
> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
> index bd3ad7684870..23db06cdc461 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
[...]
> @@ -149,6 +173,7 @@ struct sun4i_tcon;
>
> struct sun4i_tcon_quirks {
> bool has_channel_1; /* a33 does not have channel 1 */
> + bool has_lvds_pll; /* Can we mux the LVDS clock to a PLL? */
This could then read "Does LVDS clock have parent other than TCON clock?"
Otherwise,
Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
Also see my other (late) reply to the previous version.
> bool needs_de_be_mux; /* sun6i needs mux to select backend */
>
> /* callback to handle tcon muxing options */
> @@ -167,6 +192,9 @@ struct sun4i_tcon {
> struct clk *sclk0;
> struct clk *sclk1;
>
> + /* Possible mux for the LVDS clock */
> + struct clk *lvds_pll;
> +
> /* Pixel clock */
> struct clk *dclk;
> u8 dclk_max_div;
> @@ -174,6 +202,7 @@ struct sun4i_tcon {
>
> /* Reset control */
> struct reset_control *lcd_rst;
> + struct reset_control *lvds_rst;
>
> struct drm_panel *panel;
>
> --
> git-series 0.9.1
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^ permalink raw reply
* Re: [PATCH v3 08/15] drm/sun4i: Add LVDS support
From: Chen-Yu Tsai @ 2017-12-14 3:30 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Daniel Vetter, David Airlie, dri-devel,
linux-kernel, Mark Rutland, Rob Herring, linux-arm-kernel,
Priit Laes, Icenowy Zheng, Thomas Petazzoni, Jernej Skrabec,
devicetree
In-Reply-To: <20171207122521.frv5zgaay3sgol6f-ZC1Zs529Oq4@public.gmane.org>
On Thu, Dec 7, 2017 at 8:25 PM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> Hi,
>
> On Thu, Dec 07, 2017 at 02:05:47PM +0800, Chen-Yu Tsai wrote:
>> > +static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
>> > + const struct drm_encoder *encoder,
>> > + bool enabled)
>> > +{
>> > + if (enabled) {
>> > + u8 val;
>> > +
>> > + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
>> > + SUN4I_TCON0_LVDS_IF_EN,
>> > + SUN4I_TCON0_LVDS_IF_EN);
>> > +
>> > + regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
>> > + SUN4I_TCON0_LVDS_ANA0_C(2) |
>> > + SUN4I_TCON0_LVDS_ANA0_V(3) |
>> > + SUN4I_TCON0_LVDS_ANA0_PD(2) |
>> > + SUN4I_TCON0_LVDS_ANA0_EN_LDO);
>> > + udelay(2);
>> > +
>> > + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
>> > + SUN4I_TCON0_LVDS_ANA0_EN_MB,
>> > + SUN4I_TCON0_LVDS_ANA0_EN_MB);
>> > + udelay(2);
>> > +
>> > + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
>> > + SUN4I_TCON0_LVDS_ANA0_EN_DRVC,
>> > + SUN4I_TCON0_LVDS_ANA0_EN_DRVC);
>> > +
>> > + if (sun4i_tcon_get_pixel_depth(encoder) == 18)
>> > + val = 7;
>> > + else
>> > + val = 0xf;
>> > +
>> > + regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
>> > + SUN4I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
>> > + SUN4I_TCON0_LVDS_ANA0_EN_DRVD(val));
>>
>> I suggest changing the prefix of the macros of the analog bits to
>> SUN6I_TCON0_*. The register definitions and sequence do not apply
>> to the A10/A20. Furthermore you should add a comment saying this
>> doesn't apply to the A10/A20. In the future we might want to move
>> this part into a separate function, referenced by a function pointer
>> from the quirks structure.
>
> I'll change the bit field names and add a comment like you suggested.
>
>> > + } else {
>> > + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
>> > + SUN4I_TCON0_LVDS_IF_EN, 0);
>> > + }
>> > +}
>> > +
>> > void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
>> > const struct drm_encoder *encoder,
>> > bool enabled)
>> > {
>> > + bool is_lvds = false;
>> > int channel;
>> >
>> > switch (encoder->encoder_type) {
>> > + case DRM_MODE_ENCODER_LVDS:
>> > + is_lvds = true;
>> > + /* Fallthrough */
>> > case DRM_MODE_ENCODER_NONE:
>> > channel = 0;
>> > break;
>> > @@ -84,10 +171,16 @@ void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
>> > return;
>> > }
>> >
>> > + if (is_lvds && !enabled)
>> > + sun4i_tcon_lvds_set_status(tcon, encoder, false);
>> > +
>> > regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
>> > SUN4I_TCON_GCTL_TCON_ENABLE,
>> > enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0);
>> >
>> > + if (is_lvds && enabled)
>> > + sun4i_tcon_lvds_set_status(tcon, encoder, true);
>> > +
>> > sun4i_tcon_channel_set_status(tcon, channel, enabled);
>> > }
>> >
>> > @@ -170,6 +263,78 @@ static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
>> > SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
>> > }
>> >
>> > +static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
>> > + const struct drm_encoder *encoder,
>> > + const struct drm_display_mode *mode)
>> > +{
>> > + unsigned int bp;
>> > + u8 clk_delay;
>> > + u32 reg, val = 0;
>> > +
>> > + tcon->dclk_min_div = 7;
>> > + tcon->dclk_max_div = 7;
>> > + sun4i_tcon0_mode_set_common(tcon, mode);
>> > +
>> > + /* Adjust clock delay */
>> > + clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
>> > + regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
>> > + SUN4I_TCON0_CTL_CLK_DELAY_MASK,
>> > + SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
>> > +
>> > + /*
>> > + * This is called a backporch in the register documentation,
>> > + * but it really is the back porch + hsync
>> > + */
>> > + bp = mode->crtc_htotal - mode->crtc_hsync_start;
>> > + DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
>> > + mode->crtc_htotal, bp);
>> > +
>> > + /* Set horizontal display timings */
>> > + regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
>> > + SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) |
>> > + SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
>> > +
>> > + /*
>> > + * This is called a backporch in the register documentation,
>> > + * but it really is the back porch + hsync
>> > + */
>> > + bp = mode->crtc_vtotal - mode->crtc_vsync_start;
>> > + DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
>> > + mode->crtc_vtotal, bp);
>> > +
>> > + /* Set vertical display timings */
>> > + regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
>> > + SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
>> > + SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
>>
>> Can we move the above to a common function?
>
> Until we have DSI support figured out I'd rather not do too much of
> consolidation. We know already a few things are going to change there
> (like the clk_delay), but it's not clear yet how much.
>
>> > + /* Map output pins to channel 0 */
>> > + regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
>> > + SUN4I_TCON_GCTL_IOMAP_MASK,
>> > + SUN4I_TCON_GCTL_IOMAP_TCON0);
>> > +
>> > + /* Enable the output on the pins */
>> > + regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000);
>>
>> Is this still needed? You are no longer using the TCON LCD pins
>> with LVDS.
>
> We do. It's a separate function of the pins, but it's the same pins.
OK. I assume you've tried it without setting it and it failed?
I just assume that these refer to the TCON LCD output, whereas
LVDS looks like a separate module and function, and shouldn't
need it.
ChenYu
>> > static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
>> > .has_channel_1 = true,
>> > + .has_lvds_pll = true,
>>
>> The A31s does not have MIPI.
>
> I'll change that.
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
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* Re: [PATCH v4 06/15] drm/sun4i: Force the mixer rate at 150MHz
From: Chen-Yu Tsai @ 2017-12-14 3:28 UTC (permalink / raw)
To: Maxime Ripard
Cc: Daniel Vetter, David Airlie, Chen-Yu Tsai, dri-devel,
linux-kernel, Mark Rutland, Rob Herring, linux-arm-kernel,
Priit Laes, Icenowy Zheng, Thomas Petazzoni, Jernej Skrabec,
devicetree, Thierry Reding
In-Reply-To: <34f2c9d5c9ab48ead94253144a8e829cccfa4653.1512662253.git-series.maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On Thu, Dec 7, 2017 at 11:58 PM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> It seems like the mixer can only run properly when clocked at 150MHz. In
> order to have something more robust than simply a fire-and-forget
> assigned-clocks-rate, let's put that in the code.
>
> Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> ---
> drivers/gpu/drm/sun4i/sun8i_mixer.c | 9 +++++++++
> drivers/gpu/drm/sun4i/sun8i_mixer.h | 3 +++
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
> index 29ceeb016d72..ff235e3228ce 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
> +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
> @@ -400,6 +400,14 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
> }
> clk_prepare_enable(mixer->mod_clk);
>
> + /*
> + * It seems that we need to enforce that rate for whatever
> + * reason for the mixer to be functional. Make sure it's the
> + * case.
> + */
> + if (mixer->cfg->mod_rate)
> + clk_set_rate(mixer->mod_clk, mixer->cfg->mod_rate);
> +
I think it might be better to set the rate first, then enable the clock.
This is sort of implied by the user manual saying "PLLs other than CPU
do not support DVFS". And it fits better with CLK_SET_RATE_GATE semantics,
if we ever adopt it.
Otherwise,
Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> list_add_tail(&mixer->engine.list, &drv->engine_list);
>
> /* Reset the registers */
> @@ -474,6 +482,7 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
> .ui_num = 1,
> .scaler_mask = 0x3,
> .ccsc = 0,
> + .mod_rate = 150000000,
> };
>
> static const struct of_device_id sun8i_mixer_of_table[] = {
> diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
> index bc58040a88f9..f34e70c42adf 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
> +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
> @@ -121,12 +121,15 @@ struct de2_fmt_info {
> * Set value to 0 if this is first mixer or second mixer with VEP support.
> * Set value to 1 if this is second mixer without VEP support. Other values
> * are invalid.
> + * @mod_rate: module clock rate that needs to be set in order to have
> + * a functional block.
> */
> struct sun8i_mixer_cfg {
> int vi_num;
> int ui_num;
> int scaler_mask;
> int ccsc;
> + unsigned long mod_rate;
> };
>
> struct sun8i_mixer {
> --
> git-series 0.9.1
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^ permalink raw reply
* Re: [PATCH v4 03/15] dt-bindings: display: sun4i-drm: Add LVDS properties
From: Chen-Yu Tsai @ 2017-12-14 3:22 UTC (permalink / raw)
To: Maxime Ripard
Cc: Daniel Vetter, David Airlie, Chen-Yu Tsai, dri-devel,
linux-kernel, Mark Rutland, Rob Herring, linux-arm-kernel,
Priit Laes, Icenowy Zheng, Thomas Petazzoni, Jernej Skrabec,
devicetree, Thierry Reding
In-Reply-To: <8b7042f5e85cc868ea802deba79a0c53ffbe6564.1512662253.git-series.maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On Thu, Dec 7, 2017 at 11:58 PM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> Some clocks and resets supposed to drive the LVDS logic in the display
> engine have been overlooked when the driver was first introduced.
>
> Add those additional resources to the binding, and we'll deal with the ABI
> stability in the code.
>
> Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
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* Re: [PATCH 2/2] ARM: dts: sun8i: Add ADC routing
From: Chen-Yu Tsai @ 2017-12-14 3:08 UTC (permalink / raw)
To: Mylène Josserand
Cc: Liam Girdwood, Mark Brown, Jaroslav Kysela, Takashi Iwai,
Maxime Ripard, Chen-Yu Tsai, Rob Herring, Mark Rutland,
Russell King, Linux-ALSA, linux-arm-kernel, linux-kernel,
devicetree, Thomas Petazzoni
In-Reply-To: <20171213123408.10422-3-mylene.josserand-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On Wed, Dec 13, 2017 at 8:34 PM, Mylène Josserand
<mylene.josserand-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> Add the ADC route between the analog and the digital parts
> of sun8i A33. Configure the MIC1 to use MBIAS and MIC2 to use HBIAS.
>
> Signed-off-by: Mylène Josserand <mylene.josserand-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> ---
> arch/arm/boot/dts/sun8i-a33.dtsi | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
> index 22660919bd08..1841eecd5993 100644
> --- a/arch/arm/boot/dts/sun8i-a33.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a33.dtsi
> @@ -191,7 +191,15 @@
> simple-audio-card,aux-devs = <&codec_analog>;
> simple-audio-card,routing =
> "Left DAC", "AIF1 Slot 0 Left",
> - "Right DAC", "AIF1 Slot 0 Right";
> + "Right DAC", "AIF1 Slot 0 Right",
> + "AIF1 Slot 0 Left ADC", "Left ADC",
> + "AIF1 Slot 0 Right ADC", "Right ADC",
> + "Left ADC", "ADC",
> + "Right ADC", "ADC",
> + "Mic", "MBIAS",
> + "Headset Mic", "HBIAS",
> + "MIC1", "Mic",
> + "MIC2", "Headset Mic";
These entries are board level routing. They should be done in the
board dts files. Unfortunately device tree does not provide a way
to "append" entries to properties, which means one has to copy all
the preceding entries as well.
Also, you are not adding the "Mic" and "Headset Mic" widgets. A33
uses simple-card, which means these connection/board level widgets
must be added using simple-audio-card,widgets.
ChenYu
> status = "disabled";
>
> simple-audio-card,cpu {
> --
> 2.11.0
>
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^ permalink raw reply
* Re: [PATCH v3 3/4] cpufreq: Add DVFS support for Armada 37xx
From: Viresh Kumar @ 2017-12-14 3:04 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Rafael J. Wysocki, linux-pm, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Rob Herring, devicetree, Thomas Petazzoni,
linux-arm-kernel, Antoine Tenart, Miquèl Raynal,
Nadav Haklai, Victor Gu, Marcin Wojtas, Wilson Ding, Hua Jing,
Neta Zur Hershkovits, Evan Wang, Andre Heider
In-Reply-To: <20171213175119.9441-4-gregory.clement@free-electrons.com>
I just searched for tabs and spaces in this patch and here are the observations.
On 13-12-17, 18:51, Gregory CLEMENT wrote:
> +/* Power management in North Bridge register set */
> +#define ARMADA_37XX_NB_L0L1 0x18
There is a single space after #define here, which is good.
> +#define ARMADA_37XX_NB_L2L3 0x1C
> +#define ARMADA_37XX_NB_TBG_DIV_OFF 13
But here and at many places below you have two spaces after #define, which isn't
bad but isn't consistent as well.
> +#define ARMADA_37XX_NB_TBG_DIV_MASK 0x7
> +#define ARMADA_37XX_NB_CLK_SEL_OFF 11
> +#define ARMADA_37XX_NB_CLK_SEL_MASK 0x1
> +#define ARMADA_37XX_NB_CLK_SEL_TBG 0x1
You have used space instead of TAB after ARMADA_37XX_NB_CLK_SEL_TBG here, while
everywhere else we have tabs. Maybe its better to be consistent ?
> +#define ARMADA_37XX_NB_TBG_SEL_OFF 9
> +#define ARMADA_37XX_NB_TBG_SEL_MASK 0x3
> +#define ARMADA_37XX_NB_VDD_SEL_OFF 6
> +#define ARMADA_37XX_NB_VDD_SEL_MASK 0x3
> +#define ARMADA_37XX_NB_CONFIG_SHIFT 16
> +#define ARMADA_37XX_NB_DYN_MOD 0x24
> +#define ARMADA_37XX_NB_CLK_SEL_EN BIT(26)
> +#define ARMADA_37XX_NB_TBG_EN BIT(28)
> +#define ARMADA_37XX_NB_DIV_EN BIT(29)
> +#define ARMADA_37XX_NB_VDD_EN BIT(30)
> +#define ARMADA_37XX_NB_DFS_EN BIT(31)
> +#define ARMADA_37XX_NB_CPU_LOAD 0x30
> +#define ARMADA_37XX_NB_CPU_LOAD_MASK 0x3
> +#define ARMADA_37XX_DVFS_LOAD_0 0
> +#define ARMADA_37XX_DVFS_LOAD_1 1
> +#define ARMADA_37XX_DVFS_LOAD_2 2
> +#define ARMADA_37XX_DVFS_LOAD_3 3
> +
> +/*
> + * On Armada 37xx the Power management manages 4 level of CPU load,
> + * each level can be associated with a CPU clock source, a CPU
> + * divider, a VDD level, etc...
> + */
> +#define LOAD_LEVEL_NR 4
> +
> +struct armada_37xx_dvfs {
> + u32 cpu_freq_max;
> + u8 divider[LOAD_LEVEL_NR];
> +};
> +
> +static struct armada_37xx_dvfs armada_37xx_dvfs[] = {
> + {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} },
> + {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
> + {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
> + {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
> +};
> +
> +static struct armada_37xx_dvfs *armada_37xx_cpu_freq_info_get(u32 freq)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(armada_37xx_dvfs); i++) {
> + if (freq == armada_37xx_dvfs[i].cpu_freq_max)
> + return &armada_37xx_dvfs[i];
> + }
> +
> + pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000);
> + return NULL;
> +}
> +
> +/*
> + * Setup the four level managed by the hardware. Once the four level
> + * will be configured then the DVFS will be enabled.
> + */
> +static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
> + struct clk *clk, u8 *divider)
> +{
> + int load_lvl;
> + struct clk *parent;
> +
> + for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
> + unsigned int reg, mask, val, offset = 0;
double space before "val".
> +
> + if (load_lvl <= ARMADA_37XX_DVFS_LOAD_1)
> + reg = ARMADA_37XX_NB_L0L1;
> + else
> + reg = ARMADA_37XX_NB_L2L3;
> +
> + if (load_lvl == ARMADA_37XX_DVFS_LOAD_0 ||
> + load_lvl == ARMADA_37XX_DVFS_LOAD_2)
double spaces after ==
> + offset += ARMADA_37XX_NB_CONFIG_SHIFT;
> +
> + /* Set cpu clock source, for all the level we use TBG */
> + val = ARMADA_37XX_NB_CLK_SEL_TBG << ARMADA_37XX_NB_CLK_SEL_OFF;
> + mask = (ARMADA_37XX_NB_CLK_SEL_MASK
> + << ARMADA_37XX_NB_CLK_SEL_OFF);
> +
> + /*
> + * Set cpu divider based on the pre-computed array in
> + * order to have balanced step.
> + */
> + val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF;
> + mask |= (ARMADA_37XX_NB_TBG_DIV_MASK
> + << ARMADA_37XX_NB_TBG_DIV_OFF);
> +
> + /* Set VDD divider which is actually the load level. */
> + val |= load_lvl << ARMADA_37XX_NB_VDD_SEL_OFF;
> + mask |= (ARMADA_37XX_NB_VDD_SEL_MASK
> + << ARMADA_37XX_NB_VDD_SEL_OFF);
> +
> + val <<= offset;
> + mask <<= offset;
> +
> + regmap_update_bits(base, reg, mask, val);
> + }
> +
> + /*
> + * Set cpu clock source, for all the level we keep the same
> + * clock source that the one already configured. For this one
> + * we need to use the clock framework
> + */
> + parent = clk_get_parent(clk);
> + clk_set_parent(clk, parent);
> +}
> +
> +static void __init armada37xx_cpufreq_disable_dvfs(struct regmap *base)
> +{
> + unsigned int reg = ARMADA_37XX_NB_DYN_MOD,
> + mask = ARMADA_37XX_NB_DFS_EN;
> +
> + regmap_update_bits(base, reg, mask, 0);
> +}
> +
> +static void __init armada37xx_cpufreq_enable_dvfs(struct regmap *base)
> +{
> + unsigned int val, reg = ARMADA_37XX_NB_CPU_LOAD,
> + mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
> +
> + /* Start with the highest load (0) */
> + val = ARMADA_37XX_DVFS_LOAD_0;
> + regmap_update_bits(base, reg, mask, val);
> +
> + /* Now enable DVFS for the CPUs */
> + reg = ARMADA_37XX_NB_DYN_MOD;
> + mask = ARMADA_37XX_NB_CLK_SEL_EN | ARMADA_37XX_NB_TBG_EN |
> + ARMADA_37XX_NB_DIV_EN | ARMADA_37XX_NB_VDD_EN |
> + ARMADA_37XX_NB_DFS_EN;
> +
> + regmap_update_bits(base, reg, mask, mask);
> +}
> +
> +static int __init armada37xx_cpufreq_driver_init(void)
> +{
> + struct armada_37xx_dvfs *dvfs;
> + struct platform_device *pdev;
> + unsigned int cur_frequency;
> + struct regmap *nb_pm_base;
> + struct device *cpu_dev;
> + int load_lvl, ret;
> + struct clk *clk;
> +
> + nb_pm_base =
> + syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
> +
> + if (IS_ERR(nb_pm_base))
> + return -ENODEV;
> +
> + /* Before doing any configuration on the DVFS first, disable it */
> + armada37xx_cpufreq_disable_dvfs(nb_pm_base);
> +
> + /*
> + * On CPU 0 register the operating points supported (which are
> + * the nominal CPU frequency and full integer divisions of
> + * it).
> + */
> + cpu_dev = get_cpu_device(0);
> + if (!cpu_dev) {
> + dev_err(cpu_dev, "Cannot get CPU\n");
> + return -ENODEV;
> + }
> +
> + clk = clk_get(cpu_dev, 0);
> + if (IS_ERR(clk)) {
> + dev_err(cpu_dev, "Cannot get clock for CPU0\n");
> + return PTR_ERR(clk);
> + }
> +
> + /* Get nominal (current) CPU frequency */
> + cur_frequency = clk_get_rate(clk);
> + if (!cur_frequency) {
> + dev_err(cpu_dev, "Failed to get clock rate for CPU\n");
> + return -EINVAL;
> + }
> +
> + dvfs = armada_37xx_cpu_freq_info_get(cur_frequency);
> + if (!dvfs)
> + return -EINVAL;
> +
> + armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider);
> +
> + for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
> + load_lvl++) {
> + unsigned long freq = cur_frequency / dvfs->divider[load_lvl];
> +
> + ret = dev_pm_opp_add(cpu_dev, freq, 0);
> + if (ret) {
> + /* clean-up the already added opp before leaving */
Double space after /*
> + while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) {
> + freq = cur_frequency / dvfs->divider[load_lvl];
> + dev_pm_opp_remove(cpu_dev, freq);
> + }
> + return ret;
> + }
> + }
> +
> + /* Now that everything is setup, enable the DVFS at hardware level */
> + armada37xx_cpufreq_enable_dvfs(nb_pm_base);
> +
> + pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
> +
> + return PTR_ERR_OR_ZERO(pdev);
> +}
> +/* late_initcall, to guarantee the driver is loaded after A37xx clock driver */
> +late_initcall(armada37xx_cpufreq_driver_init);
> +
> +MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
> +MODULE_DESCRIPTION("Armada 37xx cpufreq driver");
> +MODULE_LICENSE("GPL");
I am not objecting to using double spaces at all these locations, its fine. Just
that I wanted to point it out in case it is not intentional.
--
viresh
^ permalink raw reply
* [PATCH v2] ARM64: dts: meson-axg: add ethernet mac controller
From: Yixun Lan @ 2017-12-14 3:02 UTC (permalink / raw)
To: devicetree, Kevin Hilman
Cc: Neil Armstrong, Jerome Brunet, Giuseppe Cavallaro,
Alexandre Torgue, Carlo Caione, Yixun Lan, linux-amlogic,
linux-arm-kernel, linux-kernel, netdev
Add DT info for the stmmac ethernet MAC which found in
the Amlogic's Meson-AXG SoC, also describe the ethernet
pinctrl & clock information here.
This is tested in the S400 dev board which use a RTL8211F PHY,
and the pins connect to the 'eth_rgmii_y_pins' group.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
Changes in v2 since [1]:
- rebase to kevin's v4.16/dt64 branch
- add Neil's Reviewed-by
- move clock info to board.dts instead of in soc.dtsi
- drop "meson-axg-dwmac" compatible string, since we didn't use this
we could re-add it later when we really need.
- note: to make ethernet work properly,it depend on clock & pinctrl[2],
to compile the DTS, the patch [3] is required.
the code part will be taken via clock & pinctrl subsystem tree.
[1]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005301.html
[2]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005735.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005694.html
[3]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005738.html
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 11 ++++++
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 50 ++++++++++++++++++++++++++
2 files changed, 61 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..138de3bc7cc8 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -20,3 +20,14 @@
&uart_AO {
status = "okay";
};
+
+ðmac {
+ status = "okay";
+ clocks = <&clkc CLKID_ETH>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_MPLL2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1";
+ phy-mode = "rgmii";
+ pinctrl-0 = <ð_rgmii_y_pins>;
+ pinctrl-names = "default";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index d356ce74ad89..106234fda765 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/axg-clkc.h>
/ {
compatible = "amlogic,meson-axg";
@@ -148,6 +149,15 @@
#address-cells = <0>;
};
+ ethmac: ethernet@ff3f0000 {
+ compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
+ reg = <0x0 0xff3f0000 0x0 0x10000
+ 0x0 0xff634540 0x0 0x8>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "macirq";
+ status = "disabled";
+ };
+
hiubus: bus@ff63c000 {
compatible = "simple-bus";
reg = <0x0 0xff63c000 0x0 0x1c00>;
@@ -194,6 +204,46 @@
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_periphs 0 0 86>;
};
+
+ eth_rgmii_x_pins: eth-x-rgmii {
+ mux {
+ groups = "eth_mdio_x",
+ "eth_mdc_x",
+ "eth_rgmii_rx_clk_x",
+ "eth_rx_dv_x",
+ "eth_rxd0_x",
+ "eth_rxd1_x",
+ "eth_rxd2_rgmii",
+ "eth_rxd3_rgmii",
+ "eth_rgmii_tx_clk",
+ "eth_txen_x",
+ "eth_txd0_x",
+ "eth_txd1_x",
+ "eth_txd2_rgmii",
+ "eth_txd3_rgmii";
+ function = "eth";
+ };
+ };
+
+ eth_rgmii_y_pins: eth-y-rgmii {
+ mux {
+ groups = "eth_mdio_y",
+ "eth_mdc_y",
+ "eth_rgmii_rx_clk_y",
+ "eth_rx_dv_y",
+ "eth_rxd0_y",
+ "eth_rxd1_y",
+ "eth_rxd2_rgmii",
+ "eth_rxd3_rgmii",
+ "eth_rgmii_tx_clk",
+ "eth_txen_y",
+ "eth_txd0_y",
+ "eth_txd1_y",
+ "eth_txd2_rgmii",
+ "eth_txd3_rgmii";
+ function = "eth";
+ };
+ };
};
};
--
2.15.1
^ permalink raw reply related
* Re: [PATCH] arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information
From: Leo Yan @ 2017-12-14 1:07 UTC (permalink / raw)
To: Valentin Schneider
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Wei Xu, Rob Herring,
Mark Rutland, Catalin Marinas, Will Deacon, Dietmar Eggemann,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <cddaf386-5688-a064-7cb0-1e75485330c4-5wv7dgnIgG8@public.gmane.org>
On Wed, Dec 13, 2017 at 03:16:13PM +0000, Valentin Schneider wrote:
> Hi Leo,
>
>
> On 12/13/2017 02:53 PM, Leo Yan wrote:
> >Hi Valentin,
> >
> >On Wed, Dec 13, 2017 at 02:21:06PM +0000, Valentin Schneider wrote:
> >>The following dt entries are added:
> >> cpus [0-3] (Cortex A53):
> >> - capacity-dmips-mhz = <592>;
> >>
> >> cpus [4-7] (Cortex A73):
> >> - capacity-dmips-mhz = <1024>;
> >>
> >>Those values were obtained by running dhrystone 2.1 on a
> >>HiKey960 with the following procedure:
> >>- Offline all CPUs but CPU0 (A53)
> >>- Set CPU0 frequency to maximum
> >>- Run Dhrystone 2.1 for 20 seconds
> >>
> >>- Offline all CPUs but CPU4 (A73)
> >>- set CPU4 frequency to maximum
> >>- Run Dhrystone 2.1 for 20 seconds
> >>
> >>The results are as follows:
> >>A53: 129633887 loops
> >>A73: 287034147 loops
> >Seems to me the capacity-dmips-mhz should be:
> >
> >CA53: 129633887 / 20 / 1844 = 3515
> >CA73: 287034147 / 20 / 2362 = 6076
> >
> >After normalized to range [0..1024], we could get:
> >
> >CA53: 592
> >CA73: 1024
>
> Yes, that's the "direct approach". I wanted to underline the fact that there
> are two different max frequencies so what I followed would be:
>
> 1) Computing the performance ratio:
> (129633887 / 287034147) * 1024 = 462.47
>
> 2) Scaling that to the same frequency scale:
> 462.47 * (2362/1844) = 592.38
>
> Which gives the same end result (it's the same equation but split in two
> steps). Also it makes it easy to check that the cpu_capacity sysfs entry for
> the A53s gets correctly set (to 462).
Yeah, thanks for clear explanation.
[...]
Thanks,
Leo Yan
--
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^ permalink raw reply
* Re: [PATCH v3 3/8] PCI: brcmstb: Add Broadcom STB PCIe host controller driver
From: Jim Quinlan @ 2017-12-13 23:53 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Bjorn Helgaas,
Catalin Marinas, Will Deacon, Rob Herring, Brian Norris,
Russell King, Robin Murphy, Christoph Hellwig, Florian Fainelli,
Jonas Gorski, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
Linux-MIPS, linux-pci, Kevin Cernekee, Ralf Baechle,
bcm-kernel-feedback-list, Gregory Fong, linux-arm-kernel
In-Reply-To: <20171212221642.GB95453-1RhO1Y9PlrlHTL0Zs8A6p5iNqAH0jzoTYJqu5kTmcBRl57MIdRCFDg@public.gmane.org>
On Tue, Dec 12, 2017 at 5:16 PM, Bjorn Helgaas <helgaas-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Tue, Nov 14, 2017 at 05:12:07PM -0500, Jim Quinlan wrote:
>> This commit adds the basic Broadcom STB PCIe controller. Missing is
>> the ability to process MSI and also handle dma-ranges for inbound
>> memory accesses. These two functionalities are added in subsequent
>> commits.
>>
>> The PCIe block contains an MDIO interface. This is a local interface
>> only accessible by the PCIe controller. It cannot be used or shared
>> by any other HW. As such, the small amount of code for this
>> controller is included in this driver as there is little upside to put
>> it elsewhere.
>>
>> Signed-off-by: Jim Quinlan <jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>> drivers/pci/host/Kconfig | 9 +
>> drivers/pci/host/Makefile | 1 +
>> drivers/pci/host/pcie-brcmstb.c | 1124 +++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 1134 insertions(+)
>> create mode 100644 drivers/pci/host/pcie-brcmstb.c
>>
>> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
>> index b868803..751463e 100644
>> --- a/drivers/pci/host/Kconfig
>> +++ b/drivers/pci/host/Kconfig
>> @@ -220,4 +220,13 @@ config VMD
>> To compile this driver as a module, choose M here: the
>> module will be called vmd.
>>
>> +config PCIE_BRCMSTB
>> + tristate "Broadcom Brcmstb PCIe platform host driver"
>> + depends on ARCH_BRCMSTB || BMIPS_GENERIC
>> + depends on OF
>> + depends on SOC_BRCMSTB
>> + default ARCH_BRCMSTB || BMIPS_GENERIC
>> + help
>> + Adds support for Broadcom Settop Box PCIe host controller.
>> +
>> endmenu
>> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
>> index 1238278..a8b9923 100644
>> --- a/drivers/pci/host/Makefile
>> +++ b/drivers/pci/host/Makefile
>> @@ -21,6 +21,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
>> obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
>> obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
>> obj-$(CONFIG_VMD) += vmd.o
>> +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
>>
>> # The following drivers are for devices that use the generic ACPI
>> # pci_root.c driver but don't support standard ECAM config access.
>> diff --git a/drivers/pci/host/pcie-brcmstb.c b/drivers/pci/host/pcie-brcmstb.c
>> new file mode 100644
>> index 0000000..d8a8f7a
>> --- /dev/null
>> +++ b/drivers/pci/host/pcie-brcmstb.c
>> @@ -0,0 +1,1124 @@
>> +/*
>> + * Copyright (C) 2009 - 2017 Broadcom
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/compiler.h>
>> +#include <linux/delay.h>
>> +#include <linux/init.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +#include <linux/ioport.h>
>> +#include <linux/irqdomain.h>
>> +#include <linux/kernel.h>
>> +#include <linux/list.h>
>> +#include <linux/log2.h>
>> +#include <linux/module.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/of_pci.h>
>> +#include <linux/of_pci.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/pci.h>
>> +#include <linux/printk.h>
>> +#include <linux/sizes.h>
>> +#include <linux/slab.h>
>> +#include <soc/brcmstb/memory_api.h>
>> +#include <linux/string.h>
>> +#include <linux/types.h>
>> +
>> +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
>> +#define BRCM_PCIE_CAP_REGS 0x00ac
>
> Add a blank line before multi-line comments.
>
>> +/*
>> + * Broadcom Settop Box PCIE Register Offsets. The names are from
>> + * the chip's RDB and we use them here so that a script can correlate
>> + * this code and the RDB to prevent discrepancies.
>
> Use "PCIe" capitalization in English text and messages.
>
>> + */
>> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
>> +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
>> +#define PCIE_RC_DL_MDIO_ADDR 0x1100
>> +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
>> +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
>> +#define PCIE_MISC_MISC_CTRL 0x4008
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
>> +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
>> +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
>> +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
>> +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
>> +#define PCIE_MISC_PCIE_CTRL 0x4064
>> +#define PCIE_MISC_PCIE_STATUS 0x4068
>> +#define PCIE_MISC_REVISION 0x406c
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
>> +#define PCIE_INTR2_CPU_BASE 0x4300
>> +
>> +/*
>> + * Broadcom Settop Box PCIE Register Field shift and mask info. The
>> + * names are from the chip's RDB and we use them here so that a script
>> + * can correlate this code and the RDB to prevent discrepancies.
>> + */
>> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
>> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 0x2
>> +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
>> +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0
>> +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
>> +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 0xc
>> +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
>> +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd
>> +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
>> +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14
>> +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
>> +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b
>> +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
>> +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16
>> +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
>> +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0
>> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
>> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0x0
>> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
>> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0x0
>> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
>> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0x0
>> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
>> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT 0x2
>> +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
>> +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 0x7
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6
>> +#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
>> +#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS 0xc
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0
>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b
>> +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
>> +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
>> +
>> +#define BRCM_NUM_PCIE_OUT_WINS 0x4
>> +#define BRCM_MAX_SCB 0x4
>> +
>> +#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
>> +#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
>> +
>> +#define BURST_SIZE_128 0
>> +#define BURST_SIZE_256 1
>> +#define BURST_SIZE_512 2
>> +
>> +/* Offsets from PCIE_INTR2_CPU_BASE */
>> +#define STATUS 0x0
>> +#define SET 0x4
>> +#define CLR 0x8
>> +#define MASK_STATUS 0xc
>> +#define MASK_SET 0x10
>> +#define MASK_CLR 0x14
>> +
>> +#define PCIE_BUSNUM_SHIFT 20
>> +#define PCIE_SLOT_SHIFT 15
>> +#define PCIE_FUNC_SHIFT 12
>> +
>> +#if defined(__BIG_ENDIAN)
>> +#define DATA_ENDIAN 2 /* PCIe->DDR inbound accesses */
>> +#define MMIO_ENDIAN 2 /* CPU->PCIe outbound accesses */
>> +#else
>> +#define DATA_ENDIAN 0
>> +#define MMIO_ENDIAN 0
>> +#endif
>> +
>> +#define MDIO_PORT0 0x0
>> +#define MDIO_DATA_MASK 0x7fffffff
>> +#define MDIO_DATA_SHIFT 0x0
>> +#define MDIO_PORT_MASK 0xf0000
>> +#define MDIO_PORT_SHIFT 0x16
>> +#define MDIO_REGAD_MASK 0xffff
>> +#define MDIO_REGAD_SHIFT 0x0
>> +#define MDIO_CMD_MASK 0xfff00000
>> +#define MDIO_CMD_SHIFT 0x14
>> +#define MDIO_CMD_READ 0x1
>> +#define MDIO_CMD_WRITE 0x0
>> +#define MDIO_DATA_DONE_MASK 0x80000000
>> +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
>> +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
>> +#define SSC_REGS_ADDR 0x1100
>> +#define SET_ADDR_OFFSET 0x1f
>> +#define SSC_CNTL_OFFSET 0x2
>> +#define SSC_CNTL_OVRD_EN_MASK 0x8000
>> +#define SSC_CNTL_OVRD_EN_SHIFT 0xf
>> +#define SSC_CNTL_OVRD_VAL_MASK 0x4000
>> +#define SSC_CNTL_OVRD_VAL_SHIFT 0xe
>> +#define SSC_STATUS_OFFSET 0x1
>> +#define SSC_STATUS_SSC_MASK 0x400
>> +#define SSC_STATUS_SSC_SHIFT 0xa
>> +#define SSC_STATUS_PLL_LOCK_MASK 0x800
>> +#define SSC_STATUS_PLL_LOCK_SHIFT 0xb
>> +
>> +#define IDX_ADDR(pcie) \
>> + ((pcie)->reg_offsets[EXT_CFG_INDEX])
>> +#define DATA_ADDR(pcie) \
>> + ((pcie)->reg_offsets[EXT_CFG_DATA])
>> +#define PCIE_RGR1_SW_INIT_1(pcie) \
>> + ((pcie)->reg_offsets[RGR1_SW_INIT_1])
>> +
>> +enum {
>> + RGR1_SW_INIT_1,
>> + EXT_CFG_INDEX,
>> + EXT_CFG_DATA,
>> +};
>> +
>> +enum {
>> + RGR1_SW_INIT_1_INIT_MASK,
>> + RGR1_SW_INIT_1_INIT_SHIFT,
>> + RGR1_SW_INIT_1_PERST_MASK,
>> + RGR1_SW_INIT_1_PERST_SHIFT,
>> +};
>> +
>> +enum pcie_type {
>> + BCM7425,
>> + BCM7435,
>> + GENERIC,
>> + BCM7278,
>> +};
>> +
>> +struct brcm_window {
>> + dma_addr_t pcie_addr;
>> + phys_addr_t cpu_addr;
>> + dma_addr_t size;
>> +};
>> +
>> +/* Internal PCIe Host Controller Information.*/
>> +struct brcm_pcie {
>> + struct list_head list;
>> + struct device *dev;
>> + void __iomem *base;
>> + struct list_head resources;
>> + int irq;
>> + struct clk *clk;
>> + struct pci_bus *root_bus;
>> + struct device_node *dn;
>> + int id;
>> + bool suspended;
>> + int num_out_wins;
>> + bool ssc;
>> + int gen;
>> + struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
>> + unsigned int rev;
>> + const int *reg_offsets;
>> + const int *reg_field_info;
>> + enum pcie_type type;
>> +};
>> +
>> +struct pcie_cfg_data {
>> + const int *reg_field_info;
>> + const int *offsets;
>> + const enum pcie_type type;
>> +};
>> +
>> +static const int pcie_reg_field_info[] = {
>> + [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
>> + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
>> +};
>> +
>> +static const int pcie_reg_field_info_bcm7278[] = {
>> + [RGR1_SW_INIT_1_INIT_MASK] = 0x1,
>> + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x0,
>> +};
>> +
>> +static const int pcie_offset_bcm7425[] = {
>> + [RGR1_SW_INIT_1] = 0x8010,
>> + [EXT_CFG_INDEX] = 0x8300,
>> + [EXT_CFG_DATA] = 0x8304,
>> +};
>> +
>> +static const struct pcie_cfg_data bcm7425_cfg = {
>> + .reg_field_info = pcie_reg_field_info,
>> + .offsets = pcie_offset_bcm7425,
>> + .type = BCM7425,
>> +};
>> +
>> +static const int pcie_offsets[] = {
>> + [RGR1_SW_INIT_1] = 0x9210,
>> + [EXT_CFG_INDEX] = 0x9000,
>> + [EXT_CFG_DATA] = 0x9004,
>> +};
>> +
>> +static const struct pcie_cfg_data bcm7435_cfg = {
>> + .reg_field_info = pcie_reg_field_info,
>> + .offsets = pcie_offsets,
>> + .type = BCM7435,
>> +};
>> +
>> +static const struct pcie_cfg_data generic_cfg = {
>> + .reg_field_info = pcie_reg_field_info,
>> + .offsets = pcie_offsets,
>> + .type = GENERIC,
>> +};
>> +
>> +static const int pcie_offset_bcm7278[] = {
>> + [RGR1_SW_INIT_1] = 0xc010,
>> + [EXT_CFG_INDEX] = 0x9000,
>> + [EXT_CFG_DATA] = 0x9004,
>> +};
>> +
>> +static const struct pcie_cfg_data bcm7278_cfg = {
>> + .reg_field_info = pcie_reg_field_info_bcm7278,
>> + .offsets = pcie_offset_bcm7278,
>> + .type = BCM7278,
>> +};
>> +
>> +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
>> + int where);
>> +
>> +static struct pci_ops brcm_pcie_ops = {
>> + .map_bus = brcm_pcie_map_conf,
>> + .read = pci_generic_config_read,
>> + .write = pci_generic_config_write,
>> +};
>> +
>> +#if defined(CONFIG_MIPS)
>> +/* Broadcom MIPs HW implicitly does the swapping if necessary */
>> +#define bcm_readl(a) __raw_readl(a)
>> +#define bcm_writel(d, a) __raw_writel(d, a)
>> +#define bcm_readw(a) __raw_readw(a)
>> +#define bcm_writew(d, a) __raw_writew(d, a)
>> +#else
>> +#define bcm_readl(a) readl(a)
>> +#define bcm_writel(d, a) writel(d, a)
>> +#define bcm_readw(a) readw(a)
>> +#define bcm_writew(d, a) writew(d, a)
>> +#endif
>> +
>> +/*
>> + * These macros are designed to sxtract/insert fields to host controller's
>> + * register set.
>
> s/are designed to s/ e/ (I assume they actually *do* extract/insert)
>
>> + */
>> +#define RD_FLD(base, reg, field) \
>> + rd_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
>> +#define WR_FLD(base, reg, field, val) \
>> + wr_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
>> +#define WR_FLD_RB(base, reg, field, val) \
>> + wr_fld_rb(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
>> +#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
>> + wr_fld(base + reg + off, reg##_##field##_MASK, \
>> + reg##_##field##_SHIFT, val)
>> +#define EXTRACT_FIELD(val, reg, field) \
>> + ((val & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
>> +#define INSERT_FIELD(val, reg, field, field_val) \
>> + ((val & ~reg##_##field##_MASK) | \
>> + (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
>> +
>> +static struct list_head brcm_pcie = LIST_HEAD_INIT(brcm_pcie);
>> +static phys_addr_t scb_size[BRCM_MAX_SCB];
>> +static int num_memc;
>> +static DEFINE_MUTEX(brcm_pcie_lock);
>> +
>> +static u32 rd_fld(void __iomem *p, u32 mask, int shift)
>> +{
>> + return (bcm_readl(p) & mask) >> shift;
>> +}
>> +
>> +static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
>> +{
>> + u32 reg = bcm_readl(p);
>> +
>> + reg = (reg & ~mask) | ((val << shift) & mask);
>> + bcm_writel(reg, p);
>> +}
>> +
>> +static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
>> +{
>> + wr_fld(p, mask, shift, val);
>> + (void)bcm_readl(p);
>> +}
>> +
>> +static const char *link_speed_to_str(int s)
>> +{
>> + switch (s) {
>> + case 1:
>> + return "2.5";
>> + case 2:
>> + return "5.0";
>> + case 3:
>> + return "8.0";
>> + default:
>> + break;
>> + }
>> + return "???";
>> +}
>> +
>> +/*
>> + * The roundup_pow_of_two() from log2.h invokes
>> + * __roundup_pow_of_two(unsigned long), but we really need a
>> + * such a function to take a native u64 since unsigned long
>> + * is 32 bits on some configurations. So we provide this helper
>> + * function below.
>> + */
>> +static u64 roundup_pow_of_two_64(u64 n)
>> +{
>> + return 1ULL << fls64(n - 1);
>> +}
>> +
>> +/*
>> + * This is to convert the size of the inbound bar region to the
>> + * non-liniear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
>
> s/bar/BAR/ (This doesn't sound like a BAR in the PCI spec sense, but if
> that's what you call it, might as well spell it as the acronym)
>
> s/non-liniear/non-linear/
>
>> + */
>> +int encode_ibar_size(u64 size)
>> +{
>> + int log2_in = ilog2(size);
>> +
>> + if (log2_in >= 12 && log2_in <= 15)
>> + /* Covers 4KB to 32KB (inclusive) */
>> + return (log2_in - 12) + 0x1c;
>> + else if (log2_in >= 16 && log2_in <= 37)
>> + /* Covers 64KB to 32GB, (inclusive) */
>> + return log2_in - 15;
>> + /* Something is awry so disable */
>> + return 0;
>> +}
>> +
>> +static u32 mdio_form_pkt(int port, int regad, int cmd)
>> +{
>> + u32 pkt = 0;
>> +
>> + pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
>> + pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
>> + pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
>> +
>> + return pkt;
>> +}
>> +
>> +/* negative return value indicates error */
>> +static int mdio_read(void __iomem *base, u8 port, u8 regad)
>> +{
>> + int tries;
>> + u32 data;
>> +
>> + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
>> + base + PCIE_RC_DL_MDIO_ADDR);
>> + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
>> +
>> + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
>> + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
>> + udelay(10);
>> + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
>> + }
>> +
>> + return MDIO_RD_DONE(data)
>> + ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
>> + : -EIO;
>> +}
>> +
>> +/* negative return value indicates error */
>> +static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
>> +{
>> + int tries;
>> + u32 data;
>> +
>> + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
>> + base + PCIE_RC_DL_MDIO_ADDR);
>> + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
>> + bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
>> + base + PCIE_RC_DL_MDIO_WR_DATA);
>> +
>> + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
>> + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
>> + udelay(10);
>> + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
>> + }
>> +
>> + return MDIO_WT_DONE(data) ? 0 : -EIO;
>> +}
>> +
>> +/* configures device for ssc mode; negative return value indicates error */
>
> I guess "ssc" means Spread Spectrum Clocking? Maybe spell out the
> first occurrence and spell as acronym in English text?
>
>> +static int set_ssc(void __iomem *base)
>> +{
>> + int tmp;
>> + u16 wrdata;
>> + int pll, ssc;
>> +
>> + tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
>> + if (tmp < 0)
>> + return tmp;
>> +
>> + tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
>> + if (tmp < 0)
>> + return tmp;
>> +
>> + wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
>> + wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
>> + tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
>> + if (tmp < 0)
>> + return tmp;
>> +
>> + usleep_range(1000, 2000);
>> + tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
>> + if (tmp < 0)
>> + return tmp;
>> +
>> + ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
>> + pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
>> +
>> + return (ssc && pll) ? 0 : -EIO;
>> +}
>> +
>> +/* limits operation to a specific generation (1, 2, or 3) */
>> +static void set_gen(void __iomem *base, int gen)
>> +{
>> + u32 lnkcap = bcm_readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
>> + u16 lnkctl2 = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
>> +
>> + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
>> + bcm_writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
>> +
>> + lnkctl2 = (lnkctl2 & ~0xf) | gen;
>> + bcm_writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
>> +}
>> +
>> +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
>> + unsigned int win, phys_addr_t cpu_addr,
>> + dma_addr_t pcie_addr, dma_addr_t size)
>> +{
>> + void __iomem *base = pcie->base;
>> + phys_addr_t cpu_addr_mb, limit_addr_mb;
>> + u32 tmp;
>> +
>> + /* Set the base of the pcie_addr window */
>> + bcm_writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN,
>> + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
>> + bcm_writel(upper_32_bits(pcie_addr),
>> + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
>> +
>> + cpu_addr_mb = cpu_addr >> 20;
>> + limit_addr_mb = (cpu_addr + size - 1) >> 20;
>> +
>> + /* Write the addr base low register */
>> + WR_FLD_WITH_OFFSET(base, (win * 4),
>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
>> + BASE, cpu_addr_mb);
>> + /* Write the addr limit low register */
>> + WR_FLD_WITH_OFFSET(base, (win * 4),
>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
>> + LIMIT, limit_addr_mb);
>> +
>> + if (pcie->type != BCM7435 && pcie->type != BCM7425) {
>> + /* Write the cpu addr high register */
>> + tmp = (u32)(cpu_addr_mb >>
>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
>> + WR_FLD_WITH_OFFSET(base, (win * 8),
>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
>> + BASE, tmp);
>> + /* Write the cpu limit high register */
>> + tmp = (u32)(limit_addr_mb >>
>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
>> + WR_FLD_WITH_OFFSET(base, (win * 8),
>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
>> + LIMIT, tmp);
>> + }
>> +}
>> +
>> +/* Configuration space read/write support */
>> +static int cfg_index(int busnr, int devfn, int reg)
>> +{
>> + return ((PCI_SLOT(devfn) & 0x1f) << PCIE_SLOT_SHIFT)
>> + | ((PCI_FUNC(devfn) & 0x07) << PCIE_FUNC_SHIFT)
>> + | (busnr << PCIE_BUSNUM_SHIFT)
>> + | (reg & ~3);
>> +}
>> +
>> +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
>> +{
>> + void __iomem *base = pcie->base;
>> + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
>> +
>> + return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
>> +}
>> +
>> +static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
>> +{
>> + void __iomem *base = pcie->base;
>> + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
>> + u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
>> + u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
>> +
>> + return (dla && plu) ? true : false;
>> +}
>> +
>> +static bool brcm_pcie_valid_device(struct brcm_pcie *pcie, struct pci_bus *bus,
>> + int dev)
>> +{
>> + if (pci_is_root_bus(bus)) {
>> + if (dev > 0)
>> + return false;
>> + } else {
>> + /* If there is no link, then there is no device */
>> + if (!brcm_pcie_link_up(pcie))
>> + return false;
>
> This is racy, since the link can go down after you check but before
> you do the config access. I assume your hardware can deal with a
> config access that targets a link that is down?
Yes, that can happen but there is really nothing that can be done if
the link goes down in that vulnerability window. What do you suggest
doing?
>
>> + }
>> +
>> + return true;
>> +}
>> +
>> +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
>> + int where)
>> +{
>> + struct brcm_pcie *pcie = bus->sysdata;
>> + void __iomem *base = pcie->base;
>> + int idx;
>> +
>> + if (!brcm_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
>> + return NULL;
>> +
>> + /* Accesses to the RC go right to the RC registers */
>> + if (pci_is_root_bus(bus))
>> + return base + where;
>> +
>> + /* For devices, write to the config space index register */
>> + idx = cfg_index(bus->number, devfn, where);
>> + bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
>> + return base + DATA_ADDR(pcie) + (where & 0x3);
>
> I guess this is protected by a higher-level config access lock?
>
>> +}
>> +
>> +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
>> + unsigned int val)
>> +{
>> + unsigned int offset;
>> + unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
>> + u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
>> +
>> + if (pcie->type != BCM7278) {
>> + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift,
>> + val);
>> + } else if (of_machine_is_compatible("brcm,bcm7278a0")) {
>> + /*
>> + * The two PCIe instances on 7278a0 are not even consistent with
>> + * respect to each other for internal offsets, here we offset
>> + * by 0x14000 + RGR1_SW_INIT_1's relative offset to account for
>> + * that.
>> + */
>> + offset = pcie->id ? 0x14010 : pcie->reg_offsets[RGR1_SW_INIT_1];
>> + wr_fld_rb(pcie->base + offset, mask, shift, val);
>> + } else {
>> + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift,
>> + val);
>> + }
>> +}
>> +
>> +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
>> + unsigned int val)
>> +{
>> + if (pcie->type != BCM7278)
>> + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
>> + PCIE_RGR1_SW_INIT_1_PERST_MASK,
>> + PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
>> + else
>> + /* Assert = 0, de-assert = 1 on 7278 */
>> + WR_FLD_RB(pcie->base, PCIE_MISC_PCIE_CTRL, PCIE_PERSTB, !val);
>> +}
>> +
>> +static int brcm_pcie_add_controller(struct brcm_pcie *pcie)
>> +{
>> + mutex_lock(&brcm_pcie_lock);
>> + list_add_tail(&pcie->list, &brcm_pcie);
>> + mutex_unlock(&brcm_pcie_lock);
>> +
>> + return 0;
>> +}
>> +
>> +static void brcm_pcie_remove_controller(struct brcm_pcie *pcie)
>> +{
>> + struct list_head *pos, *q;
>> + struct brcm_pcie *tmp;
>> +
>> + mutex_lock(&brcm_pcie_lock);
>> + list_for_each_safe(pos, q, &brcm_pcie) {
>> + tmp = list_entry(pos, struct brcm_pcie, list);
>> + if (tmp == pcie) {
>> + list_del(pos);
>> + if (list_empty(&brcm_pcie))
>> + num_memc = 0;
>> + break;
>> + }
>> + }
>> + mutex_unlock(&brcm_pcie_lock);
>
> I'm missing something. I don't see that num_memc is ever set to
> anything *other* than zero.
The num_memc is set and used in the dma commit. I will remove its
declaration from this commit.
> This pattern of keeping a list of controllers is highly unusual and
> needs some explanation.
I think I can remove the list but still need brcm_pcie_lock.
>
>> +}
>> +
>> +static int brcm_pcie_parse_request_of_pci_ranges(struct brcm_pcie *pcie)
>> +{
>> + struct resource_entry *win;
>> + int ret;
>> +
>> + ret = of_pci_get_host_bridge_resources(pcie->dn, 0, 0xff,
>> + &pcie->resources, NULL);
>> + if (ret) {
>> + dev_err(pcie->dev, "failed to get host resources\n");
>> + return ret;
>> + }
>> +
>> + resource_list_for_each_entry(win, &pcie->resources) {
>> + struct resource *parent, *res = win->res;
>> + dma_addr_t offset = (dma_addr_t)win->offset;
>> +
>> + if (resource_type(res) == IORESOURCE_IO) {
>> + parent = &ioport_resource;
>> + } else if (resource_type(res) == IORESOURCE_MEM) {
>> + if (pcie->num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
>> + dev_err(pcie->dev, "too many outbound wins\n");
>> + return -EINVAL;
>> + }
>> + pcie->out_wins[pcie->num_out_wins].cpu_addr
>> + = (phys_addr_t)res->start;
>> + pcie->out_wins[pcie->num_out_wins].pcie_addr
>> + = (dma_addr_t)(res->start
>> + - (phys_addr_t)offset);
>> + pcie->out_wins[pcie->num_out_wins].size
>> + = (dma_addr_t)(res->end - res->start + 1);
>> + pcie->num_out_wins++;
>> + parent = &iomem_resource;
>> + } else {
>> + continue;
>> + }
>> +
>> + ret = devm_request_resource(pcie->dev, parent, res);
>> + if (ret) {
>> + dev_err(pcie->dev, "failed to get res %pR\n", res);
>> + return ret;
>> + }
>> + }
>> + return 0;
>> +}
>> +
>> +static int brcm_pcie_setup(struct brcm_pcie *pcie)
>> +{
>> + void __iomem *base = pcie->base;
>> + unsigned int scb_size_val;
>> + u64 rc_bar2_size = 0, rc_bar2_offset = 0, total_mem_size = 0;
>
> Unnecessary initializations (at least of rc_bar2_size, I didn't check
> the rest).
>
> Add
>
> struct device *dev = pcie->dev;
>
> then use it below.
>
>> + u32 tmp, burst;
>> + int i, j, ret, limit;
>> + u16 nlw, cls, lnksta;
>> + bool ssc_good = false;
>> +
>> + /* reset the bridge and the endpoint device */
>> + /* field: PCIE_BRIDGE_SW_INIT = 1 */
>
> Not sure what these "field: ..." comments mean. Are they for some
> automated tool? To a human, it looks like they repeat what the code
> does.
>
>> + brcm_pcie_bridge_sw_init_set(pcie, 1);
>> +
>> + /* field: PCIE_SW_PERST = 1, on 7278, we start de-asserted already */
>> + if (pcie->type != BCM7278)
>> + brcm_pcie_perst_set(pcie, 1);
>> +
>> + usleep_range(100, 200);
>> +
>> + /* take the bridge out of reset */
>> + /* field: PCIE_BRIDGE_SW_INIT = 0 */
>> + brcm_pcie_bridge_sw_init_set(pcie, 0);
>> +
>> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
>> + /* wait for serdes to be stable */
>> + usleep_range(100, 200);
>> +
>> + /* Grab the PCIe hw revision number */
>> + tmp = bcm_readl(base + PCIE_MISC_REVISION);
>> + pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
>> +
>> + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
>> + tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
>> + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
>> + burst = (pcie->type == GENERIC || pcie->type == BCM7278)
>> + ? BURST_SIZE_512 : BURST_SIZE_256;
>> + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE, burst);
>> + bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
>> +
>> + /*
>> + * Set up inbound memory view for the EP (called RC_BAR2,
>> + * not to be confused with the BARs that are advertised by
>> + * the EP).
>> + */
>> + for (i = 0; i < num_memc; i++)
>> + total_mem_size += scb_size[i];
>> +
>> + /*
>> + * The PCIe host controller by design must set the inbound
>> + * viewport to be a contiguous arrangement of all of the
>> + * system's memory. In addition, its size mut be a power of
>> + * two. To further complicate matters, the viewport must
>> + * start on a pcie-address that is aligned on a multiple of its
>> + * size. If a portion of the viewport does not represent
>> + * system memory -- e.g. 3GB of memory requires a 4GB viewport
>> + * -- we can map the outbound memory in or after 3GB and even
>> + * though the viewport will overlap the outbound memory the
>> + * controller will know to send outbound memory downstream and
>> + * everything else upstream.
>> + */
>> + rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
>> +
>> + /*
>> + * Set simple configuration based on memory sizes
>> + * only. We always start the viewport at address 0.
>> + */
>> + rc_bar2_offset = 0;
>> +
>> + tmp = lower_32_bits(rc_bar2_offset);
>> + tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
>> + encode_ibar_size(rc_bar2_size));
>> + bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
>> + bcm_writel(upper_32_bits(rc_bar2_offset),
>> + base + PCIE_MISC_RC_BAR2_CONFIG_HI);
>> +
>> + /* field: SCB0_SIZE, default = 0xf (1 GB) */
>> + scb_size_val = scb_size[0]
>> + ? ilog2(scb_size[0]) - 15 : 0xf;
>> + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
>> +
>> + /* field: SCB1_SIZE, default = 0xf (1 GB) */
>> + if (num_memc > 1) {
>> + scb_size_val = scb_size[1]
>> + ? ilog2(scb_size[1]) - 15 : 0xf;
>> + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB1_SIZE, scb_size_val);
>> + }
>> +
>> + /* field: SCB2_SIZE, default = 0xf (1 GB) */
>> + if (num_memc > 2) {
>> + scb_size_val = scb_size[2]
>> + ? ilog2(scb_size[2]) - 15 : 0xf;
>> + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB2_SIZE, scb_size_val);
>> + }
>> +
>> + /* disable the PCIe->GISB memory window (RC_BAR1) */
>> + WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
>> +
>> + /* disable the PCIe->SCB memory window (RC_BAR3) */
>> + WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
>> +
>> + if (!pcie->suspended) {
>> + /* clear any interrupts we find on boot */
>> + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
>> + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
>> + }
>> +
>> + /* Mask all interrupts since we are not handling any yet */
>> + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
>> + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
>> +
>> + if (pcie->gen)
>> + set_gen(base, pcie->gen);
>> +
>> + /* take the EP device out of reset */
>> + /* field: PCIE_SW_PERST = 0 */
>> + brcm_pcie_perst_set(pcie, 0);
>
> <raises eyebrows> Take the *EP* out of reset? The host controller
> driver shouldn't be touching an EP directly. Maybe the comment
> doesn't match what the code actually does.
>
>> +
>> + /*
>> + * Give the RC/EP time to wake up, before trying to configure RC.
>> + * Intermittently check status for link-up, up to a total of 100ms
>> + * when we don't know if the device is there, and up to 1000ms if
>> + * we do know the device is there.
>> + */
>> + limit = pcie->suspended ? 1000 : 100;
>> + for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie);
>> + j += i, i = i * 2)
>> + msleep(i + j > limit ? limit - j : i);
>> +
>> + if (!brcm_pcie_link_up(pcie)) {
>> + dev_info(pcie->dev, "link down\n");
>> + return -ENODEV;
>> + }
>> +
>> + if (!brcm_pcie_rc_mode(pcie)) {
>> + dev_err(pcie->dev, "PCIe misconfigured; is in EP mode\n");
>> + return -EINVAL;
>> + }
>> +
>> + for (i = 0; i < pcie->num_out_wins; i++)
>> + brcm_pcie_set_outbound_win(pcie, i, pcie->out_wins[i].cpu_addr,
>> + pcie->out_wins[i].pcie_addr,
>> + pcie->out_wins[i].size);
>> +
>> + /*
>> + * For config space accesses on the RC, show the right class for
>> + * a PCIe-PCIe bridge (the default setting is to be EP mode).
>> + */
>> + WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
>> +
>> + if (pcie->ssc) {
>> + ret = set_ssc(base);
>> + if (ret == 0)
>> + ssc_good = true;
>> + else
>> + dev_err(pcie->dev,
>> + "failed attempt to enter ssc mode\n");
>> + }
>> +
>> + lnksta = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
>> + cls = lnksta & PCI_EXP_LNKSTA_CLS;
>> + nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
>> + dev_info(pcie->dev, "link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
>> + nlw, ssc_good ? "(SSC)" : "(!SSC)");
>> +
>> + /* PCIe->SCB endian mode for BAR */
>> + /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
>> + WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
>> + ENDIAN_MODE_BAR2, DATA_ENDIAN);
>> +
>> + /*
>> + * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
>> + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
>> + */
>> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
>> +
>> + return 0;
>> +}
>> +
>> +static void enter_l23(struct brcm_pcie *pcie)
>> +{
>> + void __iomem *base = pcie->base;
>> + int tries, l23;
>> +
>> + /* assert request for L23 */
>> + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
>> + /* poll L23 status */
>> + for (tries = 0, l23 = 0; tries < 1000 && !l23; tries++)
>> + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
>> + if (!l23)
>> + dev_err(pcie->dev, "failed to enter L23\n");
>
> What does "L23" mean? Some power management thing?
>
Yes, it is a low power link state. I will add a comment.
>> +}
>> +
>> +static void turn_off(struct brcm_pcie *pcie)
>> +{
>> + void __iomem *base = pcie->base;
>> +
>> + if (brcm_pcie_link_up(pcie))
>> + enter_l23(pcie);
>> + /* Reset endpoint device */
>> + brcm_pcie_perst_set(pcie, 1);
>> + /* deassert request for L23 in case it was asserted */
>> + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
>> + /* SERDES_IDDQ = 1 */
>> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
>> + /* Shutdown PCIe bridge */
>> + brcm_pcie_bridge_sw_init_set(pcie, 1);
>> +}
>> +
>> +static int brcm_pcie_suspend(struct device *dev)
>> +{
>> + struct brcm_pcie *pcie = dev_get_drvdata(dev);
>> +
>> + turn_off(pcie);
>> + clk_disable_unprepare(pcie->clk);
>> + pcie->suspended = true;
>> +
>> + return 0;
>> +}
>> +
>> +static int brcm_pcie_resume(struct device *dev)
>> +{
>> + struct brcm_pcie *pcie = dev_get_drvdata(dev);
>> + void __iomem *base;
>> + int ret;
>> +
>> + base = pcie->base;
>> + clk_prepare_enable(pcie->clk);
>> +
>> + /* Take bridge out of reset so we can access the SERDES reg */
>
> Some comments above and below spell it "serdes"; here you spell it
> "SERDES".
>
>> + brcm_pcie_bridge_sw_init_set(pcie, 0);
>> +
>> + /* SERDES_IDDQ = 0 */
>> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
>> + /* wait for serdes to be stable */
>> + usleep_range(100, 200);
>> +
>> + ret = brcm_pcie_setup(pcie);
>> + if (ret)
>> + return ret;
>> +
>> + pcie->suspended = false;
>> +
>> + return 0;
>> +}
>> +
>> +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
>> +{
>> + turn_off(pcie);
>> + clk_disable_unprepare(pcie->clk);
>> + clk_put(pcie->clk);
>> + brcm_pcie_remove_controller(pcie);
>> +}
>> +
>> +static int brcm_pcie_remove(struct platform_device *pdev)
>> +{
>> + struct brcm_pcie *pcie = platform_get_drvdata(pdev);
>> +
>> + pci_stop_root_bus(pcie->root_bus);
>> + pci_remove_root_bus(pcie->root_bus);
>> + _brcm_pcie_remove(pcie);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id brcm_pcie_match[] = {
>> + { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
>> + { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
>> + { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
>> + { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, brcm_pcie_match);
>> +
>> +static int brcm_pcie_probe(struct platform_device *pdev)
>> +{
>> + struct device_node *dn = pdev->dev.of_node;
>> + const struct of_device_id *of_id;
>> + const struct pcie_cfg_data *data;
>> + int ret;
>> + struct brcm_pcie *pcie;
>> + struct resource *res;
>> + void __iomem *base;
>> + u32 tmp;
>> + struct pci_host_bridge *bridge;
>> + struct pci_bus *child;
>> +
>> + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
>> + if (!bridge)
>> + return -ENOMEM;
>> +
>> + pcie = pci_host_bridge_priv(bridge);
>> + INIT_LIST_HEAD(&pcie->resources);
>> +
>> + of_id = of_match_node(brcm_pcie_match, dn);
>> + if (!of_id) {
>> + dev_err(&pdev->dev, "failed to look up compatible string\n");
>> + return -EINVAL;
>> + }
>> +
>> + if (of_property_read_u32(dn, "dma-ranges", &tmp) == 0) {
>> + dev_err(&pdev->dev, "cannot yet handle dma-ranges\n");
>> + return -EINVAL;
>> + }
>> +
>> + data = of_id->data;
>> + pcie->reg_offsets = data->offsets;
>> + pcie->reg_field_info = data->reg_field_info;
>> + pcie->type = data->type;
>> + pcie->dn = dn;
>> + pcie->dev = &pdev->dev;
>> +
>> + pcie->id = of_get_pci_domain_nr(dn);
>
> Why do you call of_get_pci_domain_nr() directly? No other driver
> does.
We use the domain as the controller number (id). We use the id to
identify and fix a HW bug that only affects the 2nd controller; see
the clause
" } else if (of_machine_is_compatible("brcm,bcm7278a0")) {".
>
>> + if (pcie->id < 0)
>> + return pcie->id;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + if (!res)
>> + return -EINVAL;
>> +
>> + base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(base))
>> + return PTR_ERR(base);
>> +
>> + pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
>> + if (IS_ERR(pcie->clk)) {
>> + dev_err(&pdev->dev, "could not get clock\n");
>> + pcie->clk = NULL;
>> + }
>> + pcie->base = base;
>> +
>> + ret = of_pci_get_max_link_speed(dn);
>> + pcie->gen = (ret < 0) ? 0 : ret;
>> +
>> + pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
>> +
>> + ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
>> + if (ret == 0)
>> + /* keep going, as we don't use this intr yet */
>> + dev_warn(pcie->dev, "cannot get pcie interrupt\n");
>> + else
>> + pcie->irq = ret;
>> +
>> + ret = brcm_pcie_parse_request_of_pci_ranges(pcie);
>> + if (ret)
>> + return ret;
>> +
>> + ret = clk_prepare_enable(pcie->clk);
>> + if (ret) {
>> + dev_err(&pdev->dev, "could not enable clock\n");
>> + return ret;
>> + }
>> +
>> + ret = brcm_pcie_add_controller(pcie);
>> + if (ret)
>> + return ret;
>> +
>> + ret = brcm_pcie_setup(pcie);
>> + if (ret)
>> + goto fail;
>> +
>> + list_splice_init(&pcie->resources, &bridge->windows);
>> + bridge->dev.parent = &pdev->dev;
>> + bridge->busnr = 0;
>> + bridge->ops = &brcm_pcie_ops;
>> + bridge->sysdata = pcie;
>> + bridge->map_irq = of_irq_parse_and_map_pci;
>> + bridge->swizzle_irq = pci_common_swizzle;
>> +
>> + ret = pci_scan_root_bus_bridge(bridge);
>> + if (ret < 0) {
>> + dev_err(pcie->dev, "Scanning root bridge failed");
>> + goto fail;
>> + }
>> +
>> + pci_assign_unassigned_bus_resources(bridge->bus);
>> + list_for_each_entry(child, &bridge->bus->children, node)
>> + pcie_bus_configure_settings(child);
>> + pci_bus_add_devices(bridge->bus);
>> + platform_set_drvdata(pdev, pcie);
>> + pcie->root_bus = bridge->bus;
>> +
>> + return 0;
>> +
>> +fail:
>> + _brcm_pcie_remove(pcie);
>> + return ret;
>> +}
>> +
>> +static const struct dev_pm_ops brcm_pcie_pm_ops = {
>> + .suspend_noirq = brcm_pcie_suspend,
>> + .resume_noirq = brcm_pcie_resume,
>> +};
>> +
>> +static struct platform_driver __refdata brcm_pcie_driver = {
>
> Why do you need __refdata? There's only only other occurrence in
> drivers/pci, and I'm dubious about that one as well.
>
>> + .probe = brcm_pcie_probe,
>> + .remove = brcm_pcie_remove,
>> + .driver = {
>> + .name = "brcm-pcie",
>> + .owner = THIS_MODULE,
>> + .of_match_table = brcm_pcie_match,
>> + .pm = &brcm_pcie_pm_ops,
>> + },
>> +};
>> +
>> +module_platform_driver(brcm_pcie_driver);
>> +
>> +MODULE_LICENSE("GPL");
>
> Copyright notice above says "GPL v2", which is not the same as the
> "GPL" here.
>
>> +MODULE_DESCRIPTION("Broadcom STB PCIE RC driver");
>> +MODULE_AUTHOR("Broadcom");
>> --
>> 1.9.0.138.g2de3478
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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^ permalink raw reply
* Re: [PATCH v4 3/5] media: i2c: Add TDA1997x HDMI receiver driver
From: Tim Harvey @ 2017-12-13 23:35 UTC (permalink / raw)
To: Hans Verkuil
Cc: devicetree@vger.kernel.org, alsa-devel,
linux-kernel@vger.kernel.org, Hans Verkuil, Mauro Carvalho Chehab,
Philipp Zabel, Steve Longerbeam, Shawn Guo, linux-media
In-Reply-To: <CAJ+vNU0NKZizung9+1zsd1RZBrDbBgk+A8mVJ76bQysjCUoaKw@mail.gmail.com>
On Mon, Dec 4, 2017 at 9:30 AM, Tim Harvey <tharvey@gateworks.com> wrote:
> On Mon, Dec 4, 2017 at 4:50 AM, Hans Verkuil <hverkuil@xs4all.nl> wrote:
>> Hi Tim,
>>
>> Found a few more small issues. After that's fixed and you have the Ack for the
>> bindings this can be merged I think.
>
> Hans,
>
> Thanks. Can you weigh in on the bindings? Rob was hoping for some
> discussion on making some generic bus format types for video and I'm
> not familiar with the other video encoders/decoders enough to know if
> there is enough commonality.
>
>>
>> On 11/29/2017 10:19 PM, Tim Harvey wrote:
> <snip>
>>> +
>>> +/* parse an infoframe and do some sanity checks on it */
>>> +static unsigned int
>>> +tda1997x_parse_infoframe(struct tda1997x_state *state, u16 addr)
>>> +{
>>> + struct v4l2_subdev *sd = &state->sd;
>>> + union hdmi_infoframe frame;
>>> + u8 buffer[40];
>>> + u8 reg;
>>> + int len, err;
>>> +
>>> + /* read data */
>>> + len = io_readn(sd, addr, sizeof(buffer), buffer);
>>> + err = hdmi_infoframe_unpack(&frame, buffer);
>>> + if (err) {
>>> + v4l_err(state->client,
>>> + "failed parsing %d byte infoframe: 0x%04x/0x%02x\n",
>>> + len, addr, buffer[0]);
>>> + return err;
>>> + }
>>> + hdmi_infoframe_log(KERN_INFO, &state->client->dev, &frame);
>>> + switch (frame.any.type) {
>>> + /* Audio InfoFrame: see HDMI spec 8.2.2 */
>>> + case HDMI_INFOFRAME_TYPE_AUDIO:
>>> + /* sample rate */
>>> + switch (frame.audio.sample_frequency) {
>>> + case HDMI_AUDIO_SAMPLE_FREQUENCY_32000:
>>> + state->audio_samplerate = 32000;
>>> + break;
>>> + case HDMI_AUDIO_SAMPLE_FREQUENCY_44100:
>>> + state->audio_samplerate = 44100;
>>> + break;
>>> + case HDMI_AUDIO_SAMPLE_FREQUENCY_48000:
>>> + state->audio_samplerate = 48000;
>>> + break;
>>> + case HDMI_AUDIO_SAMPLE_FREQUENCY_88200:
>>> + state->audio_samplerate = 88200;
>>> + break;
>>> + case HDMI_AUDIO_SAMPLE_FREQUENCY_96000:
>>> + state->audio_samplerate = 96000;
>>> + break;
>>> + case HDMI_AUDIO_SAMPLE_FREQUENCY_176400:
>>> + state->audio_samplerate = 176400;
>>> + break;
>>> + case HDMI_AUDIO_SAMPLE_FREQUENCY_192000:
>>> + state->audio_samplerate = 192000;
>>> + break;
>>> + default:
>>> + case HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM:
>>> + break;
>>> + }
>>> +
>>> + /* sample size */
>>> + switch (frame.audio.sample_size) {
>>> + case HDMI_AUDIO_SAMPLE_SIZE_16:
>>> + state->audio_samplesize = 16;
>>> + break;
>>> + case HDMI_AUDIO_SAMPLE_SIZE_20:
>>> + state->audio_samplesize = 20;
>>> + break;
>>> + case HDMI_AUDIO_SAMPLE_SIZE_24:
>>> + state->audio_samplesize = 24;
>>> + break;
>>> + case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
>>> + default:
>>> + break;
>>> + }
>>> +
>>> + /* Channel Count */
>>> + state->audio_channels = frame.audio.channels;
>>> + if (frame.audio.channel_allocation &&
>>> + frame.audio.channel_allocation != state->audio_ch_alloc) {
>>> + /* use the channel assignment from the infoframe */
>>> + state->audio_ch_alloc = frame.audio.channel_allocation;
>>> + tda1997x_configure_audout(sd, state->audio_ch_alloc);
>>> + /* reset the audio FIFO */
>>> + tda1997x_hdmi_info_reset(sd, RESET_AUDIO, false);
>>> + }
>>> + break;
>>> +
>>> + /* Auxiliary Video information (AVI) InfoFrame: see HDMI spec 8.2.1 */
>>> + case HDMI_INFOFRAME_TYPE_AVI:
>>> + state->colorspace = frame.avi.colorspace;
>>> + state->colorimetry = frame.avi.colorimetry;
>>> + state->content = frame.avi.content_type;
>>> + /* Quantization Range */
>>> + switch (state->rgb_quantization_range) {
>>> + case V4L2_DV_RGB_RANGE_AUTO:
>>> + state->range = frame.avi.quantization_range;
>>> + break;
>>> + case V4L2_DV_RGB_RANGE_LIMITED:
>>> + state->range = HDMI_QUANTIZATION_RANGE_LIMITED;
>>> + break;
>>> + case V4L2_DV_RGB_RANGE_FULL:
>>> + state->range = HDMI_QUANTIZATION_RANGE_FULL;
>>> + break;
>>> + }
>>> + if (state->range == HDMI_QUANTIZATION_RANGE_DEFAULT) {
>>> + if (frame.avi.video_code <= 1)
>>> + state->range = HDMI_QUANTIZATION_RANGE_FULL;
>>> + else
>>> + state->range = HDMI_QUANTIZATION_RANGE_LIMITED;
>>> + }
>>> + /*
>>> + * If colorimetry not specified, conversion depends on res type:
>>> + * - SDTV: ITU601 for SD (480/576/240/288 line resolution)
>>> + * - HDTV: ITU709 for HD (720/1080 line resolution)
>>> + * - PC: sRGB
>>> + * see HDMI specification section 6.7
>>> + */
>>> + if ((state->colorspace == HDMI_COLORSPACE_YUV422 ||
>>> + state->colorspace == HDMI_COLORSPACE_YUV444) &&
>>> + (state->colorimetry == HDMI_COLORIMETRY_EXTENDED ||
>>> + state->colorimetry == HDMI_COLORIMETRY_NONE)) {
>>> + if (is_sd(state->timings.bt.height))
>>> + state->colorimetry = HDMI_COLORIMETRY_ITU_601;
>>> + else if (is_hd(state->timings.bt.height))
>>> + state->colorimetry = HDMI_COLORIMETRY_ITU_709;
>>> + else
>>> + state->colorimetry = HDMI_COLORIMETRY_NONE;
>>> + }
>>> + v4l_dbg(1, debug, state->client,
>>> + "colorspace=%d colorimetry=%d range=%d content=%d\n",
>>> + state->colorspace, state->colorimetry, state->range,
>>> + state->content);
>>> +
>>> + /* configure upsampler: 0=bypass 1=repeatchroma 2=interpolate */
>>> + reg = io_read(sd, REG_PIX_REPEAT);
>>> + reg &= ~PIX_REPEAT_MASK_UP_SEL;
>>> + if (state->colorspace == HDMI_COLORSPACE_YUV422)
>>> + reg |= (PIX_REPEAT_CHROMA << PIX_REPEAT_SHIFT);
>>> + io_write(sd, REG_PIX_REPEAT, reg);
>>> +
>>> + /* ConfigurePixelRepeater: repeat n-times each pixel */
>>> + reg = io_read(sd, REG_PIX_REPEAT);
>>> + reg &= ~PIX_REPEAT_MASK_REP;
>>> + reg |= frame.avi.pixel_repeat;
>>> + io_write(sd, REG_PIX_REPEAT, reg);
>>> +
>>> + /* configure the receiver with the new colorspace */
>>> + tda1997x_configure_csc(sd);
>>> + break;
>>> + default:
>>> + break;
>>> + }
>>> + return 0;
>>> +}
>>> +
> <snip>
>>> +
>>> +static int tda1997x_fill_format(struct tda1997x_state *state,
>>> + struct v4l2_mbus_framefmt *format)
>>> +{
>>> + const struct v4l2_bt_timings *bt;
>>> +
>>> + v4l_dbg(1, debug, state->client, "%s\n", __func__);
>>> +
>>> + if (!state->detected_timings)
>>> + return -EINVAL;
>>> + bt = &state->detected_timings->bt;
>>> + memset(format, 0, sizeof(*format));
>>> +
>>> + format->width = bt->width;
>>> + format->height = bt->height;
>>> + format->field = V4L2_FIELD_NONE;
>>> + format->colorspace = V4L2_COLORSPACE_SRGB;
>>> + if (bt->flags & V4L2_DV_FL_IS_CE_VIDEO)
>>> + format->colorspace = (bt->height <= 576) ?
>>> + V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
>>
>> Close. What is missing is a check of the AVI InfoFrame: if it has an explicit
>> colorimetry then use that. E.g. check for HDMI_COLORIMETRY_ITU_601 or ITU_709
>> and set the colorspace accordingly. Otherwise fall back to what you have here.
>>
>
> This function currently matches adv7604/adv7842 where they don't look
> at colorimetry (but I do see a TODO in adv748x_hdmi_fill_format to
> look at this) so I don't have an example and may not understand.
>
> Do you mean:
>
> format->colorspace = V4L2_COLORSPACE_SRGB;
> if (bt->flags & V4L2_DV_FL_IS_CE_VIDEO) {
> if ((state->colorimetry == HDMI_COLORIMETRY_ITU_601) ||
> (state->colorimetry == HDMI_COLORIMETRY_ITU_709))
> format->colorspace = state->colorspace;
> else
> format->colorspace = is_sd(bt->height) ?
> V4L2_COLORSPACE_SMPTE170M :
> V4L2_COLORSPACE_REC709;
> }
>
> Also during more testing I've found that I'm not capturing interlaced
> properly and know I at least need:
>
> - format->field = V4L2_FIELD_NONE;
> + format->field = (bt->interlaced) ?
> + V4L2_FIELD_ALTERNATE : V4L2_FIELD_NONE;
>
> I'm still not quite capturing interlaced yet but I think its an issue
> of setting up the media pipeline improperly.
>
Hans,
Did you see this question above? I'm not quite understanding what you
want me to do for filling in colorspace and don't see any examples in
the existing drivers that appear to look at colorimetry for this.
Regards,
Tim
^ permalink raw reply
* Re: [PATCH 3/5] media: i2c: Add TDA1997x HDMI receiver driver
From: Tim Harvey @ 2017-12-13 23:33 UTC (permalink / raw)
To: Hans Verkuil
Cc: Rob Herring, linux-media, alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Shawn Guo,
Steve Longerbeam, Philipp Zabel, Hans Verkuil,
Mauro Carvalho Chehab
In-Reply-To: <f1d607e2-3d21-ac05-c815-a5f28b860b1e-qWit8jRvyhVmR6Xm/wNWPw@public.gmane.org>
On Tue, Dec 12, 2017 at 4:18 AM, Hans Verkuil <hverkuil-qWit8jRvyhVmR6Xm/wNWPw@public.gmane.org> wrote:
> Hi Tim,
>
> Sorry for the delay, I needed to find some time to think about this.
>
> On 11/16/17 05:30, Rob Herring wrote:
>> On Wed, Nov 15, 2017 at 10:31:14AM -0800, Tim Harvey wrote:
>>> On Wed, Nov 15, 2017 at 7:52 AM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
>>>> On Thu, Nov 09, 2017 at 10:45:34AM -0800, Tim Harvey wrote:
>>>>> Add support for the TDA1997x HDMI receivers.
>>>>>
>>>>> Cc: Hans Verkuil <hverkuil-qWit8jRvyhVmR6Xm/wNWPw@public.gmane.org>
>>>>> Signed-off-by: Tim Harvey <tharvey-UMMOYl/HMS+akBO8gow8eQ@public.gmane.org>
>>>>> ---
>>>>> v3:
>>>>> - use V4L2_DV_BT_FRAME_WIDTH/HEIGHT macros
>>>>> - fixed missing break
>>>>> - use only hdmi_infoframe_log for infoframe logging
>>>>> - simplify tda1997x_s_stream error handling
>>>>> - add delayed work proc to handle hotplug enable/disable
>>>>> - fix set_edid (disable HPD before writing, enable after)
>>>>> - remove enabling edid by default
>>>>> - initialize timings
>>>>> - take quant range into account in colorspace conversion
>>>>> - remove vendor/product tracking (we provide this in log_status via infoframes)
>>>>> - add v4l_controls
>>>>> - add more detail to log_status
>>>>> - calculate vhref generator timings
>>>>> - timing detection fixes (rounding errors, hswidth errors)
>>>>> - rename configure_input/configure_conv functions
>>>>>
>>>>> v2:
>>>>> - implement dv timings enum/cap
>>>>> - remove deprecated g_mbus_config op
>>>>> - fix dv_query_timings
>>>>> - add EDID get/set handling
>>>>> - remove max-pixel-rate support
>>>>> - add audio codec DAI support
>>>>> - change audio bindings
>>>>> ---
>>>>> drivers/media/i2c/Kconfig | 9 +
>>>>> drivers/media/i2c/Makefile | 1 +
>>>>> drivers/media/i2c/tda1997x.c | 3485 ++++++++++++++++++++++++++++++++++
>>>>> include/dt-bindings/media/tda1997x.h | 78 +
>>>>
>>>> This belongs with the binding documentation patch.
>>>>
>>>
>>> Rob,
>>>
>>> Thanks - missed that. I will move it for v4.
>>>
>>> Regarding your previous comment to the v2 series:
>>>> The rest of the binding looks fine, but I have some reservations about
>>>> this. I think this should be common probably. There's been a few
>>>> bindings for display recently that deal with the interface format. Maybe
>>>> some vendor property is needed here to map a standard interface format
>>>> back to pin configuration.
>>>
>>> I take it this is not an 'Ack' for the bindings?
>>>
>>> Which did you feel should be made common? I admit I was surprised
>>> there wasn't a common binding for audio bus format (i2s|spdif) but if
>>> you were referring to the video data that would probably be much more
>>> complicated.
>>
>> The video data. Either you have to try to come up with some way to map
>> color components to signals/pins (and even cycles) or you just enumerate
>> the formats and keep adding to them when new ones appear. There's h/w
>> that allows the former, but in the end you have to interoperate, so
>> enumerating the formats is probably enough.
>>
>>> I was hoping one of the media/driver maintainers would respond to your
>>> comment with thoughts as I'm not familiar with a very wide variety of
>>> receivers.
>>
>> I am hoping, too.
>
> I don't think it is right to store this in the DT. How you map the output pins
> is a driver thing. So when you are requested to enumerate the mediabus formats
> (include/uapi/linux/media-bus-format.h) you support, you do so based on the
> capabilities of the hardware, and when a format is requested you program the
> hardware accordingly.
>
> The device tree should describe the physical characteristics like the number
> of pins that are hooked up (i.e. are there 24, 30 or 36 pins connected).
>
> These vidout-portcfg mappings do not appear to describe physical properties
> but really register settings.
Hans,
They are register settings that define which bits on the internal data
bus are mapped to which pins on the package. Internally these parts
have a 36bit video data bus but externally the tda19971 only has 24
pins and even then perhaps only 8 are hooked up if using BT656 and the
registers also define 'which 8' as it could have been connected to the
upper or lower part of the bus. So while the bindings from
video-interfaces.txt provide bus-width and details of the sync
signals, additional hardware-specific interconnect details such as how
the video bits are shifted/mixed on the output bus are needed here.
This is why I feel vidout-portcfg should be a dt property vs something
like a module param.
Regards,
Tim
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^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: chosen: Add clocksource and clockevent selection
From: Rob Herring @ 2017-12-13 22:57 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Daniel Lezcano, Nicolas Ferre, Mark Rutland, Thomas Gleixner,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <20171213185313.20017-2-alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On Wed, Dec 13, 2017 at 12:53 PM, Alexandre Belloni
<alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> The clocksource and clockevent timer are probed early in the boot process.
> At that time it is difficult for linux to know whether a particular timer
> can be used as the clocksource or the clockevent or by another driver,
> especially when they are all identical or have similar features.
If all identical, then it shouldn't matter. "similar" means some
difference. Describe those differences.
> Until now, multiple strategies have been used to solve that:
> - use Kconfig option as MXC_USE_EPIT or ATMEL_TCB_CLKSRC_BLOCK
Compile time probably means only one option is really used.
> - use a kernel parameter as the "clocksource" early_param in mach-omap2
Yeah, OMAP was one of the previous times this came up and also
attempted something like this. This parameter predates selecting
timers based on features described in DT. Look at commit
2eb03937df3ebc (ARM: OMAP3: Update clocksource timer selection).
> - registering the first seen timer as a clockevent and the second one as
> a clocksource as in rk_timer_init or dw_apb_timer_init
>
> Add a linux,clocksource and a linux,clockevent node in chosen with a timer
> property pointing to the timer to use. Other properties, like the targeted
> precision may be added later.
Open ended expansion of this does not help convince me it is needed.
Rob
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^ permalink raw reply
* Re: [PATCH] dts: Remove leading 0x and 0s from bindings notation
From: Rob Herring @ 2017-12-13 21:56 UTC (permalink / raw)
To: Mathieu Malaterre
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
David Daney
In-Reply-To: <20171213210701.13311-1-malat@debian.org>
On Wed, Dec 13, 2017 at 3:07 PM, Mathieu Malaterre <malat@debian.org> wrote:
> Improve the DTS files by removing all the leading "0x" and zeros to fix the
> following dtc warnings:
>
> Warning (unit_address_format): Node /XXX unit name should not have leading "0x"
>
> and
>
> Warning (unit_address_format): Node /XXX unit name should not have leading 0s
>
> Converted using the following command:
>
> find . -type f \( -iname *.dts -o -iname *.dtsi \) -exec sed -E -i -e "s/@0x([0-9a-fA-F\.]+)[[:space:]]?\{/@\L\1 \{/g" -e "s/@0+([0-9a-fA-F\.]+)([[:space:]]?\{)/@\L\1 \{/g" {} +
>
> For simplicity, two sed expressions were used to solve each warnings separately.
>
> To make the regex expression more robust a few other issues were resolved,
> namely setting unit-address to lower case, and adding a whitespace before the
> the opening curly brace:
>
> https://elinux.org/Device_Tree_Linux#Linux_conventions
>
> This is a follow up to commit 4c9847b7375a ("dt-bindings: Remove leading 0x from bindings notation")
>
> Reported-by: David Daney <ddaney@caviumnetworks.com>
> Suggested-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Mathieu Malaterre <malat@debian.org>
> ---
> arch/arc/boot/dts/abilis_tb10x.dtsi | 4 +--
> arch/arc/boot/dts/axc001.dtsi | 6 ++---
> arch/arc/boot/dts/axc003.dtsi | 6 ++---
> arch/arc/boot/dts/axc003_idu.dtsi | 6 ++---
> arch/arc/boot/dts/axs10x_mb.dtsi | 22 ++++++++--------
> arch/arc/boot/dts/vdk_axc003.dtsi | 4 +--
> arch/arc/boot/dts/vdk_axc003_idu.dtsi | 4 +--
> arch/arc/boot/dts/vdk_axs10x_mb.dtsi | 14 +++++-----
> arch/arm/boot/dts/am3517.dtsi | 4 +--
> arch/arm/boot/dts/arm-realview-eb.dtsi | 18 ++++++-------
> arch/arm/boot/dts/arm-realview-pb1176.dts | 18 ++++++-------
> arch/arm/boot/dts/arm-realview-pb11mp.dts | 18 ++++++-------
> arch/arm/boot/dts/arm-realview-pbx.dtsi | 18 ++++++-------
> arch/arm/boot/dts/artpec6.dtsi | 2 +-
> arch/arm/boot/dts/at91sam9261.dtsi | 2 +-
> arch/arm/boot/dts/at91sam9261ek.dts | 2 +-
> arch/arm/boot/dts/at91sam9263.dtsi | 2 +-
> arch/arm/boot/dts/at91sam9263ek.dts | 2 +-
> arch/arm/boot/dts/at91sam9g25ek.dts | 2 +-
> arch/arm/boot/dts/at91sam9g45.dtsi | 2 +-
> arch/arm/boot/dts/at91sam9m10g45ek.dts | 2 +-
> arch/arm/boot/dts/atlas7.dtsi | 12 ++++-----
> arch/arm/boot/dts/bcm11351.dtsi | 2 +-
> arch/arm/boot/dts/bcm21664.dtsi | 2 +-
> arch/arm/boot/dts/bcm283x.dtsi | 2 +-
> arch/arm/boot/dts/da850-lcdk.dts | 4 +--
> arch/arm/boot/dts/dm8148-evm.dts | 8 +++---
> arch/arm/boot/dts/dm8168-evm.dts | 8 +++---
> arch/arm/boot/dts/dra62x-j5eco-evm.dts | 8 +++---
> arch/arm/boot/dts/exynos5420.dtsi | 36 +++++++++++++-------------
> arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 +-
> arch/arm/boot/dts/imx7d.dtsi | 2 +-
> arch/arm/boot/dts/keystone-k2e-netcp.dtsi | 2 +-
> arch/arm/boot/dts/keystone-k2hk-netcp.dtsi | 2 +-
> arch/arm/boot/dts/keystone-k2l-netcp.dtsi | 2 +-
> arch/arm/boot/dts/omap3-cm-t3x.dtsi | 8 +++---
> arch/arm/boot/dts/omap3-evm-37xx.dts | 8 +++---
> arch/arm/boot/dts/omap3-lilly-a83x.dtsi | 8 +++---
> arch/arm/boot/dts/s3c2416.dtsi | 2 +-
> arch/arm/boot/dts/sama5d3xmb.dtsi | 2 +-
> arch/arm/boot/dts/sama5d3xmb_cmp.dtsi | 2 +-
> arch/arm/boot/dts/socfpga.dtsi | 2 +-
> arch/arm/boot/dts/spear300.dtsi | 2 +-
> arch/arm/boot/dts/spear310.dtsi | 2 +-
> arch/arm/boot/dts/spear320.dtsi | 2 +-
> arch/arm/boot/dts/versatile-ab.dts | 16 ++++++------
> arch/arm/boot/dts/zx296702.dtsi | 20 +++++++-------
> arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 2 +-
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 6 ++---
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 ++---
> arch/c6x/boot/dts/dsk6455.dts | 2 +-
> arch/c6x/boot/dts/tms320c6455.dtsi | 2 +-
> arch/metag/boot/dts/tz1090.dtsi | 10 +++----
> arch/mips/boot/dts/img/boston.dts | 2 +-
> arch/mips/boot/dts/ingenic/ci20.dts | 8 +++---
> arch/nios2/boot/dts/3c120_devboard.dts | 16 ++++++------
> arch/powerpc/boot/dts/a3m071.dts | 10 +++----
> arch/powerpc/boot/dts/akebono.dts | 4 +--
> arch/powerpc/boot/dts/c2k.dts | 6 ++---
> arch/powerpc/boot/dts/currituck.dts | 2 +-
> arch/powerpc/boot/dts/fsl/mpc8568mds.dts | 12 ++++-----
> arch/powerpc/boot/dts/fsl/mpc8569mds.dts | 20 +++++++-------
> arch/powerpc/boot/dts/fsl/p1021mds.dts | 6 ++---
> arch/powerpc/boot/dts/fsl/p1025rdb.dtsi | 8 +++---
> arch/powerpc/boot/dts/fsl/p1025rdb_32b.dts | 2 +-
> arch/powerpc/boot/dts/fsl/p1025twr.dtsi | 8 +++---
> arch/powerpc/boot/dts/fsl/t1040rdb.dts | 2 +-
> arch/powerpc/boot/dts/fsl/t1042d4rdb.dts | 10 +++----
> arch/powerpc/boot/dts/fsl/t1042rdb.dts | 2 +-
> arch/powerpc/boot/dts/fsl/t104xrdb.dtsi | 6 ++---
> arch/powerpc/boot/dts/fsp2.dts | 6 ++---
> arch/powerpc/boot/dts/gamecube.dts | 14 +++++-----
> arch/powerpc/boot/dts/haleakala.dts | 2 +-
> arch/powerpc/boot/dts/kilauea.dts | 4 +--
> arch/powerpc/boot/dts/kmeter1.dts | 10 +++----
> arch/powerpc/boot/dts/makalu.dts | 4 +--
> arch/powerpc/boot/dts/mpc832x_mds.dts | 10 +++----
> arch/powerpc/boot/dts/mpc832x_rdb.dts | 8 +++---
> arch/powerpc/boot/dts/mpc836x_mds.dts | 8 +++---
> arch/powerpc/boot/dts/sbc8548-altflash.dts | 8 +++---
> arch/powerpc/boot/dts/sbc8548.dts | 8 +++---
> arch/powerpc/boot/dts/wii.dts | 32 +++++++++++------------
> arch/xtensa/boot/dts/csp.dts | 2 +-
> arch/xtensa/boot/dts/xtfpga-flash-128m.dtsi | 10 +++----
> arch/xtensa/boot/dts/xtfpga-flash-16m.dtsi | 10 +++----
> arch/xtensa/boot/dts/xtfpga-flash-4m.dtsi | 6 ++---
> arch/xtensa/boot/dts/xtfpga.dtsi | 10 +++----
> 88 files changed, 315 insertions(+), 315 deletions(-)
Thanks for doing this. It would be best to split this up by arch so
each arch maintainer can take each of their dts files. Otherwise,
looks good.
Rob
^ permalink raw reply
* Re: [PATCH] leds: as3645a: Fix checkpatch warnings
From: Laurent Pinchart @ 2017-12-13 21:32 UTC (permalink / raw)
To: Dan Murphy
Cc: Jacek Anaszewski, robh+dt, mark.rutland, rpurdie, pavel,
sakari.ailus, devicetree, linux-kernel, linux-leds
In-Reply-To: <799ae164-701a-87ce-fadf-8278f01c10d6@ti.com>
Hi Dan,
On Wednesday, 13 December 2017 22:49:38 EET Dan Murphy wrote:
> On 12/13/2017 02:43 PM, Jacek Anaszewski wrote:
> > On 12/13/2017 09:41 PM, Dan Murphy wrote:
> >> On 12/13/2017 02:29 PM, Jacek Anaszewski wrote:
> >>> Hi Dan,
> >>>
> >>> checkpatch.pl doesn't want to be mentioned in the patch subject :-)
> >>
> >> Ack
> >>
> >>> "WARNING: A patch subject line should describe the change not the tool
> >>> that found it"
> >>>
> >>> Preferably I'd see two separate patches.
> >>
> >> So you want me to split them up? I have no issue with that.
> >
> > Yeah, it will be easier to come up with concise but meaningful
> > subjects.
Well, given that one change splits a line that is too long and the other one
merges two lines that fit within the limit we could come up with a message
that covers both :-) This is nitpicking though, it doesn't matter much. I have
no issue with a patch that has some "while at it" portion anyway as long as
it's minor (I personally include white space fixes in patches that touch the
related code for instance).
> When I split these up can I add your Acked-by to each patch or would you
> prefer to resend your Acked-by for each patch?
Assuming you make no mistake, you can keep my ack :-) It will of course not
cover the commit message then.
> >>> Also, line length limit for the commit description is 75 characters.
> >>> Please use whole available space.
--
Regards,
Laurent Pinchart
^ permalink raw reply
* [PATCH] ARM: dts: am43xx: Fix inverted DS0_PULL_UP_DOWN_EN macro
From: Dave Gerlach @ 2017-12-13 21:24 UTC (permalink / raw)
To: Tony Lindgren
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Dave Gerlach
Due to a mistake in documentation the DS0_PULL_UP_DOWN_EN macro was
mistakenly defined as an active high bit, however setting the bit
actually disables the internal pull resistor on the pin, so correct this
macro and introduce a new DS0_PULL_UP_DOWN_DIS macro with the proper bit
value set now that the documentation has been updated.
Change based on AM437x Techninal Reference Manual SPRUHL7G Revised June
2017 Section 7.2.1.
Signed-off-by: Dave Gerlach <d-gerlach-l0cyMroinI0@public.gmane.org>
---
include/dt-bindings/pinctrl/am43xx.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h
index a69e310789c5..6ce4a32f77d4 100644
--- a/include/dt-bindings/pinctrl/am43xx.h
+++ b/include/dt-bindings/pinctrl/am43xx.h
@@ -25,7 +25,8 @@
#define DS0_FORCE_OFF_MODE (1 << 24)
#define DS0_INPUT (1 << 25)
#define DS0_FORCE_OUT_HIGH (1 << 26)
-#define DS0_PULL_UP_DOWN_EN (1 << 27)
+#define DS0_PULL_UP_DOWN_EN (0 << 27)
+#define DS0_PULL_UP_DOWN_DIS (1 << 27)
#define DS0_PULL_UP_SEL (1 << 28)
#define WAKEUP_ENABLE (1 << 29)
--
2.15.1
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* [PATCH] dts: Remove leading 0x and 0s from bindings notation
From: Mathieu Malaterre @ 2017-12-13 21:07 UTC (permalink / raw)
To: Rob Herring
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, David Daney, Mathieu Malaterre
Improve the DTS files by removing all the leading "0x" and zeros to fix the
following dtc warnings:
Warning (unit_address_format): Node /XXX unit name should not have leading "0x"
and
Warning (unit_address_format): Node /XXX unit name should not have leading 0s
Converted using the following command:
find . -type f \( -iname *.dts -o -iname *.dtsi \) -exec sed -E -i -e "s/@0x([0-9a-fA-F\.]+)[[:space:]]?\{/@\L\1 \{/g" -e "s/@0+([0-9a-fA-F\.]+)([[:space:]]?\{)/@\L\1 \{/g" {} +
For simplicity, two sed expressions were used to solve each warnings separately.
To make the regex expression more robust a few other issues were resolved,
namely setting unit-address to lower case, and adding a whitespace before the
the opening curly brace:
https://elinux.org/Device_Tree_Linux#Linux_conventions
This is a follow up to commit 4c9847b7375a ("dt-bindings: Remove leading 0x from bindings notation")
Reported-by: David Daney <ddaney-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
Suggested-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Mathieu Malaterre <malat-8fiUuRrzOP0dnm+yROfE0A@public.gmane.org>
---
arch/arc/boot/dts/abilis_tb10x.dtsi | 4 +--
arch/arc/boot/dts/axc001.dtsi | 6 ++---
arch/arc/boot/dts/axc003.dtsi | 6 ++---
arch/arc/boot/dts/axc003_idu.dtsi | 6 ++---
arch/arc/boot/dts/axs10x_mb.dtsi | 22 ++++++++--------
arch/arc/boot/dts/vdk_axc003.dtsi | 4 +--
arch/arc/boot/dts/vdk_axc003_idu.dtsi | 4 +--
arch/arc/boot/dts/vdk_axs10x_mb.dtsi | 14 +++++-----
arch/arm/boot/dts/am3517.dtsi | 4 +--
arch/arm/boot/dts/arm-realview-eb.dtsi | 18 ++++++-------
arch/arm/boot/dts/arm-realview-pb1176.dts | 18 ++++++-------
arch/arm/boot/dts/arm-realview-pb11mp.dts | 18 ++++++-------
arch/arm/boot/dts/arm-realview-pbx.dtsi | 18 ++++++-------
arch/arm/boot/dts/artpec6.dtsi | 2 +-
arch/arm/boot/dts/at91sam9261.dtsi | 2 +-
arch/arm/boot/dts/at91sam9261ek.dts | 2 +-
arch/arm/boot/dts/at91sam9263.dtsi | 2 +-
arch/arm/boot/dts/at91sam9263ek.dts | 2 +-
arch/arm/boot/dts/at91sam9g25ek.dts | 2 +-
arch/arm/boot/dts/at91sam9g45.dtsi | 2 +-
arch/arm/boot/dts/at91sam9m10g45ek.dts | 2 +-
arch/arm/boot/dts/atlas7.dtsi | 12 ++++-----
arch/arm/boot/dts/bcm11351.dtsi | 2 +-
arch/arm/boot/dts/bcm21664.dtsi | 2 +-
arch/arm/boot/dts/bcm283x.dtsi | 2 +-
arch/arm/boot/dts/da850-lcdk.dts | 4 +--
arch/arm/boot/dts/dm8148-evm.dts | 8 +++---
arch/arm/boot/dts/dm8168-evm.dts | 8 +++---
arch/arm/boot/dts/dra62x-j5eco-evm.dts | 8 +++---
arch/arm/boot/dts/exynos5420.dtsi | 36 +++++++++++++-------------
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 +-
arch/arm/boot/dts/imx7d.dtsi | 2 +-
arch/arm/boot/dts/keystone-k2e-netcp.dtsi | 2 +-
arch/arm/boot/dts/keystone-k2hk-netcp.dtsi | 2 +-
arch/arm/boot/dts/keystone-k2l-netcp.dtsi | 2 +-
arch/arm/boot/dts/omap3-cm-t3x.dtsi | 8 +++---
arch/arm/boot/dts/omap3-evm-37xx.dts | 8 +++---
arch/arm/boot/dts/omap3-lilly-a83x.dtsi | 8 +++---
arch/arm/boot/dts/s3c2416.dtsi | 2 +-
arch/arm/boot/dts/sama5d3xmb.dtsi | 2 +-
arch/arm/boot/dts/sama5d3xmb_cmp.dtsi | 2 +-
arch/arm/boot/dts/socfpga.dtsi | 2 +-
arch/arm/boot/dts/spear300.dtsi | 2 +-
arch/arm/boot/dts/spear310.dtsi | 2 +-
arch/arm/boot/dts/spear320.dtsi | 2 +-
arch/arm/boot/dts/versatile-ab.dts | 16 ++++++------
arch/arm/boot/dts/zx296702.dtsi | 20 +++++++-------
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 2 +-
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +-
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 6 ++---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 ++---
arch/c6x/boot/dts/dsk6455.dts | 2 +-
arch/c6x/boot/dts/tms320c6455.dtsi | 2 +-
arch/metag/boot/dts/tz1090.dtsi | 10 +++----
arch/mips/boot/dts/img/boston.dts | 2 +-
arch/mips/boot/dts/ingenic/ci20.dts | 8 +++---
arch/nios2/boot/dts/3c120_devboard.dts | 16 ++++++------
arch/powerpc/boot/dts/a3m071.dts | 10 +++----
arch/powerpc/boot/dts/akebono.dts | 4 +--
arch/powerpc/boot/dts/c2k.dts | 6 ++---
arch/powerpc/boot/dts/currituck.dts | 2 +-
arch/powerpc/boot/dts/fsl/mpc8568mds.dts | 12 ++++-----
arch/powerpc/boot/dts/fsl/mpc8569mds.dts | 20 +++++++-------
arch/powerpc/boot/dts/fsl/p1021mds.dts | 6 ++---
arch/powerpc/boot/dts/fsl/p1025rdb.dtsi | 8 +++---
arch/powerpc/boot/dts/fsl/p1025rdb_32b.dts | 2 +-
arch/powerpc/boot/dts/fsl/p1025twr.dtsi | 8 +++---
arch/powerpc/boot/dts/fsl/t1040rdb.dts | 2 +-
arch/powerpc/boot/dts/fsl/t1042d4rdb.dts | 10 +++----
arch/powerpc/boot/dts/fsl/t1042rdb.dts | 2 +-
arch/powerpc/boot/dts/fsl/t104xrdb.dtsi | 6 ++---
arch/powerpc/boot/dts/fsp2.dts | 6 ++---
arch/powerpc/boot/dts/gamecube.dts | 14 +++++-----
arch/powerpc/boot/dts/haleakala.dts | 2 +-
arch/powerpc/boot/dts/kilauea.dts | 4 +--
arch/powerpc/boot/dts/kmeter1.dts | 10 +++----
arch/powerpc/boot/dts/makalu.dts | 4 +--
arch/powerpc/boot/dts/mpc832x_mds.dts | 10 +++----
arch/powerpc/boot/dts/mpc832x_rdb.dts | 8 +++---
arch/powerpc/boot/dts/mpc836x_mds.dts | 8 +++---
arch/powerpc/boot/dts/sbc8548-altflash.dts | 8 +++---
arch/powerpc/boot/dts/sbc8548.dts | 8 +++---
arch/powerpc/boot/dts/wii.dts | 32 +++++++++++------------
arch/xtensa/boot/dts/csp.dts | 2 +-
arch/xtensa/boot/dts/xtfpga-flash-128m.dtsi | 10 +++----
arch/xtensa/boot/dts/xtfpga-flash-16m.dtsi | 10 +++----
arch/xtensa/boot/dts/xtfpga-flash-4m.dtsi | 6 ++---
arch/xtensa/boot/dts/xtfpga.dtsi | 10 +++----
88 files changed, 315 insertions(+), 315 deletions(-)
diff --git a/arch/arc/boot/dts/abilis_tb10x.dtsi b/arch/arc/boot/dts/abilis_tb10x.dtsi
index 3121536b25a3..593cdd96535d 100644
--- a/arch/arc/boot/dts/abilis_tb10x.dtsi
+++ b/arch/arc/boot/dts/abilis_tb10x.dtsi
@@ -178,7 +178,7 @@
clocks = <&ahb_clk>;
};
- spi0: spi@0xFE010000 {
+ spi0: spi@fe010000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
@@ -189,7 +189,7 @@
interrupts = <26 8>;
clocks = <&ahb_clk>;
};
- spi1: spi@0xFE011000 {
+ spi1: spi@fe011000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
diff --git a/arch/arc/boot/dts/axc001.dtsi b/arch/arc/boot/dts/axc001.dtsi
index fdc266504ada..37be3bf03ad6 100644
--- a/arch/arc/boot/dts/axc001.dtsi
+++ b/arch/arc/boot/dts/axc001.dtsi
@@ -41,7 +41,7 @@
* this GPIO block ORs all interrupts on CPU card (creg,..)
* to uplink only 1 IRQ to ARC core intc
*/
- dw-apb-gpio@0x2000 {
+ dw-apb-gpio@2000 {
compatible = "snps,dw-apb-gpio";
reg = < 0x2000 0x80 >;
#address-cells = <1>;
@@ -60,7 +60,7 @@
};
};
- debug_uart: dw-apb-uart@0x5000 {
+ debug_uart: dw-apb-uart@5000 {
compatible = "snps,dw-apb-uart";
reg = <0x5000 0x100>;
clock-frequency = <33333000>;
@@ -88,7 +88,7 @@
* avoid duplicating the MB dtsi file given that IRQ from
* this intc to cpu intc are different for axs101 and axs103
*/
- mb_intc: dw-apb-ictl@0xe0012000 {
+ mb_intc: dw-apb-ictl@e0012000 {
#interrupt-cells = <1>;
compatible = "snps,dw-apb-ictl";
reg = < 0x0 0xe0012000 0x0 0x200 >;
diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
index 4e6e9f57e790..f33694d08e1f 100644
--- a/arch/arc/boot/dts/axc003.dtsi
+++ b/arch/arc/boot/dts/axc003.dtsi
@@ -47,7 +47,7 @@
* this GPIO block ORs all interrupts on CPU card (creg,..)
* to uplink only 1 IRQ to ARC core intc
*/
- dw-apb-gpio@0x2000 {
+ dw-apb-gpio@2000 {
compatible = "snps,dw-apb-gpio";
reg = < 0x2000 0x80 >;
#address-cells = <1>;
@@ -66,7 +66,7 @@
};
};
- debug_uart: dw-apb-uart@0x5000 {
+ debug_uart: dw-apb-uart@5000 {
compatible = "snps,dw-apb-uart";
reg = <0x5000 0x100>;
clock-frequency = <33333000>;
@@ -98,7 +98,7 @@
* avoid duplicating the MB dtsi file given that IRQ from
* this intc to cpu intc are different for axs101 and axs103
*/
- mb_intc: dw-apb-ictl@0xe0012000 {
+ mb_intc: dw-apb-ictl@e0012000 {
#interrupt-cells = <1>;
compatible = "snps,dw-apb-ictl";
reg = < 0x0 0xe0012000 0x0 0x200 >;
diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi
index 63954a8b0100..256790bbd4a0 100644
--- a/arch/arc/boot/dts/axc003_idu.dtsi
+++ b/arch/arc/boot/dts/axc003_idu.dtsi
@@ -54,7 +54,7 @@
* this GPIO block ORs all interrupts on CPU card (creg,..)
* to uplink only 1 IRQ to ARC core intc
*/
- dw-apb-gpio@0x2000 {
+ dw-apb-gpio@2000 {
compatible = "snps,dw-apb-gpio";
reg = < 0x2000 0x80 >;
#address-cells = <1>;
@@ -73,7 +73,7 @@
};
};
- debug_uart: dw-apb-uart@0x5000 {
+ debug_uart: dw-apb-uart@5000 {
compatible = "snps,dw-apb-uart";
reg = <0x5000 0x100>;
clock-frequency = <33333000>;
@@ -104,7 +104,7 @@
* avoid duplicating the MB dtsi file given that IRQ from
* this intc to cpu intc are different for axs101 and axs103
*/
- mb_intc: dw-apb-ictl@0xe0012000 {
+ mb_intc: dw-apb-ictl@e0012000 {
#interrupt-cells = <1>;
compatible = "snps,dw-apb-ictl";
reg = < 0x0 0xe0012000 0x0 0x200 >;
diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index 74d070cd3c13..e4c64c05e32f 100644
--- a/arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/axs10x_mb.dtsi
@@ -68,7 +68,7 @@
};
};
- ethernet@0x18000 {
+ ethernet@18000 {
#interrupt-cells = <1>;
compatible = "snps,dwmac";
reg = < 0x18000 0x2000 >;
@@ -83,13 +83,13 @@
reset-names = "stmmaceth";
};
- ehci@0x40000 {
+ ehci@40000 {
compatible = "generic-ehci";
reg = < 0x40000 0x100 >;
interrupts = < 8 >;
};
- ohci@0x60000 {
+ ohci@60000 {
compatible = "generic-ohci";
reg = < 0x60000 0x100 >;
interrupts = < 8 >;
@@ -113,7 +113,7 @@
* dw_mci_pltfm_prepare_command() is used in generic platform
* code.
*/
- mmc@0x15000 {
+ mmc@15000 {
compatible = "altr,socfpga-dw-mshc";
reg = < 0x15000 0x400 >;
fifo-depth = < 16 >;
@@ -124,7 +124,7 @@
bus-width = < 4 >;
};
- uart@0x20000 {
+ uart@20000 {
compatible = "snps,dw-apb-uart";
reg = <0x20000 0x100>;
clock-frequency = <33333333>;
@@ -134,7 +134,7 @@
reg-io-width = <4>;
};
- uart@0x21000 {
+ uart@21000 {
compatible = "snps,dw-apb-uart";
reg = <0x21000 0x100>;
clock-frequency = <33333333>;
@@ -145,7 +145,7 @@
};
/* UART muxed with USB data port (ttyS3) */
- uart@0x22000 {
+ uart@22000 {
compatible = "snps,dw-apb-uart";
reg = <0x22000 0x100>;
clock-frequency = <33333333>;
@@ -155,7 +155,7 @@
reg-io-width = <4>;
};
- i2c@0x1d000 {
+ i2c@1d000 {
compatible = "snps,designware-i2c";
reg = <0x1d000 0x100>;
clock-frequency = <400000>;
@@ -172,7 +172,7 @@
#sound-dai-cells = <0>;
};
- i2c@0x1f000 {
+ i2c@1f000 {
compatible = "snps,designware-i2c";
#address-cells = <1>;
#size-cells = <0>;
@@ -213,13 +213,13 @@
};
};
- eeprom@0x54{
+ eeprom@54 {
compatible = "24c01";
reg = <0x54>;
pagesize = <0x8>;
};
- eeprom@0x57{
+ eeprom@57 {
compatible = "24c04";
reg = <0x57>;
pagesize = <0x8>;
diff --git a/arch/arc/boot/dts/vdk_axc003.dtsi b/arch/arc/boot/dts/vdk_axc003.dtsi
index 0fd6ba985b16..84e8766c8ca2 100644
--- a/arch/arc/boot/dts/vdk_axc003.dtsi
+++ b/arch/arc/boot/dts/vdk_axc003.dtsi
@@ -36,7 +36,7 @@
#interrupt-cells = <1>;
};
- debug_uart: dw-apb-uart@0x5000 {
+ debug_uart: dw-apb-uart@5000 {
compatible = "snps,dw-apb-uart";
reg = <0x5000 0x100>;
clock-frequency = <2403200>;
@@ -49,7 +49,7 @@
};
- mb_intc: dw-apb-ictl@0xe0012000 {
+ mb_intc: dw-apb-ictl@e0012000 {
#interrupt-cells = <1>;
compatible = "snps,dw-apb-ictl";
reg = < 0xe0012000 0x200 >;
diff --git a/arch/arc/boot/dts/vdk_axc003_idu.dtsi b/arch/arc/boot/dts/vdk_axc003_idu.dtsi
index 28956f9a9f3d..eb7e705e8a27 100644
--- a/arch/arc/boot/dts/vdk_axc003_idu.dtsi
+++ b/arch/arc/boot/dts/vdk_axc003_idu.dtsi
@@ -44,7 +44,7 @@
#interrupt-cells = <1>;
};
- debug_uart: dw-apb-uart@0x5000 {
+ debug_uart: dw-apb-uart@5000 {
compatible = "snps,dw-apb-uart";
reg = <0x5000 0x100>;
clock-frequency = <2403200>;
@@ -57,7 +57,7 @@
};
- mb_intc: dw-apb-ictl@0xe0012000 {
+ mb_intc: dw-apb-ictl@e0012000 {
#interrupt-cells = <1>;
compatible = "snps,dw-apb-ictl";
reg = < 0xe0012000 0x200 >;
diff --git a/arch/arc/boot/dts/vdk_axs10x_mb.dtsi b/arch/arc/boot/dts/vdk_axs10x_mb.dtsi
index 48bb4b4cd234..f21ade2931eb 100644
--- a/arch/arc/boot/dts/vdk_axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/vdk_axs10x_mb.dtsi
@@ -36,7 +36,7 @@
};
};
- ethernet@0x18000 {
+ ethernet@18000 {
#interrupt-cells = <1>;
compatible = "snps,dwmac";
reg = < 0x18000 0x2000 >;
@@ -49,13 +49,13 @@
clock-names = "stmmaceth";
};
- ehci@0x40000 {
+ ehci@40000 {
compatible = "generic-ehci";
reg = < 0x40000 0x100 >;
interrupts = < 8 >;
};
- uart@0x20000 {
+ uart@20000 {
compatible = "snps,dw-apb-uart";
reg = <0x20000 0x100>;
clock-frequency = <2403200>;
@@ -65,7 +65,7 @@
reg-io-width = <4>;
};
- uart@0x21000 {
+ uart@21000 {
compatible = "snps,dw-apb-uart";
reg = <0x21000 0x100>;
clock-frequency = <2403200>;
@@ -75,7 +75,7 @@
reg-io-width = <4>;
};
- uart@0x22000 {
+ uart@22000 {
compatible = "snps,dw-apb-uart";
reg = <0x22000 0x100>;
clock-frequency = <2403200>;
@@ -101,7 +101,7 @@
interrupt-names = "arc_ps2_irq";
};
- mmc@0x15000 {
+ mmc@15000 {
compatible = "snps,dw-mshc";
reg = <0x15000 0x400>;
fifo-depth = <1024>;
@@ -119,7 +119,7 @@
* This node is intentionally put outside of MB above becase
* it maps areas outside of MB's 0xEz-0xFz.
*/
- uio_ev: uio@0xD0000000 {
+ uio_ev: uio@d0000000 {
compatible = "generic-uio";
reg = <0xD0000000 0x2000 0xD1000000 0x2000 0x90000000 0x10000000 0xC0000000 0x10000000>;
reg-names = "ev_gsa", "ev_ctrl", "ev_shared_mem", "ev_code_mem";
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index 00da3f2c4072..76994165fb3a 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -26,7 +26,7 @@
interrupt-names = "mc";
};
- davinci_emac: ethernet@0x5c000000 {
+ davinci_emac: ethernet@5c000000 {
compatible = "ti,am3517-emac";
ti,hwmods = "davinci_emac";
status = "disabled";
@@ -41,7 +41,7 @@
local-mac-address = [ 00 00 00 00 00 00 ];
};
- davinci_mdio: ethernet@0x5c030000 {
+ davinci_mdio: ethernet@5c030000 {
compatible = "ti,davinci_mdio";
ti,hwmods = "davinci_mdio";
status = "disabled";
diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi
index e2e9599596e2..f92fb6debc13 100644
--- a/arch/arm/boot/dts/arm-realview-eb.dtsi
+++ b/arch/arm/boot/dts/arm-realview-eb.dtsi
@@ -154,7 +154,7 @@
compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
- led@08.0 {
+ led@8.0 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x01>;
@@ -162,7 +162,7 @@
linux,default-trigger = "heartbeat";
default-state = "on";
};
- led@08.1 {
+ led@8.1 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x02>;
@@ -170,7 +170,7 @@
linux,default-trigger = "mmc0";
default-state = "off";
};
- led@08.2 {
+ led@8.2 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x04>;
@@ -178,42 +178,42 @@
linux,default-trigger = "cpu0";
default-state = "off";
};
- led@08.3 {
+ led@8.3 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
default-state = "off";
};
- led@08.4 {
+ led@8.4 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
default-state = "off";
};
- led@08.5 {
+ led@8.5 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
default-state = "off";
};
- led@08.6 {
+ led@8.6 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
- led@08.7 {
+ led@8.7 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x80>;
label = "versatile:7";
default-state = "off";
};
- oscclk0: osc0@0c {
+ oscclk0: osc0@c {
compatible = "arm,syscon-icst307";
#clock-cells = <0>;
lock-offset = <0x20>;
diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts
index c789564f2803..c918949d7c21 100644
--- a/arch/arm/boot/dts/arm-realview-pb1176.dts
+++ b/arch/arm/boot/dts/arm-realview-pb1176.dts
@@ -172,7 +172,7 @@
compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
- led@08.0 {
+ led@8.0 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x01>;
@@ -180,7 +180,7 @@
linux,default-trigger = "heartbeat";
default-state = "on";
};
- led@08.1 {
+ led@8.1 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x02>;
@@ -188,7 +188,7 @@
linux,default-trigger = "mmc0";
default-state = "off";
};
- led@08.2 {
+ led@8.2 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x04>;
@@ -196,42 +196,42 @@
linux,default-trigger = "cpu0";
default-state = "off";
};
- led@08.3 {
+ led@8.3 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
default-state = "off";
};
- led@08.4 {
+ led@8.4 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
default-state = "off";
};
- led@08.5 {
+ led@8.5 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
default-state = "off";
};
- led@08.6 {
+ led@8.6 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
- led@08.7 {
+ led@8.7 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x80>;
label = "versatile:7";
default-state = "off";
};
- oscclk0: osc0@0c {
+ oscclk0: osc0@c {
compatible = "arm,syscon-icst307";
#clock-cells = <0>;
lock-offset = <0x20>;
diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts
index 3944765ac4b0..12c3fb69038a 100644
--- a/arch/arm/boot/dts/arm-realview-pb11mp.dts
+++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts
@@ -253,7 +253,7 @@
compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
- led@08.0 {
+ led@8.0 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x01>;
@@ -261,7 +261,7 @@
linux,default-trigger = "heartbeat";
default-state = "on";
};
- led@08.1 {
+ led@8.1 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x02>;
@@ -269,7 +269,7 @@
linux,default-trigger = "mmc0";
default-state = "off";
};
- led@08.2 {
+ led@8.2 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x04>;
@@ -277,7 +277,7 @@
linux,default-trigger = "cpu0";
default-state = "off";
};
- led@08.3 {
+ led@8.3 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x08>;
@@ -285,7 +285,7 @@
linux,default-trigger = "cpu1";
default-state = "off";
};
- led@08.4 {
+ led@8.4 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x10>;
@@ -293,7 +293,7 @@
linux,default-trigger = "cpu2";
default-state = "off";
};
- led@08.5 {
+ led@8.5 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x20>;
@@ -301,14 +301,14 @@
linux,default-trigger = "cpu3";
default-state = "off";
};
- led@08.6 {
+ led@8.6 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
- led@08.7 {
+ led@8.7 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x80>;
@@ -316,7 +316,7 @@
default-state = "off";
};
- oscclk0: osc0@0c {
+ oscclk0: osc0@c {
compatible = "arm,syscon-icst307";
#clock-cells = <0>;
lock-offset = <0x20>;
diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi
index aeb49c4bd773..ae080739229e 100644
--- a/arch/arm/boot/dts/arm-realview-pbx.dtsi
+++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi
@@ -169,7 +169,7 @@
compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
- led@08.0 {
+ led@8.0 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x01>;
@@ -177,7 +177,7 @@
linux,default-trigger = "heartbeat";
default-state = "on";
};
- led@08.1 {
+ led@8.1 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x02>;
@@ -185,7 +185,7 @@
linux,default-trigger = "mmc0";
default-state = "off";
};
- led@08.2 {
+ led@8.2 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x04>;
@@ -193,42 +193,42 @@
linux,default-trigger = "cpu0";
default-state = "off";
};
- led@08.3 {
+ led@8.3 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
default-state = "off";
};
- led@08.4 {
+ led@8.4 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
default-state = "off";
};
- led@08.5 {
+ led@8.5 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
default-state = "off";
};
- led@08.6 {
+ led@8.6 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
- led@08.7 {
+ led@8.7 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x80>;
label = "versatile:7";
default-state = "off";
};
- oscclk0: osc0@0c {
+ oscclk0: osc0@c {
compatible = "arm,syscon-icst307";
#clock-cells = <0>;
lock-offset = <0x20>;
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index 2ed11773048d..71e0e75e986b 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -98,7 +98,7 @@
clock-frequency = <125000000>;
};
- clkctrl: clkctrl@0xf8000000 {
+ clkctrl: clkctrl@f8000000 {
#clock-cells = <1>;
compatible = "axis,artpec6-clkctrl";
reg = <0xf8000000 0x48>;
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index 66876019101d..eb186245fb4c 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -80,7 +80,7 @@
status = "disabled";
};
- fb0: fb@0x00600000 {
+ fb0: fb@600000 {
compatible = "atmel,at91sam9261-lcdc";
reg = <0x00600000 0x1000>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts
index 960d6940ebf6..9733db3f739b 100644
--- a/arch/arm/boot/dts/at91sam9261ek.dts
+++ b/arch/arm/boot/dts/at91sam9261ek.dts
@@ -36,7 +36,7 @@
status = "okay";
};
- fb0: fb@0x00600000 {
+ fb0: fb@600000 {
display = <&display0>;
atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>;
status = "okay";
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index e54f14d36b6f..a26f7ada429d 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -999,7 +999,7 @@
};
};
- fb0: fb@0x00700000 {
+ fb0: fb@700000 {
compatible = "atmel,at91sam9263-lcdc";
reg = <0x00700000 0x1000>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 5a2e1af793f5..f095b5d4d410 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -95,7 +95,7 @@
};
};
- fb0: fb@0x00700000 {
+ fb0: fb@700000 {
display = <&display0>;
status = "okay";
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 91a71774472e..31fecc2cdaf9 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -25,7 +25,7 @@
};
i2c0: i2c@f8010000 {
- ov2640: camera@0x30 {
+ ov2640: camera@30 {
compatible = "ovti,ov2640";
reg = <0x30>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 2b127ca7aaa0..98348ebd6488 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -1302,7 +1302,7 @@
};
};
- fb0: fb@0x00500000 {
+ fb0: fb@500000 {
compatible = "atmel,at91sam9g45-lcdc";
reg = <0x00500000 0x1000>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index e922552a04cb..d793451ee04c 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -220,7 +220,7 @@
};
};
- fb0: fb@0x00500000 {
+ fb0: fb@500000 {
display = <&display0>;
status = "okay";
diff --git a/arch/arm/boot/dts/atlas7.dtsi b/arch/arm/boot/dts/atlas7.dtsi
index 83449b33de6b..920d22882f21 100644
--- a/arch/arm/boot/dts/atlas7.dtsi
+++ b/arch/arm/boot/dts/atlas7.dtsi
@@ -1170,7 +1170,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x13240000 0x13240000 0x00010000>;
- pmipc@0x13240000 {
+ pmipc@13240000 {
compatible = "sirf,atlas7-pmipc";
reg = <0x13240000 0x00010000>;
};
@@ -1265,7 +1265,7 @@
#dma-cells = <1>;
};
- gnssmfw@0x18100000 {
+ gnssmfw@18100000 {
compatible = "sirf,nocfw-gnssm";
reg = <0x18100000 0x3000>;
};
@@ -1374,7 +1374,7 @@
<0x13010000 0x13010000 0x1400>,
<0x13010800 0x13010800 0x100>,
<0x13011000 0x13011000 0x100>;
- gpum@0x13000000 {
+ gpum@13000000 {
compatible = "sirf,nocfw-gpum";
reg = <0x13000000 0x3000>;
};
@@ -1396,7 +1396,7 @@
#dma-cells = <1>;
#dma-channels = <1>;
};
- sdr@0x13010000 {
+ sdr@13010000 {
compatible = "sirf,atlas7-sdr";
reg = <0x13010000 0x1400>;
interrupts = <0 7 0>,
@@ -1780,7 +1780,7 @@
interrupts = <0 105 0>;
};
- memory-controller@0x10800000 {
+ memory-controller@10800000 {
compatible = "sirf,atlas7-memc";
reg = <0x10800000 0x2000>;
};
@@ -1896,7 +1896,7 @@
#size-cells = <0>;
};
- retain@0x188D0000 {
+ retain@188d0000 {
compatible = "sirf,atlas7-retain";
reg = <0x188D0000 0x1000>;
};
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 18045c38bcf1..db7cded1b7ad 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -55,7 +55,7 @@
<0x3ff00100 0x100>;
};
- smc@0x3404c000 {
+ smc@3404c000 {
compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
};
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
index 6dde95f21cef..266f2611dc22 100644
--- a/arch/arm/boot/dts/bcm21664.dtsi
+++ b/arch/arm/boot/dts/bcm21664.dtsi
@@ -55,7 +55,7 @@
<0x3ff00100 0x100>;
};
- smc@0x3404e000 {
+ smc@3404e000 {
compatible = "brcm,bcm21664-smc", "brcm,kona-smc";
reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
};
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index dcde93c85c2d..2ee4f04ea9d4 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -464,7 +464,7 @@
status = "disabled";
};
- aux: aux@0x7e215000 {
+ aux: aux@7e215000 {
compatible = "brcm,bcm2835-aux";
#clock-cells = <1>;
reg = <0x7e215000 0x8>;
diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts
index eed89e659143..a1f4d6d5a569 100644
--- a/arch/arm/boot/dts/da850-lcdk.dts
+++ b/arch/arm/boot/dts/da850-lcdk.dts
@@ -293,12 +293,12 @@
label = "u-boot env";
reg = <0 0x020000>;
};
- partition@0x020000 {
+ partition@20000 {
/* The LCDK defaults to booting from this partition */
label = "u-boot";
reg = <0x020000 0x080000>;
};
- partition@0x0a0000 {
+ partition@a0000 {
label = "free space";
reg = <0x0a0000 0>;
};
diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts
index d6657b3bae84..7747a5b9657f 100644
--- a/arch/arm/boot/dts/dm8148-evm.dts
+++ b/arch/arm/boot/dts/dm8148-evm.dts
@@ -74,19 +74,19 @@
label = "X-Loader";
reg = <0 0x80000>;
};
- partition@0x80000 {
+ partition@80000 {
label = "U-Boot";
reg = <0x80000 0x1c0000>;
};
- partition@0x1c0000 {
+ partition@1c0000 {
label = "Environment";
reg = <0x240000 0x40000>;
};
- partition@0x280000 {
+ partition@280000 {
label = "Kernel";
reg = <0x280000 0x500000>;
};
- partition@0x780000 {
+ partition@780000 {
label = "Filesystem";
reg = <0x780000 0xf880000>;
};
diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
index c72a2132aa82..85dd3c703dff 100644
--- a/arch/arm/boot/dts/dm8168-evm.dts
+++ b/arch/arm/boot/dts/dm8168-evm.dts
@@ -158,19 +158,19 @@
label = "X-Loader";
reg = <0 0x80000>;
};
- partition@0x80000 {
+ partition@80000 {
label = "U-Boot";
reg = <0x80000 0x1c0000>;
};
- partition@0x1c0000 {
+ partition@1c0000 {
label = "Environment";
reg = <0x240000 0x40000>;
};
- partition@0x280000 {
+ partition@280000 {
label = "Kernel";
reg = <0x280000 0x500000>;
};
- partition@0x780000 {
+ partition@780000 {
label = "Filesystem";
reg = <0x780000 0xf880000>;
};
diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/dra62x-j5eco-evm.dts
index 155eb32ee213..fee0547f7302 100644
--- a/arch/arm/boot/dts/dra62x-j5eco-evm.dts
+++ b/arch/arm/boot/dts/dra62x-j5eco-evm.dts
@@ -74,19 +74,19 @@
label = "X-Loader";
reg = <0 0x80000>;
};
- partition@0x80000 {
+ partition@80000 {
label = "U-Boot";
reg = <0x80000 0x1c0000>;
};
- partition@0x1c0000 {
+ partition@1c0000 {
label = "Environment";
reg = <0x240000 0x40000>;
};
- partition@0x280000 {
+ partition@280000 {
label = "Kernel";
reg = <0x280000 0x500000>;
};
- partition@0x780000 {
+ partition@780000 {
label = "Filesystem";
reg = <0x780000 0xf880000>;
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 8aa2cc7aa125..05ddbcf4413b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -752,7 +752,7 @@
#include "exynos5420-tmu-sensor-conf.dtsi"
};
- sysmmu_g2dr: sysmmu@0x10A60000 {
+ sysmmu_g2dr: sysmmu@10a60000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x10A60000 0x1000>;
interrupt-parent = <&combiner>;
@@ -762,7 +762,7 @@
#iommu-cells = <0>;
};
- sysmmu_g2dw: sysmmu@0x10A70000 {
+ sysmmu_g2dw: sysmmu@10a70000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x10A70000 0x1000>;
interrupt-parent = <&combiner>;
@@ -772,7 +772,7 @@
#iommu-cells = <0>;
};
- sysmmu_tv: sysmmu@0x14650000 {
+ sysmmu_tv: sysmmu@14650000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14650000 0x1000>;
interrupt-parent = <&combiner>;
@@ -783,7 +783,7 @@
#iommu-cells = <0>;
};
- sysmmu_gscl0: sysmmu@0x13E80000 {
+ sysmmu_gscl0: sysmmu@13e80000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13E80000 0x1000>;
interrupt-parent = <&combiner>;
@@ -794,7 +794,7 @@
#iommu-cells = <0>;
};
- sysmmu_gscl1: sysmmu@0x13E90000 {
+ sysmmu_gscl1: sysmmu@13e90000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13E90000 0x1000>;
interrupt-parent = <&combiner>;
@@ -805,7 +805,7 @@
#iommu-cells = <0>;
};
- sysmmu_scaler0r: sysmmu@0x12880000 {
+ sysmmu_scaler0r: sysmmu@12880000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12880000 0x1000>;
interrupt-parent = <&combiner>;
@@ -815,7 +815,7 @@
#iommu-cells = <0>;
};
- sysmmu_scaler1r: sysmmu@0x12890000 {
+ sysmmu_scaler1r: sysmmu@12890000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12890000 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
@@ -824,7 +824,7 @@
#iommu-cells = <0>;
};
- sysmmu_scaler2r: sysmmu@0x128A0000 {
+ sysmmu_scaler2r: sysmmu@128a0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128A0000 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
@@ -833,7 +833,7 @@
#iommu-cells = <0>;
};
- sysmmu_scaler0w: sysmmu@0x128C0000 {
+ sysmmu_scaler0w: sysmmu@128c0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128C0000 0x1000>;
interrupt-parent = <&combiner>;
@@ -843,7 +843,7 @@
#iommu-cells = <0>;
};
- sysmmu_scaler1w: sysmmu@0x128D0000 {
+ sysmmu_scaler1w: sysmmu@128d0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128D0000 0x1000>;
interrupt-parent = <&combiner>;
@@ -853,7 +853,7 @@
#iommu-cells = <0>;
};
- sysmmu_scaler2w: sysmmu@0x128E0000 {
+ sysmmu_scaler2w: sysmmu@128e0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128E0000 0x1000>;
interrupt-parent = <&combiner>;
@@ -863,7 +863,7 @@
#iommu-cells = <0>;
};
- sysmmu_rotator: sysmmu@0x11D40000 {
+ sysmmu_rotator: sysmmu@11d40000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11D40000 0x1000>;
interrupt-parent = <&combiner>;
@@ -873,7 +873,7 @@
#iommu-cells = <0>;
};
- sysmmu_jpeg0: sysmmu@0x11F10000 {
+ sysmmu_jpeg0: sysmmu@11f10000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11F10000 0x1000>;
interrupt-parent = <&combiner>;
@@ -883,7 +883,7 @@
#iommu-cells = <0>;
};
- sysmmu_jpeg1: sysmmu@0x11F20000 {
+ sysmmu_jpeg1: sysmmu@11f20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11F20000 0x1000>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
@@ -892,7 +892,7 @@
#iommu-cells = <0>;
};
- sysmmu_mfc_l: sysmmu@0x11200000 {
+ sysmmu_mfc_l: sysmmu@11200000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11200000 0x1000>;
interrupt-parent = <&combiner>;
@@ -903,7 +903,7 @@
#iommu-cells = <0>;
};
- sysmmu_mfc_r: sysmmu@0x11210000 {
+ sysmmu_mfc_r: sysmmu@11210000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11210000 0x1000>;
interrupt-parent = <&combiner>;
@@ -914,7 +914,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimd1_0: sysmmu@0x14640000 {
+ sysmmu_fimd1_0: sysmmu@14640000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14640000 0x1000>;
interrupt-parent = <&combiner>;
@@ -925,7 +925,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimd1_1: sysmmu@0x14680000 {
+ sysmmu_fimd1_1: sysmmu@14680000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14680000 0x1000>;
interrupt-parent = <&combiner>;
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index a5b8d0f0877e..353428fe10c4 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -26,7 +26,7 @@
stdout-path = "serial2:115200n8";
};
- firmware@02073000 {
+ firmware@2073000 {
compatible = "samsung,secure-firmware";
reg = <0x02073000 0x1000>;
};
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 4d308d17f040..369d5a166b3e 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -129,7 +129,7 @@
status = "disabled";
};
- pcie: pcie@0x33800000 {
+ pcie: pcie@33800000 {
compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
reg = <0x33800000 0x4000>,
<0x4ff00000 0x80000>;
diff --git a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi
index ba828cb59587..940b64935bde 100644
--- a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi
+++ b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi
@@ -98,7 +98,7 @@ qmss: qmss@2a40000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
- pdsp0@0x2a10000 {
+ pdsp0@2a10000 {
reg = <0x2a10000 0x1000 /*iram */
0x2a0f000 0x100 /*reg*/
0x2a0c000 0x3c8 /*intd */
diff --git a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi
index a5ac845464bf..ed7287a274a0 100644
--- a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi
+++ b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi
@@ -115,7 +115,7 @@ qmss: qmss@2a40000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
- pdsp0@0x2a10000 {
+ pdsp0@2a10000 {
reg = <0x2a10000 0x1000 /*iram */
0x2a0f000 0x100 /*reg*/
0x2a0c000 0x3c8 /*intd */
diff --git a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi
index 66f615a74118..b6af5f78e498 100644
--- a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi
+++ b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi
@@ -97,7 +97,7 @@ qmss: qmss@2a40000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
- pdsp0@0x2a10000 {
+ pdsp0@2a10000 {
reg = <0x2a10000 0x1000 /*iram */
0x2a0f000 0x100 /*reg*/
0x2a0c000 0x3c8 /*intd */
diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
index ab6003fe5a43..9dcb18d22cde 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
@@ -306,19 +306,19 @@
label = "xloader";
reg = <0 0x80000>;
};
- partition@0x80000 {
+ partition@80000 {
label = "uboot";
reg = <0x80000 0x1e0000>;
};
- partition@0x260000 {
+ partition@260000 {
label = "uboot environment";
reg = <0x260000 0x40000>;
};
- partition@0x2a0000 {
+ partition@2a0000 {
label = "linux";
reg = <0x2a0000 0x400000>;
};
- partition@0x6a0000 {
+ partition@6a0000 {
label = "rootfs";
reg = <0x6a0000 0x1f880000>;
};
diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts
index 5a4ba0aea447..a14303b09ae2 100644
--- a/arch/arm/boot/dts/omap3-evm-37xx.dts
+++ b/arch/arm/boot/dts/omap3-evm-37xx.dts
@@ -90,19 +90,19 @@
label = "X-Loader";
reg = <0 0x80000>;
};
- partition@0x80000 {
+ partition@80000 {
label = "U-Boot";
reg = <0x80000 0x1c0000>;
};
- partition@0x1c0000 {
+ partition@1c0000 {
label = "Environment";
reg = <0x240000 0x40000>;
};
- partition@0x280000 {
+ partition@280000 {
label = "Kernel";
reg = <0x280000 0x500000>;
};
- partition@0x780000 {
+ partition@780000 {
label = "Filesystem";
reg = <0x780000 0x1f880000>;
};
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
index 7ada1e93e166..cf7a2a72348d 100644
--- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
+++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
@@ -405,22 +405,22 @@
reg = <0 0x80000>;
};
- partition@0x80000 {
+ partition@80000 {
label = "u-boot";
reg = <0x80000 0x1e0000>;
};
- partition@0x260000 {
+ partition@260000 {
label = "u-boot-environment";
reg = <0x260000 0x20000>;
};
- partition@0x280000 {
+ partition@280000 {
label = "kernel";
reg = <0x280000 0x500000>;
};
- partition@0x780000 {
+ partition@780000 {
label = "filesystem";
reg = <0x780000 0xf880000>;
};
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi
index 80f007550324..66840f02a618 100644
--- a/arch/arm/boot/dts/s3c2416.dtsi
+++ b/arch/arm/boot/dts/s3c2416.dtsi
@@ -33,7 +33,7 @@
compatible = "samsung,s3c2416-irq";
};
- clocks: clock-controller@0x4c000000 {
+ clocks: clock-controller@4c000000 {
compatible = "samsung,s3c2416-clock";
reg = <0x4c000000 0x40>;
#clock-cells = <1>;
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
index 7f55050dd405..ef0f2d049e15 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -53,7 +53,7 @@
};
i2c1: i2c@f0018000 {
- ov2640: camera@0x30 {
+ ov2640: camera@30 {
compatible = "ovti,ov2640";
reg = <0x30>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi
index 83e3d3e08fd4..97e171db5970 100644
--- a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi
@@ -88,7 +88,7 @@
};
i2c1: i2c@f0018000 {
- ov2640: camera@0x30 {
+ ov2640: camera@30 {
compatible = "ovti,ov2640";
reg = <0x30>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 7e24dc8e82d4..36f87eb389b1 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -724,7 +724,7 @@
arm,prefetch-offset = <7>;
};
- l3regs@0xff800000 {
+ l3regs@ff800000 {
compatible = "altr,l3regs", "syscon";
reg = <0xff800000 0x1000>;
};
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
index f4e92e599729..266fefa67223 100644
--- a/arch/arm/boot/dts/spear300.dtsi
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -52,7 +52,7 @@
status = "disabled";
};
- shirq: interrupt-controller@0x50000000 {
+ shirq: interrupt-controller@50000000 {
compatible = "st,spear300-shirq";
reg = <0x50000000 0x1000>;
interrupts = <28>;
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
index da210b454753..f995ecf09acf 100644
--- a/arch/arm/boot/dts/spear310.dtsi
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -40,7 +40,7 @@
status = "disabled";
};
- shirq: interrupt-controller@0xb4000000 {
+ shirq: interrupt-controller@b4000000 {
compatible = "st,spear310-shirq";
reg = <0xb4000000 0x1000>;
interrupts = <28 29 30 1>;
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index 22be6e5edaac..2a062a3ee139 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -55,7 +55,7 @@
status = "disabled";
};
- shirq: interrupt-controller@0xb3000000 {
+ shirq: interrupt-controller@b3000000 {
compatible = "st,spear320-shirq";
reg = <0xb3000000 0x1000>;
interrupts = <30 28 29 1>;
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index 4a51612996bc..8b0ad47e7b1f 100644
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -34,7 +34,7 @@
compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
reg = <0x10000000 0x200>;
- led@08.0 {
+ led@8.0 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x01>;
@@ -42,7 +42,7 @@
linux,default-trigger = "heartbeat";
default-state = "on";
};
- led@08.1 {
+ led@8.1 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x02>;
@@ -50,7 +50,7 @@
linux,default-trigger = "mmc0";
default-state = "off";
};
- led@08.2 {
+ led@8.2 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x04>;
@@ -58,35 +58,35 @@
linux,default-trigger = "cpu0";
default-state = "off";
};
- led@08.3 {
+ led@8.3 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
default-state = "off";
};
- led@08.4 {
+ led@8.4 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
default-state = "off";
};
- led@08.5 {
+ led@8.5 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
default-state = "off";
};
- led@08.6 {
+ led@8.6 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
- led@08.7 {
+ led@8.7 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x80>;
diff --git a/arch/arm/boot/dts/zx296702.dtsi b/arch/arm/boot/dts/zx296702.dtsi
index 8a74efdb6360..240e7a23d81f 100644
--- a/arch/arm/boot/dts/zx296702.dtsi
+++ b/arch/arm/boot/dts/zx296702.dtsi
@@ -56,7 +56,7 @@
clocks = <&topclk ZX296702_A9_PERIPHCLK>;
};
- l2cc: l2-cache-controller@0x00c00000 {
+ l2cc: l2-cache-controller@c00000 {
compatible = "arm,pl310-cache";
reg = <0x00c00000 0x1000>;
cache-unified;
@@ -67,30 +67,30 @@
arm,double-linefill-incr = <0>;
};
- pcu: pcu@0xa0008000 {
+ pcu: pcu@a0008000 {
compatible = "zte,zx296702-pcu";
reg = <0xa0008000 0x1000>;
};
- topclk: topclk@0x09800000 {
+ topclk: topclk@9800000 {
compatible = "zte,zx296702-topcrm-clk";
reg = <0x09800000 0x1000>;
#clock-cells = <1>;
};
- lsp1clk: lsp1clk@0x09400000 {
+ lsp1clk: lsp1clk@9400000 {
compatible = "zte,zx296702-lsp1crpm-clk";
reg = <0x09400000 0x1000>;
#clock-cells = <1>;
};
- lsp0clk: lsp0clk@0x0b000000 {
+ lsp0clk: lsp0clk@b000000 {
compatible = "zte,zx296702-lsp0crpm-clk";
reg = <0x0b000000 0x1000>;
#clock-cells = <1>;
};
- uart0: serial@0x09405000 {
+ uart0: serial@9405000 {
compatible = "zte,zx296702-uart";
reg = <0x09405000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
@@ -98,7 +98,7 @@
status = "disabled";
};
- uart1: serial@0x09406000 {
+ uart1: serial@9406000 {
compatible = "zte,zx296702-uart";
reg = <0x09406000 0x1000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
@@ -106,7 +106,7 @@
status = "disabled";
};
- mmc0: mmc@0x09408000 {
+ mmc0: mmc@9408000 {
compatible = "snps,dw-mshc";
#address-cells = <1>;
#size-cells = <0>;
@@ -119,7 +119,7 @@
status = "disabled";
};
- mmc1: mmc@0x0b003000 {
+ mmc1: mmc@b003000 {
compatible = "snps,dw-mshc";
#address-cells = <1>;
#size-cells = <0>;
@@ -132,7 +132,7 @@
status = "disabled";
};
- sysctrl: sysctrl@0xa0007000 {
+ sysctrl: sysctrl@a0007000 {
compatible = "zte,sysctrl", "syscon";
reg = <0xa0007000 0x1000>;
};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index 3aee6123d161..3f5ff76109be 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -51,7 +51,7 @@
#size-cells = <2>;
ranges;
- ramoops@0x21f00000 {
+ ramoops@21f00000 {
compatible = "ramoops";
reg = <0x0 0x21f00000 0x0 0x00100000>;
record-size = <0x00020000>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 26396ef53bde..0446b122a6e2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -249,7 +249,7 @@
reg = <0 0x10005000 0 0x1000>;
};
- pio: pinctrl@0x10005000 {
+ pio: pinctrl@10005000 {
compatible = "mediatek,mt8173-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>;
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 492a011f14f6..1c8f1b86472d 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -140,16 +140,16 @@
};
agnoc@0 {
- qcom,pcie@00600000 {
+ qcom,pcie@600000 {
perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
};
- qcom,pcie@00608000 {
+ qcom,pcie@608000 {
status = "okay";
perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
};
- qcom,pcie@00610000 {
+ qcom,pcie@610000 {
status = "okay";
perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 4b2afcc4fdf4..0a6f7952bbb1 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -840,7 +840,7 @@
#size-cells = <1>;
ranges;
- pcie0: qcom,pcie@00600000 {
+ pcie0: qcom,pcie@600000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
status = "disabled";
power-domains = <&gcc PCIE0_GDSC>;
@@ -893,7 +893,7 @@
};
- pcie1: qcom,pcie@00608000 {
+ pcie1: qcom,pcie@608000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
power-domains = <&gcc PCIE1_GDSC>;
bus-range = <0x00 0xff>;
@@ -946,7 +946,7 @@
"bus_slave";
};
- pcie2: qcom,pcie@00610000 {
+ pcie2: qcom,pcie@610000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
power-domains = <&gcc PCIE2_GDSC>;
bus-range = <0x00 0xff>;
diff --git a/arch/c6x/boot/dts/dsk6455.dts b/arch/c6x/boot/dts/dsk6455.dts
index 2b71f800618d..3012f44e9357 100644
--- a/arch/c6x/boot/dts/dsk6455.dts
+++ b/arch/c6x/boot/dts/dsk6455.dts
@@ -55,7 +55,7 @@
interrupts = < 69 >;
};
- clock-controller@029a0000 {
+ clock-controller@29a0000 {
clock-frequency = <50000000>;
};
};
diff --git a/arch/c6x/boot/dts/tms320c6455.dtsi b/arch/c6x/boot/dts/tms320c6455.dtsi
index 0b21cb30343b..b5c36fb351db 100644
--- a/arch/c6x/boot/dts/tms320c6455.dtsi
+++ b/arch/c6x/boot/dts/tms320c6455.dtsi
@@ -68,7 +68,7 @@
ti,dscr-dev-enable = <4>;
};
- clock-controller@029a0000 {
+ clock-controller@29a0000 {
compatible = "ti,c6455-pll", "ti,c64x+pll";
reg = <0x029a0000 0x200>;
ti,c64x+pll-bypass-delay = <1440>;
diff --git a/arch/metag/boot/dts/tz1090.dtsi b/arch/metag/boot/dts/tz1090.dtsi
index 24ea7d2e9138..a3a3be7796f1 100644
--- a/arch/metag/boot/dts/tz1090.dtsi
+++ b/arch/metag/boot/dts/tz1090.dtsi
@@ -28,7 +28,7 @@
#size-cells = <1>;
ranges;
- pdc: pdc@0x02006000 {
+ pdc: pdc@2006000 {
interrupt-controller;
#interrupt-cells = <2>;
@@ -44,19 +44,19 @@
<31 IRQ_TYPE_LEVEL_HIGH>; /* Perip 2 (WDT) */
};
- pinctrl: pinctrl@02005800 {
+ pinctrl: pinctrl@2005800 {
#gpio-range-cells = <3>;
compatible = "img,tz1090-pinctrl";
reg = <0x02005800 0xe4>;
};
- pdc_pinctrl: pinctrl@02006500 {
+ pdc_pinctrl: pinctrl@2006500 {
#gpio-range-cells = <3>;
compatible = "img,tz1090-pdc-pinctrl";
reg = <0x02006500 0x100>;
};
- gpios: gpios@02005800 {
+ gpios: gpios@2005800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "img,tz1090-gpio";
@@ -91,7 +91,7 @@
};
};
- pdc_gpios: gpios@02006500 {
+ pdc_gpios: gpios@2006500 {
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/mips/boot/dts/img/boston.dts b/arch/mips/boot/dts/img/boston.dts
index 2cd49b60e030..1bd105428f61 100644
--- a/arch/mips/boot/dts/img/boston.dts
+++ b/arch/mips/boot/dts/img/boston.dts
@@ -157,7 +157,7 @@
#address-cells = <1>;
#size-cells = <0>;
- rtc@0x68 {
+ rtc@68 {
compatible = "st,m41t81s";
reg = <0x68>;
};
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index a4cc52214dbd..7d5e49e40b0d 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -110,22 +110,22 @@
reg = <0x0 0x0 0x0 0x800000>;
};
- partition@0x800000 {
+ partition@800000 {
label = "u-boot";
reg = <0x0 0x800000 0x0 0x200000>;
};
- partition@0xa00000 {
+ partition@a00000 {
label = "u-boot-env";
reg = <0x0 0xa00000 0x0 0x200000>;
};
- partition@0xc00000 {
+ partition@c00000 {
label = "boot";
reg = <0x0 0xc00000 0x0 0x4000000>;
};
- partition@0x8c00000 {
+ partition@8c00000 {
label = "system";
reg = <0x0 0x4c00000 0x1 0xfb400000>;
};
diff --git a/arch/nios2/boot/dts/3c120_devboard.dts b/arch/nios2/boot/dts/3c120_devboard.dts
index 36ccdf05837d..56f4b5df6d65 100644
--- a/arch/nios2/boot/dts/3c120_devboard.dts
+++ b/arch/nios2/boot/dts/3c120_devboard.dts
@@ -29,7 +29,7 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu: cpu@0x0 {
+ cpu: cpu@0 {
device_type = "cpu";
compatible = "altr,nios2-1.0";
reg = <0x00000000>;
@@ -69,7 +69,7 @@
compatible = "altr,avalon", "simple-bus";
bus-frequency = <125000000>;
- pb_cpu_to_io: bridge@0x8000000 {
+ pb_cpu_to_io: bridge@8000000 {
compatible = "simple-bus";
reg = <0x08000000 0x00800000>;
#address-cells = <1>;
@@ -83,7 +83,7 @@
<0x00008000 0x08008000 0x00000020>,
<0x00400000 0x08400000 0x00000020>;
- timer_1ms: timer@0x400000 {
+ timer_1ms: timer@400000 {
compatible = "altr,timer-1.0";
reg = <0x00400000 0x00000020>;
interrupt-parent = <&cpu>;
@@ -91,7 +91,7 @@
clock-frequency = <125000000>;
};
- timer_0: timer@0x8000 {
+ timer_0: timer@8000 {
compatible = "altr,timer-1.0";
reg = < 0x00008000 0x00000020 >;
interrupt-parent = < &cpu >;
@@ -99,14 +99,14 @@
clock-frequency = < 125000000 >;
};
- jtag_uart: serial@0x4d50 {
+ jtag_uart: serial@4d50 {
compatible = "altr,juart-1.0";
reg = <0x00004d50 0x00000008>;
interrupt-parent = <&cpu>;
interrupts = <1>;
};
- tse_mac: ethernet@0x4000 {
+ tse_mac: ethernet@4000 {
compatible = "altr,tse-1.0";
reg = <0x00004000 0x00000400>,
<0x00004400 0x00000040>,
@@ -133,7 +133,7 @@
};
};
- uart: serial@0x4c80 {
+ uart: serial@4c80 {
compatible = "altr,uart-1.0";
reg = <0x00004c80 0x00000020>;
interrupt-parent = <&cpu>;
@@ -143,7 +143,7 @@
};
};
- cfi_flash_64m: flash@0x0 {
+ cfi_flash_64m: flash@0 {
compatible = "cfi-flash";
reg = <0x00000000 0x04000000>;
bank-width = <2>;
diff --git a/arch/powerpc/boot/dts/a3m071.dts b/arch/powerpc/boot/dts/a3m071.dts
index bf81b8f9704c..187ce458d03a 100644
--- a/arch/powerpc/boot/dts/a3m071.dts
+++ b/arch/powerpc/boot/dts/a3m071.dts
@@ -105,24 +105,24 @@
reg = <0 0x0 0x02000000>;
compatible = "cfi-flash";
bank-width = <2>;
- partition@0x0 {
+ partition@0 {
label = "u-boot";
reg = <0x00000000 0x00040000>;
read-only;
};
- partition@0x00040000 {
+ partition@40000 {
label = "env";
reg = <0x00040000 0x00020000>;
};
- partition@0x00060000 {
+ partition@60000 {
label = "dtb";
reg = <0x00060000 0x00020000>;
};
- partition@0x00080000 {
+ partition@80000 {
label = "kernel";
reg = <0x00080000 0x00500000>;
};
- partition@0x00580000 {
+ partition@580000 {
label = "root";
reg = <0x00580000 0x00A80000>;
};
diff --git a/arch/powerpc/boot/dts/akebono.dts b/arch/powerpc/boot/dts/akebono.dts
index e61d5dc598c1..746779202a12 100644
--- a/arch/powerpc/boot/dts/akebono.dts
+++ b/arch/powerpc/boot/dts/akebono.dts
@@ -216,7 +216,7 @@
interrupts = <39 2>;
};
- IIC0: i2c@00000000 {
+ IIC0: i2c@0 {
compatible = "ibm,iic-476gtr", "ibm,iic";
reg = <0x0 0x00000020>;
interrupt-parent = <&MPIC>;
@@ -229,7 +229,7 @@
};
};
- IIC1: i2c@00000100 {
+ IIC1: i2c@100 {
compatible = "ibm,iic-476gtr", "ibm,iic";
reg = <0x100 0x00000020>;
interrupt-parent = <&MPIC>;
diff --git a/arch/powerpc/boot/dts/c2k.dts b/arch/powerpc/boot/dts/c2k.dts
index 1e32903cb0a8..27f169e3ade9 100644
--- a/arch/powerpc/boot/dts/c2k.dts
+++ b/arch/powerpc/boot/dts/c2k.dts
@@ -276,14 +276,14 @@
>;
};
- cpu-error@0070 {
+ cpu-error@70 {
compatible = "marvell,mv64360-cpu-error";
reg = <0x0070 0x10 0x0128 0x28>;
interrupts = <3>;
interrupt-parent = <&PIC>;
};
- sram-ctrl@0380 {
+ sram-ctrl@380 {
compatible = "marvell,mv64360-sram-ctrl";
reg = <0x0380 0x80>;
interrupts = <13>;
@@ -311,7 +311,7 @@
interrupt-parent = <&PIC>;
};
/* Devices attached to the device controller */
- devicebus@045c {
+ devicebus@45c {
#address-cells = <2>;
#size-cells = <1>;
compatible = "marvell,mv64306-devctrl";
diff --git a/arch/powerpc/boot/dts/currituck.dts b/arch/powerpc/boot/dts/currituck.dts
index 4191e1850ea1..f2ad5815f08d 100644
--- a/arch/powerpc/boot/dts/currituck.dts
+++ b/arch/powerpc/boot/dts/currituck.dts
@@ -108,7 +108,7 @@
reg = <0x50000000 0x4>;
};
- IIC0: i2c@00000000 {
+ IIC0: i2c@0 {
compatible = "ibm,iic-currituck", "ibm,iic";
reg = <0x0 0x00000014>;
interrupt-parent = <&MPIC>;
diff --git a/arch/powerpc/boot/dts/fsl/mpc8568mds.dts b/arch/powerpc/boot/dts/fsl/mpc8568mds.dts
index 01706a339603..bc3e8039bdc7 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/fsl/mpc8568mds.dts
@@ -126,7 +126,7 @@
par_io@e0100 {
num-ports = <7>;
- pio1: ucc_pin@01 {
+ pio1: ucc_pin@1 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
@@ -154,7 +154,7 @@
0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
};
- pio2: ucc_pin@02 {
+ pio2: ucc_pin@2 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
@@ -228,22 +228,22 @@
/* These are the same PHYs as on
* gianfar's MDIO bus */
- qe_phy0: ethernet-phy@07 {
+ qe_phy0: ethernet-phy@7 {
interrupt-parent = <&mpic>;
interrupts = <1 1 0 0>;
reg = <0x7>;
};
- qe_phy1: ethernet-phy@01 {
+ qe_phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <2 1 0 0>;
reg = <0x1>;
};
- qe_phy2: ethernet-phy@02 {
+ qe_phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <1 1 0 0>;
reg = <0x2>;
};
- qe_phy3: ethernet-phy@03 {
+ qe_phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <2 1 0 0>;
reg = <0x3>;
diff --git a/arch/powerpc/boot/dts/fsl/mpc8569mds.dts b/arch/powerpc/boot/dts/fsl/mpc8569mds.dts
index 76b2bd6f7742..d8367ceddea6 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8569mds.dts
+++ b/arch/powerpc/boot/dts/fsl/mpc8569mds.dts
@@ -141,7 +141,7 @@
gpio-controller;
};
- pio1: ucc_pin@01 {
+ pio1: ucc_pin@1 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
@@ -161,7 +161,7 @@
0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */
};
- pio2: ucc_pin@02 {
+ pio2: ucc_pin@2 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
@@ -181,7 +181,7 @@
0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */
};
- pio3: ucc_pin@03 {
+ pio3: ucc_pin@3 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
@@ -201,7 +201,7 @@
0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */
};
- pio4: ucc_pin@04 {
+ pio4: ucc_pin@4 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
@@ -272,30 +272,30 @@
reg = <0x2120 0x18>;
compatible = "fsl,ucc-mdio";
- qe_phy0: ethernet-phy@07 {
+ qe_phy0: ethernet-phy@7 {
interrupt-parent = <&mpic>;
interrupts = <1 1 0 0>;
reg = <0x7>;
};
- qe_phy1: ethernet-phy@01 {
+ qe_phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <2 1 0 0>;
reg = <0x1>;
};
- qe_phy2: ethernet-phy@02 {
+ qe_phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <3 1 0 0>;
reg = <0x2>;
};
- qe_phy3: ethernet-phy@03 {
+ qe_phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <4 1 0 0>;
reg = <0x3>;
};
- qe_phy5: ethernet-phy@04 {
+ qe_phy5: ethernet-phy@4 {
reg = <0x04>;
};
- qe_phy7: ethernet-phy@06 {
+ qe_phy7: ethernet-phy@6 {
reg = <0x6>;
};
tbi1: tbi-phy@11 {
diff --git a/arch/powerpc/boot/dts/fsl/p1021mds.dts b/arch/powerpc/boot/dts/fsl/p1021mds.dts
index 291454c75dda..1047802f4d2a 100644
--- a/arch/powerpc/boot/dts/fsl/p1021mds.dts
+++ b/arch/powerpc/boot/dts/fsl/p1021mds.dts
@@ -202,7 +202,7 @@
ranges = <0x0 0xe0100 0x60>;
device_type = "par_io";
num-ports = <3>;
- pio1: ucc_pin@01 {
+ pio1: ucc_pin@1 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
@@ -225,7 +225,7 @@
0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
};
- pio2: ucc_pin@02 {
+ pio2: ucc_pin@2 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
@@ -296,7 +296,7 @@
interrupts = <4 1 0 0>;
reg = <0x0>;
};
- qe_phy1: ethernet-phy@03 {
+ qe_phy1: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <5 1 0 0>;
reg = <0x3>;
diff --git a/arch/powerpc/boot/dts/fsl/p1025rdb.dtsi b/arch/powerpc/boot/dts/fsl/p1025rdb.dtsi
index d44bb12debb0..0a5434a631c3 100644
--- a/arch/powerpc/boot/dts/fsl/p1025rdb.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1025rdb.dtsi
@@ -245,7 +245,7 @@
ranges = <0x0 0xe0100 0x60>;
device_type = "par_io";
num-ports = <3>;
- pio1: ucc_pin@01 {
+ pio1: ucc_pin@1 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
@@ -268,7 +268,7 @@
0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
};
- pio2: ucc_pin@02 {
+ pio2: ucc_pin@2 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
@@ -283,7 +283,7 @@
0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
};
- pio3: ucc_pin@03 {
+ pio3: ucc_pin@3 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x0 0x16 0x2 0x0 0x2 0x0 /* SER7_CD_B*/
@@ -293,7 +293,7 @@
0x0 0x15 0x1 0x0 0x2 0x0>; /* SER7_TXD0*/
};
- pio4: ucc_pin@04 {
+ pio4: ucc_pin@4 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x1 0x0 0x2 0x0 0x2 0x0 /* SER3_CD_B*/
diff --git a/arch/powerpc/boot/dts/fsl/p1025rdb_32b.dts b/arch/powerpc/boot/dts/fsl/p1025rdb_32b.dts
index b15acbaea34b..ea33b57f8774 100644
--- a/arch/powerpc/boot/dts/fsl/p1025rdb_32b.dts
+++ b/arch/powerpc/boot/dts/fsl/p1025rdb_32b.dts
@@ -106,7 +106,7 @@
interrupts = <4 1 0 0>;
reg = <0x6>;
};
- qe_phy1: ethernet-phy@03 {
+ qe_phy1: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <5 1 0 0>;
reg = <0x3>;
diff --git a/arch/powerpc/boot/dts/fsl/p1025twr.dtsi b/arch/powerpc/boot/dts/fsl/p1025twr.dtsi
index 08816fb474f5..ab75b8f29ae2 100644
--- a/arch/powerpc/boot/dts/fsl/p1025twr.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1025twr.dtsi
@@ -172,7 +172,7 @@
ranges = <0x0 0xe0100 0x60>;
device_type = "par_io";
num-ports = <3>;
- pio1: ucc_pin@01 {
+ pio1: ucc_pin@1 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
@@ -195,7 +195,7 @@
0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
};
- pio2: ucc_pin@02 {
+ pio2: ucc_pin@2 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
@@ -210,7 +210,7 @@
0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
};
- pio3: ucc_pin@03 {
+ pio3: ucc_pin@3 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x0 0x16 0x2 0x0 0x2 0x0 /* SER7_CD_B*/
@@ -220,7 +220,7 @@
0x0 0x15 0x1 0x0 0x2 0x0>; /* SER7_TXD0*/
};
- pio4: ucc_pin@04 {
+ pio4: ucc_pin@4 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x1 0x0 0x2 0x0 0x2 0x0 /* SER3_CD_B*/
diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb.dts b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
index 621f2c6ee6ad..65ff34c49025 100644
--- a/arch/powerpc/boot/dts/fsl/t1040rdb.dts
+++ b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
@@ -61,7 +61,7 @@
};
mdio@fc000 {
- phy_sgmii_2: ethernet-phy@03 {
+ phy_sgmii_2: ethernet-phy@3 {
reg = <0x03>;
};
};
diff --git a/arch/powerpc/boot/dts/fsl/t1042d4rdb.dts b/arch/powerpc/boot/dts/fsl/t1042d4rdb.dts
index fcd2aeb5b8ac..4fa15f48a4c3 100644
--- a/arch/powerpc/boot/dts/fsl/t1042d4rdb.dts
+++ b/arch/powerpc/boot/dts/fsl/t1042d4rdb.dts
@@ -77,23 +77,23 @@
};
mdio0: mdio@fc000 {
- phy_sgmii_0: ethernet-phy@02 {
+ phy_sgmii_0: ethernet-phy@2 {
reg = <0x02>;
};
- phy_sgmii_1: ethernet-phy@03 {
+ phy_sgmii_1: ethernet-phy@3 {
reg = <0x03>;
};
- phy_sgmii_2: ethernet-phy@01 {
+ phy_sgmii_2: ethernet-phy@1 {
reg = <0x01>;
};
- phy_rgmii_0: ethernet-phy@04 {
+ phy_rgmii_0: ethernet-phy@4 {
reg = <0x04>;
};
- phy_rgmii_1: ethernet-phy@05 {
+ phy_rgmii_1: ethernet-phy@5 {
reg = <0x05>;
};
};
diff --git a/arch/powerpc/boot/dts/fsl/t1042rdb.dts b/arch/powerpc/boot/dts/fsl/t1042rdb.dts
index 2c138627b1b4..3ebb712224cb 100644
--- a/arch/powerpc/boot/dts/fsl/t1042rdb.dts
+++ b/arch/powerpc/boot/dts/fsl/t1042rdb.dts
@@ -59,7 +59,7 @@
};
mdio@fc000 {
- phy_sgmii_2: ethernet-phy@03 {
+ phy_sgmii_2: ethernet-phy@3 {
reg = <0x03>;
};
};
diff --git a/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi b/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
index 5fdddbd2a62b..099a598c74c0 100644
--- a/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
@@ -148,15 +148,15 @@
};
mdio0: mdio@fc000 {
- phy_sgmii_2: ethernet-phy@03 {
+ phy_sgmii_2: ethernet-phy@3 {
reg = <0x03>;
};
- phy_rgmii_0: ethernet-phy@01 {
+ phy_rgmii_0: ethernet-phy@1 {
reg = <0x01>;
};
- phy_rgmii_1: ethernet-phy@02 {
+ phy_rgmii_1: ethernet-phy@2 {
reg = <0x02>;
};
};
diff --git a/arch/powerpc/boot/dts/fsp2.dts b/arch/powerpc/boot/dts/fsp2.dts
index f10a64aeb83b..6560283c5aec 100644
--- a/arch/powerpc/boot/dts/fsp2.dts
+++ b/arch/powerpc/boot/dts/fsp2.dts
@@ -583,21 +583,21 @@
};
};
- OHCI1: ohci@02040000 {
+ OHCI1: ohci@2040000 {
compatible = "ohci-le";
reg = <0x02040000 0xa0>;
interrupt-parent = <&UIC1_3>;
interrupts = <28 0x8 29 0x8>;
};
- OHCI2: ohci@02080000 {
+ OHCI2: ohci@2080000 {
compatible = "ohci-le";
reg = <0x02080000 0xa0>;
interrupt-parent = <&UIC1_3>;
interrupts = <30 0x8 31 0x8>;
};
- EHCI: ehci@02000000 {
+ EHCI: ehci@2000000 {
compatible = "usb-ehci";
reg = <0x02000000 0xa4>;
interrupt-parent = <&UIC1_3>;
diff --git a/arch/powerpc/boot/dts/gamecube.dts b/arch/powerpc/boot/dts/gamecube.dts
index ef3be0e58b02..58d06c9ee08b 100644
--- a/arch/powerpc/boot/dts/gamecube.dts
+++ b/arch/powerpc/boot/dts/gamecube.dts
@@ -54,13 +54,13 @@
ranges = <0x0c000000 0x0c000000 0x00010000>;
interrupt-parent = <&PIC>;
- video@0c002000 {
+ video@c002000 {
compatible = "nintendo,flipper-vi";
reg = <0x0c002000 0x100>;
interrupts = <8>;
};
- processor-interface@0c003000 {
+ processor-interface@c003000 {
compatible = "nintendo,flipper-pi";
reg = <0x0c003000 0x100>;
@@ -71,7 +71,7 @@
};
};
- dsp@0c005000 {
+ dsp@c005000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "nintendo,flipper-dsp";
@@ -84,26 +84,26 @@
};
};
- disk@0c006000 {
+ disk@c006000 {
compatible = "nintendo,flipper-di";
reg = <0x0c006000 0x40>;
interrupts = <2>;
};
- audio@0c006c00 {
+ audio@c006c00 {
compatible = "nintendo,flipper-ai";
reg = <0x0c006c00 0x20>;
interrupts = <6>;
};
- gamepad-controller@0c006400 {
+ gamepad-controller@c006400 {
compatible = "nintendo,flipper-si";
reg = <0x0c006400 0x100>;
interrupts = <3>;
};
/* External Interface bus */
- exi@0c006800 {
+ exi@c006800 {
compatible = "nintendo,flipper-exi";
reg = <0x0c006800 0x40>;
virtual-reg = <0x0c006800>;
diff --git a/arch/powerpc/boot/dts/haleakala.dts b/arch/powerpc/boot/dts/haleakala.dts
index 2b256694eca6..cb16dad43c92 100644
--- a/arch/powerpc/boot/dts/haleakala.dts
+++ b/arch/powerpc/boot/dts/haleakala.dts
@@ -237,7 +237,7 @@
};
};
- PCIE0: pciex@0a0000000 {
+ PCIE0: pciex@a0000000 {
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
index 5ba7f01e2a29..2a3413221cc1 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -322,7 +322,7 @@
};
};
- PCIE0: pciex@0a0000000 {
+ PCIE0: pciex@a0000000 {
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
@@ -363,7 +363,7 @@
0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
};
- PCIE1: pciex@0c0000000 {
+ PCIE1: pciex@c0000000 {
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
diff --git a/arch/powerpc/boot/dts/kmeter1.dts b/arch/powerpc/boot/dts/kmeter1.dts
index 983aee185793..9fa33d9ba966 100644
--- a/arch/powerpc/boot/dts/kmeter1.dts
+++ b/arch/powerpc/boot/dts/kmeter1.dts
@@ -434,27 +434,27 @@
compatible = "fsl,ucc-mdio";
/* Piggy2 (UCC4, MDIO 0x00, RMII) */
- phy_piggy2: ethernet-phy@00 {
+ phy_piggy2: ethernet-phy@0 {
reg = <0x0>;
};
/* Eth-1 (UCC5, MDIO 0x08, RMII) */
- phy_eth1: ethernet-phy@08 {
+ phy_eth1: ethernet-phy@8 {
reg = <0x08>;
};
/* Eth-2 (UCC6, MDIO 0x09, RMII) */
- phy_eth2: ethernet-phy@09 {
+ phy_eth2: ethernet-phy@9 {
reg = <0x09>;
};
/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
- phy_eth3: ethernet-phy@0a {
+ phy_eth3: ethernet-phy@a {
reg = <0x0a>;
};
/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
- phy_eth4: ethernet-phy@0b {
+ phy_eth4: ethernet-phy@b {
reg = <0x0b>;
};
diff --git a/arch/powerpc/boot/dts/makalu.dts b/arch/powerpc/boot/dts/makalu.dts
index 63d48b632c84..bf8fe1629392 100644
--- a/arch/powerpc/boot/dts/makalu.dts
+++ b/arch/powerpc/boot/dts/makalu.dts
@@ -268,7 +268,7 @@
};
};
- PCIE0: pciex@0a0000000 {
+ PCIE0: pciex@a0000000 {
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
@@ -309,7 +309,7 @@
0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
};
- PCIE1: pciex@0c0000000 {
+ PCIE1: pciex@c0000000 {
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 0793cdf0d46e..49c7d657118a 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -186,7 +186,7 @@
device_type = "par_io";
num-ports = <7>;
- pio3: ucc_pin@03 {
+ pio3: ucc_pin@3 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 4 3 0 2 0 /* MDIO */
@@ -208,7 +208,7 @@
1 12 1 0 1 0 /* TX_EN */
1 13 2 0 1 0>; /* CRS */
};
- pio4: ucc_pin@04 {
+ pio4: ucc_pin@4 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 31 2 0 1 0 /* RX_CLK (CLK7) */
@@ -228,7 +228,7 @@
1 30 1 0 1 0 /* TX_EN */
1 31 2 0 1 0>; /* CRS */
};
- pio5: ucc_pin@05 {
+ pio5: ucc_pin@5 {
pio-map = <
/*
* open has
@@ -352,12 +352,12 @@
reg = <0x2320 0x18>;
compatible = "fsl,ucc-mdio";
- phy3: ethernet-phy@03 {
+ phy3: ethernet-phy@3 {
interrupt-parent = <&ipic>;
interrupts = <17 0x8>;
reg = <0x3>;
};
- phy4: ethernet-phy@04 {
+ phy4: ethernet-phy@4 {
interrupt-parent = <&ipic>;
interrupts = <18 0x8>;
reg = <0x4>;
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 91df1eb16667..647cae14c16d 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -175,7 +175,7 @@
gpio-controller;
};
- ucc2pio:ucc_pin@02 {
+ ucc2pio:ucc_pin@2 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 4 3 0 2 0 /* MDIO */
@@ -197,7 +197,7 @@
0 30 1 0 1 0 /* TX_EN */
0 31 2 0 1 0>; /* CRS */
};
- ucc3pio:ucc_pin@03 {
+ ucc3pio:ucc_pin@3 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 13 2 0 1 0 /* RX_CLK (CLK9) */
@@ -310,12 +310,12 @@
reg = <0x3120 0x18>;
compatible = "fsl,ucc-mdio";
- phy00:ethernet-phy@00 {
+ phy00:ethernet-phy@0 {
interrupt-parent = <&ipic>;
interrupts = <0>;
reg = <0x0>;
};
- phy04:ethernet-phy@04 {
+ phy04:ethernet-phy@4 {
interrupt-parent = <&ipic>;
interrupts = <0>;
reg = <0x4>;
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index ecb6ccd3a6aa..539fd9f72eda 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -228,7 +228,7 @@
gpio-controller;
};
- pio1: ucc_pin@01 {
+ pio1: ucc_pin@1 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 3 1 0 1 0 /* TxD0 */
@@ -255,7 +255,7 @@
2 9 1 0 3 0 /* GTX_CLK - CLK10 */
2 8 2 0 1 0>; /* GTX125 - CLK9 */
};
- pio2: ucc_pin@02 {
+ pio2: ucc_pin@2 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 17 1 0 1 0 /* TxD0 */
@@ -393,12 +393,12 @@
reg = <0x2120 0x18>;
compatible = "fsl,ucc-mdio";
- phy0: ethernet-phy@00 {
+ phy0: ethernet-phy@0 {
interrupt-parent = <&ipic>;
interrupts = <17 0x8>;
reg = <0x0>;
};
- phy1: ethernet-phy@01 {
+ phy1: ethernet-phy@1 {
interrupt-parent = <&ipic>;
interrupts = <18 0x8>;
reg = <0x1>;
diff --git a/arch/powerpc/boot/dts/sbc8548-altflash.dts b/arch/powerpc/boot/dts/sbc8548-altflash.dts
index 0b38a0defd2c..8967a56adad4 100644
--- a/arch/powerpc/boot/dts/sbc8548-altflash.dts
+++ b/arch/powerpc/boot/dts/sbc8548-altflash.dts
@@ -40,12 +40,12 @@
compatible = "intel,JS28F128", "cfi-flash";
bank-width = <4>;
device-width = <1>;
- partition@0x0 {
+ partition@0 {
label = "space";
/* FC000000 -> FFEFFFFF */
reg = <0x00000000 0x03f00000>;
};
- partition@0x03f00000 {
+ partition@3f00000 {
label = "bootloader";
/* FFF00000 -> FFFFFFFF */
reg = <0x03f00000 0x00100000>;
@@ -95,12 +95,12 @@
reg = <0x6 0x0 0x800000>;
bank-width = <1>;
device-width = <1>;
- partition@0x0 {
+ partition@0 {
label = "space";
/* EF800000 -> EFF9FFFF */
reg = <0x00000000 0x007a0000>;
};
- partition@0x7a0000 {
+ partition@7a0000 {
label = "bootloader";
/* EFFA0000 -> EFFFFFFF */
reg = <0x007a0000 0x00060000>;
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index 1df2a0955668..9bdb828a504e 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -38,12 +38,12 @@
reg = <0x0 0x0 0x800000>;
bank-width = <1>;
device-width = <1>;
- partition@0x0 {
+ partition@0 {
label = "space";
/* FF800000 -> FFF9FFFF */
reg = <0x00000000 0x007a0000>;
};
- partition@0x7a0000 {
+ partition@7a0000 {
label = "bootloader";
/* FFFA0000 -> FFFFFFFF */
reg = <0x007a0000 0x00060000>;
@@ -92,12 +92,12 @@
compatible = "intel,JS28F128", "cfi-flash";
bank-width = <4>;
device-width = <1>;
- partition@0x0 {
+ partition@0 {
label = "space";
/* EC000000 -> EFEFFFFF */
reg = <0x00000000 0x03f00000>;
};
- partition@0x03f00000 {
+ partition@3f00000 {
label = "bootloader";
/* EFF00000 -> EFFFFFFF */
reg = <0x03f00000 0x00100000>;
diff --git a/arch/powerpc/boot/dts/wii.dts b/arch/powerpc/boot/dts/wii.dts
index 77528c9a8dbd..17a5babb098d 100644
--- a/arch/powerpc/boot/dts/wii.dts
+++ b/arch/powerpc/boot/dts/wii.dts
@@ -65,14 +65,14 @@
0x0d800000 0x0d800000 0x00800000>;
interrupt-parent = <&PIC0>;
- video@0c002000 {
+ video@c002000 {
compatible = "nintendo,hollywood-vi",
"nintendo,flipper-vi";
reg = <0x0c002000 0x100>;
interrupts = <8>;
};
- processor-interface@0c003000 {
+ processor-interface@c003000 {
compatible = "nintendo,hollywood-pi",
"nintendo,flipper-pi";
reg = <0x0c003000 0x100>;
@@ -84,7 +84,7 @@
};
};
- dsp@0c005000 {
+ dsp@c005000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "nintendo,hollywood-dsp",
@@ -93,14 +93,14 @@
interrupts = <6>;
};
- gamepad-controller@0d006400 {
+ gamepad-controller@d006400 {
compatible = "nintendo,hollywood-si",
"nintendo,flipper-si";
reg = <0x0d006400 0x100>;
interrupts = <3>;
};
- audio@0c006c00 {
+ audio@c006c00 {
compatible = "nintendo,hollywood-ai",
"nintendo,flipper-ai";
reg = <0x0d006c00 0x20>;
@@ -108,7 +108,7 @@
};
/* External Interface bus */
- exi@0d006800 {
+ exi@d006800 {
compatible = "nintendo,hollywood-exi",
"nintendo,flipper-exi";
reg = <0x0d006800 0x40>;
@@ -116,7 +116,7 @@
interrupts = <4>;
};
- usb@0d040000 {
+ usb@d040000 {
compatible = "nintendo,hollywood-usb-ehci",
"usb-ehci";
reg = <0x0d040000 0x100>;
@@ -124,7 +124,7 @@
interrupt-parent = <&PIC1>;
};
- usb@0d050000 {
+ usb@d050000 {
compatible = "nintendo,hollywood-usb-ohci",
"usb-ohci";
reg = <0x0d050000 0x100>;
@@ -132,7 +132,7 @@
interrupt-parent = <&PIC1>;
};
- usb@0d060000 {
+ usb@d060000 {
compatible = "nintendo,hollywood-usb-ohci",
"usb-ohci";
reg = <0x0d060000 0x100>;
@@ -140,7 +140,7 @@
interrupt-parent = <&PIC1>;
};
- sd@0d070000 {
+ sd@d070000 {
compatible = "nintendo,hollywood-sdhci",
"sdhci";
reg = <0x0d070000 0x200>;
@@ -148,7 +148,7 @@
interrupt-parent = <&PIC1>;
};
- sdio@0d080000 {
+ sdio@d080000 {
compatible = "nintendo,hollywood-sdhci",
"sdhci";
reg = <0x0d080000 0x200>;
@@ -156,14 +156,14 @@
interrupt-parent = <&PIC1>;
};
- ipc@0d000000 {
+ ipc@d000000 {
compatible = "nintendo,hollywood-ipc";
reg = <0x0d000000 0x10>;
interrupts = <30>;
interrupt-parent = <&PIC1>;
};
- PIC1: pic1@0d800030 {
+ PIC1: pic1@d800030 {
#interrupt-cells = <1>;
compatible = "nintendo,hollywood-pic";
reg = <0x0d800030 0x10>;
@@ -171,7 +171,7 @@
interrupts = <14>;
};
- GPIO: gpio@0d8000c0 {
+ GPIO: gpio@d8000c0 {
#gpio-cells = <2>;
compatible = "nintendo,hollywood-gpio";
reg = <0x0d8000c0 0x40>;
@@ -203,12 +203,12 @@
*/
};
- control@0d800100 {
+ control@d800100 {
compatible = "nintendo,hollywood-control";
reg = <0x0d800100 0x300>;
};
- disk@0d806000 {
+ disk@d806000 {
compatible = "nintendo,hollywood-di";
reg = <0x0d806000 0x40>;
interrupts = <2>;
diff --git a/arch/xtensa/boot/dts/csp.dts b/arch/xtensa/boot/dts/csp.dts
index 885495460f7e..96c9bca1d737 100644
--- a/arch/xtensa/boot/dts/csp.dts
+++ b/arch/xtensa/boot/dts/csp.dts
@@ -44,7 +44,7 @@
compatible = "simple-bus";
ranges = <0x00000000 0xf0000000 0x10000000>;
- uart0: serial@0d000000 {
+ uart0: serial@d000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
clocks = <&osc>, <&osc>;
clock-names = "uart_clk", "pclk";
diff --git a/arch/xtensa/boot/dts/xtfpga-flash-128m.dtsi b/arch/xtensa/boot/dts/xtfpga-flash-128m.dtsi
index 9bf8bad1dd18..7b0cd356e0db 100644
--- a/arch/xtensa/boot/dts/xtfpga-flash-128m.dtsi
+++ b/arch/xtensa/boot/dts/xtfpga-flash-128m.dtsi
@@ -1,26 +1,26 @@
// SPDX-License-Identifier: GPL-2.0
/ {
soc {
- flash: flash@00000000 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x00000000 0x08000000>;
bank-width = <2>;
device-width = <2>;
- partition@0x0 {
+ partition@0 {
label = "data";
reg = <0x00000000 0x06000000>;
};
- partition@0x6000000 {
+ partition@6000000 {
label = "boot loader area";
reg = <0x06000000 0x00800000>;
};
- partition@0x6800000 {
+ partition@6800000 {
label = "kernel image";
reg = <0x06800000 0x017e0000>;
};
- partition@0x7fe0000 {
+ partition@7fe0000 {
label = "boot environment";
reg = <0x07fe0000 0x00020000>;
};
diff --git a/arch/xtensa/boot/dts/xtfpga-flash-16m.dtsi b/arch/xtensa/boot/dts/xtfpga-flash-16m.dtsi
index 40c2f81f7cb6..c5e56cf0f8df 100644
--- a/arch/xtensa/boot/dts/xtfpga-flash-16m.dtsi
+++ b/arch/xtensa/boot/dts/xtfpga-flash-16m.dtsi
@@ -1,26 +1,26 @@
// SPDX-License-Identifier: GPL-2.0
/ {
soc {
- flash: flash@08000000 {
+ flash: flash@8000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x08000000 0x01000000>;
bank-width = <2>;
device-width = <2>;
- partition@0x0 {
+ partition@0 {
label = "boot loader area";
reg = <0x00000000 0x00400000>;
};
- partition@0x400000 {
+ partition@400000 {
label = "kernel image";
reg = <0x00400000 0x00600000>;
};
- partition@0xa00000 {
+ partition@a00000 {
label = "data";
reg = <0x00a00000 0x005e0000>;
};
- partition@0xfe0000 {
+ partition@fe0000 {
label = "boot environment";
reg = <0x00fe0000 0x00020000>;
};
diff --git a/arch/xtensa/boot/dts/xtfpga-flash-4m.dtsi b/arch/xtensa/boot/dts/xtfpga-flash-4m.dtsi
index fb8d3a9f33c2..ad0d2ec45447 100644
--- a/arch/xtensa/boot/dts/xtfpga-flash-4m.dtsi
+++ b/arch/xtensa/boot/dts/xtfpga-flash-4m.dtsi
@@ -1,18 +1,18 @@
// SPDX-License-Identifier: GPL-2.0
/ {
soc {
- flash: flash@08000000 {
+ flash: flash@8000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x08000000 0x00400000>;
bank-width = <2>;
device-width = <2>;
- partition@0x0 {
+ partition@0 {
label = "boot loader area";
reg = <0x00000000 0x003f0000>;
};
- partition@0x3f0000 {
+ partition@3f0000 {
label = "boot environment";
reg = <0x003f0000 0x00010000>;
};
diff --git a/arch/xtensa/boot/dts/xtfpga.dtsi b/arch/xtensa/boot/dts/xtfpga.dtsi
index 1090528825ec..5ede496ed9be 100644
--- a/arch/xtensa/boot/dts/xtfpga.dtsi
+++ b/arch/xtensa/boot/dts/xtfpga.dtsi
@@ -54,7 +54,7 @@
reg = <0x0d020004 0x4>;
};
- serial0: serial@0d050020 {
+ serial0: serial@d050020 {
device_type = "serial";
compatible = "ns16550a";
no-loopback-test;
@@ -66,7 +66,7 @@
clocks = <&osc>;
};
- enet0: ethoc@0d030000 {
+ enet0: ethoc@d030000 {
compatible = "opencores,ethoc";
reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
native-endian;
@@ -75,7 +75,7 @@
clocks = <&osc>;
};
- i2s0: xtfpga-i2s@0d080000 {
+ i2s0: xtfpga-i2s@d080000 {
#sound-dai-cells = <0>;
compatible = "cdns,xtfpga-i2s";
reg = <0x0d080000 0x40>;
@@ -83,7 +83,7 @@
clocks = <&cdce706 4>;
};
- i2c0: i2c-master@0d090000 {
+ i2c0: i2c-master@d090000 {
compatible = "opencores,i2c-ocores";
#address-cells = <1>;
#size-cells = <0>;
@@ -103,7 +103,7 @@
};
};
- spi0: spi-master@0d0a0000 {
+ spi0: spi-master@d0a0000 {
compatible = "cdns,xtfpga-spi";
#address-cells = <1>;
#size-cells = <0>;
--
2.11.0
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^ permalink raw reply related
* Re: [PATCH] leds: as3645a: Fix checkpatch warnings
From: Dan Murphy @ 2017-12-13 20:49 UTC (permalink / raw)
To: Jacek Anaszewski, robh+dt, mark.rutland, rpurdie, pavel,
sakari.ailus, laurent.pinchart
Cc: devicetree, linux-kernel, linux-leds
In-Reply-To: <98df06ef-9ee4-02b1-6d6b-f10b911a8d71@gmail.com>
Pavel and Laurent
On 12/13/2017 02:43 PM, Jacek Anaszewski wrote:
> Dan,
>
> On 12/13/2017 09:41 PM, Dan Murphy wrote:
>> Jacek
>>
>> On 12/13/2017 02:29 PM, Jacek Anaszewski wrote:
>>> Hi Dan,
>>>
>>> checkpatch.pl doesn't want to be mentioned in the patch subject :-)
>>>
>>
>> Ack
>>
>>> "WARNING: A patch subject line should describe the change not the tool
>>> that found it"
>>>
>>> Preferably I'd see two separate patches.
>>>
>>
>> So you want me to split them up? I have no issue with that.
>
> Yeah, it will be easier to come up with concise but meaningful
> subjects.
>
When I split these up can I add your Acked-by to each patch or would you prefer to resend your
Acked-by for each patch?
Dan
>>> Also, line length limit for the commit description is 75 characters.
>>> Please use whole available space.
>>>
>>
>>
>
--
------------------
Dan Murphy
^ permalink raw reply
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