* [PATCH v9 12/13] ASoC: add bindings for stm32 DFSDM filter
From: Arnaud Pouliquen @ 2017-12-14 8:58 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw, Maxime Coquelin,
Alexandre Torgue, arnaud.pouliquen-qxv4g6HH51o
In-Reply-To: <1513241885-32079-1-git-send-email-arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Add bindings that describes audio settings to support
Digital Filter for pulse density modulation(PDM) microphone.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
.../devicetree/bindings/sound/st,stm32-adfsdm.txt | 63 ++++++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt b/Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt
new file mode 100644
index 0000000..864f5b0
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt
@@ -0,0 +1,63 @@
+STMicroelectronics Audio Digital Filter Sigma Delta modulators(DFSDM)
+
+The DFSDM allows PDM microphones capture through SPI interface. The Audio
+interface is seems as a sub block of the DFSDM device.
+For details on DFSDM bindings refer to ../iio/adc/st,stm32-dfsdm-adc.txt
+
+Required properties:
+ - compatible: "st,stm32h7-dfsdm-dai".
+
+ - #sound-dai-cells : Must be equal to 0
+
+ - io-channels : phandle to iio dfsdm instance node.
+
+Example of a sound card using audio DFSDM node.
+
+ sound_card {
+ compatible = "audio-graph-card";
+
+ dais = <&cpu_port>;
+ };
+
+ dfsdm: dfsdm@40017000 {
+ compatible = "st,stm32h7-dfsdm";
+ reg = <0x40017000 0x400>;
+ clocks = <&rcc DFSDM1_CK>;
+ clock-names = "dfsdm";
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dfsdm_adc0: filter@0 {
+ compatible = "st,stm32-dfsdm-dmic";
+ reg = <0>;
+ interrupts = <110>;
+ dmas = <&dmamux1 101 0x400 0x00>;
+ dma-names = "rx";
+ st,adc-channels = <1>;
+ st,adc-channel-names = "dmic0";
+ st,adc-channel-types = "SPI_R";
+ st,adc-channel-clk-src = "CLKOUT";
+ st,filter-order = <5>;
+
+ dfsdm_dai0: dfsdm-dai {
+ compatible = "st,stm32h7-dfsdm-dai";
+ #sound-dai-cells = <0>;
+ io-channels = <&dfsdm_adc0 0>;
+ cpu_port: port {
+ dfsdm_endpoint: endpoint {
+ remote-endpoint = <&dmic0_endpoint>;
+ };
+ };
+ };
+ };
+
+ dmic0: dmic@0 {
+ compatible = "dmic-codec";
+ #sound-dai-cells = <0>;
+ port {
+ dmic0_endpoint: endpoint {
+ remote-endpoint = <&dfsdm_endpoint>;
+ };
+ };
+ };
--
2.7.4
--
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^ permalink raw reply related
* [PATCH v9 11/13] IIO: consumer: allow to set buffer sizes
From: Arnaud Pouliquen @ 2017-12-14 8:58 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw, Maxime Coquelin,
Alexandre Torgue, arnaud.pouliquen-qxv4g6HH51o
In-Reply-To: <1513241885-32079-1-git-send-email-arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Add iio consumer API to set buffer size and watermark according
to sysfs API.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
drivers/iio/buffer/industrialio-buffer-cb.c | 11 +++++++++++
include/linux/iio/consumer.h | 11 +++++++++++
2 files changed, 22 insertions(+)
diff --git a/drivers/iio/buffer/industrialio-buffer-cb.c b/drivers/iio/buffer/industrialio-buffer-cb.c
index 4847534..ea63c83 100644
--- a/drivers/iio/buffer/industrialio-buffer-cb.c
+++ b/drivers/iio/buffer/industrialio-buffer-cb.c
@@ -104,6 +104,17 @@ struct iio_cb_buffer *iio_channel_get_all_cb(struct device *dev,
}
EXPORT_SYMBOL_GPL(iio_channel_get_all_cb);
+int iio_channel_cb_set_buffer_watermark(struct iio_cb_buffer *cb_buff,
+ size_t watermark)
+{
+ if (!watermark)
+ return -EINVAL;
+ cb_buff->buffer.watermark = watermark;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(iio_channel_cb_set_buffer_watermark);
+
int iio_channel_start_all_cb(struct iio_cb_buffer *cb_buff)
{
return iio_update_buffers(cb_buff->indio_dev, &cb_buff->buffer,
diff --git a/include/linux/iio/consumer.h b/include/linux/iio/consumer.h
index 2017f35..9887f4f 100644
--- a/include/linux/iio/consumer.h
+++ b/include/linux/iio/consumer.h
@@ -134,6 +134,17 @@ struct iio_cb_buffer *iio_channel_get_all_cb(struct device *dev,
void *private),
void *private);
/**
+ * iio_channel_cb_set_buffer_watermark() - set the buffer watermark.
+ * @cb_buffer: The callback buffer from whom we want the channel
+ * information.
+ * @watermark: buffer watermark in bytes.
+ *
+ * This function allows to configure the buffer watermark.
+ */
+int iio_channel_cb_set_buffer_watermark(struct iio_cb_buffer *cb_buffer,
+ size_t watermark);
+
+/**
* iio_channel_release_all_cb() - release and unregister the callback.
* @cb_buffer: The callback buffer that was allocated.
*/
--
2.7.4
--
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^ permalink raw reply related
* [PATCH v9 10/13] IIO: ADC: add stm32 DFSDM support for PDM microphone
From: Arnaud Pouliquen @ 2017-12-14 8:58 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw, Maxime Coquelin,
Alexandre Torgue, arnaud.pouliquen-qxv4g6HH51o
In-Reply-To: <1513241885-32079-1-git-send-email-arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
This code offers a way to handle PDM audio microphones in
ASOC framework. Audio driver should use consumer API.
A specific management is implemented for DMA, with a
callback, to allows to handle audio buffers efficiently.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
---
V8 to V9
- Create stm32_dfsdm_dma_request
- Replace devm_of_platform_populate by of_platform_populate.
- Reorder probe and remove sequences.
.../ABI/testing/sysfs-bus-iio-dfsdm-adc-stm32 | 16 +
drivers/iio/adc/stm32-dfsdm-adc.c | 502 ++++++++++++++++++++-
include/linux/iio/adc/stm32-dfsdm-adc.h | 18 +
3 files changed, 529 insertions(+), 7 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-dfsdm-adc-stm32
create mode 100644 include/linux/iio/adc/stm32-dfsdm-adc.h
diff --git a/Documentation/ABI/testing/sysfs-bus-iio-dfsdm-adc-stm32 b/Documentation/ABI/testing/sysfs-bus-iio-dfsdm-adc-stm32
new file mode 100644
index 0000000..da98223
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-iio-dfsdm-adc-stm32
@@ -0,0 +1,16 @@
+What: /sys/bus/iio/devices/iio:deviceX/in_voltage_spi_clk_freq
+KernelVersion: 4.14
+Contact: arnaud.pouliquen-qxv4g6HH51o@public.gmane.org
+Description:
+ For audio purpose only.
+ Used by audio driver to set/get the spi input frequency.
+ This is mandatory if DFSDM is slave on SPI bus, to
+ provide information on the SPI clock frequency during runtime
+ Notice that the SPI frequency should be a multiple of sample
+ frequency to ensure the precision.
+ if DFSDM input is SPI master
+ Reading SPI clkout frequency,
+ error on writing
+ If DFSDM input is SPI Slave:
+ Reading returns value previously set.
+ Writing value before starting conversions.
\ No newline at end of file
diff --git a/drivers/iio/adc/stm32-dfsdm-adc.c b/drivers/iio/adc/stm32-dfsdm-adc.c
index 68b5920..b03ca3f 100644
--- a/drivers/iio/adc/stm32-dfsdm-adc.c
+++ b/drivers/iio/adc/stm32-dfsdm-adc.c
@@ -6,19 +6,23 @@
* Author: Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>.
*/
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/iio/buffer.h>
#include <linux/iio/hw-consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/module.h>
-#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include "stm32-dfsdm.h"
+#define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE)
+
/* Conversion timeout */
#define DFSDM_TIMEOUT_US 100000
#define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
@@ -58,6 +62,18 @@ struct stm32_dfsdm_adc {
struct completion completion;
u32 *buffer;
+ /* Audio specific */
+ unsigned int spi_freq; /* SPI bus clock frequency */
+ unsigned int sample_freq; /* Sample frequency after filter decimation */
+ int (*cb)(const void *data, size_t size, void *cb_priv);
+ void *cb_priv;
+
+ /* DMA */
+ u8 *rx_buf;
+ unsigned int bufi; /* Buffer current position */
+ unsigned int buf_sz; /* Buffer size */
+ struct dma_chan *dma_chan;
+ dma_addr_t dma_buf;
};
struct stm32_dfsdm_str2field {
@@ -351,10 +367,63 @@ int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
return 0;
}
+static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev,
+ uintptr_t priv,
+ const struct iio_chan_spec *chan,
+ char *buf)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+
+ return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq);
+}
+
+static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
+ uintptr_t priv,
+ const struct iio_chan_spec *chan,
+ const char *buf, size_t len)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
+ struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[adc->ch_id];
+ unsigned int sample_freq = adc->sample_freq;
+ unsigned int spi_freq;
+ int ret;
+
+ dev_err(&indio_dev->dev, "enter %s\n", __func__);
+ /* If DFSDM is master on SPI, SPI freq can not be updated */
+ if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
+ return -EPERM;
+
+ ret = kstrtoint(buf, 0, &spi_freq);
+ if (ret)
+ return ret;
+
+ if (!spi_freq)
+ return -EINVAL;
+
+ if (sample_freq) {
+ if (spi_freq % sample_freq)
+ dev_warn(&indio_dev->dev,
+ "Sampling rate not accurate (%d)\n",
+ spi_freq / (spi_freq / sample_freq));
+
+ ret = stm32_dfsdm_set_osrs(fl, 0, (spi_freq / sample_freq));
+ if (ret < 0) {
+ dev_err(&indio_dev->dev,
+ "No filter parameters that match!\n");
+ return ret;
+ }
+ }
+ adc->spi_freq = spi_freq;
+
+ return len;
+}
+
static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc, bool dma)
{
struct regmap *regmap = adc->dfsdm->regmap;
int ret;
+ unsigned int dma_en = 0, cont_en = 0;
ret = stm32_dfsdm_start_channel(adc->dfsdm, adc->ch_id);
if (ret < 0)
@@ -365,6 +434,24 @@ static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc, bool dma)
if (ret < 0)
goto stop_channels;
+ if (dma) {
+ /* Enable DMA transfer*/
+ dma_en = DFSDM_CR1_RDMAEN(1);
+ /* Enable conversion triggered by SPI clock*/
+ cont_en = DFSDM_CR1_RCONT(1);
+ }
+ /* Enable DMA transfer*/
+ ret = regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
+ DFSDM_CR1_RDMAEN_MASK, dma_en);
+ if (ret < 0)
+ goto stop_channels;
+
+ /* Enable conversion triggered by SPI clock*/
+ ret = regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
+ DFSDM_CR1_RCONT_MASK, cont_en);
+ if (ret < 0)
+ goto stop_channels;
+
ret = stm32_dfsdm_start_filter(adc->dfsdm, adc->fl_id);
if (ret < 0)
goto stop_channels;
@@ -398,6 +485,231 @@ static void stm32_dfsdm_stop_conv(struct stm32_dfsdm_adc *adc)
stm32_dfsdm_stop_channel(adc->dfsdm, adc->ch_id);
}
+static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev,
+ unsigned int val)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2;
+
+ /*
+ * DMA cyclic transfers are used, buffer is split into two periods.
+ * There should be :
+ * - always one buffer (period) DMA is working on
+ * - one buffer (period) driver pushed to ASoC side.
+ */
+ watermark = min(watermark, val * (unsigned int)(sizeof(u32)));
+ adc->buf_sz = watermark * 2;
+
+ return 0;
+}
+
+static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc)
+{
+ struct dma_tx_state state;
+ enum dma_status status;
+
+ status = dmaengine_tx_status(adc->dma_chan,
+ adc->dma_chan->cookie,
+ &state);
+ if (status == DMA_IN_PROGRESS) {
+ /* Residue is size in bytes from end of buffer */
+ unsigned int i = adc->buf_sz - state.residue;
+ unsigned int size;
+
+ /* Return available bytes */
+ if (i >= adc->bufi)
+ size = i - adc->bufi;
+ else
+ size = adc->buf_sz + i - adc->bufi;
+
+ return size;
+ }
+
+ return 0;
+}
+
+static void stm32_dfsdm_audio_dma_buffer_done(void *data)
+{
+ struct iio_dev *indio_dev = data;
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ int available = stm32_dfsdm_adc_dma_residue(adc);
+ size_t old_pos;
+
+ /*
+ * FIXME: In Kernel interface does not support cyclic DMA buffer,and
+ * offers only an interface to push data samples per samples.
+ * For this reason IIO buffer interface is not used and interface is
+ * bypassed using a private callback registered by ASoC.
+ * This should be a temporary solution waiting a cyclic DMA engine
+ * support in IIO.
+ */
+
+ dev_dbg(&indio_dev->dev, "%s: pos = %d, available = %d\n", __func__,
+ adc->bufi, available);
+ old_pos = adc->bufi;
+
+ while (available >= indio_dev->scan_bytes) {
+ u32 *buffer = (u32 *)&adc->rx_buf[adc->bufi];
+
+ /* Mask 8 LSB that contains the channel ID */
+ *buffer = (*buffer & 0xFFFFFF00) << 8;
+ available -= indio_dev->scan_bytes;
+ adc->bufi += indio_dev->scan_bytes;
+ if (adc->bufi >= adc->buf_sz) {
+ if (adc->cb)
+ adc->cb(&adc->rx_buf[old_pos],
+ adc->buf_sz - old_pos, adc->cb_priv);
+ adc->bufi = 0;
+ old_pos = 0;
+ }
+ }
+ if (adc->cb)
+ adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos,
+ adc->cb_priv);
+}
+
+static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ struct dma_async_tx_descriptor *desc;
+ dma_cookie_t cookie;
+ int ret;
+
+ if (!adc->dma_chan)
+ return -EINVAL;
+
+ dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
+ adc->buf_sz, adc->buf_sz / 2);
+
+ /* Prepare a DMA cyclic transaction */
+ desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
+ adc->dma_buf,
+ adc->buf_sz, adc->buf_sz / 2,
+ DMA_DEV_TO_MEM,
+ DMA_PREP_INTERRUPT);
+ if (!desc)
+ return -EBUSY;
+
+ desc->callback = stm32_dfsdm_audio_dma_buffer_done;
+ desc->callback_param = indio_dev;
+
+ cookie = dmaengine_submit(desc);
+ ret = dma_submit_error(cookie);
+ if (ret) {
+ dmaengine_terminate_all(adc->dma_chan);
+ return ret;
+ }
+
+ /* Issue pending DMA requests */
+ dma_async_issue_pending(adc->dma_chan);
+
+ return 0;
+}
+
+static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ int ret;
+
+ /* Reset adc buffer index */
+ adc->bufi = 0;
+
+ ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
+ if (ret < 0)
+ return ret;
+
+ ret = stm32_dfsdm_start_conv(adc, true);
+ if (ret) {
+ dev_err(&indio_dev->dev, "Can't start conversion\n");
+ goto stop_dfsdm;
+ }
+
+ if (adc->dma_chan) {
+ ret = stm32_dfsdm_adc_dma_start(indio_dev);
+ if (ret) {
+ dev_err(&indio_dev->dev, "Can't start DMA\n");
+ goto err_stop_conv;
+ }
+ }
+
+ return 0;
+
+err_stop_conv:
+ stm32_dfsdm_stop_conv(adc);
+stop_dfsdm:
+ stm32_dfsdm_stop_dfsdm(adc->dfsdm);
+
+ return ret;
+}
+
+static int stm32_dfsdm_predisable(struct iio_dev *indio_dev)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+
+ if (adc->dma_chan)
+ dmaengine_terminate_all(adc->dma_chan);
+
+ stm32_dfsdm_stop_conv(adc);
+
+ stm32_dfsdm_stop_dfsdm(adc->dfsdm);
+
+ return 0;
+}
+
+static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = {
+ .postenable = &stm32_dfsdm_postenable,
+ .predisable = &stm32_dfsdm_predisable,
+};
+
+/**
+ * stm32_dfsdm_get_buff_cb() - register a callback that will be called when
+ * DMA transfer period is achieved.
+ *
+ * @iio_dev: Handle to IIO device.
+ * @cb: Pointer to callback function:
+ * - data: pointer to data buffer
+ * - size: size in byte of the data buffer
+ * - private: pointer to consumer private structure.
+ * @private: Pointer to consumer private structure.
+ */
+int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
+ int (*cb)(const void *data, size_t size,
+ void *private),
+ void *private)
+{
+ struct stm32_dfsdm_adc *adc;
+
+ if (!iio_dev)
+ return -EINVAL;
+ adc = iio_priv(iio_dev);
+
+ adc->cb = cb;
+ adc->cb_priv = private;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb);
+
+/**
+ * stm32_dfsdm_release_buff_cb - unregister buffer callback
+ *
+ * @iio_dev: Handle to IIO device.
+ */
+int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev)
+{
+ struct stm32_dfsdm_adc *adc;
+
+ if (!iio_dev)
+ return -EINVAL;
+ adc = iio_priv(iio_dev);
+
+ adc->cb = NULL;
+ adc->cb_priv = NULL;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb);
+
static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, int *res)
{
@@ -453,15 +765,41 @@ static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
{
struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
+ struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[adc->ch_id];
+ unsigned int spi_freq = adc->spi_freq;
int ret = -EINVAL;
- if (mask == IIO_CHAN_INFO_OVERSAMPLING_RATIO) {
+ switch (mask) {
+ case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
ret = stm32_dfsdm_set_osrs(fl, 0, val);
if (!ret)
adc->oversamp = val;
+
+ return ret;
+
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ if (!val)
+ return -EINVAL;
+ if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
+ spi_freq = adc->dfsdm->spi_master_freq;
+
+ if (spi_freq % val)
+ dev_warn(&indio_dev->dev,
+ "Sampling rate not accurate (%d)\n",
+ spi_freq / (spi_freq / val));
+
+ ret = stm32_dfsdm_set_osrs(fl, 0, (spi_freq / val));
+ if (ret < 0) {
+ dev_err(&indio_dev->dev,
+ "Not able to find parameter that match!\n");
+ return ret;
+ }
+ adc->sample_freq = val;
+
+ return 0;
}
- return ret;
+ return -EINVAL;
}
static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
@@ -494,11 +832,22 @@ static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
*val = adc->oversamp;
return IIO_VAL_INT;
+
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ *val = adc->sample_freq;
+
+ return IIO_VAL_INT;
}
return -EINVAL;
}
+static const struct iio_info stm32_dfsdm_info_audio = {
+ .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
+ .read_raw = stm32_dfsdm_read_raw,
+ .write_raw = stm32_dfsdm_write_raw,
+};
+
static const struct iio_info stm32_dfsdm_info_adc = {
.read_raw = stm32_dfsdm_read_raw,
.write_raw = stm32_dfsdm_write_raw,
@@ -531,6 +880,70 @@ static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
return IRQ_HANDLED;
}
+/*
+ * Define external info for SPI Frequency and audio sampling rate that can be
+ * configured by ASoC driver through consumer.h API
+ */
+static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = {
+ /* spi_clk_freq : clock freq on SPI/manchester bus used by channel */
+ {
+ .name = "spi_clk_freq",
+ .shared = IIO_SHARED_BY_TYPE,
+ .read = dfsdm_adc_audio_get_spiclk,
+ .write = dfsdm_adc_audio_set_spiclk,
+ },
+ {},
+};
+
+static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+
+ if (adc->dma_chan) {
+ dma_free_coherent(adc->dma_chan->device->dev,
+ DFSDM_DMA_BUFFER_SIZE,
+ adc->rx_buf, adc->dma_buf);
+ dma_release_channel(adc->dma_chan);
+ }
+}
+
+static int stm32_dfsdm_dma_request(struct iio_dev *indio_dev)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ struct dma_slave_config config = {
+ .src_addr = (dma_addr_t)adc->dfsdm->phys_base +
+ DFSDM_RDATAR(adc->fl_id),
+ .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
+ };
+ int ret;
+
+ adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx");
+ if (!adc->dma_chan)
+ return -EINVAL;
+
+ adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
+ DFSDM_DMA_BUFFER_SIZE,
+ &adc->dma_buf, GFP_KERNEL);
+ if (!adc->rx_buf) {
+ ret = -ENOMEM;
+ goto err_release;
+ }
+
+ ret = dmaengine_slave_config(adc->dma_chan, &config);
+ if (ret)
+ goto err_free;
+
+ return 0;
+
+err_free:
+ dma_free_coherent(adc->dma_chan->device->dev, DFSDM_DMA_BUFFER_SIZE,
+ adc->rx_buf, adc->dma_buf);
+err_release:
+ dma_release_channel(adc->dma_chan);
+
+ return ret;
+}
+
static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
struct iio_chan_spec *ch)
{
@@ -551,7 +964,12 @@ static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
- ch->scan_type.sign = 'u';
+ if (adc->dev_data->type == DFSDM_AUDIO) {
+ ch->scan_type.sign = 's';
+ ch->ext_info = dfsdm_adc_audio_ext_info;
+ } else {
+ ch->scan_type.sign = 'u';
+ }
ch->scan_type.realbits = 24;
ch->scan_type.storagebits = 32;
adc->ch_id = ch->channel;
@@ -560,6 +978,39 @@ static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
&adc->dfsdm->ch_list[ch->channel]);
}
+static int stm32_dfsdm_audio_init(struct iio_dev *indio_dev)
+{
+ struct iio_chan_spec *ch;
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ struct stm32_dfsdm_channel *d_ch;
+ int ret;
+
+ indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
+ indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops;
+
+ ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL);
+ if (!ch)
+ return -ENOMEM;
+
+ ch->scan_index = 0;
+
+ ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch);
+ if (ret < 0) {
+ dev_err(&indio_dev->dev, "Channels init failed\n");
+ return ret;
+ }
+ ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ);
+
+ d_ch = &adc->dfsdm->ch_list[adc->ch_id];
+ if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
+ adc->spi_freq = adc->dfsdm->spi_master_freq;
+
+ indio_dev->num_channels = 1;
+ indio_dev->channels = ch;
+
+ return stm32_dfsdm_dma_request(indio_dev);
+}
+
static int stm32_dfsdm_adc_init(struct iio_dev *indio_dev)
{
struct iio_chan_spec *ch;
@@ -612,11 +1063,20 @@ static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
.init = stm32_dfsdm_adc_init,
};
+static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = {
+ .type = DFSDM_AUDIO,
+ .init = stm32_dfsdm_audio_init,
+};
+
static const struct of_device_id stm32_dfsdm_adc_match[] = {
{
.compatible = "st,stm32-dfsdm-adc",
.data = &stm32h7_dfsdm_adc_data,
},
+ {
+ .compatible = "st,stm32-dfsdm-dmic",
+ .data = &stm32h7_dfsdm_audio_data,
+ },
{}
};
@@ -667,8 +1127,13 @@ static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
if (!name)
return -ENOMEM;
- iio->info = &stm32_dfsdm_info_adc;
- snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
+ if (dev_data->type == DFSDM_AUDIO) {
+ iio->info = &stm32_dfsdm_info_audio;
+ snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id);
+ } else {
+ iio->info = &stm32_dfsdm_info_adc;
+ snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
+ }
iio->name = name;
/*
@@ -700,7 +1165,27 @@ static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
if (ret < 0)
return ret;
- return iio_device_register(iio);
+ ret = iio_device_register(iio);
+ if (ret < 0)
+ goto err_cleanup;
+
+ dev_err(dev, "of_platform_populate\n");
+ if (dev_data->type == DFSDM_AUDIO) {
+ ret = of_platform_populate(np, NULL, NULL, dev);
+ if (ret < 0) {
+ dev_err(dev, "Failed to find an audio DAI\n");
+ goto err_unregister;
+ }
+ }
+
+ return 0;
+
+err_unregister:
+ iio_device_unregister(iio);
+err_cleanup:
+ stm32_dfsdm_dma_release(iio);
+
+ return ret;
}
static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
@@ -708,7 +1193,10 @@ static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
struct stm32_dfsdm_adc *adc = platform_get_drvdata(pdev);
struct iio_dev *indio_dev = iio_priv_to_dev(adc);
+ if (adc->dev_data->type == DFSDM_AUDIO)
+ of_platform_depopulate(&pdev->dev);
iio_device_unregister(indio_dev);
+ stm32_dfsdm_dma_release(indio_dev);
return 0;
}
diff --git a/include/linux/iio/adc/stm32-dfsdm-adc.h b/include/linux/iio/adc/stm32-dfsdm-adc.h
new file mode 100644
index 0000000..e7dc7a5
--- /dev/null
+++ b/include/linux/iio/adc/stm32-dfsdm-adc.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This file discribe the STM32 DFSDM IIO driver API for audio part
+ *
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>.
+ */
+
+#ifndef STM32_DFSDM_ADC_H
+#define STM32_DFSDM_ADC_H
+
+int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
+ int (*cb)(const void *data, size_t size,
+ void *private),
+ void *private);
+int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev);
+
+#endif
--
2.7.4
^ permalink raw reply related
* [PATCH v9 09/13] IIO: ADC: add STM32 DFSDM sigma delta ADC support
From: Arnaud Pouliquen @ 2017-12-14 8:58 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw, Maxime Coquelin,
Alexandre Torgue, arnaud.pouliquen-qxv4g6HH51o
In-Reply-To: <1513241885-32079-1-git-send-email-arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Add DFSDM driver to handle sigma delta ADC.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
drivers/iio/adc/Kconfig | 13 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/stm32-dfsdm-adc.c | 728 ++++++++++++++++++++++++++++++++++++++
3 files changed, 742 insertions(+)
create mode 100644 drivers/iio/adc/stm32-dfsdm-adc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index b729ae0..98ca30b 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -677,6 +677,19 @@ config STM32_DFSDM_CORE
This driver can also be built as a module. If so, the module
will be called stm32-dfsdm-core.
+config STM32_DFSDM_ADC
+ tristate "STMicroelectronics STM32 dfsdm adc"
+ depends on (ARCH_STM32 && OF) || COMPILE_TEST
+ select STM32_DFSDM_CORE
+ select REGMAP_MMIO
+ select IIO_BUFFER_HW_CONSUMER
+ help
+ Select this option to support ADCSigma delta modulator for
+ STMicroelectronics STM32 digital filter for sigma delta converter.
+
+ This driver can also be built as a module. If so, the module
+ will be called stm32-dfsdm-adc.
+
config STX104
tristate "Apex Embedded Systems STX104 driver"
depends on PC104 && X86 && ISA_BUS_API
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index b52d0a0..c4f5d15 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -64,6 +64,7 @@ obj-$(CONFIG_SUN4I_GPADC) += sun4i-gpadc-iio.o
obj-$(CONFIG_STM32_ADC_CORE) += stm32-adc-core.o
obj-$(CONFIG_STM32_ADC) += stm32-adc.o
obj-$(CONFIG_STM32_DFSDM_CORE) += stm32-dfsdm-core.o
+obj-$(CONFIG_STM32_DFSDM_ADC) += stm32-dfsdm-adc.o
obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o
obj-$(CONFIG_TI_ADC0832) += ti-adc0832.o
obj-$(CONFIG_TI_ADC084S021) += ti-adc084s021.o
diff --git a/drivers/iio/adc/stm32-dfsdm-adc.c b/drivers/iio/adc/stm32-dfsdm-adc.c
new file mode 100644
index 0000000..68b5920
--- /dev/null
+++ b/drivers/iio/adc/stm32-dfsdm-adc.c
@@ -0,0 +1,728 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This file is the ADC part of the STM32 DFSDM driver
+ *
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author: Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/iio/buffer.h>
+#include <linux/iio/hw-consumer.h>
+#include <linux/iio/iio.h>
+#include <linux/iio/sysfs.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include "stm32-dfsdm.h"
+
+/* Conversion timeout */
+#define DFSDM_TIMEOUT_US 100000
+#define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
+
+/* Oversampling attribute default */
+#define DFSDM_DEFAULT_OVERSAMPLING 100
+
+/* Oversampling max values */
+#define DFSDM_MAX_INT_OVERSAMPLING 256
+#define DFSDM_MAX_FL_OVERSAMPLING 1024
+
+/* Max sample resolutions */
+#define DFSDM_MAX_RES BIT(31)
+#define DFSDM_DATA_RES BIT(23)
+
+enum sd_converter_type {
+ DFSDM_AUDIO,
+ DFSDM_IIO,
+};
+
+struct stm32_dfsdm_dev_data {
+ int type;
+ int (*init)(struct iio_dev *indio_dev);
+ unsigned int num_channels;
+ const struct regmap_config *regmap_cfg;
+};
+
+struct stm32_dfsdm_adc {
+ struct stm32_dfsdm *dfsdm;
+ const struct stm32_dfsdm_dev_data *dev_data;
+ unsigned int fl_id;
+ unsigned int ch_id;
+
+ /* ADC specific */
+ unsigned int oversamp;
+ struct iio_hw_consumer *hwc;
+ struct completion completion;
+ u32 *buffer;
+
+};
+
+struct stm32_dfsdm_str2field {
+ const char *name;
+ unsigned int val;
+};
+
+/* DFSDM channel serial interface type */
+static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = {
+ { "SPI_R", 0 }, /* SPI with data on rising edge */
+ { "SPI_F", 1 }, /* SPI with data on falling edge */
+ { "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */
+ { "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */
+ {},
+};
+
+/* DFSDM channel clock source */
+static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = {
+ /* External SPI clock (CLKIN x) */
+ { "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL },
+ /* Internal SPI clock (CLKOUT) */
+ { "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL },
+ /* Internal SPI clock divided by 2 (falling edge) */
+ { "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING },
+ /* Internal SPI clock divided by 2 (falling edge) */
+ { "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING },
+ {},
+};
+
+static int stm32_dfsdm_str2val(const char *str,
+ const struct stm32_dfsdm_str2field *list)
+{
+ const struct stm32_dfsdm_str2field *p = list;
+
+ for (p = list; p && p->name; p++)
+ if (!strcmp(p->name, str))
+ return p->val;
+
+ return -EINVAL;
+}
+
+static int stm32_dfsdm_set_osrs(struct stm32_dfsdm_filter *fl,
+ unsigned int fast, unsigned int oversamp)
+{
+ unsigned int i, d, fosr, iosr;
+ u64 res;
+ s64 delta;
+ unsigned int m = 1; /* multiplication factor */
+ unsigned int p = fl->ford; /* filter order (ford) */
+
+ pr_debug("%s: Requested oversampling: %d\n", __func__, oversamp);
+ /*
+ * This function tries to compute filter oversampling and integrator
+ * oversampling, base on oversampling ratio requested by user.
+ *
+ * Decimation d depends on the filter order and the oversampling ratios.
+ * ford: filter order
+ * fosr: filter over sampling ratio
+ * iosr: integrator over sampling ratio
+ */
+ if (fl->ford == DFSDM_FASTSINC_ORDER) {
+ m = 2;
+ p = 2;
+ }
+
+ /*
+ * Look for filter and integrator oversampling ratios which allows
+ * to reach 24 bits data output resolution.
+ * Leave as soon as if exact resolution if reached.
+ * Otherwise the higher resolution below 32 bits is kept.
+ */
+ for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) {
+ for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) {
+ if (fast)
+ d = fosr * iosr;
+ else if (fl->ford == DFSDM_FASTSINC_ORDER)
+ d = fosr * (iosr + 3) + 2;
+ else
+ d = fosr * (iosr - 1 + p) + p;
+
+ if (d > oversamp)
+ break;
+ else if (d != oversamp)
+ continue;
+ /*
+ * Check resolution (limited to signed 32 bits)
+ * res <= 2^31
+ * Sincx filters:
+ * res = m * fosr^p x iosr (with m=1, p=ford)
+ * FastSinc filter
+ * res = m * fosr^p x iosr (with m=2, p=2)
+ */
+ res = fosr;
+ for (i = p - 1; i > 0; i--) {
+ res = res * (u64)fosr;
+ if (res > DFSDM_MAX_RES)
+ break;
+ }
+ if (res > DFSDM_MAX_RES)
+ continue;
+ res = res * (u64)m * (u64)iosr;
+ if (res > DFSDM_MAX_RES)
+ continue;
+
+ delta = res - DFSDM_DATA_RES;
+
+ if (res >= fl->res) {
+ fl->res = res;
+ fl->fosr = fosr;
+ fl->iosr = iosr;
+ fl->fast = fast;
+ pr_debug("%s: fosr = %d, iosr = %d\n",
+ __func__, fl->fosr, fl->iosr);
+ }
+
+ if (!delta)
+ return 0;
+ }
+ }
+
+ if (!fl->fosr)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int stm32_dfsdm_start_channel(struct stm32_dfsdm *dfsdm,
+ unsigned int ch_id)
+{
+ return regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(ch_id),
+ DFSDM_CHCFGR1_CHEN_MASK,
+ DFSDM_CHCFGR1_CHEN(1));
+}
+
+static void stm32_dfsdm_stop_channel(struct stm32_dfsdm *dfsdm,
+ unsigned int ch_id)
+{
+ regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(ch_id),
+ DFSDM_CHCFGR1_CHEN_MASK, DFSDM_CHCFGR1_CHEN(0));
+}
+
+static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm,
+ struct stm32_dfsdm_channel *ch)
+{
+ unsigned int id = ch->id;
+ struct regmap *regmap = dfsdm->regmap;
+ int ret;
+
+ ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
+ DFSDM_CHCFGR1_SITP_MASK,
+ DFSDM_CHCFGR1_SITP(ch->type));
+ if (ret < 0)
+ return ret;
+ ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
+ DFSDM_CHCFGR1_SPICKSEL_MASK,
+ DFSDM_CHCFGR1_SPICKSEL(ch->src));
+ if (ret < 0)
+ return ret;
+ return regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
+ DFSDM_CHCFGR1_CHINSEL_MASK,
+ DFSDM_CHCFGR1_CHINSEL(ch->alt_si));
+}
+
+static int stm32_dfsdm_start_filter(struct stm32_dfsdm *dfsdm,
+ unsigned int fl_id)
+{
+ int ret;
+
+ /* Enable filter */
+ ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
+ DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1));
+ if (ret < 0)
+ return ret;
+
+ /* Start conversion */
+ return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
+ DFSDM_CR1_RSWSTART_MASK,
+ DFSDM_CR1_RSWSTART(1));
+}
+
+void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm, unsigned int fl_id)
+{
+ /* Disable conversion */
+ regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
+ DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0));
+}
+
+static int stm32_dfsdm_filter_configure(struct stm32_dfsdm *dfsdm,
+ unsigned int fl_id, unsigned int ch_id)
+{
+ struct regmap *regmap = dfsdm->regmap;
+ struct stm32_dfsdm_filter *fl = &dfsdm->fl_list[fl_id];
+ int ret;
+
+ /* Average integrator oversampling */
+ ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK,
+ DFSDM_FCR_IOSR(fl->iosr - 1));
+ if (ret)
+ return ret;
+
+ /* Filter order and Oversampling */
+ ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK,
+ DFSDM_FCR_FOSR(fl->fosr - 1));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK,
+ DFSDM_FCR_FORD(fl->ford));
+ if (ret)
+ return ret;
+
+ /* No scan mode supported for the moment */
+ ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_RCH_MASK,
+ DFSDM_CR1_RCH(ch_id));
+ if (ret)
+ return ret;
+
+ return regmap_update_bits(regmap, DFSDM_CR1(fl_id),
+ DFSDM_CR1_RSYNC_MASK,
+ DFSDM_CR1_RSYNC(fl->sync_mode));
+}
+
+int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
+ struct iio_dev *indio_dev,
+ struct iio_chan_spec *ch)
+{
+ struct stm32_dfsdm_channel *df_ch;
+ const char *of_str;
+ int chan_idx = ch->scan_index;
+ int ret, val;
+
+ ret = of_property_read_u32_index(indio_dev->dev.of_node,
+ "st,adc-channels", chan_idx,
+ &ch->channel);
+ if (ret < 0) {
+ dev_err(&indio_dev->dev,
+ " Error parsing 'st,adc-channels' for idx %d\n",
+ chan_idx);
+ return ret;
+ }
+ if (ch->channel >= dfsdm->num_chs) {
+ dev_err(&indio_dev->dev,
+ " Error bad channel number %d (max = %d)\n",
+ ch->channel, dfsdm->num_chs);
+ return -EINVAL;
+ }
+
+ ret = of_property_read_string_index(indio_dev->dev.of_node,
+ "st,adc-channel-names", chan_idx,
+ &ch->datasheet_name);
+ if (ret < 0) {
+ dev_err(&indio_dev->dev,
+ " Error parsing 'st,adc-channel-names' for idx %d\n",
+ chan_idx);
+ return ret;
+ }
+
+ df_ch = &dfsdm->ch_list[ch->channel];
+ df_ch->id = ch->channel;
+
+ ret = of_property_read_string_index(indio_dev->dev.of_node,
+ "st,adc-channel-types", chan_idx,
+ &of_str);
+ if (!ret) {
+ val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
+ if (val < 0)
+ return val;
+ } else {
+ val = 0;
+ }
+ df_ch->type = val;
+
+ ret = of_property_read_string_index(indio_dev->dev.of_node,
+ "st,adc-channel-clk-src", chan_idx,
+ &of_str);
+ if (!ret) {
+ val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
+ if (val < 0)
+ return val;
+ } else {
+ val = 0;
+ }
+ df_ch->src = val;
+
+ ret = of_property_read_u32_index(indio_dev->dev.of_node,
+ "st,adc-alt-channel", chan_idx,
+ &df_ch->alt_si);
+ if (ret < 0)
+ df_ch->alt_si = 0;
+
+ return 0;
+}
+
+static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc, bool dma)
+{
+ struct regmap *regmap = adc->dfsdm->regmap;
+ int ret;
+
+ ret = stm32_dfsdm_start_channel(adc->dfsdm, adc->ch_id);
+ if (ret < 0)
+ return ret;
+
+ ret = stm32_dfsdm_filter_configure(adc->dfsdm, adc->fl_id,
+ adc->ch_id);
+ if (ret < 0)
+ goto stop_channels;
+
+ ret = stm32_dfsdm_start_filter(adc->dfsdm, adc->fl_id);
+ if (ret < 0)
+ goto stop_channels;
+
+ return 0;
+
+stop_channels:
+ regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
+ DFSDM_CR1_RDMAEN_MASK, 0);
+
+ regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
+ DFSDM_CR1_RCONT_MASK, 0);
+ stm32_dfsdm_stop_channel(adc->dfsdm, adc->fl_id);
+
+ return ret;
+}
+
+static void stm32_dfsdm_stop_conv(struct stm32_dfsdm_adc *adc)
+{
+ struct regmap *regmap = adc->dfsdm->regmap;
+
+ stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
+
+ /* Clean conversion options */
+ regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
+ DFSDM_CR1_RDMAEN_MASK, 0);
+
+ regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
+ DFSDM_CR1_RCONT_MASK, 0);
+
+ stm32_dfsdm_stop_channel(adc->dfsdm, adc->ch_id);
+}
+
+static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan, int *res)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ long timeout;
+ int ret;
+
+ reinit_completion(&adc->completion);
+
+ adc->buffer = res;
+
+ ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
+ DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1));
+ if (ret < 0)
+ goto stop_dfsdm;
+
+ ret = stm32_dfsdm_start_conv(adc, false);
+ if (ret < 0) {
+ regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
+ DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
+ goto stop_dfsdm;
+ }
+
+ timeout = wait_for_completion_interruptible_timeout(&adc->completion,
+ DFSDM_TIMEOUT);
+
+ /* Mask IRQ for regular conversion achievement*/
+ regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
+ DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
+
+ if (timeout == 0)
+ ret = -ETIMEDOUT;
+ else if (timeout < 0)
+ ret = timeout;
+ else
+ ret = IIO_VAL_INT;
+
+ stm32_dfsdm_stop_conv(adc);
+
+stop_dfsdm:
+ stm32_dfsdm_stop_dfsdm(adc->dfsdm);
+
+ return ret;
+}
+
+static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val, int val2, long mask)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
+ int ret = -EINVAL;
+
+ if (mask == IIO_CHAN_INFO_OVERSAMPLING_RATIO) {
+ ret = stm32_dfsdm_set_osrs(fl, 0, val);
+ if (!ret)
+ adc->oversamp = val;
+ }
+
+ return ret;
+}
+
+static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan, int *val,
+ int *val2, long mask)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ ret = iio_hw_consumer_enable(adc->hwc);
+ if (ret < 0) {
+ dev_err(&indio_dev->dev,
+ "%s: IIO enable failed (channel %d)\n",
+ __func__, chan->channel);
+ return ret;
+ }
+ ret = stm32_dfsdm_single_conv(indio_dev, chan, val);
+ iio_hw_consumer_disable(adc->hwc);
+ if (ret < 0) {
+ dev_err(&indio_dev->dev,
+ "%s: Conversion failed (channel %d)\n",
+ __func__, chan->channel);
+ return ret;
+ }
+ return IIO_VAL_INT;
+
+ case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
+ *val = adc->oversamp;
+
+ return IIO_VAL_INT;
+ }
+
+ return -EINVAL;
+}
+
+static const struct iio_info stm32_dfsdm_info_adc = {
+ .read_raw = stm32_dfsdm_read_raw,
+ .write_raw = stm32_dfsdm_write_raw,
+};
+
+static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
+{
+ struct stm32_dfsdm_adc *adc = arg;
+ struct iio_dev *indio_dev = iio_priv_to_dev(adc);
+ struct regmap *regmap = adc->dfsdm->regmap;
+ unsigned int status, int_en;
+
+ regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status);
+ regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en);
+
+ if (status & DFSDM_ISR_REOCF_MASK) {
+ /* Read the data register clean the IRQ status */
+ regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer);
+ complete(&adc->completion);
+ }
+
+ if (status & DFSDM_ISR_ROVRF_MASK) {
+ if (int_en & DFSDM_CR2_ROVRIE_MASK)
+ dev_warn(&indio_dev->dev, "Overrun detected\n");
+ regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id),
+ DFSDM_ICR_CLRROVRF_MASK,
+ DFSDM_ICR_CLRROVRF_MASK);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
+ struct iio_chan_spec *ch)
+{
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ int ret;
+
+ ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch);
+ if (ret < 0)
+ return ret;
+
+ ch->type = IIO_VOLTAGE;
+ ch->indexed = 1;
+
+ /*
+ * IIO_CHAN_INFO_RAW: used to compute regular conversion
+ * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling
+ */
+ ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
+ ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
+
+ ch->scan_type.sign = 'u';
+ ch->scan_type.realbits = 24;
+ ch->scan_type.storagebits = 32;
+ adc->ch_id = ch->channel;
+
+ return stm32_dfsdm_chan_configure(adc->dfsdm,
+ &adc->dfsdm->ch_list[ch->channel]);
+}
+
+static int stm32_dfsdm_adc_init(struct iio_dev *indio_dev)
+{
+ struct iio_chan_spec *ch;
+ struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
+ int num_ch;
+ int ret, chan_idx;
+
+ adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING;
+ ret = stm32_dfsdm_set_osrs(&adc->dfsdm->fl_list[adc->fl_id], 0,
+ adc->oversamp);
+ if (ret < 0)
+ return ret;
+
+ num_ch = of_property_count_u32_elems(indio_dev->dev.of_node,
+ "st,adc-channels");
+ if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) {
+ dev_err(&indio_dev->dev, "Bad st,adc-channels\n");
+ return num_ch < 0 ? num_ch : -EINVAL;
+ }
+
+ /* Bind to SD modulator IIO device */
+ adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev);
+ if (IS_ERR(adc->hwc))
+ return -EPROBE_DEFER;
+
+ ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch),
+ GFP_KERNEL);
+ if (!ch)
+ return -ENOMEM;
+
+ for (chan_idx = 0; chan_idx < num_ch; chan_idx++) {
+ ch->scan_index = chan_idx;
+ ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch);
+ if (ret < 0) {
+ dev_err(&indio_dev->dev, "Channels init failed\n");
+ return ret;
+ }
+ }
+
+ indio_dev->num_channels = num_ch;
+ indio_dev->channels = ch;
+
+ init_completion(&adc->completion);
+
+ return 0;
+}
+
+static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
+ .type = DFSDM_IIO,
+ .init = stm32_dfsdm_adc_init,
+};
+
+static const struct of_device_id stm32_dfsdm_adc_match[] = {
+ {
+ .compatible = "st,stm32-dfsdm-adc",
+ .data = &stm32h7_dfsdm_adc_data,
+ },
+ {}
+};
+
+static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct stm32_dfsdm_adc *adc;
+ struct device_node *np = dev->of_node;
+ const struct stm32_dfsdm_dev_data *dev_data;
+ struct iio_dev *iio;
+ const struct of_device_id *of_id;
+ char *name;
+ int ret, irq, val;
+
+ of_id = of_match_node(stm32_dfsdm_adc_match, np);
+ if (!of_id->data) {
+ dev_err(&pdev->dev, "Data associated to device is missing\n");
+ return -EINVAL;
+ }
+
+ dev_data = (const struct stm32_dfsdm_dev_data *)of_id->data;
+
+ iio = devm_iio_device_alloc(dev, sizeof(*adc));
+ if (IS_ERR(iio)) {
+ dev_err(dev, "%s: Failed to allocate IIO\n", __func__);
+ return PTR_ERR(iio);
+ }
+
+ adc = iio_priv(iio);
+ if (IS_ERR(adc)) {
+ dev_err(dev, "%s: Failed to allocate ADC\n", __func__);
+ return PTR_ERR(adc);
+ }
+ adc->dfsdm = dev_get_drvdata(dev->parent);
+
+ iio->dev.parent = dev;
+ iio->dev.of_node = np;
+ iio->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
+
+ platform_set_drvdata(pdev, adc);
+
+ ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id);
+ if (ret != 0) {
+ dev_err(dev, "Missing reg property\n");
+ return -EINVAL;
+ }
+
+ name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
+ if (!name)
+ return -ENOMEM;
+ iio->info = &stm32_dfsdm_info_adc;
+ snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
+ iio->name = name;
+
+ /*
+ * In a first step IRQs generated for channels are not treated.
+ * So IRQ associated to filter instance 0 is dedicated to the Filter 0.
+ */
+ irq = platform_get_irq(pdev, 0);
+ ret = devm_request_irq(dev, irq, stm32_dfsdm_irq,
+ 0, pdev->name, adc);
+ if (ret < 0) {
+ dev_err(dev, "Failed to request IRQ\n");
+ return ret;
+ }
+
+ ret = of_property_read_u32(dev->of_node, "st,filter-order", &val);
+ if (ret < 0) {
+ dev_err(dev, "Failed to set filter order\n");
+ return ret;
+ }
+
+ adc->dfsdm->fl_list[adc->fl_id].ford = val;
+
+ ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val);
+ if (!ret)
+ adc->dfsdm->fl_list[adc->fl_id].sync_mode = val;
+
+ adc->dev_data = dev_data;
+ ret = dev_data->init(iio);
+ if (ret < 0)
+ return ret;
+
+ return iio_device_register(iio);
+}
+
+static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
+{
+ struct stm32_dfsdm_adc *adc = platform_get_drvdata(pdev);
+ struct iio_dev *indio_dev = iio_priv_to_dev(adc);
+
+ iio_device_unregister(indio_dev);
+
+ return 0;
+}
+
+static struct platform_driver stm32_dfsdm_adc_driver = {
+ .driver = {
+ .name = "stm32-dfsdm-adc",
+ .of_match_table = stm32_dfsdm_adc_match,
+ },
+ .probe = stm32_dfsdm_adc_probe,
+ .remove = stm32_dfsdm_adc_remove,
+};
+module_platform_driver(stm32_dfsdm_adc_driver);
+
+MODULE_DESCRIPTION("STM32 sigma delta ADC");
+MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>");
+MODULE_LICENSE("GPL v2");
--
2.7.4
--
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^ permalink raw reply related
* [PATCH v9 08/13] IIO: ADC: add stm32 DFSDM core support
From: Arnaud Pouliquen @ 2017-12-14 8:58 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw, Maxime Coquelin,
Alexandre Torgue, arnaud.pouliquen-qxv4g6HH51o
In-Reply-To: <1513241885-32079-1-git-send-email-arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Add driver for stm32 DFSDM pheripheral. Its converts a sigma delta
stream in n bit samples through a low pass filter and an integrator.
stm32-dfsdm-core driver is the core part supporting the filter
instances dedicated to sigma-delta ADC or audio PDM microphone purpose.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Reviewed-by: Jonathan Cameron <jonathan.cameron-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
drivers/iio/adc/Kconfig | 12 ++
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/stm32-dfsdm-core.c | 309 ++++++++++++++++++++++++++++++++++++
drivers/iio/adc/stm32-dfsdm.h | 310 +++++++++++++++++++++++++++++++++++++
4 files changed, 632 insertions(+)
create mode 100644 drivers/iio/adc/stm32-dfsdm-core.c
create mode 100644 drivers/iio/adc/stm32-dfsdm.h
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index c5db62f..b729ae0 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -665,6 +665,18 @@ config STM32_ADC
This driver can also be built as a module. If so, the module
will be called stm32-adc.
+config STM32_DFSDM_CORE
+ tristate "STMicroelectronics STM32 DFSDM core"
+ depends on (ARCH_STM32 && OF) || COMPILE_TEST
+ select REGMAP
+ select REGMAP_MMIO
+ help
+ Select this option to enable the driver for STMicroelectronics
+ STM32 digital filter for sigma delta converter.
+
+ This driver can also be built as a module. If so, the module
+ will be called stm32-dfsdm-core.
+
config STX104
tristate "Apex Embedded Systems STX104 driver"
depends on PC104 && X86 && ISA_BUS_API
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index d800325..b52d0a0 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_STX104) += stx104.o
obj-$(CONFIG_SUN4I_GPADC) += sun4i-gpadc-iio.o
obj-$(CONFIG_STM32_ADC_CORE) += stm32-adc-core.o
obj-$(CONFIG_STM32_ADC) += stm32-adc.o
+obj-$(CONFIG_STM32_DFSDM_CORE) += stm32-dfsdm-core.o
obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o
obj-$(CONFIG_TI_ADC0832) += ti-adc0832.o
obj-$(CONFIG_TI_ADC084S021) += ti-adc084s021.o
diff --git a/drivers/iio/adc/stm32-dfsdm-core.c b/drivers/iio/adc/stm32-dfsdm-core.c
new file mode 100644
index 0000000..7242741
--- /dev/null
+++ b/drivers/iio/adc/stm32-dfsdm-core.c
@@ -0,0 +1,309 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This file is part the core part STM32 DFSDM driver
+ *
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org> for STMicroelectronics.
+ */
+
+#include <linux/clk.h>
+#include <linux/iio/iio.h>
+#include <linux/iio/sysfs.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include "stm32-dfsdm.h"
+
+struct stm32_dfsdm_dev_data {
+ unsigned int num_filters;
+ unsigned int num_channels;
+ const struct regmap_config *regmap_cfg;
+};
+
+#define STM32H7_DFSDM_NUM_FILTERS 4
+#define STM32H7_DFSDM_NUM_CHANNELS 8
+
+static bool stm32_dfsdm_volatile_reg(struct device *dev, unsigned int reg)
+{
+ if (reg < DFSDM_FILTER_BASE_ADR)
+ return false;
+
+ /*
+ * Mask is done on register to avoid to list registers of all
+ * filter instances.
+ */
+ switch (reg & DFSDM_FILTER_REG_MASK) {
+ case DFSDM_CR1(0) & DFSDM_FILTER_REG_MASK:
+ case DFSDM_ISR(0) & DFSDM_FILTER_REG_MASK:
+ case DFSDM_JDATAR(0) & DFSDM_FILTER_REG_MASK:
+ case DFSDM_RDATAR(0) & DFSDM_FILTER_REG_MASK:
+ return true;
+ }
+
+ return false;
+}
+
+static const struct regmap_config stm32h7_dfsdm_regmap_cfg = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = sizeof(u32),
+ .max_register = 0x2B8,
+ .volatile_reg = stm32_dfsdm_volatile_reg,
+ .fast_io = true,
+};
+
+static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_data = {
+ .num_filters = STM32H7_DFSDM_NUM_FILTERS,
+ .num_channels = STM32H7_DFSDM_NUM_CHANNELS,
+ .regmap_cfg = &stm32h7_dfsdm_regmap_cfg,
+};
+
+struct dfsdm_priv {
+ struct platform_device *pdev; /* platform device */
+
+ struct stm32_dfsdm dfsdm; /* common data exported for all instances */
+
+ unsigned int spi_clk_out_div; /* SPI clkout divider value */
+ atomic_t n_active_ch; /* number of current active channels */
+
+ struct clk *clk; /* DFSDM clock */
+ struct clk *aclk; /* audio clock */
+};
+
+/**
+ * stm32_dfsdm_start_dfsdm - start global dfsdm interface.
+ *
+ * Enable interface if n_active_ch is not null.
+ * @dfsdm: Handle used to retrieve dfsdm context.
+ */
+int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm)
+{
+ struct dfsdm_priv *priv = container_of(dfsdm, struct dfsdm_priv, dfsdm);
+ struct device *dev = &priv->pdev->dev;
+ unsigned int clk_div = priv->spi_clk_out_div;
+ int ret;
+
+ if (atomic_inc_return(&priv->n_active_ch) == 1) {
+ ret = clk_prepare_enable(priv->clk);
+ if (ret < 0) {
+ dev_err(dev, "Failed to start clock\n");
+ goto error_ret;
+ }
+ if (priv->aclk) {
+ ret = clk_prepare_enable(priv->aclk);
+ if (ret < 0) {
+ dev_err(dev, "Failed to start audio clock\n");
+ goto disable_clk;
+ }
+ }
+
+ /* Output the SPI CLKOUT (if clk_div == 0 clock if OFF) */
+ ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
+ DFSDM_CHCFGR1_CKOUTDIV_MASK,
+ DFSDM_CHCFGR1_CKOUTDIV(clk_div));
+ if (ret < 0)
+ goto disable_aclk;
+
+ /* Global enable of DFSDM interface */
+ ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
+ DFSDM_CHCFGR1_DFSDMEN_MASK,
+ DFSDM_CHCFGR1_DFSDMEN(1));
+ if (ret < 0)
+ goto disable_aclk;
+ }
+
+ dev_dbg(dev, "%s: n_active_ch %d\n", __func__,
+ atomic_read(&priv->n_active_ch));
+
+ return 0;
+
+disable_aclk:
+ clk_disable_unprepare(priv->aclk);
+disable_clk:
+ clk_disable_unprepare(priv->clk);
+
+error_ret:
+ atomic_dec(&priv->n_active_ch);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(stm32_dfsdm_start_dfsdm);
+
+/**
+ * stm32_dfsdm_stop_dfsdm - stop global DFSDM interface.
+ *
+ * Disable interface if n_active_ch is null
+ * @dfsdm: Handle used to retrieve dfsdm context.
+ */
+int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm)
+{
+ struct dfsdm_priv *priv = container_of(dfsdm, struct dfsdm_priv, dfsdm);
+ int ret;
+
+ if (atomic_dec_and_test(&priv->n_active_ch)) {
+ /* Global disable of DFSDM interface */
+ ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
+ DFSDM_CHCFGR1_DFSDMEN_MASK,
+ DFSDM_CHCFGR1_DFSDMEN(0));
+ if (ret < 0)
+ return ret;
+
+ /* Stop SPI CLKOUT */
+ ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
+ DFSDM_CHCFGR1_CKOUTDIV_MASK,
+ DFSDM_CHCFGR1_CKOUTDIV(0));
+ if (ret < 0)
+ return ret;
+
+ clk_disable_unprepare(priv->clk);
+ if (priv->aclk)
+ clk_disable_unprepare(priv->aclk);
+ }
+ dev_dbg(&priv->pdev->dev, "%s: n_active_ch %d\n", __func__,
+ atomic_read(&priv->n_active_ch));
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(stm32_dfsdm_stop_dfsdm);
+
+static int stm32_dfsdm_parse_of(struct platform_device *pdev,
+ struct dfsdm_priv *priv)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct resource *res;
+ unsigned long clk_freq;
+ unsigned int spi_freq, rem;
+ int ret;
+
+ if (!node)
+ return -EINVAL;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "Failed to get memory resource\n");
+ return -ENODEV;
+ }
+ priv->dfsdm.phys_base = res->start;
+ priv->dfsdm.base = devm_ioremap_resource(&pdev->dev, res);
+
+ /*
+ * "dfsdm" clock is mandatory for DFSDM peripheral clocking.
+ * "dfsdm" or "audio" clocks can be used as source clock for
+ * the SPI clock out signal and internal processing, depending
+ * on use case.
+ */
+ priv->clk = devm_clk_get(&pdev->dev, "dfsdm");
+ if (IS_ERR(priv->clk)) {
+ dev_err(&pdev->dev, "No stm32_dfsdm_clk clock found\n");
+ return -EINVAL;
+ }
+
+ priv->aclk = devm_clk_get(&pdev->dev, "audio");
+ if (IS_ERR(priv->aclk))
+ priv->aclk = NULL;
+
+ if (priv->aclk)
+ clk_freq = clk_get_rate(priv->aclk);
+ else
+ clk_freq = clk_get_rate(priv->clk);
+
+ /* SPI clock out frequency */
+ ret = of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
+ &spi_freq);
+ if (ret < 0) {
+ /* No SPI master mode */
+ return 0;
+ }
+
+ priv->spi_clk_out_div = div_u64_rem(clk_freq, spi_freq, &rem) - 1;
+ priv->dfsdm.spi_master_freq = spi_freq;
+
+ if (rem) {
+ dev_warn(&pdev->dev, "SPI clock not accurate\n");
+ dev_warn(&pdev->dev, "%ld = %d * %d + %d\n",
+ clk_freq, spi_freq, priv->spi_clk_out_div + 1, rem);
+ }
+
+ return 0;
+};
+
+static const struct of_device_id stm32_dfsdm_of_match[] = {
+ {
+ .compatible = "st,stm32h7-dfsdm",
+ .data = &stm32h7_dfsdm_data,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, stm32_dfsdm_of_match);
+
+static int stm32_dfsdm_probe(struct platform_device *pdev)
+{
+ struct dfsdm_priv *priv;
+ struct device_node *pnode = pdev->dev.of_node;
+ const struct of_device_id *of_id;
+ const struct stm32_dfsdm_dev_data *dev_data;
+ struct stm32_dfsdm *dfsdm;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->pdev = pdev;
+
+ of_id = of_match_node(stm32_dfsdm_of_match, pnode);
+ if (!of_id->data) {
+ dev_err(&pdev->dev, "Data associated to device is missing\n");
+ return -EINVAL;
+ }
+
+ dev_data = (const struct stm32_dfsdm_dev_data *)of_id->data;
+ dfsdm = &priv->dfsdm;
+ dfsdm->fl_list = devm_kcalloc(&pdev->dev, dev_data->num_filters,
+ sizeof(*dfsdm->fl_list), GFP_KERNEL);
+ if (!dfsdm->fl_list)
+ return -ENOMEM;
+
+ dfsdm->num_fls = dev_data->num_filters;
+ dfsdm->ch_list = devm_kcalloc(&pdev->dev, dev_data->num_channels,
+ sizeof(*dfsdm->ch_list),
+ GFP_KERNEL);
+ if (!dfsdm->ch_list)
+ return -ENOMEM;
+ dfsdm->num_chs = dev_data->num_channels;
+
+ ret = stm32_dfsdm_parse_of(pdev, priv);
+ if (ret < 0)
+ return ret;
+
+ dfsdm->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dfsdm",
+ dfsdm->base,
+ &stm32h7_dfsdm_regmap_cfg);
+ if (IS_ERR(dfsdm->regmap)) {
+ ret = PTR_ERR(dfsdm->regmap);
+ dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, dfsdm);
+
+ return devm_of_platform_populate(&pdev->dev);
+}
+
+static struct platform_driver stm32_dfsdm_driver = {
+ .probe = stm32_dfsdm_probe,
+ .driver = {
+ .name = "stm32-dfsdm",
+ .of_match_table = stm32_dfsdm_of_match,
+ },
+};
+
+module_platform_driver(stm32_dfsdm_driver);
+
+MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>");
+MODULE_DESCRIPTION("STMicroelectronics STM32 dfsdm driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/iio/adc/stm32-dfsdm.h b/drivers/iio/adc/stm32-dfsdm.h
new file mode 100644
index 0000000..8708394
--- /dev/null
+++ b/drivers/iio/adc/stm32-dfsdm.h
@@ -0,0 +1,310 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This file is part of STM32 DFSDM driver
+ *
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>.
+ */
+
+#ifndef MDF_STM32_DFSDM__H
+#define MDF_STM32_DFSDM__H
+
+#include <linux/bitfield.h>
+
+/*
+ * STM32 DFSDM - global register map
+ * ________________________________________________________
+ * | Offset | Registers block |
+ * --------------------------------------------------------
+ * | 0x000 | CHANNEL 0 + COMMON CHANNEL FIELDS |
+ * --------------------------------------------------------
+ * | 0x020 | CHANNEL 1 |
+ * --------------------------------------------------------
+ * | ... | ..... |
+ * --------------------------------------------------------
+ * | 0x0E0 | CHANNEL 7 |
+ * --------------------------------------------------------
+ * | 0x100 | FILTER 0 + COMMON FILTER FIELDs |
+ * --------------------------------------------------------
+ * | 0x200 | FILTER 1 |
+ * --------------------------------------------------------
+ * | 0x300 | FILTER 2 |
+ * --------------------------------------------------------
+ * | 0x400 | FILTER 3 |
+ * --------------------------------------------------------
+ */
+
+/*
+ * Channels register definitions
+ */
+#define DFSDM_CHCFGR1(y) ((y) * 0x20 + 0x00)
+#define DFSDM_CHCFGR2(y) ((y) * 0x20 + 0x04)
+#define DFSDM_AWSCDR(y) ((y) * 0x20 + 0x08)
+#define DFSDM_CHWDATR(y) ((y) * 0x20 + 0x0C)
+#define DFSDM_CHDATINR(y) ((y) * 0x20 + 0x10)
+
+/* CHCFGR1: Channel configuration register 1 */
+#define DFSDM_CHCFGR1_SITP_MASK GENMASK(1, 0)
+#define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v)
+#define DFSDM_CHCFGR1_SPICKSEL_MASK GENMASK(3, 2)
+#define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v)
+#define DFSDM_CHCFGR1_SCDEN_MASK BIT(5)
+#define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v)
+#define DFSDM_CHCFGR1_CKABEN_MASK BIT(6)
+#define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v)
+#define DFSDM_CHCFGR1_CHEN_MASK BIT(7)
+#define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v)
+#define DFSDM_CHCFGR1_CHINSEL_MASK BIT(8)
+#define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v)
+#define DFSDM_CHCFGR1_DATMPX_MASK GENMASK(13, 12)
+#define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v)
+#define DFSDM_CHCFGR1_DATPACK_MASK GENMASK(15, 14)
+#define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v)
+#define DFSDM_CHCFGR1_CKOUTDIV_MASK GENMASK(23, 16)
+#define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v)
+#define DFSDM_CHCFGR1_CKOUTSRC_MASK BIT(30)
+#define DFSDM_CHCFGR1_CKOUTSRC(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MASK, v)
+#define DFSDM_CHCFGR1_DFSDMEN_MASK BIT(31)
+#define DFSDM_CHCFGR1_DFSDMEN(v) FIELD_PREP(DFSDM_CHCFGR1_DFSDMEN_MASK, v)
+
+/* CHCFGR2: Channel configuration register 2 */
+#define DFSDM_CHCFGR2_DTRBS_MASK GENMASK(7, 3)
+#define DFSDM_CHCFGR2_DTRBS(v) FIELD_PREP(DFSDM_CHCFGR2_DTRBS_MASK, v)
+#define DFSDM_CHCFGR2_OFFSET_MASK GENMASK(31, 8)
+#define DFSDM_CHCFGR2_OFFSET(v) FIELD_PREP(DFSDM_CHCFGR2_OFFSET_MASK, v)
+
+/* AWSCDR: Channel analog watchdog and short circuit detector */
+#define DFSDM_AWSCDR_SCDT_MASK GENMASK(7, 0)
+#define DFSDM_AWSCDR_SCDT(v) FIELD_PREP(DFSDM_AWSCDR_SCDT_MASK, v)
+#define DFSDM_AWSCDR_BKSCD_MASK GENMASK(15, 12)
+#define DFSDM_AWSCDR_BKSCD(v) FIELD_PREP(DFSDM_AWSCDR_BKSCD_MASK, v)
+#define DFSDM_AWSCDR_AWFOSR_MASK GENMASK(20, 16)
+#define DFSDM_AWSCDR_AWFOSR(v) FIELD_PREP(DFSDM_AWSCDR_AWFOSR_MASK, v)
+#define DFSDM_AWSCDR_AWFORD_MASK GENMASK(23, 22)
+#define DFSDM_AWSCDR_AWFORD(v) FIELD_PREP(DFSDM_AWSCDR_AWFORD_MASK, v)
+
+/*
+ * Filters register definitions
+ */
+#define DFSDM_FILTER_BASE_ADR 0x100
+#define DFSDM_FILTER_REG_MASK 0x7F
+#define DFSDM_FILTER_X_BASE_ADR(x) ((x) * 0x80 + DFSDM_FILTER_BASE_ADR)
+
+#define DFSDM_CR1(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x00)
+#define DFSDM_CR2(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x04)
+#define DFSDM_ISR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x08)
+#define DFSDM_ICR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x0C)
+#define DFSDM_JCHGR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x10)
+#define DFSDM_FCR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x14)
+#define DFSDM_JDATAR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x18)
+#define DFSDM_RDATAR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x1C)
+#define DFSDM_AWHTR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x20)
+#define DFSDM_AWLTR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x24)
+#define DFSDM_AWSR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x28)
+#define DFSDM_AWCFR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x2C)
+#define DFSDM_EXMAX(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x30)
+#define DFSDM_EXMIN(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x34)
+#define DFSDM_CNVTIMR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x38)
+
+/* CR1 Control register 1 */
+#define DFSDM_CR1_DFEN_MASK BIT(0)
+#define DFSDM_CR1_DFEN(v) FIELD_PREP(DFSDM_CR1_DFEN_MASK, v)
+#define DFSDM_CR1_JSWSTART_MASK BIT(1)
+#define DFSDM_CR1_JSWSTART(v) FIELD_PREP(DFSDM_CR1_JSWSTART_MASK, v)
+#define DFSDM_CR1_JSYNC_MASK BIT(3)
+#define DFSDM_CR1_JSYNC(v) FIELD_PREP(DFSDM_CR1_JSYNC_MASK, v)
+#define DFSDM_CR1_JSCAN_MASK BIT(4)
+#define DFSDM_CR1_JSCAN(v) FIELD_PREP(DFSDM_CR1_JSCAN_MASK, v)
+#define DFSDM_CR1_JDMAEN_MASK BIT(5)
+#define DFSDM_CR1_JDMAEN(v) FIELD_PREP(DFSDM_CR1_JDMAEN_MASK, v)
+#define DFSDM_CR1_JEXTSEL_MASK GENMASK(12, 8)
+#define DFSDM_CR1_JEXTSEL(v) FIELD_PREP(DFSDM_CR1_JEXTSEL_MASK, v)
+#define DFSDM_CR1_JEXTEN_MASK GENMASK(14, 13)
+#define DFSDM_CR1_JEXTEN(v) FIELD_PREP(DFSDM_CR1_JEXTEN_MASK, v)
+#define DFSDM_CR1_RSWSTART_MASK BIT(17)
+#define DFSDM_CR1_RSWSTART(v) FIELD_PREP(DFSDM_CR1_RSWSTART_MASK, v)
+#define DFSDM_CR1_RCONT_MASK BIT(18)
+#define DFSDM_CR1_RCONT(v) FIELD_PREP(DFSDM_CR1_RCONT_MASK, v)
+#define DFSDM_CR1_RSYNC_MASK BIT(19)
+#define DFSDM_CR1_RSYNC(v) FIELD_PREP(DFSDM_CR1_RSYNC_MASK, v)
+#define DFSDM_CR1_RDMAEN_MASK BIT(21)
+#define DFSDM_CR1_RDMAEN(v) FIELD_PREP(DFSDM_CR1_RDMAEN_MASK, v)
+#define DFSDM_CR1_RCH_MASK GENMASK(26, 24)
+#define DFSDM_CR1_RCH(v) FIELD_PREP(DFSDM_CR1_RCH_MASK, v)
+#define DFSDM_CR1_FAST_MASK BIT(29)
+#define DFSDM_CR1_FAST(v) FIELD_PREP(DFSDM_CR1_FAST_MASK, v)
+#define DFSDM_CR1_AWFSEL_MASK BIT(30)
+#define DFSDM_CR1_AWFSEL(v) FIELD_PREP(DFSDM_CR1_AWFSEL_MASK, v)
+
+/* CR2: Control register 2 */
+#define DFSDM_CR2_IE_MASK GENMASK(6, 0)
+#define DFSDM_CR2_IE(v) FIELD_PREP(DFSDM_CR2_IE_MASK, v)
+#define DFSDM_CR2_JEOCIE_MASK BIT(0)
+#define DFSDM_CR2_JEOCIE(v) FIELD_PREP(DFSDM_CR2_JEOCIE_MASK, v)
+#define DFSDM_CR2_REOCIE_MASK BIT(1)
+#define DFSDM_CR2_REOCIE(v) FIELD_PREP(DFSDM_CR2_REOCIE_MASK, v)
+#define DFSDM_CR2_JOVRIE_MASK BIT(2)
+#define DFSDM_CR2_JOVRIE(v) FIELD_PREP(DFSDM_CR2_JOVRIE_MASK, v)
+#define DFSDM_CR2_ROVRIE_MASK BIT(3)
+#define DFSDM_CR2_ROVRIE(v) FIELD_PREP(DFSDM_CR2_ROVRIE_MASK, v)
+#define DFSDM_CR2_AWDIE_MASK BIT(4)
+#define DFSDM_CR2_AWDIE(v) FIELD_PREP(DFSDM_CR2_AWDIE_MASK, v)
+#define DFSDM_CR2_SCDIE_MASK BIT(5)
+#define DFSDM_CR2_SCDIE(v) FIELD_PREP(DFSDM_CR2_SCDIE_MASK, v)
+#define DFSDM_CR2_CKABIE_MASK BIT(6)
+#define DFSDM_CR2_CKABIE(v) FIELD_PREP(DFSDM_CR2_CKABIE_MASK, v)
+#define DFSDM_CR2_EXCH_MASK GENMASK(15, 8)
+#define DFSDM_CR2_EXCH(v) FIELD_PREP(DFSDM_CR2_EXCH_MASK, v)
+#define DFSDM_CR2_AWDCH_MASK GENMASK(23, 16)
+#define DFSDM_CR2_AWDCH(v) FIELD_PREP(DFSDM_CR2_AWDCH_MASK, v)
+
+/* ISR: Interrupt status register */
+#define DFSDM_ISR_JEOCF_MASK BIT(0)
+#define DFSDM_ISR_JEOCF(v) FIELD_PREP(DFSDM_ISR_JEOCF_MASK, v)
+#define DFSDM_ISR_REOCF_MASK BIT(1)
+#define DFSDM_ISR_REOCF(v) FIELD_PREP(DFSDM_ISR_REOCF_MASK, v)
+#define DFSDM_ISR_JOVRF_MASK BIT(2)
+#define DFSDM_ISR_JOVRF(v) FIELD_PREP(DFSDM_ISR_JOVRF_MASK, v)
+#define DFSDM_ISR_ROVRF_MASK BIT(3)
+#define DFSDM_ISR_ROVRF(v) FIELD_PREP(DFSDM_ISR_ROVRF_MASK, v)
+#define DFSDM_ISR_AWDF_MASK BIT(4)
+#define DFSDM_ISR_AWDF(v) FIELD_PREP(DFSDM_ISR_AWDF_MASK, v)
+#define DFSDM_ISR_JCIP_MASK BIT(13)
+#define DFSDM_ISR_JCIP(v) FIELD_PREP(DFSDM_ISR_JCIP_MASK, v)
+#define DFSDM_ISR_RCIP_MASK BIT(14)
+#define DFSDM_ISR_RCIP(v) FIELD_PREP(DFSDM_ISR_RCIP, v)
+#define DFSDM_ISR_CKABF_MASK GENMASK(23, 16)
+#define DFSDM_ISR_CKABF(v) FIELD_PREP(DFSDM_ISR_CKABF_MASK, v)
+#define DFSDM_ISR_SCDF_MASK GENMASK(31, 24)
+#define DFSDM_ISR_SCDF(v) FIELD_PREP(DFSDM_ISR_SCDF_MASK, v)
+
+/* ICR: Interrupt flag clear register */
+#define DFSDM_ICR_CLRJOVRF_MASK BIT(2)
+#define DFSDM_ICR_CLRJOVRF(v) FIELD_PREP(DFSDM_ICR_CLRJOVRF_MASK, v)
+#define DFSDM_ICR_CLRROVRF_MASK BIT(3)
+#define DFSDM_ICR_CLRROVRF(v) FIELD_PREP(DFSDM_ICR_CLRROVRF_MASK, v)
+#define DFSDM_ICR_CLRCKABF_MASK GENMASK(23, 16)
+#define DFSDM_ICR_CLRCKABF(v) FIELD_PREP(DFSDM_ICR_CLRCKABF_MASK, v)
+#define DFSDM_ICR_CLRCKABF_CH_MASK(y) BIT(16 + (y))
+#define DFSDM_ICR_CLRCKABF_CH(v, y) \
+ (((v) << (16 + (y))) & DFSDM_ICR_CLRCKABF_CH_MASK(y))
+#define DFSDM_ICR_CLRSCDF_MASK GENMASK(31, 24)
+#define DFSDM_ICR_CLRSCDF(v) FIELD_PREP(DFSDM_ICR_CLRSCDF_MASK, v)
+#define DFSDM_ICR_CLRSCDF_CH_MASK(y) BIT(24 + (y))
+#define DFSDM_ICR_CLRSCDF_CH(v, y) \
+ (((v) << (24 + (y))) & DFSDM_ICR_CLRSCDF_MASK(y))
+
+/* FCR: Filter control register */
+#define DFSDM_FCR_IOSR_MASK GENMASK(7, 0)
+#define DFSDM_FCR_IOSR(v) FIELD_PREP(DFSDM_FCR_IOSR_MASK, v)
+#define DFSDM_FCR_FOSR_MASK GENMASK(25, 16)
+#define DFSDM_FCR_FOSR(v) FIELD_PREP(DFSDM_FCR_FOSR_MASK, v)
+#define DFSDM_FCR_FORD_MASK GENMASK(31, 29)
+#define DFSDM_FCR_FORD(v) FIELD_PREP(DFSDM_FCR_FORD_MASK, v)
+
+/* RDATAR: Filter data register for regular channel */
+#define DFSDM_DATAR_CH_MASK GENMASK(2, 0)
+#define DFSDM_DATAR_DATA_OFFSET 8
+#define DFSDM_DATAR_DATA_MASK GENMASK(31, DFSDM_DATAR_DATA_OFFSET)
+
+/* AWLTR: Filter analog watchdog low threshold register */
+#define DFSDM_AWLTR_BKAWL_MASK GENMASK(3, 0)
+#define DFSDM_AWLTR_BKAWL(v) FIELD_PREP(DFSDM_AWLTR_BKAWL_MASK, v)
+#define DFSDM_AWLTR_AWLT_MASK GENMASK(31, 8)
+#define DFSDM_AWLTR_AWLT(v) FIELD_PREP(DFSDM_AWLTR_AWLT_MASK, v)
+
+/* AWHTR: Filter analog watchdog low threshold register */
+#define DFSDM_AWHTR_BKAWH_MASK GENMASK(3, 0)
+#define DFSDM_AWHTR_BKAWH(v) FIELD_PREP(DFSDM_AWHTR_BKAWH_MASK, v)
+#define DFSDM_AWHTR_AWHT_MASK GENMASK(31, 8)
+#define DFSDM_AWHTR_AWHT(v) FIELD_PREP(DFSDM_AWHTR_AWHT_MASK, v)
+
+/* AWSR: Filter watchdog status register */
+#define DFSDM_AWSR_AWLTF_MASK GENMASK(7, 0)
+#define DFSDM_AWSR_AWLTF(v) FIELD_PREP(DFSDM_AWSR_AWLTF_MASK, v)
+#define DFSDM_AWSR_AWHTF_MASK GENMASK(15, 8)
+#define DFSDM_AWSR_AWHTF(v) FIELD_PREP(DFSDM_AWSR_AWHTF_MASK, v)
+
+/* AWCFR: Filter watchdog status register */
+#define DFSDM_AWCFR_AWLTF_MASK GENMASK(7, 0)
+#define DFSDM_AWCFR_AWLTF(v) FIELD_PREP(DFSDM_AWCFR_AWLTF_MASK, v)
+#define DFSDM_AWCFR_AWHTF_MASK GENMASK(15, 8)
+#define DFSDM_AWCFR_AWHTF(v) FIELD_PREP(DFSDM_AWCFR_AWHTF_MASK, v)
+
+/* DFSDM filter order */
+enum stm32_dfsdm_sinc_order {
+ DFSDM_FASTSINC_ORDER, /* FastSinc filter type */
+ DFSDM_SINC1_ORDER, /* Sinc 1 filter type */
+ DFSDM_SINC2_ORDER, /* Sinc 2 filter type */
+ DFSDM_SINC3_ORDER, /* Sinc 3 filter type */
+ DFSDM_SINC4_ORDER, /* Sinc 4 filter type (N.A. for watchdog) */
+ DFSDM_SINC5_ORDER, /* Sinc 5 filter type (N.A. for watchdog) */
+ DFSDM_NB_SINC_ORDER,
+};
+
+/**
+ * struct stm32_dfsdm_filter - structure relative to stm32 FDSDM filter
+ * @iosr: integrator oversampling
+ * @fosr: filter oversampling
+ * @ford: filter order
+ * @res: output sample resolution
+ * @sync_mode: filter synchronized with filter 0
+ * @fast: filter fast mode
+ */
+struct stm32_dfsdm_filter {
+ unsigned int iosr;
+ unsigned int fosr;
+ enum stm32_dfsdm_sinc_order ford;
+ u64 res;
+ unsigned int sync_mode;
+ unsigned int fast;
+};
+
+/**
+ * struct stm32_dfsdm_channel - structure relative to stm32 FDSDM channel
+ * @id: id of the channel
+ * @type: interface type linked to stm32_dfsdm_chan_type
+ * @src: interface type linked to stm32_dfsdm_chan_src
+ * @alt_si: alternative serial input interface
+ */
+struct stm32_dfsdm_channel {
+ unsigned int id;
+ unsigned int type;
+ unsigned int src;
+ unsigned int alt_si;
+};
+
+/**
+ * struct stm32_dfsdm - stm32 FDSDM driver common data (for all instances)
+ * @base: control registers base cpu addr
+ * @phys_base: DFSDM IP register physical address
+ * @regmap: regmap for register read/write
+ * @fl_list: filter resources list
+ * @num_fls: number of filter resources available
+ * @ch_list: channel resources list
+ * @num_chs: number of channel resources available
+ * @spi_master_freq: SPI clock out frequency
+ */
+struct stm32_dfsdm {
+ void __iomem *base;
+ phys_addr_t phys_base;
+ struct regmap *regmap;
+ struct stm32_dfsdm_filter *fl_list;
+ unsigned int num_fls;
+ struct stm32_dfsdm_channel *ch_list;
+ unsigned int num_chs;
+ unsigned int spi_master_freq;
+};
+
+/* DFSDM channel serial spi clock source */
+enum stm32_dfsdm_spi_clk_src {
+ DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL,
+ DFSDM_CHANNEL_SPI_CLOCK_INTERNAL,
+ DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING,
+ DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING
+};
+
+int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm);
+int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm);
+
+#endif
--
2.7.4
--
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^ permalink raw reply related
* [PATCH v9 07/13] IIO: add DT bindings for stm32 DFSDM filter
From: Arnaud Pouliquen @ 2017-12-14 8:57 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw, Maxime Coquelin,
Alexandre Torgue, arnaud.pouliquen-qxv4g6HH51o
In-Reply-To: <1513241885-32079-1-git-send-email-arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Add bindings that describes STM32 Digital Filter for Sigma Delta
Modulators. DFSDM allows to connect sigma delta
modulators.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Acked-by: Jonathan Cameron <Jonathan.Cameron-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
.../bindings/iio/adc/st,stm32-dfsdm-adc.txt | 128 +++++++++++++++++++++
1 file changed, 128 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt
new file mode 100644
index 0000000..911492da
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt
@@ -0,0 +1,128 @@
+STMicroelectronics STM32 DFSDM ADC device driver
+
+
+STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
+interface external sigma delta modulators to STM32 micro controllers.
+It is mainly targeted for:
+- Sigma delta modulators (motor control, metering...)
+- PDM microphones (audio digital microphone)
+
+It features up to 8 serial digital interfaces (SPI or Manchester) and
+up to 4 filters on stm32h7.
+
+Each child node match with a filter instance.
+
+Contents of a STM32 DFSDM root node:
+------------------------------------
+Required properties:
+- compatible: Should be "st,stm32h7-dfsdm".
+- reg: Offset and length of the DFSDM block register set.
+- clocks: IP and serial interfaces clocking. Should be set according
+ to rcc clock ID and "clock-names".
+- clock-names: Input clock name "dfsdm" must be defined,
+ "audio" is optional. If defined CLKOUT is based on the audio
+ clock, else "dfsdm" is used.
+- #interrupt-cells = <1>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+
+Optional properties:
+- spi-max-frequency: Requested only for SPI master mode.
+ SPI clock OUT frequency (Hz). This clock must be set according
+ to "clock" property. Frequency must be a multiple of the rcc
+ clock frequency. If not, SPI CLKOUT frequency will not be
+ accurate.
+
+Contents of a STM32 DFSDM child nodes:
+--------------------------------------
+
+Required properties:
+- compatible: Must be:
+ "st,stm32-dfsdm-adc" for sigma delta ADCs
+ "st,stm32-dfsdm-dmic" for audio digital microphone.
+- reg: Specifies the DFSDM filter instance used.
+- interrupts: IRQ lines connected to each DFSDM filter instance.
+- st,adc-channels: List of single-ended channels muxed for this ADC.
+ valid values:
+ "st,stm32h7-dfsdm" compatibility: 0 to 7.
+- st,adc-channel-names: List of single-ended channel names.
+- st,filter-order: SinC filter order from 0 to 5.
+ 0: FastSinC
+ [1-5]: order 1 to 5.
+ For audio purpose it is recommended to use order 3 to 5.
+- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers".
+
+Required properties for "st,stm32-dfsdm-adc" compatibility:
+- io-channels: From common IIO binding. Used to pipe external sigma delta
+ modulator or internal ADC output to DFSDM channel.
+ This is not required for "st,stm32-dfsdm-pdm" compatibility as
+ PDM microphone is binded in Audio DT node.
+
+Required properties for "st,stm32-dfsdm-pdm" compatibility:
+- #sound-dai-cells: Must be set to 0.
+- dma: DMA controller phandle and DMA request line associated to the
+ filter instance (specified by the field "reg")
+- dma-names: Must be "rx"
+
+Optional properties:
+- st,adc-channel-types: Single-ended channel input type.
+ - "SPI_R": SPI with data on rising edge (default)
+ - "SPI_F": SPI with data on falling edge
+ - "MANCH_R": manchester codec, rising edge = logic 0
+ - "MANCH_F": manchester codec, falling edge = logic 1
+- st,adc-channel-clk-src: Conversion clock source.
+ - "CLKIN": external SPI clock (CLKIN x)
+ - "CLKOUT": internal SPI clock (CLKOUT) (default)
+ - "CLKOUT_F": internal SPI clock divided by 2 (falling edge).
+ - "CLKOUT_R": internal SPI clock divided by 2 (rising edge).
+
+- st,adc-alt-channel: Must be defined if two sigma delta modulator are
+ connected on same SPI input.
+ If not set, channel n is connected to SPI input n.
+ If set, channel n is connected to SPI input n + 1.
+
+- st,filter0-sync: Set to 1 to synchronize with DFSDM filter instance 0.
+ Used for multi microphones synchronization.
+
+Example of a sigma delta adc connected on DFSDM SPI port 0
+and a pdm microphone connected on DFSDM SPI port 1:
+
+ ads1202: simple_sd_adc@0 {
+ compatible = "ads1202";
+ #io-channel-cells = <1>;
+ };
+
+ dfsdm: dfsdm@40017000 {
+ compatible = "st,stm32h7-dfsdm";
+ reg = <0x40017000 0x400>;
+ clocks = <&rcc DFSDM1_CK>;
+ clock-names = "dfsdm";
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dfsdm_adc0: filter@0 {
+ compatible = "st,stm32-dfsdm-adc";
+ #io-channel-cells = <1>;
+ reg = <0>;
+ interrupts = <110>;
+ st,adc-channels = <0>;
+ st,adc-channel-names = "sd_adc0";
+ st,adc-channel-types = "SPI_F";
+ st,adc-channel-clk-src = "CLKOUT";
+ io-channels = <&ads1202 0>;
+ st,filter-order = <3>;
+ };
+ dfsdm_pdm1: filter@1 {
+ compatible = "st,stm32-dfsdm-dmic";
+ reg = <1>;
+ interrupts = <111>;
+ dmas = <&dmamux1 102 0x400 0x00>;
+ dma-names = "rx";
+ st,adc-channels = <1>;
+ st,adc-channel-names = "dmic1";
+ st,adc-channel-types = "SPI_R";
+ st,adc-channel-clk-src = "CLKOUT";
+ st,filter-order = <5>;
+ };
+ }
--
2.7.4
^ permalink raw reply related
* [PATCH v9 06/13] IIO: ADC: add sigma delta modulator support
From: Arnaud Pouliquen @ 2017-12-14 8:57 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree, alsa-devel, Alexandre Torgue, linux-iio,
arnaud.pouliquen, Maxime Coquelin, linux-arm-kernel
In-Reply-To: <1513241885-32079-1-git-send-email-arnaud.pouliquen@st.com>
Add generic driver to support sigma delta modulators.
Typically, this device is hardware connected to
an IIO device in charge of the conversion. Devices are
bonded through the hardware consumer API.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
drivers/iio/adc/Kconfig | 12 +++++++
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/sd_adc_modulator.c | 68 ++++++++++++++++++++++++++++++++++++++
3 files changed, 81 insertions(+)
create mode 100644 drivers/iio/adc/sd_adc_modulator.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 5762565..c5db62f 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -626,6 +626,18 @@ config SPEAR_ADC
To compile this driver as a module, choose M here: the
module will be called spear_adc.
+config SD_ADC_MODULATOR
+ tristate "Generic sigma delta modulator"
+ depends on OF
+ select IIO_BUFFER
+ select IIO_TRIGGERED_BUFFER
+ help
+ Select this option to enables sigma delta modulator. This driver can
+ support generic sigma delta modulators.
+
+ This driver can also be built as a module. If so, the module
+ will be called sd_adc_modulator.
+
config STM32_ADC_CORE
tristate "STMicroelectronics STM32 adc core"
depends on ARCH_STM32 || COMPILE_TEST
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 9874e05..d800325 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -81,3 +81,4 @@ obj-$(CONFIG_VF610_ADC) += vf610_adc.o
obj-$(CONFIG_VIPERBOARD_ADC) += viperboard_adc.o
xilinx-xadc-y := xilinx-xadc-core.o xilinx-xadc-events.o
obj-$(CONFIG_XILINX_XADC) += xilinx-xadc.o
+obj-$(CONFIG_SD_ADC_MODULATOR) += sd_adc_modulator.o
diff --git a/drivers/iio/adc/sd_adc_modulator.c b/drivers/iio/adc/sd_adc_modulator.c
new file mode 100644
index 0000000..560d8c7
--- /dev/null
+++ b/drivers/iio/adc/sd_adc_modulator.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Generic sigma delta modulator driver
+ *
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>.
+ */
+
+#include <linux/iio/iio.h>
+#include <linux/iio/triggered_buffer.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+
+static const struct iio_info iio_sd_mod_iio_info;
+
+static const struct iio_chan_spec iio_sd_mod_ch = {
+ .type = IIO_VOLTAGE,
+ .indexed = 1,
+ .scan_type = {
+ .sign = 'u',
+ .realbits = 1,
+ .shift = 0,
+ },
+};
+
+static int iio_sd_mod_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct iio_dev *iio;
+
+ iio = devm_iio_device_alloc(dev, 0);
+ if (!iio)
+ return -ENOMEM;
+
+ iio->dev.parent = dev;
+ iio->dev.of_node = dev->of_node;
+ iio->name = dev_name(dev);
+ iio->info = &iio_sd_mod_iio_info;
+ iio->modes = INDIO_BUFFER_HARDWARE;
+
+ iio->num_channels = 1;
+ iio->channels = &iio_sd_mod_ch;
+
+ platform_set_drvdata(pdev, iio);
+
+ return devm_iio_device_register(&pdev->dev, iio);
+}
+
+static const struct of_device_id sd_adc_of_match[] = {
+ { .compatible = "sd-modulator" },
+ { .compatible = "ads1201" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, sd_adc_of_match);
+
+static struct platform_driver iio_sd_mod_adc = {
+ .driver = {
+ .name = "iio_sd_adc_mod",
+ .of_match_table = of_match_ptr(sd_adc_of_match),
+ },
+ .probe = iio_sd_mod_probe,
+};
+
+module_platform_driver(iio_sd_mod_adc);
+
+MODULE_DESCRIPTION("Basic sigma delta modulator");
+MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related
* [PATCH v9 05/13] IIO: Add DT bindings for sigma delta adc modulator
From: Arnaud Pouliquen @ 2017-12-14 8:57 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw, Maxime Coquelin,
Alexandre Torgue, arnaud.pouliquen-qxv4g6HH51o
In-Reply-To: <1513241885-32079-1-git-send-email-arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Add documentation of device tree bindings to support
sigma delta modulator in IIO framework.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Acked-by: Jonathan Cameron <Jonathan.Cameron-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
.../devicetree/bindings/iio/adc/sigma-delta-modulator.txt | 13 +++++++++++++
1 file changed, 13 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt
new file mode 100644
index 0000000..e9ebb8a
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt
@@ -0,0 +1,13 @@
+Device-Tree bindings for sigma delta modulator
+
+Required properties:
+- compatible: should be "ads1201", "sd-modulator". "sd-modulator" can be use
+ as a generic SD modulator if modulator not specified in compatible list.
+- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers".
+
+Example node:
+
+ ads1202: adc@0 {
+ compatible = "sd-modulator";
+ #io-channel-cells = <1>;
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH v9 04/13] IIO: inkern: API for manipulating channel attributes
From: Arnaud Pouliquen @ 2017-12-14 8:57 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw, Maxime Coquelin,
Alexandre Torgue, arnaud.pouliquen-qxv4g6HH51o
In-Reply-To: <1513241885-32079-1-git-send-email-arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Extend the inkern API with functions for reading and writing
attribute of iio channels.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen-qxv4g6HH51o@public.gmane.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
drivers/iio/inkern.c | 17 ++++++++++++-----
include/linux/iio/consumer.h | 26 ++++++++++++++++++++++++++
include/linux/iio/iio.h | 28 ----------------------------
include/linux/iio/types.h | 28 ++++++++++++++++++++++++++++
4 files changed, 66 insertions(+), 33 deletions(-)
diff --git a/drivers/iio/inkern.c b/drivers/iio/inkern.c
index 069defc..ec98790 100644
--- a/drivers/iio/inkern.c
+++ b/drivers/iio/inkern.c
@@ -664,9 +664,8 @@ int iio_convert_raw_to_processed(struct iio_channel *chan, int raw,
}
EXPORT_SYMBOL_GPL(iio_convert_raw_to_processed);
-static int iio_read_channel_attribute(struct iio_channel *chan,
- int *val, int *val2,
- enum iio_chan_info_enum attribute)
+int iio_read_channel_attribute(struct iio_channel *chan, int *val, int *val2,
+ enum iio_chan_info_enum attribute)
{
int ret;
@@ -682,6 +681,7 @@ static int iio_read_channel_attribute(struct iio_channel *chan,
return ret;
}
+EXPORT_SYMBOL_GPL(iio_read_channel_attribute);
int iio_read_channel_offset(struct iio_channel *chan, int *val, int *val2)
{
@@ -850,7 +850,8 @@ static int iio_channel_write(struct iio_channel *chan, int val, int val2,
chan->channel, val, val2, info);
}
-int iio_write_channel_raw(struct iio_channel *chan, int val)
+int iio_write_channel_attribute(struct iio_channel *chan, int val, int val2,
+ enum iio_chan_info_enum attribute)
{
int ret;
@@ -860,12 +861,18 @@ int iio_write_channel_raw(struct iio_channel *chan, int val)
goto err_unlock;
}
- ret = iio_channel_write(chan, val, 0, IIO_CHAN_INFO_RAW);
+ ret = iio_channel_write(chan, val, val2, attribute);
err_unlock:
mutex_unlock(&chan->indio_dev->info_exist_lock);
return ret;
}
+EXPORT_SYMBOL_GPL(iio_write_channel_attribute);
+
+int iio_write_channel_raw(struct iio_channel *chan, int val)
+{
+ return iio_write_channel_attribute(chan, val, 0, IIO_CHAN_INFO_RAW);
+}
EXPORT_SYMBOL_GPL(iio_write_channel_raw);
unsigned int iio_get_channel_ext_info_count(struct iio_channel *chan)
diff --git a/include/linux/iio/consumer.h b/include/linux/iio/consumer.h
index 5e347a9..2017f35 100644
--- a/include/linux/iio/consumer.h
+++ b/include/linux/iio/consumer.h
@@ -216,6 +216,32 @@ int iio_read_channel_average_raw(struct iio_channel *chan, int *val);
int iio_read_channel_processed(struct iio_channel *chan, int *val);
/**
+ * iio_write_channel_attribute() - Write values to the device attribute.
+ * @chan: The channel being queried.
+ * @val: Value being written.
+ * @val2: Value being written.val2 use depends on attribute type.
+ * @attribute: info attribute to be read.
+ *
+ * Returns an error code or 0.
+ */
+int iio_write_channel_attribute(struct iio_channel *chan, int val,
+ int val2, enum iio_chan_info_enum attribute);
+
+/**
+ * iio_read_channel_attribute() - Read values from the device attribute.
+ * @chan: The channel being queried.
+ * @val: Value being written.
+ * @val2: Value being written.Val2 use depends on attribute type.
+ * @attribute: info attribute to be written.
+ *
+ * Returns an error code if failed. Else returns a description of what is in val
+ * and val2, such as IIO_VAL_INT_PLUS_MICRO telling us we have a value of val
+ * + val2/1e6
+ */
+int iio_read_channel_attribute(struct iio_channel *chan, int *val,
+ int *val2, enum iio_chan_info_enum attribute);
+
+/**
* iio_write_channel_raw() - write to a given channel
* @chan: The channel being queried.
* @val: Value being written.
diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h
index c380daa..007caf7 100644
--- a/include/linux/iio/iio.h
+++ b/include/linux/iio/iio.h
@@ -20,34 +20,6 @@
* Currently assumes nano seconds.
*/
-enum iio_chan_info_enum {
- IIO_CHAN_INFO_RAW = 0,
- IIO_CHAN_INFO_PROCESSED,
- IIO_CHAN_INFO_SCALE,
- IIO_CHAN_INFO_OFFSET,
- IIO_CHAN_INFO_CALIBSCALE,
- IIO_CHAN_INFO_CALIBBIAS,
- IIO_CHAN_INFO_PEAK,
- IIO_CHAN_INFO_PEAK_SCALE,
- IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW,
- IIO_CHAN_INFO_AVERAGE_RAW,
- IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY,
- IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY,
- IIO_CHAN_INFO_SAMP_FREQ,
- IIO_CHAN_INFO_FREQUENCY,
- IIO_CHAN_INFO_PHASE,
- IIO_CHAN_INFO_HARDWAREGAIN,
- IIO_CHAN_INFO_HYSTERESIS,
- IIO_CHAN_INFO_INT_TIME,
- IIO_CHAN_INFO_ENABLE,
- IIO_CHAN_INFO_CALIBHEIGHT,
- IIO_CHAN_INFO_CALIBWEIGHT,
- IIO_CHAN_INFO_DEBOUNCE_COUNT,
- IIO_CHAN_INFO_DEBOUNCE_TIME,
- IIO_CHAN_INFO_CALIBEMISSIVITY,
- IIO_CHAN_INFO_OVERSAMPLING_RATIO,
-};
-
enum iio_shared_by {
IIO_SEPARATE,
IIO_SHARED_BY_TYPE,
diff --git a/include/linux/iio/types.h b/include/linux/iio/types.h
index 2aa7b63..6eb3d683 100644
--- a/include/linux/iio/types.h
+++ b/include/linux/iio/types.h
@@ -34,4 +34,32 @@ enum iio_available_type {
IIO_AVAIL_RANGE,
};
+enum iio_chan_info_enum {
+ IIO_CHAN_INFO_RAW = 0,
+ IIO_CHAN_INFO_PROCESSED,
+ IIO_CHAN_INFO_SCALE,
+ IIO_CHAN_INFO_OFFSET,
+ IIO_CHAN_INFO_CALIBSCALE,
+ IIO_CHAN_INFO_CALIBBIAS,
+ IIO_CHAN_INFO_PEAK,
+ IIO_CHAN_INFO_PEAK_SCALE,
+ IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW,
+ IIO_CHAN_INFO_AVERAGE_RAW,
+ IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY,
+ IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY,
+ IIO_CHAN_INFO_SAMP_FREQ,
+ IIO_CHAN_INFO_FREQUENCY,
+ IIO_CHAN_INFO_PHASE,
+ IIO_CHAN_INFO_HARDWAREGAIN,
+ IIO_CHAN_INFO_HYSTERESIS,
+ IIO_CHAN_INFO_INT_TIME,
+ IIO_CHAN_INFO_ENABLE,
+ IIO_CHAN_INFO_CALIBHEIGHT,
+ IIO_CHAN_INFO_CALIBWEIGHT,
+ IIO_CHAN_INFO_DEBOUNCE_COUNT,
+ IIO_CHAN_INFO_DEBOUNCE_TIME,
+ IIO_CHAN_INFO_CALIBEMISSIVITY,
+ IIO_CHAN_INFO_OVERSAMPLING_RATIO,
+};
+
#endif /* _IIO_TYPES_H_ */
--
2.7.4
--
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^ permalink raw reply related
* [PATCH v9 03/13] IIO: hw_consumer: add devm_iio_hw_consumer_alloc
From: Arnaud Pouliquen @ 2017-12-14 8:57 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree, alsa-devel, Alexandre Torgue, linux-iio,
arnaud.pouliquen, Maxime Coquelin, linux-arm-kernel
In-Reply-To: <1513241885-32079-1-git-send-email-arnaud.pouliquen@st.com>
Add devm_iio_hw_consumer_alloc function that calls iio_hw_consumer_free
when the device is unbound from the bus.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
drivers/iio/buffer/industrialio-hw-consumer.c | 66 +++++++++++++++++++++++++++
include/linux/iio/hw-consumer.h | 2 +
2 files changed, 68 insertions(+)
diff --git a/drivers/iio/buffer/industrialio-hw-consumer.c b/drivers/iio/buffer/industrialio-hw-consumer.c
index 993ecdc..9516569 100644
--- a/drivers/iio/buffer/industrialio-hw-consumer.c
+++ b/drivers/iio/buffer/industrialio-hw-consumer.c
@@ -137,6 +137,72 @@ void iio_hw_consumer_free(struct iio_hw_consumer *hwc)
}
EXPORT_SYMBOL_GPL(iio_hw_consumer_free);
+static void devm_iio_hw_consumer_release(struct device *dev, void *res)
+{
+ iio_hw_consumer_free(*(struct iio_hw_consumer **)res);
+}
+
+static int devm_iio_hw_consumer_match(struct device *dev, void *res, void *data)
+{
+ struct iio_hw_consumer **r = res;
+
+ if (!r || !*r) {
+ WARN_ON(!r || !*r);
+ return 0;
+ }
+ return *r == data;
+}
+
+/**
+ * devm_iio_hw_consumer_alloc - Resource-managed iio_hw_consumer_alloc()
+ * @dev: Pointer to consumer device.
+ *
+ * Managed iio_hw_consumer_alloc. iio_hw_consumer allocated with this function
+ * is automatically freed on driver detach.
+ *
+ * If an iio_hw_consumer allocated with this function needs to be freed
+ * separately, devm_iio_hw_consumer_free() must be used.
+ *
+ * returns pointer to allocated iio_hw_consumer on success, NULL on failure.
+ */
+struct iio_hw_consumer *devm_iio_hw_consumer_alloc(struct device *dev)
+{
+ struct iio_hw_consumer **ptr, *iio_hwc;
+
+ ptr = devres_alloc(devm_iio_hw_consumer_release, sizeof(*ptr),
+ GFP_KERNEL);
+ if (!ptr)
+ return NULL;
+
+ iio_hwc = iio_hw_consumer_alloc(dev);
+ if (IS_ERR(iio_hwc)) {
+ devres_free(ptr);
+ } else {
+ *ptr = iio_hwc;
+ devres_add(dev, ptr);
+ }
+
+ return iio_hwc;
+}
+EXPORT_SYMBOL_GPL(devm_iio_hw_consumer_alloc);
+
+/**
+ * devm_iio_hw_consumer_free - Resource-managed iio_hw_consumer_free()
+ * @dev: Pointer to consumer device.
+ * @hwc: iio_hw_consumer to free.
+ *
+ * Free iio_hw_consumer allocated with devm_iio_hw_consumer_alloc().
+ */
+void devm_iio_hw_consumer_free(struct device *dev, struct iio_hw_consumer *hwc)
+{
+ int rc;
+
+ rc = devres_release(dev, devm_iio_hw_consumer_release,
+ devm_iio_hw_consumer_match, hwc);
+ WARN_ON(rc);
+}
+EXPORT_SYMBOL_GPL(devm_iio_hw_consumer_free);
+
/**
* iio_hw_consumer_enable() - Enable IIO hardware consumer
* @hwc: iio_hw_consumer to enable.
diff --git a/include/linux/iio/hw-consumer.h b/include/linux/iio/hw-consumer.h
index db8c00b..44d48bb 100644
--- a/include/linux/iio/hw-consumer.h
+++ b/include/linux/iio/hw-consumer.h
@@ -13,6 +13,8 @@ struct iio_hw_consumer;
struct iio_hw_consumer *iio_hw_consumer_alloc(struct device *dev);
void iio_hw_consumer_free(struct iio_hw_consumer *hwc);
+struct iio_hw_consumer *devm_iio_hw_consumer_alloc(struct device *dev);
+void devm_iio_hw_consumer_free(struct device *dev, struct iio_hw_consumer *hwc);
int iio_hw_consumer_enable(struct iio_hw_consumer *hwc);
void iio_hw_consumer_disable(struct iio_hw_consumer *hwc);
--
2.7.4
^ permalink raw reply related
* [PATCH v9 02/13] docs: driver-api: add iio hw consumer section
From: Arnaud Pouliquen @ 2017-12-14 8:57 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree, alsa-devel, Alexandre Torgue, linux-iio,
arnaud.pouliquen, Maxime Coquelin, linux-arm-kernel
In-Reply-To: <1513241885-32079-1-git-send-email-arnaud.pouliquen@st.com>
This adds a section about the Hardware consumer
API of the IIO subsystem to the driver API
documentation.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Documentation/driver-api/iio/hw-consumer.rst | 51 ++++++++++++++++++++++++++++
Documentation/driver-api/iio/index.rst | 1 +
2 files changed, 52 insertions(+)
create mode 100644 Documentation/driver-api/iio/hw-consumer.rst
diff --git a/Documentation/driver-api/iio/hw-consumer.rst b/Documentation/driver-api/iio/hw-consumer.rst
new file mode 100644
index 0000000..8facce6
--- /dev/null
+++ b/Documentation/driver-api/iio/hw-consumer.rst
@@ -0,0 +1,51 @@
+===========
+HW consumer
+===========
+An IIO device can be directly connected to another device in hardware. in this
+case the buffers between IIO provider and IIO consumer are handled by hardware.
+The Industrial I/O HW consumer offers a way to bond these IIO devices without
+software buffer for data. The implementation can be found under
+:file:`drivers/iio/buffer/hw-consumer.c`
+
+
+* struct :c:type:`iio_hw_consumer` — Hardware consumer structure
+* :c:func:`iio_hw_consumer_alloc` — Allocate IIO hardware consumer
+* :c:func:`iio_hw_consumer_free` — Free IIO hardware consumer
+* :c:func:`iio_hw_consumer_enable` — Enable IIO hardware consumer
+* :c:func:`iio_hw_consumer_disable` — Disable IIO hardware consumer
+
+
+HW consumer setup
+=================
+
+As standard IIO device the implementation is based on IIO provider/consumer.
+A typical IIO HW consumer setup looks like this::
+
+ static struct iio_hw_consumer *hwc;
+
+ static const struct iio_info adc_info = {
+ .read_raw = adc_read_raw,
+ };
+
+ static int adc_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan, int *val,
+ int *val2, long mask)
+ {
+ ret = iio_hw_consumer_enable(hwc);
+
+ /* Acquire data */
+
+ ret = iio_hw_consumer_disable(hwc);
+ }
+
+ static int adc_probe(struct platform_device *pdev)
+ {
+ hwc = devm_iio_hw_consumer_alloc(&iio->dev);
+ }
+
+More details
+============
+.. kernel-doc:: include/linux/iio/hw-consumer.h
+.. kernel-doc:: drivers/iio/buffer/industrialio-hw-consumer.c
+ :export:
+
diff --git a/Documentation/driver-api/iio/index.rst b/Documentation/driver-api/iio/index.rst
index e5c3922..7fba341 100644
--- a/Documentation/driver-api/iio/index.rst
+++ b/Documentation/driver-api/iio/index.rst
@@ -15,3 +15,4 @@ Contents:
buffers
triggers
triggered-buffers
+ hw-consumer
--
2.7.4
_______________________________________________
Alsa-devel mailing list
Alsa-devel@alsa-project.org
http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
^ permalink raw reply related
* [PATCH v9 01/13] iio: Add hardware consumer buffer support
From: Arnaud Pouliquen @ 2017-12-14 8:57 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree, alsa-devel, Alexandre Torgue, linux-iio,
arnaud.pouliquen, Maxime Coquelin, linux-arm-kernel
In-Reply-To: <1513241885-32079-1-git-send-email-arnaud.pouliquen@st.com>
From: Lars-Peter Clausen <lars@metafoo.de>
Hardware consumer interface can be used when one IIO device has
a direct connection to another device in hardware.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
drivers/iio/buffer/Kconfig | 10 ++
drivers/iio/buffer/Makefile | 1 +
drivers/iio/buffer/industrialio-hw-consumer.c | 181 ++++++++++++++++++++++++++
include/linux/iio/hw-consumer.h | 19 +++
4 files changed, 211 insertions(+)
create mode 100644 drivers/iio/buffer/industrialio-hw-consumer.c
create mode 100644 include/linux/iio/hw-consumer.h
diff --git a/drivers/iio/buffer/Kconfig b/drivers/iio/buffer/Kconfig
index 4ffd3db..338774c 100644
--- a/drivers/iio/buffer/Kconfig
+++ b/drivers/iio/buffer/Kconfig
@@ -29,6 +29,16 @@ config IIO_BUFFER_DMAENGINE
Should be selected by drivers that want to use this functionality.
+config IIO_BUFFER_HW_CONSUMER
+ tristate "Industrial I/O HW buffering"
+ help
+ Provides a way to bonding when an IIO device has a direct connection
+ to another device in hardware. In this case buffers for data transfers
+ are handled by hardware.
+
+ Should be selected by drivers that want to use the generic Hw consumer
+ interface.
+
config IIO_KFIFO_BUF
tristate "Industrial I/O buffering based on kfifo"
help
diff --git a/drivers/iio/buffer/Makefile b/drivers/iio/buffer/Makefile
index 85beaae..324a36b 100644
--- a/drivers/iio/buffer/Makefile
+++ b/drivers/iio/buffer/Makefile
@@ -6,5 +6,6 @@
obj-$(CONFIG_IIO_BUFFER_CB) += industrialio-buffer-cb.o
obj-$(CONFIG_IIO_BUFFER_DMA) += industrialio-buffer-dma.o
obj-$(CONFIG_IIO_BUFFER_DMAENGINE) += industrialio-buffer-dmaengine.o
+obj-$(CONFIG_IIO_BUFFER_HW_CONSUMER) += industrialio-hw-consumer.o
obj-$(CONFIG_IIO_TRIGGERED_BUFFER) += industrialio-triggered-buffer.o
obj-$(CONFIG_IIO_KFIFO_BUF) += kfifo_buf.o
diff --git a/drivers/iio/buffer/industrialio-hw-consumer.c b/drivers/iio/buffer/industrialio-hw-consumer.c
new file mode 100644
index 0000000..993ecdc
--- /dev/null
+++ b/drivers/iio/buffer/industrialio-hw-consumer.c
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017 Analog Devices Inc.
+ * Author: Lars-Peter Clausen <lars@metafoo.de>
+ */
+
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+
+#include <linux/iio/iio.h>
+#include <linux/iio/consumer.h>
+#include <linux/iio/hw-consumer.h>
+#include <linux/iio/buffer_impl.h>
+
+/**
+ * struct iio_hw_consumer - IIO hw consumer block
+ * @buffers: hardware buffers list head.
+ * @channels: IIO provider channels.
+ */
+struct iio_hw_consumer {
+ struct list_head buffers;
+ struct iio_channel *channels;
+};
+
+struct hw_consumer_buffer {
+ struct list_head head;
+ struct iio_dev *indio_dev;
+ struct iio_buffer buffer;
+ long scan_mask[];
+};
+
+static struct hw_consumer_buffer *iio_buffer_to_hw_consumer_buffer(
+ struct iio_buffer *buffer)
+{
+ return container_of(buffer, struct hw_consumer_buffer, buffer);
+}
+
+static void iio_hw_buf_release(struct iio_buffer *buffer)
+{
+ struct hw_consumer_buffer *hw_buf =
+ iio_buffer_to_hw_consumer_buffer(buffer);
+ kfree(hw_buf);
+}
+
+static const struct iio_buffer_access_funcs iio_hw_buf_access = {
+ .release = &iio_hw_buf_release,
+ .modes = INDIO_BUFFER_HARDWARE,
+};
+
+static struct hw_consumer_buffer *iio_hw_consumer_get_buffer(
+ struct iio_hw_consumer *hwc, struct iio_dev *indio_dev)
+{
+ size_t mask_size = BITS_TO_LONGS(indio_dev->masklength) * sizeof(long);
+ struct hw_consumer_buffer *buf;
+
+ list_for_each_entry(buf, &hwc->buffers, head) {
+ if (buf->indio_dev == indio_dev)
+ return buf;
+ }
+
+ buf = kzalloc(sizeof(*buf) + mask_size, GFP_KERNEL);
+ if (!buf)
+ return NULL;
+
+ buf->buffer.access = &iio_hw_buf_access;
+ buf->indio_dev = indio_dev;
+ buf->buffer.scan_mask = buf->scan_mask;
+
+ iio_buffer_init(&buf->buffer);
+ list_add_tail(&buf->head, &hwc->buffers);
+
+ return buf;
+}
+
+/**
+ * iio_hw_consumer_alloc() - Allocate IIO hardware consumer
+ * @dev: Pointer to consumer device.
+ *
+ * Returns a valid iio_hw_consumer on success or a ERR_PTR() on failure.
+ */
+struct iio_hw_consumer *iio_hw_consumer_alloc(struct device *dev)
+{
+ struct hw_consumer_buffer *buf;
+ struct iio_hw_consumer *hwc;
+ struct iio_channel *chan;
+ int ret;
+
+ hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
+ if (!hwc)
+ return ERR_PTR(-ENOMEM);
+
+ INIT_LIST_HEAD(&hwc->buffers);
+
+ hwc->channels = iio_channel_get_all(dev);
+ if (IS_ERR(hwc->channels)) {
+ ret = PTR_ERR(hwc->channels);
+ goto err_free_hwc;
+ }
+
+ chan = &hwc->channels[0];
+ while (chan->indio_dev) {
+ buf = iio_hw_consumer_get_buffer(hwc, chan->indio_dev);
+ if (!buf) {
+ ret = -ENOMEM;
+ goto err_put_buffers;
+ }
+ set_bit(chan->channel->scan_index, buf->buffer.scan_mask);
+ chan++;
+ }
+
+ return hwc;
+
+err_put_buffers:
+ list_for_each_entry(buf, &hwc->buffers, head)
+ iio_buffer_put(&buf->buffer);
+ iio_channel_release_all(hwc->channels);
+err_free_hwc:
+ kfree(hwc);
+ return ERR_PTR(ret);
+}
+EXPORT_SYMBOL_GPL(iio_hw_consumer_alloc);
+
+/**
+ * iio_hw_consumer_free() - Free IIO hardware consumer
+ * @hwc: hw consumer to free.
+ */
+void iio_hw_consumer_free(struct iio_hw_consumer *hwc)
+{
+ struct hw_consumer_buffer *buf, *n;
+
+ iio_channel_release_all(hwc->channels);
+ list_for_each_entry_safe(buf, n, &hwc->buffers, head)
+ iio_buffer_put(&buf->buffer);
+ kfree(hwc);
+}
+EXPORT_SYMBOL_GPL(iio_hw_consumer_free);
+
+/**
+ * iio_hw_consumer_enable() - Enable IIO hardware consumer
+ * @hwc: iio_hw_consumer to enable.
+ *
+ * Returns 0 on success.
+ */
+int iio_hw_consumer_enable(struct iio_hw_consumer *hwc)
+{
+ struct hw_consumer_buffer *buf;
+ int ret;
+
+ list_for_each_entry(buf, &hwc->buffers, head) {
+ ret = iio_update_buffers(buf->indio_dev, &buf->buffer, NULL);
+ if (ret)
+ goto err_disable_buffers;
+ }
+
+ return 0;
+
+err_disable_buffers:
+ list_for_each_entry_continue_reverse(buf, &hwc->buffers, head)
+ iio_update_buffers(buf->indio_dev, NULL, &buf->buffer);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(iio_hw_consumer_enable);
+
+/**
+ * iio_hw_consumer_disable() - Disable IIO hardware consumer
+ * @hwc: iio_hw_consumer to disable.
+ */
+void iio_hw_consumer_disable(struct iio_hw_consumer *hwc)
+{
+ struct hw_consumer_buffer *buf;
+
+ list_for_each_entry(buf, &hwc->buffers, head)
+ iio_update_buffers(buf->indio_dev, NULL, &buf->buffer);
+}
+EXPORT_SYMBOL_GPL(iio_hw_consumer_disable);
+
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
+MODULE_DESCRIPTION("Hardware consumer buffer the IIO framework");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/iio/hw-consumer.h b/include/linux/iio/hw-consumer.h
new file mode 100644
index 0000000..db8c00b
--- /dev/null
+++ b/include/linux/iio/hw-consumer.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Industrial I/O in kernel hardware consumer interface
+ *
+ * Copyright 2017 Analog Devices Inc.
+ * Author: Lars-Peter Clausen <lars@metafoo.de>
+ */
+
+#ifndef LINUX_IIO_HW_CONSUMER_H
+#define LINUX_IIO_HW_CONSUMER_H
+
+struct iio_hw_consumer;
+
+struct iio_hw_consumer *iio_hw_consumer_alloc(struct device *dev);
+void iio_hw_consumer_free(struct iio_hw_consumer *hwc);
+int iio_hw_consumer_enable(struct iio_hw_consumer *hwc);
+void iio_hw_consumer_disable(struct iio_hw_consumer *hwc);
+
+#endif
--
2.7.4
^ permalink raw reply related
* [PATCH v9 00/13] Add STM32 DFSDM support
From: Arnaud Pouliquen @ 2017-12-14 8:57 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jaroslav Kysela,
Takashi Iwai, Liam Girdwood, Mark Brown
Cc: devicetree, alsa-devel, Alexandre Torgue, linux-iio,
arnaud.pouliquen, Maxime Coquelin, linux-arm-kernel
Hello
New version to fix patch 10/13: IIO: ADC: add stm32 DFSDM support for PDM microphone
Main deltas V9 vs V8:
- Rework probe and remove order for audio configuration in stm32-dfsdm-adc.c.
- Optimization of the filling of the dma_slave_config struct.
Main deltas V8 vs V7:
- Few typos fixes.
- Function return optimizations in sound/soc/stm/stm32_adfsdm.c.
Main deltas V7 vs V6:
- Replaces the custom license information text with the appropriate
SPDX identifier.
- Few fixes in sound/soc/stm/stm32_adfsdm.c and stm32-dfsdm-core.c.
- Add missing #interrupt-cells in binding examples.
- Integrate last Jonathan's comments.
Main deltas V6 vs V5:
- Fix warning reported by kbuild test in :
include/linux/iio/consumer.h
sound/soc/stm/stm32_adfsdm.c
Main deltas V5 vs V4:
- Integrate ASOC DAI as a subnode of the DFSDM.
- Add in kernel consumer interface to allow to manipulate attribute.
Thanks,
Arnaud
Arnaud Pouliquen (12):
docs: driver-api: add iio hw consumer section
IIO: hw_consumer: add devm_iio_hw_consumer_alloc
IIO: inkern: API for manipulating channel attributes
IIO: Add DT bindings for sigma delta adc modulator
IIO: ADC: add sigma delta modulator support
IIO: add DT bindings for stm32 DFSDM filter
IIO: ADC: add stm32 DFSDM core support
IIO: ADC: add STM32 DFSDM sigma delta ADC support
IIO: ADC: add stm32 DFSDM support for PDM microphone
IIO: consumer: allow to set buffer sizes
ASoC: add bindings for stm32 DFSDM filter
ASoC: stm32: add DFSDM DAI support
Lars-Peter Clausen (1):
iio: Add hardware consumer buffer support
.../ABI/testing/sysfs-bus-iio-dfsdm-adc-stm32 | 16 +
.../bindings/iio/adc/sigma-delta-modulator.txt | 13 +
.../bindings/iio/adc/st,stm32-dfsdm-adc.txt | 128 +++
.../devicetree/bindings/sound/st,stm32-adfsdm.txt | 63 +
Documentation/driver-api/iio/hw-consumer.rst | 51 +
Documentation/driver-api/iio/index.rst | 1 +
drivers/iio/adc/Kconfig | 37 +
drivers/iio/adc/Makefile | 3 +
drivers/iio/adc/sd_adc_modulator.c | 68 ++
drivers/iio/adc/stm32-dfsdm-adc.c | 1216 ++++++++++++++++++++
drivers/iio/adc/stm32-dfsdm-core.c | 309 +++++
drivers/iio/adc/stm32-dfsdm.h | 310 +++++
drivers/iio/buffer/Kconfig | 10 +
drivers/iio/buffer/Makefile | 1 +
drivers/iio/buffer/industrialio-buffer-cb.c | 11 +
drivers/iio/buffer/industrialio-hw-consumer.c | 247 ++++
drivers/iio/inkern.c | 17 +-
include/linux/iio/adc/stm32-dfsdm-adc.h | 18 +
include/linux/iio/consumer.h | 37 +
include/linux/iio/hw-consumer.h | 21 +
include/linux/iio/iio.h | 28 -
include/linux/iio/types.h | 28 +
sound/soc/stm/Kconfig | 11 +
sound/soc/stm/Makefile | 3 +
sound/soc/stm/stm32_adfsdm.c | 347 ++++++
25 files changed, 2961 insertions(+), 33 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-dfsdm-adc-stm32
create mode 100644 Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt
create mode 100644 Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt
create mode 100644 Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt
create mode 100644 Documentation/driver-api/iio/hw-consumer.rst
create mode 100644 drivers/iio/adc/sd_adc_modulator.c
create mode 100644 drivers/iio/adc/stm32-dfsdm-adc.c
create mode 100644 drivers/iio/adc/stm32-dfsdm-core.c
create mode 100644 drivers/iio/adc/stm32-dfsdm.h
create mode 100644 drivers/iio/buffer/industrialio-hw-consumer.c
create mode 100644 include/linux/iio/adc/stm32-dfsdm-adc.h
create mode 100644 include/linux/iio/hw-consumer.h
create mode 100644 sound/soc/stm/stm32_adfsdm.c
--
2.7.4
^ permalink raw reply
* Re: [PATCH 2/3] ARM: dts: add Samsung's exynos4412-based midas boards
From: Krzysztof Kozlowski @ 2017-12-14 8:48 UTC (permalink / raw)
To: Simon Shields
Cc: linux-samsung-soc, Kukjin Kim, devicetree, Marek Szyprowski,
Bartłomiej Żołnierkiewicz
In-Reply-To: <20171212140815.28257-3-simon@lineageos.org>
Hi Simon,
Thanks for new boards!
+Cc Marek, Bartlomiej,
On Tue, Dec 12, 2017 at 3:08 PM, Simon Shields <simon@lineageos.org> wrote:
> "midas" is the codename for a family of smartphones released by Samsung
> Mobile. It includes the Galaxy S3 (GT-I9300/I9305) and the Galaxy
> Note 2 (GT-N7100/N7105). The boards largely have the same peripherals:
> the main differences are touchscreen, display panel and cellular modem.
>
> Signed-off-by: Simon Shields <simon@lineageos.org>
> ---
> arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi | 144 +++
> arch/arm/boot/dts/exynos4412-m0.dts | 14 +
> arch/arm/boot/dts/exynos4412-m3.dts | 19 +
> arch/arm/boot/dts/exynos4412-midas.dtsi | 1291 +++++++++++++++++++++++++++
M0 is essentially Trats2. You are duplicating here almost entire
Trats2 which means:
1. A lot of duplicated code thus it will require more maintenance to
keep DTS synced,
2. It is very difficult to spot the changes and possible errors
between Trats2 and Midas DTSI/M0.
Please make a generic family of devices based on Midas, including
Trats2. You might make it in steps for easier review:
1. Split common Trats2 part,
2. Add new boards.
Also, few minor nits below.
> arch/arm/boot/dts/exynos4412-t0.dts | 51 ++
> 5 files changed, 1519 insertions(+)
> create mode 100644 arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
> create mode 100644 arch/arm/boot/dts/exynos4412-m0.dts
> create mode 100644 arch/arm/boot/dts/exynos4412-m3.dts
> create mode 100644 arch/arm/boot/dts/exynos4412-midas.dtsi
> create mode 100644 arch/arm/boot/dts/exynos4412-t0.dts
>
> diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
> new file mode 100644
> index 000000000000..536195adfe65
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
> @@ -0,0 +1,144 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/dts-v1/;
> +#include "exynos4412-midas.dtsi"
> +
> +/ {
> + regulators {
> + lcd_vdd3_reg: voltage-regulator-10 {
> + compatible = "regulator-fixed";
> + regulator-name = "LCD_VDD_2.2V";
> + regulator-min-microvolt = <2200000>;
> + regulator-max-microvolt = <2200000>;
> + enable-active-high;
> + gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>;
> + };
> +
> + ps_als_reg: voltage-regulator-11 {
> + compatible = "regulator-fixed";
> + regulator-name = "LED_A_3.0V";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + enable-active-high;
> + gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + i2c_ak8975: i2c-gpio-10 {
> + compatible = "i2c-gpio";
> + gpios = <&gpy2 4 GPIO_ACTIVE_HIGH>, <&gpy2 5 GPIO_ACTIVE_HIGH>;
> + i2c-gpio,delay-us = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ak8975@c {
> + compatible = "asahi-kasei,ak8975";
> + reg = <0x0c>;
> + gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + i2c_cm36651: i2c-gpio-11 {
> + compatible = "i2c-gpio";
> + gpios = <&gpf0 0 GPIO_ACTIVE_LOW>, <&gpf0 1 GPIO_ACTIVE_LOW>;
> + i2c-gpio,delay-us = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cm36651@18 {
> + compatible = "capella,cm36651";
> + reg = <0x18>;
> + interrupt-parent = <&gpx0>;
> + interrupts = <2 IRQ_EDGE_TYPE_FALLING>;
> + vled-supply = <&ps_als_reg>;
> + };
> + };
> +};
> +
> +&buck9_reg {
> + maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>;
> +};
> +
> +&cam_af_reg {
> + gpio = <&gpm0 4 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +};
> +
> +&cam_io_reg {
> + gpio = <&gpm0 2 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +};
> +
> +&dsi_0 {
> + vddcore-supply = <&ldo8_reg>;
> + vddio-supply = <&ldo10_reg>;
> + samsung,burst-clock-frequency = <500000000>;
> + samsung,esc-clock-frequency = <20000000>;
> + samsung,pll-clock-frequency = <24000000>;
> + status = "okay";
> +
> + panel@0 {
> + compatible = "samsung,s6e8aa0";
> + reg = <0>;
> + vdd3-supply = <&lcd_vdd3_reg>;
> + vci-supply = <&ldo25_reg>;
> + reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>;
> + power-on-delay= <50>;
> + reset-delay = <100>;
> + init-delay = <100>;
> + flip-horizontal;
> + flip-vertical;
> + panel-width-mm = <58>;
> + panel-height-mm = <103>;
> +
> + display-timings {
> + timing-0 {
> + clock-frequency = <57153600>;
> + hactive = <720>;
> + vactive = <1280>;
> + hfront-porch = <5>;
> + hback-porch = <5>;
> + hsync-len = <5>;
> + vfront-porch = <13>;
> + vback-porch = <1>;
> + vsync-len = <2>;
> + };
> + };
> + };
> +};
> +
> +&i2c_0 {
> + status = "okay";
> +};
> +
> +&i2c_3 {
> + samsung,i2c-sda-delay = <100>;
> + samsung,i2c-slave-addr = <0x10>;
> + samsung,i2c-max-bus-freq = <400000>;
> + pinctrl-0 = <&i2c3_bus>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + mms114-touchscreen@48 {
> + compatible = "melfas,mms114";
> + reg = <0x48>;
> + interrupt-parent = <&gpm2>;
> + interrupts = <3 IRQ_EDGE_TYPE_FALLING>;
> + x-size = <720>;
> + y-size = <1280>;
> + avdd-supply = <&ldo23_reg>;
> + vdd-supply = <&ldo24_reg>;
> + };
> +};
> +
> +&ldo17_reg {
> + regulator-name = "CAM_SENSOR_CORE_1.2V";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> +};
> +
> +&ldo25_reg {
> + regulator-name = "LCD_VCC_3.3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> diff --git a/arch/arm/boot/dts/exynos4412-m0.dts b/arch/arm/boot/dts/exynos4412-m0.dts
> new file mode 100644
> index 000000000000..18aff81682a9
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos4412-m0.dts
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/dts-v1/;
> +#include "exynos4412-galaxy-s3.dtsi"
> +
> +/ {
> + compatible = "samsung,m0", "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
> + model = "Samsung M0 (GT-I9300) based on Exynos4412";
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x40000000 0x40000000>;
> + };
> +};
> +
> diff --git a/arch/arm/boot/dts/exynos4412-m3.dts b/arch/arm/boot/dts/exynos4412-m3.dts
> new file mode 100644
> index 000000000000..e13ee49ad867
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos4412-m3.dts
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/dts-v1/;
> +#include "exynos4412-galaxy-s3.dtsi"
> +
> +/ {
> + compatible = "samsung,m3", "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
> + model = "Samsung M3 (GT-I9305) based on Exynos4412";
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x40000000 0x80000000>;
> + };
> +};
> +
> +&i2c0_bus {
> + // SCL and SDA pins are swapped
Use /* comments (except SPDX line).
> + samsung,pins = "gpd1-1", "gpd1-0";
> +};
> +
> diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi
> new file mode 100644
> index 000000000000..65c1e2d14d26
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi
> @@ -0,0 +1,1291 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/dts-v1/;
> +#include "exynos4412.dtsi"
> +#include "exynos4412-ppmu-common.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/clock/maxim,max77686.h>
> +#include <dt-bindings/pinctrl/samsung.h>
> +
> +/ {
> + compatible = "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
> +
> + aliases {
> + i2c9 = &i2c_max77693;
> + i2c10 = &i2c_max77693_fuel;
> + };
> +
> + chosen {
> + stdout-path = &serial_2;
> + };
> +
> + firmware@204f000 {
> + compatible = "samsung,secure-firmware";
> + reg = <0x0204F000 0x1000>;
> + };
> +
> + fixed-rate-clocks {
> + xxti {
> + compatible = "samsung,clock-xxti", "fixed-clock";
> + clock-frequency = <0>;
> + };
> +
> + xusbxti {
> + compatible = "samsung,clock-xusbxti", "fixed-clock";
> + clock-frequency = <24000000>;
> + };
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cam_io_reg: voltage-regulator-0 {
> + compatible = "regulator-fixed";
> + regulator-name = "CAM_SENSOR_A";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + enable-active-high;
> + status = "disabled";
> + };
> +
> + cam_af_reg: voltage-regulator-1 {
> + compatible = "regulator-fixed";
> + regulator-name = "CAM_AF";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + enable-active-high;
> + status = "disabled";
> + };
> +
> + vsil12: voltage-regulator-6 {
> + compatible = "regulator-fixed";
> + regulator-name = "VSIL_1.2V";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + vin-supply = <&buck7_reg>;
> + };
> +
> + vcc33mhl: voltage-regulator-7 {
> + compatible = "regulator-fixed";
> + regulator-name = "VCC_3.3_MHL";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + vcc18mhl: voltage-regulator-8 {
> + compatible = "regulator-fixed";
> + regulator-name = "VCC_1.8_MHL";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + key-down {
> + gpios = <&gpx3 3 GPIO_ACTIVE_LOW>;
> + linux,code = <114>;
> + label = "volume down";
> + debounce-interval = <10>;
> + };
> +
> + key-up {
> + gpios = <&gpx2 2 GPIO_ACTIVE_LOW>;
> + linux,code = <115>;
> + label = "volume up";
> + debounce-interval = <10>;
> + };
> +
> + key-power {
> + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
> + linux,code = <116>;
> + label = "power";
> + debounce-interval = <10>;
> + wakeup-source;
> + };
> +
> + key-home {
> + gpios = <&gpx0 1 GPIO_ACTIVE_LOW>;
> + linux,code = <172>;
> + label = "home";
> + debounce-inteval = <10>;
> + wakeup-source;
> + };
> + };
> +
> + i2c_max77693: i2c-gpio-0 {
> + compatible = "i2c-gpio";
> + gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>;
> + i2c-gpio,delay-us = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + max77693@66 {
> + compatible = "maxim,max77693";
> + interrupt-parent = <&gpx1>;
> + interrupts = <5 IRQ_EDGE_TYPE_FALLING>;
> + reg = <0x66>;
> +
> + regulators {
> + esafeout1_reg: ESAFEOUT1 {
> + regulator-name = "ESAFEOUT1";
> + };
> + esafeout2_reg: ESAFEOUT2 {
> + regulator-name = "ESAFEOUT2";
> + };
> + charger_reg: CHARGER {
> + regulator-name = "CHARGER";
> + regulator-min-microamp = <60000>;
> + regulator-max-microamp = <2580000>;
> + };
> + };
> +
> + max77693_haptic {
> + compatible = "maxim,max77693-haptic";
> + haptic-supply = <&ldo26_reg>;
> + pwms = <&pwm 0 38022 0>;
> + };
> +
> + charger {
> + compatible = "maxim,max77693-charger";
> +
> + maxim,constant-microvolt = <4350000>;
> + maxim,min-system-microvolt = <3600000>;
> + maxim,thermal-regulation-celsius = <100>;
> + maxim,battery-overcurrent-microamp = <3500000>;
> + maxim,charge-input-threshold-microvolt = <4300000>;
> + };
> + };
> + };
> +
> + i2c_max77693_fuel: i2c-gpio-1 {
> + compatible = "i2c-gpio";
> + gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>, <&gpf1 4 GPIO_ACTIVE_HIGH>;
> + i2c-gpio,delay-us = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + max77693-fuel-gauge@36 {
> + compatible = "maxim,max17047";
> + interrupt-parent = <&gpx2>;
> + interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
> + reg = <0x36>;
> +
> + maxim,over-heat-temp = <700>;
> + maxim,over-volt = <4500>;
> + };
> + };
> +
> + i2c-mhl {
> + compatible = "i2c-gpio";
> + gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>;
> + i2c-gpio,delay-us = <100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pinctrl-0 = <&i2c_mhl_bus>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + sii9234: hdmi-bridge@39 {
> + compatible = "sil,sii9234";
> + avcc33-supply = <&vcc33mhl>;
> + iovcc18-supply = <&vcc18mhl>;
> + avcc12-supply = <&vsil12>;
> + cvcc12-supply = <&vsil12>;
> + reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>;
> + interrupt-parent = <&gpf3>;
> + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x39>;
> +
> + port {
> + mhl_to_hdmi: endpoint {
> + remote-endpoint = <&hdmi_to_mhl>;
> + };
> + };
> + };
> + };
> +
> + camera: camera {
> + pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
> + pinctrl-names = "default";
> + status = "okay";
> + assigned-clocks = <&clock CLK_MOUT_CAM0>,
> + <&clock CLK_MOUT_CAM1>;
> + assigned-clock-parents = <&clock CLK_XUSBXTI>,
> + <&clock CLK_XUSBXTI>;
> + };
> +
> + wlan_pwrseq: sdhci3-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&gpj0 0 GPIO_ACTIVE_LOW>;
> + clocks = <&max77686 MAX77686_CLK_PMIC>;
> + clock-names = "ext_clock";
> + };
> +
> + thermistor-ap {
> + compatible = "murata,ncp15wb473";
> + pullup-uv = <1800000>; /* VCC_1.8V_AP */
> + pullup-ohm = <100000>; /* 100K */
> + pulldown-ohm = <100000>; /* 100K */
> + io-channels = <&adc 1>; /* AP temperature */
> + };
> +
> + thermistor-battery {
> + compatible = "murata,ncp15wb473";
> + pullup-uv = <1800000>; /* VCC_1.8V_AP */
> + pullup-ohm = <100000>; /* 100K */
> + pulldown-ohm = <100000>; /* 100K */
> + io-channels = <&adc 2>; /* Battery temperature */
> + };
> +
> + thermal-zones {
> + cpu_thermal: cpu-thermal {
> + cooling-maps {
> + map0 {
> + /* Corresponds to 800MHz at freq_table */
> + cooling-device = <&cpu0 7 7>;
> + };
> + map1 {
> + /* Corresponds to 200MHz at freq_table */
> + cooling-device = <&cpu0 13 13>;
> + };
> + };
> + };
> + };
> +
> +};
> +
> +&adc {
> + vdd-supply = <&ldo3_reg>;
> + status = "okay";
> +};
> +
> +&bus_dmc {
> + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
> + vdd-supply = <&buck1_reg>;
> + status = "okay";
> +};
> +
> +&bus_acp {
> + devfreq = <&bus_dmc>;
> + status = "okay";
> +};
> +
> +&bus_c2c {
> + devfreq = <&bus_dmc>;
> + status = "okay";
> +};
> +
> +&bus_leftbus {
> + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
> + vdd-supply = <&buck3_reg>;
> + status = "okay";
> +};
> +
> +&bus_rightbus {
> + devfreq = <&bus_leftbus>;
> + status = "okay";
> +};
> +
> +&bus_display {
> + devfreq = <&bus_leftbus>;
> + status = "okay";
> +};
> +
> +&bus_fsys {
> + devfreq = <&bus_leftbus>;
> + status = "okay";
> +};
> +
> +&bus_peri {
> + devfreq = <&bus_leftbus>;
> + status = "okay";
> +};
> +
> +&bus_mfc {
> + devfreq = <&bus_leftbus>;
> + status = "okay";
> +};
> +
> +&cpu0 {
> + cpu0-supply = <&buck2_reg>;
> +};
> +
> +&csis_0 {
> + status = "okay";
> + vddcore-supply = <&ldo8_reg>;
> + vddio-supply = <&ldo10_reg>;
> + assigned-clocks = <&clock CLK_MOUT_CSIS0>,
> + <&clock CLK_SCLK_CSIS0>;
> + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
> + assigned-clock-rates = <0>, <176000000>;
> +
> + /* Camera C (3) MIPI CSI-2 (CSIS0) */
> + port@3 {
> + reg = <3>;
> + csis0_ep: endpoint {
> + remote-endpoint = <&s5c73m3_ep>;
> + data-lanes = <1 2 3 4>;
> + samsung,csis-hs-settle = <12>;
> + };
> + };
> +};
> +
> +&csis_1 {
> + status = "okay";
> + vddcore-supply = <&ldo8_reg>;
> + vddio-supply = <&ldo10_reg>;
> + assigned-clocks = <&clock CLK_MOUT_CSIS1>,
> + <&clock CLK_SCLK_CSIS1>;
> + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
> + assigned-clock-rates = <0>, <176000000>;
> +
> + /* Camera D (4) MIPI CSI-2 (CSIS1) */
> + port@4 {
> + reg = <4>;
> + csis1_ep: endpoint {
> + remote-endpoint = <&is_s5k6a3_ep>;
> + data-lanes = <1>;
> + samsung,csis-hs-settle = <18>;
> + samsung,csis-wclk;
> + };
> + };
> +};
> +
> +&exynos_usbphy {
> + vbus-supply = <&esafeout1_reg>;
> + status = "okay";
> +};
> +
> +&fimc_0 {
> + status = "okay";
> + assigned-clocks = <&clock CLK_MOUT_FIMC0>,
> + <&clock CLK_SCLK_FIMC0>;
> + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
> + assigned-clock-rates = <0>, <176000000>;
> +};
> +
> +&fimc_1 {
> + status = "okay";
> + assigned-clocks = <&clock CLK_MOUT_FIMC1>,
> + <&clock CLK_SCLK_FIMC1>;
> + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
> + assigned-clock-rates = <0>, <176000000>;
> +};
> +
> +&fimc_2 {
> + status = "okay";
> + assigned-clocks = <&clock CLK_MOUT_FIMC2>,
> + <&clock CLK_SCLK_FIMC2>;
> + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
> + assigned-clock-rates = <0>, <176000000>;
> +};
> +
> +&fimc_3 {
> + status = "okay";
> + assigned-clocks = <&clock CLK_MOUT_FIMC3>,
> + <&clock CLK_SCLK_FIMC3>;
> + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
> + assigned-clock-rates = <0>, <176000000>;
> +};
> +
> +&fimc_is {
> + pinctrl-0 = <&fimc_is_uart>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + i2c1_isp: i2c-isp@12140000 {
> + pinctrl-0 = <&fimc_is_i2c1>;
> + pinctrl-names = "default";
> +
> + s5k6a3@10 {
> + compatible = "samsung,s5k6a3";
> + reg = <0x10>;
> + svdda-supply = <&cam_io_reg>;
> + svddio-supply = <&ldo19_reg>;
> + afvdd-supply = <&ldo19_reg>;
> + clock-frequency = <24000000>;
> + /* CAM_B_CLKOUT */
> + clocks = <&camera 1>;
> + clock-names = "extclk";
> + samsung,camclk-out = <1>;
> + gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>;
> +
> + port {
> + is_s5k6a3_ep: endpoint {
> + remote-endpoint = <&csis1_ep>;
> + data-lanes = <1>;
> + };
> + };
> + };
> + };
> +};
> +
> +&fimc_lite_0 {
> + status = "okay";
> +};
> +
> +&fimc_lite_1 {
> + status = "okay";
> +};
> +
> +&fimd {
> + status = "okay";
> +};
> +
> +&hdmi {
> + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hdmi_hpd>;
> + vdd-supply = <&ldo3_reg>;
> + vdd_osc-supply = <&ldo4_reg>;
> + vdd_pll-supply = <&ldo3_reg>;
> + ddc = <&i2c_5>;
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> + hdmi_to_mhl: endpoint {
> + remote-endpoint = <&mhl_to_hdmi>;
> + };
> + };
> + };
> +};
> +
> +&hsotg {
> + vusb_d-supply = <&ldo15_reg>;
> + vusb_a-supply = <&ldo12_reg>;
> + dr_mode = "peripheral";
> + status = "okay";
> +};
> +
> +&i2c_0 {
> + samsung,i2c-sda-delay = <100>;
> + samsung,i2c-slave-addr = <0x10>;
> + samsung,i2c-max-bus-freq = <400000>;
> + pinctrl-0 = <&i2c0_bus>;
> + pinctrl-names = "default";
> +
> + status = "disabled";
> +
> + s5c73m3@3c {
> + compatible = "samsung,s5c73m3";
> + reg = <0x3c>;
> + standby-gpios = <&gpm0 1 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */
> + xshutdown-gpios = <&gpf1 3 GPIO_ACTIVE_LOW>; /* ISP_RESET */
> + vdd-int-supply = <&buck9_reg>;
> + vddio-cis-supply = <&ldo9_reg>;
> + vdda-supply = <&ldo17_reg>;
> + vddio-host-supply = <&ldo18_reg>;
> + vdd-af-supply = <&cam_af_reg>;
> + vdd-reg-supply = <&cam_io_reg>;
> + clock-frequency = <24000000>;
> + /* CAM_A_CLKOUT */
> + clocks = <&camera 0>;
> + clock-names = "cis_extclk";
> + port {
> + s5c73m3_ep: endpoint {
> + remote-endpoint = <&csis0_ep>;
> + data-lanes = <1 2 3 4>;
> + };
> + };
> + };
> +};
> +
> +&i2c_4 {
> + samsung,i2c-sda-delay = <100>;
> + samsung,i2c-slave-addr = <0x10>;
> + samsung,i2c-max-bus-freq = <100000>;
> + pinctrl-0 = <&i2c4_bus>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + wm1811: wm1811@1a {
> + compatible = "wlf,wm1811";
> + reg = <0x1a>;
> + clocks = <&pmu_system_controller 0>;
> + clock-names = "MCLK1";
> + DCVDD-supply = <&ldo3_reg>;
> + DBVDD1-supply = <&ldo3_reg>;
> + wlf,ldo1ena = <&gpj0 4 0>;
> + };
> +};
> +
> +&i2c_5 {
> + status = "okay";
> +};
> +
> +&i2c_7 {
> + samsung,i2c-sda-delay = <100>;
> + samsung,i2c-slave-addr = <0x10>;
> + samsung,i2c-max-bus-freq = <100000>;
> + pinctrl-0 = <&i2c7_bus>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + max77686: max77686_pmic@9 {
> + compatible = "maxim,max77686";
> + interrupt-parent = <&gpx0>;
> + interrupts = <7 IRQ_EDGE_TYPE_NONE>;
> + reg = <0x09>;
> + #clock-cells = <1>;
> +
> + voltage-regulators {
> + ldo1_reg: LDO1 {
> + regulator-name = "VALIVE_1.0V_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + };
> +
> + ldo2_reg: LDO2 {
> + regulator-name = "VM1M2_1.2V_AP";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + };
> + };
> +
> + ldo3_reg: LDO3 {
> + regulator-name = "VCC_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo4_reg: LDO4 {
> + regulator-name = "VCC_2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-always-on;
> + };
> +
> + ldo5_reg: LDO5 {
> + regulator-name = "VTOUCH_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo6_reg: LDO6 {
> + regulator-name = "VMPLL_1.0V_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + };
> + };
> +
> + ldo7_reg: LDO7 {
> + regulator-name = "VPLL_1.0V_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + };
> + };
> +
> + ldo8_reg: LDO8 {
> + regulator-name = "VMIPI_1.0V";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo9_reg: LDO9 {
> + regulator-name = "CAM_ISP_MIPI_1.2V";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + ldo10_reg: LDO10 {
> + regulator-name = "VMIPI_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo11_reg: LDO11 {
> + regulator-name = "VABB1_1.95V";
> + regulator-min-microvolt = <1950000>;
> + regulator-max-microvolt = <1950000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo12_reg: LDO12 {
> + regulator-name = "VUOTG_3.0V";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo13_reg: LDO13 {
> + status = "disabled";
> + };
> +
> + ldo14_reg: LDO14 {
> + regulator-name = "VABB2_1.95V";
> + regulator-min-microvolt = <1950000>;
> + regulator-max-microvolt = <1950000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo15_reg: LDO15 {
> + regulator-name = "VHSIC_1.0V";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + };
> + };
> +
> + ldo16_reg: LDO16 {
> + regulator-name = "VHSIC_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + };
> + };
> +
> + ldo17_reg: LDO17 {
> + status = "disabled";
> + };
> +
> + ldo18_reg: LDO18 {
> + regulator-name = "CAM_ISP_SENSOR_IO_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo19_reg: LDO19 {
> + regulator-name = "VT_CAM_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo20_reg: LDO20 {
> + regulator-name = "VDDQ_PRE_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo21_reg: LDO21 {
> + regulator-name = "VTF_2.8V";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>;
> + };
> +
> + ldo22_reg: LDO22 {
> + regulator-name = "VMEM_VDD_2.8V";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
> + };
> +
> + ldo23_reg: LDO23 {
> + regulator-name = "TSP_AVDD_3.3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + ldo24_reg: LDO24 {
> + regulator-name = "TSP_VDD_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo25_reg: LDO25 {
> + status = "disabled";
> + };
> +
> + ldo26_reg: LDO26 {
> + regulator-name = "MOTOR_VCC_3.0V";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + };
> +
> + buck1_reg: BUCK1 {
> + regulator-name = "vdd_mif";
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck2_reg: BUCK2 {
> + regulator-name = "vdd_arm";
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + };
> + };
> +
> + buck3_reg: BUCK3 {
> + regulator-name = "vdd_int";
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <1150000>;
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck4_reg: BUCK4 {
> + regulator-name = "vdd_g3d";
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <1150000>;
> + regulator-boot-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck5_reg: BUCK5 {
> + regulator-name = "VMEM_1.2V_AP";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + buck6_reg: BUCK6 {
> + regulator-name = "VCC_SUB_1.35V";
> + regulator-min-microvolt = <1350000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-always-on;
> + };
> +
> + buck7_reg: BUCK7 {
> + regulator-name = "VCC_SUB_2.0V";
> + regulator-min-microvolt = <2000000>;
> + regulator-max-microvolt = <2000000>;
> + regulator-always-on;
> + };
> +
> + buck8_reg: BUCK8 {
> + regulator-name = "VMEM_VDDF_3.0V";
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <2850000>;
> + maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
> + };
> +
> + buck9_reg: BUCK9 {
> + regulator-name = "CAM_ISP_CORE_1.2V";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1200000>;
> + };
> + };
> + };
> +};
> +
> +&i2c_8 {
> + status = "okay";
> +};
> +
> +&i2s0 {
> + pinctrl-0 = <&i2s0_bus>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&mixer {
> + status = "okay";
> +};
> +
> +&mshc_0 {
> + broken-cd;
> + non-removable;
> + card-detect-delay = <200>;
> + vmmc-supply = <&ldo22_reg>;
> + clock-frequency = <400000000>;
> + samsung,dw-mshc-ciu-div = <0>;
> + samsung,dw-mshc-sdr-timing = <2 3>;
> + samsung,dw-mshc-ddr-timing = <1 2>;
> + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
> + pinctrl-names = "default";
> + status = "okay";
> + bus-width = <8>;
> + cap-mmc-highspeed;
> +};
> +
> +&pmu_system_controller {
> + assigned-clocks = <&pmu_system_controller 0>;
> + assigned-clock-parents = <&clock CLK_XUSBXTI>;
> +};
> +
> +&pinctrl_0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&sleep0>;
> +
> + mhl_int: mhl-int {
> + samsung,pins = "gpf3-5";
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + };
> +
> + i2c_mhl_bus: i2c-mhl-bus {
> + samsung,pins = "gpf0-4", "gpf0-6";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
> + };
> +
> + sleep0: sleep-states {
> + PIN_SLP(gpa0-0, INPUT, NONE);
> + PIN_SLP(gpa0-1, OUT0, NONE);
> + PIN_SLP(gpa0-2, INPUT, NONE);
> + PIN_SLP(gpa0-3, INPUT, UP);
> + PIN_SLP(gpa0-4, INPUT, NONE);
> + PIN_SLP(gpa0-5, INPUT, DOWN);
> + PIN_SLP(gpa0-6, INPUT, DOWN);
> + PIN_SLP(gpa0-7, INPUT, UP);
> +
> + PIN_SLP(gpa1-0, INPUT, DOWN);
> + PIN_SLP(gpa1-1, INPUT, DOWN);
> + PIN_SLP(gpa1-2, INPUT, DOWN);
> + PIN_SLP(gpa1-3, INPUT, DOWN);
> + PIN_SLP(gpa1-4, INPUT, DOWN);
> + PIN_SLP(gpa1-5, INPUT, DOWN);
> +
> + PIN_SLP(gpb-0, INPUT, NONE);
> + PIN_SLP(gpb-1, INPUT, NONE);
> + PIN_SLP(gpb-2, INPUT, NONE);
> + PIN_SLP(gpb-3, INPUT, NONE);
> + PIN_SLP(gpb-4, INPUT, DOWN);
> + PIN_SLP(gpb-5, INPUT, UP);
> + PIN_SLP(gpb-6, INPUT, DOWN);
> + PIN_SLP(gpb-7, INPUT, DOWN);
> +
> + PIN_SLP(gpc0-0, INPUT, DOWN);
> + PIN_SLP(gpc0-1, INPUT, DOWN);
> + PIN_SLP(gpc0-2, INPUT, DOWN);
> + PIN_SLP(gpc0-3, INPUT, DOWN);
> + PIN_SLP(gpc0-4, INPUT, DOWN);
> +
> + PIN_SLP(gpc1-0, INPUT, NONE);
> + PIN_SLP(gpc1-1, PREV, NONE);
> + PIN_SLP(gpc1-2, INPUT, NONE);
> + PIN_SLP(gpc1-3, INPUT, NONE);
> + PIN_SLP(gpc1-4, INPUT, NONE);
> +
> + PIN_SLP(gpd0-0, INPUT, DOWN);
> + PIN_SLP(gpd0-1, INPUT, DOWN);
> + PIN_SLP(gpd0-2, INPUT, NONE);
> + PIN_SLP(gpd0-3, INPUT, NONE);
> +
> + PIN_SLP(gpd1-0, INPUT, DOWN);
> + PIN_SLP(gpd1-1, INPUT, DOWN);
> + PIN_SLP(gpd1-2, INPUT, NONE);
> + PIN_SLP(gpd1-3, INPUT, NONE);
> +
> + PIN_SLP(gpf0-0, INPUT, NONE);
> + PIN_SLP(gpf0-1, INPUT, NONE);
> + PIN_SLP(gpf0-2, INPUT, DOWN);
> + PIN_SLP(gpf0-3, INPUT, DOWN);
> + PIN_SLP(gpf0-4, INPUT, NONE);
> + PIN_SLP(gpf0-5, INPUT, DOWN);
> + PIN_SLP(gpf0-6, INPUT, NONE);
> + PIN_SLP(gpf0-7, INPUT, DOWN);
> +
> + PIN_SLP(gpf1-0, INPUT, DOWN);
> + PIN_SLP(gpf1-1, INPUT, DOWN);
> + PIN_SLP(gpf1-2, INPUT, DOWN);
> + PIN_SLP(gpf1-3, INPUT, DOWN);
> + PIN_SLP(gpf1-4, INPUT, NONE);
> + PIN_SLP(gpf1-5, INPUT, NONE);
> + PIN_SLP(gpf1-6, INPUT, DOWN);
> + PIN_SLP(gpf1-7, PREV, NONE);
> +
> + PIN_SLP(gpf2-0, PREV, NONE);
> + PIN_SLP(gpf2-1, INPUT, DOWN);
> + PIN_SLP(gpf2-2, INPUT, DOWN);
> + PIN_SLP(gpf2-3, INPUT, DOWN);
> + PIN_SLP(gpf2-4, INPUT, DOWN);
> + PIN_SLP(gpf2-5, INPUT, DOWN);
> + PIN_SLP(gpf2-6, INPUT, NONE);
> + PIN_SLP(gpf2-7, INPUT, NONE);
> +
> + PIN_SLP(gpf3-0, INPUT, NONE);
> + PIN_SLP(gpf3-1, PREV, NONE);
> + PIN_SLP(gpf3-2, PREV, NONE);
> + PIN_SLP(gpf3-3, PREV, NONE);
> + PIN_SLP(gpf3-4, OUT1, NONE);
> + PIN_SLP(gpf3-5, INPUT, DOWN);
> +
> + PIN_SLP(gpj0-0, PREV, NONE);
> + PIN_SLP(gpj0-1, PREV, NONE);
> + PIN_SLP(gpj0-2, PREV, NONE);
> + PIN_SLP(gpj0-3, INPUT, DOWN);
> + PIN_SLP(gpj0-4, PREV, NONE);
> + PIN_SLP(gpj0-5, PREV, NONE);
> + PIN_SLP(gpj0-6, INPUT, DOWN);
> + PIN_SLP(gpj0-7, INPUT, DOWN);
> +
> + PIN_SLP(gpj1-0, INPUT, DOWN);
> + PIN_SLP(gpj1-1, PREV, NONE);
> + PIN_SLP(gpj1-2, PREV, NONE);
> + PIN_SLP(gpj1-3, INPUT, DOWN);
> + PIN_SLP(gpj1-4, INPUT, DOWN);
> + };
> +};
> +
> +&pinctrl_1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&sleep1>;
> +
> + hdmi_hpd: hdmi-hpd {
> + samsung,pins = "gpx3-7";
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + };
> +
> + sleep1: sleep-states {
> + PIN_SLP(gpk0-0, PREV, NONE);
> + PIN_SLP(gpk0-1, PREV, NONE);
> + PIN_SLP(gpk0-2, OUT0, NONE);
> + PIN_SLP(gpk0-3, PREV, NONE);
> + PIN_SLP(gpk0-4, PREV, NONE);
> + PIN_SLP(gpk0-5, PREV, NONE);
> + PIN_SLP(gpk0-6, PREV, NONE);
> +
> + PIN_SLP(gpk1-0, INPUT, DOWN);
> + PIN_SLP(gpk1-1, INPUT, DOWN);
> + PIN_SLP(gpk1-2, INPUT, DOWN);
> + PIN_SLP(gpk1-3, PREV, NONE);
> + PIN_SLP(gpk1-4, PREV, NONE);
> + PIN_SLP(gpk1-5, PREV, NONE);
> + PIN_SLP(gpk1-6, PREV, NONE);
> +
> + PIN_SLP(gpk2-0, INPUT, DOWN);
> + PIN_SLP(gpk2-1, INPUT, DOWN);
> + PIN_SLP(gpk2-2, INPUT, DOWN);
> + PIN_SLP(gpk2-3, INPUT, DOWN);
> + PIN_SLP(gpk2-4, INPUT, DOWN);
> + PIN_SLP(gpk2-5, INPUT, DOWN);
> + PIN_SLP(gpk2-6, INPUT, DOWN);
> +
> + PIN_SLP(gpk3-0, OUT0, NONE);
> + PIN_SLP(gpk3-1, INPUT, NONE);
> + PIN_SLP(gpk3-2, INPUT, DOWN);
> + PIN_SLP(gpk3-3, INPUT, NONE);
> + PIN_SLP(gpk3-4, INPUT, NONE);
> + PIN_SLP(gpk3-5, INPUT, NONE);
> + PIN_SLP(gpk3-6, INPUT, NONE);
> +
> + PIN_SLP(gpl0-0, INPUT, DOWN);
> + PIN_SLP(gpl0-1, INPUT, DOWN);
> + PIN_SLP(gpl0-2, INPUT, DOWN);
> + PIN_SLP(gpl0-3, INPUT, DOWN);
> + PIN_SLP(gpl0-4, PREV, NONE);
> + PIN_SLP(gpl0-6, PREV, NONE);
> +
> + PIN_SLP(gpl1-0, INPUT, DOWN);
> + PIN_SLP(gpl1-1, INPUT, DOWN);
> + PIN_SLP(gpl2-0, INPUT, DOWN);
> + PIN_SLP(gpl2-1, INPUT, DOWN);
> + PIN_SLP(gpl2-2, INPUT, DOWN);
> + PIN_SLP(gpl2-3, INPUT, DOWN);
> + PIN_SLP(gpl2-4, INPUT, DOWN);
> + PIN_SLP(gpl2-5, INPUT, DOWN);
> + PIN_SLP(gpl2-6, PREV, NONE);
> + PIN_SLP(gpl2-7, INPUT, DOWN);
> +
> + PIN_SLP(gpm0-0, INPUT, DOWN);
> + PIN_SLP(gpm0-1, INPUT, DOWN);
> + PIN_SLP(gpm0-2, INPUT, DOWN);
> + PIN_SLP(gpm0-3, INPUT, DOWN);
> + PIN_SLP(gpm0-4, INPUT, DOWN);
> + PIN_SLP(gpm0-5, INPUT, DOWN);
> + PIN_SLP(gpm0-6, INPUT, DOWN);
> + PIN_SLP(gpm0-7, INPUT, DOWN);
> +
> + PIN_SLP(gpm1-0, INPUT, DOWN);
> + PIN_SLP(gpm1-1, INPUT, DOWN);
> + PIN_SLP(gpm1-2, INPUT, NONE);
> + PIN_SLP(gpm1-3, INPUT, NONE);
> + PIN_SLP(gpm1-4, INPUT, NONE);
> + PIN_SLP(gpm1-5, INPUT, NONE);
> + PIN_SLP(gpm1-6, INPUT, DOWN);
> +
> + PIN_SLP(gpm2-0, INPUT, NONE);
> + PIN_SLP(gpm2-1, INPUT, NONE);
> + PIN_SLP(gpm2-2, INPUT, DOWN);
> + PIN_SLP(gpm2-3, INPUT, DOWN);
> + PIN_SLP(gpm2-4, INPUT, DOWN);
> +
> + PIN_SLP(gpm3-0, PREV, NONE);
> + PIN_SLP(gpm3-1, PREV, NONE);
> + PIN_SLP(gpm3-2, PREV, NONE);
> + PIN_SLP(gpm3-3, OUT1, NONE);
> + PIN_SLP(gpm3-4, INPUT, DOWN);
> + PIN_SLP(gpm3-5, INPUT, DOWN);
> + PIN_SLP(gpm3-6, INPUT, DOWN);
> + PIN_SLP(gpm3-7, INPUT, DOWN);
> +
> + PIN_SLP(gpm4-0, INPUT, DOWN);
> + PIN_SLP(gpm4-1, INPUT, DOWN);
> + PIN_SLP(gpm4-2, INPUT, DOWN);
> + PIN_SLP(gpm4-3, INPUT, DOWN);
> + PIN_SLP(gpm4-4, INPUT, DOWN);
> + PIN_SLP(gpm4-5, INPUT, DOWN);
> + PIN_SLP(gpm4-6, INPUT, DOWN);
> + PIN_SLP(gpm4-7, INPUT, DOWN);
> +
> + PIN_SLP(gpy0-0, INPUT, DOWN);
> + PIN_SLP(gpy0-1, INPUT, DOWN);
> + PIN_SLP(gpy0-2, INPUT, DOWN);
> + PIN_SLP(gpy0-3, INPUT, DOWN);
> + PIN_SLP(gpy0-4, INPUT, DOWN);
> + PIN_SLP(gpy0-5, INPUT, DOWN);
> +
> + PIN_SLP(gpy1-0, INPUT, DOWN);
> + PIN_SLP(gpy1-1, INPUT, DOWN);
> + PIN_SLP(gpy1-2, INPUT, DOWN);
> + PIN_SLP(gpy1-3, INPUT, DOWN);
> +
> + PIN_SLP(gpy2-0, PREV, NONE);
> + PIN_SLP(gpy2-1, INPUT, DOWN);
> + PIN_SLP(gpy2-2, INPUT, NONE);
> + PIN_SLP(gpy2-3, INPUT, NONE);
> + PIN_SLP(gpy2-4, INPUT, NONE);
> + PIN_SLP(gpy2-5, INPUT, NONE);
> +
> + PIN_SLP(gpy3-0, INPUT, DOWN);
> + PIN_SLP(gpy3-1, INPUT, DOWN);
> + PIN_SLP(gpy3-2, INPUT, DOWN);
> + PIN_SLP(gpy3-3, INPUT, DOWN);
> + PIN_SLP(gpy3-4, INPUT, DOWN);
> + PIN_SLP(gpy3-5, INPUT, DOWN);
> + PIN_SLP(gpy3-6, INPUT, DOWN);
> + PIN_SLP(gpy3-7, INPUT, DOWN);
> +
> + PIN_SLP(gpy4-0, INPUT, DOWN);
> + PIN_SLP(gpy4-1, INPUT, DOWN);
> + PIN_SLP(gpy4-2, INPUT, DOWN);
> + PIN_SLP(gpy4-3, INPUT, DOWN);
> + PIN_SLP(gpy4-4, INPUT, DOWN);
> + PIN_SLP(gpy4-5, INPUT, DOWN);
> + PIN_SLP(gpy4-6, INPUT, DOWN);
> + PIN_SLP(gpy4-7, INPUT, DOWN);
> +
> + PIN_SLP(gpy5-0, INPUT, DOWN);
> + PIN_SLP(gpy5-1, INPUT, DOWN);
> + PIN_SLP(gpy5-2, INPUT, DOWN);
> + PIN_SLP(gpy5-3, INPUT, DOWN);
> + PIN_SLP(gpy5-4, INPUT, DOWN);
> + PIN_SLP(gpy5-5, INPUT, DOWN);
> + PIN_SLP(gpy5-6, INPUT, DOWN);
> + PIN_SLP(gpy5-7, INPUT, DOWN);
> +
> + PIN_SLP(gpy6-0, INPUT, DOWN);
> + PIN_SLP(gpy6-1, INPUT, DOWN);
> + PIN_SLP(gpy6-2, INPUT, DOWN);
> + PIN_SLP(gpy6-3, INPUT, DOWN);
> + PIN_SLP(gpy6-4, INPUT, DOWN);
> + PIN_SLP(gpy6-5, INPUT, DOWN);
> + PIN_SLP(gpy6-6, INPUT, DOWN);
> + PIN_SLP(gpy6-7, INPUT, DOWN);
> + };
> +};
> +
> +&pinctrl_2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&sleep2>;
> +
> + sleep2: sleep-states {
> + PIN_SLP(gpz-0, INPUT, DOWN);
> + PIN_SLP(gpz-1, INPUT, DOWN);
> + PIN_SLP(gpz-2, INPUT, DOWN);
> + PIN_SLP(gpz-3, INPUT, DOWN);
> + PIN_SLP(gpz-4, INPUT, DOWN);
> + PIN_SLP(gpz-5, INPUT, DOWN);
> + PIN_SLP(gpz-6, INPUT, DOWN);
> + };
> +};
> +
> +&pinctrl_3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&sleep3>;
> +
> + sleep3: sleep-states {
> + PIN_SLP(gpv0-0, INPUT, DOWN);
> + PIN_SLP(gpv0-1, INPUT, DOWN);
> + PIN_SLP(gpv0-2, INPUT, DOWN);
> + PIN_SLP(gpv0-3, INPUT, DOWN);
> + PIN_SLP(gpv0-4, INPUT, DOWN);
> + PIN_SLP(gpv0-5, INPUT, DOWN);
> + PIN_SLP(gpv0-6, INPUT, DOWN);
> + PIN_SLP(gpv0-7, INPUT, DOWN);
> +
> + PIN_SLP(gpv1-0, INPUT, DOWN);
> + PIN_SLP(gpv1-1, INPUT, DOWN);
> + PIN_SLP(gpv1-2, INPUT, DOWN);
> + PIN_SLP(gpv1-3, INPUT, DOWN);
> + PIN_SLP(gpv1-4, INPUT, DOWN);
> + PIN_SLP(gpv1-5, INPUT, DOWN);
> + PIN_SLP(gpv1-6, INPUT, DOWN);
> + PIN_SLP(gpv1-7, INPUT, DOWN);
> +
> + PIN_SLP(gpv2-0, INPUT, DOWN);
> + PIN_SLP(gpv2-1, INPUT, DOWN);
> + PIN_SLP(gpv2-2, INPUT, DOWN);
> + PIN_SLP(gpv2-3, INPUT, DOWN);
> + PIN_SLP(gpv2-4, INPUT, DOWN);
> + PIN_SLP(gpv2-5, INPUT, DOWN);
> + PIN_SLP(gpv2-6, INPUT, DOWN);
> + PIN_SLP(gpv2-7, INPUT, DOWN);
> +
> + PIN_SLP(gpv3-0, INPUT, DOWN);
> + PIN_SLP(gpv3-1, INPUT, DOWN);
> + PIN_SLP(gpv3-2, INPUT, DOWN);
> + PIN_SLP(gpv3-3, INPUT, DOWN);
> + PIN_SLP(gpv3-4, INPUT, DOWN);
> + PIN_SLP(gpv3-5, INPUT, DOWN);
> + PIN_SLP(gpv3-6, INPUT, DOWN);
> + PIN_SLP(gpv3-7, INPUT, DOWN);
> +
> + PIN_SLP(gpv4-0, INPUT, DOWN);
> + };
> +};
> +
> +&pwm {
> + pinctrl-0 = <&pwm0_out>;
> + pinctrl-names = "default";
> + samsung,pwm-outputs = <0>;
> + status = "okay";
> +};
> +
> +&rtc {
> + status = "okay";
> + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
> + clock-names = "rtc", "rtc_src";
> +};
> +
> +&sdhci_2 {
> + bus-width = <4>;
> + cd-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>;
> + cd-inverted;
> + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
> + pinctrl-names = "default";
> + vmmc-supply = <&ldo21_reg>;
> + status = "okay";
> +};
> +
> +&sdhci_3 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
> +
> + broken-cd;
> +
> + mmc-pwrseq = <&wlan_pwrseq>;
> +
> + bus-width = <4>;
> + status = "okay";
> +
> + brcmf: wifi@1 {
> + reg = <1>;
> + compatible = "brcm,bcm4329-fmac";
> + interrupt-parent = <&gpx2>;
> + interrupts = <5 IRQ_TYPE_NONE>;
> + interrupt-names = "host-wake";
> + };
> +};
> +
> +&serial_0 {
> + status = "okay";
> +};
> +
> +&serial_1 {
> + status = "okay";
> +};
> +
> +&serial_2 {
> + status = "okay";
> +};
> +
> +&serial_3 {
> + status = "okay";
> +};
> +
> +&sleep0 {
> + gpf1-0 {
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> + };
> +};
> +
> +&spi_1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi1_bus>;
> + cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +
> + s5c73m3_spi: s5c73m3@0 {
> + compatible = "samsung,s5c73m3";
> + spi-max-frequency = <50000000>;
> + reg = <0>;
> + controller-data {
> + samsung,spi-feedback-delay = <2>;
> + };
> + };
> +};
> +
> +&tmu {
> + vtmu-supply = <&ldo10_reg>;
> + status = "okay";
> +};
> +
> +&pmu_system_controller {
> + compatible = "samsung,exynos4210-pmu", "syscon", "simple-mfd";
> +
> + reboot-mode {
> + compatible = "syscon-reboot-mode";
> + offset = <0x80c>;
> +
> + mode-normal = <0x12345670>;
> + mode-bootloader = <0x12345671>;
> + mode-download = <0x12345671>;
> + mode-recovery = <0x12345674>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/exynos4412-t0.dts b/arch/arm/boot/dts/exynos4412-t0.dts
> new file mode 100644
> index 000000000000..c49abe857b6f
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos4412-t0.dts
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/dts-v1/;
> +#include "exynos4412-midas.dtsi"
> +
> +/ {
> + compatible = "samsung,t0", "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
> + model = "Samsung T0 (GT-N7100, GT-N7105) based on Exynos4412";
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x40000000 0x80000000>;
> + };
> +
Unnecessary blank line.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v4 00/15] drm/sun4i: Add A83t LVDS support
From: Maxime Ripard @ 2017-12-14 8:37 UTC (permalink / raw)
To: Priit Laes
Cc: Daniel Vetter, David Airlie, Chen-Yu Tsai,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Mark Rutland, Rob Herring,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
icenowy-h8G6r0blFSE, Thomas Petazzoni, jernej.skrabec-gGgVlfcn5nU,
devicetree-u79uwXL29TY76Z2rM5mHXA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <20171214070157.rqx4tfpluzaqmtxu-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 728 bytes --]
On Thu, Dec 14, 2017 at 07:01:57AM +0000, Priit Laes wrote:
> On Thu, Dec 07, 2017 at 04:58:45PM +0100, Maxime Ripard wrote:
> > Hi,
> >
> > Here is an attempt at supporting the LVDS output in our DRM driver. This
> > has been tested on the A83T (with DE2), but since everything is basically
> > in the TCON, it should also be usable on the older SoCs with minor
> > modifications.
>
> I managed to get the single-channel LVDS working on an A10 tablet after
> doing those minor modifications (although, the colours are off a bit).
> So in general this series looks good :)
Is that a Tested-by? :)
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* Re: [alsa-devel] [PATCH v10 08/13] regmap: add SLIMbus support
From: Takashi Iwai @ 2017-12-14 8:19 UTC (permalink / raw)
To: Vinod Koul
Cc: Mark Brown, Greg Kroah-Hartman, Mark Rutland, devicetree,
alsa-devel, Jonathan Corbet, linux-arm-msm, linux-doc,
j.neuschaefer, linux-kernel, Rob Herring, srinivas.kandagatla,
pombredanne, sdharia
In-Reply-To: <20171214051739.GV18649@localhost>
On Thu, 14 Dec 2017 06:17:39 +0100,
Vinod Koul wrote:
>
> On Wed, Dec 13, 2017 at 04:06:11PM +0000, Mark Brown wrote:
> > > On Mon, Dec 11, 2017 at 11:43:02PM +0000, srinivas.kandagatla@linaro.org wrote:
> >
> > > Mark, can I get an Ack for this patch so I can take it through my tree
> > > with the other patches in this series?
> >
> > I'm actually not seeing a direct dependency here (there's a depends in
> > place stopping the regmap code building if the Slimbus core isn't
> > enabled) so if you want you can go ahead and apply the main stuff and I
> > can apply the regmap change separately, it'll avoid Makefile/Kconfig
> > conflicts anyway.
>
> + Takashi
>
> FWIW, since this is another MIPI Audio specfic bus, would it make sense for
> this series to go thru sound/ tree? I have discussed with Takashi and Greg
> for soundwire and we are taking sound path.
>
> Would that be okay here too? Either ways I dont mind :)
Me too, I don't mind who takes what.
Just let me know.
thanks,
Takashi
^ permalink raw reply
* Re: [RFC V7 2/2] OPP: Allow "opp-hz" and "opp-microvolt" to contain magic values
From: Viresh Kumar @ 2017-12-14 7:30 UTC (permalink / raw)
To: Stephen Boyd
Cc: Ulf Hansson, Rob Herring, Kevin Hilman, Viresh Kumar,
Nishanth Menon, Rafael Wysocki, linux-pm@vger.kernel.org,
Vincent Guittot, Rajendra Nayak, Sudeep Holla,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <20171130065907.GI11413@vireshk-i7>
On 30-11-17, 12:29, Viresh Kumar wrote:
> On 29-11-17, 16:50, Stephen Boyd wrote:
> > Sorry it still makes zero sense to me. It seems that we're trying
> > to make the OPP table parsing generic just for the sake of code
> > brevity.
>
> Not just the code but bindings as well to make sure we don't add a new
> property (similar to earlier ones) for every platform that wants to
> use performance states.
@Stephen: Do you have any feedback on my previous email? If no, then I
would like to refresh this version with the feedback received from
Rob.
--
viresh
^ permalink raw reply
* Re: [PATCH v4 00/15] drm/sun4i: Add A83t LVDS support
From: Priit Laes @ 2017-12-14 7:01 UTC (permalink / raw)
To: Maxime Ripard
Cc: Daniel Vetter, David Airlie, Chen-Yu Tsai, dri-devel,
linux-kernel, Mark Rutland, Rob Herring, linux-arm-kernel,
icenowy, Thomas Petazzoni, jernej.skrabec, devicetree,
thierry.reding
In-Reply-To: <cover.e46a07c0e181d735c807dc94fe0ce0ea013788be.1512662253.git-series.maxime.ripard@free-electrons.com>
On Thu, Dec 07, 2017 at 04:58:45PM +0100, Maxime Ripard wrote:
> Hi,
>
> Here is an attempt at supporting the LVDS output in our DRM driver. This
> has been tested on the A83T (with DE2), but since everything is basically
> in the TCON, it should also be usable on the older SoCs with minor
> modifications.
I managed to get the single-channel LVDS working on an A10 tablet after
doing those minor modifications (although, the colours are off a bit).
So in general this series looks good :)
>
> This was the occasion to refactor a bunch of things. The most notable ones
> would be the documentation, and split of the UI layers in the mixer code,
> and the switch to kfifo for our endpoint parsing code in the driver that
> fixes an issue introduced by the switch to BFS.
>
> Let me know what you think,
> Maxime
>
> Changes from v3:
> - Collect the tags
> - Use SPDX headers when possible
> - Added the new mixer configuration options
> - Changed the LVDS clock for lvds-alt instead of lvds-pll
> - Removed the MIPI PLL from the A31s
> - Changed the LVDS_ANA0 macros name to reflect the generation they were
> introduced in, and added a comment to mention the changes needed to
> support the older SoCs
>
> Changes from v2:
> - Move the module clock rate to the mixer structure
> - Adjusted the simple-panel documentation for power-supply
> - Changed the compatible for the first A83t mixer to mixer 0
> - Rebased on top of current drm-misc
> - Split out the A83t bindings in its separate patch
>
> Changes from v1:
> - Added a fix for the error path handling in the TCON
> - Enable the TCON by default
> - Removed the patch that changes the channels offset but kept most of the
> modifications as a cleanup
> - Deal with the LVDS clock being able to have another PLL parent on some
> SoCs
> - Renamed the TCON compatible to TCON-TV, following the convention used
> on newer SoCs
> - Removed the hardcoded timings
> - Moved LVDS enable quirks to a separate function
> - Used clock indices define in the DT
> - Removed the hardcoded clock rate in the DT and moved it to the driver
> - Changed sun8i_mixer_planes to sun8i_mixer_ui_planes to be consistent
> - Added the various tags collected
> - Rebased on top of 4.15
>
> Maxime Ripard (15):
> dt-bindings: panel: lvds: Document power-supply property
> drm/panel: lvds: Add support for the power-supply property
> dt-bindings: display: sun4i-drm: Add LVDS properties
> dt-bindings: display: sun4i-drm: Add A83T pipeline
> drm/sun4i: Fix error path handling
> drm/sun4i: Force the mixer rate at 150MHz
> drm/sun4i: Create minimal multipliers and dividers
> drm/sun4i: Add LVDS support
> drm/sun4i: Add A83T support
> ARM: dts: sun8i: a83t: Add display pipeline
> ARM: dts: sun8i: a83t: Enable the PWM
> ARM: dts: sun8i: a83t: Add LVDS pins group
> ARM: dts: sun8i: a83t: Add the PWM pin group
> ARM: dts: sun8i: a711: Reinstate the PMIC compatible
> ARM: dts: sun8i: a711: Enable the LCD
>
> Documentation/devicetree/bindings/display/panel/panel-common.txt | 6 ++-
> Documentation/devicetree/bindings/display/panel/panel-lvds.txt | 1 +-
> Documentation/devicetree/bindings/display/panel/simple-panel.txt | 2 +-
> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 12 +++-
> arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 62 ++++++++++++++++++-
> arch/arm/boot/dts/sun8i-a83t.dtsi | 99 ++++++++++++++++++++++++++++-
> drivers/gpu/drm/panel/panel-lvds.c | 23 +++++++-
> drivers/gpu/drm/sun4i/Makefile | 1 +-
> drivers/gpu/drm/sun4i/sun4i_dotclock.c | 10 ++-
> drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +-
> drivers/gpu/drm/sun4i/sun4i_lvds.c | 177 +++++++++++++++++++++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/sun4i/sun4i_lvds.h | 18 +++++-
> drivers/gpu/drm/sun4i/sun4i_tcon.c | 251 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/sun4i/sun4i_tcon.h | 31 +++++++++-
> drivers/gpu/drm/sun4i/sun8i_mixer.c | 20 ++++++-
> drivers/gpu/drm/sun4i/sun8i_mixer.h | 3 +-
> 16 files changed, 710 insertions(+), 7 deletions(-)
> create mode 100644 drivers/gpu/drm/sun4i/sun4i_lvds.c
> create mode 100644 drivers/gpu/drm/sun4i/sun4i_lvds.h
>
> base-commit: 3b71239181e5429702387666f1ac70a9e6856cce
> --
> git-series 0.9.1
^ permalink raw reply
* Re: [PATCH 1/1] arm: sunxi: Add alternative pins for spi0
From: Stefan Mavrodiev @ 2017-12-14 6:24 UTC (permalink / raw)
To: Maxime Ripard, Stefan Mavrodiev
Cc: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Rob Herring, Mark Rutland,
Russell King, Chen-Yu Tsai,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM PORT, open list
In-Reply-To: <20171213154035.qc655iahjoeflftq-ZC1Zs529Oq4@public.gmane.org>
On 12/13/2017 05:40 PM, Maxime Ripard wrote:
> Hi,
>
> On Wed, Dec 13, 2017 at 09:44:34AM +0200, Stefan Mavrodiev wrote:
>> Allwinner A10/A13/A20 SoCs have pinmux for spi0
>> on port C. The patch adds these pins in the respective
>> dts includes.
>>
>> Signed-off-by: Stefan Mavrodiev <stefan-kyXcfZUBQGPQT0dZR+AlfA@public.gmane.org>
> Do you have any boards that are using these?
>
> We won't merge that patch if there's no users for it.
>
> Maxime
>
A20-OLinuXino-Lime/Lime2 and A10-OLinuXino-Lime with spi flash.
For A13 we still doesn't have that option.
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^ permalink raw reply
* Re: [PATCH 00/12] Marvell NAND controller rework with ->exec_op()
From: Boris Brezillon @ 2017-12-14 6:09 UTC (permalink / raw)
To: Miquel Raynal, Robert Jarzmik
Cc: David Woodhouse, Brian Norris, Marek Vasut, Richard Weinberger,
Cyrille Pitchen, Rob Herring, Mark Rutland, Jason Cooper,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth, Russell King,
Daniel Mack, Haojian Zhuang, Eric Miao, Catalin Marinas,
Will Deacon, Ezequiel Garcia, linux-mtd-IAPFreCvJWMP3drIcvDWNA
In-Reply-To: <20171207201814.30411-1-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Hi,
On Thu, 7 Dec 2017 21:18:02 +0100
Miquel Raynal <miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> Hi,
>
> After the addition of the NAND framework ->exec_op() interface (see [1]
> for the series preparing it and [2] for the last version of the
> core-side implementation of ->exec_op() itself), this series replaces
> the current Marvell NAND controller driver pxa3xx_nand.c with a rework
> called marvell_nand.c.
>
> Aside the fact that it drops the big state machine, improves the overall
> speed and implements raw accesses, it is the first driver-side
> implementation of the ->exec_op() interface and may be used as reference
> for latter reworks of the same type.
>
> One may find more detail about why a completely new driver is needed in
> the commit log of:
>
> "mtd: nand: add reworked Marvell NAND controller driver"
>
> The series also changes the device tree NAND node definition for all
> platforms referring to the Marvell driver to use the new bindings. They
> are more hierarchical and fit the real organization of the hardware, by
> having NAND partitions that are part of NAND chip nodes, themselves part
> of the NAND controller node.
>
> These changes have been tested on:
> - PXA3xx platform with a CM-X300 board (2kiB page NAND, 1b/512B
> strength, Hamming ECC engine) [32 bits]
> - Armada 385 DB AP (4kiB page NAND, 4b/512B, BCH ECC engine) [32 bits]
> - Armada 398 DB (4kiB page NAND, 8b/512B, BCH ECC engine using a layout
> with a last chunk different than the others) [32 bits]
> - Armada 7040 DB and Armada 8040 DB (4kiB page NAND, 4b/512B, BCH ECC
> engine) [64 bits]
>
> Robert, it would be great if you could also do more testing on PXA and
> validate this driver. If needed, a branch ready to be tested is
> available at [3]. It is based on nand/next and has all the changes
> brought by the previously mentionned series as well as this one.
Robert, do you think you'll have some time to test Miquel's branch on
your PXA boards? Miquel already tested on one of these boards (CM-X300),
but we'd like to have other testers. Also feel free to review the
driver if have the time.
Thanks,
Boris
>
> Thank you,
> Miquèl
>
>
> [1] https://www.spinics.net/lists/arm-kernel/msg619633.html
> [2] http://lists.infradead.org/pipermail/linux-mtd/2017-December/077965.html
> [3] https://github.com/miquelraynal/linux/tree/marvell/nand-next/nfc-rework
>
> Miquel Raynal (12):
> dt-bindings: mtd: add Marvell NAND controller documentation
> mtd: nand: add reworked Marvell NAND controller driver
> mtd: nand: replace pxa3xx_nand driver by its rework called
> marvell_nand
> dt-bindings: mtd: remove pxa3xx NAND controller documentation
> mtd: nand: remove useless fields from pxa3xx NAND platform data
> ARM: dts: armada-370-xp: use reworked NAND controller driver
> ARM: dts: armada-375: use reworked NAND controller driver
> ARM: dts: armada-38x: use reworked NAND controller driver
> ARM: dts: armada-39x: use reworked NAND controller driver
> ARM: dts: pxa: use reworked NAND controller driver
> ARM64: dts: marvell: use reworked NAND controller driver on Armada 7K
> ARM64: dts: marvell: use reworked NAND controller driver on Armada 8K
>
> .../devicetree/bindings/mtd/marvell-nand.txt | 84 +
> .../devicetree/bindings/mtd/pxa3xx-nand.txt | 50 -
> arch/arm/boot/dts/armada-370-db.dts | 57 +-
> arch/arm/boot/dts/armada-370-dlink-dns327l.dts | 120 +-
> arch/arm/boot/dts/armada-370-mirabox.dts | 51 +-
> arch/arm/boot/dts/armada-370-netgear-rn102.dts | 90 +-
> arch/arm/boot/dts/armada-370-netgear-rn104.dts | 90 +-
> arch/arm/boot/dts/armada-370-rd.dts | 52 +-
> arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi | 64 +-
> arch/arm/boot/dts/armada-370-xp.dtsi | 6 +-
> arch/arm/boot/dts/armada-375-db.dts | 50 +-
> arch/arm/boot/dts/armada-375.dtsi | 6 +-
> arch/arm/boot/dts/armada-385-db-ap.dts | 69 +-
> arch/arm/boot/dts/armada-385-linksys-caiman.dts | 129 +-
> arch/arm/boot/dts/armada-385-linksys-cobra.dts | 129 +-
> arch/arm/boot/dts/armada-385-linksys-rango.dts | 141 +-
> arch/arm/boot/dts/armada-385-linksys-shelby.dts | 129 +-
> arch/arm/boot/dts/armada-385-linksys.dtsi | 16 +-
> arch/arm/boot/dts/armada-388-db.dts | 55 +-
> arch/arm/boot/dts/armada-38x.dtsi | 6 +-
> arch/arm/boot/dts/armada-390-db.dts | 66 +-
> arch/arm/boot/dts/armada-395-gp.dts | 74 +-
> arch/arm/boot/dts/armada-398-db.dts | 60 +-
> arch/arm/boot/dts/armada-39x.dtsi | 6 +-
> arch/arm/boot/dts/armada-xp-db-dxbc2.dts | 2 +-
> arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 2 +-
> arch/arm/boot/dts/armada-xp-db.dts | 2 +-
> arch/arm/boot/dts/armada-xp-gp.dts | 2 +-
> arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts | 2 +-
> arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 156 +-
> arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 90 +-
> arch/arm/boot/dts/pxa3xx.dtsi | 6 +-
> arch/arm/configs/cm_x300_defconfig | 2 +-
> arch/arm/configs/mvebu_v7_defconfig | 2 +-
> arch/arm/configs/pxa3xx_defconfig | 3 +-
> arch/arm/configs/pxa_defconfig | 2 +-
> arch/arm/configs/raumfeld_defconfig | 2 +-
> arch/arm/mach-mmp/ttc_dkb.c | 4 +-
> arch/arm/mach-pxa/cm-x300.c | 8 +-
> arch/arm/mach-pxa/colibri-pxa3xx.c | 8 +-
> arch/arm/mach-pxa/colibri.h | 2 +-
> arch/arm/mach-pxa/littleton.c | 10 +-
> arch/arm/mach-pxa/mxm8x10.c | 10 +-
> arch/arm/mach-pxa/raumfeld.c | 6 +-
> arch/arm/mach-pxa/zylonite.c | 10 +-
> arch/arm64/boot/dts/marvell/armada-7040-db.dts | 52 +-
> arch/arm64/boot/dts/marvell/armada-8040-db.dts | 46 +-
> .../boot/dts/marvell/armada-cp110-master.dtsi | 8 +-
> .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 10 +-
> drivers/mtd/nand/Kconfig | 12 +
> drivers/mtd/nand/Makefile | 2 +-
> drivers/mtd/nand/marvell_nand.c | 2950 ++++++++++++++++++++
> drivers/mtd/nand/pxa3xx_nand.c | 2104 --------------
> include/linux/platform_data/mtd-nand-pxa3xx.h | 43 +-
> 54 files changed, 4093 insertions(+), 3065 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/mtd/marvell-nand.txt
> delete mode 100644 Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
> create mode 100644 drivers/mtd/nand/marvell_nand.c
> delete mode 100644 drivers/mtd/nand/pxa3xx_nand.c
>
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^ permalink raw reply
* [PATCH v3 2/2] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver
From: Dhaval Shah @ 2017-12-14 5:55 UTC (permalink / raw)
To: arnd-r2nGTMty4D4, gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
pombredanne-od1rfyK75/E, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
michal.simek-gjFFaj9aHVfQT0dZR+AlfA, hyunk-gjFFaj9aHVfQT0dZR+AlfA,
Dhaval Shah
In-Reply-To: <1513230920-9005-1-git-send-email-dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
Xilinx ZYNQMP logicoreIP Init driver is based on the new
LogiCoreIP design created. This driver provides the processing system
and programmable logic isolation. Set the frequency based on the clock
information get from the logicoreIP register set.
It is put in drivers/misc as there is no subsystem for this logicoreIP.
Signed-off-by: Dhaval Shah <dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
---
Changes since v3:
No Changes.
Changes since v2:
* Removed the "default n" from the Kconfig
* More help text added to explain more about the logicoreIP driver
* SPDX id is relocated at top of the file with // style comment
* Removed the export API and header file and make it a single driver
which provides logocoreIP init.
* Provide the information in commit message as well for the why driver
in drivers/misc.
drivers/misc/Kconfig | 15 ++
drivers/misc/Makefile | 1 +
drivers/misc/xlnx_vcu.c | 629 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 645 insertions(+)
create mode 100644 drivers/misc/xlnx_vcu.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index f1a5c23..24ea516 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -496,6 +496,21 @@ config PCI_ENDPOINT_TEST
Enable this configuration option to enable the host side test driver
for PCI Endpoint.
+config XILINX_VCU
+ tristate "Xilinx VCU logicoreIP Init"
+ help
+ Provides the driver to enable and disable the isolation between the
+ processing system and programmable logic part by using the logicoreIP
+ register set. This driver also configure the frequency based on the
+ clock information get from the logicoreIP register set.
+
+ If you say yes here you get support for the logcoreIP.
+
+ If unsure, say N.
+
+ To compile this driver as a module, choose M here: the
+ module will be called xlnx_vcu.
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 5ca5f64..a6bd0b1 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_CXL_BASE) += cxl/
obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
+obj-$(CONFIG_XILINX_VCU) += xlnx_vcu.o
lkdtm-$(CONFIG_LKDTM) += lkdtm_core.o
lkdtm-$(CONFIG_LKDTM) += lkdtm_bugs.o
diff --git a/drivers/misc/xlnx_vcu.c b/drivers/misc/xlnx_vcu.c
new file mode 100644
index 0000000..41819f0
--- /dev/null
+++ b/drivers/misc/xlnx_vcu.c
@@ -0,0 +1,629 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx VCU Init
+ *
+ * Copyright (C) 2016 - 2017 Xilinx, Inc.
+ *
+ * Contacts Dhaval Shah <dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ */
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+/* Address map for different registers implemented in the VCU LogiCORE IP. */
+#define VCU_ECODER_ENABLE 0x00
+#define VCU_DECODER_ENABLE 0x04
+#define VCU_MEMORY_DEPTH 0x08
+#define VCU_ENC_COLOR_DEPTH 0x0c
+#define VCU_ENC_VERTICAL_RANGE 0x10
+#define VCU_ENC_FRAME_SIZE_X 0x14
+#define VCU_ENC_FRAME_SIZE_Y 0x18
+#define VCU_ENC_COLOR_FORMAT 0x1c
+#define VCU_ENC_FPS 0x20
+#define VCU_MCU_CLK 0x24
+#define VCU_CORE_CLK 0x28
+#define VCU_PLL_BYPASS 0x2c
+#define VCU_ENC_CLK 0x30
+#define VCU_PLL_CLK 0x34
+#define VCU_ENC_VIDEO_STANDARD 0x38
+#define VCU_STATUS 0x3c
+#define VCU_AXI_ENC_CLK 0x40
+#define VCU_AXI_DEC_CLK 0x44
+#define VCU_AXI_MCU_CLK 0x48
+#define VCU_DEC_VIDEO_STANDARD 0x4c
+#define VCU_DEC_FRAME_SIZE_X 0x50
+#define VCU_DEC_FRAME_SIZE_Y 0x54
+#define VCU_DEC_FPS 0x58
+#define VCU_BUFFER_B_FRAME 0x5c
+#define VCU_WPP_EN 0x60
+#define VCU_PLL_CLK_DEC 0x64
+#define VCU_GASKET_INIT 0x74
+#define VCU_GASKET_VALUE 0x03
+
+/* vcu slcr registers, bitmask and shift */
+#define VCU_PLL_CTRL 0x24
+#define VCU_PLL_CTRL_RESET_MASK 0x01
+#define VCU_PLL_CTRL_RESET_SHIFT 0
+#define VCU_PLL_CTRL_BYPASS_MASK 0x01
+#define VCU_PLL_CTRL_BYPASS_SHIFT 3
+#define VCU_PLL_CTRL_FBDIV_MASK 0x7f
+#define VCU_PLL_CTRL_FBDIV_SHIFT 8
+#define VCU_PLL_CTRL_POR_IN_MASK 0x01
+#define VCU_PLL_CTRL_POR_IN_SHIFT 1
+#define VCU_PLL_CTRL_PWR_POR_MASK 0x01
+#define VCU_PLL_CTRL_PWR_POR_SHIFT 2
+#define VCU_PLL_CTRL_CLKOUTDIV_MASK 0x03
+#define VCU_PLL_CTRL_CLKOUTDIV_SHIFT 16
+#define VCU_PLL_CTRL_DEFAULT 0
+#define VCU_PLL_DIV2 2
+
+#define VCU_PLL_CFG 0x28
+#define VCU_PLL_CFG_RES_MASK 0x0f
+#define VCU_PLL_CFG_RES_SHIFT 0
+#define VCU_PLL_CFG_CP_MASK 0x0f
+#define VCU_PLL_CFG_CP_SHIFT 5
+#define VCU_PLL_CFG_LFHF_MASK 0x03
+#define VCU_PLL_CFG_LFHF_SHIFT 10
+#define VCU_PLL_CFG_LOCK_CNT_MASK 0x03ff
+#define VCU_PLL_CFG_LOCK_CNT_SHIFT 13
+#define VCU_PLL_CFG_LOCK_DLY_MASK 0x7f
+#define VCU_PLL_CFG_LOCK_DLY_SHIFT 25
+#define VCU_ENC_CORE_CTRL 0x30
+#define VCU_ENC_MCU_CTRL 0x34
+#define VCU_DEC_CORE_CTRL 0x38
+#define VCU_DEC_MCU_CTRL 0x3c
+#define VCU_PLL_DIVISOR_MASK 0x3f
+#define VCU_PLL_DIVISOR_SHIFT 4
+#define VCU_SRCSEL_MASK 0x01
+#define VCU_SRCSEL_SHIFT 0
+#define VCU_SRCSEL_PLL 1
+
+#define VCU_PLL_STATUS 0x60
+#define VCU_PLL_STATUS_LOCK_STATUS_MASK 0x01
+
+#define MHZ 1000000
+#define FVCO_MIN (1500U * MHZ)
+#define FVCO_MAX (3000U * MHZ)
+#define DIVISOR_MIN 0
+#define DIVISOR_MAX 63
+#define FRAC 100
+#define LIMIT (10 * MHZ)
+
+/**
+ * struct xvcu_device - Xilinx VCU init device structure
+ * @dev: Platform device
+ * @pll_ref: pll ref clock source
+ * @aclk: axi clock source
+ * @logicore_reg_ba: logicore reg base address
+ * @vcu_slcr_ba: vcu_slcr Register base address
+ * @coreclk: core clock frequency
+ */
+struct xvcu_device {
+ struct device *dev;
+ struct clk *pll_ref;
+ struct clk *aclk;
+ void __iomem *logicore_reg_ba;
+ void __iomem *vcu_slcr_ba;
+ u32 coreclk;
+};
+
+/**
+ * struct xvcu_pll_cfg - Helper data
+ * @fbdiv: The integer portion of the feedback divider to the PLL
+ * @cp: PLL charge pump control
+ * @res: PLL loop filter resistor control
+ * @lfhf: PLL loop filter high frequency capacitor control
+ * @lock_dly: Lock circuit configuration settings for lock windowsize
+ * @lock_cnt: Lock circuit counter setting
+ */
+struct xvcu_pll_cfg {
+ u32 fbdiv;
+ u32 cp;
+ u32 res;
+ u32 lfhf;
+ u32 lock_dly;
+ u32 lock_cnt;
+};
+
+static const struct xvcu_pll_cfg xvcu_pll_cfg[] = {
+ { 25, 3, 10, 3, 63, 1000 },
+ { 26, 3, 10, 3, 63, 1000 },
+ { 27, 4, 6, 3, 63, 1000 },
+ { 28, 4, 6, 3, 63, 1000 },
+ { 29, 4, 6, 3, 63, 1000 },
+ { 30, 4, 6, 3, 63, 1000 },
+ { 31, 6, 1, 3, 63, 1000 },
+ { 32, 6, 1, 3, 63, 1000 },
+ { 33, 4, 10, 3, 63, 1000 },
+ { 34, 5, 6, 3, 63, 1000 },
+ { 35, 5, 6, 3, 63, 1000 },
+ { 36, 5, 6, 3, 63, 1000 },
+ { 37, 5, 6, 3, 63, 1000 },
+ { 38, 5, 6, 3, 63, 975 },
+ { 39, 3, 12, 3, 63, 950 },
+ { 40, 3, 12, 3, 63, 925 },
+ { 41, 3, 12, 3, 63, 900 },
+ { 42, 3, 12, 3, 63, 875 },
+ { 43, 3, 12, 3, 63, 850 },
+ { 44, 3, 12, 3, 63, 850 },
+ { 45, 3, 12, 3, 63, 825 },
+ { 46, 3, 12, 3, 63, 800 },
+ { 47, 3, 12, 3, 63, 775 },
+ { 48, 3, 12, 3, 63, 775 },
+ { 49, 3, 12, 3, 63, 750 },
+ { 50, 3, 12, 3, 63, 750 },
+ { 51, 3, 2, 3, 63, 725 },
+ { 52, 3, 2, 3, 63, 700 },
+ { 53, 3, 2, 3, 63, 700 },
+ { 54, 3, 2, 3, 63, 675 },
+ { 55, 3, 2, 3, 63, 675 },
+ { 56, 3, 2, 3, 63, 650 },
+ { 57, 3, 2, 3, 63, 650 },
+ { 58, 3, 2, 3, 63, 625 },
+ { 59, 3, 2, 3, 63, 625 },
+ { 60, 3, 2, 3, 63, 625 },
+ { 61, 3, 2, 3, 63, 600 },
+ { 62, 3, 2, 3, 63, 600 },
+ { 63, 3, 2, 3, 63, 600 },
+ { 64, 3, 2, 3, 63, 600 },
+ { 65, 3, 2, 3, 63, 600 },
+ { 66, 3, 2, 3, 63, 600 },
+ { 67, 3, 2, 3, 63, 600 },
+ { 68, 3, 2, 3, 63, 600 },
+ { 69, 3, 2, 3, 63, 600 },
+ { 70, 3, 2, 3, 63, 600 },
+ { 71, 3, 2, 3, 63, 600 },
+ { 72, 3, 2, 3, 63, 600 },
+ { 73, 3, 2, 3, 63, 600 },
+ { 74, 3, 2, 3, 63, 600 },
+ { 75, 3, 2, 3, 63, 600 },
+ { 76, 3, 2, 3, 63, 600 },
+ { 77, 3, 2, 3, 63, 600 },
+ { 78, 3, 2, 3, 63, 600 },
+ { 79, 3, 2, 3, 63, 600 },
+ { 80, 3, 2, 3, 63, 600 },
+ { 81, 3, 2, 3, 63, 600 },
+ { 82, 3, 2, 3, 63, 600 },
+ { 83, 4, 2, 3, 63, 600 },
+ { 84, 4, 2, 3, 63, 600 },
+ { 85, 4, 2, 3, 63, 600 },
+ { 86, 4, 2, 3, 63, 600 },
+ { 87, 4, 2, 3, 63, 600 },
+ { 88, 4, 2, 3, 63, 600 },
+ { 89, 4, 2, 3, 63, 600 },
+ { 90, 4, 2, 3, 63, 600 },
+ { 91, 4, 2, 3, 63, 600 },
+ { 92, 4, 2, 3, 63, 600 },
+ { 93, 4, 2, 3, 63, 600 },
+ { 94, 4, 2, 3, 63, 600 },
+ { 95, 4, 2, 3, 63, 600 },
+ { 96, 4, 2, 3, 63, 600 },
+ { 97, 4, 2, 3, 63, 600 },
+ { 98, 4, 2, 3, 63, 600 },
+ { 99, 4, 2, 3, 63, 600 },
+ { 100, 4, 2, 3, 63, 600 },
+ { 101, 4, 2, 3, 63, 600 },
+ { 102, 4, 2, 3, 63, 600 },
+ { 103, 5, 2, 3, 63, 600 },
+ { 104, 5, 2, 3, 63, 600 },
+ { 105, 5, 2, 3, 63, 600 },
+ { 106, 5, 2, 3, 63, 600 },
+ { 107, 3, 4, 3, 63, 600 },
+ { 108, 3, 4, 3, 63, 600 },
+ { 109, 3, 4, 3, 63, 600 },
+ { 110, 3, 4, 3, 63, 600 },
+ { 111, 3, 4, 3, 63, 600 },
+ { 112, 3, 4, 3, 63, 600 },
+ { 113, 3, 4, 3, 63, 600 },
+ { 114, 3, 4, 3, 63, 600 },
+ { 115, 3, 4, 3, 63, 600 },
+ { 116, 3, 4, 3, 63, 600 },
+ { 117, 3, 4, 3, 63, 600 },
+ { 118, 3, 4, 3, 63, 600 },
+ { 119, 3, 4, 3, 63, 600 },
+ { 120, 3, 4, 3, 63, 600 },
+ { 121, 3, 4, 3, 63, 600 },
+ { 122, 3, 4, 3, 63, 600 },
+ { 123, 3, 4, 3, 63, 600 },
+ { 124, 3, 4, 3, 63, 600 },
+ { 125, 3, 4, 3, 63, 600 },
+};
+
+/**
+ * xvcu_read - Read from the VCU register space
+ * @iomem: vcu reg space base address
+ * @offset: vcu reg offset from base
+ *
+ * Return: Returns 32bit value from VCU register specified
+ *
+ */
+static u32 xvcu_read(void __iomem *iomem, u32 offset)
+{
+ return ioread32(iomem + offset);
+}
+
+/**
+ * xvcu_write - Write to the VCU register space
+ * @iomem: vcu reg space base address
+ * @offset: vcu reg offset from base
+ * @value: Value to write
+ */
+static void xvcu_write(void __iomem *iomem, u32 offset, u32 value)
+{
+ iowrite32(value, iomem + offset);
+}
+
+/**
+ * xvcu_write_field_reg - Write to the vcu reg field
+ * @iomem: vcu reg space base address
+ * @offset: vcu reg offset from base
+ * @field: vcu reg field to write to
+ * @mask: vcu reg mask
+ * @shift: vcu reg number of bits to shift the bitfield
+ */
+static void xvcu_write_field_reg(void __iomem *iomem, int offset,
+ u32 field, u32 mask, int shift)
+{
+ u32 val = xvcu_read(iomem, offset);
+
+ val &= ~(mask << shift);
+ val |= (field & mask) << shift;
+
+ xvcu_write(iomem, offset, val);
+}
+
+/**
+ * xvcu_set_vcu_pll_info - Set the VCU PLL info
+ * @xvcu: Pointer to the xvcu_device structure
+ *
+ * Programming the VCU PLL based on the user configuration
+ * (ref clock freq, core clock freq, mcu clock freq).
+ * Core clock frequency has higher priority than mcu clock frequency
+ * Errors in following cases
+ * - When mcu or clock clock get from logicoreIP is 0
+ * - When VCU PLL DIV related bits value other than 1
+ * - When proper data not found for given data
+ * - When sis570_1 clocksource related operation failed
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int xvcu_set_vcu_pll_info(struct xvcu_device *xvcu)
+{
+ u32 refclk, coreclk, mcuclk, inte, deci;
+ u32 divisor_mcu, divisor_core, fvco;
+ u32 clkoutdiv, vcu_pll_ctrl, pll_clk;
+ u32 cfg_val, mod, ctrl;
+ int ret;
+ unsigned int i;
+ const struct xvcu_pll_cfg *found = NULL;
+
+ inte = xvcu_read(xvcu->logicore_reg_ba, VCU_PLL_CLK);
+ deci = xvcu_read(xvcu->logicore_reg_ba, VCU_PLL_CLK_DEC);
+ coreclk = xvcu_read(xvcu->logicore_reg_ba, VCU_CORE_CLK) * MHZ;
+ mcuclk = xvcu_read(xvcu->logicore_reg_ba, VCU_MCU_CLK) * MHZ;
+ if (!mcuclk || !coreclk) {
+ dev_err(xvcu->dev, "Invalid mcu and core clock data\n");
+ return -EINVAL;
+ }
+
+ refclk = (inte * MHZ) + (deci * (MHZ / FRAC));
+ dev_dbg(xvcu->dev, "Ref clock from logicoreIP is %uHz\n", refclk);
+ dev_dbg(xvcu->dev, "Core clock from logicoreIP is %uHz\n", coreclk);
+ dev_dbg(xvcu->dev, "Mcu clock from logicoreIP is %uHz\n", mcuclk);
+
+ clk_disable_unprepare(xvcu->pll_ref);
+ ret = clk_set_rate(xvcu->pll_ref, refclk);
+ if (ret)
+ dev_warn(xvcu->dev, "failed to set logicoreIP refclk rate\n");
+
+ ret = clk_prepare_enable(xvcu->pll_ref);
+ if (ret) {
+ dev_err(xvcu->dev, "failed to enable pll_ref clock source\n");
+ return ret;
+ }
+
+ refclk = clk_get_rate(xvcu->pll_ref);
+
+ /* The divide-by-2 should be always enabled (==1)
+ * to meet the timing in the design.
+ * Otherwise, it's an error
+ */
+ vcu_pll_ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_PLL_CTRL);
+ clkoutdiv = vcu_pll_ctrl >> VCU_PLL_CTRL_CLKOUTDIV_SHIFT;
+ clkoutdiv = clkoutdiv && VCU_PLL_CTRL_CLKOUTDIV_MASK;
+ if (clkoutdiv != 1) {
+ dev_err(xvcu->dev, "clkoutdiv value is invalid\n");
+ return -EINVAL;
+ }
+
+ for (i = ARRAY_SIZE(xvcu_pll_cfg) - 1; i > 0; i--) {
+ const struct xvcu_pll_cfg *cfg = &xvcu_pll_cfg[i];
+
+ fvco = cfg->fbdiv * refclk;
+ if (fvco >= FVCO_MIN && fvco <= FVCO_MAX) {
+ pll_clk = fvco / VCU_PLL_DIV2;
+ if (fvco % VCU_PLL_DIV2 != 0)
+ pll_clk++;
+ mod = pll_clk % coreclk;
+ if (mod < LIMIT) {
+ divisor_core = pll_clk / coreclk;
+ } else if (coreclk - mod < LIMIT) {
+ divisor_core = pll_clk / coreclk;
+ divisor_core++;
+ } else {
+ continue;
+ }
+ if (divisor_core >= DIVISOR_MIN &&
+ divisor_core <= DIVISOR_MAX) {
+ found = cfg;
+ divisor_mcu = pll_clk / mcuclk;
+ mod = pll_clk % mcuclk;
+ if (mcuclk - mod < LIMIT)
+ divisor_mcu++;
+ break;
+ }
+ }
+ }
+
+ if (!found) {
+ dev_err(xvcu->dev, "Invalid clock combination.\n");
+ return -EINVAL;
+ }
+
+ xvcu->coreclk = pll_clk / divisor_core;
+ mcuclk = pll_clk / divisor_mcu;
+ dev_dbg(xvcu->dev, "Actual Ref clock freq is %uHz\n", refclk);
+ dev_dbg(xvcu->dev, "Actual Core clock freq is %uHz\n", xvcu->coreclk);
+ dev_dbg(xvcu->dev, "Actual Mcu clock freq is %uHz\n", mcuclk);
+
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_FBDIV_MASK << VCU_PLL_CTRL_FBDIV_SHIFT);
+ vcu_pll_ctrl |= (found->fbdiv & VCU_PLL_CTRL_FBDIV_MASK) <<
+ VCU_PLL_CTRL_FBDIV_SHIFT;
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_POR_IN_MASK <<
+ VCU_PLL_CTRL_POR_IN_SHIFT);
+ vcu_pll_ctrl |= (VCU_PLL_CTRL_DEFAULT & VCU_PLL_CTRL_POR_IN_MASK) <<
+ VCU_PLL_CTRL_POR_IN_SHIFT;
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_PWR_POR_MASK <<
+ VCU_PLL_CTRL_PWR_POR_SHIFT);
+ vcu_pll_ctrl |= (VCU_PLL_CTRL_DEFAULT & VCU_PLL_CTRL_PWR_POR_MASK) <<
+ VCU_PLL_CTRL_PWR_POR_SHIFT;
+ xvcu_write(xvcu->vcu_slcr_ba, VCU_PLL_CTRL, vcu_pll_ctrl);
+
+ /* Set divisor for the core and mcu clock */
+ ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_ENC_CORE_CTRL);
+ ctrl &= ~(VCU_PLL_DIVISOR_MASK << VCU_PLL_DIVISOR_SHIFT);
+ ctrl |= (divisor_core & VCU_PLL_DIVISOR_MASK) <<
+ VCU_PLL_DIVISOR_SHIFT;
+ ctrl &= ~(VCU_SRCSEL_MASK << VCU_SRCSEL_SHIFT);
+ ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) << VCU_SRCSEL_SHIFT;
+ xvcu_write(xvcu->vcu_slcr_ba, VCU_ENC_CORE_CTRL, ctrl);
+
+ ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_DEC_CORE_CTRL);
+ ctrl &= ~(VCU_PLL_DIVISOR_MASK << VCU_PLL_DIVISOR_SHIFT);
+ ctrl |= (divisor_core & VCU_PLL_DIVISOR_MASK) <<
+ VCU_PLL_DIVISOR_SHIFT;
+ ctrl &= ~(VCU_SRCSEL_MASK << VCU_SRCSEL_SHIFT);
+ ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) << VCU_SRCSEL_SHIFT;
+ xvcu_write(xvcu->vcu_slcr_ba, VCU_DEC_CORE_CTRL, ctrl);
+
+ ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_ENC_MCU_CTRL);
+ ctrl &= ~(VCU_PLL_DIVISOR_MASK << VCU_PLL_DIVISOR_SHIFT);
+ ctrl |= (divisor_mcu & VCU_PLL_DIVISOR_MASK) << VCU_PLL_DIVISOR_SHIFT;
+ ctrl &= ~(VCU_SRCSEL_MASK << VCU_SRCSEL_SHIFT);
+ ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) << VCU_SRCSEL_SHIFT;
+ xvcu_write(xvcu->vcu_slcr_ba, VCU_ENC_MCU_CTRL, ctrl);
+
+ ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_DEC_MCU_CTRL);
+ ctrl &= ~(VCU_PLL_DIVISOR_MASK << VCU_PLL_DIVISOR_SHIFT);
+ ctrl |= (divisor_mcu & VCU_PLL_DIVISOR_MASK) << VCU_PLL_DIVISOR_SHIFT;
+ ctrl &= ~(VCU_SRCSEL_MASK << VCU_SRCSEL_SHIFT);
+ ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) << VCU_SRCSEL_SHIFT;
+ xvcu_write(xvcu->vcu_slcr_ba, VCU_DEC_MCU_CTRL, ctrl);
+
+ /* Set RES, CP, LFHF, LOCK_CNT and LOCK_DLY cfg values */
+ cfg_val = (found->res << VCU_PLL_CFG_RES_SHIFT) |
+ (found->cp << VCU_PLL_CFG_CP_SHIFT) |
+ (found->lfhf << VCU_PLL_CFG_LFHF_SHIFT) |
+ (found->lock_cnt << VCU_PLL_CFG_LOCK_CNT_SHIFT) |
+ (found->lock_dly << VCU_PLL_CFG_LOCK_DLY_SHIFT);
+ xvcu_write(xvcu->vcu_slcr_ba, VCU_PLL_CFG, cfg_val);
+
+ return 0;
+}
+
+/**
+ * xvcu_set_pll - PLL init sequence
+ * @xvcu: Pointer to the xvcu_device structure
+ *
+ * Call the api to set the PLL info and once that is done then
+ * init the PLL sequence to make the PLL stable.
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int xvcu_set_pll(struct xvcu_device *xvcu)
+{
+ u32 lock_status;
+ unsigned long timeout;
+ int ret;
+
+ ret = xvcu_set_vcu_pll_info(xvcu);
+ if (ret) {
+ dev_err(xvcu->dev, "failed to set pll info\n");
+ return ret;
+ }
+
+ xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL,
+ 1, VCU_PLL_CTRL_BYPASS_MASK,
+ VCU_PLL_CTRL_BYPASS_SHIFT);
+ xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL,
+ 1, VCU_PLL_CTRL_RESET_MASK,
+ VCU_PLL_CTRL_RESET_SHIFT);
+ xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL,
+ 0, VCU_PLL_CTRL_RESET_MASK,
+ VCU_PLL_CTRL_RESET_SHIFT);
+ /* Defined the timeout for the max time to wait the
+ * PLL_STATUS to be locked.
+ */
+ timeout = jiffies + msecs_to_jiffies(2000);
+ do {
+ lock_status = xvcu_read(xvcu->vcu_slcr_ba, VCU_PLL_STATUS);
+ if (lock_status & VCU_PLL_STATUS_LOCK_STATUS_MASK) {
+ xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL,
+ 0, VCU_PLL_CTRL_BYPASS_MASK,
+ VCU_PLL_CTRL_BYPASS_SHIFT);
+ return 0;
+ }
+ } while (!time_after(jiffies, timeout));
+
+ /* PLL is not locked even after the timeout of the 2sec */
+ dev_err(xvcu->dev, "PLL is not locked\n");
+ return -ETIMEDOUT;
+}
+
+/**
+ * xvcu_probe - Probe existence of the logicoreIP
+ * and initialize PLL
+ *
+ * @pdev: Pointer to the platform_device structure
+ *
+ * Return: Returns 0 on success
+ * Negative error code otherwise
+ */
+static int xvcu_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct xvcu_device *xvcu;
+ int ret;
+
+ xvcu = devm_kzalloc(&pdev->dev, sizeof(*xvcu), GFP_KERNEL);
+ if (!xvcu)
+ return -ENOMEM;
+
+ xvcu->dev = &pdev->dev;
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vcu_slcr");
+ if (!res) {
+ dev_err(&pdev->dev, "get vcu_slcr memory resource failed.\n");
+ return -ENODEV;
+ }
+
+ xvcu->vcu_slcr_ba = devm_ioremap_nocache(&pdev->dev,
+ res->start, resource_size(res));
+ if (!xvcu->vcu_slcr_ba) {
+ dev_err(&pdev->dev, "vcu_slcr register mapping failed.\n");
+ return -ENOMEM;
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "logicore");
+ if (!res) {
+ dev_err(&pdev->dev, "get logicore memory resource failed.\n");
+ return -ENODEV;
+ }
+
+ xvcu->logicore_reg_ba = devm_ioremap_nocache(&pdev->dev,
+ res->start, resource_size(res));
+ if (!xvcu->logicore_reg_ba) {
+ dev_err(&pdev->dev, "logicore register mapping failed.\n");
+ return -ENOMEM;
+ }
+
+ xvcu->aclk = devm_clk_get(&pdev->dev, "aclk");
+ if (IS_ERR(xvcu->aclk)) {
+ dev_err(&pdev->dev, "Could not get aclk clock\n");
+ return PTR_ERR(xvcu->aclk);
+ }
+
+ xvcu->pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
+ if (IS_ERR(xvcu->pll_ref)) {
+ dev_err(&pdev->dev, "Could not get pll_ref clock\n");
+ return PTR_ERR(xvcu->pll_ref);
+ }
+
+ ret = clk_prepare_enable(xvcu->aclk);
+ if (ret) {
+ dev_err(&pdev->dev, "aclk clock enable failed\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(xvcu->pll_ref);
+ if (ret) {
+ dev_err(&pdev->dev, "pll_ref clock enable failed\n");
+ goto error_aclk;
+ }
+
+ /* Do the Gasket isolation and put the VCU out of reset
+ * Bit 0 : Gasket isolation
+ * Bit 1 : put VCU out of reset
+ */
+ xvcu_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, VCU_GASKET_VALUE);
+
+ /* Do the PLL Settings based on the ref clk,core and mcu clk freq */
+ ret = xvcu_set_pll(xvcu);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to set the pll\n");
+ goto error_pll_ref;
+ }
+
+ dev_set_drvdata(&pdev->dev, xvcu);
+
+ dev_info(&pdev->dev, "%s: Probed successfully\n", __func__);
+
+ return 0;
+
+error_pll_ref:
+ clk_disable_unprepare(xvcu->pll_ref);
+error_aclk:
+ clk_disable_unprepare(xvcu->aclk);
+ return ret;
+}
+
+/**
+ * xvcu_remove - Insert gasket isolation
+ * and disable the clock
+ * @pdev: Pointer to the platform_device structure
+ *
+ * Return: Returns 0 on success
+ * Negative error code otherwise
+ */
+static int xvcu_remove(struct platform_device *pdev)
+{
+ struct xvcu_device *xvcu;
+
+ xvcu = platform_get_drvdata(pdev);
+ if (!xvcu)
+ return -ENODEV;
+
+ /* Add the the Gasket isolation and put the VCU in reset.
+ */
+ xvcu_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, 0);
+
+ clk_disable_unprepare(xvcu->pll_ref);
+ clk_disable_unprepare(xvcu->aclk);
+
+ return 0;
+}
+
+static const struct of_device_id xvcu_of_id_table[] = {
+ { .compatible = "xlnx,vcu" },
+ { .compatible = "xlnx,vcu-logicoreip-1.0" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, xvcu_of_id_table);
+
+static struct platform_driver xvcu_driver = {
+ .driver = {
+ .name = "xilinx-vcu",
+ .of_match_table = xvcu_of_id_table,
+ },
+ .probe = xvcu_probe,
+ .remove = xvcu_remove,
+};
+
+module_platform_driver(xvcu_driver);
+
+MODULE_AUTHOR("Dhaval Shah <dshah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>");
+MODULE_DESCRIPTION("Xilinx VCU init Driver");
+MODULE_LICENSE("GPL v2");
--
2.7.4
--
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^ permalink raw reply related
* [PATCH v3 1/2] dt-bindings: misc: Add DT bindings to xlnx_vcu driver
From: Dhaval Shah @ 2017-12-14 5:55 UTC (permalink / raw)
To: arnd, gregkh, pombredanne, robh+dt, mark.rutland
Cc: devicetree, linux-kernel, michal.simek, hyunk, Dhaval Shah
In-Reply-To: <1513230920-9005-1-git-send-email-dshah@xilinx.com>
Add Device Tree binding document for logicoreIP. This logicoreIP
provides the isolation between the processing system and
programmable logic. Also provides the clock related information.
Signed-off-by: Dhaval Shah <dshah@xilinx.com>
---
Chnages since v3:
* Use "dt-bindings: misc: ..." for the subject.
Changes since v2:
* Describe the h/w
* compatible string is updated to make it more specific
based on the logicoreIP version.
* Removed that encoder and decoder child nodes and relatd properties as that
will be a separate driver and dts nodes. other team is working on that.
* Updated to use as a single driver.
.../devicetree/bindings/misc/xlnx,vcu.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/xlnx,vcu.txt
diff --git a/Documentation/devicetree/bindings/misc/xlnx,vcu.txt b/Documentation/devicetree/bindings/misc/xlnx,vcu.txt
new file mode 100644
index 0000000..6786d67
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/xlnx,vcu.txt
@@ -0,0 +1,31 @@
+LogicoreIP designed compatible with Xilinx ZYNQ family.
+-------------------------------------------------------
+
+General concept
+---------------
+
+LogicoreIP design to provide the isolation between processing system
+and programmable logic. Also provides the list of register set to configure
+the frequency.
+
+Required properties:
+- compatible: shall be one of:
+ "xlnx,vcu"
+ "xlnx,vcu-logicoreip-1.0"
+- reg, reg-names: There are two sets of registers need to provide.
+ 1. vcu slcr
+ 2. Logicore
+ reg-names should contain name for the each register sequence.
+- clocks: phandle for aclk and pll_ref clocksource
+- clock-names: The identification string, "aclk", is always required for
+ the axi clock. "pll_ref" is required for pll.
+Example:
+
+ xlnx_vcu: vcu@a0040000 {
+ compatible = "xlnx,vcu-logicoreip-1.0";
+ reg = <0x0 0xa0040000 0x0 0x1000>,
+ <0x0 0xa0041000 0x0 0x1000>;
+ reg-names = "vcu_slcr", "logicore";
+ clocks = <&si570_1>, <&clkc 71>;
+ clock-names = "pll_ref", "aclk";
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH v3 0/2] Documentation and driver of logicoreIP
From: Dhaval Shah @ 2017-12-14 5:55 UTC (permalink / raw)
To: arnd, gregkh, pombredanne, robh+dt, mark.rutland
Cc: devicetree, linux-kernel, michal.simek, hyunk, Dhaval Shah
In-Reply-To: <200703.nxabyfcjbswwbp4v@rob-hp-laptop>
1st patch provide Device Tree binding document for logicoreIP
2nd patch provide the xlnx_vcu logicoreIP driver, Kconfig changes
and Makefile changes for the driver.
Dhaval Shah (2):
Documentation: devicetree: Add DT bindings to xlnx_vcu driver
misc: Add Xilinx ZYNQMP VCU logicoreIP init driver
.../devicetree/bindings/misc/xlnx,vcu.txt | 31 +
drivers/misc/Kconfig | 15 +
drivers/misc/Makefile | 1 +
drivers/misc/xlnx_vcu.c | 629 +++++++++++++++++++++
4 files changed, 676 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/xlnx,vcu.txt
create mode 100644 drivers/misc/xlnx_vcu.c
--
2.7.4
^ permalink raw reply
* Re: [PATCH v10 08/13] regmap: add SLIMbus support
From: Vinod Koul @ 2017-12-14 5:17 UTC (permalink / raw)
To: Mark Brown, Takashi Iwai
Cc: Mark Rutland, devicetree, alsa-devel, Jonathan Corbet,
pombredanne, Greg Kroah-Hartman, linux-doc, j.neuschaefer,
linux-kernel, Rob Herring, srinivas.kandagatla, linux-arm-msm,
sdharia
In-Reply-To: <20171213160611.GO6416@sirena.org.uk>
On Wed, Dec 13, 2017 at 04:06:11PM +0000, Mark Brown wrote:
> > On Mon, Dec 11, 2017 at 11:43:02PM +0000, srinivas.kandagatla@linaro.org wrote:
>
> > Mark, can I get an Ack for this patch so I can take it through my tree
> > with the other patches in this series?
>
> I'm actually not seeing a direct dependency here (there's a depends in
> place stopping the regmap code building if the Slimbus core isn't
> enabled) so if you want you can go ahead and apply the main stuff and I
> can apply the regmap change separately, it'll avoid Makefile/Kconfig
> conflicts anyway.
+ Takashi
FWIW, since this is another MIPI Audio specfic bus, would it make sense for
this series to go thru sound/ tree? I have discussed with Takashi and Greg
for soundwire and we are taking sound path.
Would that be okay here too? Either ways I dont mind :)
Thanks
--
~Vinod
^ permalink raw reply
* Re: [PATCH 4/4] PM / OPP: Add ti-opp-supply driver
From: Viresh Kumar @ 2017-12-14 4:34 UTC (permalink / raw)
To: Dave Gerlach
Cc: Rob Herring, Rafael J . Wysocki, linux-arm-kernel, linux-omap,
linux-pm, devicetree, Tony Lindgren, Nishanth Menon
In-Reply-To: <20171213203358.20839-5-d-gerlach@ti.com>
On 13-12-17, 14:33, Dave Gerlach wrote:
> Introduce a ti-opp-supply driver that will use new multiple regulator
> support that is part of the OPP core This is needed on TI platforms like
> DRA7/AM57 in order to control both CPU regulator and Adaptive Body Bias
> (ABB) regulator. These regulators must be scaled in sequence during an
> OPP transition depending on whether or not the frequency is being scaled
> up or down.
>
> This driver also implements AVS Class0 for these parts by looking up the
> required values from registers in the SoC and programming adjusted
> optimal voltage values for each OPP.
>
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
> ---
> drivers/opp/Makefile | 1 +
> drivers/opp/ti-opp-supply.c | 428 ++++++++++++++++++++++++++++++++++++++++++++
Why is this added as a separate driver and not part of the same ti-cpufreq.c
file?
> 2 files changed, 429 insertions(+)
> create mode 100644 drivers/opp/ti-opp-supply.c
>
> diff --git a/drivers/opp/Makefile b/drivers/opp/Makefile
> index e70ceb406fe9..6ce6aefacc81 100644
> --- a/drivers/opp/Makefile
> +++ b/drivers/opp/Makefile
> @@ -2,3 +2,4 @@ ccflags-$(CONFIG_DEBUG_DRIVER) := -DDEBUG
> obj-y += core.o cpu.o
> obj-$(CONFIG_OF) += of.o
> obj-$(CONFIG_DEBUG_FS) += debugfs.o
> +obj-$(CONFIG_ARM_TI_CPUFREQ) += ti-opp-supply.o
> diff --git a/drivers/opp/ti-opp-supply.c b/drivers/opp/ti-opp-supply.c
> new file mode 100644
> index 000000000000..73d795c90b79
> --- /dev/null
> +++ b/drivers/opp/ti-opp-supply.c
> @@ -0,0 +1,428 @@
> +/*
> + * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
> + * Nishanth Menon <nm@ti.com>
> + * Dave Gerlach <d-gerlach@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
Please use the new SPDX format for licenses.
> + * TI OPP supply driver that provides override into the regulator control
> + * for generic opp core to handle devices with ABB regulator and/or
> + * SmartReflex Class0.
> + */
> +#include <linux/clk.h>
> +#include <linux/cpufreq.h>
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/notifier.h>
> +#include <linux/of_device.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/slab.h>
> +
> +/**
> + * struct ti_opp_supply_optimum_voltage_table - optimized voltage table
> + * @reference_uv: reference voltage (usually Nominal voltage)
> + * @optimized_uv: Optimized voltage from efuse
> + */
> +struct ti_opp_supply_optimum_voltage_table {
> + unsigned int reference_uv;
> + unsigned int optimized_uv;
> +};
> +
> +/**
> + * struct ti_opp_supply_data - OMAP specific opp supply data
> + * @vdd_table: Optimized voltage mapping table
> + * @num_vdd_table: number of entries in vdd_table
> + * @vdd_absolute_max_voltage_uv: absolute maximum voltage in UV for the supply
> + */
> +struct ti_opp_supply_data {
> + struct ti_opp_supply_optimum_voltage_table *vdd_table;
> + u32 num_vdd_table;
> + u32 vdd_absolute_max_voltage_uv;
> +};
> +
> +static struct ti_opp_supply_data opp_data;
> +
> +/**
> + * struct ti_opp_supply_of_data - device tree match data
> + * @flags: specific type of opp supply
> + * @efuse_voltage_mask: mask required for efuse register representing voltage
> + * @efuse_voltage_uv: Are the efuse entries in micro-volts? if not, assume
> + * milli-volts.
> + */
> +struct ti_opp_supply_of_data {
> +#define OPPDM_EFUSE_CLASS0_OPTIMIZED_VOLTAGE BIT(1)
> +#define OPPDM_HAS_NO_ABB BIT(2)
> + const u8 flags;
> + const u32 efuse_voltage_mask;
> + const bool efuse_voltage_uv;
> +};
> +
> +/**
> + * _store_optimized_voltages() - store optimized voltages
> + * @dev: ti opp supply device for which we need to store info
> + * @data: data specific to the device
> + *
> + * Picks up efuse based optimized voltages for VDD unique per device and
> + * stores it in internal data structure for use during transition requests.
> + *
> + * Return: If successful, 0, else appropriate error value.
> + */
> +static int _store_optimized_voltages(struct device *dev,
> + struct ti_opp_supply_data *data)
> +{
> + void __iomem *base;
> + struct property *prop;
> + struct resource *res;
> + const __be32 *val;
> + int proplen, i;
> + int ret = 0;
> + struct ti_opp_supply_optimum_voltage_table *table;
> + const struct ti_opp_supply_of_data *of_data = dev_get_drvdata(dev);
> +
> + /* pick up Efuse based voltages */
> + res = platform_get_resource(to_platform_device(dev), IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "Unable to get IO resource\n");
> + ret = -ENODEV;
> + goto out_map;
> + }
> +
> + base = ioremap_nocache(res->start, resource_size(res));
> + if (!base) {
> + dev_err(dev, "Unable to map Efuse registers\n");
> + ret = -ENOMEM;
> + goto out_map;
> + }
> +
> + /* Fetch efuse-settings. */
> + prop = of_find_property(dev->of_node, "ti,efuse-settings", NULL);
> + if (!prop) {
> + dev_err(dev, "No 'ti,efuse-settings' property found\n");
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + proplen = prop->length / sizeof(int);
> + data->num_vdd_table = proplen / 2;
> + /* Verify for corrupted OPP entries in dt */
> + if (data->num_vdd_table * 2 * sizeof(int) != prop->length) {
> + dev_err(dev, "Invalid 'ti,efuse-settings'\n");
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + ret = of_property_read_u32(dev->of_node, "ti,absolute-max-voltage-uv",
> + &data->vdd_absolute_max_voltage_uv);
> + if (ret) {
> + dev_err(dev, "ti,absolute-max-voltage-uv is missing\n");
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + table = kzalloc(sizeof(*data->vdd_table) *
> + data->num_vdd_table, GFP_KERNEL);
> + if (!table) {
> + ret = -ENOMEM;
> + goto out;
> + }
> + data->vdd_table = table;
> +
> + val = prop->value;
> + for (i = 0; i < data->num_vdd_table; i++, table++) {
> + u32 efuse_offset;
> + u32 tmp;
> +
> + table->reference_uv = be32_to_cpup(val++);
> + efuse_offset = be32_to_cpup(val++);
> +
> + tmp = readl(base + efuse_offset);
> + tmp &= of_data->efuse_voltage_mask;
> + tmp >>= __ffs(of_data->efuse_voltage_mask);
> +
> + table->optimized_uv = of_data->efuse_voltage_uv ? tmp :
> + tmp * 1000;
> +
> + dev_dbg(dev, "[%d] efuse=0x%08x volt_table=%d vset=%d\n",
> + i, efuse_offset, table->reference_uv,
> + table->optimized_uv);
> +
> + /*
> + * Some older samples might not have optimized efuse
> + * Use reference voltage for those - just add debug message
> + * for them.
> + */
> + if (!table->optimized_uv) {
> + dev_dbg(dev, "[%d] efuse=0x%08x volt_table=%d:vset0\n",
> + i, efuse_offset, table->reference_uv);
> + table->optimized_uv = table->reference_uv;
> + }
> + }
> +out:
> + iounmap(base);
> +out_map:
> + return ret;
> +}
> +
> +/**
> + * _free_optimized_voltages() - free resources for optvoltages
> + * @dev: device for which we need to free info
> + * @data: data specific to the device
> + */
> +static void _free_optimized_voltages(struct device *dev,
> + struct ti_opp_supply_data *data)
> +{
> + kfree(data->vdd_table);
> + data->vdd_table = NULL;
> + data->num_vdd_table = 0;
> +}
> +
> +/**
> + * _get_optimal_vdd_voltage() - Finds optimal voltage for the supply
> + * @dev: device for which we need to find info
> + * @data: data specific to the device
> + * @reference_uv: reference voltage (OPP voltage) for which we need value
> + *
> + * Return: if a match is found, return optimized voltage, else return
> + * reference_uv, also return reference_uv if no optimization is needed.
> + */
> +static int _get_optimal_vdd_voltage(struct device *dev,
> + struct ti_opp_supply_data *data,
> + int reference_uv)
> +{
> + int i;
> + struct ti_opp_supply_optimum_voltage_table *table;
> +
> + if (!data->num_vdd_table)
> + return reference_uv;
> +
> + table = data->vdd_table;
> + if (!table)
> + return -EINVAL;
> +
> + /* Find a exact match - this list is usually very small */
> + for (i = 0; i < data->num_vdd_table; i++, table++)
> + if (table->reference_uv == reference_uv)
> + return table->optimized_uv;
> +
> + /* IF things are screwed up, we'd make a mess on console.. ratelimit */
> + dev_err_ratelimited(dev, "%s: Failed optimized voltage match for %d\n",
> + __func__, reference_uv);
> + return reference_uv;
> +}
> +
> +static int _opp_set_voltage(struct device *dev,
> + struct dev_pm_opp_supply *supply,
> + int new_target_uv, struct regulator *reg,
> + char *reg_name)
> +{
> + int ret;
> + unsigned long vdd_uv, uv_max;
> +
> + if (new_target_uv)
> + vdd_uv = new_target_uv;
> + else
> + vdd_uv = supply->u_volt;
> +
> + /*
> + * If we do have an absolute max voltage specified, then we should
> + * use that voltage instead to allow for cases where the voltage rails
> + * are ganged (example if we set the max for an opp as 1.12v, and
> + * the absolute max is 1.5v, for another rail to get 1.25v, it cannot
> + * be achieved if the regulator is constrainted to max of 1.12v, even
> + * if it can function at 1.25v
> + */
> + if (opp_data.vdd_absolute_max_voltage_uv)
> + uv_max = opp_data.vdd_absolute_max_voltage_uv;
> + else
> + uv_max = supply->u_volt_max;
> +
> + if (vdd_uv > uv_max ||
> + vdd_uv < supply->u_volt_min ||
> + supply->u_volt_min > uv_max) {
> + dev_warn(dev,
> + "Invalid range voltages [Min:%lu target:%lu Max:%lu]\n",
> + supply->u_volt_min, vdd_uv, uv_max);
> + return -EINVAL;
> + }
> +
> + dev_dbg(dev, "%s scaling to %luuV[min %luuV max %luuV]\n", reg_name,
> + vdd_uv, supply->u_volt_min,
> + uv_max);
> +
> + ret = regulator_set_voltage_triplet(reg,
> + supply->u_volt_min,
> + vdd_uv,
> + uv_max);
> + if (ret) {
> + dev_err(dev, "%s failed for %luuV[min %luuV max %luuV]\n",
> + reg_name, vdd_uv, supply->u_volt_min,
> + uv_max);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * ti_opp_supply_set_opp() - do the opp supply transition
> + * @data: information on regulators and new and old opps provided by
> + * opp core to use in transition
> + *
> + * Return: If successful, 0, else appropriate error value.
> + */
> +int ti_opp_supply_set_opp(struct dev_pm_set_opp_data *data)
> +{
> + struct dev_pm_opp_supply *old_supply_vdd = &data->old_opp.supplies[0];
> + struct dev_pm_opp_supply *old_supply_vbb = &data->old_opp.supplies[1];
> + struct dev_pm_opp_supply *new_supply_vdd = &data->new_opp.supplies[0];
> + struct dev_pm_opp_supply *new_supply_vbb = &data->new_opp.supplies[1];
> + struct device *dev = data->dev;
> + unsigned long old_freq = data->old_opp.rate, freq = data->new_opp.rate;
> + struct clk *clk = data->clk;
> + struct regulator *vdd_reg = data->regulators[0];
> + struct regulator *vbb_reg = data->regulators[1];
> + int vdd_uv;
> + int ret;
> +
> + vdd_uv = _get_optimal_vdd_voltage(dev, &opp_data,
> + new_supply_vbb->u_volt);
> +
> + /* Scaling up? Scale voltage before frequency */
> + if (freq > old_freq) {
> + ret = _opp_set_voltage(dev, new_supply_vdd, vdd_uv, vdd_reg,
> + "vdd");
> + if (ret)
> + goto restore_voltage;
> +
> + ret = _opp_set_voltage(dev, new_supply_vbb, 0, vbb_reg, "vbb");
> + if (ret)
> + goto restore_voltage;
> + }
> +
> + /* Change frequency */
> + dev_dbg(dev, "%s: switching OPP: %lu Hz --> %lu Hz\n",
> + __func__, old_freq, freq);
> +
> + ret = clk_set_rate(clk, freq);
> + if (ret) {
> + dev_err(dev, "%s: failed to set clock rate: %d\n", __func__,
> + ret);
> + goto restore_voltage;
> + }
> +
> + /* Scaling down? Scale voltage after frequency */
> + if (freq < old_freq) {
> + ret = _opp_set_voltage(dev, new_supply_vbb, 0, vbb_reg, "vbb");
> + if (ret)
> + goto restore_freq;
> +
> + ret = _opp_set_voltage(dev, new_supply_vdd, vdd_uv, vdd_reg,
> + "vdd");
> + if (ret)
> + goto restore_freq;
> + }
> +
> + return 0;
> +
> +restore_freq:
> + ret = clk_set_rate(clk, old_freq);
> + if (ret)
> + dev_err(dev, "%s: failed to restore old-freq (%lu Hz)\n",
> + __func__, old_freq);
> +restore_voltage:
> + /* This shouldn't harm even if the voltages weren't updated earlier */
> + if (old_supply_vdd->u_volt) {
> + ret = _opp_set_voltage(dev, old_supply_vbb, 0, vbb_reg, "vbb");
> + if (ret)
> + return ret;
> +
> + ret = _opp_set_voltage(dev, old_supply_vdd, 0, vdd_reg,
> + "vdd");
> + if (ret)
> + return ret;
> + }
> +
> + return ret;
> +}
> +
> +static const struct ti_opp_supply_of_data omap_generic_of_data = {
> +};
> +
> +static const struct ti_opp_supply_of_data omap_omap5_of_data = {
> + .flags = OPPDM_EFUSE_CLASS0_OPTIMIZED_VOLTAGE,
> + .efuse_voltage_mask = 0xFFF,
> + .efuse_voltage_uv = false,
> +};
> +
> +static const struct ti_opp_supply_of_data omap_omap5core_of_data = {
> + .flags = OPPDM_EFUSE_CLASS0_OPTIMIZED_VOLTAGE | OPPDM_HAS_NO_ABB,
> + .efuse_voltage_mask = 0xFFF,
> + .efuse_voltage_uv = false,
> +};
> +
> +static const struct of_device_id ti_opp_supply_of_match[] = {
> + {.compatible = "ti,omap-opp-supply", .data = &omap_generic_of_data},
> + {.compatible = "ti,omap5-opp-supply", .data = &omap_omap5_of_data},
> + {.compatible = "ti,omap5-core-opp-supply",
> + .data = &omap_omap5core_of_data},
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, ti_opp_supply_of_match);
> +
> +static int ti_opp_supply_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device *cpu_dev = get_cpu_device(0);
> + const struct of_device_id *match;
> + const struct ti_opp_supply_of_data *of_data;
> + int ret = 0;
> +
> + match = of_match_device(ti_opp_supply_of_match, dev);
> + if (!match) {
> + /* We do not expect this to happen */
> + dev_err(dev, "%s: Unable to match device\n", __func__);
> + return -ENODEV;
> + }
> + if (!match->data) {
> + /* Again, unlikely.. but mistakes do happen */
> + dev_err(dev, "%s: Bad data in match\n", __func__);
> + return -EINVAL;
> + }
> + of_data = match->data;
> +
> + dev_set_drvdata(dev, (void *)of_data);
> +
> + /* If we need optimized voltage */
> + if (of_data->flags & OPPDM_EFUSE_CLASS0_OPTIMIZED_VOLTAGE) {
> + ret = _store_optimized_voltages(dev, &opp_data);
> + if (ret)
> + return ret;
> + }
> +
> + ret = PTR_ERR_OR_ZERO(dev_pm_opp_register_set_opp_helper(cpu_dev,
> + ti_opp_supply_set_opp));
> + if (ret)
> + _free_optimized_voltages(dev, &opp_data);
> +
> + return ret;
> +}
> +
> +static struct platform_driver ti_opp_supply_driver = {
> + .probe = ti_opp_supply_probe,
> + .driver = {
> + .name = "ti_opp_supply",
> + .owner = THIS_MODULE,
> + .of_match_table = of_match_ptr(ti_opp_supply_of_match),
> + },
> +};
> +module_platform_driver(ti_opp_supply_driver);
> +
> +MODULE_DESCRIPTION("Texas Instruments OMAP OPP Supply driver");
> +MODULE_AUTHOR("Texas Instruments Inc.");
> +MODULE_LICENSE("GPL v2");
Looks fine otherwise.
--
viresh
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