* Re: [PATCH v3 3/8] PCI: brcmstb: Add Broadcom STB PCIe host controller driver
From: Jim Quinlan @ 2017-12-15 19:53 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-kernel, Bjorn Helgaas, Catalin Marinas, Will Deacon,
Rob Herring, Brian Norris, Russell King, Robin Murphy,
Christoph Hellwig, Florian Fainelli, Jonas Gorski, Mark Rutland,
devicetree, Linux-MIPS, linux-pci, Kevin Cernekee, Ralf Baechle,
bcm-kernel-feedback-list, Gregory Fong, linux-arm-kernel
In-Reply-To: <20171214225133.GM30595@bhelgaas-glaptop.roam.corp.google.com>
On Thu, Dec 14, 2017 at 5:51 PM, Bjorn Helgaas <helgaas@kernel.org> wrote:
> On Wed, Dec 13, 2017 at 06:53:53PM -0500, Jim Quinlan wrote:
>> On Tue, Dec 12, 2017 at 5:16 PM, Bjorn Helgaas <helgaas@kernel.org> wrote:
>> > On Tue, Nov 14, 2017 at 05:12:07PM -0500, Jim Quinlan wrote:
>> >> This commit adds the basic Broadcom STB PCIe controller. Missing is
>> >> the ability to process MSI and also handle dma-ranges for inbound
>> >> memory accesses. These two functionalities are added in subsequent
>> >> commits.
>> >>
>> >> The PCIe block contains an MDIO interface. This is a local interface
>> >> only accessible by the PCIe controller. It cannot be used or shared
>> >> by any other HW. As such, the small amount of code for this
>> >> controller is included in this driver as there is little upside to put
>> >> it elsewhere.
>> ...
>
>> >> +static bool brcm_pcie_valid_device(struct brcm_pcie *pcie, struct pci_bus *bus,
>> >> + int dev)
>> >> +{
>> >> + if (pci_is_root_bus(bus)) {
>> >> + if (dev > 0)
>> >> + return false;
>> >> + } else {
>> >> + /* If there is no link, then there is no device */
>> >> + if (!brcm_pcie_link_up(pcie))
>> >> + return false;
>> >
>> > This is racy, since the link can go down after you check but before
>> > you do the config access. I assume your hardware can deal with a
>> > config access that targets a link that is down?
>>
>> Yes, that can happen but there is really nothing that can be done if
>> the link goes down in that vulnerability window. What do you suggest
>> doing?
>
> Most hardware drops writes and returns ~0 on reads if the link is
> down. I assume your hardware does something similar, and that should
> be enough. You shouldn't have to check whether the link is up.
Unfortunately our HW is quite unforgiving and effects a synchronous or
asynchronous abort when doing a config access when the link or power
has gone down on the EP. I will open a discussion with the PCIe HW
folks regarding why our controller does not behave like "most
hardware". Thanks, Jim
>
> The hardware might report errors, e.g., via AER, if the link is down.
> And we might not not handle those nicely. If we have issues there, we
> should find out and fix them.
>
> I see that dwc, altera, rockchip, and xilinx all do check for link up
> there, too. I can't remember if they had a legitimate reason, or if I
> just missed it.
>
>> >> +static void brcm_pcie_remove_controller(struct brcm_pcie *pcie)
>> >> +{
>> >> + struct list_head *pos, *q;
>> >> + struct brcm_pcie *tmp;
>> >> +
>> >> + mutex_lock(&brcm_pcie_lock);
>> >> + list_for_each_safe(pos, q, &brcm_pcie) {
>> >> + tmp = list_entry(pos, struct brcm_pcie, list);
>> >> + if (tmp == pcie) {
>> >> + list_del(pos);
>> >> + if (list_empty(&brcm_pcie))
>> >> + num_memc = 0;
>> >> + break;
>> >> + }
>> >> + }
>> >> + mutex_unlock(&brcm_pcie_lock);
>> >
>> > I'm missing something. I don't see that num_memc is ever set to
>> > anything *other* than zero.
>> The num_memc is set and used in the dma commit. I will remove its
>> declaration from this commit.
>
> Thanks, that will make the patches much easier to read.
>
>> >> + pcie->id = of_get_pci_domain_nr(dn);
>> >
>> > Why do you call of_get_pci_domain_nr() directly? No other driver
>> > does.
>>
>> We use the domain as the controller number (id). We use the id to
>> identify and fix a HW bug that only affects the 2nd controller; see
>> the clause
>> " } else if (of_machine_is_compatible("brcm,bcm7278a0")) {".
>
> pci_register_host_bridge() already sets bus->domain_nr for every host
> bridge. That path calls of_get_pci_domain_nr() eventually. But I
> guess that's too late for your use case, because you have this:
>
> brcm_pcie_probe
> brcm_pcie_setup
> brcm_pcie_bridge_sw_init_set
> if (of_machine_is_compatible("brcm,bcm7278a0")) {
> offset = pcie->id ? ... <--- use
> pci_scan_root_bus_bridge
> pci_register_host_bridge
> bus->domain_nr = pci_bus_find_domain_nr <--- available
>
> I guess you haven't added a binding for brcm,bcm7278a0 yet?
>
> I'm not really sure that using the linux,pci-domain DT property is the
> best way to distinguish the two controllers. Maybe Rob has an
> opinion?
>
>> >> + if (pcie->id < 0)
>> >> + return pcie->id;
>
> Bjorn
^ permalink raw reply
* Re: [PATCH v3] arm: imx: dts: Use lower case for bindings notation
From: Fabio Estevam @ 2017-12-15 19:53 UTC (permalink / raw)
To: Mathieu Malaterre
Cc: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Mark Rutland,
Russell King, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel
In-Reply-To: <20171215191930.11410-1-malat-8fiUuRrzOP0dnm+yROfE0A@public.gmane.org>
On Fri, Dec 15, 2017 at 5:19 PM, Mathieu Malaterre <malat-8fiUuRrzOP0dnm+yROfE0A@public.gmane.org> wrote:
> Improve the DTS files using lower case to fix the following dtc warnings:
>
> Warning (simple_bus_reg): Node /XXX@<UPPER> simple-bus unit address format error, expected "<lower>"
>
> Converted using the following command:
>
> find . -type f \( -iname *.dts -o -iname *.dtsi \) -exec sed -i -e "s/@\([0-9a-fA-FxX\.;:#]+\)\s*{/@\L\1 {/g" -e "s/@0x\(.*\) {/@\1 {/g" -e "s/@0+\(.*\) {/@\1 {/g" {} +^C
>
> For simplicity, two sed expressions were used to solve each warnings separately.
>
> To make the regex expression more robust a few other issues were resolved,
> namely setting unit-address to lower case, and adding a whitespace before the
> the opening curly brace:
>
> https://elinux.org/Device_Tree_Linux#Linux_conventions
>
> This is a follow up to commit 4c9847b7375a ("dt-bindings: Remove leading 0x from bindings notation")
>
> Reported-by: David Daney <ddaney-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
> Suggested-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Mathieu Malaterre <malat-8fiUuRrzOP0dnm+yROfE0A@public.gmane.org>
Reviewed-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH v3 1/8] SOC: brcmstb: add memory API
From: Jim Quinlan @ 2017-12-15 19:50 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Bjorn Helgaas, linux-kernel, Bjorn Helgaas, Catalin Marinas,
Will Deacon, Rob Herring, Brian Norris, Russell King,
Robin Murphy, Christoph Hellwig, Florian Fainelli, Jonas Gorski,
Mark Rutland, devicetree, Linux-MIPS, linux-pci, Kevin Cernekee,
Ralf Baechle, bcm-kernel-feedback-list,
Gregory Fong <gregory.0xf0>
In-Reply-To: <20171215171440.GB32131@red-moon>
On Fri, Dec 15, 2017 at 12:14 PM, Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
> On Tue, Dec 12, 2017 at 03:14:04PM -0600, Bjorn Helgaas wrote:
>> [+cc Lorenzo]
>>
>> On Tue, Dec 12, 2017 at 03:53:28PM -0500, Jim Quinlan wrote:
>> > On Tue, Dec 5, 2017 at 3:59 PM, Bjorn Helgaas <helgaas@kernel.org> wrote:
>> > > On Tue, Nov 14, 2017 at 05:12:05PM -0500, Jim Quinlan wrote:
>> > >> From: Florian Fainelli <f.fainelli@gmail.com>
>> > >>
>> > >> This commit adds a memory API suitable for ascertaining the sizes of
>> > >> each of the N memory controllers in a Broadcom STB chip. Its first
>> > >> user will be the Broadcom STB PCIe root complex driver, which needs
>> > >> to know these sizes to properly set up DMA mappings for inbound
>> > >> regions.
>> > >>
>> > >> We cannot use memblock here or anything like what Linux provides
>> > >> because it collapses adjacent regions within a larger block, and here
>> > >> we actually need per-memory controller addresses and sizes, which is
>> > >> why we resort to manual DT parsing.
>> > >>
>> > >> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
>> > >> ---
>> > >> drivers/soc/bcm/brcmstb/Makefile | 2 +-
>> > >> drivers/soc/bcm/brcmstb/memory.c | 172 +++++++++++++++++++++++++++++++++++++++
>> > >> include/soc/brcmstb/memory_api.h | 25 ++++++
>> > >> 3 files changed, 198 insertions(+), 1 deletion(-)
>> > >> create mode 100644 drivers/soc/bcm/brcmstb/memory.c
>> > >> create mode 100644 include/soc/brcmstb/memory_api.h
>> > >>
>> > >> diff --git a/drivers/soc/bcm/brcmstb/Makefile b/drivers/soc/bcm/brcmstb/Makefile
>> > >> index 9120b27..4cea7b6 100644
>> > >> --- a/drivers/soc/bcm/brcmstb/Makefile
>> > >> +++ b/drivers/soc/bcm/brcmstb/Makefile
>> > >> @@ -1 +1 @@
>> > >> -obj-y += common.o biuctrl.o
>> > >> +obj-y += common.o biuctrl.o memory.o
>> > >> diff --git a/drivers/soc/bcm/brcmstb/memory.c b/drivers/soc/bcm/brcmstb/memory.c
>> > >> new file mode 100644
>> > >> index 0000000..eb647ad9
>> > >> --- /dev/null
>> > >> +++ b/drivers/soc/bcm/brcmstb/memory.c
>> > >
>> > > I sort of assume based on [1] that every new file should have an SPDX
>> > > identifier ("The Linux kernel requires the precise SPDX identifier in
>> > > all source files") and that the actual text of the GPL can be omitted.
>> > >
>> > > Only a few files in drivers/pci currently have an SPDX identifier. I
>> > > don't know if that's oversight or work-in-progress or what.
>> > >
>> > > [1] https://lkml.kernel.org/r/20171204212120.484179273@linutronix.de
>> > >
>> >
>> > Bjorn, Did you get a chance to review the other commits of this
>> > submission (V3)? I would like any additional feedback before I send
>> > out a V4 with SPDX fixes. Thanks, JimQ
>>
>> Lorenzo is taking over drivers/pci/host/* and he'll no doubt have some
>> comments when he gets to this. I'll point out a few quick formatting
>> things in the meantime.
>
> I need some time to review the code but overall I am quite worried about
> patches 1 and 4 in particular, it is ok to have platform host bridge
> drivers but we can't rewrite a DMA layer for a specific host bridge, I
> really do not like that - it is just not manageable from a maintenance
> perspective for the mainline kernel.
>
> Lorenzo
Hi Lorenzo,
First I note that the file drivers/pci/host/vmd.c appears to do the
same thing -- rewrite a layer over the DMA ops. Secondly, there seems
to be no other way to accomplish what we need to do, especially that
will work with ARM, ARM64, and MIPs. Someone raised the same point
you did and suggested I involve ARM/ARM64 maintainers, so I expanded
my "--to" list to include Russell. I'm open to ideas. I've asked the
HW PCIe folks to redesign the controller to accommodate an
identity-map for inbound memory, but it will be a while if that
happens, if ever. --Jim
^ permalink raw reply
* Re: [PATCH v4 0/2] dt: add pinctrl driver for Meson-AXG SoC
From: Kevin Hilman @ 2017-12-15 19:48 UTC (permalink / raw)
To: Yixun Lan
Cc: linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring,
Mark Rutland, Linus Walleij, Neil Armstrong, Jerome Brunet,
Carlo Caione, Xingyu Chen, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171208015418.9632-1-yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>
Yixun Lan <yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org> writes:
> This is DT part patchset for adding pinctrl support for
> the Amlogic's Meson-AXG SoC.
>
> Changes since v3 at [3]
> -- rebase to khilman's v4.16/dt64 branch and re-send
> -- add Rob's Ack
>
> Changes since v2 at [2]:
> -- Resend this patch series due to fail to send patch [2/2]
>
> Changes since v1 at [1]:
> -- Separate DT part patches
> -- Add Neil Armstrong's Ack
>
> [3]
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005392.html
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005393.html
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005394.html
>
> [2]
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005390.html
>
> [1]
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005270.html
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005271.html
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005272.html
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005273.html
> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005274.html
>
> Xingyu Chen (2):
> documentation: Add compatibles for Amlogic Meson AXG pin controllers
> ARM64: dts: meson-axg: add pinctrl DT info for Meson-AXG SoC
Applied both to v4.14/dt64
Normally, the documentation patch should go with the driver, but since
Linus has already merged the driver, this time I'll take it with the DT
itself.
Kevin
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^ permalink raw reply
* Re: [PATCH v3 2/2] ARM64: dts: meson-axg: enable ethernet for A113D S400 board
From: Kevin Hilman @ 2017-12-15 19:31 UTC (permalink / raw)
To: Yixun Lan
Cc: devicetree, Neil Armstrong, Jerome Brunet, Giuseppe Cavallaro,
Alexandre Torgue, Carlo Caione, linux-amlogic, linux-arm-kernel,
linux-kernel, netdev
In-Reply-To: <20171215021014.231308-3-yixun.lan@amlogic.com>
Yixun Lan <yixun.lan@amlogic.com> writes:
> This is tested in the S400 dev board which use a RTL8211F PHY,
> and the pins connect to the 'eth_rgmii_y_pins' group.
>
> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
> arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> index 70eca1f8736a..b8c4f1913d28 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> @@ -20,3 +20,10 @@
> &uart_AO {
> status = "okay";
> };
> +
> +ðmac {
> + status = "okay";
> + phy-mode = "rgmii";
> + pinctrl-0 = <ð_rgmii_y_pins>;
> + pinctrl-names = "default";
> +};
Minor nit: we try to keep these sorted alphabetically. Can you move
this above the uart_A0 one?
Note: if PATCH 1/1 had applied cleanly, I would have fixed this up
myself and not required a respin.
Kevin
^ permalink raw reply
* Re: [PATCH v3 1/2] ARM64: dts: meson-axg: add ethernet mac controller
From: Kevin Hilman @ 2017-12-15 19:29 UTC (permalink / raw)
To: Yixun Lan
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Neil Armstrong, Jerome Brunet,
Giuseppe Cavallaro, Alexandre Torgue, Carlo Caione,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
netdev-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171215021014.231308-2-yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>
Yixun Lan <yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org> writes:
> Add DT info for the stmmac ethernet MAC which found in
> the Amlogic's Meson-AXG SoC, also describe the ethernet
> pinctrl & clock information here.
>
> Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> Signed-off-by: Yixun Lan <yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>
This patch does not apply, and dependencies are not described.
> ---
> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 54 ++++++++++++++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index d356ce74ad89..94c4972222b7 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -7,6 +7,7 @@
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/axg-clkc.h>
>
> / {
> compatible = "amlogic,meson-axg";
> @@ -148,6 +149,19 @@
> #address-cells = <0>;
> };
>
> + ethmac: ethernet@ff3f0000 {
> + compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
> + reg = <0x0 0xff3f0000 0x0 0x10000
> + 0x0 0xff634540 0x0 0x8>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "macirq";
> + clocks = <&clkc CLKID_ETH>,
> + <&clkc CLKID_FCLK_DIV2>,
> + <&clkc CLKID_MPLL2>;
> + clock-names = "stmmaceth", "clkin0", "clkin1";
> + status = "disabled";
> + };
> +
> hiubus: bus@ff63c000 {
> compatible = "simple-bus";
> reg = <0x0 0xff63c000 0x0 0x1c00>;
Based on the hiubus node, presumably this depends on the patch from the
clock series.
> @@ -194,6 +208,46 @@
> #gpio-cells = <2>;
> gpio-ranges = <&pinctrl_periphs 0 0 86>;
> };
I'm not sure where this part is coming from, but it causes the rest of
it to not apply.
Please be sure to describe all dependencies.
Kevin
> +
> + eth_rgmii_x_pins: eth-x-rgmii {
> + mux {
> + groups = "eth_mdio_x",
> + "eth_mdc_x",
> + "eth_rgmii_rx_clk_x",
> + "eth_rx_dv_x",
> + "eth_rxd0_x",
> + "eth_rxd1_x",
> + "eth_rxd2_rgmii",
> + "eth_rxd3_rgmii",
> + "eth_rgmii_tx_clk",
> + "eth_txen_x",
> + "eth_txd0_x",
> + "eth_txd1_x",
> + "eth_txd2_rgmii",
> + "eth_txd3_rgmii";
> + function = "eth";
> + };
> + };
> +
> + eth_rgmii_y_pins: eth-y-rgmii {
> + mux {
> + groups = "eth_mdio_y",
> + "eth_mdc_y",
> + "eth_rgmii_rx_clk_y",
> + "eth_rx_dv_y",
> + "eth_rxd0_y",
> + "eth_rxd1_y",
> + "eth_rxd2_rgmii",
> + "eth_rxd3_rgmii",
> + "eth_rgmii_tx_clk",
> + "eth_txen_y",
> + "eth_txd0_y",
> + "eth_txd1_y",
> + "eth_txd2_rgmii",
> + "eth_txd3_rgmii";
> + function = "eth";
> + };
> + };
> };
> };
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^ permalink raw reply
* Re: [PATCH 1/2] serial: stm32: add default console
From: Greg Kroah-Hartman @ 2017-12-15 19:25 UTC (permalink / raw)
To: Ludovic Barre
Cc: Jiri Slaby, Rob Herring, Maxime Coquelin, Alexandre Torgue,
linux-serial-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1512146211-29086-2-git-send-email-ludovic.Barre-qxv4g6HH51o@public.gmane.org>
On Fri, Dec 01, 2017 at 05:36:50PM +0100, Ludovic Barre wrote:
> From: Ludovic Barre <ludovic.barre-qxv4g6HH51o@public.gmane.org>
>
> This patch adds by default the console support
> on stm32.
Why? 'default y' should only mean "machine will not boot without this".
And I think your machine will boot without the console, right? :)
thanks,
greg k-h
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^ permalink raw reply
* Re: DT dtc warnings
From: Alexandre Belloni @ 2017-12-15 19:21 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Fabio Estevam, Rob Herring, Barry Song, Kukjin Kim, Maxime Ripard,
Chen-Yu Tsai, Nicolas Ferre, Patrice Chotard, Peter Rosin,
Santosh Shilimkar, arm-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Mathieu Malaterre
In-Reply-To: <CAJKOXPcf_zf3X8i9xVpK_BSvnR-78otwmaiOERDYTT2tC3VC2A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 15/12/2017 at 08:34:55 +0100, Krzysztof Kozlowski wrote:
> On Fri, Dec 15, 2017 at 8:29 AM, Alexandre Belloni
> <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> > On 15/12/2017 at 08:23:39 +0100, Krzysztof Kozlowski wrote:
> >> On Fri, Dec 15, 2017 at 12:02 AM, Fabio Estevam <festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> >> > On Thu, Dec 14, 2017 at 7:19 PM, Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> >> >
> >> >> Thanks for reply!
> >> >>
> >> >> Isn't this property of a SoC? The registers used by
> >> >> syscon-poweroff/reboot are part of SoC power management unit. It does
> >> >> not refer to any externals. Why then it should be put outside of soc?
> >> >
> >> > If these nodes have registers, then they should have a unit address
> >> > and reg property.
> >>
> >> That's the point - they do not have unit address.
> >>
> >
> > Should they be put under the syscon they are using?
>
> They are not using syscon but regmap provided by such external IP
> block (for example this:
> http://elixir.free-electrons.com/linux/v4.15-rc3/source/arch/arm/boot/dts/exynos3250.dtsi#L153).
> I guess you are proposing something like on imx7s:
> http://elixir.free-electrons.com/linux/v4.15-rc3/source/arch/arm/boot/dts/imx7s.dtsi#L539
>
Yeah, exactly.
Another example here:
http://elixir.free-electrons.com/linux/v4.15-rc3/source/arch/arm/boot/dts/gemini.dtsi#L32
It seems your poweroff and reboot bits are in registers that are in the
pmu_system_controller so it makes sense to put them under it. I would
even remove the regmap property and get the regmap from the parent
first. This can easily be done while keeping the ABI backward
compatibility.
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH 0/2] Use SPDX-License-Identifier for rockchip devicetree files
From: Brian Norris @ 2017-12-15 19:19 UTC (permalink / raw)
To: klaus.goger
Cc: Mark Rutland, Heiko Stübner, Huibin Hong, Catalin Marinas,
Linus Walleij, Will Deacon, Kever Yang, LKML, Finley Xiao,
Joseph Chen, Romain Perier, Randy Li, Matthias Kaehlcke,
Emil Renner Berthing, Sugar Zhang, Simon Xue, Heinrich Schuchardt,
Russell King, FUKAUMI Naoki, Jaehoon Chung, linux-rockchip,
Chen-Yu Tsai, Jacob Chen
In-Reply-To: <24788EB1-9868-41E9-B97C-7D85D8C3761D@theobroma-systems.com>
On Fri, Dec 15, 2017 at 05:27:52PM +0100, klaus.goger@theobroma-systems.com wrote:
> > On 15.12.2017, at 16:20, Heiko Stübner <heiko@sntech.de> wrote:
> > Am Freitag, 15. Dezember 2017, 15:42:48 CET schrieb Philippe Ombredanne:
> >> On Fri, Dec 15, 2017 at 3:28 PM, Heiko Stübner <heiko@sntech.de> wrote:
> >>> Am Freitag, 15. Dezember 2017, 14:45:34 CET schrieb Philippe Ombredanne:
> >>>> On Fri, Dec 15, 2017 at 12:44 PM, Klaus Goger
> >>>> <klaus.goger@theobroma-systems.com> wrote:
> >>>>> This patch series replaces all the license text in rockchip devicetree
> >>>>> files text with a proper SPDX-License-Identifier.
> >>>>> It follows the guidelines submitted[1] by Thomas Gleixner that are not
> >>>>> yet merged.
[...]
> I added the full list from the get_maintainers script. Some of the original authors
> got dropped as the current contribution level dropped below the scripts limit.
> I added the missing email addresses from the copyright headers to the CC list.
>
> Convenience links to the original patches for the added people:
>
> https://patchwork.kernel.org/patch/10114845/
> https://patchwork.kernel.org/patch/10114843/
I can't possibly miss my chance to spam dozens of people! I don't really
care at all about this change, so pick whichever of the following will
get these patches out of my mailbox quicker (choice is at the
maintainers' discretion):
Acked-by: Brian Norris <briannorris@chromium.org>
Nacked-by: Brian Norris <briannorris@chromium.org>
Viewed-with-strong-indifference-by: Brian Norris <briannorris@chromium.org>
for both patches. (I was CC'd only on 1, but I contributed to both
sets.)
Brian
^ permalink raw reply
* [PATCH v3] arm: imx: dts: Use lower case for bindings notation
From: Mathieu Malaterre @ 2017-12-15 19:19 UTC (permalink / raw)
To: Rob Herring
Cc: Fabio Estevam, Mathieu Malaterre, Shawn Guo, Sascha Hauer,
Fabio Estevam, Mark Rutland, Russell King,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171215124631.30132-1-malat-8fiUuRrzOP0dnm+yROfE0A@public.gmane.org>
Improve the DTS files using lower case to fix the following dtc warnings:
Warning (simple_bus_reg): Node /XXX@<UPPER> simple-bus unit address format error, expected "<lower>"
Converted using the following command:
find . -type f \( -iname *.dts -o -iname *.dtsi \) -exec sed -i -e "s/@\([0-9a-fA-FxX\.;:#]+\)\s*{/@\L\1 {/g" -e "s/@0x\(.*\) {/@\1 {/g" -e "s/@0+\(.*\) {/@\1 {/g" {} +^C
For simplicity, two sed expressions were used to solve each warnings separately.
To make the regex expression more robust a few other issues were resolved,
namely setting unit-address to lower case, and adding a whitespace before the
the opening curly brace:
https://elinux.org/Device_Tree_Linux#Linux_conventions
This is a follow up to commit 4c9847b7375a ("dt-bindings: Remove leading 0x from bindings notation")
Reported-by: David Daney <ddaney-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
Suggested-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Mathieu Malaterre <malat-8fiUuRrzOP0dnm+yROfE0A@public.gmane.org>
---
v2: Remove invalid patch for imx7s.dtsi, remove duplicate patch for imx7d.dtsi
v3: Clarify the commit message
arch/arm/boot/dts/imx6q-display5.dtsi | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q-display5.dtsi b/arch/arm/boot/dts/imx6q-display5.dtsi
index 4084de43d4d9..09085fde3341 100644
--- a/arch/arm/boot/dts/imx6q-display5.dtsi
+++ b/arch/arm/boot/dts/imx6q-display5.dtsi
@@ -255,7 +255,7 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- codec: tfa9879@6C {
+ codec: tfa9879@6c {
#sound-dai-cells = <0>;
compatible = "nxp,tfa9879";
reg = <0x6C>;
--
2.11.0
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^ permalink raw reply related
* Re: [PATCH v7 6/6] arm64: dts: meson-axg: switch uart_ao clock to CLK81
From: Kevin Hilman @ 2017-12-15 19:14 UTC (permalink / raw)
To: Yixun Lan
Cc: Jerome Brunet, Neil Armstrong, Rob Herring, Mark Rutland,
Michael Turquette, Stephen Boyd, Carlo Caione, Qiufang Dai,
Jian Hu, linux-amlogic, devicetree, linux-clk, linux-arm-kernel,
linux-kernel
In-Reply-To: <b4e29e22-c0e9-1085-fbb7-eabc5c361445@amlogic.com>
Yixun Lan <yixun.lan@amlogic.com> writes:
> On 12/15/17 00:47, Jerome Brunet wrote:
>> On Mon, 2017-12-11 at 22:13 +0800, Yixun Lan wrote:
>>> Switch the uart_ao pclk to CLK81 since the clock driver is ready.
>>> Also move the clock info to the board.dts instead in the soc.dtsi.
>>
>> Same comment as for ethmac, is it really wise ?
>> Isn't the clock setup the same for the axg family ?
>>
> HI Jerome:
> yes, should be same for AXG family
>
>
> HI Kevin:
> could you take the patch [5/6]? then I just need to resend for this one
Yes, I've applied PATCH 5/6.
Kevin
^ permalink raw reply
* Re: [PATCH v7 5/6] arm64: dts: meson-axg: add clock DT info for Meson AXG SoC
From: Kevin Hilman @ 2017-12-15 18:58 UTC (permalink / raw)
To: Yixun Lan
Cc: Neil Armstrong, Jerome Brunet, Rob Herring, Mark Rutland,
Michael Turquette, Stephen Boyd, Carlo Caione, Qiufang Dai,
Jian Hu, linux-amlogic, devicetree, linux-clk, linux-arm-kernel,
linux-kernel
In-Reply-To: <20171211141348.22048-6-yixun.lan@amlogic.com>
Yixun Lan <yixun.lan@amlogic.com> writes:
> From: Qiufang Dai <qiufang.dai@amlogic.com>
>
> Try to add Hiubus DT info, and also enable clock DT info
> for the Amlogic's Meson-AXG SoC.
>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Applied to v4.16/dt64,
Thanks,
Kevin
> ---
> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index b932a784b02a..6fe5ee0c144e 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -148,6 +148,20 @@
> #address-cells = <0>;
> };
>
> + hiubus: bus@ff63c000 {
> + compatible = "simple-bus";
> + reg = <0x0 0xff63c000 0x0 0x1c00>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
> +
> + clkc: clock-controller@0 {
> + compatible = "amlogic,axg-clkc";
> + #clock-cells = <1>;
> + reg = <0x0 0x0 0x0 0x320>;
> + };
> + };
> +
> mailbox: mailbox@ff63dc00 {
> compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
> reg = <0 0xff63dc00 0 0x400>;
^ permalink raw reply
* Re: DT dtc warnings
From: Rob Herring @ 2017-12-15 18:52 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Alexandre Belloni, Fabio Estevam, Barry Song, Kukjin Kim,
Maxime Ripard, Chen-Yu Tsai, Nicolas Ferre, Patrice Chotard,
Peter Rosin, Santosh Shilimkar,
arm-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Mathieu Malaterre
In-Reply-To: <CAJKOXPcf_zf3X8i9xVpK_BSvnR-78otwmaiOERDYTT2tC3VC2A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Fri, Dec 15, 2017 at 1:34 AM, Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Fri, Dec 15, 2017 at 8:29 AM, Alexandre Belloni
> <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
>> On 15/12/2017 at 08:23:39 +0100, Krzysztof Kozlowski wrote:
>>> On Fri, Dec 15, 2017 at 12:02 AM, Fabio Estevam <festevam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>>> > On Thu, Dec 14, 2017 at 7:19 PM, Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
>>> >
>>> >> Thanks for reply!
>>> >>
>>> >> Isn't this property of a SoC? The registers used by
>>> >> syscon-poweroff/reboot are part of SoC power management unit. It does
>>> >> not refer to any externals. Why then it should be put outside of soc?
>>> >
>>> > If these nodes have registers, then they should have a unit address
>>> > and reg property.
>>>
>>> That's the point - they do not have unit address.
>>>
>>
>> Should they be put under the syscon they are using?
+1
> They are not using syscon but regmap provided by such external IP
> block (for example this:
> http://elixir.free-electrons.com/linux/v4.15-rc3/source/arch/arm/boot/dts/exynos3250.dtsi#L153).
> I guess you are proposing something like on imx7s:
> http://elixir.free-electrons.com/linux/v4.15-rc3/source/arch/arm/boot/dts/imx7s.dtsi#L539
Yes, but the regmap property is pointless. It's the parent!
> That makes sense... I am not sure how this would be related to the
> warning itself but anyway it looks logically.
They just have to be under a node that is not a simple-bus.
"soc" nodes with a simple-bus compatible don't really mean everything
in the SoC, but just all (or some part of) the memory mapped space.
There's many board specific settings within those nodes. We don't
really split up top-level things into board and soc levels.
Rob
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^ permalink raw reply
* Re: [PATCH 0/2] Add SFF module support
From: David Miller @ 2017-12-15 18:23 UTC (permalink / raw)
To: linux; +Cc: andrew, f.fainelli, robh+dt, devicetree, mark.rutland, netdev
In-Reply-To: <20171214102712.GP10595@n2100.armlinux.org.uk>
From: Russell King - ARM Linux <linux@armlinux.org.uk>
Date: Thu, 14 Dec 2017 10:27:13 +0000
> Add support for SFF modules. SFF modules are similar to SFP modules,
> but they have fewer control signals, and are soldered down rather than
> pluggable.
>
> They also have different IDs in the EEPROM to identify as soldered down
> SFF modules.
Series applied.
^ permalink raw reply
* [PATCH 9/9] ARM: dts: Update ti-sysc data for existing users
From: Tony Lindgren @ 2017-12-15 18:09 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: Benoît Cousson, Dave Gerlach, Nishanth Menon, Paul Walmsley,
Tero Kristo, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171215180900.3243-1-tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
Let's update the existing users with features and clock data.
Note that we had few mistakes that did not get noticed as we're still
probing the SmartReflex driver with legacy platform data and using
"ti,hwmods" legacy property for ti-sysc driver.
So let's fix the dra7 smartreflex registers as they are different
from omap4 with no revision register.
And on omap4, the mcasp module has a revision register according to
the TRM.
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
arch/arm/boot/dts/dra7.dtsi | 26 ++++++++++++----
arch/arm/boot/dts/omap4.dtsi | 74 ++++++++++++++++++++++++++++++++++++++++++--
2 files changed, 92 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -7,6 +7,8 @@
* Based on "omap4.dtsi"
*/
+#include <dt-bindings/bus/ti-sysc.h>
+#include <dt-bindings/clock/dra7.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/dra.h>
@@ -1500,9 +1502,15 @@
target-module@4a0dd000 {
compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_core";
- reg = <0x4a0dd000 0x4>,
- <0x4a0dd008 0x4>;
- reg-names = "rev", "sysc";
+ reg = <0x4a0dd038 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_CORE_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a0dd000 0x001000>;
@@ -1513,9 +1521,15 @@
target-module@4a0d9000 {
compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_mpu";
- reg = <0x4a0d9000 0x4>,
- <0x4a0d9008 0x4>;
- reg-names = "rev", "sysc";
+ reg = <0x4a0d9038 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_MPU_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a0d9000 0x001000>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -6,6 +6,8 @@
* published by the Free Software Foundation.
*/
+#include <dt-bindings/bus/ti-sysc.h>
+#include <dt-bindings/clock/omap4.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>
@@ -388,6 +390,13 @@
reg = <0x48076000 0x4>,
<0x48076010 0x4>;
reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48076000 0x001000>;
@@ -461,6 +470,8 @@
reg = <0x4a0db000 0x4>,
<0x4a0db008 0x4>;
reg-names = "rev", "sysc";
+ clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a0db000 0x001000>;
@@ -478,6 +489,8 @@
reg = <0x4a0dd000 0x4>,
<0x4a0dd008 0x4>;
reg-names = "rev", "sysc";
+ clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a0dd000 0x001000>;
@@ -495,6 +508,8 @@
reg = <0x4a0d9000 0x4>,
<0x4a0d9008 0x4>;
reg-names = "rev", "sysc";
+ clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a0d9000 0x001000>;
@@ -715,6 +730,18 @@
reg = <0x52000000 0x4>,
<0x52000010 0x4>;
reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-delay-us = <2>;
+ clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x52000000 0x1000000>;
@@ -819,8 +846,15 @@
target-module@40128000 {
compatible = "ti,sysc-mcasp", "ti,sysc";
ti,hwmods = "mcasp";
- reg = <0x40128004 0x4>;
- reg-names = "sysc";
+ reg = <0x40128000 0x4>,
+ <0x40128004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x40128000 0x1000>, /* MPU */
@@ -840,6 +874,13 @@
reg = <0x4012c000 0x4>,
<0x4012c010 0x4>;
reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
@@ -854,6 +895,15 @@
reg = <0x401f1000 0x4>,
<0x401f1010 0x4>;
reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x401f1000 0x1000>, /* MPU */
@@ -960,6 +1010,16 @@
reg = <0x4a10a000 0x4>,
<0x4a10a010 0x4>;
reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-delay-us = <2>;
+ clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a10a000 0x1000>;
@@ -1188,6 +1248,16 @@
reg = <0x5601fc00 0x4>,
<0x5601fc10 0x4>;
reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x56000000 0x2000000>;
--
2.15.0
--
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^ permalink raw reply
* [PATCH 8/9] bus: ti-sysc: Add parsing of module capabilities
From: Tony Lindgren @ 2017-12-15 18:08 UTC (permalink / raw)
To: linux-omap
Cc: Benoît Cousson, Dave Gerlach, Nishanth Menon, Paul Walmsley,
Tero Kristo, linux-kernel, linux-arm-kernel, devicetree
In-Reply-To: <20171215180900.3243-1-tony@atomide.com>
We need to configure the interconnect target module based on the
device three configuration.
Let's also add a new quirk for SYSC_QUIRK_RESET_STATUS to indicate
that the SYSCONFIG reset bit changes after the reset is done.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
drivers/bus/ti-sysc.c | 100 ++++++++++++++++++++++++++++++++++
include/linux/platform_data/ti-sysc.h | 10 ++++
2 files changed, 110 insertions(+)
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
--- a/drivers/bus/ti-sysc.c
+++ b/drivers/bus/ti-sysc.c
@@ -39,6 +39,9 @@ enum sysc_clocks {
static const char * const clock_names[] = { "fck", "ick", };
+#define SYSC_IDLEMODE_MASK 3
+#define SYSC_CLOCKACTIVITY_MASK 3
+
/**
* struct sysc - TI sysc interconnect target module registers and capabilities
* @dev: struct device pointer
@@ -517,6 +520,91 @@ static int sysc_init_module(struct sysc *ddata)
return 0;
}
+static int sysc_init_sysc_mask(struct sysc *ddata)
+{
+ struct device_node *np = ddata->dev->of_node;
+ int error;
+ u32 val;
+
+ error = of_property_read_u32(np, "ti,sysc-mask", &val);
+ if (error)
+ return 0;
+
+ if (val)
+ ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
+ else
+ ddata->cfg.sysc_val = ddata->cap->sysc_mask;
+
+ return 0;
+}
+
+static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
+ const char *name)
+{
+ struct device_node *np = ddata->dev->of_node;
+ struct property *prop;
+ const __be32 *p;
+ u32 val;
+
+ of_property_for_each_u32(np, name, prop, p, val) {
+ if (val >= SYSC_NR_IDLEMODES) {
+ dev_err(ddata->dev, "invalid idlemode: %i\n", val);
+ return -EINVAL;
+ }
+ *idlemodes |= (1 << val);
+ }
+
+ return 0;
+}
+
+static int sysc_init_idlemodes(struct sysc *ddata)
+{
+ int error;
+
+ error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
+ "ti,sysc-midle");
+ if (error)
+ return error;
+
+ error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
+ "ti,sysc-sidle");
+ if (error)
+ return error;
+
+ return 0;
+}
+
+/*
+ * Only some devices on omap4 and later have SYSCONFIG reset done
+ * bit. We can detect this if there is no SYSSTATUS at all, or the
+ * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
+ * have multiple bits for the child devices like OHCI and EHCI.
+ * Depends on SYSC being parsed first.
+ */
+static int sysc_init_syss_mask(struct sysc *ddata)
+{
+ struct device_node *np = ddata->dev->of_node;
+ int error;
+ u32 val;
+
+ error = of_property_read_u32(np, "ti,syss-mask", &val);
+ if (error) {
+ if ((ddata->cap->type == TI_SYSC_OMAP4 ||
+ ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
+ (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
+ ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
+
+ return 0;
+ }
+
+ if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
+ ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
+
+ ddata->cfg.syss_mask = val;
+
+ return 0;
+}
+
/* Device tree configured quirks */
struct sysc_dts_quirk {
const char *name;
@@ -820,6 +908,18 @@ static int sysc_probe(struct platform_device *pdev)
if (error)
goto unprepare;
+ error = sysc_init_sysc_mask(ddata);
+ if (error)
+ goto unprepare;
+
+ error = sysc_init_idlemodes(ddata);
+ if (error)
+ goto unprepare;
+
+ error = sysc_init_syss_mask(ddata);
+ if (error)
+ goto unprepare;
+
pm_runtime_enable(ddata->dev);
error = sysc_init_module(ddata);
diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h
--- a/include/linux/platform_data/ti-sysc.h
+++ b/include/linux/platform_data/ti-sysc.h
@@ -41,6 +41,7 @@ struct sysc_regbits {
s8 emufree_shift;
};
+#define SYSC_QUIRK_RESET_STATUS BIT(7)
#define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6)
#define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5)
#define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4)
@@ -49,6 +50,8 @@ struct sysc_regbits {
#define SYSC_QUIRK_UNCACHED BIT(1)
#define SYSC_QUIRK_USE_CLOCKACT BIT(0)
+#define SYSC_NR_IDLEMODES 4
+
/**
* struct sysc_capabilities - capabilities for an interconnect target module
*
@@ -65,10 +68,17 @@ struct sysc_capabilities {
/**
* struct sysc_config - configuration for an interconnect target module
+ * @sysc_val: configured value for sysc register
+ * @midlemodes: bitmask of supported master idle modes
+ * @sidlemodes: bitmask of supported master idle modes
* @srst_udelay: optional delay needed after OCP soft reset
* @quirks: bitmask of enabled quirks
*/
struct sysc_config {
+ u32 sysc_val;
+ u32 syss_mask;
+ u8 midlemodes;
+ u8 sidlemodes;
u8 srst_udelay;
u32 quirks;
};
--
2.15.0
^ permalink raw reply
* [PATCH 7/9] bus: ti-sysc: Handle module quirks based dts configuration
From: Tony Lindgren @ 2017-12-15 18:08 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: Benoît Cousson, Dave Gerlach, Nishanth Menon, Paul Walmsley,
Tero Kristo, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171215180900.3243-1-tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
Let's configure few module quirks via device tree using the
properties for "ti,no-idle-on-init", "ti,no-reset-on-init"
and "ti,sysc-delay-us".
Let's also reorder the probe a bit so we have pdata available
earlier, and move the PM runtime calls to sysc_init_module()
from sysc_read_revision().
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
drivers/bus/ti-sysc.c | 114 ++++++++++++++++++++++++++++------
include/linux/platform_data/ti-sysc.h | 6 ++
2 files changed, 102 insertions(+), 18 deletions(-)
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
--- a/drivers/bus/ti-sysc.c
+++ b/drivers/bus/ti-sysc.c
@@ -50,6 +50,8 @@ static const char * const clock_names[] = { "fck", "ick", };
* @legacy_mode: configured for legacy mode if set
* @cap: interconnect target module capabilities
* @cfg: interconnect target module configuration
+ * @name: name if available
+ * @revision: interconnect target module revision
*/
struct sysc {
struct device *dev;
@@ -61,12 +63,32 @@ struct sysc {
const char *legacy_mode;
const struct sysc_capabilities *cap;
struct sysc_config cfg;
+ const char *name;
+ u32 revision;
};
+static u32 sysc_read(struct sysc *ddata, int offset)
+{
+ if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
+ u32 val;
+
+ val = readw_relaxed(ddata->module_va + offset);
+ val |= (readw_relaxed(ddata->module_va + offset + 4) << 16);
+
+ return val;
+ }
+
+ return readl_relaxed(ddata->module_va + offset);
+}
+
static u32 sysc_read_revision(struct sysc *ddata)
{
- return readl_relaxed(ddata->module_va +
- ddata->offsets[SYSC_REVISION]);
+ int offset = ddata->offsets[SYSC_REVISION];
+
+ if (offset < 0)
+ return 0;
+
+ return sysc_read(ddata, offset);
}
static int sysc_get_one_clock(struct sysc *ddata,
@@ -393,22 +415,12 @@ static int sysc_map_and_check_registers(struct sysc *ddata)
*/
static int sysc_show_rev(char *bufp, struct sysc *ddata)
{
- int error, len;
+ int len;
if (ddata->offsets[SYSC_REVISION] < 0)
return sprintf(bufp, ":NA");
- error = pm_runtime_get_sync(ddata->dev);
- if (error < 0) {
- pm_runtime_put_noidle(ddata->dev);
-
- return 0;
- }
-
- len = sprintf(bufp, ":%08x", sysc_read_revision(ddata));
-
- pm_runtime_mark_last_busy(ddata->dev);
- pm_runtime_put_autosuspend(ddata->dev);
+ len = sprintf(bufp, ":%08x", ddata->revision);
return len;
}
@@ -488,6 +500,66 @@ static const struct dev_pm_ops sysc_pm_ops = {
NULL)
};
+/* At this point the module is configured enough to read the revision */
+static int sysc_init_module(struct sysc *ddata)
+{
+ int error;
+
+ error = pm_runtime_get_sync(ddata->dev);
+ if (error < 0) {
+ pm_runtime_put_noidle(ddata->dev);
+
+ return 0;
+ }
+ ddata->revision = sysc_read_revision(ddata);
+ pm_runtime_put_sync(ddata->dev);
+
+ return 0;
+}
+
+/* Device tree configured quirks */
+struct sysc_dts_quirk {
+ const char *name;
+ u32 mask;
+};
+
+static const struct sysc_dts_quirk sysc_dts_quirks[] = {
+ { .name = "ti,no-idle-on-init",
+ .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
+ { .name = "ti,no-reset-on-init",
+ .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
+};
+
+static int sysc_init_dts_quirks(struct sysc *ddata)
+{
+ struct device_node *np = ddata->dev->of_node;
+ const struct property *prop;
+ int i, len, error;
+ u32 val;
+
+ ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
+
+ for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
+ prop = of_get_property(np, sysc_dts_quirks[i].name, &len);
+ if (!prop)
+ break;
+
+ ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
+ }
+
+ error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
+ if (!error) {
+ if (val > 255) {
+ dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
+ val);
+ }
+
+ ddata->cfg.srst_udelay = (u8)val;
+ }
+
+ return 0;
+}
+
static void sysc_unprepare(struct sysc *ddata)
{
int i;
@@ -722,7 +794,6 @@ static int sysc_init_match(struct sysc *ddata)
static int sysc_probe(struct platform_device *pdev)
{
- struct device_node *np = pdev->dev.of_node;
struct sysc *ddata;
int error;
@@ -731,12 +802,16 @@ static int sysc_probe(struct platform_device *pdev)
return -ENOMEM;
ddata->dev = &pdev->dev;
- ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
+ platform_set_drvdata(pdev, ddata);
error = sysc_init_match(ddata);
if (error)
return error;
+ error = sysc_init_dts_quirks(ddata);
+ if (error)
+ goto unprepare;
+
error = sysc_get_clocks(ddata);
if (error)
return error;
@@ -745,9 +820,12 @@ static int sysc_probe(struct platform_device *pdev)
if (error)
goto unprepare;
- platform_set_drvdata(pdev, ddata);
-
pm_runtime_enable(ddata->dev);
+
+ error = sysc_init_module(ddata);
+ if (error)
+ goto unprepare;
+
error = pm_runtime_get_sync(ddata->dev);
if (error < 0) {
pm_runtime_put_noidle(ddata->dev);
diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h
--- a/include/linux/platform_data/ti-sysc.h
+++ b/include/linux/platform_data/ti-sysc.h
@@ -41,6 +41,10 @@ struct sysc_regbits {
s8 emufree_shift;
};
+#define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6)
+#define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5)
+#define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4)
+#define SYSC_QUIRK_OPT_CLKS_IN_RESET BIT(3)
#define SYSC_QUIRK_16BIT BIT(2)
#define SYSC_QUIRK_UNCACHED BIT(1)
#define SYSC_QUIRK_USE_CLOCKACT BIT(0)
@@ -61,9 +65,11 @@ struct sysc_capabilities {
/**
* struct sysc_config - configuration for an interconnect target module
+ * @srst_udelay: optional delay needed after OCP soft reset
* @quirks: bitmask of enabled quirks
*/
struct sysc_config {
+ u8 srst_udelay;
u32 quirks;
};
--
2.15.0
--
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^ permalink raw reply
* [PATCH 6/9] bus: ti-sysc: Detect i2c interconnect target module based on register layout
From: Tony Lindgren @ 2017-12-15 18:08 UTC (permalink / raw)
To: linux-omap
Cc: Benoît Cousson, Dave Gerlach, Nishanth Menon, Paul Walmsley,
Tero Kristo, linux-kernel, linux-arm-kernel, devicetree
In-Reply-To: <20171215180900.3243-1-tony@atomide.com>
We can easily detect i2c based on it's non-standard module registers that
consist of two 32-bit registers accessed in 16-bit mode.
So far we don't have other 16-bit modules, so there's currently no need
to add a custom property for 16-bit register access.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
drivers/bus/ti-sysc.c | 17 +++++++++++++++++
include/linux/platform_data/ti-sysc.h | 1 +
2 files changed, 18 insertions(+)
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
--- a/drivers/bus/ti-sysc.c
+++ b/drivers/bus/ti-sysc.c
@@ -213,6 +213,21 @@ static int sysc_check_children(struct sysc *ddata)
return 0;
}
+/*
+ * So far only I2C uses 16-bit read access with clockactivity with revision
+ * in two registers with stride of 4. We can detect this based on the rev
+ * register size to configure things far enough to be able to properly read
+ * the revision register.
+ */
+static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
+{
+ if (resource_size(res) == 8) {
+ dev_dbg(ddata->dev,
+ "enabling 16-bit and clockactivity quirks\n");
+ ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
+ }
+}
+
/**
* sysc_parse_one - parses the interconnect target module registers
* @ddata: device driver data
@@ -243,6 +258,8 @@ static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
}
ddata->offsets[reg] = res->start - ddata->module_pa;
+ if (reg == SYSC_REVISION)
+ sysc_check_quirk_16bit(ddata, res);
return 0;
}
diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h
--- a/include/linux/platform_data/ti-sysc.h
+++ b/include/linux/platform_data/ti-sysc.h
@@ -41,6 +41,7 @@ struct sysc_regbits {
s8 emufree_shift;
};
+#define SYSC_QUIRK_16BIT BIT(2)
#define SYSC_QUIRK_UNCACHED BIT(1)
#define SYSC_QUIRK_USE_CLOCKACT BIT(0)
--
2.15.0
^ permalink raw reply
* [PATCH 5/9] bus: ti-sysc: Add register bits for interconnect target modules
From: Tony Lindgren @ 2017-12-15 18:08 UTC (permalink / raw)
To: linux-omap
Cc: Benoît Cousson, Dave Gerlach, Nishanth Menon, Paul Walmsley,
Tero Kristo, linux-kernel, linux-arm-kernel, devicetree
In-Reply-To: <20171215180900.3243-1-tony@atomide.com>
Let's add data for the known interconnect target module types by mapping
their register bits.
Note that we can handle many quirks for the older omap2 type1 modules
directly in the driver without a need for adding custom properties.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
drivers/bus/ti-sysc.c | 256 ++++++++++++++++++++++++++++++++--
include/linux/platform_data/ti-sysc.h | 40 ++++++
2 files changed, 286 insertions(+), 10 deletions(-)
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
--- a/drivers/bus/ti-sysc.c
+++ b/drivers/bus/ti-sysc.c
@@ -18,6 +18,9 @@
#include <linux/pm_runtime.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
+#include <linux/platform_data/ti-sysc.h>
+
+#include <dt-bindings/bus/ti-sysc.h>
enum sysc_registers {
SYSC_REVISION,
@@ -45,6 +48,8 @@ static const char * const clock_names[] = { "fck", "ick", };
* @offsets: register offsets from module base
* @clocks: clocks used by the interconnect target module
* @legacy_mode: configured for legacy mode if set
+ * @cap: interconnect target module capabilities
+ * @cfg: interconnect target module configuration
*/
struct sysc {
struct device *dev;
@@ -54,6 +59,8 @@ struct sysc {
int offsets[SYSC_MAX_REGS];
struct clk *clocks[SYSC_MAX_CLOCKS];
const char *legacy_mode;
+ const struct sysc_capabilities *cap;
+ struct sysc_config cfg;
};
static u32 sysc_read_revision(struct sysc *ddata)
@@ -474,6 +481,228 @@ static void sysc_unprepare(struct sysc *ddata)
}
}
+/*
+ * Common sysc register bits found on omap2, also known as type1
+ */
+static const struct sysc_regbits sysc_regbits_omap2 = {
+ .dmadisable_shift = -ENODEV,
+ .midle_shift = 12,
+ .sidle_shift = 3,
+ .clkact_shift = 8,
+ .emufree_shift = 5,
+ .enwkup_shift = 2,
+ .srst_shift = 1,
+ .autoidle_shift = 0,
+};
+
+static const struct sysc_capabilities sysc_omap2 = {
+ .type = TI_SYSC_OMAP2,
+ .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE,
+ .regbits = &sysc_regbits_omap2,
+};
+
+/* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
+static const struct sysc_capabilities sysc_omap2_timer = {
+ .type = TI_SYSC_OMAP2_TIMER,
+ .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE,
+ .regbits = &sysc_regbits_omap2,
+ .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
+};
+
+/*
+ * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
+ * with different sidle position
+ */
+static const struct sysc_regbits sysc_regbits_omap3_sham = {
+ .dmadisable_shift = -ENODEV,
+ .midle_shift = -ENODEV,
+ .sidle_shift = 4,
+ .clkact_shift = -ENODEV,
+ .enwkup_shift = -ENODEV,
+ .srst_shift = 1,
+ .autoidle_shift = 0,
+ .emufree_shift = -ENODEV,
+};
+
+static const struct sysc_capabilities sysc_omap3_sham = {
+ .type = TI_SYSC_OMAP3_SHAM,
+ .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
+ .regbits = &sysc_regbits_omap3_sham,
+};
+
+/*
+ * AES register bits found on omap3 and later, a variant of
+ * sysc_regbits_omap2 with different sidle position
+ */
+static const struct sysc_regbits sysc_regbits_omap3_aes = {
+ .dmadisable_shift = -ENODEV,
+ .midle_shift = -ENODEV,
+ .sidle_shift = 6,
+ .clkact_shift = -ENODEV,
+ .enwkup_shift = -ENODEV,
+ .srst_shift = 1,
+ .autoidle_shift = 0,
+ .emufree_shift = -ENODEV,
+};
+
+static const struct sysc_capabilities sysc_omap3_aes = {
+ .type = TI_SYSC_OMAP3_AES,
+ .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
+ .regbits = &sysc_regbits_omap3_aes,
+};
+
+/*
+ * Common sysc register bits found on omap4, also known as type2
+ */
+static const struct sysc_regbits sysc_regbits_omap4 = {
+ .dmadisable_shift = 16,
+ .midle_shift = 4,
+ .sidle_shift = 2,
+ .clkact_shift = -ENODEV,
+ .enwkup_shift = -ENODEV,
+ .emufree_shift = 1,
+ .srst_shift = 0,
+ .autoidle_shift = -ENODEV,
+};
+
+static const struct sysc_capabilities sysc_omap4 = {
+ .type = TI_SYSC_OMAP4,
+ .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET,
+ .regbits = &sysc_regbits_omap4,
+};
+
+static const struct sysc_capabilities sysc_omap4_timer = {
+ .type = TI_SYSC_OMAP4_TIMER,
+ .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET,
+ .regbits = &sysc_regbits_omap4,
+};
+
+/*
+ * Common sysc register bits found on omap4, also known as type3
+ */
+static const struct sysc_regbits sysc_regbits_omap4_simple = {
+ .dmadisable_shift = -ENODEV,
+ .midle_shift = 2,
+ .sidle_shift = 0,
+ .clkact_shift = -ENODEV,
+ .enwkup_shift = -ENODEV,
+ .srst_shift = -ENODEV,
+ .emufree_shift = -ENODEV,
+ .autoidle_shift = -ENODEV,
+};
+
+static const struct sysc_capabilities sysc_omap4_simple = {
+ .type = TI_SYSC_OMAP4_SIMPLE,
+ .regbits = &sysc_regbits_omap4_simple,
+};
+
+/*
+ * SmartReflex sysc found on omap34xx
+ */
+static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
+ .dmadisable_shift = -ENODEV,
+ .midle_shift = -ENODEV,
+ .sidle_shift = -ENODEV,
+ .clkact_shift = 20,
+ .enwkup_shift = -ENODEV,
+ .srst_shift = -ENODEV,
+ .emufree_shift = -ENODEV,
+ .autoidle_shift = -ENODEV,
+};
+
+static const struct sysc_capabilities sysc_34xx_sr = {
+ .type = TI_SYSC_OMAP34XX_SR,
+ .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
+ .regbits = &sysc_regbits_omap34xx_sr,
+ .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED,
+};
+
+/*
+ * SmartReflex sysc found on omap36xx and later
+ */
+static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
+ .dmadisable_shift = -ENODEV,
+ .midle_shift = -ENODEV,
+ .sidle_shift = 24,
+ .clkact_shift = -ENODEV,
+ .enwkup_shift = 26,
+ .srst_shift = -ENODEV,
+ .emufree_shift = -ENODEV,
+ .autoidle_shift = -ENODEV,
+};
+
+static const struct sysc_capabilities sysc_36xx_sr = {
+ .type = TI_SYSC_OMAP36XX_SR,
+ .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
+ .regbits = &sysc_regbits_omap36xx_sr,
+ .mod_quirks = SYSC_QUIRK_UNCACHED,
+};
+
+static const struct sysc_capabilities sysc_omap4_sr = {
+ .type = TI_SYSC_OMAP4_SR,
+ .regbits = &sysc_regbits_omap36xx_sr,
+};
+
+/*
+ * McASP register bits found on omap4 and later
+ */
+static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
+ .dmadisable_shift = -ENODEV,
+ .midle_shift = -ENODEV,
+ .sidle_shift = 0,
+ .clkact_shift = -ENODEV,
+ .enwkup_shift = -ENODEV,
+ .srst_shift = -ENODEV,
+ .emufree_shift = -ENODEV,
+ .autoidle_shift = -ENODEV,
+};
+
+static const struct sysc_capabilities sysc_omap4_mcasp = {
+ .type = TI_SYSC_OMAP4_MCASP,
+ .regbits = &sysc_regbits_omap4_mcasp,
+};
+
+/*
+ * FS USB host found on omap4 and later
+ */
+static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
+ .dmadisable_shift = -ENODEV,
+ .midle_shift = -ENODEV,
+ .sidle_shift = 24,
+ .clkact_shift = -ENODEV,
+ .enwkup_shift = 26,
+ .srst_shift = -ENODEV,
+ .emufree_shift = -ENODEV,
+ .autoidle_shift = -ENODEV,
+};
+
+static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
+ .type = TI_SYSC_OMAP4_USB_HOST_FS,
+ .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
+ .regbits = &sysc_regbits_omap4_usb_host_fs,
+};
+
+static int sysc_init_match(struct sysc *ddata)
+{
+ const struct sysc_capabilities *cap;
+
+ cap = of_device_get_match_data(ddata->dev);
+ if (!cap)
+ return -EINVAL;
+
+ ddata->cap = cap;
+ if (ddata->cap)
+ ddata->cfg.quirks |= ddata->cap->mod_quirks;
+
+ return 0;
+}
+
static int sysc_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@@ -487,6 +716,10 @@ static int sysc_probe(struct platform_device *pdev)
ddata->dev = &pdev->dev;
ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
+ error = sysc_init_match(ddata);
+ if (error)
+ return error;
+
error = sysc_get_clocks(ddata);
if (error)
return error;
@@ -554,16 +787,19 @@ static int sysc_remove(struct platform_device *pdev)
}
static const struct of_device_id sysc_match[] = {
- { .compatible = "ti,sysc-omap2" },
- { .compatible = "ti,sysc-omap4" },
- { .compatible = "ti,sysc-omap4-simple" },
- { .compatible = "ti,sysc-omap3430-sr" },
- { .compatible = "ti,sysc-omap3630-sr" },
- { .compatible = "ti,sysc-omap4-sr" },
- { .compatible = "ti,sysc-omap3-sham" },
- { .compatible = "ti,sysc-omap-aes" },
- { .compatible = "ti,sysc-mcasp" },
- { .compatible = "ti,sysc-usb-host-fs" },
+ { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
+ { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
+ { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
+ { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
+ { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
+ { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
+ { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
+ { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
+ { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
+ { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
+ { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
+ { .compatible = "ti,sysc-usb-host-fs",
+ .data = &sysc_omap4_usb_host_fs, },
{ },
};
MODULE_DEVICE_TABLE(of, sysc_match);
diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h
--- a/include/linux/platform_data/ti-sysc.h
+++ b/include/linux/platform_data/ti-sysc.h
@@ -1,6 +1,21 @@
#ifndef __TI_SYSC_DATA_H__
#define __TI_SYSC_DATA_H__
+enum ti_sysc_module_type {
+ TI_SYSC_OMAP2,
+ TI_SYSC_OMAP2_TIMER,
+ TI_SYSC_OMAP3_SHAM,
+ TI_SYSC_OMAP3_AES,
+ TI_SYSC_OMAP4,
+ TI_SYSC_OMAP4_TIMER,
+ TI_SYSC_OMAP4_SIMPLE,
+ TI_SYSC_OMAP34XX_SR,
+ TI_SYSC_OMAP36XX_SR,
+ TI_SYSC_OMAP4_SR,
+ TI_SYSC_OMAP4_MCASP,
+ TI_SYSC_OMAP4_USB_HOST_FS,
+};
+
/**
* struct sysc_regbits - TI OCP_SYSCONFIG register field offsets
* @midle_shift: Offset of the midle bit
@@ -26,4 +41,29 @@ struct sysc_regbits {
s8 emufree_shift;
};
+#define SYSC_QUIRK_UNCACHED BIT(1)
+#define SYSC_QUIRK_USE_CLOCKACT BIT(0)
+
+/**
+ * struct sysc_capabilities - capabilities for an interconnect target module
+ *
+ * @sysc_mask: bitmask of supported SYSCONFIG register bits
+ * @regbits: bitmask of SYSCONFIG register bits
+ * @mod_quirks: bitmask of module specific quirks
+ */
+struct sysc_capabilities {
+ const enum ti_sysc_module_type type;
+ const u32 sysc_mask;
+ const struct sysc_regbits *regbits;
+ const u32 mod_quirks;
+};
+
+/**
+ * struct sysc_config - configuration for an interconnect target module
+ * @quirks: bitmask of enabled quirks
+ */
+struct sysc_config {
+ u32 quirks;
+};
+
#endif /* __TI_SYSC_DATA_H__ */
--
2.15.0
^ permalink raw reply
* [PATCH 4/9] bus: ti-sysc: Make omap_hwmod_sysc_fields into sysc_regbits platform data
From: Tony Lindgren @ 2017-12-15 18:08 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: Benoît Cousson, Dave Gerlach, Nishanth Menon, Paul Walmsley,
Tero Kristo, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171215180900.3243-1-tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
We want to be able to configure hwmod sysc data from ti-sysc driver using
platform data callbacks. So let's make struct omap_hwmod_sysc_fields into
struct sysc_data and have it available for both ti-sysc driver and hwmod
code.
Note that we can make it use s8 instead of u8 as the hwmod code uses the
feature flags to check for this field. However, for ti-sysc we can use
-ENODEV to indicate a feature is not supported in the hardware and can
simplify the code that way.
And let's add also emufree_shift as the dts files will be describing the
hardware for the SYSCONFIG register capbilities mask.
Cc: Paul Walmsley <paul-DWxLp4Yu+b8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
arch/arm/mach-omap2/omap_hwmod.c | 2 ++
arch/arm/mach-omap2/omap_hwmod.h | 40 +++++++---------------------
arch/arm/mach-omap2/omap_hwmod_common_data.c | 21 ++++++++-------
include/linux/platform_data/ti-sysc.h | 29 ++++++++++++++++++++
4 files changed, 53 insertions(+), 39 deletions(-)
create mode 100644 include/linux/platform_data/ti-sysc.h
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -143,6 +143,8 @@
#include <linux/of_address.h>
#include <linux/bootmem.h>
+#include <linux/platform_data/ti-sysc.h>
+
#include <asm/system_misc.h>
#include "clock.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -37,15 +37,15 @@
struct omap_device;
-extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
-extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
-extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
-extern struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields;
-extern struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields;
-extern struct omap_hwmod_sysc_fields omap3_sham_sysc_fields;
-extern struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields;
-extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp;
-extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs;
+extern struct sysc_regbits omap_hwmod_sysc_type1;
+extern struct sysc_regbits omap_hwmod_sysc_type2;
+extern struct sysc_regbits omap_hwmod_sysc_type3;
+extern struct sysc_regbits omap34xx_sr_sysc_fields;
+extern struct sysc_regbits omap36xx_sr_sysc_fields;
+extern struct sysc_regbits omap3_sham_sysc_fields;
+extern struct sysc_regbits omap3xxx_aes_sysc_fields;
+extern struct sysc_regbits omap_hwmod_sysc_type_mcasp;
+extern struct sysc_regbits omap_hwmod_sysc_type_usb_host_fs;
/*
* OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
@@ -290,26 +290,6 @@ struct omap_hwmod_ocp_if {
#define CLOCKACT_TEST_ICLK 0x2
#define CLOCKACT_TEST_NONE 0x3
-/**
- * struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets.
- * @midle_shift: Offset of the midle bit
- * @clkact_shift: Offset of the clockactivity bit
- * @sidle_shift: Offset of the sidle bit
- * @enwkup_shift: Offset of the enawakeup bit
- * @srst_shift: Offset of the softreset bit
- * @autoidle_shift: Offset of the autoidle bit
- * @dmadisable_shift: Offset of the dmadisable bit
- */
-struct omap_hwmod_sysc_fields {
- u8 midle_shift;
- u8 clkact_shift;
- u8 sidle_shift;
- u8 enwkup_shift;
- u8 srst_shift;
- u8 autoidle_shift;
- u8 dmadisable_shift;
-};
-
/**
* struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data
* @rev_offs: IP block revision register offset (from module base addr)
@@ -341,7 +321,7 @@ struct omap_hwmod_class_sysconfig {
u32 sysc_offs;
u32 syss_offs;
u16 sysc_flags;
- struct omap_hwmod_sysc_fields *sysc_fields;
+ struct sysc_regbits *sysc_fields;
u8 srst_udelay;
u8 idlemodes;
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
@@ -16,6 +16,9 @@
* data and their integration with other OMAP modules and Linux.
*/
+#include <linux/types.h>
+#include <linux/platform_data/ti-sysc.h>
+
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
@@ -27,7 +30,7 @@
* if the device ip is compliant with the original PRCM protocol
* defined for OMAP2420.
*/
-struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1 = {
+struct sysc_regbits omap_hwmod_sysc_type1 = {
.midle_shift = SYSC_TYPE1_MIDLEMODE_SHIFT,
.clkact_shift = SYSC_TYPE1_CLOCKACTIVITY_SHIFT,
.sidle_shift = SYSC_TYPE1_SIDLEMODE_SHIFT,
@@ -43,7 +46,7 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1 = {
* device ip is compliant with the new PRCM protocol defined for new
* OMAP4 IPs.
*/
-struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
+struct sysc_regbits omap_hwmod_sysc_type2 = {
.midle_shift = SYSC_TYPE2_MIDLEMODE_SHIFT,
.sidle_shift = SYSC_TYPE2_SIDLEMODE_SHIFT,
.srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,
@@ -54,7 +57,7 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
* struct omap_hwmod_sysc_type3 - TYPE3 sysconfig scheme.
* Used by some IPs on AM33xx
*/
-struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3 = {
+struct sysc_regbits omap_hwmod_sysc_type3 = {
.midle_shift = SYSC_TYPE3_MIDLEMODE_SHIFT,
.sidle_shift = SYSC_TYPE3_SIDLEMODE_SHIFT,
};
@@ -64,32 +67,32 @@ struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
.has_framedonetv_irq = 0
};
-struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
+struct sysc_regbits omap34xx_sr_sysc_fields = {
.clkact_shift = 20,
};
-struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
+struct sysc_regbits omap36xx_sr_sysc_fields = {
.sidle_shift = 24,
.enwkup_shift = 26,
};
-struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
+struct sysc_regbits omap3_sham_sysc_fields = {
.sidle_shift = 4,
.srst_shift = 1,
.autoidle_shift = 0,
};
-struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
+struct sysc_regbits omap3xxx_aes_sysc_fields = {
.sidle_shift = 6,
.srst_shift = 1,
.autoidle_shift = 0,
};
-struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
+struct sysc_regbits omap_hwmod_sysc_type_mcasp = {
.sidle_shift = 0,
};
-struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
+struct sysc_regbits omap_hwmod_sysc_type_usb_host_fs = {
.midle_shift = 4,
.sidle_shift = 2,
.srst_shift = 1,
diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h
new file mode 100644
--- /dev/null
+++ b/include/linux/platform_data/ti-sysc.h
@@ -0,0 +1,29 @@
+#ifndef __TI_SYSC_DATA_H__
+#define __TI_SYSC_DATA_H__
+
+/**
+ * struct sysc_regbits - TI OCP_SYSCONFIG register field offsets
+ * @midle_shift: Offset of the midle bit
+ * @clkact_shift: Offset of the clockactivity bit
+ * @sidle_shift: Offset of the sidle bit
+ * @enwkup_shift: Offset of the enawakeup bit
+ * @srst_shift: Offset of the softreset bit
+ * @autoidle_shift: Offset of the autoidle bit
+ * @dmadisable_shift: Offset of the dmadisable bit
+ * @emufree_shift; Offset of the emufree bit
+ *
+ * Note that 0 is a valid shift, and for ti-sysc.c -ENODEV can be used if a
+ * feature is not available.
+ */
+struct sysc_regbits {
+ s8 midle_shift;
+ s8 clkact_shift;
+ s8 sidle_shift;
+ s8 enwkup_shift;
+ s8 srst_shift;
+ s8 autoidle_shift;
+ s8 dmadisable_shift;
+ s8 emufree_shift;
+};
+
+#endif /* __TI_SYSC_DATA_H__ */
--
2.15.0
--
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^ permalink raw reply
* [PATCH 3/9] ARM: OMAP2+: Move all omap_hwmod_sysc_fields to omap_hwmod_common_data.c
From: Tony Lindgren @ 2017-12-15 18:08 UTC (permalink / raw)
To: linux-omap
Cc: Nishanth Menon, devicetree, Paul Walmsley, Dave Gerlach,
linux-kernel, Tero Kristo, Benoît Cousson, linux-arm-kernel
In-Reply-To: <20171215180900.3243-1-tony@atomide.com>
We want to be able to eventually allocate these dynamically with the
data for omap_hwmod_class_sysconfig coming from dts.
Note that omap_hwmod_sysc_type_smartreflex is the same as the older
omap36xx_sr_sysc_fields, so let's use the earlier omap36xx_sr_sysc_fields
instead.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/omap_hwmod.h | 6 ++++++
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 21 -------------------
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 17 +--------------
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 7 +------
arch/arm/mach-omap2/omap_hwmod_common_data.c | 31 ++++++++++++++++++++++++++++
5 files changed, 39 insertions(+), 43 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -40,6 +40,12 @@ struct omap_device;
extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
+extern struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields;
+extern struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields;
+extern struct omap_hwmod_sysc_fields omap3_sham_sysc_fields;
+extern struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields;
+extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp;
+extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs;
/*
* OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1190,10 +1190,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
};
/* SR common */
-static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
- .clkact_shift = 20,
-};
-
static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
.sysc_offs = 0x24,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
@@ -1206,11 +1202,6 @@ static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
.rev = 1,
};
-static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
- .sidle_shift = 24,
- .enwkup_shift = 26,
-};
-
static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
.sysc_offs = 0x38,
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
@@ -2731,12 +2722,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
};
/* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
-static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
- .sidle_shift = 4,
- .srst_shift = 1,
- .autoidle_shift = 0,
-};
-
static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
.rev_offs = 0x5c,
.sysc_offs = 0x60,
@@ -2777,12 +2762,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
};
/* l4_core -> AES */
-static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
- .sidle_shift = 6,
- .srst_shift = 1,
- .autoidle_shift = 0,
-};
-
static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
.rev_offs = 0x44,
.sysc_offs = 0x48,
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1658,10 +1658,6 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
*/
/* The IP is not compliant to type1 / type2 scheme */
-static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
- .sidle_shift = 0,
-};
-
static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
.sysc_offs = 0x0004,
.sysc_flags = SYSC_HAS_SIDLEMODE,
@@ -2403,17 +2399,12 @@ static struct omap_hwmod omap44xx_slimbus2_hwmod = {
*/
/* The IP is not compliant to type1 / type2 scheme */
-static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
- .sidle_shift = 24,
- .enwkup_shift = 26,
-};
-
static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
.sysc_offs = 0x0038,
.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
+ .sysc_fields = &omap36xx_sr_sysc_fields,
};
static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
@@ -2844,12 +2835,6 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
*/
/* The IP is not compliant to type1 / type2 scheme */
-static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
- .midle_shift = 4,
- .sidle_shift = 2,
- .srst_shift = 1,
-};
-
static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0210,
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -2055,17 +2055,12 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
*/
/* The IP is not compliant to type1 / type2 scheme */
-static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
- .sidle_shift = 24,
- .enwkup_shift = 26,
-};
-
static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
.sysc_offs = 0x0038,
.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
+ .sysc_fields = &omap36xx_sr_sysc_fields,
};
static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
@@ -63,3 +63,34 @@ struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
.manager_count = 2,
.has_framedonetv_irq = 0
};
+
+struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
+ .clkact_shift = 20,
+};
+
+struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
+ .sidle_shift = 24,
+ .enwkup_shift = 26,
+};
+
+struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
+ .sidle_shift = 4,
+ .srst_shift = 1,
+ .autoidle_shift = 0,
+};
+
+struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
+ .sidle_shift = 6,
+ .srst_shift = 1,
+ .autoidle_shift = 0,
+};
+
+struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
+ .sidle_shift = 0,
+};
+
+struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
+ .midle_shift = 4,
+ .sidle_shift = 2,
+ .srst_shift = 1,
+};
--
2.15.0
^ permalink raw reply
* [PATCH 2/9] ARM: dts: Add generic ti, sysc compatible in addition to the custom ones
From: Tony Lindgren @ 2017-12-15 18:08 UTC (permalink / raw)
To: linux-omap
Cc: Nishanth Menon, devicetree, Paul Walmsley, Dave Gerlach,
linux-kernel, Tero Kristo, Benoît Cousson, linux-arm-kernel
In-Reply-To: <20171215180900.3243-1-tony@atomide.com>
Otherwise we cannot use generic OF_DEV_AUXDATA match without listing
all the compatibles separately for OF_DEV_AUXDATA. Let's also update the
binding accordingly.
Let's also fix omap4.dtsi to use "ti,sysc-omap4-sr" compatible as we
have documented in the binding. This was not noticed earlier as we're
still probing SmartReflex driver with platform data.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
Documentation/devicetree/bindings/bus/ti-sysc.txt | 1 +
arch/arm/boot/dts/dra7.dtsi | 4 ++--
arch/arm/boot/dts/omap4.dtsi | 20 ++++++++++----------
3 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt
--- a/Documentation/devicetree/bindings/bus/ti-sysc.txt
+++ b/Documentation/devicetree/bindings/bus/ti-sysc.txt
@@ -19,6 +19,7 @@ Required standard properties:
- compatible shall be one of the following generic types:
+ "ti,sysc"
"ti,sysc-omap2"
"ti,sysc-omap4"
"ti,sysc-omap4-simple"
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1498,7 +1498,7 @@
};
target-module@4a0dd000 {
- compatible = "ti,sysc-omap4-sr";
+ compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_core";
reg = <0x4a0dd000 0x4>,
<0x4a0dd008 0x4>;
@@ -1511,7 +1511,7 @@
};
target-module@4a0d9000 {
- compatible = "ti,sysc-omap4-sr";
+ compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_mpu";
reg = <0x4a0d9000 0x4>,
<0x4a0d9008 0x4>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -383,7 +383,7 @@
};
target-module@48076000 {
- compatible = "ti,sysc-omap4";
+ compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "slimbus2";
reg = <0x48076000 0x4>,
<0x48076010 0x4>;
@@ -456,7 +456,7 @@
};
target-module@4a0db000 {
- compatible = "ti,sysc-sr";
+ compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_iva";
reg = <0x4a0db000 0x4>,
<0x4a0db008 0x4>;
@@ -473,7 +473,7 @@
};
target-module@4a0dd000 {
- compatible = "ti,sysc-sr";
+ compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_core";
reg = <0x4a0dd000 0x4>,
<0x4a0dd008 0x4>;
@@ -490,7 +490,7 @@
};
target-module@4a0d9000 {
- compatible = "ti,sysc-sr";
+ compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_mpu";
reg = <0x4a0d9000 0x4>,
<0x4a0d9008 0x4>;
@@ -710,7 +710,7 @@
};
target-module@52000000 {
- compatible = "ti,sysc-omap4";
+ compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "iss";
reg = <0x52000000 0x4>,
<0x52000010 0x4>;
@@ -817,7 +817,7 @@
};
target-module@40128000 {
- compatible = "ti,sysc-mcasp";
+ compatible = "ti,sysc-mcasp", "ti,sysc";
ti,hwmods = "mcasp";
reg = <0x40128004 0x4>;
reg-names = "sysc";
@@ -835,7 +835,7 @@
};
target-module@4012c000 {
- compatible = "ti,sysc-omap4";
+ compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "slimbus1";
reg = <0x4012c000 0x4>,
<0x4012c010 0x4>;
@@ -849,7 +849,7 @@
};
target-module@401f1000 {
- compatible = "ti,sysc-omap4";
+ compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "aess";
reg = <0x401f1000 0x4>,
<0x401f1010 0x4>;
@@ -955,7 +955,7 @@
};
target-module@4a10a000 {
- compatible = "ti,sysc-omap4";
+ compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "fdif";
reg = <0x4a10a000 0x4>,
<0x4a10a010 0x4>;
@@ -1183,7 +1183,7 @@
};
target-module@56000000 {
- compatible = "ti,sysc-omap4";
+ compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "gpu";
reg = <0x5601fc00 0x4>,
<0x5601fc10 0x4>;
--
2.15.0
^ permalink raw reply
* [PATCH 1/9] dt-bindings: ti-sysc: Update binding for timers and capabilities
From: Tony Lindgren @ 2017-12-15 18:08 UTC (permalink / raw)
To: linux-omap
Cc: Benoît Cousson, Dave Gerlach, Nishanth Menon, Paul Walmsley,
Tero Kristo, linux-kernel, linux-arm-kernel, devicetree,
Laurent Pinchart, Liam Girdwood, Mark Brown, Mark Rutland,
Mauro Carvalho Chehab, Matthijs van Duin, Peter Ujfalusi,
Sakari Ailus, Suman Anna, Tomi Valkeinen
In-Reply-To: <20171215180900.3243-1-tony@atomide.com>
The ti-sysc binding does not yet describe the capabilities of the
interconnect target module. So to make the ti-sysc binding usable
for configuring the interconnect target module, we need to add few
more properties:
1. To detect between omap2 and omap4 timers, let's add compatibles
for them for "ti,sysc-omap2-timer" and,sysc-omap4-timer". This
makes it easier to pick up the already initialized system timers
later on
2. Let's add "ti,sysc-mask" for a mask of features supported by the
interconnect target module. This describes what we have available
in the various SYSCONFIG registers
3. Let's add "ti,sysc-midle" and "ti,sysc-sidle" lists for the master
and slave idle modes supported by the interconnect target module.
These describe the values available for MIDLE and SIDLE bits in
the SYSCONFIG registers
4. Some interconnect target modules need a short delay after reset
before they can be accessed, let's use "ti,sysc-delay-us" for
that
5. Let's add "ti,syss-mask" bit to describe the optional SYSSTATUS
register bits for reset done bits
6. Let's support the two existing custom quirk properties already
listed in Documentation/devicetree/bindings/arm/omap/omap.txt for
"ti,no-reset-on-init" and "ti,no-idle-on-init"
7. And finally, let's add a header for the binding for the dts
files and the driver to use
Cc: Benoît Cousson <bcousson@baylibre.com>
Cc: Dave Gerlach <d-gerlach@ti.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Sakari Ailus <sakari.ailus@iki.fi>
Cc: Suman Anna <s-anna@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
Documentation/devicetree/bindings/bus/ti-sysc.txt | 36 +++++++++++++++++++++++
include/dt-bindings/bus/ti-sysc.h | 22 ++++++++++++++
2 files changed, 58 insertions(+)
create mode 100644 include/dt-bindings/bus/ti-sysc.h
diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt
--- a/Documentation/devicetree/bindings/bus/ti-sysc.txt
+++ b/Documentation/devicetree/bindings/bus/ti-sysc.txt
@@ -26,6 +26,8 @@ Required standard properties:
or one of the following derivative types for hardware
needing special workarounds:
+ "ti,sysc-omap2-timer"
+ "ti,sysc-omap4-timer"
"ti,sysc-omap3430-sr"
"ti,sysc-omap3630-sr"
"ti,sysc-omap4-sr"
@@ -49,6 +51,26 @@ Required standard properties:
Optional properties:
+- ti,sysc-mask shall contain mask of supported register bits for the
+ SYSCONFIG register as documented in the Technical Reference
+ Manual (TRM) for the interconnect target module
+
+- ti,sysc-midle list of master idle modes supported by the interconnect
+ target module as documented in the TRM for SYSCONFIG
+ register MIDLEMODE bits
+
+- ti,sysc-sidle list of slave idle modes supported by the interconnect
+ target module as documented in the TRM for SYSCONFIG
+ register SIDLEMODE bits
+
+- ti,sysc-delay-us delay needed after OCP softreset before accssing
+ SYSCONFIG register again
+
+- ti,syss-mask optional mask of reset done status bits as described in the
+ TRM for SYSSTATUS registers, typically 1 with some devices
+ having separate reset done bits for children like OHCI and
+ EHCI
+
- clocks clock specifier for each name in the clock-names as
specified in the binding documentation for ti-clkctrl,
typically available for all interconnect targets on TI SoCs
@@ -61,6 +83,9 @@ Optional properties:
- ti,hwmods optional TI interconnect module name to use legacy
hwmod platform data
+- ti,no-reset-on-init interconnect target module should not be reset at init
+
+- ti,no-idle-on-init interconnect target module should not be idled at init
Example: Single instance of MUSB controller on omap4 using interconnect ranges
using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
@@ -74,6 +99,17 @@ using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
reg-names = "rev", "sysc", "syss";
clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
clock-names = "fck";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2b000 0x1000>;
diff --git a/include/dt-bindings/bus/ti-sysc.h b/include/dt-bindings/bus/ti-sysc.h
new file mode 100644
--- /dev/null
+++ b/include/dt-bindings/bus/ti-sysc.h
@@ -0,0 +1,22 @@
+/* TI sysc interconnect target module defines */
+
+/* Generic sysc found on omap2 and later, also known as type1 */
+#define SYSC_OMAP2_CLOCKACTIVITY (3 << 8)
+#define SYSC_OMAP2_EMUFREE (1 << 5)
+#define SYSC_OMAP2_ENAWAKEUP (1 << 2)
+#define SYSC_OMAP2_SOFTRESET (1 << 1)
+#define SYSC_OMAP2_AUTOIDLE (1 << 0)
+
+/* Generic sysc found on omap4 and later, also known as type2 */
+#define SYSC_OMAP4_DMADISABLE (1 << 16)
+#define SYSC_OMAP4_FREEEMU (1 << 1) /* Also known as EMUFREE */
+#define SYSC_OMAP4_SOFTRESET (1 << 0)
+
+/* SmartReflex sysc found on 36xx and later */
+#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26)
+
+/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */
+#define SYSC_IDLE_FORCE 0
+#define SYSC_IDLE_NO 1
+#define SYSC_IDLE_SMART 2
+#define SYSC_IDLE_SMART_WKUP 3
--
2.15.0
^ permalink raw reply
* [PATCH 0/9] Update ti-sysc driver to use dts for capabilities
From: Tony Lindgren @ 2017-12-15 18:08 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: Benoît Cousson, Dave Gerlach, Nishanth Menon, Paul Walmsley,
Tero Kristo, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Hi all,
Here are patches for review to update ti-sysc binding and driver to
get interconnect target module capabilities from device tree.
After this series I'll be posting another series to dynamically
allocate struct omap_hwmod_class_sysconfig based on device tree
data instead of the current platform data.
These patches are against v4.15-rc series with the last patch
depending on the clkctrl nodes in Linux next.
Regards,
Tony
Tony Lindgren (9):
dt-bindings: ti-sysc: Update binding for timers and capabilities
ARM: dts: Add generic ti,sysc compatible in addition to the custom
ones
ARM: OMAP2+: Move all omap_hwmod_sysc_fields to
omap_hwmod_common_data.c
bus: ti-sysc: Make omap_hwmod_sysc_fields into sysc_regbits platform
data
bus: ti-sysc: Add register bits for interconnect target modules
bus: ti-sysc: Detect i2c interconnect target module based on register
layout
bus: ti-sysc: Handle module quirks based dts configuration
bus: ti-sysc: Add parsing of module capabilities
ARM: dts: Update ti-sysc data for existing users
Documentation/devicetree/bindings/bus/ti-sysc.txt | 37 ++
arch/arm/boot/dts/dra7.dtsi | 30 +-
arch/arm/boot/dts/omap4.dtsi | 94 ++++-
arch/arm/mach-omap2/omap_hwmod.c | 2 +
arch/arm/mach-omap2/omap_hwmod.h | 34 +-
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 21 -
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 17 +-
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 7 +-
arch/arm/mach-omap2/omap_hwmod_common_data.c | 40 +-
drivers/bus/ti-sysc.c | 485 ++++++++++++++++++++--
include/dt-bindings/bus/ti-sysc.h | 22 +
include/linux/platform_data/ti-sysc.h | 86 ++++
12 files changed, 758 insertions(+), 117 deletions(-)
create mode 100644 include/dt-bindings/bus/ti-sysc.h
create mode 100644 include/linux/platform_data/ti-sysc.h
--
2.15.0
--
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^ permalink raw reply
* Re: [PATCH net-next v6 2/2] net: ethernet: socionext: add AVE ethernet driver
From: David Miller @ 2017-12-15 17:57 UTC (permalink / raw)
To: hayashi.kunihiko-uWyLwvC0a2jby3iVrkZq2A
Cc: netdev-u79uwXL29TY76Z2rM5mHXA, andrew-g2DYL2Zd6BY,
f.fainelli-Re5JQEeQqe8AvxtiuMwx3w, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A,
masami.hiramatsu-QSEj5FYQhm4dnm+yROfE0A,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <1513245910-15961-3-git-send-email-hayashi.kunihiko-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
From: Kunihiko Hayashi <hayashi.kunihiko-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
Date: Thu, 14 Dec 2017 19:05:10 +0900
> +static void ave_desc_write(struct net_device *ndev, enum desc_id id,
> + int entry, int offset, u32 val)
> +{
> + struct ave_private *priv = netdev_priv(ndev);
> + u32 addr = (id == AVE_DESCID_TX) ? priv->tx.daddr : priv->rx.daddr;
Please always order local variables from longest to shortest line.
Audit your entire submission for this issue, thank you.
> + ret = register_netdev(ndev);
> + if (ret) {
> + dev_err(dev, "failed to register netdevice\n");
> + goto out_del_napi;
> + }
> +
> + platform_set_drvdata(pdev, ndev);
You must make all software state settings before reigster_netdev() is
invoked.
At the exact moment you call register_netdev(), your device can be
brought up, interrupts processed, PHY state changes made, etc.
So you must put this platform_set_drvdata() before the
register_netdev() call.
Generally speaking, register_netdev() must always be the last state
modification done by your probe routine.
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