* Re: [PATCH 3/3] arm64: dts: meson-axg: add new reset DT node
From: Kevin Hilman @ 2017-12-16 0:17 UTC (permalink / raw)
To: Neil Armstrong
Cc: Yixun Lan, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
Philipp Zabel, Jerome Brunet, Carlo Caione,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <04b96767-2412-7242-780c-f3e1e610a62b-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> writes:
> On 10/11/2017 09:46, Yixun Lan wrote:
>> Add reset DT node for Amlogic's Meson-AXG SoC.
>>
>> Signed-off-by: Yixun Lan <yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>
>> ---
>> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index e0fb860e12c5..65945c6c8b65 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -123,6 +123,12 @@
>> #size-cells = <2>;
>> ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
>>
>> + reset: reset-controller@1004 {
>> + compatible = "amlogic,meson-axg-reset";
>> + reg = <0x0 0x01004 0x0 0x9c>;
>> + #reset-cells = <1>;
>> + };
>> +
>> uart_A: serial@24000 {
>> compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
>> reg = <0x0 0x24000 0x0 0x14>;
>>
>
> Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Applied to v4.16/dt64,
Kevin
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^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: chosen: Add clocksource and clockevent selection
From: Grygorii Strashko @ 2017-12-16 1:57 UTC (permalink / raw)
To: Alexandre Belloni, Rob Herring, Daniel Lezcano
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Thomas Gleixner,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Boris Brezillon
In-Reply-To: <20171213185313.20017-2-alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On 12/13/2017 12:53 PM, Alexandre Belloni wrote:
> The clocksource and clockevent timer are probed early in the boot process.
> At that time it is difficult for linux to know whether a particular timer
> can be used as the clocksource or the clockevent or by another driver,
> especially when they are all identical or have similar features.
>
> Until now, multiple strategies have been used to solve that:
> - use Kconfig option as MXC_USE_EPIT or ATMEL_TCB_CLKSRC_BLOCK
> - use a kernel parameter as the "clocksource" early_param in mach-omap2
> - registering the first seen timer as a clockevent and the second one as
> a clocksource as in rk_timer_init or dw_apb_timer_init
>
> Add a linux,clocksource and a linux,clockevent node in chosen with a timer
> property pointing to the timer to use. Other properties, like the targeted
> precision may be added later.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> ---
> Documentation/devicetree/bindings/chosen.txt | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/chosen.txt b/Documentation/devicetree/bindings/chosen.txt
> index e3b13ea7d2ae..c7ee3ecb5276 100644
> --- a/Documentation/devicetree/bindings/chosen.txt
> +++ b/Documentation/devicetree/bindings/chosen.txt
> @@ -120,3 +120,23 @@ e.g.
> While this property does not represent a real hardware, the address
> and the size are expressed in #address-cells and #size-cells,
> respectively, of the root node.
> +
> +linux,clocksource and linux,clockevent
> +--------------------------------------
> +
> +Those nodes have a timer property. This property is a phandle to the timer to be
> +chosen as the clocksource or clockevent. This is only useful when the platform
> +has multiple identical timers and it is not possible to let linux make the
> +correct choice.
> +
> +/ {
> + chosen {
> + linux,clocksource {
> + timer = <&timer0>;
> + };
> +
> + linux,clockevent {
> + timer = <&timer1>;
> + };
> + };
> +};
>
It'd be nice if smth. like this will actually happen, as on some OMAP
platforms can be up to 3-4 alternatives for each clocksource/clockevent and
different combination need to be selected depending on SoC and platform
(and sometime - use case) which is pain in multi-platform environment now.
But more important note from my side is clocksource and clockevent selections seems
not enough :( There are also sched clock (sched_clock_register()) and delay_timer
(register_current_timer_delay() at least on ARM).
Both above can't be unregistered (at least last time I've checked).
--
regards,
-grygorii
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^ permalink raw reply
* [RFC 0/5] IR support for A83T - sunxi-ir driver update
From: Philipp Rossak @ 2017-12-16 2:49 UTC (permalink / raw)
To: mchehab-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8,
maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, wens-jdAy2FN1RRM,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, sean-hENCXIMQXOg,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, andi.shyti-Sze3O3UU22JBDgjK7y7TUQ
Cc: linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
This patch series adds support for the sunxi A83T ir module and enhances the sunxi-ir driver.
Right now the base clock frequency for the ir driver is a hard coded define and is set to 8 MHz.
This works for the most common ir receivers. On the Sinovoip Bananapi M3 the ir receiver needs,
a 3 MHz base clock frequency to work without problems with this driver (like in the legacy kernel).
To fix this issue I reworked the driver that this value could be set over the devicetree.
About 37 devices would have a devicetree change if this patch series would be applied.
Therfore I would like to ask you to give me some feedback about the patch series, before I finialize it.
Thanks in advance!
Philipp
Philipp Rossak (5):
[media] rc: update sunxi-ir driver to get base frequency from
devicetree
[media] dt: bindings: Update binding documentation for sunxi IR
controller
ARM: dts: sun8i: a83t: Add the ir pin for the A83T
ARM: dts: sun8i: a83t: Add support for the ir interface
ARM: dts: sun8i: a83t: bananapi-m3: Enable IR controller
Documentation/devicetree/bindings/media/sunxi-ir.txt | 14 ++++++++------
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++++++
arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +++++++++++++++
drivers/media/rc/sunxi-cir.c | 20 +++++++++++---------
4 files changed, 41 insertions(+), 15 deletions(-)
--
2.11.0
^ permalink raw reply
* [RFC 1/5] [media] rc: update sunxi-ir driver to get base frequency from devicetree
From: Philipp Rossak @ 2017-12-16 2:49 UTC (permalink / raw)
To: mchehab-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8,
maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, wens-jdAy2FN1RRM,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, sean-hENCXIMQXOg,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, andi.shyti-Sze3O3UU22JBDgjK7y7TUQ
Cc: linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20171216024914.7550-1-embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
This patch updates the sunxi-ir driver to set the ir base clock from
devicetree.
This is neccessary since there are different ir recievers on the
market, that operate with different frequencys. So this value needs to
be set depending on the attached receiver.
Signed-off-by: Philipp Rossak <embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/media/rc/sunxi-cir.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 97f367b446c4..55b53d6463e9 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -72,12 +72,6 @@
/* CIR_REG register idle threshold */
#define REG_CIR_ITHR(val) (((val) << 8) & (GENMASK(15, 8)))
-/* Required frequency for IR0 or IR1 clock in CIR mode */
-#define SUNXI_IR_BASE_CLK 8000000
-/* Frequency after IR internal divider */
-#define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64)
-/* Sample period in ns */
-#define SUNXI_IR_SAMPLE (1000000000ul / SUNXI_IR_CLK)
/* Noise threshold in samples */
#define SUNXI_IR_RXNOISE 1
/* Idle Threshold in samples */
@@ -122,7 +116,7 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
/* for each bit in fifo */
dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
rawir.pulse = (dt & 0x80) != 0;
- rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
+ rawir.duration = ((dt & 0x7f) + 1) * ir->rc->rx_resolution;
ir_raw_event_store_with_filter(ir->rc, &rawir);
}
}
@@ -148,6 +142,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
struct device_node *dn = dev->of_node;
struct resource *res;
struct sunxi_ir *ir;
+ u32 b_clk_freq;
ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
if (!ir)
@@ -172,6 +167,12 @@ static int sunxi_ir_probe(struct platform_device *pdev)
return PTR_ERR(ir->clk);
}
+ /* Required frequency for IR0 or IR1 clock in CIR mode */
+ if (of_property_read_u32(dn, "base-clk-frequency", &b_clk_freq)) {
+ dev_err(dev, "failed to get ir base clock frequency.\n");
+ return -ENODATA;
+ }
+
/* Reset (optional) */
ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(ir->rst))
@@ -180,7 +181,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
if (ret)
return ret;
- ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
+ ret = clk_set_rate(ir->clk, b_clk_freq);
if (ret) {
dev_err(dev, "set ir base clock failed!\n");
goto exit_reset_assert;
@@ -225,7 +226,8 @@ static int sunxi_ir_probe(struct platform_device *pdev)
ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
ir->rc->dev.parent = dev;
ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
- ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
+ /* Frequency after IR internal divider with sample period in ns */
+ ir->rc->rx_resolution = (1000000000ul / (b_clk_freq / 64));
ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
ir->rc->driver_name = SUNXI_IR_DEV;
--
2.11.0
^ permalink raw reply related
* [RFC 2/5] [media] dt: bindings: Update binding documentation for sunxi IR controller
From: Philipp Rossak @ 2017-12-16 2:49 UTC (permalink / raw)
To: mchehab-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8,
maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, wens-jdAy2FN1RRM,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, sean-hENCXIMQXOg,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, andi.shyti-Sze3O3UU22JBDgjK7y7TUQ
Cc: linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20171216024914.7550-1-embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new requiered property for the base clock frequency.
Signed-off-by: Philipp Rossak <embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 91648c569b1e..5f4960c61245 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -1,12 +1,13 @@
Device-Tree bindings for SUNXI IR controller found in sunXi SoC family
Required properties:
-- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir"
-- clocks : list of clock specifiers, corresponding to
- entries in clock-names property;
-- clock-names : should contain "apb" and "ir" entries;
-- interrupts : should contain IR IRQ number;
-- reg : should contain IO map address for IR.
+- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir"
+- clocks : list of clock specifiers, corresponding to
+ entries in clock-names property;
+- clock-names : should contain "apb" and "ir" entries;
+- interrupts : should contain IR IRQ number;
+- reg : should contain IO map address for IR.
+- base-clk-frequency : should contain the base clock frequency
Optional properties:
- linux,rc-map-name: see rc.txt file in the same directory.
@@ -21,5 +22,6 @@ ir0: ir@1c21800 {
resets = <&apb0_rst 1>;
interrupts = <0 5 1>;
reg = <0x01C21800 0x40>;
+ base-clk-frequency = <8000000>;
linux,rc-map-name = "rc-rc6-mce";
};
--
2.11.0
^ permalink raw reply related
* [RFC 3/5] ARM: dts: sun8i: a83t: Add the ir pin for the A83T
From: Philipp Rossak @ 2017-12-16 2:49 UTC (permalink / raw)
To: mchehab-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8,
maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, wens-jdAy2FN1RRM,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, sean-hENCXIMQXOg,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, andi.shyti-Sze3O3UU22JBDgjK7y7TUQ
Cc: linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20171216024914.7550-1-embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
The CIR Pin of the A83T is located at PL12
Signed-off-by: Philipp Rossak <embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 19acae1b4089..5edb645b506f 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -488,6 +488,11 @@
drive-strength = <20>;
bias-pull-up;
};
+
+ ir_pins_a: ir@0 {
+ pins = "PL12";
+ function = "s_cir_rx";
+ };
};
r_rsb: rsb@1f03400 {
--
2.11.0
^ permalink raw reply related
* [RFC 4/5] ARM: dts: sun8i: a83t: Add support for the ir interface
From: Philipp Rossak @ 2017-12-16 2:49 UTC (permalink / raw)
To: mchehab-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8,
maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, wens-jdAy2FN1RRM,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, sean-hENCXIMQXOg,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, andi.shyti-Sze3O3UU22JBDgjK7y7TUQ
Cc: linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20171216024914.7550-1-embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
The ir interface is like the H3 at 0x01f02000 located and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 5edb645b506f..5dbf2f0891c1 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -470,6 +470,16 @@
#reset-cells = <1>;
};
+ ir: ir@01f02000 {
+ compatible = "allwinner,sun5i-a13-ir";
+ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <&r_ccu RST_APB0_IR>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x01f02000 0x40>;
+ status = "disabled";
+ };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
--
2.11.0
^ permalink raw reply related
* [RFC 5/5] ARM: dts: sun8i: a83t: bananapi-m3: Enable IR controller
From: Philipp Rossak @ 2017-12-16 2:49 UTC (permalink / raw)
To: mchehab-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8,
maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, wens-jdAy2FN1RRM,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, sean-hENCXIMQXOg,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, andi.shyti-Sze3O3UU22JBDgjK7y7TUQ
Cc: linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20171216024914.7550-1-embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Other than the other IR receivers this one needs a base clock frequency
of 3000000 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++++++
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index c606af3dbfed..2c92c501cd59 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -88,6 +88,13 @@
/* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */
};
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ base-clk-frequency = <3000000>;
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 5dbf2f0891c1..679ce3a66b4b 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -470,7 +470,7 @@
#reset-cells = <1>;
};
- ir: ir@01f02000 {
+ ir: ir@1f02000 {
compatible = "allwinner,sun5i-a13-ir";
clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
clock-names = "apb", "ir";
--
2.11.0
^ permalink raw reply related
* Re: [PATCH v4 0/2] dt: add pinctrl driver for Meson-AXG SoC
From: Yixun Lan @ 2017-12-16 3:27 UTC (permalink / raw)
To: Kevin Hilman
Cc: yixun.lan, linux-amlogic, Rob Herring, Mark Rutland,
Linus Walleij, Neil Armstrong, Jerome Brunet, Carlo Caione,
Xingyu Chen, devicetree, linux-gpio, linux-arm-kernel,
linux-kernel
In-Reply-To: <7ha7yj93hu.fsf@baylibre.com>
On 12/16/2017 03:48 AM, Kevin Hilman wrote:
> Yixun Lan <yixun.lan@amlogic.com> writes:
>
>> This is DT part patchset for adding pinctrl support for
>> the Amlogic's Meson-AXG SoC.
>>
>> Changes since v3 at [3]
>> -- rebase to khilman's v4.16/dt64 branch and re-send
>> -- add Rob's Ack
>>
>> Changes since v2 at [2]:
>> -- Resend this patch series due to fail to send patch [2/2]
>>
>> Changes since v1 at [1]:
>> -- Separate DT part patches
>> -- Add Neil Armstrong's Ack
>>
>> [3]
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005392.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005393.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005394.html
>>
>> [2]
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005390.html
>>
>> [1]
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005270.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005271.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005272.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005273.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005274.html
>>
>> Xingyu Chen (2):
>> documentation: Add compatibles for Amlogic Meson AXG pin controllers
>> ARM64: dts: meson-axg: add pinctrl DT info for Meson-AXG SoC
>
> Applied both to v4.14/dt64
>
> Normally, the documentation patch should go with the driver, but since
> Linus has already merged the driver, this time I'll take it with the DT
> itself.
>
Hi Kevin
sorry, I just checked Linus' pinctrl tree - the for-next branch, the
documentation patch is already taken there. so probably you could drop
it here?
Yixun
^ permalink raw reply
* Re: [PATCH v3 1/2] ARM64: dts: meson-axg: add ethernet mac controller
From: Yixun Lan @ 2017-12-16 3:38 UTC (permalink / raw)
To: Kevin Hilman
Cc: yixun.lan, devicetree, Neil Armstrong, Jerome Brunet,
Giuseppe Cavallaro, Alexandre Torgue, Carlo Caione, linux-amlogic,
linux-arm-kernel, linux-kernel, netdev
In-Reply-To: <7ho9mz94dg.fsf@baylibre.com>
HI Kevin
On 12/16/2017 03:29 AM, Kevin Hilman wrote:
> Yixun Lan <yixun.lan@amlogic.com> writes:
>
>> Add DT info for the stmmac ethernet MAC which found in
>> the Amlogic's Meson-AXG SoC, also describe the ethernet
>> pinctrl & clock information here.
>>
>> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>
> This patch does not apply, and dependencies are not described.
>
>> ---
>> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 54 ++++++++++++++++++++++++++++++
>> 1 file changed, 54 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index d356ce74ad89..94c4972222b7 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -7,6 +7,7 @@
>> #include <dt-bindings/gpio/gpio.h>
>> #include <dt-bindings/interrupt-controller/irq.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/axg-clkc.h>
>>
>> / {
>> compatible = "amlogic,meson-axg";
>> @@ -148,6 +149,19 @@
>> #address-cells = <0>;
>> };
>>
>> + ethmac: ethernet@ff3f0000 {
>> + compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
>> + reg = <0x0 0xff3f0000 0x0 0x10000
>> + 0x0 0xff634540 0x0 0x8>;
>> + interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
>> + interrupt-names = "macirq";
>> + clocks = <&clkc CLKID_ETH>,
>> + <&clkc CLKID_FCLK_DIV2>,
>> + <&clkc CLKID_MPLL2>;
>> + clock-names = "stmmaceth", "clkin0", "clkin1";
>> + status = "disabled";
>> + };
>> +
>> hiubus: bus@ff63c000 {
>> compatible = "simple-bus";
>> reg = <0x0 0xff63c000 0x0 0x1c00>;
>
> Based on the hiubus node, presumably this depends on the patch from the
> clock series.
>
yes, it depend on clock, also the pinctrl patch
>> @@ -194,6 +208,46 @@
>> #gpio-cells = <2>;
>> gpio-ranges = <&pinctrl_periphs 0 0 86>;
>> };
>
> I'm not sure where this part is coming from, but it causes the rest of
> it to not apply.
>
> Please be sure to describe all dependencies.
>
.
exactly, it depend on pinctrl
actually, once you apply the clock & pinctrl DT patch, this one should
go fine. I will send another v4 which base on your recent v4.16/dt64
branch for your convenience.
Yixun
^ permalink raw reply
* [PATCH v4 0/2] Add ethernet support for Meson-AXG SoC
From: Yixun Lan @ 2017-12-16 3:55 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA, Kevin Hilman
Cc: Neil Armstrong, Jerome Brunet, Giuseppe Cavallaro,
Alexandre Torgue, Carlo Caione, Yixun Lan,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
netdev-u79uwXL29TY76Z2rM5mHXA
This series try to add support for the ethernet MAC controller
found in Meson-AXG SoC, and also enable it in the S400 board.
Hi Kevin:
You still need to at least merge the clock patch[3] in order to
compile the DTS, or just merge the tag from meson-clock's tree[6]
- the tag is 'meson-clk-for-v4.16-2', since the clock part already
taken there.
Changes in v4 since [5]:
- rebase to kevin's v4.16/dt64
- fix order
Changes in v3 since [4]:
- put clock DT info in soc.dtsi
- separate DT for 'add support for the controller' vs 'enable in board'
Changes in v2 since [1]:
- rebase to kevin's v4.16/dt64 branch
- add Neil's Reviewed-by
- move clock info to board.dts instead of in soc.dtsi
- drop "meson-axg-dwmac" compatible string, since we didn't use this
we could re-add it later when we really need.
- note: to make ethernet work properly,it depend on clock & pinctrl[2],
to compile the DTS, the patch [3] is required.
the code part will be taken via clock & pinctrl subsystem tree.
[5]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005783.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005784.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005785.html
[4]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005768.html
[1]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005301.html
[2]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005735.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005694.html
[3]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005738.html
[6] git://github.com/BayLibre/clk-meson.git
Yixun Lan (2):
ARM64: dts: meson-axg: add ethernet mac controller
ARM64: dts: meson-axg: enable ethernet for A113D S400 board
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 ++++
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 54 ++++++++++++++++++++++++++
2 files changed, 61 insertions(+)
--
2.15.1
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^ permalink raw reply
* [PATCH v4 1/2] ARM64: dts: meson-axg: add ethernet mac controller
From: Yixun Lan @ 2017-12-16 3:55 UTC (permalink / raw)
To: devicetree, Kevin Hilman
Cc: Neil Armstrong, Jerome Brunet, Giuseppe Cavallaro,
Alexandre Torgue, Carlo Caione, Yixun Lan, linux-amlogic,
linux-arm-kernel, linux-kernel, netdev
In-Reply-To: <20171216035527.96952-1-yixun.lan@amlogic.com>
Add DT info for the stmmac ethernet MAC which found in
the Amlogic's Meson-AXG SoC, also describe the ethernet
pinctrl & clock information here.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 54 ++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index d288d4724ae3..dea1bc31b4de 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/axg-clkc.h>
/ {
compatible = "amlogic,meson-axg";
@@ -155,6 +156,19 @@
};
};
+ ethmac: ethernet@ff3f0000 {
+ compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
+ reg = <0x0 0xff3f0000 0x0 0x10000
+ 0x0 0xff634540 0x0 0x8>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "macirq";
+ clocks = <&clkc CLKID_ETH>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_MPLL2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1";
+ status = "disabled";
+ };
+
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
reg = <0x0 0xffc01000 0 0x1000>,
@@ -215,6 +229,46 @@
gpio-ranges = <&pinctrl_periphs 0 0 86>;
};
+ eth_rgmii_x_pins: eth-x-rgmii {
+ mux {
+ groups = "eth_mdio_x",
+ "eth_mdc_x",
+ "eth_rgmii_rx_clk_x",
+ "eth_rx_dv_x",
+ "eth_rxd0_x",
+ "eth_rxd1_x",
+ "eth_rxd2_rgmii",
+ "eth_rxd3_rgmii",
+ "eth_rgmii_tx_clk",
+ "eth_txen_x",
+ "eth_txd0_x",
+ "eth_txd1_x",
+ "eth_txd2_rgmii",
+ "eth_txd3_rgmii";
+ function = "eth";
+ };
+ };
+
+ eth_rgmii_y_pins: eth-y-rgmii {
+ mux {
+ groups = "eth_mdio_y",
+ "eth_mdc_y",
+ "eth_rgmii_rx_clk_y",
+ "eth_rx_dv_y",
+ "eth_rxd0_y",
+ "eth_rxd1_y",
+ "eth_rxd2_rgmii",
+ "eth_rxd3_rgmii",
+ "eth_rgmii_tx_clk",
+ "eth_txen_y",
+ "eth_txd0_y",
+ "eth_txd1_y",
+ "eth_txd2_rgmii",
+ "eth_txd3_rgmii";
+ function = "eth";
+ };
+ };
+
pwm_a_a_pins: pwm_a_a {
mux {
groups = "pwm_a_a";
--
2.15.1
^ permalink raw reply related
* [PATCH v4 2/2] ARM64: dts: meson-axg: enable ethernet for A113D S400 board
From: Yixun Lan @ 2017-12-16 3:55 UTC (permalink / raw)
To: devicetree, Kevin Hilman
Cc: Neil Armstrong, Jerome Brunet, Giuseppe Cavallaro,
Alexandre Torgue, Carlo Caione, Yixun Lan, linux-amlogic,
linux-arm-kernel, linux-kernel, netdev
In-Reply-To: <20171216035527.96952-1-yixun.lan@amlogic.com>
This is tested in the S400 dev board which use a RTL8211F PHY,
and the pins connect to the 'eth_rgmii_y_pins' group.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..8932654f5090 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -17,6 +17,13 @@
};
};
+ðmac {
+ status = "okay";
+ phy-mode = "rgmii";
+ pinctrl-0 = <ð_rgmii_y_pins>;
+ pinctrl-names = "default";
+};
+
&uart_AO {
status = "okay";
};
--
2.15.1
^ permalink raw reply related
* Re: [PATCH v2 04/10] arm64: dts: qcom: msm8916: drop unused board-specific nodes
From: Bjorn Andersson @ 2017-12-16 5:12 UTC (permalink / raw)
To: Damien Riegel
Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andy Gross, David Brown,
Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
kernel-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/
In-Reply-To: <20171207151942.5805-5-damien.riegel-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/@public.gmane.org>
On Thu 07 Dec 07:19 PST 2017, Damien Riegel wrote:
> These nodes reserve and configure some pins as GPIOs. They are not
> generic pinctrls, they actually belong to board files but they are not
> used by any other node, so just drop them altogether.
>
> Signed-off-by: Damien Riegel <damien.riegel-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/@public.gmane.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Let's introduce them back into the db410c when we define a client.
Regards,
Bjorn
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^ permalink raw reply
* Re: [PATCH v2 05/10] arm64: dts: qcom: apq8016-sbc: sort nodes alphabetically
From: Bjorn Andersson @ 2017-12-16 5:17 UTC (permalink / raw)
To: Damien Riegel
Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andy Gross, David Brown,
Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
kernel-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/
In-Reply-To: <20171207151942.5805-6-damien.riegel-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/@public.gmane.org>
On Thu 07 Dec 07:19 PST 2017, Damien Riegel wrote:
> Also, it was using whitespaces for indentation on some lines, fix that
> while moving it.
>
> Signed-off-by: Damien Riegel <damien.riegel-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/@public.gmane.org>
Rather than extending single nodes like this I would prefer that we
bring in the associated pmic node, by this we avoid just having a huge
flat list of nodes. I.e. that we make this:
&pm8916_1 {
codec@f000 {
status = "okay";
clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
clock-names = "mclk";
qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
};
};
Regards,
Bjorn
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^ permalink raw reply
* Re: [PATCH v2 06/10] arm64: dts: qcom: msm8916: move pinconfs to board files
From: Bjorn Andersson @ 2017-12-16 5:18 UTC (permalink / raw)
To: Damien Riegel
Cc: linux-arm-msm, linux-soc, devicetree, linux-arm-kernel,
linux-kernel, Andy Gross, David Brown, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, kernel
In-Reply-To: <20171207151942.5805-7-damien.riegel@savoirfairelinux.com>
On Thu 07 Dec 07:19 PST 2017, Damien Riegel wrote:
> Following a suggestion from Bjorn Andersson [1], this commit moves
> electrical specifications which were defined in mms8916-pins.dtsi to
> board files, where they actually belong.
>
> Pinmuxing is kept in the platform file because there are no alternative
> pins on which all these functions could be routed, so this part is
> indeed common to all boards using this SoC.
>
> [1] https://www.spinics.net/lists/devicetree/msg201764.html
>
> Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com>
> Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
I like the move, but I would prefer that you mimic the base structure,
rather than just appending properties based on labels.
Regards,
Bjorn
^ permalink raw reply
* Re: [PATCH v2 07/10] arm64: dts: qcom: msm8916: drop remaining unused pinconfs
From: Bjorn Andersson @ 2017-12-16 5:18 UTC (permalink / raw)
To: Damien Riegel
Cc: linux-arm-msm, linux-soc, devicetree, linux-arm-kernel,
linux-kernel, Andy Gross, David Brown, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, kernel
In-Reply-To: <20171207151942.5805-8-damien.riegel@savoirfairelinux.com>
On Thu 07 Dec 07:19 PST 2017, Damien Riegel wrote:
> This commit drops pin configs that cannot be moved to board files as
> no boards use them.
>
> Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
^ permalink raw reply
* Re: [PATCH v2 08/10] arm64: dts: qcom: msm8916-pins: move sdhc2 cd node with its siblings
From: Bjorn Andersson @ 2017-12-16 5:19 UTC (permalink / raw)
To: Damien Riegel
Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andy Gross, David Brown,
Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
kernel-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/
In-Reply-To: <20171207151942.5805-9-damien.riegel-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/@public.gmane.org>
On Thu 07 Dec 07:19 PST 2017, Damien Riegel wrote:
> Nodes relative to the first sdhc node were interlaced with node of the
> second sdhc. Move sdhc2_cd_pin with its siblings to prevent that. Also
> rename the grouping node from sdhc2_cd_pin to pmx_sdc2_cd_pin, as
> "pmx_sdc" is the prefix used by other nodes.
>
> Signed-off-by: Damien Riegel <damien.riegel-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/@public.gmane.org>
Acked-by: Bjorn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Regards,
Bjorn
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^ permalink raw reply
* Re: [PATCH v2 09/10] arm64: dts: qcom: msm8916: normalize I2C and SPI nodes
From: Bjorn Andersson @ 2017-12-16 5:20 UTC (permalink / raw)
To: Damien Riegel
Cc: linux-arm-msm, linux-soc, devicetree, linux-arm-kernel,
linux-kernel, Andy Gross, David Brown, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, kernel
In-Reply-To: <20171207151942.5805-10-damien.riegel@savoirfairelinux.com>
On Thu 07 Dec 07:19 PST 2017, Damien Riegel wrote:
> The QUP core can be used either for I2C or SPI, so the same IP is mapped
> by a driver or the other. SPI bindings use a leading 0 for the start
> address and a size of 0x600, I2C bindings don't have the leading 0 and
> have a size 0x1000.
>
> To make them more similar, add the leading 0 to I2C bindings and changes
> the size to 0x500 for all of them, as this is the actual size of these
> blocks. Also align the second entry of the clocks array.
>
> Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
^ permalink raw reply
* Re: [PATCH v2 10/10] arm64: dts: qcom: msm8916: add nodes for i2c1, i2c3, i2c5
From: Bjorn Andersson @ 2017-12-16 5:23 UTC (permalink / raw)
To: Damien Riegel
Cc: linux-arm-msm, linux-soc, devicetree, linux-arm-kernel,
linux-kernel, Andy Gross, David Brown, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, kernel
In-Reply-To: <20171207151942.5805-11-damien.riegel@savoirfairelinux.com>
On Thu 07 Dec 07:19 PST 2017, Damien Riegel wrote:
> Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com>
Please move pinconf settings into the structure in
apq8016-sbc-soc-pins.dtsi (didn't see this when commenting on the
previous patch).
Apart from this, the patch looks good.
Regards,
Bjorn
> ---
> Changes in v2:
> - Reworded commit title
> - Changed size to 0x500
>
> arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 48 ++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 42 ++++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 45 ++++++++++++++++++++++++++++
> 3 files changed, 135 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
> index 53c1ddd281a4..11305015ba0b 100644
> --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
> +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
> @@ -630,6 +630,22 @@
> };
> };
>
> +&i2c1_default {
> + pinconf {
> + pins = "gpio2", "gpio3";
> + drive-strength = <16>;
> + bias-disable;
> + };
> +};
> +
> +&i2c1_sleep {
> + pinconf {
> + pins = "gpio2", "gpio3";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +};
> +
> &i2c2_default {
> pinconf {
> pins = "gpio6", "gpio7";
> @@ -646,6 +662,22 @@
> };
> };
>
> +&i2c3_default {
> + pinconf {
> + pins = "gpio10", "gpio11";
> + drive-strength = <16>;
> + bias-disable;
> + };
> +};
> +
> +&i2c3_sleep {
> + pinconf {
> + pins = "gpio10", "gpio11";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +};
> +
> &i2c4_default {
> pinconf {
> pins = "gpio14", "gpio15";
> @@ -662,6 +694,22 @@
> };
> };
>
> +&i2c5_default {
> + pinconf {
> + pins = "gpio18", "gpio19";
> + drive-strength = <16>;
> + bias-disable;
> + };
> +};
> +
> +&i2c5_sleep {
> + pinconf {
> + pins = "gpio18", "gpio19";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +};
> +
> &i2c6_default {
> pinconf {
> pins = "gpio22", "gpio23";
> diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
> index 7704ddecb6c4..44e68860fc8c 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
> @@ -152,6 +152,20 @@
> };
> };
>
> + i2c1_default: i2c1_default {
> + pinmux {
> + function = "blsp_i2c1";
> + pins = "gpio2", "gpio3";
> + };
> + };
> +
> + i2c1_sleep: i2c1_sleep {
> + pinmux {
> + function = "gpio";
> + pins = "gpio2", "gpio3";
> + };
> + };
> +
> i2c2_default: i2c2_default {
> pinmux {
> function = "blsp_i2c2";
> @@ -166,6 +180,20 @@
> };
> };
>
> + i2c3_default: i2c3_default {
> + pinmux {
> + function = "blsp_i2c3";
> + pins = "gpio10", "gpio11";
> + };
> + };
> +
> + i2c3_sleep: i2c3_sleep {
> + pinmux {
> + function = "gpio";
> + pins = "gpio10", "gpio11";
> + };
> + };
> +
> i2c4_default: i2c4_default {
> pinmux {
> function = "blsp_i2c4";
> @@ -180,6 +208,20 @@
> };
> };
>
> + i2c5_default: i2c5_default {
> + pinmux {
> + function = "blsp_i2c5";
> + pins = "gpio18", "gpio19";
> + };
> + };
> +
> + i2c5_sleep: i2c5_sleep {
> + pinmux {
> + function = "gpio";
> + pins = "gpio18", "gpio19";
> + };
> + };
> +
> i2c6_default: i2c6_default {
> pinmux {
> function = "blsp_i2c6";
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index ac440f287633..7478c7337995 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -455,6 +455,21 @@
> status = "disabled";
> };
>
> + blsp_i2c1: i2c@78b5000 {
> + compatible = "qcom,i2c-qup-v2.2.1";
> + reg = <0x078b5000 0x500>;
> + interrupts = <GIC_SPI 95 0>;
> + clocks = <&gcc GCC_BLSP1_AHB_CLK>,
> + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
> + clock-names = "iface", "core";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&i2c1_default>;
> + pinctrl-1 = <&i2c1_sleep>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> blsp_i2c2: i2c@78b6000 {
> compatible = "qcom,i2c-qup-v2.2.1";
> reg = <0x078b6000 0x500>;
> @@ -470,6 +485,21 @@
> status = "disabled";
> };
>
> + blsp_i2c3: i2c@78b7000 {
> + compatible = "qcom,i2c-qup-v2.2.1";
> + reg = <0x078b7000 0x500>;
> + interrupts = <GIC_SPI 97 0>;
> + clocks = <&gcc GCC_BLSP1_AHB_CLK>,
> + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
> + clock-names = "iface", "core";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&i2c3_default>;
> + pinctrl-1 = <&i2c3_sleep>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> blsp_i2c4: i2c@78b8000 {
> compatible = "qcom,i2c-qup-v2.2.1";
> reg = <0x078b8000 0x500>;
> @@ -485,6 +515,21 @@
> status = "disabled";
> };
>
> + blsp_i2c5: i2c@78b9000 {
> + compatible = "qcom,i2c-qup-v2.2.1";
> + reg = <0x078b9000 0x500>;
> + interrupts = <GIC_SPI 99 0>;
> + clocks = <&gcc GCC_BLSP1_AHB_CLK>,
> + <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
> + clock-names = "iface", "core";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&i2c5_default>;
> + pinctrl-1 = <&i2c5_sleep>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> blsp_i2c6: i2c@78ba000 {
> compatible = "qcom,i2c-qup-v2.2.1";
> reg = <0x078ba000 0x500>;
> --
> 2.15.0
>
^ permalink raw reply
* Re: [PATCH] dt-bindings: chosen: Document linux,initrd-{start,end}
From: Jonathan Neuschäfer @ 2017-12-16 5:41 UTC (permalink / raw)
To: Rob Herring
Cc: Jonathan Neuschäfer, devicetree-u79uwXL29TY76Z2rM5mHXA,
Mark Rutland, AKASHI Takahiro, Ard Biesheuvel, Kees Cook,
James Morse, Frank Rowand, linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171215210147.w3xqs3di2vbbvv5p@rob-hp-laptop>
[-- Attachment #1: Type: text/plain, Size: 976 bytes --]
On Fri, Dec 15, 2017 at 03:01:47PM -0600, Rob Herring wrote:
> On Sat, Dec 09, 2017 at 04:33:02PM +0100, Jonathan Neuschäfer wrote:
> > These properties have been in use for a very long time (at least since
> > 2005), but were never documented in chosen.txt.
> >
> > Signed-off-by: Jonathan Neuschäfer <j.neuschaefer-hi6Y0CQ0nG0@public.gmane.org>
> > ---
> > Documentation/devicetree/bindings/chosen.txt | 15 +++++++++++++++
> > 1 file changed, 15 insertions(+)
>
> Applied.
Thanks.
> I'm inclined to say to document these in the DT spec, but I'm assuming
> there was some reason why they weren't put into the spec (ePAPR at the
> time) originally.
I don't know about the history of this, but I think if and when these
properties were specified in DTSpec, they should get a non-linux-specific
name, such as initrd-start/initrd-end, and a compatibility fallback to
linux,initrd-* (similar to stdout-path and phandle).
Jonathan Neuschäfer
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply
* Re: [PATCH 2/8] ARM: dts: keystone*: Use a single soc0 instance
From: santosh.shilimkar-QHcLZuEGTsvQT0dZR+AlfA @ 2017-12-16 8:33 UTC (permalink / raw)
To: Nishanth Menon, Russell King, Mark Rutland, Rob Herring,
Santosh Shilimkar
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1fce818d-f1a2-818d-7db8-d15a345f4c1e-l0cyMroinI0@public.gmane.org>
On 12/15/17 5:38 AM, Nishanth Menon wrote:
> Crap.. couple of typos crept in. Apologies - Santosh, if you dont want
> to manualy change, I can rebase and repost if you like to any branch of
> your choice.
>
Just post it against for_4.16/keystone-dts
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^ permalink raw reply
* Re: [PATCH 07/25] arm: keystone: dts: Remove leading 0x and 0s from bindings notation
From: santosh.shilimkar @ 2017-12-16 8:36 UTC (permalink / raw)
To: Mathieu Malaterre, Rob Herring
Cc: Mark Rutland, devicetree, linux-kernel, Russell King,
Santosh Shilimkar, linux-arm-kernel
In-Reply-To: <20171215124638.30233-1-malat@debian.org>
On 12/15/17 4:46 AM, Mathieu Malaterre wrote:
> Improve the DTS files by removing all the leading "0x" and zeros to fix the
> following dtc warnings:
>
> Warning (unit_address_format): Node /XXX unit name should not have leading "0x"
>
> and
>
> Warning (unit_address_format): Node /XXX unit name should not have leading 0s
>
> Converted using the following command:
>
> find . -type f \( -iname *.dts -o -iname *.dtsi \) -exec sed -i -e "s/@\([0-9a-fA-FxX\.;:#]+\)\s*{/@\L\1 {/g" -e "s/@0x\(.*\) {/@\1 {/g" -e "s/@0+\(.*\) {/@\1 {/g" {} +^C
>
> For simplicity, two sed expressions were used to solve each warnings separately.
>
> To make the regex expression more robust a few other issues were resolved,
> namely setting unit-address to lower case, and adding a whitespace before the
> the opening curly brace:
>
> https://urldefense.proofpoint.com/v2/url?u=https-3A__elinux.org_Device-5FTree-5FLinux-23Linux-5Fconventions&d=DwIBAg&c=RoP1YumCXCgaWHvlZYR8PZh8Bv7qIrMUB65eapI_JnE&r=hWpFvp_cTkkwMMULcvbV65orOO9Gv3OUaY0ATWhQwak&m=4zPLm6aGenI9keAZLborgvk3tLzaGsH_T4xXnh1mN3c&s=nCTYz6lbODdmoNqNYOTb6wm8nNYWW-AZlwiaUp7gpmM&e=
>
> This will solve as a side effect warning:
>
> Warning (simple_bus_reg): Node /XXX@<UPPER> simple-bus unit address format error, expected "<lower>"
>
> This is a follow up to commit 4c9847b7375a ("dt-bindings: Remove leading 0x from bindings notation")
>
> Reported-by: David Daney <ddaney@caviumnetworks.com>
> Suggested-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Mathieu Malaterre <malat@debian.org>
> ---
Looks good.
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
^ permalink raw reply
* Re: [RFC 1/5] [media] rc: update sunxi-ir driver to get base frequency from devicetree
From: Mauro Carvalho Chehab @ 2017-12-16 9:18 UTC (permalink / raw)
To: Philipp Rossak
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, wens-jdAy2FN1RRM,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, sean-hENCXIMQXOg,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, andi.shyti-Sze3O3UU22JBDgjK7y7TUQ,
linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20171216024914.7550-2-embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Em Sat, 16 Dec 2017 03:49:10 +0100
Philipp Rossak <embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> escreveu:
Hi Phillip,
This is not a full review of this patchset. I just want to point you
that you should keep supporting existing DT files.
> This patch updates the sunxi-ir driver to set the ir base clock from
> devicetree.
>
> This is neccessary since there are different ir recievers on the
> market, that operate with different frequencys. So this value needs to
> be set depending on the attached receiver.
Please don't break backward compatibility with old DT files. In this
specific case, it seems simple enough to be backward-compatible.
>
> Signed-off-by: Philipp Rossak <embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> drivers/media/rc/sunxi-cir.c | 20 +++++++++++---------
> 1 file changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
> index 97f367b446c4..55b53d6463e9 100644
> --- a/drivers/media/rc/sunxi-cir.c
> +++ b/drivers/media/rc/sunxi-cir.c
> @@ -72,12 +72,6 @@
> /* CIR_REG register idle threshold */
> #define REG_CIR_ITHR(val) (((val) << 8) & (GENMASK(15, 8)))
>
> -/* Required frequency for IR0 or IR1 clock in CIR mode */
> -#define SUNXI_IR_BASE_CLK 8000000
> -/* Frequency after IR internal divider */
> -#define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64)
Keep those to definitions...
> -/* Sample period in ns */
> -#define SUNXI_IR_SAMPLE (1000000000ul / SUNXI_IR_CLK)
> /* Noise threshold in samples */
> #define SUNXI_IR_RXNOISE 1
> /* Idle Threshold in samples */
> @@ -122,7 +116,7 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
> /* for each bit in fifo */
> dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
> rawir.pulse = (dt & 0x80) != 0;
> - rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
> + rawir.duration = ((dt & 0x7f) + 1) * ir->rc->rx_resolution;
> ir_raw_event_store_with_filter(ir->rc, &rawir);
> }
> }
> @@ -148,6 +142,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
> struct device_node *dn = dev->of_node;
> struct resource *res;
> struct sunxi_ir *ir;
> + u32 b_clk_freq;
>
> ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
> if (!ir)
> @@ -172,6 +167,12 @@ static int sunxi_ir_probe(struct platform_device *pdev)
> return PTR_ERR(ir->clk);
> }
>
> + /* Required frequency for IR0 or IR1 clock in CIR mode */
> + if (of_property_read_u32(dn, "base-clk-frequency", &b_clk_freq)) {
> + dev_err(dev, "failed to get ir base clock frequency.\n");
> + return -ENODATA;
> + }
> +
And here, instead of returning an error, if the property can't be read,
it means it is an older DT file. Just default to SUNXI_IR_BASE_CLK.
This will make it backward-compatible with old DT files that don't have
such property.
Regards,
Mauro
> /* Reset (optional) */
> ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
> if (IS_ERR(ir->rst))
> @@ -180,7 +181,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
> if (ret)
> return ret;
>
> - ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
> + ret = clk_set_rate(ir->clk, b_clk_freq);
> if (ret) {
> dev_err(dev, "set ir base clock failed!\n");
> goto exit_reset_assert;
> @@ -225,7 +226,8 @@ static int sunxi_ir_probe(struct platform_device *pdev)
> ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
> ir->rc->dev.parent = dev;
> ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
> - ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
> + /* Frequency after IR internal divider with sample period in ns */
> + ir->rc->rx_resolution = (1000000000ul / (b_clk_freq / 64));
> ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
> ir->rc->driver_name = SUNXI_IR_DEV;
>
Thanks,
Mauro
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^ permalink raw reply
* Waiting For Your Urgent Replay.........
From: Mr.Mohamed Akram @ 2017-12-16 9:25 UTC (permalink / raw)
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