* Re: [PATCH v3 2/3] dt-bindings: media: Add Allwinner V3s Camera Sensor Interface (CSI)
From: Maxime Ripard @ 2017-12-18 9:24 UTC (permalink / raw)
To: Yong
Cc: wens-jdAy2FN1RRM, Mauro Carvalho Chehab, Rob Herring,
Mark Rutland, David S. Miller, Greg Kroah-Hartman, Hans Verkuil,
Randy Dunlap, Benoit Parrot, Stanimir Varbanov, Arnd Bergmann,
Hugues Fruchet, Philipp Zabel, Benjamin Gaignard,
Ramesh Shanmugasundaram, Yannick Fertre, Sakari Ailus, Rick Chang,
Linux Media Mailing List, devicetree, linux-arm-kernel
In-Reply-To: <20171218164921.227b82349c778283f5e5eba8-+3dxTMOEIRNWk0Htik3J/w@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 708 bytes --]
Hi,
On Mon, Dec 18, 2017 at 04:49:21PM +0800, Yong wrote:
> > > + compatible = "allwinner,sun8i-v3s-csi";
> > > + reg = <0x01cb4000 0x1000>;
> > > + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&ccu CLK_BUS_CSI>,
> > > + <&ccu CLK_CSI1_SCLK>,
> >
> > CSI also has an MCLK. Do you need that one?
>
> MCLK is not needed if the front end is not a sensor (like adv7611).
> I will add it as an option.
I guess this should always be needed then. And the driver will make
the decision to enable it or not.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH v2 10/19] ARM: dts: aspeed: Add LPC Snoop device
From: Cédric Le Goater @ 2017-12-18 9:16 UTC (permalink / raw)
To: Joel Stanley, Rob Herring, Mark Rutland, Arnd Bergmann,
Andrew Jeffery, Patrick Venture, Xo Wang, Lei YU
Cc: Benjamin Herrenschmidt, Jeremy Kerr,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-aspeed-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <20171215062443.23059-11-joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> LPC snoop hardware on the ASPEED BMC, used for monitoring
> host I/O port activity.
>
> Signed-off-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 7 +++++++
> arch/arm/boot/dts/aspeed-g5.dtsi | 6 ++++++
> 2 files changed, 13 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> index f6fee40c04c0..b3580f37f507 100644
> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> @@ -236,6 +236,13 @@
> status = "disabled";
> };
>
> + lpc_snoop: lpc-snoop@0 {
> + compatible = "aspeed,ast2500-lpc-snoop";
it should be :
aspeed,ast2400-lpc-snoop
a part from that :
Reviewed-by: Cédric Le Goater <clg-Bxea+6Xhats@public.gmane.org>
> + reg = <0x0 0x80>;
> + interrupts = <8>;
> + status = "disabled";
> + };
> +
> lhc: lhc@20 {
> compatible = "aspeed,ast2500-lhc";
> reg = <0x20 0x24 0x48 0x8>;
> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> index 96a9d2fe3f0d..50766f0629f8 100644
> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> @@ -287,6 +287,12 @@
> status = "disabled";
> };
>
> + lpc_snoop: lpc-snoop@0 {
> + compatible = "aspeed,ast2500-lpc-snoop";
> + reg = <0x0 0x80>;
> + interrupts = <8>;
> + status = "disabled";
> + };
>
> lhc: lhc@20 {
> compatible = "aspeed,ast2500-lhc";
>
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^ permalink raw reply
* Re: [PATCH v2 19/19] ARM: dts: aspeed-plametto: Add flash layout
From: Cédric Le Goater @ 2017-12-18 9:09 UTC (permalink / raw)
To: Joel Stanley, Rob Herring, Mark Rutland, Arnd Bergmann,
Andrew Jeffery, Patrick Venture, Xo Wang, Lei YU
Cc: devicetree, linux-aspeed, Benjamin Herrenschmidt, linux-kernel,
Jeremy Kerr, linux-arm-kernel
In-Reply-To: <20171215062443.23059-20-joel@jms.id.au>
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> The OpenBMC flash layout is used by Palmetto systems.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
> index a8f0c046e83e..cc18137386f2 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
> @@ -34,6 +34,7 @@
> status = "okay";
> m25p,fast-read;
> label = "bmc";
> +#include "openbmc-flash-layout.dtsi"
> };
> };
>
>
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^ permalink raw reply
* Re: [PATCH v3 07/33] nds32: MMU initialization
From: Guo Ren @ 2017-12-18 9:08 UTC (permalink / raw)
To: Greentime Hu
Cc: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial,
geert.uytterhoeven, linus.walleij, mark.rutland, greg,
Vincent Chen
In-Reply-To: <0964714c3dcac46ac700085717b0f414b7978112.1512723245.git.green.hu@gmail.com>
Hi Greentime,
On Fri, Dec 08, 2017 at 05:11:50PM +0800, Greentime Hu wrote:
[...]
>
> diff --git a/arch/nds32/mm/highmem.c b/arch/nds32/mm/highmem.c
[...]
> +void *kmap(struct page *page)
> +{
> + unsigned long vaddr;
> + might_sleep();
> + if (!PageHighMem(page))
> + return page_address(page);
> + vaddr = (unsigned long)kmap_high(page);
Here should invalid the cpu_mmu_tlb's entry, Or invalid it in the
set_pte().
eg:
vaddr0 = kmap(page0)
*vaddr0 = val0 //It will cause tlb-miss, and hard-refill to MMU-tlb
kunmap(page0)
vaddr1 = kmap(page1) // Mostly vaddr1 = vaddr0
val = vaddr1; //No tlb-miss and it will get page0's val not page1, because
last expired vaddr0's entry is left in CPU-MMU-tlb.
Best Regards
Guo Ren
^ permalink raw reply
* Re: [PATCH v2 11/19] ARM: dts: aspeed: Remove skeleton.dtsi
From: Cédric Le Goater @ 2017-12-18 9:08 UTC (permalink / raw)
To: Joel Stanley, Rob Herring, Mark Rutland, Arnd Bergmann,
Andrew Jeffery, Patrick Venture, Xo Wang, Lei YU
Cc: devicetree, linux-aspeed, Benjamin Herrenschmidt, linux-kernel,
Jeremy Kerr, linux-arm-kernel
In-Reply-To: <20171215062443.23059-12-joel@jms.id.au>
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> We don't require it for any of the ASPEED systems.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 1 -
> arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
> 2 files changed, 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> index b3580f37f507..2d7ac577d6b5 100644
> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> @@ -1,5 +1,4 @@
> // SPDX-License-Identifier: GPL-2.0
> -#include "skeleton.dtsi"
> #include <dt-bindings/clock/aspeed-clock.h>
> #include <dt-bindings/gpio/aspeed-gpio.h>
>
> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> index 50766f0629f8..030a760696fd 100644
> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> @@ -1,5 +1,4 @@
> // SPDX-License-Identifier: GPL-2.0
> -#include "skeleton.dtsi"
> #include <dt-bindings/clock/aspeed-clock.h>
> #include <dt-bindings/gpio/aspeed-gpio.h>
>
>
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^ permalink raw reply
* Re: [PATCH v2 14/19] ARM: dts: aspeed: Sort ASPEED entries in makefile
From: Cédric Le Goater @ 2017-12-18 9:06 UTC (permalink / raw)
To: Joel Stanley, Rob Herring, Mark Rutland, Arnd Bergmann,
Andrew Jeffery, Patrick Venture, Xo Wang, Lei YU
Cc: devicetree, linux-aspeed, Benjamin Herrenschmidt, linux-kernel,
Jeremy Kerr, linux-arm-kernel
In-Reply-To: <20171215062443.23059-15-joel@jms.id.au>
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> In preperation for adding more boards.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> arch/arm/boot/dts/Makefile | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index d0381e9caf21..5d1e9d37bf3a 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1101,7 +1101,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
> mt8127-moose.dtb \
> mt8135-evbp1.dtb
> dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
> -dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \
> - aspeed-bmc-opp-romulus.dtb \
> - aspeed-ast2500-evb.dtb
> +dtb-$(CONFIG_ARCH_ASPEED) += \
> + aspeed-ast2500-evb.dtb \
> + aspeed-bmc-opp-palmetto.dtb \
> + aspeed-bmc-opp-romulus.dtb
> endif
>
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v2 12/19] ARM: dts: aspeed: Update license headers
From: Cédric Le Goater @ 2017-12-18 9:05 UTC (permalink / raw)
To: Joel Stanley, Rob Herring, Mark Rutland, Arnd Bergmann,
Andrew Jeffery, Patrick Venture, Xo Wang, Lei YU
Cc: Benjamin Herrenschmidt, Jeremy Kerr, devicetree, linux-arm-kernel,
linux-kernel, linux-aspeed
In-Reply-To: <20171215062443.23059-13-joel@jms.id.au>
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> In b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier
> to files with no license") these files had the GPL-2.0 licence added
> automatically. Update them to be GPL 2.0+ in line with other IBM kernel
> contributions.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> arch/arm/boot/dts/aspeed-ast2500-evb.dts | 2 +-
> arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 2 +-
> arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 2 +-
> arch/arm/boot/dts/aspeed-g4.dtsi | 2 +-
> arch/arm/boot/dts/aspeed-g5.dtsi | 2 +-
> 5 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
> index 602bc10fdaf4..3e6f38e5d5d0 100644
> --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
> +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
> @@ -1,4 +1,4 @@
> -// SPDX-License-Identifier: GPL-2.0
> +// SPDX-License-Identifier: GPL-2.0+
> /dts-v1/;
>
> #include "aspeed-g5.dtsi"
> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
> index c786bc2f2919..a8f0c046e83e 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
> @@ -1,4 +1,4 @@
> -// SPDX-License-Identifier: GPL-2.0
> +// SPDX-License-Identifier: GPL-2.0+
> /dts-v1/;
>
> #include "aspeed-g4.dtsi"
> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
> index 8067793129ea..a7a9386f964d 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
> @@ -1,4 +1,4 @@
> -// SPDX-License-Identifier: GPL-2.0
> +// SPDX-License-Identifier: GPL-2.0+
> /dts-v1/;
>
> #include "aspeed-g5.dtsi"
> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> index 2d7ac577d6b5..9c175832babc 100644
> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> @@ -1,4 +1,4 @@
> -// SPDX-License-Identifier: GPL-2.0
> +// SPDX-License-Identifier: GPL-2.0+
> #include <dt-bindings/clock/aspeed-clock.h>
> #include <dt-bindings/gpio/aspeed-gpio.h>
>
> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> index 030a760696fd..360329eab7c3 100644
> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> @@ -1,4 +1,4 @@
> -// SPDX-License-Identifier: GPL-2.0
> +// SPDX-License-Identifier: GPL-2.0+
> #include <dt-bindings/clock/aspeed-clock.h>
> #include <dt-bindings/gpio/aspeed-gpio.h>
>
>
^ permalink raw reply
* Re: [PATCH v2 13/19] ARM: dts: Add OpenBMC flash layout
From: Cédric Le Goater @ 2017-12-18 9:04 UTC (permalink / raw)
To: Joel Stanley, Rob Herring, Mark Rutland, Arnd Bergmann,
Andrew Jeffery, Patrick Venture, Xo Wang, Lei YU
Cc: devicetree, linux-aspeed, Benjamin Herrenschmidt, linux-kernel,
Jeremy Kerr, linux-arm-kernel
In-Reply-To: <20171215062443.23059-14-joel@jms.id.au>
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> This is a layout used by OpenBMC systems. It describes the fixed flash
> layout of a 32MB mtd device.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> arch/arm/boot/dts/openbmc-flash-layout.dtsi | 32 +++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
> create mode 100644 arch/arm/boot/dts/openbmc-flash-layout.dtsi
>
> diff --git a/arch/arm/boot/dts/openbmc-flash-layout.dtsi b/arch/arm/boot/dts/openbmc-flash-layout.dtsi
> new file mode 100644
> index 000000000000..63ad8db7a431
> --- /dev/null
> +++ b/arch/arm/boot/dts/openbmc-flash-layout.dtsi
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + u-boot@0 {
> + reg = <0x0 0x60000>;
> + label = "u-boot";
> + };
> +
> + u-boot-env@60000 {
> + reg = <0x60000 0x20000>;
> + label = "u-boot-env";
> + };
> +
> + kernel@80000 {
> + reg = <0x80000 0x440000>;
> + label = "kernel";
> + };
> +
> + rofs@0c0000 {
> + reg = <0x4c0000 0x1740000>;
> + label = "rofs";
> + };
> +
> + rwfs@1c00000 {
> + reg = <0x1c00000 0x400000>;
> + label = "rwfs";
> + };
> +};
>
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^ permalink raw reply
* Re: [PATCH v2 07/19] ARM: dts: aspeed: Add flash controller clocks
From: Cédric Le Goater @ 2017-12-18 9:03 UTC (permalink / raw)
To: Joel Stanley, Rob Herring, Mark Rutland, Arnd Bergmann,
Andrew Jeffery, Patrick Venture, Xo Wang, Lei YU
Cc: devicetree, linux-aspeed, Benjamin Herrenschmidt, linux-kernel,
Jeremy Kerr, linux-arm-kernel
In-Reply-To: <20171215062443.23059-8-joel@jms.id.au>
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++
> arch/arm/boot/dts/aspeed-g5.dtsi | 3 +++
> 2 files changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> index 2e3666d4fbeb..afac0ca0cb10 100644
> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> @@ -56,6 +56,7 @@
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2400-fmc";
> + clocks = <&syscon ASPEED_CLK_AHB>;
> status = "disabled";
> interrupts = <19>;
> flash@0 {
> @@ -71,6 +72,7 @@
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2400-spi";
> + clocks = <&syscon ASPEED_CLK_AHB>;
> status = "disabled";
> flash@0 {
> reg = < 0 >;
> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> index 24bb2d16b900..f3689caf6fe2 100644
> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> @@ -56,6 +56,7 @@
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2500-fmc";
> + clocks = <&syscon ASPEED_CLK_AHB>;
> status = "disabled";
> interrupts = <19>;
> flash@0 {
> @@ -81,6 +82,7 @@
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2500-spi";
> + clocks = <&syscon ASPEED_CLK_AHB>;
> status = "disabled";
> flash@0 {
> reg = < 0 >;
> @@ -100,6 +102,7 @@
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2500-spi";
> + clocks = <&syscon ASPEED_CLK_AHB>;
> status = "disabled";
> flash@0 {
> reg = < 0 >;
>
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^ permalink raw reply
* Re: [PATCH v2 06/19] ARM: dts: aspeed: Add watchdog clocks
From: Cédric Le Goater @ 2017-12-18 9:02 UTC (permalink / raw)
To: Joel Stanley, Rob Herring, Mark Rutland, Arnd Bergmann,
Andrew Jeffery, Patrick Venture, Xo Wang, Lei YU
Cc: devicetree, linux-aspeed, Benjamin Herrenschmidt, linux-kernel,
Jeremy Kerr, linux-arm-kernel
In-Reply-To: <20171215062443.23059-7-joel@jms.id.au>
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++
> arch/arm/boot/dts/aspeed-g5.dtsi | 3 +++
> 2 files changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> index cf407b4db630..2e3666d4fbeb 100644
> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> @@ -177,11 +177,13 @@
> wdt1: watchdog@1e785000 {
> compatible = "aspeed,ast2400-wdt";
> reg = <0x1e785000 0x1c>;
> + clocks = <&syscon ASPEED_CLK_APB>;
> };
>
> wdt2: watchdog@1e785020 {
> compatible = "aspeed,ast2400-wdt";
> reg = <0x1e785020 0x1c>;
> + clocks = <&syscon ASPEED_CLK_APB>;
> };
>
> vuart: serial@1e787000 {
> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> index ab26156d6822..24bb2d16b900 100644
> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> @@ -219,16 +219,19 @@
> wdt1: watchdog@1e785000 {
> compatible = "aspeed,ast2500-wdt";
> reg = <0x1e785000 0x20>;
> + clocks = <&syscon ASPEED_CLK_APB>;
> };
>
> wdt2: watchdog@1e785020 {
> compatible = "aspeed,ast2500-wdt";
> reg = <0x1e785020 0x20>;
> + clocks = <&syscon ASPEED_CLK_APB>;
> };
>
> wdt3: watchdog@1e785040 {
> compatible = "aspeed,ast2500-wdt";
> reg = <0x1e785040 0x20>;
> + clocks = <&syscon ASPEED_CLK_APB>;
> status = "disabled";
> };
>
>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v2 1/4] dt-bindings: usb: add DT binding for RK3328 dwc3 controller
From: Felipe Balbi @ 2017-12-18 9:00 UTC (permalink / raw)
To: Heiko Stuebner, gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r
Cc: william.wu-TNX95d0MmH7DzftRWevZcw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, linux-usb-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1863083.H0I2rMmhUr@phil>
Hi,
Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> writes:
> Hi Greg, Felipe,
>
> Am Montag, 4. Dezember 2017, 10:40:38 CET schrieb Heiko Stuebner:
>> From: William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>>
>> Adds the device tree bindings description for RK3328 and
>> compatible USB DWC3 controller.
>>
>> Signed-off-by: William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
>
> do you want to pick this patch with only the small dt-binding
> change or Ack it for me to pick up together with the actual
> devicetree changes in the other patches?
it seems best if you carry this one:
Acked-by: Felipe Balbi <felipe.balbi-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
--
balbi
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^ permalink raw reply
* Re: [PATCH v5 0/5] misc serdev: new serdev based driver for Wi2Wi w2sg00x4 GPS module
From: H. Nikolaus Schaller @ 2017-12-18 8:52 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Benoît Cousson, Tony Lindgren,
Russell King, Arnd Bergmann, Greg Kroah-Hartman,
Nikolaus Schaller, Kevin Hilman, Andreas Färber,
Thierry Reding, Jonathan Cameron, Andrew F. Davis
Cc: DTML, linux-omap, Linux Kernel Mailing List, kernel,
Discussions about the Letux Kernel, Linux ARM
In-Reply-To: <cover.1512114576.git.hns@goldelico.com>
Hi,
unfortunately I had lost to include Andrew Davis' address who had provided
very valuable comments for v5. Sorry, Andrew!
There has only been one more comment by Andreas Färber in the past 14 days.
So how to proceed? Who is taking care of deciding/merging towards linux-next?
BR and thanks,
Nikolaus
> Am 01.12.2017 um 08:49 schrieb H. Nikolaus Schaller <hns@goldelico.com>:
>
> Changes V5:
> * clarified to keep it in drivers/misc and not create a new group drivers/gps
> * fix formatting of new entry in omap3-gta04.dtsi (suggested by Tony Lindgren)
> * removed MODULE_ALIAS (suggested by Andrew F. Davis)
> * some more formatting, code&style fixes (suggested by Andrew F. Davis)
> * apply __maybe_unused for PM (suggested by Andrew F. Davis)
> * fixed copyright and author records (suggested by Andrew F. Davis)
>
> 2017-11-15 22:38:01: Changes V4:
> * removed all pdata remains (suggested by Arnd Bergmann and Rob Herring)
> * fixed minor issues and subject/commit messages (suggested by Rob Herring)
> * added one missing Signed-off-By: (suggested by Andreas Färber)
> * added SPDX header (suggested by Rob Herring)
>
> 2017-11-15 16:19:17: Changes V3:
> * worked in suggestions by kbuild test robot
> * added misc+serdev to the subject
>
> 2017-11-12 22:00:02: Changes V2:
> * reduced to submit only w2sg00x4 GPS driver code
> * add DT node for GTA04 device to make use of the driver
> * split into base code and a debugging Kconfig option (brings device into false power state after boot)
> * worked in comments by kbuild robot and Rob Herring
>
> 2017-05-21 12:44:07: RFC V1
> * RFC concerning new serdev based drivers for Wi2Wi w2sg00x4 GPS module and w2cbw003 bluetooth
>
> Years long history of getting this devices supported (original work by Neil Brown).
>
> H. Nikolaus Schaller (5):
> dt-bindings: define vendor prefix for Wi2Wi, Inc.
> dt-bindings: gps: add w2sg00x4 bindings documentation (GPS module with
> UART))
> misc serdev: Add w2sg0004 (gps receiver) power control driver
> DTS: gta04: add uart2 child node for w2sg00x4
> misc serdev: w2sg0004: add debugging code and Kconfig
>
> .../devicetree/bindings/gps/wi2wi,w2sg0004.txt | 24 +
> .../devicetree/bindings/vendor-prefixes.txt | 1 +
> arch/arm/boot/dts/omap3-gta04.dtsi | 7 +
> drivers/misc/Kconfig | 18 +
> drivers/misc/Makefile | 1 +
> drivers/misc/w2sg0004.c | 590 +++++++++++++++++++++
> 6 files changed, 641 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/gps/wi2wi,w2sg0004.txt
> create mode 100644 drivers/misc/w2sg0004.c
>
> --
> 2.12.2
>
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v3 2/3] dt-bindings: media: Add Allwinner V3s Camera Sensor Interface (CSI)
From: Yong @ 2017-12-18 8:49 UTC (permalink / raw)
To: wens-jdAy2FN1RRM
Cc: Maxime Ripard, Mauro Carvalho Chehab, Rob Herring, Mark Rutland,
David S. Miller, Greg Kroah-Hartman, Hans Verkuil, Randy Dunlap,
Benoit Parrot, Stanimir Varbanov, Arnd Bergmann, Hugues Fruchet,
Philipp Zabel, Benjamin Gaignard, Ramesh Shanmugasundaram,
Yannick Fertre, Sakari Ailus, Rick Chang,
Linux Media Mailing List, devicetree
In-Reply-To: <CAGb2v67JhMfba8Ao7WyrYikkxvTxX8WaBRqu3GkrhOCWndresg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Mon, 18 Dec 2017 16:35:51 +0800
Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> wrote:
> On Mon, Nov 13, 2017 at 3:32 PM, Yong Deng <yong.deng-+3dxTMOEIRNWk0Htik3J/w@public.gmane.org> wrote:
> > Add binding documentation for Allwinner V3s CSI.
> >
> > Signed-off-by: Yong Deng <yong.deng-+3dxTMOEIRNWk0Htik3J/w@public.gmane.org>
> > ---
> > .../devicetree/bindings/media/sun6i-csi.txt | 51 ++++++++++++++++++++++
> > 1 file changed, 51 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/media/sun6i-csi.txt
> >
> > diff --git a/Documentation/devicetree/bindings/media/sun6i-csi.txt b/Documentation/devicetree/bindings/media/sun6i-csi.txt
> > new file mode 100644
> > index 0000000..f3916a2
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/sun6i-csi.txt
> > @@ -0,0 +1,51 @@
> > +Allwinner V3s Camera Sensor Interface
> > +------------------------------
> > +
> > +Required properties:
> > + - compatible: value must be "allwinner,sun8i-v3s-csi"
> > + - reg: base address and size of the memory-mapped region.
> > + - interrupts: interrupt associated to this IP
> > + - clocks: phandles to the clocks feeding the CSI
> > + * bus: the CSI interface clock
> > + * mod: the CSI module clock
> > + * ram: the CSI DRAM clock
> > + - clock-names: the clock names mentioned above
> > + - resets: phandles to the reset line driving the CSI
> > +
> > +- ports: A ports node with endpoint definitions as defined in
> > + Documentation/devicetree/bindings/media/video-interfaces.txt.
> > + Currently, the driver only support the parallel interface. So, a single port
> > + node with one endpoint and parallel bus is supported.
> > +
> > +Example:
> > +
> > + csi1: csi@01cb4000 {
>
> Drop the leading zero in the address part.
OK.
>
> > + compatible = "allwinner,sun8i-v3s-csi";
> > + reg = <0x01cb4000 0x1000>;
> > + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_CSI>,
> > + <&ccu CLK_CSI1_SCLK>,
>
> CSI also has an MCLK. Do you need that one?
MCLK is not needed if the front end is not a sensor (like adv7611).
I will add it as an option.
>
> ChenYu
>
> > + <&ccu CLK_DRAM_CSI>;
> > + clock-names = "bus", "mod", "ram";
> > + resets = <&ccu RST_BUS_CSI>;
> > +
> > + port {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + /* Parallel bus endpoint */
> > + csi1_ep: endpoint {
> > + remote-endpoint = <&adv7611_ep>;
> > + bus-width = <16>;
> > + data-shift = <0>;
> > +
> > + /* If hsync-active/vsync-active are missing,
> > + embedded BT.656 sync is used */
> > + hsync-active = <0>; /* Active low */
> > + vsync-active = <0>; /* Active low */
> > + data-active = <1>; /* Active high */
> > + pclk-sample = <1>; /* Rising */
> > + };
> > + };
> > + };
> > +
> > --
> > 1.8.3.1
> >
> > --
> > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
> > For more options, visit https://groups.google.com/d/optout.
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
> For more options, visit https://groups.google.com/d/optout.
Thanks,
Yong
^ permalink raw reply
* Re: [PATCH 1/4 v5] drm/bridge: Add bindings for TI THS8134
From: Laurent Pinchart @ 2017-12-18 8:46 UTC (permalink / raw)
To: Linus Walleij
Cc: Archit Taneja, Andrzej Hajda,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Eric Anholt,
devicetree-u79uwXL29TY76Z2rM5mHXA, Bartosz Golaszewski
In-Reply-To: <20171215121047.3650-2-linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Hello Linus,
Thank you for the patch.
On Friday, 15 December 2017 14:10:44 EET Linus Walleij wrote:
> This adds device tree bindings for the Texas Instruments
> THS8134, THS8134A and THS8134B VGA DACs by extending and
> renaming the existing bindings for THS8135.
>
> These DACs are used for the VGA outputs on the ARM reference
> designs such as Integrator, Versatile and RealView.
>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> ChangeLog v2->v5:
> - Dropped the "ti,ths813x" as it turns out we need precise info
> about the sub-variant anyways as they all very in timings.
> - Refine the THS8134 variants, it turns out ths8134, ths8134a
> and ths8134b are three different variants of ths8134.
> ChangeLog v1->v2:
> - Introduce specific-to-general compatible string:
> compatible = "ti,ths8134a", "ti,ths813x";
> so drivers can handle the whole family the same way.
> - Collected Rob's ACK.
> ---
> .../display/bridge/{ti,ths8135.txt => ti,ths813x.txt} | 13 +++++++--
> 1 file changed, 9 insertions(+), 4 deletions(-)
> rename Documentation/devicetree/bindings/display/bridge/{ti,ths8135.txt =>
> ti,ths813x.txt} (69%)
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/ti,ths8135.txt
> b/Documentation/devicetree/bindings/display/bridge/ti,ths813x.txt
> similarity index 69%
> rename from Documentation/devicetree/bindings/display/bridge/ti,ths8135.txt
> rename to Documentation/devicetree/bindings/display/bridge/ti,ths813x.txt
> index 6ec1a880ac18..49f155467f00 100644
> --- a/Documentation/devicetree/bindings/display/bridge/ti,ths8135.txt
> +++ b/Documentation/devicetree/bindings/display/bridge/ti,ths813x.txt
> @@ -1,11 +1,16 @@
> -THS8135 Video DAC
> ------------------
> +THS8134 and THS8135 Video DAC
> +-----------------------------
>
> -This is the binding for Texas Instruments THS8135 Video DAC bridge.
> +This is the binding for Texas Instruments THS8134, THS8134A, THS8134B and
> +THS8135 Video DAC bridge.
There's more than one no, so s/bridge/bridges/. Or just s/DAC bridge/DACs/ as
bridge refers to the software implementation.
With this and Rob's comment about the compatible string ordering
("ti,ths8134[ab]", "ti,ths8134" instead of "ti,ths8134[ab]", "ti,ths8134"),
Reviewed-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> Required properties:
>
> -- compatible: Must be "ti,ths8135"
> +- compatible: Must be one of
> + "ti,ths8134"
> + "ti,ths8134", "ti,ths8134a"
> + "ti,ths8134", "ti,ths8134b"
> + "ti,ths8135"
>
> Required nodes:
--
Regards,
Laurent Pinchart
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^ permalink raw reply
* Re: [PATCH v2 2/7] i3c: Add core I3C infrastructure
From: Boris Brezillon @ 2017-12-18 8:37 UTC (permalink / raw)
To: Randy Dunlap
Cc: Wolfram Sang, linux-i2c, Jonathan Corbet, linux-doc,
Greg Kroah-Hartman, Arnd Bergmann, Przemyslaw Sroka,
Arkadiusz Golec, Alan Douglas, Bartosz Folta, Damian Kos,
Alicja Jurasik-Urbaniak, Cyprian Wronka, Suresh Punnoose,
Thomas Petazzoni, Nishanth Menon, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala
In-Reply-To: <63546906-2fab-300a-b952-a0a7e8eb8bb5@infradead.org>
On Sun, 17 Dec 2017 14:32:04 -0800
Randy Dunlap <rdunlap@infradead.org> wrote:
> On 12/14/17 07:16, Boris Brezillon wrote:
> > Add core infrastructure to support I3C in Linux and document it.
> >
> > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
> > ---
> > drivers/Kconfig | 2 +
> > drivers/Makefile | 2 +-
> > drivers/i3c/Kconfig | 24 +
> > drivers/i3c/Makefile | 4 +
> > drivers/i3c/core.c | 573 ++++++++++++++++
> > drivers/i3c/device.c | 344 ++++++++++
> > drivers/i3c/internals.h | 34 +
> > drivers/i3c/master.c | 1433 +++++++++++++++++++++++++++++++++++++++
> > drivers/i3c/master/Kconfig | 0
> > drivers/i3c/master/Makefile | 0
> > include/linux/i3c/ccc.h | 380 +++++++++++
> > include/linux/i3c/device.h | 321 +++++++++
> > include/linux/i3c/master.h | 564 +++++++++++++++
> > include/linux/mod_devicetable.h | 17 +
> > 14 files changed, 3697 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/i3c/Kconfig
> > create mode 100644 drivers/i3c/Makefile
> > create mode 100644 drivers/i3c/core.c
> > create mode 100644 drivers/i3c/device.c
> > create mode 100644 drivers/i3c/internals.h
> > create mode 100644 drivers/i3c/master.c
> > create mode 100644 drivers/i3c/master/Kconfig
> > create mode 100644 drivers/i3c/master/Makefile
> > create mode 100644 include/linux/i3c/ccc.h
> > create mode 100644 include/linux/i3c/device.h
> > create mode 100644 include/linux/i3c/master.h
> >
> > diff --git a/drivers/i3c/Kconfig b/drivers/i3c/Kconfig
> > new file mode 100644
> > index 000000000000..cf3752412ae9
> > --- /dev/null
> > +++ b/drivers/i3c/Kconfig
> > @@ -0,0 +1,24 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +
> > +menuconfig I3C
> > + tristate "I3C support"
> > + select I2C
> > + help
> > + I3C is a serial protocol standardized by the MIPI alliance.
> > +
> > + It's supposed to be backward compatible with I2C while providing
> > + support for high speed transfers and native interrupt support
> > + without the need for extra pins.
> > +
> > + The I3C protocol also standardizes the slave device types and is
> > + mainly design to communicate with sensors.
> > +
> > + If you want I3C support, you should say Y here and also to the
> > + specific driver for your bus adapter(s) below.
> > +
> > + This I3C support can also be built as a module. If so, the module
> > + will be called i3c.
> > +
> > +if I3C
> > +source "drivers/i3c/master/Kconfig"
> > +endif # I3C
>
> > diff --git a/drivers/i3c/core.c b/drivers/i3c/core.c
> > new file mode 100644
> > index 000000000000..7eb8e84acd33
> > --- /dev/null
> > +++ b/drivers/i3c/core.c
> > @@ -0,0 +1,573 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2017 Cadence Design Systems Inc.
> > + *
> > + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> > + */
> > +
> > +#include <linux/idr.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/slab.h>
>
> #include <linux/device.h>
> #include <linux/init.h>
> #include <linux/list.h>
> #include <linux/mutex.h>
> #include <linux/rwsem.h>
Do you have a tool to detect those missing inclusions?
>
>
> > +#include "internals.h"
> > +
> > +static DEFINE_IDR(i3c_bus_idr);
> > +static DEFINE_MUTEX(i3c_core_lock);
> > +
>
> > +/**
> > + * i3c_bus_maintenance_lock - Release the bus lock after a maintenance
>
> unlock
>
Will fix that.
> > + * operation
> > + * @bus: I3C bus to release the lock on
> > + *
> > + * Should be called when the bus maintenance operation is done. See
> > + * i3c_bus_maintenance_lock() for more details on what these maintenance
> > + * operations are.
> > + */
> > +void i3c_bus_maintenance_unlock(struct i3c_bus *bus)
> > +{
> > + up_write(&bus->lock);
> > +}
> > +EXPORT_SYMBOL_GPL(i3c_bus_maintenance_unlock);
> > +
>
> > +/**
> > + * i3c_bus_normaluse_lock - Release the bus lock after a normal operation
>
> unlock
Ditto.
>
> > + * @bus: I3C bus to release the lock on
> > + *
> > + * Should be called when a normal operation is done. See
> > + * i3c_bus_normaluse_lock() for more details on what these normal operations
> > + * are.
> > + */
> > +void i3c_bus_normaluse_unlock(struct i3c_bus *bus)
> > +{
> > + up_read(&bus->lock);
> > +}
> > +EXPORT_SYMBOL_GPL(i3c_bus_normaluse_unlock);
>
>
>
> > +static int i3c_device_match(struct device *dev, struct device_driver *drv)
>
> bool?
>
> > +{
> > + struct i3c_device *i3cdev;
> > + struct i3c_driver *i3cdrv;
> > +
> > + if (dev->type != &i3c_device_type)
> > + return 0;
> > +
> > + i3cdev = dev_to_i3cdev(dev);
> > + i3cdrv = drv_to_i3cdrv(drv);
> > + if (i3c_device_match_id(i3cdev, i3cdrv->id_table))
> > + return 1;
> > +
> > + return 0;
> > +}
>
>
> > diff --git a/drivers/i3c/device.c b/drivers/i3c/device.c
> > new file mode 100644
> > index 000000000000..dcf51150b7cb
> > --- /dev/null
> > +++ b/drivers/i3c/device.c
> > @@ -0,0 +1,344 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2017 Cadence Design Systems Inc.
> > + *
> > + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> > + */
> > +
> > +#include <linux/slab.h>
>
> #include <linux/atomic.h>
> #include <linux/bug.h>
> #include <linux/completion.h>
> #include <linux/device.h>
> #include <linux/mutex.h>
>
> > +#include "internals.h"
>
>
>
> > diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
> > new file mode 100644
> > index 000000000000..1c85abac08d5
> > --- /dev/null
> > +++ b/drivers/i3c/master.c
> > @@ -0,0 +1,1433 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2017 Cadence Design Systems Inc.
> > + *
> > + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> > + */
>
> #include <linux/atomic.h>
> #include <linux/device.h>
> #include <linux/err.h>
> #include <linux/export.h>
> #include <linux/kernel.h>
> #include <linux/list.h>
> #include <linux/of.h>
>
> > +#include <linux/slab.h>
>
> #include <linux/spinlock.h>
> #include <linux/workqueue.h>
>
> #include <asm-generic/bug.h>
>
> > +#include "internals.h"
>
>
> and I probably missed a few.
>
>
>
>
> > diff --git a/include/linux/i3c/ccc.h b/include/linux/i3c/ccc.h
> > new file mode 100644
> > index 000000000000..ff3e1a3e2c4c
> > --- /dev/null
> > +++ b/include/linux/i3c/ccc.h
> > @@ -0,0 +1,380 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2017 Cadence Design Systems Inc.
> > + *
> > + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> > + */
>
> > +/**
> > + * struct i3c_ccc_dev_desc - I3C/I3C device descriptor used for DEFSLVS
>
> Is one of those I3C above supposed to be I2C?
Indeed, should be I2C/I3C.
>
> > + *
> > + * @dyn_addr: dynamic address assigned to the I3C slave or 0 if the entry is
> > + * describing an I2C slave.
> > + * @dcr: DCR value (not applicable to entries describing I2C devices)
> > + * @lvr: LVR value (not applicable to entries describing I3C devices)
> > + * @bcr: BCR value or 0 if this entry is describing an I2C slave
> > + * @static_addr: static address or 0 if the device does not have a static
> > + * address
> > + *
> > + * The DEFSLVS command should be passed an array of i3c_ccc_dev_desc
> > + * descriptors (one entry per I3C/I2C dev controlled by the master).
> > + */
> > +struct i3c_ccc_dev_desc {
> > + u8 dyn_addr;
> > + union {
> > + u8 dcr;
> > + u8 lvr;
> > + };
> > + u8 bcr;
> > + u8 static_addr;
> > +} __packed;
>
>
> Needs bitops.h
>
> > diff --git a/include/linux/i3c/device.h b/include/linux/i3c/device.h
> > new file mode 100644
> > index 000000000000..83958d3a02e2
> > --- /dev/null
> > +++ b/include/linux/i3c/device.h
> > @@ -0,0 +1,321 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2017 Cadence Design Systems Inc.
> > + *
> > + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> > + */
> > +
> > +#ifndef I3C_DEV_H
> > +#define I3C_DEV_H
> > +
> > +#include <linux/device.h>
> > +#include <linux/i2c.h>
> > +#include <linux/mod_devicetable.h>
> > +#include <linux/module.h>
>
>
> Needs bitops.h, kconfig.h.
>
>
> > diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h
> > new file mode 100644
> > index 000000000000..7ec9a4821bac
> > --- /dev/null
> > +++ b/include/linux/i3c/master.h
> > @@ -0,0 +1,564 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2017 Cadence Design Systems Inc.
> > + *
> > + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> > + */
> > +
> > +#ifndef I3C_MASTER_H
> > +#define I3C_MASTER_H
> > +
> > +#include <linux/i2c.h>
> > +#include <linux/i3c/ccc.h>
> > +#include <linux/i3c/device.h>
> > +#include <linux/spinlock.h>
> > +
> > +#define I3C_HOT_JOIN_ADDR 0x2
> > +#define I3C_BROADCAST_ADDR 0x7e
> > +#define I3C_MAX_ADDR GENMASK(6, 0)
> > +
>
> Needs bitops.h, workqueue.h, rwsem.h
>
>
> Needs <asm-generic/bitsperlong.h>
Okay, that's really weird to directly include a header from the
asm-generic directory, are you sure this is the right thing to do here?
>
>
>
> > diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
> > index abb6dc2ebbf8..e59da92d8ac9 100644
> > --- a/include/linux/mod_devicetable.h
> > +++ b/include/linux/mod_devicetable.h
> > @@ -442,6 +442,23 @@ struct pci_epf_device_id {
> > kernel_ulong_t driver_data;
> > };
> >
> > +/* i3c */
> > +
> > +#define I3C_MATCH_DCR BIT(0)
> > +#define I3C_MATCH_MANUF BIT(1)
> > +#define I3C_MATCH_PART BIT(2)
> > +#define I3C_MATCH_EXTRA_INFO BIT(3)
>
> Needs bitops.h.
I think I'll just avoid using BIT() here, as done for other definitions
in this file.
>
> > +struct i3c_device_id {
> > + __u8 match_flags;
> > + __u8 dcr;
> > + __u16 manuf_id;
> > + __u16 part_id;
> > + __u16 extra_info;
> > +
> > + const void *data;
> > +};
> > +
> > /* spi */
> >
> > #define SPI_NAME_SIZE 32
> >
>
>
^ permalink raw reply
* RE: [PATCH 1/2] dt-bindings: usb-xhci: add usb3-resume-missing-cas property
From: Jun Li @ 2017-12-18 8:35 UTC (permalink / raw)
To: Rob Herring
Cc: mathias.nyman-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <20171215222600.qffkck67qjwwpref@rob-hp-laptop>
> -----Original Message-----
> From: Rob Herring [mailto:robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
> Sent: Saturday, December 16, 2017 6:26 AM
> To: Jun Li <jun.li-3arQi8VN3Tc@public.gmane.org>
> Cc: mathias.nyman-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org; gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org;
> mark.rutland-5wv7dgnIgG8@public.gmane.org; linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org;
> devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Subject: Re: [PATCH 1/2] dt-bindings: usb-xhci: add usb3-resume-missing-cas
> property
>
> On Tue, Dec 12, 2017 at 11:57:17AM +0800, Li Jun wrote:
> > Adding 'usb3-resume-missing-cas' property to enable XHCI_MISSING_CAS
> > quirk flag in case there is CAS missing if device plugged in S3.
> >
> > Signed-off-by: Li Jun <jun.li-3arQi8VN3Tc@public.gmane.org>
> > ---
> > Documentation/devicetree/bindings/usb/usb-xhci.txt | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt
> > b/Documentation/devicetree/bindings/usb/usb-xhci.txt
> > index e2ea59b..c413e188 100644
> > --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
> > +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
> > @@ -32,6 +32,8 @@ Optional properties:
> > - usb3-lpm-capable: determines if platform is USB3 LPM capable
> > - quirk-broken-port-ped: set if the controller has broken port disable
> mechanism
> > - imod-interval-ns: default interrupt moderation interval is 5000ns
> > + - usb3-resume-missing-cas: set if the CAS(Cold Attach Status) may lose in
> case
> > + usb3 device plugged in while system sleep.
>
> This should be implied by an SoC specific compatible string for the XHCI block.
The quirk is already using on some PCI platforms(xhci-pci.c), so I think it will
be possible used for other SoCs as well in future.
thanks
Jun Li
>
> Rob
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^ permalink raw reply
* Re: [PATCH v3 2/3] dt-bindings: media: Add Allwinner V3s Camera Sensor Interface (CSI)
From: Chen-Yu Tsai @ 2017-12-18 8:35 UTC (permalink / raw)
To: Yong Deng
Cc: Maxime Ripard, Mauro Carvalho Chehab, Rob Herring, Mark Rutland,
Chen-Yu Tsai, David S. Miller, Greg Kroah-Hartman, Hans Verkuil,
Randy Dunlap, Benoit Parrot, Stanimir Varbanov, Arnd Bergmann,
Hugues Fruchet, Philipp Zabel, Benjamin Gaignard,
Ramesh Shanmugasundaram, Yannick Fertre, Sakari Ailus, Rick Chang,
Linux Media Mailing List, devicetree
In-Reply-To: <1510558344-45402-1-git-send-email-yong.deng-+3dxTMOEIRNWk0Htik3J/w@public.gmane.org>
On Mon, Nov 13, 2017 at 3:32 PM, Yong Deng <yong.deng-+3dxTMOEIRNWk0Htik3J/w@public.gmane.org> wrote:
> Add binding documentation for Allwinner V3s CSI.
>
> Signed-off-by: Yong Deng <yong.deng-+3dxTMOEIRNWk0Htik3J/w@public.gmane.org>
> ---
> .../devicetree/bindings/media/sun6i-csi.txt | 51 ++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/sun6i-csi.txt
>
> diff --git a/Documentation/devicetree/bindings/media/sun6i-csi.txt b/Documentation/devicetree/bindings/media/sun6i-csi.txt
> new file mode 100644
> index 0000000..f3916a2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/sun6i-csi.txt
> @@ -0,0 +1,51 @@
> +Allwinner V3s Camera Sensor Interface
> +------------------------------
> +
> +Required properties:
> + - compatible: value must be "allwinner,sun8i-v3s-csi"
> + - reg: base address and size of the memory-mapped region.
> + - interrupts: interrupt associated to this IP
> + - clocks: phandles to the clocks feeding the CSI
> + * bus: the CSI interface clock
> + * mod: the CSI module clock
> + * ram: the CSI DRAM clock
> + - clock-names: the clock names mentioned above
> + - resets: phandles to the reset line driving the CSI
> +
> +- ports: A ports node with endpoint definitions as defined in
> + Documentation/devicetree/bindings/media/video-interfaces.txt.
> + Currently, the driver only support the parallel interface. So, a single port
> + node with one endpoint and parallel bus is supported.
> +
> +Example:
> +
> + csi1: csi@01cb4000 {
Drop the leading zero in the address part.
> + compatible = "allwinner,sun8i-v3s-csi";
> + reg = <0x01cb4000 0x1000>;
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CSI>,
> + <&ccu CLK_CSI1_SCLK>,
CSI also has an MCLK. Do you need that one?
ChenYu
> + <&ccu CLK_DRAM_CSI>;
> + clock-names = "bus", "mod", "ram";
> + resets = <&ccu RST_BUS_CSI>;
> +
> + port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* Parallel bus endpoint */
> + csi1_ep: endpoint {
> + remote-endpoint = <&adv7611_ep>;
> + bus-width = <16>;
> + data-shift = <0>;
> +
> + /* If hsync-active/vsync-active are missing,
> + embedded BT.656 sync is used */
> + hsync-active = <0>; /* Active low */
> + vsync-active = <0>; /* Active low */
> + data-active = <1>; /* Active high */
> + pclk-sample = <1>; /* Rising */
> + };
> + };
> + };
> +
> --
> 1.8.3.1
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
> For more options, visit https://groups.google.com/d/optout.
^ permalink raw reply
* Re: [PATCH 1/2] serial: stm32: add default console
From: Ludovic BARRE @ 2017-12-18 8:31 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Maxime Coquelin, Alexandre Torgue, devicetree, linux-kernel,
Rob Herring, linux-serial, Jiri Slaby, linux-arm-kernel
In-Reply-To: <20171215192517.GA27395@kroah.com>
hi Greg
Yes, the machine could be boot without console. but our
boards has a console by default. it is just to simplified the
configuration.
you can abandoned this patch, if you prefer.
BR
Ludo
On 12/15/2017 08:25 PM, Greg Kroah-Hartman wrote:
> On Fri, Dec 01, 2017 at 05:36:50PM +0100, Ludovic Barre wrote:
>> From: Ludovic Barre <ludovic.barre@st.com>
>>
>> This patch adds by default the console support
>> on stm32.
>
> Why? 'default y' should only mean "machine will not boot without this".
> And I think your machine will boot without the console, right? :)
>
> thanks,
>
> greg k-h
>
^ permalink raw reply
* Re: [PATCH 00/12] Marvell NAND controller rework with ->exec_op()
From: Miquel RAYNAL @ 2017-12-18 8:25 UTC (permalink / raw)
To: Robert Jarzmik
Cc: Boris Brezillon, David Woodhouse, Brian Norris, Marek Vasut,
Richard Weinberger, Cyrille Pitchen, Rob Herring, Mark Rutland,
Jason Cooper, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Russell King, Daniel Mack, Haojian Zhuang, Eric Miao,
Catalin Marinas, Will Deacon
In-Reply-To: <877etkecig.fsf-4ty26DBLk+jEm7gnYqmdkQ@public.gmane.org>
Hello Robert,
On Mon, 18 Dec 2017 08:11:35 +0100
Robert Jarzmik <robert.jarzmik-GANU6spQydw@public.gmane.org> wrote:
> Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> writes:
>
> >> Robert, it would be great if you could also do more testing on PXA
> >> and validate this driver. If needed, a branch ready to be tested is
> >> available at [3]. It is based on nand/next and has all the changes
> >> brought by the previously mentionned series as well as this one.
> >
> > Robert, do you think you'll have some time to test Miquel's branch
> > on your PXA boards? Miquel already tested on one of these boards
> > (CM-X300), but we'd like to have other testers. Also feel free to
> > review the driver if have the time.
> >
> > Thanks,
> >
> > Boris
>
> Hi Boris and Miquel,
>
> I have applied the whole serie to linux-next yesterday.
>
> A boot attempt on my zylonite with my old defconfig (with the new
> Marvell NAND config activated) yields to :
> - this message
> [ 3.136818] marvell-nfc pxa3xx-nand: could not identify the nand
> chip [ 3.143874] marvell-nfc: probe of pxa3xx-nand failed with
> error -22
> - then my board hangs
>
> Is there something to be done to improve the trace level so that you
> can guess what's happening ?
Thank you very much for testing this.
Could you please try this branch [1] instead of linux-next + the
patches?
Also, can you please add #define DEBUG in marvell_nand.c + nand_base.c,
it should help us figuring out what is wrong.
Thank you,
Miquèl
[1] https://github.com/miquelraynal/linux/tree/marvell/nand-next/nfc
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^ permalink raw reply
* Re: [PATCH 4/5] arm: dts: sun8i: a83t: Add support for the ir interface
From: Maxime Ripard @ 2017-12-18 7:47 UTC (permalink / raw)
To: Philipp Rossak
Cc: mchehab-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, wens-jdAy2FN1RRM,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, sean-hENCXIMQXOg,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, andi.shyti-Sze3O3UU22JBDgjK7y7TUQ,
linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20171217224547.21481-5-embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1169 bytes --]
On Sun, Dec 17, 2017 at 11:45:46PM +0100, Philipp Rossak wrote:
> The ir interface is like on the H3 located at 0x01f02000 and is exactly
> the same. This patch adds support for the ir interface on the A83T.
>
> Signed-off-by: Philipp Rossak <embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index 954c2393325f..9e7ed3b9a6b8 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -503,6 +503,16 @@
> #reset-cells = <1>;
> };
>
> + ir: ir@01f02000 {
> + compatible = "allwinner,sun5i-a13-ir";
> + clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
> + clock-names = "apb", "ir";
> + resets = <&r_ccu RST_APB0_IR>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x01f02000 0x40>;
The size should be the size of the whole memory block, not just the
registers you need.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH 2/5] media: dt: bindings: Update binding documentation for sunxi IR controller
From: Maxime Ripard @ 2017-12-18 7:46 UTC (permalink / raw)
To: Philipp Rossak
Cc: mchehab-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, wens-jdAy2FN1RRM,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, sean-hENCXIMQXOg,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, andi.shyti-Sze3O3UU22JBDgjK7y7TUQ,
linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20171217224547.21481-3-embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1195 bytes --]
Hi,
On Sun, Dec 17, 2017 at 11:45:44PM +0100, Philipp Rossak wrote:
> This patch updates documentation for Device-Tree bindings for sunxi IR
> controller and adds the new optional property for the base clock
> frequency.
>
> Signed-off-by: Philipp Rossak <embed3d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> Documentation/devicetree/bindings/media/sunxi-ir.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
> index 91648c569b1e..9f45bab07d6e 100644
> --- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
> +++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
> @@ -11,6 +11,7 @@ Required properties:
> Optional properties:
> - linux,rc-map-name: see rc.txt file in the same directory.
> - resets : phandle + reset specifier pair
> +- clock-frequency : overrides the default base clock frequency (8 MHz)
You're at least missing the unit one needs to use, but something like:
IR Receiver clock frequency, in Hertz. Defaults to 8MHz if missing.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH net-next v5 1/4] phylib: Add device reset delay support
From: Richard Leitner @ 2017-12-18 7:30 UTC (permalink / raw)
To: Rob Herring, Richard Leitner
Cc: mark.rutland-5wv7dgnIgG8, fugang.duan-3arQi8VN3Tc,
andrew-g2DYL2Zd6BY, f.fainelli-Re5JQEeQqe8AvxtiuMwx3w,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w, davem-fT/PcQaiUtIeIZ0/mPfg9Q,
geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ,
sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8,
baruch-NswTu9S1W3P6gbPvEgmw2w, david.wu-TNX95d0MmH7DzftRWevZcw,
lukma-ynQEQJNshbs, netdev-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20171215221752.42sz53izxeebkfuq@rob-hp-laptop>
Hi Rob,
On 12/15/2017 11:17 PM, Rob Herring wrote:
> On Mon, Dec 11, 2017 at 01:16:57PM +0100, Richard Leitner wrote:
>> From: Richard Leitner <richard.leitner-WcANXNA0UjBBDgjK7y7TUQ@public.gmane.org>
>>
>> Some PHYs need a minimum time after the reset gpio was asserted and/or
>> deasserted. To ensure we meet these timing requirements add two new
>> optional devicetree parameters for the phy: reset-delay-us and
>> reset-post-delay-us.
>>
>> Signed-off-by: Richard Leitner <richard.leitner-WcANXNA0UjBBDgjK7y7TUQ@public.gmane.org>
>> Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
>> ---
>> Documentation/devicetree/bindings/net/phy.txt | 10 ++++++++++
>> drivers/net/phy/mdio_device.c | 13 +++++++++++--
>> drivers/of/of_mdio.c | 4 ++++
>> include/linux/mdio.h | 2 ++
>> 4 files changed, 27 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt
>> index c05479f5ac7c..72860ce7f610 100644
>> --- a/Documentation/devicetree/bindings/net/phy.txt
>> +++ b/Documentation/devicetree/bindings/net/phy.txt
>> @@ -55,6 +55,12 @@ Optional Properties:
>>
>> - reset-gpios: The GPIO phandle and specifier for the PHY reset signal.
>>
>> +- reset-delay-us: Delay after the reset was asserted in microseconds.
>> + If this property is missing the delay will be skipped.
>> +
>> +- reset-post-delay-us: Delay after the reset was deasserted in microseconds.
>> + If this property is missing the delay will be skipped.
>
> I think these names could be clearer as to exactly what they mean.
> Looking at existing properties with "reset-delay" there's a mixture of
> definitions whether it is the assert time or the time after deassert.
>
> So I'd call these "reset-assert-us" and "reset-deassert-us".
Ok, that would be fine with me, but are you sure that we should omit the
"-delay" term completely?
What would be the best approach to post this change (as the patchset was
already merged to net-next)? A separate patch or a v6 of the complete
patchset?
>
> Rob
>
regards;Richard.L
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^ permalink raw reply
* Re: [PATCH 00/12] Marvell NAND controller rework with ->exec_op()
From: Robert Jarzmik @ 2017-12-18 7:11 UTC (permalink / raw)
To: Boris Brezillon, Miquel Raynal
Cc: Mark Rutland, Andrew Lunn, Catalin Marinas, Hanna Hawa,
Will Deacon, Nadav Haklai, linux-mtd, Richard Weinberger,
Russell King, Marek Vasut, Ezequiel Garcia, Sebastian Hesselbarth,
devicetree, Jason Cooper, Haojian Zhuang, Rob Herring,
Gregory Clement, Ofer Heifetz, linux-arm-kernel, Thomas Petazzoni,
Eric Miao, Antoine Tenart, Cyri
In-Reply-To: <20171214070930.0b885f6d@bbrezillon>
Boris Brezillon <boris.brezillon@free-electrons.com> writes:
>> Robert, it would be great if you could also do more testing on PXA and
>> validate this driver. If needed, a branch ready to be tested is
>> available at [3]. It is based on nand/next and has all the changes
>> brought by the previously mentionned series as well as this one.
>
> Robert, do you think you'll have some time to test Miquel's branch on
> your PXA boards? Miquel already tested on one of these boards (CM-X300),
> but we'd like to have other testers. Also feel free to review the
> driver if have the time.
>
> Thanks,
>
> Boris
Hi Boris and Miquel,
I have applied the whole serie to linux-next yesterday.
A boot attempt on my zylonite with my old defconfig (with the new Marvell NAND
config activated) yields to :
- this message
[ 3.136818] marvell-nfc pxa3xx-nand: could not identify the nand chip
[ 3.143874] marvell-nfc: probe of pxa3xx-nand failed with error -22
- then my board hangs
Is there something to be done to improve the trace level so that you can guess
what's happening ?
Cheers.
--
Robert
^ permalink raw reply
* Re: [PATCH v6] mfd: syscon: Add hardware spinlock support
From: Baolin Wang @ 2017-12-18 6:54 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Lee Jones, Rob Herring, Mark Rutland, Mark Brown,
Linux Kernel Mailing List, DTML
In-Reply-To: <CAK8P3a0Eu4zaVrSEMps06ZZmFs=6026WZ7ze5V2k=nu0zL0bxQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 15 December 2017 at 21:13, Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> wrote:
> On Fri, Dec 15, 2017 at 11:42 AM, Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
>
>>> @@ -87,6 +88,30 @@ static struct syscon *of_syscon_register(struct device_node *np)
>>> if (ret)
>>> reg_io_width = 4;
>>>
>>> + ret = of_hwspin_lock_get_id(np, 0);
>>> + if (ret > 0) {
>>> + syscon_config.hwlock_id = ret;
>>> + syscon_config.hwlock_mode = HWLOCK_IRQSTATE;
>>> + } else {
>>> + switch (ret) {
>>> + case -ENOENT:
>>> + /* Ignore missing hwlock, it's optional. */
>>> + break;
>>> + case 0:
>>> + /* In case of the HWSPINLOCK is not enabled. */
>>> + if (!IS_ENABLED(CONFIG_HWSPINLOCK))
>>> + break;
>>> +
>>> + ret = -EINVAL;
>>> + /* fall-through */
>>> + default:
>>> + pr_err("Failed to retrieve valid hwlock: %d\n", ret);
>>> + /* fall-through */
>>> + case -EPROBE_DEFER:
>>> + goto err_regmap;
>>> + }
>
> The 'case 0' seems odd here, are we sure that this is always a failure?
> From the of_hwspin_lock_get_id() definition it looks like zero might
> be valid, and the !CONFIG_HWSPINLOCK implementation appears
> to be written so that we should consider '0' valid but unused and
> silently continue with that. If that is generally not the intended
> use, it should probably return -EINVAL or something like that.
Yes, 0 is valid for of_hwspin_lock_get_id(), but if we pass 'hwlock id
= 0' to regmap, the regmap core will not regard it as a valid hwlock
id to request the hwlock and will use default mutex lock instead of
hwlock, which will cause problems. Meanwhile if we silently continue
with case 0, users will not realize that they set one invalid hwlock
id to regmap core, so here we regarded case 0 as one invalid id to
print error messages for users.
--
Baolin.wang
Best Regards
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^ permalink raw reply
* [PATCH v4 36/36] dt-bindings: timer: Add andestech atcpit100 timer binding doc
From: Greentime Hu @ 2017-12-18 6:46 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial,
geert.uytterhoeven, linus.walleij, mark.rutland, greg, ren_guo,
pombredanne
Cc: Rick Chen, green.hu
In-Reply-To: <cover.1513577007.git.green.hu@gmail.com>
From: Rick Chen <rickchen36@gmail.com>
Add a document to describe Andestech atcpit100 timer and
binding information.
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../bindings/timer/andestech,atcpit100-timer.txt | 33 ++++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
diff --git a/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
new file mode 100644
index 0000000..4c9ea59
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
@@ -0,0 +1,33 @@
+Andestech ATCPIT100 timer
+------------------------------------------------------------------
+ATCPIT100 is a generic IP block from Andes Technology, embedded in
+Andestech AE3XX platforms and other designs.
+
+This timer is a set of compact multi-function timers, which can be
+used as pulse width modulators (PWM) as well as simple timers.
+
+It supports up to 4 PIT channels. Each PIT channel is a
+multi-function timer and provide the following usage scenarios:
+One 32-bit timer
+Two 16-bit timers
+Four 8-bit timers
+One 16-bit PWM
+One 16-bit timer and one 8-bit PWM
+Two 8-bit timer and one 8-bit PWM
+
+Required properties:
+- compatible : Should be "andestech,atcpit100"
+- reg : Address and length of the register set
+- interrupts : Reference to the timer interrupt
+- clocks : a clock to provide the tick rate for "andestech,atcpit100"
+- clock-names : should be "PCLK" for the peripheral clock source.
+
+Examples:
+
+timer0: timer@f0400000 {
+ compatible = "andestech,atcpit100";
+ reg = <0xf0400000 0x1000>;
+ interrupts = <2>;
+ clocks = <&apb>;
+ clock-names = "PCLK";
+};
--
1.7.9.5
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