* Re: [PATCH v5 15/15] devicetree: bindings: Document qcom,pvs
From: Viresh Kumar @ 2017-12-20 6:27 UTC (permalink / raw)
To: Sricharan R
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, andy.gross-QSEj5FYQhm4dnm+yROfE0A,
david.brown-QSEj5FYQhm4dnm+yROfE0A, rjw-LthD3rsA81gm4RdzfppkhA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA, linux-pm-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <b0d8147a-46e1-0787-ae37-9c1ef957d190-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On 20-12-17, 11:55, Sricharan R wrote:
> >> + opp-1400000000 {
> >> + opp-hz = /bits/ 64 <1400000000>;
> >> + opp-microvolt-speed0-pvs0-v0 = <1250000>;
> >
> > Why speed0 and v0 in all the names ?
> >
>
> Ya, all the three (speed, pvs and version) are read from efuse. So all the three
> can vary.
Okay, so may be in the example you should have a mix of all the
combinations to show how these things work ? You only showed values
for a single efuse configuration currently.
--
viresh
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* Re: [PATCH v5 15/15] devicetree: bindings: Document qcom,pvs
From: Sricharan R @ 2017-12-20 6:25 UTC (permalink / raw)
To: Viresh Kumar
Cc: robh+dt, mark.rutland, mturquette, sboyd, linux, andy.gross,
david.brown, rjw, linux-arm-kernel, devicetree, linux-kernel,
linux-clk, linux-arm-msm, linux-soc, linux-pm
In-Reply-To: <20171220032614.GQ19815@vireshk-i7>
Hi Viresh,
On 12/20/2017 8:56 AM, Viresh Kumar wrote:
> On 19-12-17, 21:25, Sricharan R wrote:
>> + cpu@0 {
>> + compatible = "qcom,krait";
>> + enable-method = "qcom,kpss-acc-v1";
>> + device_type = "cpu";
>> + reg = <0>;
>> + qcom,acc = <&acc0>;
>> + qcom,saw = <&saw0>;
>> + clocks = <&kraitcc 0>;
>> + clock-names = "cpu";
>> + cpu-supply = <&smb208_s2a>;
>> + operating-points-v2 = <&cpu_opp_table>;
>> + };
>> +
>> + qcom,pvs {
>> + qcom,pvs-format-a;
>> + };
>
> Not sure what Rob is going to say on that :)
>
Yes. Would be good to know the best way.
>> +
>> +
>> + cpu_opp_table: opp_table {
>> + compatible = "operating-points-v2";
>> +
>> + /*
>> + * Missing opp-shared property means CPUs switch DVFS states
>> + * independently.
>> + */
>> +
>> + opp-1400000000 {
>> + opp-hz = /bits/ 64 <1400000000>;
>> + opp-microvolt-speed0-pvs0-v0 = <1250000>;
>
> Why speed0 and v0 in all the names ?
>
Ya, all the three (speed, pvs and version) are read from efuse. So all the three
can vary.
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* Re: [PATCH v5 14/15] cpufreq: Add module to register cpufreq on Krait CPUs
From: Sricharan R @ 2017-12-20 6:19 UTC (permalink / raw)
To: Viresh Kumar
Cc: mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA, rjw-LthD3rsA81gm4RdzfppkhA,
mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
david.brown-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
andy.gross-QSEj5FYQhm4dnm+yROfE0A,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20171220033608.GR19815@vireshk-i7>
Hi Viresh,
On 12/20/2017 9:06 AM, Viresh Kumar wrote:
> On 19-12-17, 21:24, Sricharan R wrote:
>> From: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>>
>> Register a cpufreq-generic device whenever we detect that a
>> "qcom,krait" compatible CPU is present in DT.
>>
>> Cc: <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
>> [Sricharan: updated to use dev_pm_opp_set_prop_name]
>> Signed-off-by: Sricharan R <sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>> Signed-off-by: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>> ---
>> drivers/cpufreq/Kconfig.arm | 9 ++
>> drivers/cpufreq/Makefile | 1 +
>> drivers/cpufreq/cpufreq-dt-platdev.c | 3 +-
>> drivers/cpufreq/qcom-cpufreq.c | 171 +++++++++++++++++++++++++++++++++++
>> 4 files changed, 183 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/cpufreq/qcom-cpufreq.c
>>
>> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
>> index bdce448..60f28e7 100644
>> --- a/drivers/cpufreq/Kconfig.arm
>> +++ b/drivers/cpufreq/Kconfig.arm
>> @@ -100,6 +100,15 @@ config ARM_OMAP2PLUS_CPUFREQ
>> depends on ARCH_OMAP2PLUS
>> default ARCH_OMAP2PLUS
>>
>> +config ARM_QCOM_CPUFREQ
>> + tristate "Qualcomm based"
>
> Qualcomm based ... ? You want to add something after this ?
>
Hmm, got truncated. Will add a proper one.
> And why tristate ? Do you really want to build a module for this ?
>
Given that cpufreq-dt that registers the driver already supports module,
don't think this needs to be a module. So will make it a bool.
>> + depends on ARCH_QCOM
>> + select PM_OPP
>> + help
>> + This adds the CPUFreq driver for Qualcomm SoC based boards.
>> +
>> + If in doubt, say N.
>> +
>> config ARM_S3C_CPUFREQ
>> bool
>> help
>> diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
>> index 812f9e0..1496464 100644
>> --- a/drivers/cpufreq/Makefile
>> +++ b/drivers/cpufreq/Makefile
>> @@ -62,6 +62,7 @@ obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ) += mediatek-cpufreq.o
>> obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
>> obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
>> obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
>> +obj-$(CONFIG_ARM_QCOM_CPUFREQ) += qcom-cpufreq.o
>> obj-$(CONFIG_ARM_S3C24XX_CPUFREQ) += s3c24xx-cpufreq.o
>> obj-$(CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS) += s3c24xx-cpufreq-debugfs.o
>> obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o
>> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
>> index ecc56e2..032ac4f 100644
>> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
>> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
>> @@ -118,7 +118,7 @@
>> { .compatible = "ti,am33xx", },
>> { .compatible = "ti,am43", },
>> { .compatible = "ti,dra7", },
>> -
>
> Keep this blank line as is..
>
ok
>> + { .compatible = "qcom,ipq8064", },
>
> And add another one here.
>
ok
>> { }
>> };
>>
>> @@ -157,6 +157,7 @@ static int __init cpufreq_dt_platdev_init(void)
>>
>> create_pdev:
>> of_node_put(np);
>> +
>
> Remove this.
>
ok
>> return PTR_ERR_OR_ZERO(platform_device_register_data(NULL, "cpufreq-dt",
>> -1, data,
>> sizeof(struct cpufreq_dt_platform_data)));
>> diff --git a/drivers/cpufreq/qcom-cpufreq.c b/drivers/cpufreq/qcom-cpufreq.c
>> new file mode 100644
>> index 0000000..3e5583d
>> --- /dev/null
>> +++ b/drivers/cpufreq/qcom-cpufreq.c
>> @@ -0,0 +1,171 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +// Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
>> +
>> +#include <linux/cpu.h>
>> +#include <linux/err.h>
>> +#include <linux/init.h>
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pm_opp.h>
>> +#include <linux/slab.h>
>> +#include "cpufreq-dt.h"
>> +
>> +static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver)
>> +{
>> + void __iomem *base;
>> + u32 pte_efuse;
>> +
>> + *speed = *pvs = *pvs_ver = 0;
>> +
>> + base = ioremap(0x007000c0, 4);
>> + if (!base) {
>> + pr_warn("Unable to read efuse data. Defaulting to 0!\n");
>> + return;
>> + }
>> +
>> + pte_efuse = readl_relaxed(base);
>> + iounmap(base);
>> +
>> + *speed = pte_efuse & 0xf;
>> + if (*speed == 0xf)
>> + *speed = (pte_efuse >> 4) & 0xf;
>> +
>> + if (*speed == 0xf) {
>> + *speed = 0;
>> + pr_warn("Speed bin: Defaulting to %d\n", *speed);
>> + } else {
>> + pr_info("Speed bin: %d\n", *speed);
>> + }
>> +
>> + *pvs = (pte_efuse >> 10) & 0x7;
>> + if (*pvs == 0x7)
>> + *pvs = (pte_efuse >> 13) & 0x7;
>> +
>> + if (*pvs == 0x7) {
>> + *pvs = 0;
>> + pr_warn("PVS bin: Defaulting to %d\n", *pvs);
>> + } else {
>> + pr_info("PVS bin: %d\n", *pvs);
>> + }
>> +}
>> +
>> +static void __init get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver)
>> +{
>> + u32 pte_efuse, redundant_sel;
>> + void __iomem *base;
>> +
>> + *speed = 0;
>> + *pvs = 0;
>> + *pvs_ver = 0;
>> +
>> + base = ioremap(0xfc4b80b0, 8);
>> + if (!base) {
>> + pr_warn("Unable to read efuse data. Defaulting to 0!\n");
>> + return;
>> + }
>> +
>> + pte_efuse = readl_relaxed(base);
>> + redundant_sel = (pte_efuse >> 24) & 0x7;
>> + *speed = pte_efuse & 0x7;
>> + /* 4 bits of PVS are in efuse register bits 31, 8-6. */
>> + *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
>> + *pvs_ver = (pte_efuse >> 4) & 0x3;
>> +
>> + switch (redundant_sel) {
>> + case 1:
>> + *speed = (pte_efuse >> 27) & 0xf;
>> + break;
>> + case 2:
>> + *pvs = (pte_efuse >> 27) & 0xf;
>> + break;
>> + }
>> +
>> + /* Check SPEED_BIN_BLOW_STATUS */
>> + if (pte_efuse & BIT(3)) {
>> + pr_info("Speed bin: %d\n", *speed);
>> + } else {
>> + pr_warn("Speed bin not set. Defaulting to 0!\n");
>> + *speed = 0;
>> + }
>> +
>> + /* Check PVS_BLOW_STATUS */
>> + pte_efuse = readl_relaxed(base + 0x4) & BIT(21);
>> + if (pte_efuse) {
>> + pr_info("PVS bin: %d\n", *pvs);
>> + } else {
>> + pr_warn("PVS bin not set. Defaulting to 0!\n");
>> + *pvs = 0;
>> + }
>> +
>> + pr_info("PVS version: %d\n", *pvs_ver);
>> + iounmap(base);
>> +}
>> +
>> +static int __init qcom_cpufreq_populate_opps(void)
>> +{
>> + int speed, pvs, pvs_ver;
>> + struct device_node *np;
>> + struct device *dev;
>> + int cpu = 0;
>> + char pvs_name[] = "speedXX-pvsXX-vXX";
>> +
>> + np = of_find_node_by_name(NULL, "qcom,pvs");
>> + if (!np)
>> + return -ENODEV;
>> +
>> + if (of_property_read_bool(np, "qcom,pvs-format-a"))
>> + get_krait_bin_format_a(&speed, &pvs, &pvs_ver);
>> + else if (of_property_read_bool(np, "qcom,pvs-format-b"))
>> + get_krait_bin_format_b(&speed, &pvs, &pvs_ver);
>> + else
>> + return -ENODEV;
>> +
>> + snprintf(pvs_name, sizeof(pvs_name), "speed%d-pvs%d-v%d",
>> + speed, pvs, pvs_ver);
>> +
>> + for (cpu = 0; cpu < num_possible_cpus(); cpu++) {
>> + dev = get_cpu_device(cpu);
>> + if (!dev)
>> + return -ENODEV;
>> +
>> + if (IS_ERR(dev_pm_opp_set_prop_name(dev, pvs_name)))
>> + pr_warn("failed to add OPP name %s\n", pvs_name);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int __init qcom_cpufreq_driver_init(void)
>> +{
>> + struct device *cpu_dev;
>> + struct device_node *np;
>> + int ret;
>> +
>> + cpu_dev = get_cpu_device(0);
>> + if (!cpu_dev)
>> + return -ENODEV;
>> +
>> + np = of_node_get(cpu_dev->of_node);
>> + if (!np)
>> + return -ENOENT;
>> +
>> + if (!of_device_is_compatible(np, "qcom,krait")) {
>> + of_node_put(np);
>> + return -ENODEV;
>> + }
>> + of_node_put(np);
>> +
>> + ret = qcom_cpufreq_populate_opps();
>> + if (ret)
>> + return ret;
>> +
>> + return PTR_ERR(platform_device_register_simple("cpufreq-dt",
>> + -1, NULL, 0));
>> +}
>> +module_init(qcom_cpufreq_driver_init);
>
> As there is no module exit, it doesn't make sense to keep this as
> tristate.
>
ok
> Looks mostly fine now other than these minor nits.
>
Ok, Thanks for the review. Will wait on feedback for rest of the patches
and repost with these fixed.
Regards,
Sricharan
--
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* RE: [PATCH v2] arm64: dts: ls1088a: Add USB support
From: Yinbo Zhu @ 2017-12-20 4:42 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Mark Rutland, Catalin Marinas ), Will Deacon ),
Harninder Rai, Raghav Dogra, Ashish Kumar, Andy Tang,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Ran Wang,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
open list
In-Reply-To: <20171220025239.GB3766@dragon>
-----Original Message-----
From: Shawn Guo [mailto:shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
Sent: Wednesday, December 20, 2017 10:53 AM
To: Yinbo Zhu <yinbo.zhu-3arQi8VN3Tc@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>; Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>; Catalin Marinas ) <catalin.marinas-5wv7dgnIgG8@public.gmane.org>; Will Deacon ) <will.deacon@arm.com>; Harninder Rai <harninder.rai-3arQi8VN3Tc@public.gmane.org>; Raghav Dogra <raghav.dogra@nxp.com>; Ashish Kumar <ashish.kumar-3arQi8VN3Tc@public.gmane.org>; Andy Tang <andy.tang-3arQi8VN3Tc@public.gmane.org>; open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] arm64: dts: ls1088a: Add USB support
On Thu, Dec 07, 2017 at 07:33:28AM +0000, Yinbo Zhu wrote:
> Hi shawn guo,
>
> If my patch has no other issue,
> Can you help me push it to upstream.
>Are you talking about v4 patch? First of all, I cannot find v4 in my mailbox. That said, it seems you did not send
>the patch to me.
>Secondly, by checking the patch on patchwork, the usb nodes in fsl-ls1088a-rdb.dts do not sorted alphabetically
>in label name.
>Shawn
Hi shawn,
I will change the code as follows, right?
&esdhc {
status = "okay";
};
...
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
https://patchwork.kernel.org/patch/10059097/
Thanks
Yinbo.
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* [PATCH] RISC-V: Support built-in dtb
From: Zong Li @ 2017-12-20 4:20 UTC (permalink / raw)
To: palmer-SpMDHPYPyPbQT0dZR+AlfA, albert-SpMDHPYPyPbQT0dZR+AlfA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
wesley-SpMDHPYPyPbQT0dZR+AlfA, patches-q3qR2WxjNRFS9aJRtSZj7A,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
greentime-MUIXKm3Oiri1Z/+hSey0Gg, zong-MUIXKm3Oiri1Z/+hSey0Gg
Cc: Zong Li
Build the dtb into the kernel image.
If the DTB is given via bootloader, the external DTB is adopted first.
Signed-off-by: Zong Li <zongbox-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/riscv/Kconfig | 4 ++++
arch/riscv/Makefile | 9 +++++++++
arch/riscv/boot/Makefile | 17 +++++++++++++++++
arch/riscv/boot/dts/Makefile | 11 +++++++++++
arch/riscv/kernel/setup.c | 2 +-
5 files changed, 42 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/boot/Makefile
create mode 100644 arch/riscv/boot/dts/Makefile
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 2e15e85..831cbb9 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -189,6 +189,10 @@ config RISCV_ISA_C
config RISCV_ISA_A
def_bool y
+config RISCV_BUILTIN_DTB
+ string "Builtin DTB"
+ default ""
+
endmenu
menu "Kernel type"
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 6719dd3..baed60a 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -57,6 +57,12 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
KBUILD_CFLAGS += -mcmodel=medany
endif
+ifneq '$(CONFIG_NDS32_BUILTIN_DTB)' '""'
+BUILTIN_DTB := y
+else
+BUILTIN_DTB := n
+endif
+
# GCC versions that support the "-mstrict-align" option default to allowing
# unaligned accesses. While unaligned accesses are explicitly allowed in the
# RISC-V ISA, they're emulated by machine mode traps on all extant
@@ -69,4 +75,7 @@ core-y += arch/riscv/kernel/ arch/riscv/mm/
libs-y += arch/riscv/lib/
+boot := arch/riscv/boot
+core-$(BUILTIN_DTB) += $(boot)/dts/
+
all: vmlinux
diff --git a/arch/riscv/boot/Makefile b/arch/riscv/boot/Makefile
new file mode 100644
index 0000000..003d697
--- /dev/null
+++ b/arch/riscv/boot/Makefile
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0
+
+targets := Image Image.gz
+
+$(obj)/Image: vmlinux FORCE
+ $(call if_changed,objcopy)
+
+$(obj)/Image.gz: $(obj)/Image FORCE
+ $(call if_changed,gzip)
+
+install: $(obj)/Image
+ $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
+ $(obj)/Image System.map "$(INSTALL_PATH)"
+
+zinstall: $(obj)/Image.gz
+ $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
+ $(obj)/Image.gz System.map "$(INSTALL_PATH)"
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
new file mode 100644
index 0000000..b65d070
--- /dev/null
+++ b/arch/riscv/boot/dts/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0
+
+ifneq '$(CONFIG_RISCV_BUILTIN_DTB)' '""'
+BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_RISCV_BUILTIN_DTB)).dtb.o
+else
+BUILTIN_DTB :=
+endif
+
+obj-$(CONFIG_OF) += $(BUILTIN_DTB)
+
+clean-files := *.dtb *.dtb.S
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index e59a28c..3c89f3d 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -149,7 +149,7 @@ asmlinkage void __init setup_vm(void)
void __init sbi_save(unsigned int hartid, void *dtb)
{
- early_init_dt_scan(__va(dtb));
+ early_init_dt_scan(dtb ? __va(dtb) : __dtb_start);
}
/*
--
2.7.4
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^ permalink raw reply related
* Re: [PATCH 1/4] pci: dwc: pci-dra7xx: Enable errata i870 for both EP and RC mode
From: Vignesh R @ 2017-12-20 4:15 UTC (permalink / raw)
To: Lorenzo Pieralisi, KISHON VIJAY ABRAHAM
Cc: devicetree@vger.kernel.org, Tony Lindgren,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
Rob Herring, Chris Welch, Bjorn Helgaas,
linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20171219162421.GD21501@red-moon>
On Tuesday 19 December 2017 09:54 PM, Lorenzo Pieralisi wrote:
> On Fri, Dec 01, 2017 at 11:43:08AM +0530, Vignesh R wrote:
>> Errata i870 is applicable in both EP and RC mode. Therefore rename
>> function dra7xx_pcie_ep_unaligned_memaccess(), that implements errata
>> workaround, to dra7xx_pcie_unaligned_memaccess() and call it from a
>> common place. So, that errata workaround is applied for both modes of
>> operation.
>>
>> Reported-by: Chris Welch <Chris.Welch@viavisolutions.com>
>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>> ---
>> drivers/pci/dwc/pci-dra7xx.c | 12 ++++++------
>> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> I need Kishon's ACK to apply it, thanks.
There are some enhancements to this patch. Will submit a v2 shortly.
Please ignore this version for now. Thanks!
--
Regards
Vignesh
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v15 5/5] dt-bindings: watchdog: Add bindings for RAVE SP watchdog driver
From: Andrey Smirnov @ 2017-12-20 4:00 UTC (permalink / raw)
To: Lee Jones
Cc: Andrey Smirnov, linux-kernel, devicetree, linux-watchdog, cphealy,
Lucas Stach, Nikita Yushchenko, Greg Kroah-Hartman, Pavel Machek,
Andy Shevchenko, Guenter Roeck, Rob Herring, Johan Hovold,
Mark Rutland, Sebastian Reichel
In-Reply-To: <20171220040017.7605-1-andrew.smirnov@gmail.com>
Add Device Tree bindings for RAVE SP watchdog drvier - an MFD cell of
parent RAVE SP driver (documented in
Documentation/devicetree/bindings/mfd/zii,rave-sp.txt).
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-watchdog@vger.kernel.org
Cc: cphealy@gmail.com
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Rob Herring <robh@kernel.org>
Cc: Johan Hovold <johan@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Pavel Machek <pavel@ucw.cz>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
.../bindings/watchdog/zii,rave-sp-wdt.txt | 39 ++++++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt
diff --git a/Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt b/Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt
new file mode 100644
index 000000000000..3de96186e92e
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt
@@ -0,0 +1,39 @@
+Zodiac Inflight Innovations RAVE Supervisory Processor Watchdog Bindings
+
+RAVE SP watchdog device is a "MFD cell" device corresponding to
+watchdog functionality of RAVE Supervisory Processor. It is expected
+that its Device Tree node is specified as a child of the node
+corresponding to the parent RAVE SP device (as documented in
+Documentation/devicetree/bindings/mfd/zii,rave-sp.txt)
+
+Required properties:
+
+- compatible: Depending on wire protocol implemented by RAVE SP
+ firmware, should be one of:
+ - "zii,rave-sp-watchdog"
+ - "zii,rave-sp-watchdog-legacy"
+
+Optional properties:
+
+- wdt-timeout: Two byte nvmem cell specified as per
+ Documentation/devicetree/bindings/nvmem/nvmem.txt
+
+Example:
+
+ rave-sp {
+ compatible = "zii,rave-sp-rdu1";
+ current-speed = <38400>;
+
+ eeprom {
+ wdt_timeout: wdt-timeout@8E {
+ reg = <0x8E 2>;
+ };
+ };
+
+ watchdog {
+ compatible = "zii,rave-sp-watchdog";
+ nvmem-cells = <&wdt_timeout>;
+ nvmem-cell-names = "wdt-timeout";
+ };
+ }
+
--
2.14.3
^ permalink raw reply related
* [PATCH v15 0/5] ZII RAVE platform driver
From: Andrey Smirnov @ 2017-12-20 4:00 UTC (permalink / raw)
To: Lee Jones
Cc: Andrey Smirnov, Pavel Machek, Greg Kroah-Hartman,
cphealy-Re5JQEeQqe8AvxtiuMwx3w, Andy Shevchenko, Lucas Stach,
Nikita Yushchenko, Guenter Roeck, Rob Herring, Mark Rutland,
Johan Hovold, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Sebastian Reichel
Everyone:
This patch series is v15 of the driver for supervisory processor found
on RAVE series of devices from ZII. Supervisory processor is a PIC
microcontroller connected to various electrical subsystems on RAVE
devices whose firmware implements protocol to command/qery them.
NOTE:
* This driver dependends on crc_ccitt_false(), added by
2da9378d531f8cc6670c7497f20d936b706ab80b in 'linux-next', the patch
was pulled in by Andrew Morton and is currently avaiting users, so
this series might have to go in through Andrew's tree
Changes since [v14]:
- Fixed a bug in deframer code where byte processing loop was not
being terminated early is it should've been. This would result,
among other things, in packets of maximum valid length being
incorrectly reported as tool long.
- Increased command timeout value in support other valid commands
that are outsied of scope for this patch set.
- Converted watchdog driver to differentiate between variants
based on its own compatiblity string as opposed to relying on
that of parent MFD device (as per request by Johan and Lee).
NOTE: This change didn't seem to change DT bingins enough to
warrant dropping any Acks for patches affected, so I kept
them. If anyone wants to rescind their Ack, please let me know.
- Collected Acked-by from Pavel
- Collected Acked-by from Lee (for patch 3/5)
Changes since [v13]:
- Fixed incorrect MFD driver menuconfig entry placement
Changes since [v12]:
- Minor comment inconsistencies fixes in rave-sp.c
Changes since [v11]:
- Fix incorrect include in rave-sp-wdt.c as uncovered by kernel
test robot
Changes since [v10]:
- Collected Acked-by from Rob and Reviewed-by from Guenter
- Incorporated watchdog driver feedback from Gunter and Johan
- Incorporated Johan's feedback for the rest of the code
Changes since [v9]:
- Converted watchdog driver to use watchdog_active() instead of
watchdog_hw_running() and replaced WARN_ON with a regular error
message as per feedback from Guenter
- Changed rave_sp_wdt_start() to set WDOG_HW_RUNNING only if
communicating with hardware was sucessful
- Collected Reviewd-by from Sebastian (for serdev related patches)
- Collected Acked-by from Rob (for watchdog DT bindings)
Changes since [v8]:
- Driver moved from drivers/platform to drivers/mfd
- Collected Reviewed-by from Guenter (for patches 1, 2 and 3)
- Incorporated feedback from Guenter into watchdog driver
- Incorporated feedback from Rob into watchdog DT bindings
- Removed struct rave_sp_rsp_status, which was a leftover from v5
-> v6 code removal.
- Fixed minor problems reported by checkpatch
Changes since [v7]:
- Added watchdog driver to the patchset, so it would be easier to
understand how parent/children drivers are tied together
- Added serdev patches to implement devm_serdev_device_open() and make .remove optional
- "Added" missing serdev_device_close() by converting the driver
to use devm_serdev_device_open()
- Converted the driver to use devm_of_platform_populate()
- Removed needless dependency on MFD_CORE
- Removed dependency on SERIAL_DEV_CTRL_TTYPORT
Changes since [v6]:
- Patch 2/2 has been applied by Lee so it is no longer a part of the series
- Removed all sysfs and debugfs attribute to reduce the scope of
the driver propsed for inclusion. This is not a critical to have
feature and can be added/discussed later.
Changes since [v5]:
- Fixed a build break, introduced by a last minute change in [v5]
- Moved majority of attributes that were exposed over sysfs to debugfs
- Document remaining sysfs attributes in Documentation/ABI/testing/sysfs-platform-rave-sp
Changes since [v4]:
- Replaced usage of DEVICE_ATTR with DEVICE_ATTR_RW
- Fixed a number of warnings produces by sparse tool
- Incorporated event more feedback from Andy Shevchenko
- Collected Reviewed-by from Andy
Changes since [v3]:
- Re-collected lost Acked-by from Rob
- Incorporated further feedback from Andy Shevchenko
- Dropped useless change (stray newline) to drivers/mfd/Makefile
Changes since [v2]:
- Fixed swapped command codes in rave_sp_common_get_boot_source()
and rave_sp_common_set_boot_source() revealed by further testing
of the code
- Incorporated feedback from Andy Shevchenko
Changes since [v1]:
- Updated wording in DT-bindings as per Rob's request.
- Collected Rob's Acked-by for patch 2/2
Feedback is greatly appreciated!
Thanks,
Andrey Smirnov
[v14] lkml.kernel.org/r/20171207162735.25873-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v13] lkml.kernel.org/r/20171204161118.19558-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v12] lkml.kernel.org/r/20171109160556.17018-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v11] lkml.kernel.org/r/20171106152935.16920-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v10] lkml.kernel.org/r/20171031163656.24552-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v9] lkml.kernel.org/r/20171025190421.18415-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v8] lkml.kernel.org/r/20171018170136.12347-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v7] lkml.kernel.org/r/20171013061321.31252-2-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v6] lkml.kernel.org/r/20170828163131.24815-2-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v5] lkml.kernel.org/r/20170728142704.11156-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v4] lkml.kernel.org/r/20170725184450.13171-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v3] lkml.kernel.org/r/20170724150915.4824-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v2] lkml.kernel.org/r/20170718175604.11735-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
[v1] lkml.kernel.org/r/20170710170449.4544-1-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Andrey Smirnov (5):
serdev: Make .remove in struct serdev_device_driver optional
serdev: Introduce devm_serdev_device_open()
mfd: Add driver for RAVE Supervisory Processor
watchdog: Add RAVE SP watchdog driver
dt-bindings: watchdog: Add bindings for RAVE SP watchdog driver
.../bindings/watchdog/zii,rave-sp-wdt.txt | 39 ++
Documentation/driver-model/devres.txt | 3 +
drivers/mfd/Kconfig | 8 +
drivers/mfd/Makefile | 2 +
drivers/mfd/rave-sp.c | 720 +++++++++++++++++++++
drivers/tty/serdev/core.c | 31 +-
drivers/watchdog/Kconfig | 7 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/rave-sp-wdt.c | 348 ++++++++++
include/linux/mfd/rave-sp.h | 52 ++
include/linux/serdev.h | 1 +
11 files changed, 1210 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt
create mode 100644 drivers/mfd/rave-sp.c
create mode 100644 drivers/watchdog/rave-sp-wdt.c
create mode 100644 include/linux/mfd/rave-sp.h
--
2.14.3
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^ permalink raw reply
* Re: [PATCH v3 00/19] ARM: dts: aspeed: updates and new machines
From: Joel Stanley @ 2017-12-20 3:37 UTC (permalink / raw)
To: Arnd Bergmann, Stephen Boyd, Michael Turquette, Rob Herring
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, Andrew Jeffery, Linux ARM, Linux Kernel Mailing List,
linux-aspeed-uLR06cmDAlY/bJ5BZ2RsiQ, Patrick Venture, Xo Wang,
Lei YU, Mark Rutland
In-Reply-To: <20171220032328.30584-1-joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
On Wed, Dec 20, 2017 at 1:53 PM, Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org> wrote:
> This series of device tree patches for the ASPEED BMC machines
> moves all systems to use the soon to be merged clk driver, and
> updates machines to use all of the drivers we have upstream.
>
> v3: Address review from Rob and Cedric
> - Move aspeed-gpio.h usage out into the patches where use of the GPIO
> is added
> - Clarify that the aspeed-clock.h patch will be merged as part of
> the device tree tree. This is to ensure we don't depend on the clk
> tree for building.
Arnd, Michael, Stephen; how do we resolve this? We need the
dt-bindings header to be present for both the clk driver and the
device tree to build.
The clk driver is not (yet - soon I hope?) merged by Michael and
Stephen. I am about to commit the device tree changes that will go
through the ARM SoC tree.
Cheers,
Joel
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^ permalink raw reply
* Re: [PATCH v5 14/15] cpufreq: Add module to register cpufreq on Krait CPUs
From: Viresh Kumar @ 2017-12-20 3:36 UTC (permalink / raw)
To: Sricharan R
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, andy.gross-QSEj5FYQhm4dnm+yROfE0A,
david.brown-QSEj5FYQhm4dnm+yROfE0A, rjw-LthD3rsA81gm4RdzfppkhA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA, linux-pm-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1513698900-10638-15-git-send-email-sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On 19-12-17, 21:24, Sricharan R wrote:
> From: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>
> Register a cpufreq-generic device whenever we detect that a
> "qcom,krait" compatible CPU is present in DT.
>
> Cc: <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
> [Sricharan: updated to use dev_pm_opp_set_prop_name]
> Signed-off-by: Sricharan R <sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> Signed-off-by: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
> drivers/cpufreq/Kconfig.arm | 9 ++
> drivers/cpufreq/Makefile | 1 +
> drivers/cpufreq/cpufreq-dt-platdev.c | 3 +-
> drivers/cpufreq/qcom-cpufreq.c | 171 +++++++++++++++++++++++++++++++++++
> 4 files changed, 183 insertions(+), 1 deletion(-)
> create mode 100644 drivers/cpufreq/qcom-cpufreq.c
>
> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index bdce448..60f28e7 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -100,6 +100,15 @@ config ARM_OMAP2PLUS_CPUFREQ
> depends on ARCH_OMAP2PLUS
> default ARCH_OMAP2PLUS
>
> +config ARM_QCOM_CPUFREQ
> + tristate "Qualcomm based"
Qualcomm based ... ? You want to add something after this ?
And why tristate ? Do you really want to build a module for this ?
> + depends on ARCH_QCOM
> + select PM_OPP
> + help
> + This adds the CPUFreq driver for Qualcomm SoC based boards.
> +
> + If in doubt, say N.
> +
> config ARM_S3C_CPUFREQ
> bool
> help
> diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
> index 812f9e0..1496464 100644
> --- a/drivers/cpufreq/Makefile
> +++ b/drivers/cpufreq/Makefile
> @@ -62,6 +62,7 @@ obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ) += mediatek-cpufreq.o
> obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
> obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
> obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
> +obj-$(CONFIG_ARM_QCOM_CPUFREQ) += qcom-cpufreq.o
> obj-$(CONFIG_ARM_S3C24XX_CPUFREQ) += s3c24xx-cpufreq.o
> obj-$(CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS) += s3c24xx-cpufreq-debugfs.o
> obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> index ecc56e2..032ac4f 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -118,7 +118,7 @@
> { .compatible = "ti,am33xx", },
> { .compatible = "ti,am43", },
> { .compatible = "ti,dra7", },
> -
Keep this blank line as is..
> + { .compatible = "qcom,ipq8064", },
And add another one here.
> { }
> };
>
> @@ -157,6 +157,7 @@ static int __init cpufreq_dt_platdev_init(void)
>
> create_pdev:
> of_node_put(np);
> +
Remove this.
> return PTR_ERR_OR_ZERO(platform_device_register_data(NULL, "cpufreq-dt",
> -1, data,
> sizeof(struct cpufreq_dt_platform_data)));
> diff --git a/drivers/cpufreq/qcom-cpufreq.c b/drivers/cpufreq/qcom-cpufreq.c
> new file mode 100644
> index 0000000..3e5583d
> --- /dev/null
> +++ b/drivers/cpufreq/qcom-cpufreq.c
> @@ -0,0 +1,171 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
> +
> +#include <linux/cpu.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/slab.h>
> +#include "cpufreq-dt.h"
> +
> +static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver)
> +{
> + void __iomem *base;
> + u32 pte_efuse;
> +
> + *speed = *pvs = *pvs_ver = 0;
> +
> + base = ioremap(0x007000c0, 4);
> + if (!base) {
> + pr_warn("Unable to read efuse data. Defaulting to 0!\n");
> + return;
> + }
> +
> + pte_efuse = readl_relaxed(base);
> + iounmap(base);
> +
> + *speed = pte_efuse & 0xf;
> + if (*speed == 0xf)
> + *speed = (pte_efuse >> 4) & 0xf;
> +
> + if (*speed == 0xf) {
> + *speed = 0;
> + pr_warn("Speed bin: Defaulting to %d\n", *speed);
> + } else {
> + pr_info("Speed bin: %d\n", *speed);
> + }
> +
> + *pvs = (pte_efuse >> 10) & 0x7;
> + if (*pvs == 0x7)
> + *pvs = (pte_efuse >> 13) & 0x7;
> +
> + if (*pvs == 0x7) {
> + *pvs = 0;
> + pr_warn("PVS bin: Defaulting to %d\n", *pvs);
> + } else {
> + pr_info("PVS bin: %d\n", *pvs);
> + }
> +}
> +
> +static void __init get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver)
> +{
> + u32 pte_efuse, redundant_sel;
> + void __iomem *base;
> +
> + *speed = 0;
> + *pvs = 0;
> + *pvs_ver = 0;
> +
> + base = ioremap(0xfc4b80b0, 8);
> + if (!base) {
> + pr_warn("Unable to read efuse data. Defaulting to 0!\n");
> + return;
> + }
> +
> + pte_efuse = readl_relaxed(base);
> + redundant_sel = (pte_efuse >> 24) & 0x7;
> + *speed = pte_efuse & 0x7;
> + /* 4 bits of PVS are in efuse register bits 31, 8-6. */
> + *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
> + *pvs_ver = (pte_efuse >> 4) & 0x3;
> +
> + switch (redundant_sel) {
> + case 1:
> + *speed = (pte_efuse >> 27) & 0xf;
> + break;
> + case 2:
> + *pvs = (pte_efuse >> 27) & 0xf;
> + break;
> + }
> +
> + /* Check SPEED_BIN_BLOW_STATUS */
> + if (pte_efuse & BIT(3)) {
> + pr_info("Speed bin: %d\n", *speed);
> + } else {
> + pr_warn("Speed bin not set. Defaulting to 0!\n");
> + *speed = 0;
> + }
> +
> + /* Check PVS_BLOW_STATUS */
> + pte_efuse = readl_relaxed(base + 0x4) & BIT(21);
> + if (pte_efuse) {
> + pr_info("PVS bin: %d\n", *pvs);
> + } else {
> + pr_warn("PVS bin not set. Defaulting to 0!\n");
> + *pvs = 0;
> + }
> +
> + pr_info("PVS version: %d\n", *pvs_ver);
> + iounmap(base);
> +}
> +
> +static int __init qcom_cpufreq_populate_opps(void)
> +{
> + int speed, pvs, pvs_ver;
> + struct device_node *np;
> + struct device *dev;
> + int cpu = 0;
> + char pvs_name[] = "speedXX-pvsXX-vXX";
> +
> + np = of_find_node_by_name(NULL, "qcom,pvs");
> + if (!np)
> + return -ENODEV;
> +
> + if (of_property_read_bool(np, "qcom,pvs-format-a"))
> + get_krait_bin_format_a(&speed, &pvs, &pvs_ver);
> + else if (of_property_read_bool(np, "qcom,pvs-format-b"))
> + get_krait_bin_format_b(&speed, &pvs, &pvs_ver);
> + else
> + return -ENODEV;
> +
> + snprintf(pvs_name, sizeof(pvs_name), "speed%d-pvs%d-v%d",
> + speed, pvs, pvs_ver);
> +
> + for (cpu = 0; cpu < num_possible_cpus(); cpu++) {
> + dev = get_cpu_device(cpu);
> + if (!dev)
> + return -ENODEV;
> +
> + if (IS_ERR(dev_pm_opp_set_prop_name(dev, pvs_name)))
> + pr_warn("failed to add OPP name %s\n", pvs_name);
> + }
> +
> + return 0;
> +}
> +
> +static int __init qcom_cpufreq_driver_init(void)
> +{
> + struct device *cpu_dev;
> + struct device_node *np;
> + int ret;
> +
> + cpu_dev = get_cpu_device(0);
> + if (!cpu_dev)
> + return -ENODEV;
> +
> + np = of_node_get(cpu_dev->of_node);
> + if (!np)
> + return -ENOENT;
> +
> + if (!of_device_is_compatible(np, "qcom,krait")) {
> + of_node_put(np);
> + return -ENODEV;
> + }
> + of_node_put(np);
> +
> + ret = qcom_cpufreq_populate_opps();
> + if (ret)
> + return ret;
> +
> + return PTR_ERR(platform_device_register_simple("cpufreq-dt",
> + -1, NULL, 0));
> +}
> +module_init(qcom_cpufreq_driver_init);
As there is no module exit, it doesn't make sense to keep this as
tristate.
Looks mostly fine now other than these minor nits.
--
viresh
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^ permalink raw reply
* Re: [v2] arm: dts: ls1021a: fix the value of TMR_FIPER1
From: Shawn Guo @ 2017-12-20 3:33 UTC (permalink / raw)
To: Y.b. Lu
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Russell King, Rob Herring,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <DB6PR0401MB2536CAFE776097EDEBE82C49F80E0-2mNvjAGDOPkZcyyZo0JLBI3W/0Ik+aLCnBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
On Mon, Dec 18, 2017 at 02:51:06AM +0000, Y.b. Lu wrote:
> Hi Shawn,
>
> Sorry for bother. I just couldn’t find this patch on your git tree.
> Could you help to check?
Sorry. I forgot to push the update. Just pushed now.
Shawn
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^ permalink raw reply
* Re: [PATCH v5 15/15] devicetree: bindings: Document qcom,pvs
From: Viresh Kumar @ 2017-12-20 3:26 UTC (permalink / raw)
To: Sricharan R
Cc: robh+dt, mark.rutland, mturquette, sboyd, linux, andy.gross,
david.brown, rjw, linux-arm-kernel, devicetree, linux-kernel,
linux-clk, linux-arm-msm, linux-soc, linux-pm
In-Reply-To: <1513698900-10638-16-git-send-email-sricharan@codeaurora.org>
On 19-12-17, 21:25, Sricharan R wrote:
> + cpu@0 {
> + compatible = "qcom,krait";
> + enable-method = "qcom,kpss-acc-v1";
> + device_type = "cpu";
> + reg = <0>;
> + qcom,acc = <&acc0>;
> + qcom,saw = <&saw0>;
> + clocks = <&kraitcc 0>;
> + clock-names = "cpu";
> + cpu-supply = <&smb208_s2a>;
> + operating-points-v2 = <&cpu_opp_table>;
> + };
> +
> + qcom,pvs {
> + qcom,pvs-format-a;
> + };
Not sure what Rob is going to say on that :)
> +
> +
> + cpu_opp_table: opp_table {
> + compatible = "operating-points-v2";
> +
> + /*
> + * Missing opp-shared property means CPUs switch DVFS states
> + * independently.
> + */
> +
> + opp-1400000000 {
> + opp-hz = /bits/ 64 <1400000000>;
> + opp-microvolt-speed0-pvs0-v0 = <1250000>;
Why speed0 and v0 in all the names ?
--
viresh
^ permalink raw reply
* [PATCH v3 20/20] ARM: dts: aspeed-evb: Add unit name to memory node
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-aspeed-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <20171220032328.30584-1-joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
Fixes a warning when building with W=1.
All of the ASPEED device trees build without warnings now.
Signed-off-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
---
arch/arm/boot/dts/aspeed-ast2500-evb.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
index 3e6f38e5d5d0..91a36c1f029b 100644
--- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -16,7 +16,7 @@
bootargs = "console=ttyS4,115200 earlyprintk";
};
- memory {
+ memory@80000000 {
reg = <0x80000000 0x20000000>;
};
};
--
2.15.1
--
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^ permalink raw reply related
* [PATCH v3 19/20] ARM: dts: aspeed-plametto: Add flash layout and fix memory node
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-aspeed-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <20171220032328.30584-1-joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
The OpenBMC flash layout is used by Palmetto systems.
Add the unit name to the memory node to fix a warning with W=1.
Reviewed-by: Cédric Le Goater <clg-Bxea+6Xhats@public.gmane.org>
Signed-off-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
---
v3:
- Added memory node unit name
---
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index a8f0c046e83e..4379d09a261f 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -12,7 +12,7 @@
bootargs = "console=ttyS4,115200 earlyprintk";
};
- memory {
+ memory@40000000 {
reg = <0x40000000 0x20000000>;
};
@@ -34,6 +34,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
+#include "openbmc-flash-layout.dtsi"
};
};
--
2.15.1
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^ permalink raw reply related
* [PATCH v3 18/20] ARM: dts: aspeed-romulus: Update Romulus system
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171220032328.30584-1-joel@jms.id.au>
- Fix incorrect RAM size
- Remove alias; these are now specified in the dtsi
- Add newly upstreamed devices
- Include OpenBMC flash layout
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v3:
- Add GPIO include
- Fix duplicate fmc and spi nodes
- Add unit name for memory node to fix warning
---
arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 133 +++++++++++++++++++++++++--
1 file changed, 126 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index a7a9386f964d..623b6ab42021 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
@@ -1,23 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
-
#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "Romulus BMC";
compatible = "ibm,romulus-bmc", "aspeed,ast2500";
- aliases {
- serial4 = &uart5;
- };
-
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
- memory {
- reg = <0x80000000 0x40000000>;
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
};
reserved-memory {
@@ -29,6 +25,49 @@
no-map;
reg = <0xbf000000 0x01000000>; /* 16M */
};
+
+ flash_memory: region@98000000 {
+ no-map;
+ reg = <0x98000000 0x04000000>; /* 64M */
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ fault {
+ gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ identify {
+ gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+ };
+
+ power {
+ gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ fsi: gpio-fsi {
+ compatible = "fsi-master-gpio", "fsi-master";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
+ data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
+ mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+ trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ checkstop {
+ label = "checkstop";
+ gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(J, 2)>;
+ };
};
};
@@ -38,6 +77,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
+#include "openbmc-flash-layout.dtsi"
};
};
@@ -53,6 +93,12 @@
};
};
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
&uart1 {
/* Rear RS-232 connector */
status = "okay";
@@ -81,6 +127,10 @@
pinctrl-0 = <&pinctrl_rmii1_default>;
};
+&i2c1 {
+ status = "okay";
+};
+
&i2c2 {
status = "okay";
};
@@ -133,8 +183,77 @@
&i2c12 {
status = "okay";
+
+ max31785@52 {
+ compatible = "maxim,max31785";
+ reg = <0x52>;
+ };
+};
+
+&gpio {
+ nic_func_mode0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "nic_func_mode0";
+ };
+ nic_func_mode1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "nic_func_mode1";
+ };
};
&vuart {
status = "okay";
};
+
+&gfx {
+ status = "okay";
+};
+
+&pinctrl {
+ aspeed,external-nodes = <&gfx &lhc>;
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
+
+ fan@0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x08>;
+ };
+
+ fan@1 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x09>;
+ };
+
+ fan@2 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
+ };
+
+ fan@3 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
+ };
+
+ fan@4 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
+ };
+
+ fan@5 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
+ };
+
+ fan@6 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0e>;
+ };
+};
--
2.15.1
^ permalink raw reply related
* [PATCH v3 17/20] ARM: dts: aspeed: Add Qanta Q71L BMC machine
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Rick Altherr, Cédric Le Goater, Benjamin Herrenschmidt,
Jeremy Kerr, devicetree, linux-arm-kernel, linux-kernel,
linux-aspeed, Peter Hanson
In-Reply-To: <20171220032328.30584-1-joel@jms.id.au>
From: Rick Altherr <raltherr@google.com>
The Qanta Q71L BMC is an ASPEED ast2400 based BMC that is part of a
Qanta x86 server.
This adds the device tree description for most upstream components. It
is a squashed commit from the OpenBMC kernel tree.
Signed-off-by: Peter Hanson <peterh@google.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Patrick Venture <venture@google.com>
Signed-off-by: Rick Altherr <raltherr@google.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v3:
- Add GPIO include
- Add unit name to memory node to fix warning
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 458 +++++++++++++++++++++++++++
2 files changed, 460 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 48c55f307aa9..5ab5d9169511 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1106,5 +1106,6 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-opp-palmetto.dtb \
aspeed-bmc-opp-romulus.dtb \
aspeed-bmc-opp-witherspoon.dtb \
- aspeed-bmc-opp-zaius.dtb
+ aspeed-bmc-opp-zaius.dtb \
+ aspeed-bmc-quanta-q71l.dtb
endif
diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
new file mode 100644
index 000000000000..76aa6ea1f988
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
@@ -0,0 +1,458 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "aspeed-g4.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "Quanta Q71L BMC";
+ compatible = "quanta,q71l-bmc", "aspeed,ast2400";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory@40000000 {
+ reg = <0x40000000 0x8000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ vga_memory: framebuffer@47800000 {
+ no-map;
+ reg = <0x47800000 0x00800000>; /* 8MB */
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
+ };
+
+ power {
+ gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ identify {
+ gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
+ <&adc 8>, <&adc 9>, <&adc 10>;
+ };
+
+ iio-hwmon-battery {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 11>;
+ };
+
+ i2c1mux: i2cmux {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH> */
+ i2c-parent = <&i2c1>;
+ };
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ label = "bmc";
+ m25p,fast-read;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&spi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ };
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default
+ &pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
+};
+
+&lpc_snoop {
+ status = "okay";
+ snoop-ports = <0x80>;
+};
+
+&mac0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ use-ncsi;
+};
+
+&mac1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ /* temp2 inlet */
+ tmp75@4c {
+ compatible = "ti,tmp75";
+ reg = <0x4c>;
+ };
+
+ /* temp3 */
+ tmp75@4e {
+ compatible = "ti,tmp75";
+ reg = <0x4e>;
+ };
+
+ /* temp1 */
+ tmp75@4f {
+ compatible = "ti,tmp75";
+ reg = <0x4f>;
+ };
+
+ /* Baseboard FRU */
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
+
+ /* FP FRU */
+ eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ /* 0: PCIe Slot 2,
+ * Slot 3,
+ * Slot 6,
+ * Slot 7
+ */
+ i2c-switch@74 {
+ compatible = "nxp,pca9546";
+ reg = <0x74>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect; /* may use mux@77 next. */
+
+ i2c_pcie2: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_pcie3: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_pcie6: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_pcie7: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+
+ /* 0: PCIe Slot 1,
+ * Slot 4,
+ * Slot 5,
+ * Slot 8,
+ * Slot 9,
+ * Slot 10,
+ * SSD 1,
+ * SSD 2
+ */
+ i2c-switch@77 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x77>;
+ i2c-mux-idle-disconnect; /* may use mux@74 next. */
+
+ i2c_pcie1: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_pcie4: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_pcie5: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_pcie8: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+
+ i2c_pcie9: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ i2c_pcie10: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ i2c_ssd1: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+
+ i2c_ssd2: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+};
+
+&i2c3 {
+ status = "okay";
+
+ /* BIOS FRU */
+ eeprom@56 {
+ compatible = "atmel,24c64";
+ reg = <0x56>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+
+ /* 0: PSU4
+ * PSU1
+ * PSU3
+ * PSU2
+ */
+ i2c-switch@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c_psu4: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_psu1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_psu3: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_psu2: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+
+ /* PDB FRU */
+ eeprom@52 {
+ compatible = "atmel,24c64";
+ reg = <0x52>;
+ };
+};
+
+&i2c8 {
+ status = "okay";
+
+ /* BMC FRU */
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+};
+
+&vuart {
+ status = "okay";
+};
+
+&wdt2 {
+ status = "okay";
+};
+
+&pwm_tacho {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default
+ &pinctrl_pwm1_default
+ &pinctrl_pwm2_default
+ &pinctrl_pwm3_default>;
+
+ fan@0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+
+ fan@1 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ };
+
+ fan@2 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+ };
+
+ fan@3 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x03>;
+ };
+
+ fan@4 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x04>;
+ };
+
+ fan@5 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x05>;
+ };
+
+ fan@6 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x06>;
+ };
+
+ fan@7 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x07>;
+ };
+};
+
+&i2c1mux {
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Memory Riser 1 FRU */
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+
+ /* Memory Riser 2 FRU */
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+
+ /* Memory Riser 3 FRU */
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ /* Memory Riser 4 FRU */
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ };
+ };
+
+ i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Memory Riser 5 FRU */
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+
+ /* Memory Riser 6 FRU */
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+
+ /* Memory Riser 7 FRU */
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ /* Memory Riser 8 FRU */
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ };
+ };
+};
--
2.15.1
^ permalink raw reply related
* [PATCH v3 16/20] ARM: dts: aspeed: Add Ingrasys Zaius BMC machine
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed,
Robert Lippert, Peter Hanson, Rick Altherr
In-Reply-To: <20171220032328.30584-1-joel@jms.id.au>
From: Xo Wang <xow@google.com>
Zaius is a POWER9 platform announced at OpenPOWER Summit 2016. This adds
basic DTS support for its AST2500 BMC.
This adds the device tree description for most upstream components. It
is a squashed commit of all of the patches from the OpenBMC kernel tree.
Signed-off-by: Xo Wang <xow@google.com>
Signed-off-by: Patrick Venture <venture@google.com>
Signed-off-by: Robert Lippert <rlippert@google.com>
Signed-off-by: Peter Hanson <peterh@google.com>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Rick Altherr <raltherr@google.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v3:
- Add GPIO include
- Add unit name for memory node to fix warning
---
arch/arm/boot/dts/Makefile | 4 +-
arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 426 +++++++++++++++++++++++++++++
2 files changed, 428 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 15a9207319c1..48c55f307aa9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1105,6 +1105,6 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-bmc-opp-palmetto.dtb \
aspeed-bmc-opp-romulus.dtb \
- aspeed-bmc-opp-witherspoon.dtb
-
+ aspeed-bmc-opp-witherspoon.dtb \
+ aspeed-bmc-opp-zaius.dtb
endif
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
new file mode 100644
index 000000000000..c881484a85cf
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
@@ -0,0 +1,426 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "Zaius BMC";
+ compatible = "ingrasys,zaius-bmc", "aspeed,ast2500";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region@98000000 {
+ no-map;
+ reg = <0x98000000 0x04000000>; /* 64M */
+ };
+ };
+
+ onewire0 {
+ compatible = "w1-gpio";
+ gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
+ };
+
+ onewire1 {
+ compatible = "w1-gpio";
+ gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ };
+
+ onewire2 {
+ compatible = "w1-gpio";
+ gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ };
+
+ onewire3 {
+ compatible = "w1-gpio";
+ gpios = <&gpio ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ checkstop {
+ label = "checkstop";
+ gpios = <&gpio ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(F, 7)>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ sys_boot_status {
+ label = "System boot status";
+ gpios = <&gpio ASPEED_GPIO(D, 5) GPIO_ACTIVE_LOW>;
+ };
+
+ attention {
+ label = "Attention";
+ gpios = <&gpio ASPEED_GPIO(D, 6) GPIO_ACTIVE_LOW>;
+ };
+
+ plt_fault {
+ label = "Platform fault";
+ gpios = <&gpio ASPEED_GPIO(D, 7) GPIO_ACTIVE_LOW>;
+ };
+
+ hdd_fault {
+ label = "Onboard drive fault";
+ gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ fsi: gpio-fsi {
+ compatible = "fsi-master-gpio", "fsi-master";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ trans-gpios = <&gpio ASPEED_GPIO(O, 6) GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+ clock-gpios = <&gpio ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>;
+ data-gpios = <&gpio ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>;
+ mux-gpios = <&gpio ASPEED_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
+ <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
+ <&adc 13>, <&adc 14>, <&adc 15>;
+ };
+
+ iio-hwmon-battery {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 12>;
+ };
+
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ label = "bmc";
+ m25p,fast-read;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ label = "pnor";
+ m25p,fast-read;
+ };
+};
+
+&spi2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2ck_default
+ &pinctrl_spi2cs0_default
+ &pinctrl_spi2cs1_default
+ &pinctrl_spi2miso_default
+ &pinctrl_spi2mosi_default>;
+
+ flash@0 {
+ status = "okay";
+ };
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default>;
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
+&lpc_snoop {
+ status = "okay";
+ snoop-ports = <0x80>;
+};
+
+
+&uart5 {
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ use-ncsi;
+};
+
+&mac1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+
+ rtc@68 {
+ compatible = "nxp,pcf8523";
+ reg = <0x68>;
+ };
+
+ ucd90160@64 {
+ compatible = "ti,ucd90160";
+ reg = <0x64>;
+ };
+
+ /* Power sequencer UCD90160 PMBUS @64h
+ * FRU AT24C64D @50h
+ * RTC PCF8523 @68h
+ * Clock buffer 9DBL04 @6dh
+ */
+};
+
+&i2c1 {
+ status = "okay";
+
+ i2c-switch@71 {
+ compatible = "nxp,pca9546";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* MUX1 PCA9546A @71h
+ * PCIe 0
+ * PCIe 1
+ * PCIe 2
+ * TPM header
+ */
+};
+
+&i2c2 {
+ status = "disabled";
+
+ /* OCP Mezz Connector A (OOB SMBUS) */
+};
+
+&i2c3 {
+ status = "disabled";
+
+ /* OCP Mezz Connector A (PCIe slot SMBUS) */
+};
+
+&i2c4 {
+ status = "okay";
+
+ i2c-switch@71 {
+ compatible = "nxp,pca9546";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* MUX1 PCA9546A @71h
+ * PCIe 3
+ * PCIe 4
+ */
+};
+
+
+&i2c5 {
+ status = "disabled";
+
+ /* CPU0 PRM 0.7V */
+ /* CPU0 PRM 1.2V CH03 */
+ /* CPU0 PRM 0.8V */
+ /* CPU0 PRM 1.2V CH47 */
+};
+
+&i2c6 {
+ status = "disabled";
+
+ /* CPU1 PRM 0.7V */
+ /* CPU1 PRM 1.2V CH03 */
+ /* CPU1 PRM 0.8V */
+ /* CPU1 PRM 1.2V CH47 */
+};
+
+&i2c7 {
+ status = "okay";
+
+ pca9541a@70 {
+ compatible = "nxp,pca9541";
+ reg = <0x70>;
+
+ i2c-arb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hotswap@54 {
+ compatible = "ti,lm5066i";
+ reg = <0x54>;
+ };
+ };
+ };
+
+ /* Master selector PCA9541A @70h (other master: CPU0)
+ * LM5066I PMBUS @10h
+ */
+
+ /* 12V Quarter Brick DC/DC Converter Q54SJ12050 @61h */
+ power-brick@61 {
+ compatible = "delta,dps800";
+ reg = <0x61>;
+ };
+
+ /* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */
+ /* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */
+ /* CPU0 VR ISL68137 0.8V PMBUS @60h */
+ /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @41h */
+ /* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */
+};
+
+&i2c8 {
+ status = "okay";
+
+ /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @65h */
+ /* CPU1 VR ISL68137 1.2V CH03 PMBUS @44h */
+ /* CPU1 VR ISL68137 0.8V PMBUS @61h */
+ /* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */
+ /* CPU0 VR ISL68137 1.2V CH47 PMBUS @45h */
+};
+
+
+&i2c9 {
+ status = "disabled";
+
+ /* Fan board */
+};
+
+&i2c10 {
+ status = "disabled";
+};
+
+&i2c11 {
+ status = "disabled";
+
+ /* GPU sideband */
+};
+
+&i2c12 {
+ status = "disabled";
+};
+
+&i2c13 {
+ status = "disabled";
+
+ /* MUX PI3USB102
+ * CPU0 debug
+ * CPU1 debug
+ */
+};
+
+&pinctrl {
+ aspeed,external-nodes = <&gfx &lhc>;
+
+ pinctrl_gpioh_unbiased: gpioi_unbiased {
+ pins = "A8", "C7", "B7", "A7", "D7", "B6", "A6", "E7";
+ bias-disable;
+ };
+};
+
+&gpio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpioh_unbiased>;
+
+ line_iso_u146_en {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(O, 4) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "iso_u164_en";
+ };
+
+ ncsi_mux_en_n {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "ncsi_mux_en_n";
+ };
+
+ line_bmc_i2c2_sw_rst_n {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "bmc_i2c2_sw_rst_n";
+ };
+
+ line_bmc_i2c5_sw_rst_n {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "bmc_i2c5_sw_rst_n";
+ };
+};
+
+&vuart {
+ status = "okay";
+};
+
+&gfx {
+ status = "okay";
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
+ &pinctrl_pwm2_default &pinctrl_pwm3_default>;
+
+ fan@0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+
+ fan@1 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ };
+
+ fan@2 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+ };
+
+ fan@3 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x03>;
+ };
+};
--
2.15.1
^ permalink raw reply related
* [PATCH v3 15/20] ARM: dts: aspeed: Add Witherspoon BMC machine
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed,
Brandon Wyman, Matt Spinler, Brad Bishop, Edward A . James
In-Reply-To: <20171220032328.30584-1-joel@jms.id.au>
The Witherspoon BMC is an ASPEED ast2500 based BMC that is part of an
OpenPower Power9 server.
This adds the device tree description for most upstream components. It
is a squashed commit from the OpenBMC kernel tree.
Signed-off-by: Brandon Wyman <bjwyman@gmail.com>
Signed-off-by: Matt Spinler <spinler@us.ibm.com>
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Signed-off-by: Edward A. James <eajames@us.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Brandon Wyman <bjwyman@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v2:
- Add Brandon's reviewed-by tag
v3:
- Add GPIO include
- Add unit name for memory node to fix warning
---
arch/arm/boot/dts/Makefile | 4 +-
arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 548 +++++++++++++++++++++++
2 files changed, 551 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5d1e9d37bf3a..15a9207319c1 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1104,5 +1104,7 @@ dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-bmc-opp-palmetto.dtb \
- aspeed-bmc-opp-romulus.dtb
+ aspeed-bmc-opp-romulus.dtb \
+ aspeed-bmc-opp-witherspoon.dtb
+
endif
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
new file mode 100644
index 000000000000..5f9049d2c4c3
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
@@ -0,0 +1,548 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/leds/leds-pca955x.h>
+
+/ {
+ model = "Witherspoon BMC";
+ compatible = "ibm,witherspoon-bmc", "aspeed,ast2500";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region@98000000 {
+ no-map;
+ reg = <0x98000000 0x04000000>; /* 64M */
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <1000>;
+
+ fan0-presence {
+ label = "fan0-presence";
+ gpios = <&pca0 4 GPIO_ACTIVE_LOW>;
+ linux,code = <4>;
+ };
+
+ fan1-presence {
+ label = "fan1-presence";
+ gpios = <&pca0 5 GPIO_ACTIVE_LOW>;
+ linux,code = <5>;
+ };
+
+ fan2-presence {
+ label = "fan2-presence";
+ gpios = <&pca0 6 GPIO_ACTIVE_LOW>;
+ linux,code = <6>;
+ };
+
+ fan3-presence {
+ label = "fan3-presence";
+ gpios = <&pca0 7 GPIO_ACTIVE_LOW>;
+ linux,code = <7>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ fan0 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 0 GPIO_ACTIVE_LOW>;
+ };
+
+ fan1 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 1 GPIO_ACTIVE_LOW>;
+ };
+
+ fan2 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 2 GPIO_ACTIVE_LOW>;
+ };
+
+ fan3 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 3 GPIO_ACTIVE_LOW>;
+ };
+
+ front-fault {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 13 GPIO_ACTIVE_LOW>;
+ };
+
+ front-power {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 14 GPIO_ACTIVE_LOW>;
+ };
+
+ front-id {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 15 GPIO_ACTIVE_LOW>;
+ };
+
+ rear-fault {
+ gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ rear-id {
+ gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>;
+ };
+
+ rear-power {
+ gpios = <&gpio ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>;
+ };
+
+ power-button {
+ gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ fsi: gpio-fsi {
+ compatible = "fsi-master-gpio", "fsi-master";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
+ data-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>;
+ mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+ trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+ };
+
+ iio-hwmon-dps310 {
+ compatible = "iio-hwmon";
+ io-channels = <&dps 0>;
+ };
+
+ iio-hwmon-bmp280 {
+ compatible = "iio-hwmon";
+ io-channels = <&bmp 1>;
+ };
+
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ label = "bmc";
+ m25p,fast-read;
+#include "openbmc-flash-layout.dtsi"
+ };
+
+ flash@1 {
+ status = "okay";
+ label = "alt";
+ m25p,fast-read;
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ label = "pnor";
+ m25p,fast-read;
+ };
+};
+
+&uart1 {
+ /* Rear RS-232 connector */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default
+ &pinctrl_nrts1_default
+ &pinctrl_ndtr1_default
+ &pinctrl_ndsr1_default
+ &pinctrl_ncts1_default
+ &pinctrl_ndcd1_default
+ &pinctrl_nri1_default>;
+};
+
+&uart2 {
+ /* APSS */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
+&mac0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ use-ncsi;
+};
+
+&i2c2 {
+ status = "okay";
+
+ /* MUX ->
+ * Samtec 1
+ * Samtec 2
+ */
+};
+
+&i2c3 {
+ status = "okay";
+
+ bmp: bmp280@77 {
+ compatible = "bosch,bmp280";
+ reg = <0x77>;
+ #io-channel-cells = <1>;
+ };
+
+ max31785@52 {
+ compatible = "maxim,max31785a";
+ reg = <0x52>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ dps: dps310@76 {
+ compatible = "infineon,dps310";
+ reg = <0x76>;
+ #io-channel-cells = <0>;
+ };
+
+ pca0: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ power-supply@68 {
+ compatible = "ibm,cffps1";
+ reg = <0x68>;
+ };
+
+ power-supply@69 {
+ compatible = "ibm,cffps1";
+ reg = <0x69>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ ir35221@70 {
+ compatible = "infineon,ir35221";
+ reg = <0x70>;
+ };
+
+ ir35221@71 {
+ compatible = "infineon,ir35221";
+ reg = <0x71>;
+ };
+};
+
+
+&i2c5 {
+ status = "okay";
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ ir35221@70 {
+ compatible = "infineon,ir35221";
+ reg = <0x70>;
+ };
+
+ ir35221@71 {
+ compatible = "infineon,ir35221";
+ reg = <0x71>;
+ };
+};
+
+&i2c9 {
+ status = "okay";
+
+ tmp275@4a {
+ compatible = "ti,tmp275";
+ reg = <0x4a>;
+ };
+};
+
+&i2c10 {
+ /* MUX
+ * -> PCIe Slot 3
+ * -> PCIe Slot 4
+ */
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+
+ pca9552: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N",
+ "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF",
+ "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF",
+ "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF",
+ "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF",
+ "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF",
+ "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF",
+ "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N";
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+
+ ucd90160@64 {
+ compatible = "ti,ucd90160";
+ reg = <0x64>;
+ };
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&vuart {
+ status = "okay";
+};
+
+&gfx {
+ status = "okay";
+};
+
+&pinctrl {
+ aspeed,external-nodes = <&gfx &lhc>;
+};
+
+&wdt1 {
+ aspeed,reset-type = "none";
+ aspeed,external-signal;
+ aspeed,ext-push-pull;
+ aspeed,ext-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst1_default>;
+};
--
2.15.1
^ permalink raw reply related
* [PATCH v3 14/20] ARM: dts: aspeed: Sort ASPEED entries in makefile
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171220032328.30584-1-joel@jms.id.au>
In preperation for adding more boards.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/Makefile | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d0381e9caf21..5d1e9d37bf3a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1101,7 +1101,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt8127-moose.dtb \
mt8135-evbp1.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
-dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \
- aspeed-bmc-opp-romulus.dtb \
- aspeed-ast2500-evb.dtb
+dtb-$(CONFIG_ARCH_ASPEED) += \
+ aspeed-ast2500-evb.dtb \
+ aspeed-bmc-opp-palmetto.dtb \
+ aspeed-bmc-opp-romulus.dtb
endif
--
2.15.1
^ permalink raw reply related
* [PATCH v3 13/20] ARM: dts: Add OpenBMC flash layout
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171220032328.30584-1-joel@jms.id.au>
This is a layout used by OpenBMC systems. It describes the fixed flash
layout of a 32MB mtd device.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v3:
- Remove leading zeros to fix warning
---
arch/arm/boot/dts/openbmc-flash-layout.dtsi | 32 +++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 arch/arm/boot/dts/openbmc-flash-layout.dtsi
diff --git a/arch/arm/boot/dts/openbmc-flash-layout.dtsi b/arch/arm/boot/dts/openbmc-flash-layout.dtsi
new file mode 100644
index 000000000000..6c26524e93e1
--- /dev/null
+++ b/arch/arm/boot/dts/openbmc-flash-layout.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u-boot@0 {
+ reg = <0x0 0x60000>;
+ label = "u-boot";
+ };
+
+ u-boot-env@60000 {
+ reg = <0x60000 0x20000>;
+ label = "u-boot-env";
+ };
+
+ kernel@80000 {
+ reg = <0x80000 0x440000>;
+ label = "kernel";
+ };
+
+ rofs@c0000 {
+ reg = <0x4c0000 0x1740000>;
+ label = "rofs";
+ };
+
+ rwfs@1c00000 {
+ reg = <0x1c00000 0x400000>;
+ label = "rwfs";
+ };
+};
--
2.15.1
^ permalink raw reply related
* [PATCH v3 12/20] ARM: dts: aspeed: Update license headers
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171220032328.30584-1-joel@jms.id.au>
In b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier
to files with no license") these files had the GPL-2.0 licence added
automatically. Update them to be GPL 2.0+ in line with other IBM kernel
contributions.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-ast2500-evb.dts | 2 +-
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 2 +-
arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 2 +-
arch/arm/boot/dts/aspeed-g4.dtsi | 2 +-
arch/arm/boot/dts/aspeed-g5.dtsi | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
index 602bc10fdaf4..3e6f38e5d5d0 100644
--- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index c786bc2f2919..a8f0c046e83e 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g4.dtsi"
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index 8067793129ea..a7a9386f964d 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 1186fe55e2d8..b0d8431a3700 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/clock/aspeed-clock.h>
/ {
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 6043876ad85f..40de3b66c33f 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/clock/aspeed-clock.h>
/ {
--
2.15.1
^ permalink raw reply related
* [PATCH v3 11/20] ARM: dts: aspeed: Remove skeleton.dtsi
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171220032328.30584-1-joel@jms.id.au>
We don't require it for any of the ASPEED systems.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 1 -
arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
2 files changed, 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index e8a61fc3956d..1186fe55e2d8 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -1,5 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
-#include "skeleton.dtsi"
#include <dt-bindings/clock/aspeed-clock.h>
/ {
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d558091aa92b..6043876ad85f 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -1,5 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
-#include "skeleton.dtsi"
#include <dt-bindings/clock/aspeed-clock.h>
/ {
--
2.15.1
^ permalink raw reply related
* [PATCH v3 10/20] ARM: dts: aspeed: Add LPC Snoop device
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171220032328.30584-1-joel@jms.id.au>
LPC snoop hardware on the ASPEED BMC, used for monitoring
host I/O port activity.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 7 +++++++
arch/arm/boot/dts/aspeed-g5.dtsi | 6 ++++++
2 files changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 91aea96c10c8..e8a61fc3956d 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -237,6 +237,13 @@
status = "disabled";
};
+ lpc_snoop: lpc-snoop@0 {
+ compatible = "aspeed,ast2400-lpc-snoop";
+ reg = <0x0 0x80>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
lhc: lhc@20 {
compatible = "aspeed,ast2400-lhc";
reg = <0x20 0x24 0x48 0x8>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index af3869ec87bb..d558091aa92b 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -288,6 +288,12 @@
status = "disabled";
};
+ lpc_snoop: lpc-snoop@0 {
+ compatible = "aspeed,ast2500-lpc-snoop";
+ reg = <0x0 0x80>;
+ interrupts = <8>;
+ status = "disabled";
+ };
lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
--
2.15.1
^ permalink raw reply related
* [PATCH v3 09/20] ARM: dts: aspeed: Add PWM and tachometer node
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171220032328.30584-1-joel@jms.id.au>
The PWM/tach unit has a clock and reset phandle. It needs both in order
to function correctly.
Signed-off-by: Joel Stanley <joel@jms.id.au>
--
v3:
Add the pwm reset phandle
---
arch/arm/boot/dts/aspeed-g4.dtsi | 10 ++++++++++
arch/arm/boot/dts/aspeed-g5.dtsi | 10 ++++++++++
2 files changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index d2a82850b05b..91aea96c10c8 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -189,6 +189,16 @@
clocks = <&syscon ASPEED_CLK_APB>;
};
+ pwm_tacho: pwm-tacho-controller@1e786000 {
+ compatible = "aspeed,ast2400-pwm-tacho";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1e786000 0x1000>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_PWM>;
+ status = "disabled";
+ };
+
vuart: serial@1e787000 {
compatible = "aspeed,ast2400-vuart";
reg = <0x1e787000 0x40>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 3a25fa48d4f6..af3869ec87bb 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -239,6 +239,16 @@
status = "disabled";
};
+ pwm_tacho: pwm-tacho-controller@1e786000 {
+ compatible = "aspeed,ast2500-pwm-tacho";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1e786000 0x1000>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_PWM>;
+ status = "disabled";
+ };
+
vuart: serial@1e787000 {
compatible = "aspeed,ast2500-vuart";
reg = <0x1e787000 0x40>;
--
2.15.1
^ permalink raw reply related
* [PATCH v3 08/20] ARM: dts: aspeed: Add clock phandle to GPIO
From: Joel Stanley @ 2017-12-20 3:23 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Andrew Jeffery,
Patrick Venture, Xo Wang, Lei YU
Cc: Cédric Le Goater, Benjamin Herrenschmidt, Jeremy Kerr,
devicetree, linux-arm-kernel, linux-kernel, linux-aspeed
In-Reply-To: <20171220032328.30584-1-joel@jms.id.au>
This enables a feature where the driver can debounce inputs.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 1 +
arch/arm/boot/dts/aspeed-g5.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 36cb66d8cc10..d2a82850b05b 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -144,6 +144,7 @@
reg = <0x1e780000 0x1000>;
interrupts = <20>;
gpio-ranges = <&pinctrl 0 0 220>;
+ clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 156b345ff20d..3a25fa48d4f6 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -187,6 +187,7 @@
reg = <0x1e780000 0x1000>;
interrupts = <20>;
gpio-ranges = <&pinctrl 0 0 220>;
+ clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
};
--
2.15.1
^ permalink raw reply related
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