* Re: [PATCH net-next v2 0/2] of: mdio: Fall back to mdiobus_register() with NULL device_node
From: Geert Uytterhoeven @ 2018-05-16 8:54 UTC (permalink / raw)
To: Florian Fainelli
Cc: netdev, Andrew Lunn, Vivien Didelot, David S. Miller,
Nicolas Ferre, Fugang Duan, Sergei Shtylyov, Giuseppe Cavallaro,
Alexandre Torgue, Jose Abreu, Grygorii Strashko, Woojung Huh,
Microchip Linux Driver Support, Rob Herring, Frank Rowand,
Antoine Tenart, Tobias Jordan, Russell King
In-Reply-To: <20180515235619.27773-1-f.fainelli@gmail.com>
Hi Florian,
Thanks for your series!
I like the effect on simplifying drivers.
On Wed, May 16, 2018 at 1:56 AM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> This patch series updates of_mdiobus_register() such that when the device_node
> argument is NULL, it calls mdiobus_register() directly. This is consistent with
> the behavior of of_mdiobus_register() when CONFIG_OF=n.
IMHO the CONFIG_OF=n behavior of of_mdiobus_register() (which I wasn't
aware of) is inconsistent with the behavior of other of_*() functions,
which are just empty stubs.
So I'm wondering if you should do it the other way around, and let
mdiobus_register() call of_mdiobus_register() if dev->of_node exists?
This does mean mdiobus_register() should gain a struct device * parameter,
and thus changes to many more drivers are needed.
> I only converted the most obvious drivers, there are others that have a much
> less obvious behavior and specifically attempt to deal with CONFIG_ACPI.
I haven't looked at the ACPI handling, but perhaps this can be moved
inside mdiobus_register() as well?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v2 2/2] ARM: dts: r8a7740: Add CEU0
From: Simon Horman @ 2018-05-16 8:54 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Jacopo Mondi, Rob Herring, Mark Rutland, Linux-Renesas,
Linux Media Mailing List,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List
In-Reply-To: <CAMuHMdWSasm9PfurphB5wrgrhkO8v7YBpSZNnnC+mS_Vs4AJ5Q@mail.gmail.com>
On Wed, May 16, 2018 at 09:40:09AM +0200, Geert Uytterhoeven wrote:
> Hi Jacopo,
>
> On Thu, Apr 26, 2018 at 8:24 PM, Jacopo Mondi <jacopo+renesas@jmondi.org> wrote:
> > Describe CEU0 peripheral for Renesas R-Mobile A1 R8A7740 Soc.
> >
> > Reported-by: Geert Uytterhoeven <geert@glider.be>
> > Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
>
> Thanks for your patch!
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Minor question below.
>
> > --- a/arch/arm/boot/dts/r8a7740.dtsi
> > +++ b/arch/arm/boot/dts/r8a7740.dtsi
> > @@ -67,6 +67,16 @@
> > power-domains = <&pd_d4>;
> > };
> >
> > + ceu0: ceu@fe910000 {
> > + reg = <0xfe910000 0x3000>;
> > + compatible = "renesas,r8a7740-ceu";
> > + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&mstp1_clks R8A7740_CLK_CEU20>;
> > + clock-names = "ceu20";
>
> Why the "clock-names" property? It's not mentioned in the DT bindings, and
> may cause issues if the bindings are ever amended.
I have dropped that property for now.
>
> > + power-domains = <&pd_a4r>;
> > + status = "disabled";
> > + };
> > +
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
>
^ permalink raw reply
* Re: [PATCH v2 1/2] soc: renesas: rcar-sysc: Add support for R-Car E3 power areas
From: Simon Horman @ 2018-05-16 8:57 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Yoshihiro Shimoda, Magnus Damm, Rob Herring, Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas, Takeshi Kihara
In-Reply-To: <CAMuHMdXiyKvN3mnzwN8cyRaW5z0eCjQ=p_4=JR-K5evny=PiAA@mail.gmail.com>
On Wed, May 16, 2018 at 09:45:30AM +0200, Geert Uytterhoeven wrote:
> On Tue, May 15, 2018 at 2:07 PM, Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> >
> > This patch adds Cortex-A53 CPU{0,1}, Cortex-A53 SCU, Cortex-R7, A3VC,
> > A2VC1 and 3DG-{A,B} power domain areas for the R8A77990 SoC.
> >
> > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > [shimoda: fix 3DG-{A,B} and add SPDX-License-Identifier]
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied.
^ permalink raw reply
* Re: [PATCH v2 2/2] soc: renesas: r8a77990-sysc: Add workaround for 3DG-{A,B}
From: Simon Horman @ 2018-05-16 8:58 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Yoshihiro Shimoda, Magnus Damm, Rob Herring, Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas
In-Reply-To: <CAMuHMdUedCHrvJd79P49Sa+=f905k=hAE=ZNYRhbyPEdaw8rjQ@mail.gmail.com>
On Wed, May 16, 2018 at 09:47:04AM +0200, Geert Uytterhoeven wrote:
> On Tue, May 15, 2018 at 2:07 PM, Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > This patch adds workaround for 3DG-{A,B} of R-Car E3 ES1.0 because
> > the SoC has a restriction about the order.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, accepted.
^ permalink raw reply
* Re: [PATCH v2 09/11] docs: Fix some broken references
From: Charles Keepax @ 2018-05-16 9:09 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: Catalin Marinas, Linus Walleij, Will Deacon, dri-devel,
Jaroslav Kysela, Eric Paris, linux-clk, James Morris, Alan Stern,
xen-devel, Boqun Feng, Nicholas Piggin, Sean Paul,
Thomas Gleixner, Antoine Jacquet, Greg Kroah-Hartman, linux-usb,
linux-kernel, Li Zefan, linux-crypto, Mark Rutland, alsa-devel,
Linux Doc Mailing List, David Airlie, Gustavo Padovan
In-Reply-To: <e959f23d6f6905ee606fadfda13e2bb37deed017.1525870886.git.mchehab+samsung@kernel.org>
On Wed, May 09, 2018 at 10:18:52AM -0300, Mauro Carvalho Chehab wrote:
> As we move stuff around, some doc references are broken. Fix some of
> them via this script:
> ./scripts/documentation-file-ref-check --fix-rst
>
> Manually checked if the produced result is valid, removing a few
> false-positives.
>
> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
> ---
> drivers/input/touchscreen/wm97xx-core.c | 2 +-
Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Thanks,
Charles
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply
* [PATCH] arm64: dts: move berlin SoC files from marvell dir to synaptics dir
From: Jisheng Zhang @ 2018-05-16 9:51 UTC (permalink / raw)
To: sebastian.hesselbarth, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon
Cc: devicetree, linux-arm-kernel, linux-kernel
Move device tree files as part of transition from Marvell berlin to
Synaptics berlin.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/marvell/Makefile | 4 ----
arch/arm64/boot/dts/synaptics/Makefile | 4 ++++
arch/arm64/boot/dts/{marvell => synaptics}/berlin4ct-dmp.dts | 0
arch/arm64/boot/dts/{marvell => synaptics}/berlin4ct-stb.dts | 0
arch/arm64/boot/dts/{marvell => synaptics}/berlin4ct.dtsi | 0
6 files changed, 5 insertions(+), 4 deletions(-)
create mode 100644 arch/arm64/boot/dts/synaptics/Makefile
rename arch/arm64/boot/dts/{marvell => synaptics}/berlin4ct-dmp.dts (100%)
rename arch/arm64/boot/dts/{marvell => synaptics}/berlin4ct-stb.dts (100%)
rename arch/arm64/boot/dts/{marvell => synaptics}/berlin4ct.dtsi (100%)
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 4aa50b9b26bc..3543bc324553 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -22,5 +22,6 @@ subdir-y += renesas
subdir-y += rockchip
subdir-y += socionext
subdir-y += sprd
+subdir-y += synaptics
subdir-y += xilinx
subdir-y += zte
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index cb454beede55..ea9d49f2a911 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -1,8 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-# Berlin SoC Family
-dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-dmp.dtb
-dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-stb.dtb
-
# Mvebu SoC Family
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb
diff --git a/arch/arm64/boot/dts/synaptics/Makefile b/arch/arm64/boot/dts/synaptics/Makefile
new file mode 100644
index 000000000000..de71ddda6835
--- /dev/null
+++ b/arch/arm64/boot/dts/synaptics/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+# Berlin SoC Family
+dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-dmp.dtb
+dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-stb.dtb
diff --git a/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts b/arch/arm64/boot/dts/synaptics/berlin4ct-dmp.dts
similarity index 100%
rename from arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts
rename to arch/arm64/boot/dts/synaptics/berlin4ct-dmp.dts
diff --git a/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts b/arch/arm64/boot/dts/synaptics/berlin4ct-stb.dts
similarity index 100%
rename from arch/arm64/boot/dts/marvell/berlin4ct-stb.dts
rename to arch/arm64/boot/dts/synaptics/berlin4ct-stb.dts
diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
similarity index 100%
rename from arch/arm64/boot/dts/marvell/berlin4ct.dtsi
rename to arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
--
2.17.0
^ permalink raw reply related
* [PATCH v4 1/4] rtc: ds1307: fix data pointer to m41t0
From: Giulio Benetti @ 2018-05-16 10:05 UTC (permalink / raw)
To: a.zummo, alexandre.belloni
Cc: robh+dt, mark.rutland, linux-rtc, devicetree, linux-kernel,
Giulio Benetti
data field points to m41t00, instead it should point to m41t0.
Driver works correctly because on both cases(m41t0 and m41t00) chip_desc
are equal.
Point to right enum m41t0 instead of m41t00.
Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
---
drivers/rtc/rtc-ds1307.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
index a13e59edff53..32aadcbc377f 100644
--- a/drivers/rtc/rtc-ds1307.c
+++ b/drivers/rtc/rtc-ds1307.c
@@ -298,7 +298,7 @@ static const struct of_device_id ds1307_of_match[] = {
},
{
.compatible = "st,m41t0",
- .data = (void *)m41t00
+ .data = (void *)m41t0
},
{
.compatible = "st,m41t00",
--
2.17.0
^ permalink raw reply related
* [PATCH v4 2/4] rtc: ds1307: support m41t11 variant
From: Giulio Benetti @ 2018-05-16 10:05 UTC (permalink / raw)
To: a.zummo, alexandre.belloni
Cc: robh+dt, mark.rutland, linux-rtc, devicetree, linux-kernel,
Giulio Benetti
In-Reply-To: <20180516100526.73549-1-giulio.benetti@micronovasrl.com>
The m41t11 variant is very similar to the already supported m41t00 and
m41t0, but it has also 56 bytes of NVRAM.
Add it to driver taking into account NVRAM section.
Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
---
.../devicetree/bindings/rtc/rtc-ds1307.txt | 1 +
drivers/rtc/rtc-ds1307.c | 14 ++++++++++++++
2 files changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt b/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt
index d28d6e7f6ae8..ce6469c1a516 100644
--- a/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt
+++ b/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt
@@ -13,6 +13,7 @@ Required properties:
"maxim,ds3231",
"st,m41t0",
"st,m41t00",
+ "st,m41t11",
"microchip,mcp7940x",
"microchip,mcp7941x",
"pericom,pt7c4338",
diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
index 32aadcbc377f..0ab0c166da83 100644
--- a/drivers/rtc/rtc-ds1307.c
+++ b/drivers/rtc/rtc-ds1307.c
@@ -44,6 +44,7 @@ enum ds_type {
ds_3231,
m41t0,
m41t00,
+ m41t11,
mcp794xx,
rx_8025,
rx_8130,
@@ -226,6 +227,11 @@ static const struct chip_desc chips[last_ds_type] = {
.irq_handler = rx8130_irq,
.rtc_ops = &rx8130_rtc_ops,
},
+ [m41t11] = {
+ /* this is battery backed SRAM */
+ .nvram_offset = 8,
+ .nvram_size = 56,
+ },
[mcp794xx] = {
.alarm = 1,
/* this is battery backed SRAM */
@@ -248,6 +254,7 @@ static const struct i2c_device_id ds1307_id[] = {
{ "ds3231", ds_3231 },
{ "m41t0", m41t0 },
{ "m41t00", m41t00 },
+ { "m41t11", m41t11 },
{ "mcp7940x", mcp794xx },
{ "mcp7941x", mcp794xx },
{ "pt7c4338", ds_1307 },
@@ -304,6 +311,10 @@ static const struct of_device_id ds1307_of_match[] = {
.compatible = "st,m41t00",
.data = (void *)m41t00
},
+ {
+ .compatible = "st,m41t11",
+ .data = (void *)m41t11
+ },
{
.compatible = "microchip,mcp7940x",
.data = (void *)mcp794xx
@@ -346,6 +357,7 @@ static const struct acpi_device_id ds1307_acpi_ids[] = {
{ .id = "DS3231", .driver_data = ds_3231 },
{ .id = "M41T0", .driver_data = m41t0 },
{ .id = "M41T00", .driver_data = m41t00 },
+ { .id = "M41T11", .driver_data = m41t11 },
{ .id = "MCP7940X", .driver_data = mcp794xx },
{ .id = "MCP7941X", .driver_data = mcp794xx },
{ .id = "PT7C4338", .driver_data = ds_1307 },
@@ -1574,6 +1586,7 @@ static int ds1307_probe(struct i2c_client *client,
case ds_1307:
case m41t0:
case m41t00:
+ case m41t11:
/* clock halted? turn it on, so clock can tick. */
if (tmp & DS1307_BIT_CH) {
regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
@@ -1639,6 +1652,7 @@ static int ds1307_probe(struct i2c_client *client,
case ds_1340:
case m41t0:
case m41t00:
+ case m41t11:
/*
* NOTE: ignores century bits; fix before deploying
* systems that will run through year 2100.
--
2.17.0
^ permalink raw reply related
* [PATCH v4 3/4] rtc: ds1307: add offset sysfs for mt41txx chips.
From: Giulio Benetti @ 2018-05-16 10:05 UTC (permalink / raw)
To: a.zummo, alexandre.belloni
Cc: robh+dt, mark.rutland, linux-rtc, devicetree, linux-kernel,
Giulio Benetti
In-Reply-To: <20180516100526.73549-1-giulio.benetti@micronovasrl.com>
m41txx chips can hold a calibration value to get correct clock bias.
Add offset handling (ranging between -63ppm and 126ppm) via sysfs.
Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
---
V3 => V4:
* use ppm as offset input according to documentation instead of
raw ic offset values.
* use regmap_update_bits instead of regmap_write to update ic registers
* sysfs_remove_group if devm_add_action_or_reset fails
* rtc_device_unregister if ds1307_add_frequency_test fails on m41txx
series
drivers/rtc/rtc-ds1307.c | 81 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
index 0ab0c166da83..2797d01bfa1d 100644
--- a/drivers/rtc/rtc-ds1307.c
+++ b/drivers/rtc/rtc-ds1307.c
@@ -114,6 +114,20 @@ enum ds_type {
# define RX8025_BIT_VDET 0x40
# define RX8025_BIT_XST 0x20
+#define M41TXX_REG_CONTROL 0x07
+# define M41TXX_BIT_OUT 0x80
+# define M41TXX_BIT_FT 0x40
+# define M41TXX_BIT_CALIB_SIGN 0x20
+# define M41TXX_M_CALIBRATION 0x1f
+
+/* negative offset step is -2.034ppm */
+#define M41TXX_NEG_OFFSET_STEP_PPM 2034
+/* positive offset step is +4.068ppm */
+#define M41TXX_POS_OFFSET_STEP_PPM 4068
+/* Min and max values supported with 'offset' interface by M41TXX */
+#define M41TXX_MIN_OFFSET (((-31) * M41TXX_NEG_OFFSET_STEP_PPM) / 1000)
+#define M41TXX_MAX_OFFSET (((31) * M41TXX_POS_OFFSET_STEP_PPM) / 1000)
+
struct ds1307 {
enum ds_type type;
unsigned long flags;
@@ -146,6 +160,9 @@ struct chip_desc {
static int ds1307_get_time(struct device *dev, struct rtc_time *t);
static int ds1307_set_time(struct device *dev, struct rtc_time *t);
+static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t);
+static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t);
+static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled);
static u8 do_trickle_setup_ds1339(struct ds1307 *, u32 ohms, bool diode);
static irqreturn_t rx8130_irq(int irq, void *dev_id);
static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t);
@@ -155,6 +172,8 @@ static irqreturn_t mcp794xx_irq(int irq, void *dev_id);
static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t);
static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t);
static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled);
+static int m41txx_rtc_read_offset(struct device *dev, long *offset);
+static int m41txx_rtc_set_offset(struct device *dev, long offset);
static const struct rtc_class_ops rx8130_rtc_ops = {
.read_time = ds1307_get_time,
@@ -172,6 +191,16 @@ static const struct rtc_class_ops mcp794xx_rtc_ops = {
.alarm_irq_enable = mcp794xx_alarm_irq_enable,
};
+static const struct rtc_class_ops m41txx_rtc_ops = {
+ .read_time = ds1307_get_time,
+ .set_time = ds1307_set_time,
+ .read_alarm = ds1337_read_alarm,
+ .set_alarm = ds1337_set_alarm,
+ .alarm_irq_enable = ds1307_alarm_irq_enable,
+ .read_offset = m41txx_rtc_read_offset,
+ .set_offset = m41txx_rtc_set_offset,
+};
+
static const struct chip_desc chips[last_ds_type] = {
[ds_1307] = {
.nvram_offset = 8,
@@ -227,10 +256,17 @@ static const struct chip_desc chips[last_ds_type] = {
.irq_handler = rx8130_irq,
.rtc_ops = &rx8130_rtc_ops,
},
+ [m41t0] = {
+ .rtc_ops = &m41txx_rtc_ops,
+ },
+ [m41t00] = {
+ .rtc_ops = &m41txx_rtc_ops,
+ },
[m41t11] = {
/* this is battery backed SRAM */
.nvram_offset = 8,
.nvram_size = 56,
+ .rtc_ops = &m41txx_rtc_ops,
},
[mcp794xx] = {
.alarm = 1,
@@ -972,6 +1008,51 @@ static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
enabled ? MCP794XX_BIT_ALM0_EN : 0);
}
+static int m41txx_rtc_read_offset(struct device *dev, long *offset)
+{
+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
+ unsigned int ctrl_reg;
+ u8 val;
+
+ regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
+
+ val = ctrl_reg & M41TXX_M_CALIBRATION;
+
+ /* check if positive */
+ if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
+ *offset = (val * M41TXX_POS_OFFSET_STEP_PPM);
+ else
+ *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPM);
+
+ *offset = DIV_ROUND_CLOSEST(*offset, 1000);
+
+ return 0;
+}
+
+static int m41txx_rtc_set_offset(struct device *dev, long offset)
+{
+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
+ unsigned int ctrl_reg;
+
+ if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
+ return -ERANGE;
+
+ offset *= 1000;
+
+ if (offset >= 0) {
+ ctrl_reg = DIV_ROUND_CLOSEST(offset,
+ M41TXX_POS_OFFSET_STEP_PPM);
+ ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
+ } else {
+ ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
+ M41TXX_NEG_OFFSET_STEP_PPM);
+ }
+
+ return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
+ M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
+ ctrl_reg);
+}
+
/*----------------------------------------------------------------------*/
static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
--
2.17.0
^ permalink raw reply related
* [PATCH v4 4/4] rtc: ds1307: add freq_test sysfs attribute to check tick on m41txx
From: Giulio Benetti @ 2018-05-16 10:05 UTC (permalink / raw)
To: a.zummo, alexandre.belloni
Cc: robh+dt, mark.rutland, linux-rtc, devicetree, linux-kernel,
Giulio Benetti
In-Reply-To: <20180516100526.73549-1-giulio.benetti@micronovasrl.com>
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with freq_test attribute, OUT pin will tick 512 times
faster than 1s tick base.
Enable or Disable FT bit on CONTROL register if freq_test is 1 or 0.
Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
---
V3 => V4:
* change attribute from freq_test to frequency_test_enable
* use regmap_update_bits instead of regmap_write
drivers/rtc/rtc-ds1307.c | 99 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 99 insertions(+)
diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
index 2797d01bfa1d..de98ddc39515 100644
--- a/drivers/rtc/rtc-ds1307.c
+++ b/drivers/rtc/rtc-ds1307.c
@@ -1053,6 +1053,99 @@ static int m41txx_rtc_set_offset(struct device *dev, long offset)
ctrl_reg);
}
+static ssize_t frequency_test_enable_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
+ unsigned long freq_test = 0;
+ int retval;
+
+ retval = kstrtoul(buf, 10, &freq_test);
+ if ((retval < 0) || (retval > 1)) {
+ dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
+ return -EINVAL;
+ }
+
+ regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
+ freq_test ? M41TXX_BIT_FT : 0);
+
+ return retval ? retval : count;
+}
+
+static ssize_t frequency_test_enable_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
+ int freq_test_en = 0;
+ unsigned int ctrl_reg;
+
+ regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
+
+ if (ctrl_reg & M41TXX_BIT_FT)
+ freq_test_en = true;
+ else
+ freq_test_en = false;
+
+ return sprintf(buf, "%d\n", freq_test_en);
+}
+
+static DEVICE_ATTR_RW(frequency_test_enable);
+
+static struct attribute *rtc_freq_test_attrs[] = {
+ &dev_attr_frequency_test_enable.attr,
+ NULL,
+};
+
+static const struct attribute_group rtc_freq_test_attr_group = {
+ .attrs = rtc_freq_test_attrs,
+};
+
+static void rtc_calib_remove_sysfs_group(void *_dev)
+{
+ struct device *dev = _dev;
+
+ sysfs_remove_group(&dev->kobj, &rtc_freq_test_attr_group);
+}
+
+static int ds1307_add_frequency_test(struct ds1307 *ds1307)
+{
+ int err = 0;
+
+ switch (ds1307->type) {
+ case m41t0:
+ case m41t00:
+ case m41t11:
+ /* Export sysfs entries */
+ err = sysfs_create_group(&(ds1307->dev)->kobj,
+ &rtc_freq_test_attr_group);
+ if (err) {
+ dev_err(ds1307->dev,
+ "Failed to create sysfs group: %d\n",
+ err);
+ return err;
+ }
+
+ err = devm_add_action_or_reset(ds1307->dev,
+ rtc_calib_remove_sysfs_group,
+ ds1307->dev);
+ if (err) {
+ dev_err(ds1307->dev,
+ "Failed to add sysfs cleanup action: %d\n",
+ err);
+ sysfs_remove_group(&(ds1307->dev)->kobj,
+ &rtc_freq_test_attr_group);
+ return err;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return err;
+}
+
/*----------------------------------------------------------------------*/
static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
@@ -1794,6 +1887,12 @@ static int ds1307_probe(struct i2c_client *client,
if (err)
return err;
+ err = ds1307_add_frequency_test(ds1307);
+ if (err) {
+ rtc_device_unregister(ds1307->rtc);
+ return err;
+ }
+
if (chip->nvram_size) {
struct nvmem_config nvmem_cfg = {
.name = "ds1307_nvram",
--
2.17.0
^ permalink raw reply related
* Re: [RESEND PATCH v5 0/6] Add support for PWM input capture on STM32
From: Lee Jones @ 2018-05-16 10:13 UTC (permalink / raw)
To: Fabrice Gasnier
Cc: alexandre.torgue, thierry.reding, benjamin.gaignard, robh+dt,
mark.rutland, linux, mcoquelin.stm32, benjamin.gaignard,
devicetree, linux-arm-kernel, linux-kernel, linux-pwm
In-Reply-To: <c48acc96-1eca-9adc-abb7-131921305ee8@st.com>
On Wed, 16 May 2018, Fabrice Gasnier wrote:
> On 05/16/2018 10:06 AM, Lee Jones wrote:
> > On Wed, 16 May 2018, Fabrice Gasnier wrote:
> >
> >> This series adds support for capture to stm32-pwm driver.
> >> Capture is based on DMAs.
> >> - First two patches add support for requesting DMAs to MFD core
> >> - Next three patches add support for capture to stm32-pwm driver
> >> - This has been tested on stm32429i-eval board.
> >>
> >> ---
> >> Changes in v5:
> >> - update patch 2 (mfd: stm32-timers: add support for dmas)
> >> move stm32_timers_dma struct to header file,
> >> fix warning on dma_mapping_error().
> >>
> >> Changes in v4:
> >> - Lee's comments on patch 2 (mfd: stm32-timers: add support for dmas)
> >> Add kerneldoc header, better format comments.
> >>
> >> Changes in v3:
> >> - Dropped 2 precusor patches applied by Thierry in pwm tree:
> >> "pwm: stm32: fix, remove unused struct device"
> >> "pwm: stm32: protect common prescaler for all channels"
> >> - Note: this series applies on top on pwm tree
> >> - Implements Lee's comments on MFD part: rework stm32_timers_dma struct,
> >> exported routine prototype now use generic device struct, more
> >> various comments (see patch 2 changelog).
> >>
> >> Resend v2:
> >> - Add collected Acks
> >>
> >> Changes in v2:
> >> - Abstract DMA handling from child driver: move it to MFD core
> >> - Rework pwm capture routines to adopt this change
> >> - Comment on optional dma support, beautify DMAs probe
> >>
> >> Fabrice Gasnier (6):
> >> dt-bindings: mfd: stm32-timers: add support for dmas
> >> mfd: stm32-timers: add support for dmas
> >> pwm: stm32: add capture support
> >> pwm: stm32: improve capture by tuning counter prescaler
> >> pwm: stm32: use input prescaler to improve period capture
> >> ARM: dts: stm32: Enable pwm3 input capture on stm32f429i-eval
> >
> > Applied patches 1-5.
>
> Many thanks Lee !
>
> Maybe I missed something, but just in case...
> In your pull request ("[GIT PULL] Immutable branch between MFD and PWM
> due for the v4.18 merge window") I only see 4 patches:
> Fabrice Gasnier (4):
> mfd: stm32-timers: Add support for DMAs
> pwm: stm32: Add capture support
> pwm: stm32: Improve capture by tuning counter prescaler
> pwm: stm32: Use input prescaler to improve period capture
>
> I can't see patch 1 ("dt-bindings: mfd: stm32-timers: add support for dmas")
> Is it applied on another tree ?
Good spot.
Looks like a fumbled the key combination for the bindings patch.
Pull-request to follow.
> >> .../devicetree/bindings/mfd/stm32-timers.txt | 20 ++
> >> arch/arm/boot/dts/stm32429i-eval.dts | 3 +
> >> drivers/mfd/stm32-timers.c | 201 +++++++++++++++-
> >> drivers/pwm/pwm-stm32.c | 257 +++++++++++++++++++++
> >> include/linux/mfd/stm32-timers.h | 58 +++++
> >> 5 files changed, 537 insertions(+), 2 deletions(-)
> >>
> >
--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [GIT PULL ++] Immutable branch between MFD and PWM due for the v4.18 merge window (v2)
From: Lee Jones @ 2018-05-16 10:16 UTC (permalink / raw)
To: Fabrice Gasnier, thierry.reding
Cc: alexandre.torgue, benjamin.gaignard, robh+dt, mark.rutland, linux,
mcoquelin.stm32, benjamin.gaignard, devicetree, linux-arm-kernel,
linux-kernel, linux-pwm
In-Reply-To: <20180516081910.GF5130@dell>
Subsequent pull-request containing additional bindings patch.
Enjoy!
The following changes since commit 60cc43fc888428bb2f18f08997432d426a243338:
Linux 4.17-rc1 (2018-04-15 18:24:20 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git ib-mfd-pwm-v4.18-1
for you to fetch changes up to acc8e22f5d41558c90519aadc011b6d2839aedfe:
dt-bindings: mfd: stm32-timers: Add support for dmas (2018-05-16 11:13:13 +0100)
----------------------------------------------------------------
Immutable branch between MFD and PWM due for the v4.18 merge window (v2)
----------------------------------------------------------------
Fabrice Gasnier (5):
mfd: stm32-timers: Add support for DMAs
pwm: stm32: Add capture support
pwm: stm32: Improve capture by tuning counter prescaler
pwm: stm32: Use input prescaler to improve period capture
dt-bindings: mfd: stm32-timers: Add support for dmas
Documentation/devicetree/bindings/mfd/stm32-timers.txt | 20 ++++
drivers/mfd/stm32-timers.c | 201 +++++++++++++++++++++++++++++++-
drivers/pwm/pwm-stm32.c | 257 +++++++++++++++++++++++++++++++++++++++++
include/linux/mfd/stm32-timers.h | 58 ++++++++++
4 files changed, 534 insertions(+), 2 deletions(-)
--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* Re: [PATCH v4 4/4] rtc: ds1307: add freq_test sysfs attribute to check tick on m41txx
From: Giulio Benetti @ 2018-05-16 10:27 UTC (permalink / raw)
To: a.zummo, alexandre.belloni
Cc: robh+dt, mark.rutland, linux-rtc, devicetree, linux-kernel
In-Reply-To: <20180516100526.73549-4-giulio.benetti@micronovasrl.com>
Oh, sorry, I've forgotten to reword commit log.
I follow with v5 patchset.
Sorry again.
Giulio
Il 16/05/2018 12:05, Giulio Benetti ha scritto:
> On m41txx you can enable open-drain OUT pin to check if offset is ok.
> Enabling OUT pin with freq_test attribute, OUT pin will tick 512 times
> faster than 1s tick base.
>
> Enable or Disable FT bit on CONTROL register if freq_test is 1 or 0.
>
> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
> ---
> V3 => V4:
> * change attribute from freq_test to frequency_test_enable
> * use regmap_update_bits instead of regmap_write
>
> drivers/rtc/rtc-ds1307.c | 99 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 99 insertions(+)
>
> diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
> index 2797d01bfa1d..de98ddc39515 100644
> --- a/drivers/rtc/rtc-ds1307.c
> +++ b/drivers/rtc/rtc-ds1307.c
> @@ -1053,6 +1053,99 @@ static int m41txx_rtc_set_offset(struct device *dev, long offset)
> ctrl_reg);
> }
>
> +static ssize_t frequency_test_enable_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t count)
> +{
> + struct ds1307 *ds1307 = dev_get_drvdata(dev);
> + unsigned long freq_test = 0;
> + int retval;
> +
> + retval = kstrtoul(buf, 10, &freq_test);
> + if ((retval < 0) || (retval > 1)) {
> + dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
> + return -EINVAL;
> + }
> +
> + regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
> + freq_test ? M41TXX_BIT_FT : 0);
> +
> + return retval ? retval : count;
> +}
> +
> +static ssize_t frequency_test_enable_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct ds1307 *ds1307 = dev_get_drvdata(dev);
> + int freq_test_en = 0;
> + unsigned int ctrl_reg;
> +
> + regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
> +
> + if (ctrl_reg & M41TXX_BIT_FT)
> + freq_test_en = true;
> + else
> + freq_test_en = false;
> +
> + return sprintf(buf, "%d\n", freq_test_en);
> +}
> +
> +static DEVICE_ATTR_RW(frequency_test_enable);
> +
> +static struct attribute *rtc_freq_test_attrs[] = {
> + &dev_attr_frequency_test_enable.attr,
> + NULL,
> +};
> +
> +static const struct attribute_group rtc_freq_test_attr_group = {
> + .attrs = rtc_freq_test_attrs,
> +};
> +
> +static void rtc_calib_remove_sysfs_group(void *_dev)
> +{
> + struct device *dev = _dev;
> +
> + sysfs_remove_group(&dev->kobj, &rtc_freq_test_attr_group);
> +}
> +
> +static int ds1307_add_frequency_test(struct ds1307 *ds1307)
> +{
> + int err = 0;
> +
> + switch (ds1307->type) {
> + case m41t0:
> + case m41t00:
> + case m41t11:
> + /* Export sysfs entries */
> + err = sysfs_create_group(&(ds1307->dev)->kobj,
> + &rtc_freq_test_attr_group);
> + if (err) {
> + dev_err(ds1307->dev,
> + "Failed to create sysfs group: %d\n",
> + err);
> + return err;
> + }
> +
> + err = devm_add_action_or_reset(ds1307->dev,
> + rtc_calib_remove_sysfs_group,
> + ds1307->dev);
> + if (err) {
> + dev_err(ds1307->dev,
> + "Failed to add sysfs cleanup action: %d\n",
> + err);
> + sysfs_remove_group(&(ds1307->dev)->kobj,
> + &rtc_freq_test_attr_group);
> + return err;
> + }
> + break;
> + default:
> + break;
> + }
> +
> + return err;
> +}
> +
> /*----------------------------------------------------------------------*/
>
> static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
> @@ -1794,6 +1887,12 @@ static int ds1307_probe(struct i2c_client *client,
> if (err)
> return err;
>
> + err = ds1307_add_frequency_test(ds1307);
> + if (err) {
> + rtc_device_unregister(ds1307->rtc);
> + return err;
> + }
> +
> if (chip->nvram_size) {
> struct nvmem_config nvmem_cfg = {
> .name = "ds1307_nvram",
>
^ permalink raw reply
* [PATCH v5 1/4] rtc: ds1307: fix data pointer to m41t0
From: Giulio Benetti @ 2018-05-16 10:32 UTC (permalink / raw)
To: a.zummo, alexandre.belloni
Cc: robh+dt, mark.rutland, linux-rtc, devicetree, linux-kernel,
Giulio Benetti
data field points to m41t00, instead it should point to m41t0.
Driver works correctly because on both cases(m41t0 and m41t00) chip_desc
are equal.
Point to right enum m41t0 instead of m41t00.
Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
---
drivers/rtc/rtc-ds1307.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
index a13e59edff53..32aadcbc377f 100644
--- a/drivers/rtc/rtc-ds1307.c
+++ b/drivers/rtc/rtc-ds1307.c
@@ -298,7 +298,7 @@ static const struct of_device_id ds1307_of_match[] = {
},
{
.compatible = "st,m41t0",
- .data = (void *)m41t00
+ .data = (void *)m41t0
},
{
.compatible = "st,m41t00",
--
2.17.0
^ permalink raw reply related
* [PATCH v5 2/4] rtc: ds1307: support m41t11 variant
From: Giulio Benetti @ 2018-05-16 10:32 UTC (permalink / raw)
To: a.zummo, alexandre.belloni
Cc: robh+dt, mark.rutland, linux-rtc, devicetree, linux-kernel,
Giulio Benetti
In-Reply-To: <20180516103251.74707-1-giulio.benetti@micronovasrl.com>
The m41t11 variant is very similar to the already supported m41t00 and
m41t0, but it has also 56 bytes of NVRAM.
Add it to driver taking into account NVRAM section.
Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
---
.../devicetree/bindings/rtc/rtc-ds1307.txt | 1 +
drivers/rtc/rtc-ds1307.c | 14 ++++++++++++++
2 files changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt b/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt
index d28d6e7f6ae8..ce6469c1a516 100644
--- a/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt
+++ b/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt
@@ -13,6 +13,7 @@ Required properties:
"maxim,ds3231",
"st,m41t0",
"st,m41t00",
+ "st,m41t11",
"microchip,mcp7940x",
"microchip,mcp7941x",
"pericom,pt7c4338",
diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
index 32aadcbc377f..0ab0c166da83 100644
--- a/drivers/rtc/rtc-ds1307.c
+++ b/drivers/rtc/rtc-ds1307.c
@@ -44,6 +44,7 @@ enum ds_type {
ds_3231,
m41t0,
m41t00,
+ m41t11,
mcp794xx,
rx_8025,
rx_8130,
@@ -226,6 +227,11 @@ static const struct chip_desc chips[last_ds_type] = {
.irq_handler = rx8130_irq,
.rtc_ops = &rx8130_rtc_ops,
},
+ [m41t11] = {
+ /* this is battery backed SRAM */
+ .nvram_offset = 8,
+ .nvram_size = 56,
+ },
[mcp794xx] = {
.alarm = 1,
/* this is battery backed SRAM */
@@ -248,6 +254,7 @@ static const struct i2c_device_id ds1307_id[] = {
{ "ds3231", ds_3231 },
{ "m41t0", m41t0 },
{ "m41t00", m41t00 },
+ { "m41t11", m41t11 },
{ "mcp7940x", mcp794xx },
{ "mcp7941x", mcp794xx },
{ "pt7c4338", ds_1307 },
@@ -304,6 +311,10 @@ static const struct of_device_id ds1307_of_match[] = {
.compatible = "st,m41t00",
.data = (void *)m41t00
},
+ {
+ .compatible = "st,m41t11",
+ .data = (void *)m41t11
+ },
{
.compatible = "microchip,mcp7940x",
.data = (void *)mcp794xx
@@ -346,6 +357,7 @@ static const struct acpi_device_id ds1307_acpi_ids[] = {
{ .id = "DS3231", .driver_data = ds_3231 },
{ .id = "M41T0", .driver_data = m41t0 },
{ .id = "M41T00", .driver_data = m41t00 },
+ { .id = "M41T11", .driver_data = m41t11 },
{ .id = "MCP7940X", .driver_data = mcp794xx },
{ .id = "MCP7941X", .driver_data = mcp794xx },
{ .id = "PT7C4338", .driver_data = ds_1307 },
@@ -1574,6 +1586,7 @@ static int ds1307_probe(struct i2c_client *client,
case ds_1307:
case m41t0:
case m41t00:
+ case m41t11:
/* clock halted? turn it on, so clock can tick. */
if (tmp & DS1307_BIT_CH) {
regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
@@ -1639,6 +1652,7 @@ static int ds1307_probe(struct i2c_client *client,
case ds_1340:
case m41t0:
case m41t00:
+ case m41t11:
/*
* NOTE: ignores century bits; fix before deploying
* systems that will run through year 2100.
--
2.17.0
^ permalink raw reply related
* [PATCH v5 3/4] rtc: ds1307: add offset sysfs for mt41txx chips.
From: Giulio Benetti @ 2018-05-16 10:32 UTC (permalink / raw)
To: a.zummo, alexandre.belloni
Cc: robh+dt, mark.rutland, linux-rtc, devicetree, linux-kernel,
Giulio Benetti
In-Reply-To: <20180516103251.74707-1-giulio.benetti@micronovasrl.com>
m41txx chips can hold a calibration value to get correct clock bias.
Add offset handling (ranging between -63ppm and 126ppm) via sysfs.
Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
---
V3 => V4:
* use ppm as offset input according to documentation instead of
raw ic offset values.
* use regmap_update_bits instead of regmap_write to update ic registers
* sysfs_remove_group if devm_add_action_or_reset fails
* rtc_device_unregister if ds1307_add_frequency_test fails on m41txx
series
drivers/rtc/rtc-ds1307.c | 81 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
index 0ab0c166da83..2797d01bfa1d 100644
--- a/drivers/rtc/rtc-ds1307.c
+++ b/drivers/rtc/rtc-ds1307.c
@@ -114,6 +114,20 @@ enum ds_type {
# define RX8025_BIT_VDET 0x40
# define RX8025_BIT_XST 0x20
+#define M41TXX_REG_CONTROL 0x07
+# define M41TXX_BIT_OUT 0x80
+# define M41TXX_BIT_FT 0x40
+# define M41TXX_BIT_CALIB_SIGN 0x20
+# define M41TXX_M_CALIBRATION 0x1f
+
+/* negative offset step is -2.034ppm */
+#define M41TXX_NEG_OFFSET_STEP_PPM 2034
+/* positive offset step is +4.068ppm */
+#define M41TXX_POS_OFFSET_STEP_PPM 4068
+/* Min and max values supported with 'offset' interface by M41TXX */
+#define M41TXX_MIN_OFFSET (((-31) * M41TXX_NEG_OFFSET_STEP_PPM) / 1000)
+#define M41TXX_MAX_OFFSET (((31) * M41TXX_POS_OFFSET_STEP_PPM) / 1000)
+
struct ds1307 {
enum ds_type type;
unsigned long flags;
@@ -146,6 +160,9 @@ struct chip_desc {
static int ds1307_get_time(struct device *dev, struct rtc_time *t);
static int ds1307_set_time(struct device *dev, struct rtc_time *t);
+static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t);
+static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t);
+static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled);
static u8 do_trickle_setup_ds1339(struct ds1307 *, u32 ohms, bool diode);
static irqreturn_t rx8130_irq(int irq, void *dev_id);
static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t);
@@ -155,6 +172,8 @@ static irqreturn_t mcp794xx_irq(int irq, void *dev_id);
static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t);
static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t);
static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled);
+static int m41txx_rtc_read_offset(struct device *dev, long *offset);
+static int m41txx_rtc_set_offset(struct device *dev, long offset);
static const struct rtc_class_ops rx8130_rtc_ops = {
.read_time = ds1307_get_time,
@@ -172,6 +191,16 @@ static const struct rtc_class_ops mcp794xx_rtc_ops = {
.alarm_irq_enable = mcp794xx_alarm_irq_enable,
};
+static const struct rtc_class_ops m41txx_rtc_ops = {
+ .read_time = ds1307_get_time,
+ .set_time = ds1307_set_time,
+ .read_alarm = ds1337_read_alarm,
+ .set_alarm = ds1337_set_alarm,
+ .alarm_irq_enable = ds1307_alarm_irq_enable,
+ .read_offset = m41txx_rtc_read_offset,
+ .set_offset = m41txx_rtc_set_offset,
+};
+
static const struct chip_desc chips[last_ds_type] = {
[ds_1307] = {
.nvram_offset = 8,
@@ -227,10 +256,17 @@ static const struct chip_desc chips[last_ds_type] = {
.irq_handler = rx8130_irq,
.rtc_ops = &rx8130_rtc_ops,
},
+ [m41t0] = {
+ .rtc_ops = &m41txx_rtc_ops,
+ },
+ [m41t00] = {
+ .rtc_ops = &m41txx_rtc_ops,
+ },
[m41t11] = {
/* this is battery backed SRAM */
.nvram_offset = 8,
.nvram_size = 56,
+ .rtc_ops = &m41txx_rtc_ops,
},
[mcp794xx] = {
.alarm = 1,
@@ -972,6 +1008,51 @@ static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
enabled ? MCP794XX_BIT_ALM0_EN : 0);
}
+static int m41txx_rtc_read_offset(struct device *dev, long *offset)
+{
+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
+ unsigned int ctrl_reg;
+ u8 val;
+
+ regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
+
+ val = ctrl_reg & M41TXX_M_CALIBRATION;
+
+ /* check if positive */
+ if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
+ *offset = (val * M41TXX_POS_OFFSET_STEP_PPM);
+ else
+ *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPM);
+
+ *offset = DIV_ROUND_CLOSEST(*offset, 1000);
+
+ return 0;
+}
+
+static int m41txx_rtc_set_offset(struct device *dev, long offset)
+{
+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
+ unsigned int ctrl_reg;
+
+ if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
+ return -ERANGE;
+
+ offset *= 1000;
+
+ if (offset >= 0) {
+ ctrl_reg = DIV_ROUND_CLOSEST(offset,
+ M41TXX_POS_OFFSET_STEP_PPM);
+ ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
+ } else {
+ ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
+ M41TXX_NEG_OFFSET_STEP_PPM);
+ }
+
+ return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
+ M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
+ ctrl_reg);
+}
+
/*----------------------------------------------------------------------*/
static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
--
2.17.0
^ permalink raw reply related
* [PATCH v5 4/4] rtc: ds1307: add frequency_test_enable sysfs attribute to check tick on m41txx
From: Giulio Benetti @ 2018-05-16 10:32 UTC (permalink / raw)
To: a.zummo, alexandre.belloni
Cc: robh+dt, mark.rutland, linux-rtc, devicetree, linux-kernel,
Giulio Benetti
In-Reply-To: <20180516103251.74707-1-giulio.benetti@micronovasrl.com>
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with frequency_test_enable attribute, OUT pin will tick
512 times faster than 1s tick base.
Enable or Disable FT bit on CONTROL register if freq_test is 1 or 0.
Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
---
V3 => V4:
* change attribute from freq_test to frequency_test_enable
* use regmap_update_bits instead of regmap_write
V4 => V5:
* update commit log
drivers/rtc/rtc-ds1307.c | 99 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 99 insertions(+)
diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
index 2797d01bfa1d..de98ddc39515 100644
--- a/drivers/rtc/rtc-ds1307.c
+++ b/drivers/rtc/rtc-ds1307.c
@@ -1053,6 +1053,99 @@ static int m41txx_rtc_set_offset(struct device *dev, long offset)
ctrl_reg);
}
+static ssize_t frequency_test_enable_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
+ unsigned long freq_test = 0;
+ int retval;
+
+ retval = kstrtoul(buf, 10, &freq_test);
+ if ((retval < 0) || (retval > 1)) {
+ dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
+ return -EINVAL;
+ }
+
+ regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
+ freq_test ? M41TXX_BIT_FT : 0);
+
+ return retval ? retval : count;
+}
+
+static ssize_t frequency_test_enable_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct ds1307 *ds1307 = dev_get_drvdata(dev);
+ int freq_test_en = 0;
+ unsigned int ctrl_reg;
+
+ regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
+
+ if (ctrl_reg & M41TXX_BIT_FT)
+ freq_test_en = true;
+ else
+ freq_test_en = false;
+
+ return sprintf(buf, "%d\n", freq_test_en);
+}
+
+static DEVICE_ATTR_RW(frequency_test_enable);
+
+static struct attribute *rtc_freq_test_attrs[] = {
+ &dev_attr_frequency_test_enable.attr,
+ NULL,
+};
+
+static const struct attribute_group rtc_freq_test_attr_group = {
+ .attrs = rtc_freq_test_attrs,
+};
+
+static void rtc_calib_remove_sysfs_group(void *_dev)
+{
+ struct device *dev = _dev;
+
+ sysfs_remove_group(&dev->kobj, &rtc_freq_test_attr_group);
+}
+
+static int ds1307_add_frequency_test(struct ds1307 *ds1307)
+{
+ int err = 0;
+
+ switch (ds1307->type) {
+ case m41t0:
+ case m41t00:
+ case m41t11:
+ /* Export sysfs entries */
+ err = sysfs_create_group(&(ds1307->dev)->kobj,
+ &rtc_freq_test_attr_group);
+ if (err) {
+ dev_err(ds1307->dev,
+ "Failed to create sysfs group: %d\n",
+ err);
+ return err;
+ }
+
+ err = devm_add_action_or_reset(ds1307->dev,
+ rtc_calib_remove_sysfs_group,
+ ds1307->dev);
+ if (err) {
+ dev_err(ds1307->dev,
+ "Failed to add sysfs cleanup action: %d\n",
+ err);
+ sysfs_remove_group(&(ds1307->dev)->kobj,
+ &rtc_freq_test_attr_group);
+ return err;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return err;
+}
+
/*----------------------------------------------------------------------*/
static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
@@ -1794,6 +1887,12 @@ static int ds1307_probe(struct i2c_client *client,
if (err)
return err;
+ err = ds1307_add_frequency_test(ds1307);
+ if (err) {
+ rtc_device_unregister(ds1307->rtc);
+ return err;
+ }
+
if (chip->nvram_size) {
struct nvmem_config nvmem_cfg = {
.name = "ds1307_nvram",
--
2.17.0
^ permalink raw reply related
* [PATCH] arm64: dts: juno: fix graph node unit addresses for coresight components
From: Sudeep Holla @ 2018-05-16 10:34 UTC (permalink / raw)
To: linux-arm-kernel, devicetree
Cc: Suzuki K Poulose, Liviu Dudau, Mathieu Poirier, Sudeep Holla
Currently the coresight components graph node unit addresses are
continuous for both input and output ports while the "reg" properties
are restarted for input and output ports separately. This results is
the following DTC warnings:
(graph_port): /etf@20010000/ports/port@1: graph node unit address error, expected "0"
(graph_port): /etf@20140000/ports/port@1: graph node unit address error, expected "0"
(graph_port): /funnel@20040000/ports/port@1: graph node unit address error, expected "0"
(graph_port): /funnel@20040000/ports/port@2: graph node unit address error, expected "1"
(graph_port): /funnel@20040000/ports/port@3: graph node unit address error, expected "2"
(graph_port): /funnel@20130000/ports/port@1: graph node unit address error, expected "0"
(graph_port): /funnel@20150000/ports/port@1: graph node unit address error, expected "0"
(graph_port): /funnel@20150000/ports/port@2: graph node unit address error, expected "1"
(graph_port): /funnel@220c0000/ports/port@1: graph node unit address error, expected "0"
(graph_port): /funnel@220c0000/ports/port@2: graph node unit address error, expected "1"
(graph_port): /funnel@230c0000/ports/port@1: graph node unit address error, expected "0"
(graph_port): /funnel@230c0000/ports/port@2: graph node unit address error, expected "1"
(graph_port): /funnel@230c0000/ports/port@3: graph node unit address error, expected "2"
(graph_port): /funnel@230c0000/ports/port@4: graph node unit address error, expected "3"
(graph_port): /replicator@20120000/ports/port@2: graph node unit address error, expected "0"
This patch makes even the reg property to follow the continuous
numbering as in the graph node unit address.
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 20 ++++++++++----------
arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 8 ++++----
arch/arm64/boot/dts/arm/juno.dts | 2 +-
3 files changed, 15 insertions(+), 15 deletions(-)
Hi Suzuki/Mathieu,
I did a quick scan @ drivers/hwtracing/coresight/of_coresight.c to check
if reg field is being used or not and whether this change causes any
regression. I don't think so, but I may be wrong, let me know.
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 708a15887af4..dbeca292a57c 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -131,7 +131,7 @@
/* output port */
port@1 {
- reg = <0>;
+ reg = <1>;
etf0_out_port: endpoint {
};
};
@@ -175,7 +175,7 @@
/* input ports */
port@1 {
- reg = <0>;
+ reg = <1>;
main_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&cluster0_funnel_out_port>;
@@ -183,7 +183,7 @@
};
port@2 {
- reg = <1>;
+ reg = <2>;
main_funnel_in_port1: endpoint {
slave-mode;
remote-endpoint = <&cluster1_funnel_out_port>;
@@ -265,7 +265,7 @@
};
port@1 {
- reg = <0>;
+ reg = <1>;
cluster0_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&cluster0_etm0_out_port>;
@@ -273,7 +273,7 @@
};
port@2 {
- reg = <1>;
+ reg = <2>;
cluster0_funnel_in_port1: endpoint {
slave-mode;
remote-endpoint = <&cluster0_etm1_out_port>;
@@ -347,7 +347,7 @@
};
port@1 {
- reg = <0>;
+ reg = <1>;
cluster1_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&cluster1_etm0_out_port>;
@@ -355,21 +355,21 @@
};
port@2 {
- reg = <1>;
+ reg = <2>;
cluster1_funnel_in_port1: endpoint {
slave-mode;
remote-endpoint = <&cluster1_etm1_out_port>;
};
};
port@3 {
- reg = <2>;
+ reg = <3>;
cluster1_funnel_in_port2: endpoint {
slave-mode;
remote-endpoint = <&cluster1_etm2_out_port>;
};
};
port@4 {
- reg = <3>;
+ reg = <4>;
cluster1_funnel_in_port3: endpoint {
slave-mode;
remote-endpoint = <&cluster1_etm3_out_port>;
@@ -476,7 +476,7 @@
/* replicator input port */
port@2 {
- reg = <0>;
+ reg = <2>;
replicator_in_port0: endpoint {
slave-mode;
};
diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi
index 21287f2d75d3..a99f311c8dcb 100644
--- a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi
@@ -21,7 +21,7 @@
/* input port */
port@1 {
- reg = <0>;
+ reg = <1>;
csys1_funnel_in_port0: endpoint {
slave-mode;
};
@@ -52,7 +52,7 @@
/* output port */
port@1 {
- reg = <0>;
+ reg = <1>;
etf1_out_port: endpoint {
remote-endpoint = <&csys2_funnel_in_port1>;
};
@@ -81,7 +81,7 @@
/* input ports */
port@1 {
- reg = <0>;
+ reg = <1>;
csys2_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&etf0_out_port>;
@@ -89,7 +89,7 @@
};
port@2 {
- reg = <1>;
+ reg = <2>;
csys2_funnel_in_port1: endpoint {
slave-mode;
remote-endpoint = <&etf1_out_port>;
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index aa3b341a7547..34e940e7465b 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -260,7 +260,7 @@
&main_funnel {
ports {
port@3 {
- reg = <2>;
+ reg = <3>;
main_funnel_in_port2: endpoint {
slave-mode;
remote-endpoint = <&stm_out_port>;
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v10 00/27] ARM: davinci: convert to common clock framework
From: Sekhar Nori @ 2018-05-16 10:43 UTC (permalink / raw)
To: Bartosz Golaszewski, Adam Ford
Cc: Bartosz Golaszewski, David Lechner, linux-clk, devicetree,
arm-soc, Michael Turquette, Stephen Boyd, Rob Herring,
Mark Rutland, Kevin Hilman, Linux Kernel Mailing List
In-Reply-To: <CAMpxmJUKGS_wm1O+HJBt2yY=BQ4169ka1p0264O-PJFdGj5Fdg@mail.gmail.com>
On Wednesday 16 May 2018 01:17 PM, Bartosz Golaszewski wrote:
> 2018-05-16 0:44 GMT+02:00 Adam Ford <aford173@gmail.com>:
>> On Tue, May 15, 2018 at 4:25 AM, Bartosz Golaszewski <brgl@bgdev.pl> wrote:
>>> 2018-05-14 2:40 GMT+02:00 Adam Ford <aford173@gmail.com>:
>>>> On Wed, May 9, 2018 at 12:25 PM, David Lechner <david@lechnology.com> wrote:
>>>>> This series converts mach-davinci to use the common clock framework.
>>>>>
>>>>> The series works like this, the first 3 patches fix some issues with the clock
>>>>> drivers that have already been accepted into the mainline kernel.
>>>>>
>>>>> Then, starting with "ARM: davinci: pass clock as parameter to
>>>>> davinci_timer_init()", we get the mach code ready for the switch by adding the
>>>>> code needed for the new clock drivers and adding #ifndef CONFIG_COMMON_CLK
>>>>> around the legacy clocks so that we can switch easily between the old and the
>>>>> new.
>>>>>
>>>>> "ARM: davinci: switch to common clock framework" actually flips the switch
>>>>> to start using the new clock drivers. Then the next 8 patches remove all
>>>>> of the old clock code.
>>>>>
>>>>> The final four patches add device tree clock support to the one SoC that
>>>>> supports it.
>>>>>
>>>>> This series has been tested on TI OMAP-L138 LCDK (both device tree and legacy
>>>>> board file).
>>>>>
>>>>
>>>> I am not sure if I did something wrong, but I attempted to build and I
>>>> wasn't able to boot the da850-evm.dtb your repo common-clk-v11,
>>>> however the legacy board file boot was OK.
>>>>
>>>> make davinci_all_defconfig ARCH=arm
>>>> make zImage modules da850-evm.dtb ARCH=arm CROSS_COMPILE=arm-linux- -j8
>>>>
>>>> 3140416 bytes read in 1464 ms (2 MiB/s)
>>>> 20353 bytes read in 15 ms (1.3 MiB/s)
>>>> ## Flattened Device Tree blob at c0600000
>>>> Booting using the fdt blob at 0xc0600000
>>>> Loading Device Tree to c7e57000, end c7e5ef80 ... OK
>>>>
>>>> Starting kernel ...
>>>>
>>>> Uncompressing Linux... done, booting the kernel.
>>>>
>>>> (and hang)
>>>>
>>>> If you have some suggestions, I am try them as I get time.
>>>>
>>>> adam
>>>>
>>>
>>> Runs fine on da850-lcdk and dm365-evm. I'll test the da850-evm
>>> tomorrow when I'll have access to it.
>>
>> I set the bootargs to: bootargs=console=ttyS2,115200n8
>> clk_ignore_unused root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait
>>
>> I enabled DEBUG_LL and EARLY_PRINTK, yet when it loads, I only get:
With DEBUG_LL, you dont get any prints "automatically". You need add
printascii() calls where you need. I use the attached patch which
patches printk() calls with printascii()[1]
>>
>> ## Flattened Device Tree blob at c0600000
>> Booting using the fdt blob at 0xc0600000
>> Loading Device Tree to c7e57000, end c7e5ef35 ... OK
>>
>> Starting kernel ...
>>
>> Uncompressing Linux... done, booting the kernel.
>>
>>
>> I am doing this at my home, so I don't have a debugger for the
>> DA850-EVM. I am using a SOM that is an AM1808, but I vaguely remember
>> something about enabling a DSP clock somewhere, but I cannot seem to
>> find the e-mail. I know its counter intuitive that we'd need to
>> enable a clock that runs the DSP since it doesn't exist on the AM1808,
>> but I would have thought the clk_ignore_unused would have worked
>> around that issue.
>>
>> If someone else has a DA850-EVM or suggestions, I'm willing to try
>> them as I have time.
>>
>> adam
>
> Hi Adam,
>
> everything works fine for me both when booting the DTB and in legacy
> mode on da850-evm.
>
> I'm using the following bootargs:
> ip=dhcp console=ttyS2,115200n8 root=/dev/nfs rw nfsroot=<snip!>,v3
> nfsrootdebug
>
> Regular davinci_all_defconfig on David's common-clk-v11 branch.
Adam, if you still cannot get it to work, one problem could be that the
DT size has increased and its being overwritten. You could look at where
you are loading various binaries. Or append the .dtb to zImage and
switch on APPENDED_DTB config in kernel.
Thanks,
Sekhar
[1]
diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
index 5b5a708..c3419c0 100644
--- a/kernel/printk/printk.c
+++ b/kernel/printk/printk.c
@@ -1488,6 +1488,7 @@ static size_t cont_print_text(char *text, size_t size)
return textlen;
}
+void printascii(char *);
asmlinkage int vprintk_emit(int facility, int level,
const char *dict, size_t dictlen,
const char *fmt, va_list args)
@@ -1552,6 +1553,7 @@ asmlinkage int vprintk_emit(int facility, int level,
text_len--;
lflags |= LOG_NEWLINE;
}
+ printascii(text);
/* strip kernel syslog prefix and extract log level or control flags */
if (facility == 0) {
^ permalink raw reply related
* Re: [PATCH net-next v2 2/2] drivers: net: Remove device_node checks with of_mdiobus_register()
From: Jose Abreu @ 2018-05-16 11:01 UTC (permalink / raw)
To: Florian Fainelli, netdev
Cc: Andrew Lunn, Vivien Didelot, David S. Miller, Nicolas Ferre,
Fugang Duan, Sergei Shtylyov, Giuseppe Cavallaro,
Alexandre Torgue, Jose Abreu, Grygorii Strashko, Woojung Huh,
Microchip Linux Driver Support, Rob Herring, Frank Rowand,
Antoine Tenart, Tobias Jordan, Russell King, Geert
In-Reply-To: <20180515235619.27773-3-f.fainelli@gmail.com>
On 16-05-2018 00:56, Florian Fainelli wrote:
> A number of drivers have the following pattern:
>
> if (np)
> of_mdiobus_register()
> else
> mdiobus_register()
>
> which the implementation of of_mdiobus_register() now takes care of.
> Remove that pattern in drivers that strictly adhere to it.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> drivers/net/dsa/bcm_sf2.c | 8 ++------
> drivers/net/dsa/mv88e6xxx/chip.c | 5 +----
> drivers/net/ethernet/cadence/macb_main.c | 12 +++---------
> drivers/net/ethernet/freescale/fec_main.c | 8 ++------
> drivers/net/ethernet/marvell/mvmdio.c | 5 +----
> drivers/net/ethernet/renesas/sh_eth.c | 11 +++--------
> drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 5 +----
For stmmac:
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Thanks and Best Regards,
Jose Miguel Abreu
> drivers/net/ethernet/ti/davinci_mdio.c | 8 +++-----
> drivers/net/phy/mdio-gpio.c | 6 +-----
> drivers/net/phy/mdio-mscc-miim.c | 6 +-----
> drivers/net/usb/lan78xx.c | 7 ++-----
> 11 files changed, 20 insertions(+), 61 deletions(-)
>
^ permalink raw reply
* Re: [PATCH] arm64: dts: juno: fix graph node unit addresses for coresight components
From: Suzuki K Poulose @ 2018-05-16 11:23 UTC (permalink / raw)
To: Sudeep Holla, linux-arm-kernel, devicetree; +Cc: Liviu Dudau, Mathieu Poirier
In-Reply-To: <1526466862-19173-1-git-send-email-sudeep.holla@arm.com>
On 05/16/2018 11:34 AM, Sudeep Holla wrote:
> Currently the coresight components graph node unit addresses are
> continuous for both input and output ports while the "reg"
> properties are restarted for input and output ports separately. This
> results is the following DTC warnings:
>
> (graph_port): /etf@20010000/ports/port@1: graph node unit address
> error, expected "0" (graph_port): /etf@20140000/ports/port@1: graph
> node unit address error, expected "0" (graph_port):
> /funnel@20040000/ports/port@1: graph node unit address error,
> expected "0" (graph_port): /funnel@20040000/ports/port@2: graph node
> unit address error, expected "1" (graph_port):
> /funnel@20040000/ports/port@3: graph node unit address error,
> expected "2" (graph_port): /funnel@20130000/ports/port@1: graph node
> unit address error, expected "0" (graph_port):
> /funnel@20150000/ports/port@1: graph node unit address error,
> expected "0" (graph_port): /funnel@20150000/ports/port@2: graph node
> unit address error, expected "1" (graph_port):
> /funnel@220c0000/ports/port@1: graph node unit address error,
> expected "0" (graph_port): /funnel@220c0000/ports/port@2: graph node
> unit address error, expected "1" (graph_port):
> /funnel@230c0000/ports/port@1: graph node unit address error,
> expected "0" (graph_port): /funnel@230c0000/ports/port@2: graph node
> unit address error, expected "1" (graph_port):
> /funnel@230c0000/ports/port@3: graph node unit address error,
> expected "2" (graph_port): /funnel@230c0000/ports/port@4: graph node
> unit address error, expected "3" (graph_port):
> /replicator@20120000/ports/port@2: graph node unit address error,
> expected "0"
>
> This patch makes even the reg property to follow the continuous
> numbering as in the graph node unit address.
>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mathieu Poirier
> <mathieu.poirier@linaro.org> Cc: Liviu Dudau <liviu.dudau@arm.com>
> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>> ---
> arch/arm64/boot/dts/arm/juno-base.dtsi | 20 ++++++++++----------
> arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 8 ++++----
> arch/arm64/boot/dts/arm/juno.dts | 2 +- 3 files changed, 15
> insertions(+), 15 deletions(-)
>
> Hi Suzuki/Mathieu,
>
> I did a quick scan @ drivers/hwtracing/coresight/of_coresight.c to
> check if reg field is being used or not and whether this change
> causes any regression. I don't think so, but I may be wrong, let me
> know.
Unfortunately, I think this would break the components like funnel,
where we need the input port number for the connected master to enable
the port. Similarly for the output port number for master components in
the paths. I have a set of patches which address this by taking care of
the port number order to find out the hardware port number.
I will dust it up and send it. That would bring up another important
question.
How do we deal with the change in the port number scheme ? e.g, should
the new kernel support DTBs with old scheme ? If so, how do we specify
that the DT uses new scheme.
Cheers
Suzuki
^ permalink raw reply
* [PATCH 1/1] ARM:dts:sunxi: Add Olimex A20-SOM-EVB-eMMC board
From: Stefan Mavrodiev @ 2018-05-16 11:38 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Maxime Ripard, Chen-Yu Tsai,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, moderated list:ARM/Allwinner sunXi SoC support
Cc: linux-sunxi, Stefan Mavrodiev
With the new rev.E of A20-SOM-EVB, there is option for 16GB eMMC.
Currently used card is KLMAG2GEND, wired to MMC2 slot.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
---
arch/arm/boot/dts/Makefile | 1 +
.../arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts | 37 ++++++++++++++++++++++
2 files changed, 38 insertions(+)
create mode 100644 arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 1db91ec..7f1ee65 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -959,6 +959,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-m3.dtb \
sun7i-a20-mk808c.dtb \
sun7i-a20-olimex-som-evb.dtb \
+ sun7i-a20-olimex-som-evb-emmc.dtb \
sun7i-a20-olimex-som204-evb.dtb \
sun7i-a20-olimex-som204-evb-emmc.dtb \
sun7i-a20-olinuxino-lime.dtb \
diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts
new file mode 100644
index 0000000..81ebc97
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-Olimex-SOM-EVB-eMMC Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ * Author: Stefan Mavrodiev <stefan@olimex.com>
+ */
+
+/dts-v1/;
+#include "sun7i-a20-olimex-som-evb.dts"
+
+/ {
+
+ model = "Olimex A20-Olimex-SOM-EVB-eMMC";
+ compatible = "olimex,a20-olimex-som-evb-emmc", "allwinner,sun7i-a20";
+
+ mmc2_pwrseq: mmc2_pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&pio 2 18 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&mmc2_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ emmc: emmc@0 {
+ reg = <0>;
+ compatible = "mmc-card";
+ broken-hpi;
+ };
+};
--
2.7.4
^ permalink raw reply related
* Re: [PATCH] arm64: dts: juno: fix graph node unit addresses for coresight components
From: Sudeep Holla @ 2018-05-16 11:49 UTC (permalink / raw)
To: Suzuki K Poulose, linux-arm-kernel, devicetree
Cc: Liviu Dudau, Mathieu Poirier, Sudeep Holla
In-Reply-To: <574f6959-6a84-9e0e-3d89-84d2d75d9191@arm.com>
On 16/05/18 12:23, Suzuki K Poulose wrote:
> On 05/16/2018 11:34 AM, Sudeep Holla wrote:
[..]
>> Hi Suzuki/Mathieu,
>>
>> I did a quick scan @ drivers/hwtracing/coresight/of_coresight.c to
>> check if reg field is being used or not and whether this change
>> causes any regression. I don't think so, but I may be wrong, let me
>> know.
>
> Unfortunately, I think this would break the components like funnel,
> where we need the input port number for the connected master to enable
> the port. Similarly for the output port number for master components in
> the paths. I have a set of patches which address this by taking care of
> the port number order to find out the hardware port number.
>
Ah ok, I now see of_graph_parse_endpoint, sorry for missing that.
> I will dust it up and send it. That would bring up another important
> question.
>
Cool
> How do we deal with the change in the port number scheme ? e.g, should
> the new kernel support DTBs with old scheme ?
IIUC, that's needed for backward compatibility as it was used schema.
Again I may be wrong.
> If so, how do we specify that the DT uses new scheme.
Perhaps, add something to indicate the change in numbering scheme ?
--
Regards,
Sudeep
^ permalink raw reply
* Re: [PATCH v5 1/7] gpio: pca953x: convert register constants to hex
From: Linus Walleij @ 2018-05-16 11:49 UTC (permalink / raw)
To: H. Nikolaus Schaller
Cc: Kumar Gala, Andy Shevchenko, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Alexandre Courbot,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org,
Discussions about the Letux Kernel, kernel
In-Reply-To: <56bf53debf69534a452538e689dc15f94aea31a4.1524933096.git.hns@goldelico.com>
On Sat, Apr 28, 2018 at 6:31 PM, H. Nikolaus Schaller <hns@goldelico.com> wrote:
> which makes it easier to match them with the data sheets.
>
> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Patch applied with Andy's ACK.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v5 2/7] gpio: pca953x: add more register definitions for pcal953x
From: Linus Walleij @ 2018-05-16 11:51 UTC (permalink / raw)
To: H. Nikolaus Schaller
Cc: Kumar Gala, Andy Shevchenko, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Alexandre Courbot,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org,
Discussions about the Letux Kernel, kernel
In-Reply-To: <79da0e04213915b797222027bbeaebf513387e62.1524933096.git.hns@goldelico.com>
On Sat, Apr 28, 2018 at 6:31 PM, H. Nikolaus Schaller <hns@goldelico.com> wrote:
> PCAL chips ("L" seems to stand for "latched") have additional
> registers starting at address 0x40 to control the latches,
> interrupt mask, pull-up and pull down etc.
>
> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Patch applied with Andy's ACK.
Yours,
Linus Walleij
^ permalink raw reply
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