* Re: [PATCH v5 2/7] gpio: pca953x: add more register definitions for pcal953x
From: Linus Walleij @ 2018-05-16 11:51 UTC (permalink / raw)
To: H. Nikolaus Schaller
Cc: Kumar Gala, Andy Shevchenko, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Alexandre Courbot,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org,
Discussions about the Letux Kernel, kernel
In-Reply-To: <79da0e04213915b797222027bbeaebf513387e62.1524933096.git.hns@goldelico.com>
On Sat, Apr 28, 2018 at 6:31 PM, H. Nikolaus Schaller <hns@goldelico.com> wrote:
> PCAL chips ("L" seems to stand for "latched") have additional
> registers starting at address 0x40 to control the latches,
> interrupt mask, pull-up and pull down etc.
>
> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Patch applied with Andy's ACK.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v5 3/7] gpio: pca953x: add more register definitions for pcal6524
From: Linus Walleij @ 2018-05-16 11:52 UTC (permalink / raw)
To: H. Nikolaus Schaller
Cc: Kumar Gala, Andy Shevchenko, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Alexandre Courbot,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org,
Discussions about the Letux Kernel, kernel
In-Reply-To: <3cb7c78f496ec9933288b7aac7b4ee9c55d9037d.1524933096.git.hns@goldelico.com>
On Sat, Apr 28, 2018 at 6:31 PM, H. Nikolaus Schaller <hns@goldelico.com> wrote:
> The pcal6524 has another set of registers to fine control
> the interrupt handling.
>
> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Patch applied with Andy's ACK.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v5 0/7] pcal6524 extensions and fixes for pca953x driver
From: Linus Walleij @ 2018-05-16 11:53 UTC (permalink / raw)
To: H. Nikolaus Schaller
Cc: Kumar Gala, Andy Shevchenko, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Alexandre Courbot,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org,
Discussions about the Letux Kernel, kernel
In-Reply-To: <cover.1524933096.git.hns@goldelico.com>
On Sat, Apr 28, 2018 at 6:31 PM, H. Nikolaus Schaller <hns@goldelico.com> wrote:
> V5:
> * fix wrong split up between patches 1/7and 2/7.
I applied patches 1, 2, 3 so we get some movement on the patch
set and not too much for you to rebase.
It's fine to just resend the rest next time.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v5 6/7] DTS: Bindings: pca953x add an optional vcc-supply property
From: Linus Walleij @ 2018-05-16 11:55 UTC (permalink / raw)
To: H. Nikolaus Schaller
Cc: Kumar Gala, Andy Shevchenko, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Alexandre Courbot,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org,
Discussions about the Letux Kernel, kernel
In-Reply-To: <de4bade4236415f62088d68cd5fcd6fb7b67e020.1524933096.git.hns@goldelico.com>
On Sat, Apr 28, 2018 at 6:31 PM, H. Nikolaus Schaller <hns@goldelico.com> wrote:
> Hardware can have a switchable Vcc supply, so let's add it to
> the bindings (the current Linux driver code already supports it).
>
> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v5 7/7] DTS: Bindings: pca953x: add example how to use interrupt-controller and gpio-controller
From: Linus Walleij @ 2018-05-16 11:56 UTC (permalink / raw)
To: H. Nikolaus Schaller
Cc: Kumar Gala, Andy Shevchenko, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Alexandre Courbot,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org,
Discussions about the Letux Kernel, kernel
In-Reply-To: <23c048310088d42c99c3c20a83795c97d1b8f1cc.1524933096.git.hns@goldelico.com>
On Sat, Apr 28, 2018 at 6:31 PM, H. Nikolaus Schaller <hns@goldelico.com> wrote:
> It is not completely obvious that these are required and
> how to use them. So we provide a tested example.
>
> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v5 0/7] pcal6524 extensions and fixes for pca953x driver
From: Linus Walleij @ 2018-05-16 11:56 UTC (permalink / raw)
To: H. Nikolaus Schaller
Cc: Kumar Gala, Andy Shevchenko, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Alexandre Courbot,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org,
Discussions about the Letux Kernel, kernel
In-Reply-To: <CACRpkdbk0rNZ3cUN_noqVtNYgDrydGtCCn2fk7yqVRPoroYqpA@mail.gmail.com>
On Wed, May 16, 2018 at 1:53 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Sat, Apr 28, 2018 at 6:31 PM, H. Nikolaus Schaller <hns@goldelico.com> wrote:
>
>> V5:
>> * fix wrong split up between patches 1/7and 2/7.
>
> I applied patches 1, 2, 3 so we get some movement on the patch
> set and not too much for you to rebase.
>
> It's fine to just resend the rest next time.
Oh also 6,7 was ripe. So only two patches to resend :)
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v7 2/3] pinctrl: bcm2835: Add support for generic pinctrl binding
From: Linus Walleij @ 2018-05-16 12:00 UTC (permalink / raw)
To: Matheus Castello
Cc: Stefan Wahren, Eric Anholt, Stephen Warren, Rob Herring,
Mark Rutland, linux-kernel@vger.kernel.org,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
In-Reply-To: <1525135334-28506-2-git-send-email-matheus@castello.eng.br>
On Tue, May 1, 2018 at 2:42 AM, Matheus Castello
<matheus@castello.eng.br> wrote:
> To keep driver up to date we add generic pinctrl binding support, which
> covers the features used in this driver and has additional node properties
> that this SoC has compatibility, so enabling future implementations of
> these properties without the need to create new node properties in the
> device trees.
>
> The logic of this change maintain the old brcm legacy binding support in
> order to keep the ABI stable.
>
> Signed-off-by: Matheus Castello <matheus@castello.eng.br>
> Reviewed-by: Eric Anholt <eric@anholt.net>
Patch applied with Stefan's ACK!
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v7 3/3] pinctrl: bcm2835: Add support for output-low output-high properties
From: Linus Walleij @ 2018-05-16 12:02 UTC (permalink / raw)
To: Matheus Castello
Cc: Stefan Wahren, Eric Anholt, Stephen Warren, Rob Herring,
Mark Rutland, linux-kernel@vger.kernel.org,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
In-Reply-To: <1525135334-28506-3-git-send-email-matheus@castello.eng.br>
On Tue, May 1, 2018 at 2:42 AM, Matheus Castello
<matheus@castello.eng.br> wrote:
> Properties to set initial value of pin output buffer.
> This can be useful for configure hardware in overlay files, and in early
> boot for checking it states in QA sanity tests.
>
> Signed-off-by: Matheus Castello <matheus@castello.eng.br>
> Reviewed-by: Eric Anholt <eric@anholt.net>
Patch applied with Stefan's ACK.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: gpio-xilinx: Update no-init property
From: Linus Walleij @ 2018-05-16 12:12 UTC (permalink / raw)
To: Shubhrajyoti Datta
Cc: open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
git-dev, Rob Herring, michals, Shubhrajyoti Datta
In-Reply-To: <1525338346-31684-1-git-send-email-shubhrajyoti.datta@gmail.com>
On Thu, May 3, 2018 at 11:05 AM, <shubhrajyoti.datta@gmail.com> wrote:
> From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
>
> In some cases the user may not want to initialise the
> gpios to default. Add a property to allow the same. This is specially
> useful in case the PS is reset and PL is not.
>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
(...)
> @@ -25,6 +25,7 @@ Optional properties:
> - xlnx,dout-default-2 : as above but the second channel
> - xlnx,gpio2-width : as above but for the second channel
> - xlnx,tri-default-2 : as above but for the second channel
> +- xlnx,no-init : No initialisation at probe
This doesn't seem very Xilinx-specific? It looks more like something
any GPIO driver would want to do.
So a no-init-hardware; in gpio.txt seems more appropriate,
if this is even needed, see comments on next patch.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 2/2] gpio: xilinx: Add support for no initialisation at probe
From: Linus Walleij @ 2018-05-16 12:14 UTC (permalink / raw)
To: Shubhrajyoti Datta, michals
Cc: open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
git-dev, Rob Herring, Shubhrajyoti Datta
In-Reply-To: <1525338346-31684-2-git-send-email-shubhrajyoti.datta@gmail.com>
On Thu, May 3, 2018 at 11:05 AM, <shubhrajyoti.datta@gmail.com> wrote:
> From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
>
> Add a dt property to indicate no initialisation at probe.
> In some cases the user may want no initialisation of the
> gpios. For example PS only reset the user may not want the
> re-initialisation of the ip.
>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Usually the recommendation is to leave electronics in the
power-on-state until their state is explicitly changed.
Is it possible to just make the new "no-init" behaviour
the default? Do we even need to keep the initialization code?
Michal?
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 3/7] pinctrl: sunxi: add support for H6 R_PIO pin controller
From: Linus Walleij @ 2018-05-16 12:20 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Maxime Ripard, Chen-Yu Tsai, linux-clk,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
open list:GPIO SUBSYSTEM, linux-sunxi
In-Reply-To: <20180503183847.11046-4-icenowy-h8G6r0blFSE@public.gmane.org>
On Thu, May 3, 2018 at 8:38 PM, Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org> wrote:
> Allwinner H6 SoC has a R_PIO pin controller like other Allwinner SoCs,
> which controls the PL and PM pin banks.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
Patch applied with the ACKs.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v5 05/14] usb: typec: add API to get typec basic port power and data config
From: Heikki Krogerus @ 2018-05-16 12:25 UTC (permalink / raw)
To: Jun Li, Mats Karrman
Cc: robh+dt@kernel.org, gregkh@linuxfoundation.org,
linux@roeck-us.net, a.hajda@samsung.com, cw00.choi@samsung.com,
shufan_lee@richtek.com, Peter Chen, gsomlo@gmail.com,
devicetree@vger.kernel.org, linux-usb@vger.kernel.org,
dl-linux-imx
In-Reply-To: <74e1c164-1652-75f4-409c-bd1c214bda4d@gmail.com>
Hi guys,
On Tue, May 15, 2018 at 10:52:57PM +0200, Mats Karrman wrote:
> Hi,
>
> On 05/14/2018 11:36 AM, Jun Li wrote:
>
> > Hi
> >> -----Original Message-----
> >> From: Mats Karrman [mailto:mats.dev.list@gmail.com]
> >> Sent: 2018???5???12??? 3:56
> >> To: Jun Li <jun.li@nxp.com>; robh+dt@kernel.org; gregkh@linuxfoundation.org;
> >> heikki.krogerus@linux.intel.com; linux@roeck-us.net
> >> Cc: a.hajda@samsung.com; cw00.choi@samsung.com;
> >> shufan_lee@richtek.com; Peter Chen <peter.chen@nxp.com>;
> >> gsomlo@gmail.com; devicetree@vger.kernel.org; linux-usb@vger.kernel.org;
> >> dl-linux-imx <linux-imx@nxp.com>
> >> Subject: Re: [PATCH v5 05/14] usb: typec: add API to get typec basic port power
> >> and data config
> >>
> >> Hi Li Jun,
> >>
> >> On 2018-05-03 02:24, Li Jun wrote:
> >>
> >>> This patch adds 3 APIs to get the typec port power and data type, and
> >>> preferred power role by its name string.
> >>>
> >>> Signed-off-by: Li Jun <jun.li@nxp.com>
> >>> ---
> >>> drivers/usb/typec/class.c | 52
> >> +++++++++++++++++++++++++++++++++++++++++++++++
> >>> include/linux/usb/typec.h | 3 +++
> >>> 2 files changed, 55 insertions(+)
> >>>
> >>> diff --git a/drivers/usb/typec/class.c b/drivers/usb/typec/class.c
> >>> index 53df10d..5981e18 100644
> >>> --- a/drivers/usb/typec/class.c
> >>> +++ b/drivers/usb/typec/class.c
> >>> @@ -9,6 +9,7 @@
> >>> #include <linux/device.h>
> >>> #include <linux/module.h>
> >>> #include <linux/mutex.h>
> >>> +#include <linux/property.h>
I don't think you need that anymore.
> >>> #include <linux/slab.h>
> >>> #include <linux/usb/typec.h>
> >>> #include <linux/usb/typec_mux.h>
> >>> @@ -802,6 +803,12 @@ static const char * const typec_port_types[] = {
> >>> [TYPEC_PORT_DRP] = "dual",
> >>> };
> >>>
> >>> +static const char * const typec_data_types[] = {
> >>> + [TYPEC_PORT_DFP] = "host",
> >>> + [TYPEC_PORT_UFP] = "device",
> >>> + [TYPEC_PORT_DRD] = "dual",
> >>> +};
> >>> +
> >>> static const char * const typec_port_types_drp[] = {
> >>> [TYPEC_PORT_SRC] = "dual [source] sink",
> >>> [TYPEC_PORT_SNK] = "dual source [sink]", @@ -1252,6 +1259,51
> >> @@
> >>> void typec_set_pwr_opmode(struct typec_port *port,
> >>> }
> >>> EXPORT_SYMBOL_GPL(typec_set_pwr_opmode);
> >>>
> >>> +/**
> >>> + * typec_find_power_type - Get the typec port power type
> >> Why is this function called typec_find_power_type() and not
> >> typec_find_port_type()?
> >> It's called port_type in sysfs, having different names just adds confusion.
> >> (Otherwise I agree power_type is a better name but...)
> > We have "port type" before the power and data role separation,
> > this API name's intention is to reflect the power cap, anyway I
> > leave this to be decided by Heikki then.
I really hate the "*_type" naming. It was understandable when there
was no separate power and data roles defined in the specification, but
now that there are, it's just confusing. IMO we should not use it
anywhere.
So to me typec_find_type() is just as bad as typec_find_power_type()
because it has the "type" in it. I wonder if this function is
necessary at all? If it is, then perhaps we can think of some better
name for it, name that gives a better hint what it is used for.
> >>> + * @name: port type string
> >>> + *
> >>> + * This routine is used to find the typec_port_type by its string name.
> >>> + *
> >>> + * Returns typec_port_type if success, otherwise negative error code.
> >>> + */
> >>> +int typec_find_power_type(const char *name) {
> >>> + return match_string(typec_port_types, ARRAY_SIZE(typec_port_types),
> >>> + name);
> >>> +}
> >>> +EXPORT_SYMBOL_GPL(typec_find_power_type);
> >>> +
> >>> +/**
> >>> + * typec_find_preferred_role - Find the typec drp port preferred
> >>> +power role
> >> Why typec_find_preferred_role()? Could be used for any power_role so why not
> >> typec_find_power_role()?
> > I am not sure if I catch your point of this comment.
> > For preferred role(if support try.sink or try.src) the only allowed power roles are
> > "sink"
> > "source"
> > But for power role, the allowed type are
> > "sink"
> > "source"
> > "dual"
>
> Uhm, typing too fast again, I am. A better name would be just typec_find_role().
> What I mean is that the function could be used for any situation when
> someone wants to map a string to a TYPEC_{SOURCE,SINK} constant so it
> is unnecessary to limit its usage to just preferred role.
That sounds reasonable to me.
Thanks,
--
heikki
^ permalink raw reply
* Re: [PATCH net-next v2 0/2] of: mdio: Fall back to mdiobus_register() with NULL device_node
From: Andrew Lunn @ 2018-05-16 12:27 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Florian Fainelli, netdev, Vivien Didelot, David S. Miller,
Nicolas Ferre, Fugang Duan, Sergei Shtylyov, Giuseppe Cavallaro,
Alexandre Torgue, Jose Abreu, Grygorii Strashko, Woojung Huh,
Microchip Linux Driver Support, Rob Herring, Frank Rowand,
Antoine Tenart, Tobias Jordan, Russell
In-Reply-To: <CAMuHMdXfOOgADe1my9Y3s3b9_OsXPjbqq1PPFR9izZWhtPuaFg@mail.gmail.com>
On Wed, May 16, 2018 at 10:54:12AM +0200, Geert Uytterhoeven wrote:
> Hi Florian,
>
> Thanks for your series!
> I like the effect on simplifying drivers.
>
> On Wed, May 16, 2018 at 1:56 AM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> > This patch series updates of_mdiobus_register() such that when the device_node
> > argument is NULL, it calls mdiobus_register() directly. This is consistent with
> > the behavior of of_mdiobus_register() when CONFIG_OF=n.
>
> IMHO the CONFIG_OF=n behavior of of_mdiobus_register() (which I wasn't
> aware of) is inconsistent with the behavior of other of_*() functions,
> which are just empty stubs.
>
> So I'm wondering if you should do it the other way around, and let
> mdiobus_register() call of_mdiobus_register() if dev->of_node exists?
Hi Geert
dev->of_node is often not the correct OF node. The mdio properties are
often embedded inside a MAC driver, and use an 'mdio' container
node. This container node is needed, not the device node.
> I haven't looked at the ACPI handling, but perhaps this can be moved
> inside mdiobus_register() as well?
The ACPI binding for MDIO and PHYs has not been defined yet.
Andrew
^ permalink raw reply
* [PATCH 0/3] input: touchscreen: edt-ft5x06: make wakeup source behavior configurable
From: Daniel Mack @ 2018-05-16 12:28 UTC (permalink / raw)
To: dmitry.torokhov, robh+dt, mark.rutland, shawnguo, kernel,
fabio.estevam
Cc: devicetree, Daniel Mack, linux-arm-kernel, linux-input
Hi,
I have a platform that features an edt-ft5x06 touch panel and that
doesn't want to wake on touch screen activity.
Here's a trivial series of patches that make the edt-ft5x06 driver only
act as wakeup source when requested through device properties or DTS.
The third patch changes the default in two DTS files that use this
driver.
I guess the first two patches should go through the input tree, while
the third can be picked by the IMX people. There are no compile-time
dependencies, so the order doesn't matter.
Thanks,
Daniel
Daniel Mack (3):
input: touchscreen: edt-ft5x06: make wakeup source behavior
configurable
input: touchscreen: edt-ft5x06: assert reset during suspend
ARM: dts: imx28/imx53: enable edt-ft5x06 wakeup source
.../devicetree/bindings/input/touchscreen/edt-ft5x06.txt | 3 +++
arch/arm/boot/dts/imx28-tx28.dts | 1 +
arch/arm/boot/dts/imx53-tx53-x03x.dts | 1 +
drivers/input/touchscreen/edt-ft5x06.c | 9 ++++++++-
4 files changed, 13 insertions(+), 1 deletion(-)
--
2.14.3
^ permalink raw reply
* [PATCH 1/3] input: touchscreen: edt-ft5x06: make wakeup source behavior configurable
From: Daniel Mack @ 2018-05-16 12:28 UTC (permalink / raw)
To: dmitry.torokhov, robh+dt, mark.rutland, shawnguo, kernel,
fabio.estevam
Cc: devicetree, Daniel Mack, linux-arm-kernel, linux-input
In-Reply-To: <20180516122829.23694-1-daniel@zonque.org>
Allow configuring the device as wakeup source through device properties, as
not all platforms want to wake up on touch screen activity.
Note that by default, the device will now no longer be a wakeup source.
Signed-off-by: Daniel Mack <daniel@zonque.org>
---
Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt | 3 +++
drivers/input/touchscreen/edt-ft5x06.c | 3 ++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
index 025cf8c9324a..83f792d4d88c 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
@@ -52,6 +52,8 @@ Optional properties:
- touchscreen-inverted-y : See touchscreen.txt
- touchscreen-swapped-x-y : See touchscreen.txt
+ - wakeup-source: touchscreen acts as wakeup source
+
Example:
polytouch: edt-ft5x06@38 {
compatible = "edt,edt-ft5406", "edt,edt-ft5x06";
@@ -62,4 +64,5 @@ Example:
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+ wakeup-source;
};
diff --git a/drivers/input/touchscreen/edt-ft5x06.c b/drivers/input/touchscreen/edt-ft5x06.c
index 5bf63f76ddda..955f085627fa 100644
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -1007,7 +1007,8 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client,
goto err_remove_attrs;
edt_ft5x06_ts_prepare_debugfs(tsdata, dev_driver_string(&client->dev));
- device_init_wakeup(&client->dev, 1);
+ device_init_wakeup(&client->dev,
+ device_property_read_bool(dev, "wakeup-source"));
dev_dbg(&client->dev,
"EDT FT5x06 initialized: IRQ %d, WAKE pin %d, Reset pin %d.\n",
--
2.14.3
^ permalink raw reply related
* [PATCH 2/3] input: touchscreen: edt-ft5x06: assert reset during suspend
From: Daniel Mack @ 2018-05-16 12:28 UTC (permalink / raw)
To: dmitry.torokhov, robh+dt, mark.rutland, shawnguo, kernel,
fabio.estevam
Cc: devicetree, Daniel Mack, linux-arm-kernel, linux-input
In-Reply-To: <20180516122829.23694-1-daniel@zonque.org>
If the device is not configured as wakeup source, it can be put in reset
during suspend to save some power.
Signed-off-by: Daniel Mack <daniel@zonque.org>
---
drivers/input/touchscreen/edt-ft5x06.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/input/touchscreen/edt-ft5x06.c b/drivers/input/touchscreen/edt-ft5x06.c
index 955f085627fa..c34a0b23f90a 100644
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -1036,9 +1036,12 @@ static int edt_ft5x06_ts_remove(struct i2c_client *client)
static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
+ struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
if (device_may_wakeup(dev))
enable_irq_wake(client->irq);
+ else if (tsdata->reset_gpio)
+ gpiod_set_value_cansleep(tsdata->reset_gpio, 1);
return 0;
}
@@ -1046,9 +1049,12 @@ static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
static int __maybe_unused edt_ft5x06_ts_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
+ struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
if (device_may_wakeup(dev))
disable_irq_wake(client->irq);
+ else if (tsdata->reset_gpio)
+ gpiod_set_value_cansleep(tsdata->reset_gpio, 0);
return 0;
}
--
2.14.3
^ permalink raw reply related
* [PATCH 3/3] ARM: dts: imx28/imx53: enable edt-ft5x06 wakeup source
From: Daniel Mack @ 2018-05-16 12:28 UTC (permalink / raw)
To: dmitry.torokhov, robh+dt, mark.rutland, shawnguo, kernel,
fabio.estevam
Cc: devicetree, Daniel Mack, linux-arm-kernel, linux-input
In-Reply-To: <20180516122829.23694-1-daniel@zonque.org>
The touchscreen driver no longer configures the device as wakeup source by
default. A "wakeup-source" property is needed.
To avoid regressions, this patch changes the DTS files for the only two
users of this driver that didn't have this property yet.
Signed-off-by: Daniel Mack <daniel@zonque.org>
---
arch/arm/boot/dts/imx28-tx28.dts | 1 +
arch/arm/boot/dts/imx53-tx53-x03x.dts | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index 0ebbc83852d0..094a39a67ec8 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -328,6 +328,7 @@
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+ wakeup-source;
};
touchscreen: tsc2007@48 {
diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/imx53-tx53-x03x.dts
index 0ecb43d88522..dbf0d73dc7b9 100644
--- a/arch/arm/boot/dts/imx53-tx53-x03x.dts
+++ b/arch/arm/boot/dts/imx53-tx53-x03x.dts
@@ -220,6 +220,7 @@
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+ wakeup-source;
};
touchscreen: tsc2007@48 {
--
2.14.3
^ permalink raw reply related
* Re: [PATCH v2] ARM: dts: imx6/7: Remove unit-address from anatop regulators
From: Fabio Estevam @ 2018-05-16 12:35 UTC (permalink / raw)
To: Shawn Guo
Cc: Fabio Estevam,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Rob Herring,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20180515074042.GP26863@dragon>
Hi Shawn,
On Tue, May 15, 2018 at 4:40 AM, Shawn Guo <shawnguo@kernel.org> wrote:
> I'm a bit confused. It looks that the change is just to revert commit
> 685e1321ba74 ("ARM: dts: imx6: Add unit address and reg for the anatop
> nodes"). But what about the simple_bus_reg warning the commit was
> fixing?
Yes, I don't get the original simple_bus_reg warning anymore.
I think we don't need the unit address and reg properties to the
anatop regulators.
There is already a 'anatop-reg-offset' property that indicates the
anatop register offset.
Rob, is this patch the correct solution to fix the duplicate
unit-address dtc warnings?
Thanks
^ permalink raw reply
* [PATCH V6 00/12] ARM: dts: ipq: updates to enable a few peripherals
From: Sricharan R @ 2018-05-16 12:49 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier, richardcochran, sricharan
All the patches have been tested on ipq4019 dk01, 04, 07 and ipq8074 hk01
boards for spi, bam, qup, qpic, spi-nor, serial, pci.
[V6]
* Fixed Bjorn's comments, added his acks that he gave, added Varada's acks
* Rebased on top of Andy's for-next branch.
[v5]
* Fixed a minor comment that i missed earlier.
* https://www.spinics.net/lists/arm-kernel/msg643071.html
[v4]
* Fixed more comments.
* Dropped reserved-memory nodes from board files as
that might break existing users whose u-boot do not
specify the fdt_high accordingly.
* Added chosen serial node for all boards to have
the default serial console specified from DT.
[v3]
* Fixed minor comments from v2,
https://www.spinics.net/lists/arm-kernel/msg641480.html
* Added Abhishek's review tags
[v2]
* Addressed all comments from Abhishek
* Removed dk01-c2 and dk04-c5 spinand based boards
as support for spinand is not complete
* Based all patches on top of Andy's for-next branch
[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html
Sricharan R (12):
ARM: dts: ipq4019: Add a default chosen node
ARM: dts: ipq4019: Add a few peripheral nodes
ARM: dts: ipq4019: Change the max opp frequency
ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
ARM: dts: ipq8074: Add peripheral nodes
ARM: dts: ipq8074: Add pcie nodes
ARM: dts: ipq8074: Enable few peripherals for hk01 board
arch/arm/boot/dts/Makefile | 4 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 10 +-
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 19 ++
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 9 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 111 +++++++++
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 64 +++++
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 25 ++
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 75 ++++++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 162 ++++++++++--
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 62 ++++-
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 313 +++++++++++++++++++++++-
11 files changed, 827 insertions(+), 27 deletions(-)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* [PATCH V6 01/12] ARM: dts: ipq4019: Add a default chosen node
From: Sricharan R @ 2018-05-16 12:49 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier, richardcochran, sricharan
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
Add a 'chosen' node to select the serial console.
This is needed when bootloaders do not pass the
'console=' bootargs.
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 8 ++++++++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index e413b21e..ef8d8c8 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,6 +20,14 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
+ aliases {
+ serial0 = &blsp1_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
soc {
rng@22000 {
status = "ok";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 10d112a..ea9202a 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -256,7 +256,7 @@
regulator;
};
- serial@78af000 {
+ blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
interrupts = <0 107 0>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 02/12] ARM: dts: ipq4019: Add a few peripheral nodes
From: Sricharan R @ 2018-05-16 12:49 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier, richardcochran, sricharan
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +-
arch/arm/boot/dts/qcom-ipq4019.dtsi | 156 ++++++++++++++++++++++++--
2 files changed, 146 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index ef8d8c8..418f9a0 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -69,7 +69,7 @@
status = "ok";
};
- spi_0: spi@78b5000 {
+ spi@78b5000 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "ok";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index ea9202a..1541e18 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -24,8 +24,10 @@
interrupt-parent = <&intc>;
aliases {
- spi0 = &spi_0;
- i2c0 = &i2c_0;
+ spi0 = &blsp1_spi1;
+ spi1 = &blsp1_spi2;
+ i2c0 = &blsp1_i2c3;
+ i2c1 = &blsp1_i2c4;
};
cpus {
@@ -104,6 +106,12 @@
};
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq4019";
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
@@ -149,13 +157,13 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- interrupts = <0 208 0>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
};
blsp_dma: dma@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x23000>;
- interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -163,7 +171,7 @@
status = "disabled";
};
- spi_0: spi@78b5000 {
+ blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
@@ -172,10 +180,26 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&blsp_dma 5>, <&blsp_dma 4>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x78b6000 0x600>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&blsp_dma 7>, <&blsp_dma 6>;
+ dma-names = "rx", "tx";
status = "disabled";
};
- i2c_0: i2c@78b7000 {
+ blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
@@ -184,14 +208,29 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&blsp_dma 9>, <&blsp_dma 8>;
+ dma-names = "rx", "tx";
status = "disabled";
};
+ blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x78b8000 0x600>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&blsp_dma 11>, <&blsp_dma 10>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
cryptobam: dma@8e04000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x08e04000 0x20000>;
- interrupts = <GIC_SPI 207 0>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -259,7 +298,7 @@
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
- interrupts = <0 107 0>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
@@ -271,7 +310,7 @@
serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b0000 0x200>;
- interrupts = <0 108 0>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
@@ -293,6 +332,101 @@
reg = <0x4ab000 0x4>;
};
+ pcie0: pci@40000000 {
+ compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
+ reg = <0x40000000 0xf1d
+ 0x40000f20 0xa8
+ 0x80000 0x2000
+ 0x40100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
+ 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ clocks = <&gcc GCC_PCIE_AHB_CLK>,
+ <&gcc GCC_PCIE_AXI_M_CLK>,
+ <&gcc GCC_PCIE_AXI_S_CLK>;
+ clock-names = "aux",
+ "master_bus",
+ "slave_bus";
+
+ resets = <&gcc PCIE_AXI_M_ARES>,
+ <&gcc PCIE_AXI_S_ARES>,
+ <&gcc PCIE_PIPE_ARES>,
+ <&gcc PCIE_AXI_M_VMIDMT_ARES>,
+ <&gcc PCIE_AXI_S_XPU_ARES>,
+ <&gcc PCIE_PARF_XPU_ARES>,
+ <&gcc PCIE_PHY_ARES>,
+ <&gcc PCIE_AXI_M_STICKY_ARES>,
+ <&gcc PCIE_PIPE_STICKY_ARES>,
+ <&gcc PCIE_PWR_ARES>,
+ <&gcc PCIE_AHB_ARES>,
+ <&gcc PCIE_PHY_AHB_ARES>;
+ reset-names = "axi_m",
+ "axi_s",
+ "pipe",
+ "axi_m_vmid",
+ "axi_s_xpu",
+ "parf",
+ "phy",
+ "axi_m_sticky",
+ "pipe_sticky",
+ "pwr",
+ "ahb",
+ "phy_ahb";
+
+ status = "disabled";
+ };
+
+ qpic_bam: dma@7984000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x7984000 0x1a000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QPIC_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ status = "disabled";
+ };
+
+ nand: qpic-nand@79b0000 {
+ compatible = "qcom,ipq4019-nand";
+ reg = <0x79b0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpic_bam 0>,
+ <&qpic_bam 1>,
+ <&qpic_bam 2>;
+ dma-names = "tx", "rx", "cmd";
+ status = "disabled";
+
+ nand@0 {
+ reg = <0>;
+
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+ };
+ };
+
wifi0: wifi@a000000 {
compatible = "qcom,ipq4019-wifi";
reg = <0xa000000 0x200000>;
@@ -326,7 +460,7 @@
<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 168 IRQ_TYPE_NONE>;
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
@@ -368,7 +502,7 @@
<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 169 IRQ_TYPE_NONE>;
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 03/12] ARM: dts: ipq4019: Change the max opp frequency
From: Sricharan R @ 2018-05-16 12:49 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier, richardcochran, sricharan
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
The max opp frequency is 716MHZ. So update that.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 1541e18..2c4ad7d 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -47,7 +47,7 @@
48000 1100000
200000 1100000
500000 1100000
- 666000 1100000
+ 716000 1100000
>;
clock-latency = <256000>;
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 04/12] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
From: Sricharan R @ 2018-05-16 12:49 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier, richardcochran, sricharan
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
Add the common parts for the dk04 boards.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 111 ++++++++++++++++++++++++++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
2 files changed, 112 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
new file mode 100644
index 0000000..7c1eb19
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
+
+ aliases {
+ serial0 = &blsp1_uart1;
+ serial1 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256MB */
+ };
+
+ soc {
+ pinctrl@1000000 {
+ serial_0_pins: serial0-pinmux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+
+ serial_1_pins: serial1-pinmux {
+ pins = "gpio8", "gpio9",
+ "gpio10", "gpio11";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+
+ spi_0_pins: spi-0-pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ bias-disable;
+ };
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
+ bias-disable;
+ output-high;
+ };
+ };
+
+ i2c_0_pins: i2c-0-pinmux {
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ bias-disable;
+ };
+
+ nand_pins: nand-pins {
+ pins = "gpio53", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59",
+ "gpio60", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68", "gpio69";
+ function = "qpic";
+ };
+ };
+
+ serial@78af000 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ serial@78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ dma@7884000 {
+ status = "ok";
+ };
+
+ spi@78b5000 { /* BLSP1 QUP1 */
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ cs-gpios = <&tlmm 12 0>;
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "n25q128a11";
+ spi-max-frequency = <24000000>;
+ };
+ };
+
+ pci@40000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 38 0x1>;
+ };
+
+ qpic-nand@79b0000 {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 2c4ad7d..815c912 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -307,7 +307,7 @@
dma-names = "rx", "tx";
};
- serial@78b0000 {
+ blsp1_uart2: serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b0000 0x200>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 05/12] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
From: Sricharan R @ 2018-05-16 12:49 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier, richardcochran, sricharan
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Tested-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7e24249..4e15d0d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -760,6 +760,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
new file mode 100644
index 0000000..7a96f30
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
+ compatible = "qcom,ipq4019-dk04.1-c1";
+
+ soc {
+ dma@7984000 {
+ status = "ok";
+ };
+
+ qpic-nand@79b0000 {
+ status = "ok";
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 06/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
From: Sricharan R @ 2018-05-16 12:49 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier, richardcochran, sricharan
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 9 +++++++++
2 files changed, 10 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4e15d0d..c6cabec 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -761,6 +761,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
new file mode 100644
index 0000000..2d1c4c6
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
+ compatible = "qcom,ipq4019-ap-dk04.1-c3";
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
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