* Re: [PATCH v2 10/11] arm64: dts: r8a77965-salvator-x: Enable DU external clocks and HDMI
From: Kuninori Morimoto @ 2018-05-29 1:44 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Kieran Bingham, Linux-Renesas, Laurent Pinchart, DRI Development,
Simon Horman, Magnus Damm, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM64 PORT (AARCH64 ARCHITECTURE), open list
In-Reply-To: <CAMuHMdW6HeWMwRDcn6PLnwzgxvYz-h=jx=1qvYEK9okwqY0itg@mail.gmail.com>
Hi Geert
> > +&hdmi0_con {
> > + remote-endpoint = <&rcar_dw_hdmi0_out>;
> > +};
>
> I think the hdmi0 and hdmi0_con parts can be moved to salvator-common.dtsi.
> Can we do that now (with stubs?), or does this have to wait until r8a77965 has
> received HDMI sound support?
HDMI sound doesn't use hdmi0_con.
You can do it now, thanks
Best regards
---
Kuninori Morimoto
^ permalink raw reply
* RE: [PATCH v5] usb: gadget: udc: renesas_usb3: Add register of usb role switch
From: Yoshihiro Shimoda @ 2018-05-29 2:51 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Greg Kroah-Hartman, Rob Herring, Mark Rutland, Krogerus, Heikki,
Hans de Goede, USB, Linux-Renesas, devicetree
In-Reply-To: <CAHp75VcFNkrBXXgCB+pQJHGvHquik7OMD+W=eZn4Gj9b14799w@mail.gmail.com>
Hi Andy,
Thank you for your review!
> From: Andy Shevchenko, Sent: Monday, May 28, 2018 9:47 PM
>
> On Fri, May 25, 2018 at 10:12 AM, Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
>
> > -static void usb3_set_mode(struct renesas_usb3 *usb3, bool host)
>
> Wouldn't be better to choose another name for a new function?
I got it. I'll choose another name for a new function as "usb3_set_mode_by_role_sw".
> > + struct renesas_usb3 *usb3 = container_of(work, struct renesas_usb3,
> > + role_work);
>
> Matter of style, though I would rather put entire container_of() on
> the next line (see for the existing style in the module and use it).
I got it. I'll modify that.
> > + /* This device_attach() might sleep */
> > + if (device_attach(host) < 0)
> > + dev_err(dev, "device_attach(usb3_port) failed\n");
>
> can't be "usb3_port" part derived from the host variable somehow and
> to some extend?
Oops. I should describe "host" instead of "usb3_port".
> > + usb3->role_sw = usb_role_switch_register(&pdev->dev,
> > + &renesas_usb3_role_switch_desc);
> > + if (!IS_ERR(usb3->role_sw)) {
>
> > + usb3->host_dev = usb_of_get_companion_dev(&pdev->dev);
>
> Hmm... Can it possible return -EPROBE_DEFER? If so, would it be better
> to use other approach to handle it?
Does this "it" mean " usb_of_get_companion_dev()"? If so, it is not possible
to return -EPROBE_DEFER.
Or, " usb_role_switch_register()"? Also this function is not possible to
return -EPROBE_DEFER, IIUC.
> > + if (IS_ERR_OR_NULL(usb3->host_dev)) {
So, I can just use "if (!usb3->host_dev) {" instead of above.
Best regards,
Yoshihiro Shimoda
> > + /* If not found, this driver will not use a role sw */
> > + usb_role_switch_unregister(usb3->role_sw);
> > + usb3->role_sw = NULL;
> > + }
> > + } else {
> > + usb3->role_sw = NULL;
> > + }
>
>
> --
> With Best Regards,
> Andy Shevchenko
^ permalink raw reply
* RE: [PATCH v5] usb: gadget: udc: renesas_usb3: Add register of usb role switch
From: Yoshihiro Shimoda @ 2018-05-29 2:52 UTC (permalink / raw)
To: Heikki Krogerus
Cc: gregkh@linuxfoundation.org, robh+dt@kernel.org,
mark.rutland@arm.com, hdegoede@redhat.com,
andy.shevchenko@gmail.com, linux-usb@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org
In-Reply-To: <20180528130439.GD29600@kuha.fi.intel.com>
Hi Heikki,
> From: Heikki Krogerus, Sent: Monday, May 28, 2018 10:05 PM
>
> On Fri, May 25, 2018 at 04:12:56PM +0900, Yoshihiro Shimoda wrote:
> > @@ -2573,6 +2635,12 @@ static void renesas_usb3_init_ram(struct renesas_usb3 *usb3, struct device *dev,
> > EXTCON_NONE,
> > };
> >
> > +static struct usb_role_switch_desc renesas_usb3_role_switch_desc = {
>
> You can constify that.
Thank you for the review! I'll modify this in v6 patch.
Best regards,
Yoshihiro Shimoda
> > + .set = renesas_usb3_role_switch_set,
> > + .get = renesas_usb3_role_switch_get,
> > + .allow_userspace_control = true,
> > +};
> > +
> > static int renesas_usb3_probe(struct platform_device *pdev)
> > {
> > struct renesas_usb3 *usb3;
>
> Thanks,
>
> --
> heikki
^ permalink raw reply
* Re: [PATCH 1/5] ptp: rework gianfar_ptp as QorIQ common PTP driver
From: David Miller @ 2018-05-29 3:05 UTC (permalink / raw)
To: yangbo.lu
Cc: netdev, devicetree, linux-kernel, richardcochran, claudiu.manoil,
robh+dt
In-Reply-To: <20180525044038.37756-1-yangbo.lu@nxp.com>
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Fri, 25 May 2018 12:40:34 +0800
> gianfar_ptp was the PTP clock driver for 1588 timer
> module of Freescale QorIQ eTSEC (Enhanced Three-Speed
> Ethernet Controllers) platforms. Actually QorIQ DPAA
> (Data Path Acceleration Architecture) platforms is
> also using the same 1588 timer module in hardware.
>
> This patch is to rework gianfar_ptp as QorIQ common
> PTP driver to support both DPAA and eTSEC. Moved
> gianfar_ptp.c to drivers/ptp/, renamed it as
> ptp_qoriq.c, and renamed many variables. There were
> not any function changes.
>
> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Applied.
^ permalink raw reply
* Re: [PATCH 2/5] ptp_qoriq: move some definitions to header file
From: David Miller @ 2018-05-29 3:05 UTC (permalink / raw)
To: yangbo.lu
Cc: netdev, devicetree, linux-kernel, richardcochran, claudiu.manoil,
robh+dt
In-Reply-To: <20180525044038.37756-2-yangbo.lu@nxp.com>
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Fri, 25 May 2018 12:40:35 +0800
> This patch is to move some definitions in ptp_qoriq.c
> to the header file.
>
> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Applied.
^ permalink raw reply
* Re: [PATCH 3/5] net: ethernet: gianfar_ethtool: get phc index through drvdata
From: David Miller @ 2018-05-29 3:06 UTC (permalink / raw)
To: yangbo.lu
Cc: netdev, devicetree, linux-kernel, richardcochran, claudiu.manoil,
robh+dt
In-Reply-To: <20180525044038.37756-3-yangbo.lu@nxp.com>
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Fri, 25 May 2018 12:40:36 +0800
> Global variable gfar_phc_index was used to get and store
> phc index through gianfar_ptp driver. However gianfar_ptp
> had been renamed as ptp_qoriq for QorIQ common PTP driver.
> This gfar_phc_index doesn't work any more, and the phc index
> is stored in drvdata now. This patch is to support getting
> phc index through ptp_qoriq drvdata.
>
> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Applied.
^ permalink raw reply
* Re: [PATCH 4/5] dt-bindings: ptp: add ptp-qoriq.txt
From: David Miller @ 2018-05-29 3:06 UTC (permalink / raw)
To: yangbo.lu
Cc: netdev, devicetree, linux-kernel, richardcochran, claudiu.manoil,
robh+dt
In-Reply-To: <20180525044038.37756-4-yangbo.lu@nxp.com>
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Fri, 25 May 2018 12:40:37 +0800
> This patch is to add a documentation for ptp_qoriq dt-bindings.
> The description for ptp_qoriq dt-bindings was actually moved
> from Documentation/devicetree/bindings/net/fsl-tsec-phy.txt,
> since gianfar_ptp driver was moved to ptp_qoriq driver.
>
> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Applied.
^ permalink raw reply
* Re: [PATCH 5/5] MAINTAINERS: add myself as maintainer for QorIQ PTP clock driver
From: David Miller @ 2018-05-29 3:06 UTC (permalink / raw)
To: yangbo.lu
Cc: netdev, devicetree, linux-kernel, richardcochran, claudiu.manoil,
robh+dt
In-Reply-To: <20180525044038.37756-5-yangbo.lu@nxp.com>
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Fri, 25 May 2018 12:40:38 +0800
> Added myself as maintainer for QorIQ PTP clock driver.
> Since gianfar_ptp.c was renamed to ptp_qoriq.c, let's
> also maintain it under QorIQ PTP clock driver.
>
> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Because of the dependency on the staging tree changes, this
doesn't apply cleanly to net-next.
You'll have to figure out how you want to sort this out.
^ permalink raw reply
* [v2] MAINTAINERS: add myself as maintainer for QorIQ PTP clock driver
From: Yangbo Lu @ 2018-05-29 3:47 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel, Richard Cochran, claudiu.manoil,
Rob Herring
Cc: Yangbo Lu
Added myself as maintainer for QorIQ PTP clock driver.
Since gianfar_ptp.c was renamed to ptp_qoriq.c, let's
maintain it under QorIQ PTP clock driver.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
Changes for v2:
- Dropped dpaa2/rtc part.
---
MAINTAINERS | 10 ++++++++--
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index f492431..c16340c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5620,7 +5620,6 @@ M: Claudiu Manoil <claudiu.manoil@nxp.com>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ethernet/freescale/gianfar*
-X: drivers/net/ethernet/freescale/gianfar_ptp.c
F: Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
FREESCALE GPMI NAND DRIVER
@@ -5667,6 +5666,14 @@ S: Maintained
F: drivers/net/ethernet/freescale/fman
F: Documentation/devicetree/bindings/powerpc/fsl/fman.txt
+FREESCALE QORIQ PTP CLOCK DRIVER
+M: Yangbo Lu <yangbo.lu@nxp.com>
+L: netdev@vger.kernel.org
+S: Maintained
+F: drivers/ptp/ptp_qoriq.c
+F: include/linux/fsl/ptp_qoriq.h
+F: Documentation/devicetree/bindings/ptp/ptp-qoriq.txt
+
FREESCALE QUAD SPI DRIVER
M: Han Xu <han.xu@nxp.com>
L: linux-mtd@lists.infradead.org
@@ -11405,7 +11412,6 @@ S: Maintained
W: http://linuxptp.sourceforge.net/
F: Documentation/ABI/testing/sysfs-ptp
F: Documentation/ptp/*
-F: drivers/net/ethernet/freescale/gianfar_ptp.c
F: drivers/net/phy/dp83640*
F: drivers/ptp/*
F: include/linux/ptp_cl*
--
1.7.1
^ permalink raw reply related
* RE: [PATCH 5/5] MAINTAINERS: add myself as maintainer for QorIQ PTP clock driver
From: Y.b. Lu @ 2018-05-29 3:57 UTC (permalink / raw)
To: David Miller
Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, richardcochran@gmail.com,
Claudiu Manoil, robh+dt@kernel.org
In-Reply-To: <20180528.230631.1400838711386498433.davem@davemloft.net>
Hi David,
> -----Original Message-----
> From: David Miller [mailto:davem@davemloft.net]
> Sent: Tuesday, May 29, 2018 11:07 AM
> To: Y.b. Lu <yangbo.lu@nxp.com>
> Cc: netdev@vger.kernel.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; richardcochran@gmail.com; Claudiu Manoil
> <claudiu.manoil@nxp.com>; robh+dt@kernel.org
> Subject: Re: [PATCH 5/5] MAINTAINERS: add myself as maintainer for QorIQ
> PTP clock driver
>
> From: Yangbo Lu <yangbo.lu@nxp.com>
> Date: Fri, 25 May 2018 12:40:38 +0800
>
> > Added myself as maintainer for QorIQ PTP clock driver.
> > Since gianfar_ptp.c was renamed to ptp_qoriq.c, let's also maintain it
> > under QorIQ PTP clock driver.
> >
> > Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
>
> Because of the dependency on the staging tree changes, this doesn't apply
> cleanly to net-next.
>
> You'll have to figure out how you want to sort this out.
[Y.b. Lu] I sent out a v2 MAINTAINERS patch. I think it also makes sense to drop dpaa2 rtc drivers in the entry.
Thanks a lot.
^ permalink raw reply
* Re: [PATCH 1/3] ASoC: simple-card: set cpu dai clk in hw_params
From: Daniel Mack @ 2018-05-29 4:26 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: devicetree, alsa-devel, broonie, lgirdwood
In-Reply-To: <874lir5jox.wl%kuninori.morimoto.gx@renesas.com>
On Tuesday, May 29, 2018 03:38 AM, Kuninori Morimoto wrote:
>> The simple-card driver currently accepts a clock node in the cpu dai
>> sub-node and only uses it as an alternative to the
>> 'system-clock-frequency' property to get the current frequency.
>>
>> This patch adds another use of the passed clock node. If mclk-fs is
>> specified, the clock will be set to the calculated rate (stream rate *
>> mclk_fs) in hw_params. This allows platforms to pass a tuneable clock
>> as phandle that will automatically be set to the right rates.
>>
>> Signed-off-by: Daniel Mack <daniel@zonque.org>
>> ---
> (snip)
>> if (mclk_fs) {
>> mclk = params_rate(params) * mclk_fs;
>> +
>> + if (dai_props->cpu_dai.clk)
>> + clk_set_rate(dai_props->cpu_dai.clk, mclk);
>> +
>> ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
>> SND_SOC_CLOCK_IN);
>> if (ret && ret != -ENOTSUPP)
>
> Having codec is nice balance ?
Ah, yes, why not. Will post a v2.
Thanks,
Daniel
^ permalink raw reply
* Re: [PATCH 2/3] ASoC: simple-card: make sysclk index configurable
From: Daniel Mack @ 2018-05-29 4:34 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: devicetree, alsa-devel, broonie, lgirdwood
In-Reply-To: <8760375jsj.wl%kuninori.morimoto.gx@renesas.com>
On Tuesday, May 29, 2018 03:35 AM, Kuninori Morimoto wrote:
>> The simple-card driver currently hard-codes the clk_id parameter in
>> snd_soc_dai_set_sysclk() to 0. Make this configrable for both CPU and
>> codec dai sub-nodes.
>>
>> This still has the limitation that only one clk_id can be configured, but it
>> should help some more platforms to use simple-card in favor to a more
>> specific machine driver.
>>
>> Signed-off-by: Daniel Mack <daniel@zonque.org>
>> ---
>> Documentation/devicetree/bindings/sound/simple-card.txt | 3 +++
>> include/sound/simple_card_utils.h | 1 +
>> sound/soc/generic/simple-card-utils.c | 3 +++
>> sound/soc/generic/simple-card.c | 10 ++++++----
>> 4 files changed, 13 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/sound/simple-card.txt b/Documentation/devicetree/bindings/sound/simple-card.txt
>> index a4c72d09cd45..c8d268285a9e 100644
>> --- a/Documentation/devicetree/bindings/sound/simple-card.txt
>> +++ b/Documentation/devicetree/bindings/sound/simple-card.txt
>> @@ -94,6 +94,9 @@ Optional CPU/CODEC subnodes properties:
>> - system-clock-direction-out : specifies clock direction as 'out' on
>> initialization. It is useful for some aCPUs with
>> fixed clocks.
>> +- system-clock-index : index of the system clock to use when
>> + the mclk frequency is on the CPU/CODEC
>> + DAI. Defaults to 0.
>
> I'm not a DT guy, but I think DT doesn't want to have index directly ?
> I don't know detail, but I guess DT want to have like
>
> system-mclock = <&xxxx 3>
Hmm, no. That index doesn't describe a particular output of a clock
phandle but an internal detail of the CPU or CODEC DAI on the other end.
Most DAIs will use 0 here, like your code had it before.
The DAI can be both a producer and a consumer of a clock, depending on
the audio clocking setup, and these details are not exposed in DT.
Thanks,
Daniel
^ permalink raw reply
* Re: [PATCH] remoteproc: Add APSS based Qualcomm ADSP PIL driver for SDM845
From: Bjorn Andersson @ 2018-05-29 4:36 UTC (permalink / raw)
To: Rohit Kumar
Cc: ohad, robh+dt, mark.rutland, linux-remoteproc, devicetree,
linux-kernel, bgoswami, sbpata, asishb, rkarra,
RajendraBabu Medisetti, Krishnamurthy Renu, asishb, Ramlal Karra,
Rohit Kumar
In-Reply-To: <767dc01f-abed-8192-0274-ff5fc092f60b@codeaurora.org>
On Wed 23 May 22:18 PDT 2018, Rohit Kumar wrote:
> Thanks Bjorn for reviewing.
>
>
> On 5/23/2018 11:56 AM, Bjorn Andersson wrote:
> > On Sun 13 May 00:01 PDT 2018, Rohit kumar wrote:
> >
> > > --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> > > +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> > > @@ -10,6 +10,7 @@ on the Qualcomm ADSP Hexagon core.
> > > "qcom,msm8974-adsp-pil"
> > > "qcom,msm8996-adsp-pil"
> > > "qcom,msm8996-slpi-pil"
> > > + "qcom,sdm845-apss-adsp-pil"
> > Afaict there's nothing in this binding that ties this to the apss, so I
> > don't think we should base the compatible on this. The differentiation
> > is PAS vs non-PAS; so let's start naming the PAS variants
> > "qcom,platform-subsystem-pas" and the non-PAS
> > "qcom,platform-subsystem-pil" instead.
> >
> > I.e. please make this "qcom,sdm845-adsp-pil".
> >
> > More importantly, any resources such as clocks or reset lines should
> > come from DT and as such you need to extend the binding quite a bit -
> > which I suggest you do by introducing a new binding document.
> Sure. Will create new dt-binding document with clocks and reset driver info
> added for sdm845 PIL.
>
> > > - interrupts-extended:
> > > Usage: required
> > > diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
> > > index 02627ed..759831b 100644
> > > --- a/drivers/remoteproc/Makefile
> > > +++ b/drivers/remoteproc/Makefile
> > > @@ -14,7 +14,8 @@ obj-$(CONFIG_OMAP_REMOTEPROC) += omap_remoteproc.o
> > > obj-$(CONFIG_WKUP_M3_RPROC) += wkup_m3_rproc.o
> > > obj-$(CONFIG_DA8XX_REMOTEPROC) += da8xx_remoteproc.o
> > > obj-$(CONFIG_KEYSTONE_REMOTEPROC) += keystone_remoteproc.o
> > > -obj-$(CONFIG_QCOM_ADSP_PIL) += qcom_adsp_pil.o
> > > +obj-$(CONFIG_QCOM_ADSP_PIL) += qcom_adsp.o
> > > +qcom_adsp-objs += qcom_adsp_pil.o qcom_adsp_pil_sdm845.o
> > > obj-$(CONFIG_QCOM_RPROC_COMMON) += qcom_common.o
> > > obj-$(CONFIG_QCOM_Q6V5_PIL) += qcom_q6v5_pil.o
> > > obj-$(CONFIG_QCOM_SYSMON) += qcom_sysmon.o
> > > diff --git a/drivers/remoteproc/qcom_adsp_pil.c b/drivers/remoteproc/qcom_adsp_pil.c
> > I get the feeling that the main reason for modifying this file is its
> > name, not that it reduces the complexity of the final solution. I
> > definitely think it's cleaner to have some structural duplication and
> > keep this driver handling the various PAS based remoteprocs.
> The main intention was to re-use exisiting APIs in PAS based PIL
> driver as the major change was w.r.t. start and stop of ADSP firmware.
> Load(), interrupt handling and few other APIs will be same as done in
> exisiting PAS based PIL driver.
A very good intention, I just think it's good to keep the PAS driver
only dealing with PAS targets and work on reducing the duplication in
other ways; keeping the logic as simple as possible.
> > Please see the RFC series I posted reducing the duplication between the
> > various "Q6V5 drivers".
> I went through the RFC. Our code will fit into the design. However, we
> will still have some amount of code duplication between PAS and
> Non-PAS ADSP PIL driver. Will this be fine?
I'm sorry for not finding the time to provide you this feedback earlier.
> Please suggest.
> Will wait for your response whether to write complete new driver or reuse
> exisitng one.
>
For the Hexagon based non-PAS WCSS remoteproc in IPQ8074 we're creating
a new driver [1], in doing so I extracted some common helper functions
that reduces the duplication between the drivers and there are a few
more things on the way (e.g. reduce the code needed to deal with
memory-regions).
Please have a look at either extending this (non-PAS, non-MSA) driver to
cover the ADSP as well. It's hard for me to see how the exact details
will look after extracting the clocks and resets to their appropriate
drivers, if it doesn't fit the details we should work further on making
sure frameworks and helper functions reduces the logical duplication
between drivers.
[1] https://patchwork.kernel.org/patch/10420185/
> > [..]
> > > diff --git a/drivers/remoteproc/qcom_adsp_pil.h b/drivers/remoteproc/qcom_adsp_pil.h
> > [..]
> > > +static inline void update_bits(void *reg, u32 mask_val, u32 set_val, u32 shift)
> > > +{
> > > + u32 reg_val = 0;
> > > +
> > > + reg_val = ((readl(reg)) & ~mask_val) | ((set_val << shift) & mask_val);
> > > + writel(reg_val, reg);
> > > +}
> > > +
> > > +static inline unsigned int read_bit(void *reg, u32 mask, int shift)
> > > +{
> > > + return ((readl(reg) & mask) >> shift);
> > > +}
> > I don't like these helper functions, their prototype is nonstandard and
> > makes it really hard to read all the calling code.
> >
> > I would prefer if you just inline the operations directly, to make it
> > clearer what's going on in each case - if not then at least follow the
> > prototype of e.g. regmap_udpate_bits(), which people might be used to.
> Sure. Will update these APIs to follow standard format used in regmap and
> other drivers.
I like Rob's argument here (just use readl/writel) and it does suit our
current style.
[..]
> Thanks,
> Rohit
>
Thank you Rohit,
Bjorn
^ permalink raw reply
* [PATCH v6 0/3] Support for Qualcomm UFS QMP PHY on SDM845
From: Can Guo @ 2018-05-29 4:37 UTC (permalink / raw)
To: subhashj, asutoshd, vivek.gautam, mgautam, kishon, robh+dt,
mark.rutland
Cc: linux-kernel, devicetree, Can Guo
This patch series adds support for UFS QMP PHY on SDM845 and the
compatible string for it. This patch series depends on the current
proposed QMP V3 USB3 UNI PHY support for sdm845 driver [1], on
the DT bindings for the QMP V3 USB3 PHYs based dirver [2], and also
rebased on updated pipe_clk initialization sequence [3]. This series
can only be merged once the dependent patches do.
[1] http://lists-archives.com/linux-kernel/29071659-dt-bindings-phy-qcom-qmp-update-bindings-for-sdm845.html
[2] http://lists-archives.com/linux-kernel/29071660-phy-qcom-qmp-add-qmp-v3-usb3-uni-phy-support-for-sdm845.html
[3] https://patchwork.kernel.org/patch/10376551/
Changes since v5:
- Updates the PHY power control sequence.
- Updates UFS PHY power on condition check.
Changes since v4:
- Adds 'ref_aux' clock back to SDM845 UFS PHY clock list.
- Power on PHY before serdes configuration starts.
- Updates the UFS PHY initialization sequence.
- Updates a few UFS PHY registers.
- Incorporated review comments from Vivek and Manu.
Changes since v3:
- Incorporated review comments from Vivek and Rob.
Changes since v2:
- Incorporated review comments from Vivek and Rob.
- Remove "ref_aux" from sdm845 ufs phy clock list structure.
Changes since v1:
- Incorporated review comments from Vivek and Manu.
- Update the commit title of patch 2.
Can Guo (3):
phy: Update PHY power control sequence
phy: Add QMP phy based UFS phy support for sdm845
dt-bindings: phy-qcom-qmp: Add UFS phy compatible string for sdm845
.../devicetree/bindings/phy/qcom-qmp-phy.txt | 4 +-
drivers/phy/qualcomm/phy-qcom-qmp.c | 205 +++++++++++++++++++--
drivers/phy/qualcomm/phy-qcom-qmp.h | 15 ++
3 files changed, 210 insertions(+), 14 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v6 1/3] phy: Update PHY power control sequence
From: Can Guo @ 2018-05-29 4:37 UTC (permalink / raw)
To: subhashj, asutoshd, vivek.gautam, mgautam, kishon, robh+dt,
mark.rutland
Cc: linux-kernel, devicetree, Can Guo
In-Reply-To: <20180529043751.10580-1-cang@codeaurora.org>
All PHYs should be powered on before register configuration starts. And
only PCIe PHYs need an extra power control before deasserts reset state.
Signed-off-by: Can Guo <cang@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 97ef942..f779b0f 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -982,6 +982,8 @@ static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp)
if (cfg->has_phy_com_ctrl)
qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
SW_PWRDN);
+ else
+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
if (cfg->has_phy_dp_com_ctrl) {
qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
@@ -1127,7 +1129,8 @@ static int qcom_qmp_phy_init(struct phy *phy)
* Pull out PHY from POWER DOWN state.
* This is active low enable signal to power-down PHY.
*/
- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
+ if (cfg->type == PHY_TYPE_PCIE)
+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
if (cfg->has_pwrdn_delay)
usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v6 2/3] phy: Add QMP phy based UFS phy support for sdm845
From: Can Guo @ 2018-05-29 4:37 UTC (permalink / raw)
To: subhashj, asutoshd, vivek.gautam, mgautam, kishon, robh+dt,
mark.rutland
Cc: linux-kernel, devicetree, Can Guo
In-Reply-To: <20180529043751.10580-1-cang@codeaurora.org>
Add UFS PHY support to make SDM845 UFS work with common PHY framework.
Signed-off-by: Can Guo <cang@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 200 +++++++++++++++++++++++++++++++++---
drivers/phy/qualcomm/phy-qcom-qmp.h | 15 +++
2 files changed, 203 insertions(+), 12 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index f779b0f..ee74dcd 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -156,6 +156,11 @@ enum qphy_reg_layout {
[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
};
+static const unsigned int sdm845_ufsphy_regs_layout[] = {
+ [QPHY_START_CTRL] = 0x00,
+ [QPHY_PCS_READY_STATUS] = 0x160,
+};
+
static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
@@ -601,6 +606,83 @@ enum qphy_reg_layout {
QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
};
+static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
+
+ /* Rate B */
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
+};
+
+static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
+};
+
+static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
+};
+
+static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
+};
/* struct qmp_phy_cfg - per-PHY initialization config */
struct qmp_phy_cfg {
@@ -649,9 +731,14 @@ struct qmp_phy_cfg {
/* true, if PHY has a separate DP_COM control block */
bool has_phy_dp_com_ctrl;
+ /* true, if PHY has secondary tx/rx lanes to be configured */
+ bool is_dual_lane_phy;
/* Register offset of secondary tx/rx lanes for USB DP combo PHY */
unsigned int tx_b_lane_offset;
unsigned int rx_b_lane_offset;
+
+ /* true, if PCS block has no separate SW_RESET register */
+ bool no_pcs_sw_reset;
};
/**
@@ -748,6 +835,10 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
"aux", "cfg_ahb", "ref", "com_aux",
};
+static const char * const sdm845_ufs_phy_clk_l[] = {
+ "ref", "ref_aux",
+};
+
/* list of resets */
static const char * const msm8996_pciephy_reset_l[] = {
"phy", "common", "cfg",
@@ -758,7 +849,7 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
};
/* list of regulators */
-static const char * const msm8996_phy_vreg_l[] = {
+static const char * const qmp_phy_vreg_l[] = {
"vdda-phy", "vdda-pll",
};
@@ -778,8 +869,8 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
.num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
.reset_list = msm8996_pciephy_reset_l,
.num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
- .vreg_list = msm8996_phy_vreg_l,
- .num_vregs = ARRAY_SIZE(msm8996_phy_vreg_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = pciephy_regs_layout,
.start_ctrl = PCS_START | PLL_READY_GATE_EN,
@@ -809,8 +900,8 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
.num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
- .vreg_list = msm8996_phy_vreg_l,
- .num_vregs = ARRAY_SIZE(msm8996_phy_vreg_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = usb3phy_regs_layout,
.start_ctrl = SERDES_START | PCS_START,
@@ -870,8 +961,8 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
.num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
- .vreg_list = msm8996_phy_vreg_l,
- .num_vregs = ARRAY_SIZE(msm8996_phy_vreg_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = qmp_v3_usb3phy_regs_layout,
.start_ctrl = SERDES_START | PCS_START,
@@ -883,6 +974,7 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
.has_phy_dp_com_ctrl = true,
+ .is_dual_lane_phy = true,
.tx_b_lane_offset = 0x400,
.rx_b_lane_offset = 0x400,
};
@@ -903,8 +995,8 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
.num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
- .vreg_list = msm8996_phy_vreg_l,
- .num_vregs = ARRAY_SIZE(msm8996_phy_vreg_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = qmp_v3_usb3phy_regs_layout,
.start_ctrl = SERDES_START | PCS_START,
@@ -916,6 +1008,35 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
};
+static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
+ .type = PHY_TYPE_UFS,
+ .nlanes = 2,
+
+ .serdes_tbl = sdm845_ufsphy_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
+ .tx_tbl = sdm845_ufsphy_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
+ .rx_tbl = sdm845_ufsphy_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
+ .pcs_tbl = sdm845_ufsphy_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
+ .clk_list = sdm845_ufs_phy_clk_l,
+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = sdm845_ufsphy_regs_layout,
+
+ .start_ctrl = SERDES_START,
+ .pwrdn_ctrl = SW_PWRDN,
+ .mask_pcs_ready = PCS_READY,
+
+ .is_dual_lane_phy = true,
+ .tx_b_lane_offset = 0x400,
+ .rx_b_lane_offset = 0x400,
+
+ .no_pcs_sw_reset = true,
+};
+
static void qcom_qmp_phy_configure(void __iomem *base,
const unsigned int *regs,
const struct qmp_phy_init_tbl tbl[],
@@ -938,7 +1059,9 @@ static void qcom_qmp_phy_configure(void __iomem *base,
static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp)
{
const struct qmp_phy_cfg *cfg = qmp->cfg;
+ struct qmp_phy *qphy = qmp->phys[0];
void __iomem *serdes = qmp->serdes;
+ void __iomem *pcs = qphy->pcs;
void __iomem *dp_com = qmp->dp_com;
int ret, i;
@@ -1114,18 +1237,27 @@ static int qcom_qmp_phy_init(struct phy *phy)
/* Tx, Rx, and PCS configurations */
qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num);
/* Configuration for other LANE for USB-DP combo PHY */
- if (cfg->has_phy_dp_com_ctrl)
+ if (cfg->is_dual_lane_phy)
qcom_qmp_phy_configure(tx + cfg->tx_b_lane_offset, cfg->regs,
cfg->tx_tbl, cfg->tx_tbl_num);
qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num);
- if (cfg->has_phy_dp_com_ctrl)
+ if (cfg->is_dual_lane_phy)
qcom_qmp_phy_configure(rx + cfg->rx_b_lane_offset, cfg->regs,
cfg->rx_tbl, cfg->rx_tbl_num);
qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
/*
+ * UFS PHY requires the deassert of software reset before serdes start.
+ * For UFS PHY that has not software reset control bits in its address
+ * space, it should skip starting serdes here. UFS PHY Serdes shall
+ * start when UFS explicitly calls PHY power on.
+ */
+ if ((cfg->type == PHY_TYPE_UFS) && cfg->no_pcs_sw_reset)
+ goto out;
+
+ /*
* Pull out PHY from POWER DOWN state.
* This is active low enable signal to power-down PHY.
*/
@@ -1154,6 +1286,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
}
qmp->phy_initialized = true;
+out:
return ret;
err_pcs_ready:
@@ -1176,7 +1309,8 @@ static int qcom_qmp_phy_exit(struct phy *phy)
clk_disable_unprepare(qphy->pipe_clk);
/* PHY reset */
- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
+ if (!cfg->no_pcs_sw_reset)
+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
/* stop SerDes and Phy-Coding-Sublayer */
qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
@@ -1194,6 +1328,44 @@ static int qcom_qmp_phy_exit(struct phy *phy)
return 0;
}
+static int qcom_qmp_phy_poweron(struct phy *phy)
+{
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+ struct qcom_qmp *qmp = qphy->qmp;
+ const struct qmp_phy_cfg *cfg = qmp->cfg;
+ void __iomem *pcs = qphy->pcs;
+ void __iomem *status;
+ unsigned int mask, val;
+ int ret = 0;
+
+ if (cfg->type != PHY_TYPE_UFS)
+ return 0;
+
+ /*
+ * For UFS PHY that has not software reset control, serdes start
+ * should only happen when UFS driver explicitly calls phy_power_on
+ * after it deasserts software reset.
+ */
+ if (cfg->no_pcs_sw_reset && !qmp->phy_initialized &&
+ (qmp->init_count !=0)) {
+ /* start SerDes and Phy-Coding-Sublayer */
+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
+
+ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
+ mask = cfg->mask_pcs_ready;
+
+ ret = readl_poll_timeout(status, val, !(val & mask), 1,
+ PHY_INIT_COMPLETE_TIMEOUT);
+ if (ret) {
+ dev_err(qmp->dev, "phy initialization timed-out\n");
+ return ret;
+ }
+ qmp->phy_initialized = true;
+ }
+
+ return ret;
+}
+
static int qcom_qmp_phy_set_mode(struct phy *phy, enum phy_mode mode)
{
struct qmp_phy *qphy = phy_get_drvdata(phy);
@@ -1423,6 +1595,7 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
static const struct phy_ops qcom_qmp_phy_gen_ops = {
.init = qcom_qmp_phy_init,
.exit = qcom_qmp_phy_exit,
+ .power_on = qcom_qmp_phy_poweron,
.set_mode = qcom_qmp_phy_set_mode,
.owner = THIS_MODULE,
};
@@ -1528,6 +1701,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
}, {
.compatible = "qcom,sdm845-qmp-usb3-uni-phy",
.data = &qmp_v3_usb3_uniphy_cfg,
+ }, {
+ .compatible = "qcom,sdm845-qmp-ufs-phy",
+ .data = &sdm845_ufsphy_cfg,
},
{ },
};
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 5d78d43..d201cc3 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -184,6 +184,8 @@
#define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8
#define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc
#define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100
+#define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104
+#define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108
#define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c
#define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120
#define QSERDES_V3_COM_CLK_SELECT 0x138
@@ -211,8 +213,13 @@
/* Only for QMP V3 PHY - RX registers */
#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c
#define QSERDES_V3_RX_UCDR_SO_GAIN 0x014
+#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024
+#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
+#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c
#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030
#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
+#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
+#define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044
#define QSERDES_V3_RX_RX_TERM_BW 0x07c
#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc
#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0
@@ -239,6 +246,8 @@
#define QPHY_V3_PCS_TXMGN_V3 0x018
#define QPHY_V3_PCS_TXMGN_V4 0x01c
#define QPHY_V3_PCS_TXMGN_LS 0x020
+#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c
+#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c
@@ -275,6 +284,12 @@
#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
+#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134
+#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138
+#define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c
+#define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140
+#define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc
+#define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4
#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v6 3/3] dt-bindings: phy-qcom-qmp: Add UFS phy compatible string for sdm845
From: Can Guo @ 2018-05-29 4:37 UTC (permalink / raw)
To: subhashj, asutoshd, vivek.gautam, mgautam, kishon, robh+dt,
mark.rutland
Cc: linux-kernel, devicetree, Can Guo
In-Reply-To: <20180529043751.10580-1-cang@codeaurora.org>
Update the compatible string for UFS QMP PHY on SDM845.
Signed-off-by: Can Guo <cang@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
index cef8765..930d94c 100644
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -11,7 +11,8 @@ Required properties:
"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
"qcom,qmp-v3-usb3-phy" for USB3 QMP V3 phy,
"qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
- "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845.
+ "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
+ "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
- reg: offset and length of register set for PHY's common serdes block.
@@ -29,6 +30,7 @@ Required properties:
"aux" for phy aux clock,
"ref" for 19.2 MHz ref clk,
"com_aux" for phy common block aux clock,
+ "ref_aux" for phy reference aux clock,
For "qcom,msm8996-qmp-pcie-phy" must contain:
"aux", "cfg_ahb", "ref".
For "qcom,msm8996-qmp-usb3-phy" must contain:
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* Re: [v5 1/6] dmaengine: fsldma: Replace DMA_IN/OUT by FSL_DMA_IN/OUT
From: Vinod @ 2018-05-29 4:49 UTC (permalink / raw)
To: Wen He; +Cc: dmaengine, robh+dt, devicetree, leoyang.li, jiafei.pan,
jiaheng.fan
In-Reply-To: <20180525111920.24498-1-wen.he_1@nxp.com>
On 25-05-18, 19:19, Wen He wrote:
> This patch implenment a standard macro call functions is
> used to NXP dma drivers.
Well that patch seems to do a bit more than replace DMA_IN/OUT by FSL_DMA_IN/OUT
care to explain those. best would be to do a patch which does replace and then
add new things in separate patch, easier to review
--
~Vinod
^ permalink raw reply
* [PATCH 0/2] Add Mediatek X20 Development Board support
From: Manivannan Sadhasivam @ 2018-05-29 4:52 UTC (permalink / raw)
To: matthias.bgg, robh+dt
Cc: linux-arm-kernel, linux-mediatek, devicetree, linux-kernel,
taiten.peng, daniel.thompson, amit.kucheria, manivannanece23,
Manivannan Sadhasivam
Add devicetree support for Mediatek X20 Development Board by Archermind.
This board is based on the Deca-Core MT6797 SoC from Mediatek and is
one of the 96Boards Consumer Edition platform.
With this devicetree change, board can boot into initramfs.
More information about this board can be found in 96Boards product page:
https://www.96boards.org/product/mediatek-x20/
Manivannan Sadhasivam (2):
dt-bindings: Add vendor prefix for ArcherMind
arm64: dts: Add Mediatek X20 Development Board support
.../devicetree/bindings/vendor-prefixes.txt | 1 +
arch/arm64/boot/dts/mediatek/Makefile | 1 +
.../boot/dts/mediatek/mt6797-x20-dev.dts | 33 +++++++++++++++++++
3 files changed, 35 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
--
2.17.0
^ permalink raw reply
* [PATCH 1/2] dt-bindings: Add vendor prefix for ArcherMind
From: Manivannan Sadhasivam @ 2018-05-29 4:52 UTC (permalink / raw)
To: matthias.bgg, robh+dt
Cc: linux-arm-kernel, linux-mediatek, devicetree, linux-kernel,
taiten.peng, daniel.thompson, amit.kucheria, manivannanece23,
Manivannan Sadhasivam
In-Reply-To: <20180529045258.1415-1-manivannan.sadhasivam@linaro.org>
Add vendor prefix for ArcherMind Technology (Nanjing) Co., Ltd.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index a38d8bfae19c..f601acb5a0b4 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -32,6 +32,7 @@ andestech Andes Technology Corporation
apm Applied Micro Circuits Corporation (APM)
aptina Aptina Imaging
arasan Arasan Chip Systems
+archermind ArcherMind Technology (Nanjing) Co., Ltd.
arctic Arctic Sand
aries Aries Embedded GmbH
arm ARM Ltd.
--
2.17.0
^ permalink raw reply related
* [PATCH 2/2] arm64: dts: Add Mediatek X20 Development Board support
From: Manivannan Sadhasivam @ 2018-05-29 4:52 UTC (permalink / raw)
To: matthias.bgg, robh+dt
Cc: linux-arm-kernel, linux-mediatek, devicetree, linux-kernel,
taiten.peng, daniel.thompson, amit.kucheria, manivannanece23,
Manivannan Sadhasivam
In-Reply-To: <20180529045258.1415-1-manivannan.sadhasivam@linaro.org>
Add initial device tree support for Mediatek X20 Development Board
based on MT6797 Deca core SoC. This board is one of the 96Boards
Consumer Edition platform.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
.../boot/dts/mediatek/mt6797-x20-dev.dts | 33 +++++++++++++++++++
2 files changed, 34 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index ac17f60f998c..5b7fd6ad96e4 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -3,5 +3,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
new file mode 100644
index 000000000000..2c09ca95d9e2
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for MediaTek X20 Development Board
+ *
+ * Copyright (C) 2018, Linaro Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "mt6797.dtsi"
+
+/ {
+ model = "Mediatek X20 Development Board";
+ compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x1e605000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
--
2.17.0
^ permalink raw reply related
* Re: [PATCH v2 1/8] driver core: make deferring probe after init optional
From: Frank Rowand @ 2018-05-29 5:12 UTC (permalink / raw)
To: Mark Brown, Rob Herring
Cc: Greg Kroah-Hartman, Linus Walleij, Alexander Graf,
Bjorn Andersson, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson,
Joerg Roedel, Robin Murphy, linux-kernel, devicetree,
boot-architecture, linux-arm-kernel
In-Reply-To: <20180524181834.GF4828@sirena.org.uk>
On 05/24/18 11:18, Mark Brown wrote:
> On Thu, May 24, 2018 at 12:50:17PM -0500, Rob Herring wrote:
>
>> Subsystems or drivers may opt-in to this behavior by calling
>> driver_deferred_probe_check_init_done() instead of just returning
>> -EPROBE_DEFER. They may use additional information from DT or kernel's
>> config to decide whether to continue to defer probe or not.
>
> Should userspace have some involvement in this decision? It knows if
> it's got any intention of loading modules for example. Kernel config
> checks might be good enough, though it's going to be a pain to work out
> if the relevant driver is built as a module for example.
>
A parallel issue is that loading an overlay could provide the resource
that will allow the deferred probe to complete. (That is, once we
finish implementing the run time overlays feature.)
-Frank
^ permalink raw reply
* enable OTG on wandboard and riotboard
From: Alexander Kurz @ 2018-05-29 6:20 UTC (permalink / raw)
To: Shawn Guo; +Cc: Fabio Estevam, devicetree, linux-arm-kernel
Both boards wandboard and riotboard feature an USB OTG connector.
Change the DT regulator nodes to match the convention, fix the
GPIO regulator polatity for the riotboard and add enable OTG
including the regulator infrastructure on the riotboard.
Changes since v2:
* split patch 0001 into two board specific patches
* use GPIO_ACTIVE_HIGH instead of literal numbers in patch v1-0001 (now v2-0002)
^ permalink raw reply
* [PATCH v2 1/4] ARM: dts: imx6qdl-wandboard: remove regulators bus node
From: Alexander Kurz @ 2018-05-29 6:20 UTC (permalink / raw)
To: Shawn Guo; +Cc: Fabio Estevam, devicetree, Alexander Kurz, linux-arm-kernel
In-Reply-To: <20180529062021.3154-1-akurz@blala.de>
To match the convention, move all regulator-fixed nodes directly into
the root node.
Signed-off-by: Alexander Kurz <akurz@blala.de>
---
arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 40 +++++++++++++-------------------
1 file changed, 16 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index ed96d7b5feab..b9c6c9d5d357 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -12,30 +12,6 @@
#include <dt-bindings/gpio/gpio.h>
/ {
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg_2p5v: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "2P5V";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- regulator-always-on;
- };
-
- reg_3p3v: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
-
sound {
compatible = "fsl,imx6-wandboard-sgtl5000",
"fsl,imx-audio-sgtl5000";
@@ -56,6 +32,22 @@
spdif-controller = <&spdif>;
spdif-out;
};
+
+ reg_2p5v: regulator-2p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
};
&audmux {
--
2.11.0
^ permalink raw reply related
* [PATCH v2 2/4] ARM: dts: imx6dl-riotboard: remove regulators bus node
From: Alexander Kurz @ 2018-05-29 6:20 UTC (permalink / raw)
To: Shawn Guo; +Cc: Fabio Estevam, devicetree, Alexander Kurz, linux-arm-kernel
In-Reply-To: <20180529062021.3154-1-akurz@blala.de>
To match the convention, move regulator-fixed nodes directly into
the root node.
Signed-off-by: Alexander Kurz <akurz@blala.de>
---
arch/arm/boot/dts/imx6dl-riotboard.dts | 55 ++++++++++++++--------------------
1 file changed, 23 insertions(+), 32 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
index 2e98c92adff7..a6851bfebbdb 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -19,38 +19,6 @@
reg = <0x10000000 0x40000000>;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg_2p5v: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "2P5V";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- };
-
- reg_3p3v: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- reg_usb_otg_vbus: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "usb_otg_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio3 22 0>;
- enable-active-high;
- };
- };
-
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -82,6 +50,29 @@
mux-int-port = <1>;
mux-ext-port = <3>;
};
+
+ reg_2p5v: regulator-2p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usb_otg_vbus: regulator-usbotgvbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
&audmux {
--
2.11.0
^ permalink raw reply related
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