* [PATCH 1/2] arm64: dts: stratix10: Fix SPI nodes for Stratix10
From: thor.thayer @ 2018-05-29 18:13 UTC (permalink / raw)
To: dinguyen
Cc: robh+dt, mark.rutland, catalin.marinas, will.deacon, devicetree,
linux-arm-kernel, Thor Thayer, stable
From: Thor Thayer <thor.thayer@linux.intel.com>
Remove the unused bus-num node and change num-chipselect
to num-cs to match SPI bindings.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Fixes: 78cd6a9d8e154 ("arm64: dts: Add base stratix 10 dtsi")
Cc: stable@vger.kernel.org
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index d8c94d5ff4b4..47fa4b450324 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -315,8 +315,7 @@
interrupts = <0 99 4>;
resets = <&rst SPIM0_RESET>;
reg-io-width = <4>;
- num-chipselect = <4>;
- bus-num = <0>;
+ num-cs = <4>;
status = "disabled";
};
@@ -328,8 +327,7 @@
interrupts = <0 100 4>;
resets = <&rst SPIM1_RESET>;
reg-io-width = <4>;
- num-chipselect = <4>;
- bus-num = <0>;
+ num-cs = <4>;
status = "disabled";
};
--
2.7.4
^ permalink raw reply related
* [PATCH 2/2] ARM: dts: Add SPI0 node for Arria10
From: thor.thayer @ 2018-05-29 18:08 UTC (permalink / raw)
To: dinguyen; +Cc: robh+dt, mark.rutland, devicetree, Thor Thayer
In-Reply-To: <1527617319-1936-1-git-send-email-thor.thayer@linux.intel.com>
From: Thor Thayer <thor.thayer@linux.intel.com>
Add the SPI0 node for Arria10.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 9138f834bad4..ee9a5fc616a8 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -587,6 +587,18 @@
status = "disabled";
};
+ spi0: spi@ffda4000 {
+ compatible = "snps,dw-apb-ssi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xffda4000 0x100>;
+ interrupts = <0 101 4>;
+ num-cs = <4>;
+ /*32bit_access;*/
+ clocks = <&spi_m_clk>;
+ status = "disabled";
+ };
+
spi1: spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
--
2.7.4
^ permalink raw reply related
* [PATCH 1/2] ARM: dts: Fix SPI node for Arria10
From: thor.thayer @ 2018-05-29 18:08 UTC (permalink / raw)
To: dinguyen; +Cc: robh+dt, mark.rutland, devicetree, Thor Thayer, stable
From: Thor Thayer <thor.thayer@linux.intel.com>
Remove the unused bus-num node and change num-chipselect
to num-cs to match SPI bindings.
Fixes: f2d6f8f817814 ("ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chip")
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Cc: stable@vger.kernel.org
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index bead79e4b2aa..9138f834bad4 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -593,8 +593,7 @@
#size-cells = <0>;
reg = <0xffda5000 0x100>;
interrupts = <0 102 4>;
- num-chipselect = <4>;
- bus-num = <0>;
+ num-cs = <4>;
/*32bit_access;*/
tx-dma-channel = <&pdma 16>;
rx-dma-channel = <&pdma 17>;
--
2.7.4
^ permalink raw reply related
* Re: [PATCH] i2c: rcar: document R8A77980 bindings
From: Wolfram Sang @ 2018-05-29 18:08 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, linux-i2c, devicetree, Mark Rutland,
linux-renesas-soc
In-Reply-To: <95b945f7-1e6c-39f1-e101-06ed748ccec2@cogentembedded.com>
[-- Attachment #1: Type: text/plain, Size: 301 bytes --]
On Mon, May 28, 2018 at 10:39:05PM +0300, Sergei Shtylyov wrote:
> R-Car V3H (R8A77980) SoC also has the R-Car gen3 compatible I2C controller,
> so document the SoC specific bindings.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
Applied to for-next, thanks!
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH 01/11] PM / devfreq: Init user limits from OPP limits, not viceversa
From: Matthias Kaehlcke @ 2018-05-29 18:06 UTC (permalink / raw)
To: Chanwoo Choi
Cc: MyungJoo Ham, Kyungmin Park, Arnd Bergmann, Greg Kroah-Hartman,
Rob Herring, Mark Rutland, linux-pm, devicetree, linux-kernel,
Brian Norris, Douglas Anderson
In-Reply-To: <5B0B9319.9060709@samsung.com>
On Mon, May 28, 2018 at 02:26:49PM +0900, Chanwoo Choi wrote:
> Hi,
>
> On 2018년 05월 26일 05:30, Matthias Kaehlcke wrote:
> > Commit ab8f58ad72c4 ("PM / devfreq: Set min/max_freq when adding
> > the devfreq device") introduced the initialization of the user
> > limits min/max_freq from the lowest/highest available OPPs. Later
> > commit f1d981eaecf8 ("PM / devfreq: Use the available min/max
> > frequency") added scaling_min/max_freq, which actually represent
> > the frequencies of the lowest/highest available OPP. scaling_min/
> > max_freq are initialized with the values from min/max_freq, which
> > is totally correct in the context, but a bit awkward to read.
> >
> > Swap the initialization and assign scaling_min/max_freq with the
> > OPP freqs and then the user limts min/max_freq with scaling_min/
> > max_freq.
> >
> > Needless to say that this change is a NOP, intended to improve
> > readability.
> >
> > Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
> > ---
> > drivers/devfreq/devfreq.c | 12 ++++++------
> > 1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
> > index fe2af6aa88fc..0057ef5b0a98 100644
> > --- a/drivers/devfreq/devfreq.c
> > +++ b/drivers/devfreq/devfreq.c
> > @@ -604,21 +604,21 @@ struct devfreq *devfreq_add_device(struct device *dev,
> > mutex_lock(&devfreq->lock);
> > }
> >
> > - devfreq->min_freq = find_available_min_freq(devfreq);
> > - if (!devfreq->min_freq) {
> > + devfreq->scaling_min_freq = find_available_min_freq(devfreq);
> > + if (!devfreq->scaling_min_freq) {
> > mutex_unlock(&devfreq->lock);
> > err = -EINVAL;
> > goto err_dev;
> > }
> > - devfreq->scaling_min_freq = devfreq->min_freq;
> > + devfreq->min_freq = devfreq->scaling_min_freq;
> >
> > - devfreq->max_freq = find_available_max_freq(devfreq);
> > - if (!devfreq->max_freq) {
> > + devfreq->scaling_max_freq = find_available_max_freq(devfreq);
> > + if (!devfreq->scaling_max_freq) {
> > mutex_unlock(&devfreq->lock);
> > err = -EINVAL;
> > goto err_dev;
> > }
> > - devfreq->scaling_max_freq = devfreq->max_freq;
> > + devfreq->max_freq = devfreq->scaling_max_freq;
> >
> > dev_set_name(&devfreq->dev, "devfreq%d",
> > atomic_inc_return(&devfreq_no));
> >
>
> I already replied with my Reviewed-by tag. You are missing my tag.
>
> Again,
> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Sorry, forgot to add the tag after creating the series. I now added it
to my local tree.
^ permalink raw reply
* Re: [RFC 12/13] ARM: dts: ti: add dra71-evm FIT description file
From: Russell King - ARM Linux @ 2018-05-29 17:33 UTC (permalink / raw)
To: Frank Rowand
Cc: mark.rutland, Rob Herring, devicetree, Tony Lindgren, Tero Kristo,
trini, wmills, linux-arm-kernel@lists.infradead.org
In-Reply-To: <16a6017f-96c8-42d8-38bc-5cdd36d6793f@gmail.com>
On Tue, May 29, 2018 at 10:05:37AM -0700, Frank Rowand wrote:
> On 05/22/18 13:01, Rob Herring wrote:
> > I'll tell you up front, I'm not a fan of FIT image (nor uImage,
> > Android boot image, $bootloader image). If you want a collection of
> > files and some configuration data, use a filesystem and a text file.
Me neither.
> My gut feel is that using a filesystem and a text file is the easier way
> to create the boot info. But that also makes applying the overlay(s)
> during early Linux boot (at the point of FDT unflattening) impractical
> (can't access the file system without a driver, the driver depends on
> the devicetree, the devicetree depends upon the overlay).
Why do you want to apply overlays during the kernel boot? The boot
loader should be providing the kernel with the merged DT to describe
the system that the kernel is running on - it's not the kernel's
job to put that together.
The whole point of DT is to make the kernel _less_ tied to the hardware
and more generic. If we're going to introduce an entirely new set of
drivers into the kernel to "probe" the hardware to determine which
overlays are required, then that's really defeating the purpose of DT.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up
^ permalink raw reply
* [PATCH] arm64: allwinner: a64-amarula-relic: Enable AP6330 WiFi support
From: Jagan Teki @ 2018-05-29 17:22 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Michael Trimarchi, Icenowy Zheng
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Jagan Teki
Enable AP6330 WiFi/BT combo chip on Amarula A64-Relic board:
- WiFi SDIO interface is connected to MMC1
- WiFi WL-PMU-EN pin connected to gpio PL2: attach to mmc-pwrseq
- WiFi WL-WAKE-AP pin connected to gpio PL3
- 32kHz external oscillator gate clock from RTC
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
.../dts/allwinner/sun50i-a64-amarula-relic.dts | 37 ++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
index ce4a256ff086..a77b70ca88e3 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
@@ -21,12 +21,43 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rtc 1>;
+ clock-names = "ext_clock";
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */
+ };
};
&ehci0 {
status = "okay";
};
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <®_dcdc1>;
+ /*
+ * Schematic shows both dldo4 and eldo1 connected for vcc-io-wifi, but
+ * dldo4 connection shows DNP(Do Not Populate) and eldo1 connected with
+ * 0Ohm register to vcc-io-wifi so eldo1 is used.
+ */
+ vqmmc-supply = <®_eldo1>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* WL-WAKE-AP: PL3 */
+ interrupt-names = "host-wake";
+ };
+};
+
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
@@ -170,6 +201,12 @@
regulator-name = "vcc-rtc";
};
+&rtc {
+ clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
+ clocks = <&osc32k>;
+ #clock-cells = <1>;
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
--
2.14.3
^ permalink raw reply related
* Re: [RFC 12/13] ARM: dts: ti: add dra71-evm FIT description file
From: Frank Rowand @ 2018-05-29 17:05 UTC (permalink / raw)
To: Rob Herring, Tero Kristo
Cc: mark.rutland, devicetree, trini, Tony Lindgren,
Russell King - ARM Linux, wmills,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20180522200100.GA23937@rob-hp-laptop>
On 05/22/18 13:01, Rob Herring wrote:
> On Mon, May 21, 2018 at 09:57:54AM +0300, Tero Kristo wrote:
>> On 17/04/18 17:49, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [180417 09:36]:
>>>> In typical setup, you can boot a large number of different configs via:
>>>>
>>>> bootm 0x82000000#dra71-evm#nand#lcd-auo-g101evn01.0
>>>>
>>>> ... assuming the configs were named like that, and assuming they would be
>>>> compatible with each other. The am57xx-evm example provided is better, as
>>>> you can chain the different cameras to the available evm configs.
>>>
>>> Why not just do it in the bootloader to put together the dtb?
>>>
>>> Then for external devices, you could just pass info on the
>>> kernel cmdline with lcd=foo camera=bar if they cannot be
>>> detected over I2C.
>>
>> (Added Linux ARM list to CC, this was not part of the original delivery.)
>>
>> Ok trying to resurrect this thread a bit. Is there any kind of consensus how
>> things like this should be handled? Should we add the DT overlay files to
>> kernel tree or not?
>
> IMO, yes.
Agreed.
>
>> Should we add any kind of build infra to kernel tree, and at what level
>> would this be? Just DT overlay file building support, and drop the FIT build
>> support as was proposed in this RFC series or...?
>
> I think I mentioned this already, but I expect that this is going to
> cause a number of conversions of dtsi + dtsi -> dtb into base dts and
> overlay(s) dts files. In doing so, we still need to be able to build the
> original, full dtb.
>
>> U-boot can obviously parse the base DTB + overlay DTB:s into a single DTB,
>> but this is somewhat clumsy approach and is relatively error prone to get it
>> right.
>
> Why? How is the kernel better?
>
>> Building the FIT image post kernel build would also be possible, but who
>> would be doing this, is there any need to get this done in generic manner or
>> shall we just add SoC vendor specific tools for this?
>
> I'll tell you up front, I'm not a fan of FIT image (nor uImage,
> Android boot image, $bootloader image). If you want a collection of
> files and some configuration data, use a filesystem and a text file.
My gut feel is that using a filesystem and a text file is the easier way
to create the boot info. But that also makes applying the overlay(s)
during early Linux boot (at the point of FDT unflattening) impractical
(can't access the file system without a driver, the driver depends on
the devicetree, the devicetree depends upon the overlay).
>
> Rob
>
^ permalink raw reply
* [PATCH v3 5/5] ARM: dts: imx6qdl: add missing compatible and clock properties for EPIT
From: Clément Péron @ 2018-05-29 17:04 UTC (permalink / raw)
To: Colin Didier, linux-arm-kernel, devicetree, linux-clk
Cc: Rob Herring, Sascha Hauer, Clément Peron, NXP Linux Team,
Pengutronix Kernel Team, Fabio Estevam, Vladimir Zapolskiy
In-Reply-To: <20180529170436.22711-1-peron.clem@gmail.com>
From: Colin Didier <colin.didier@devialet.com>
Add missing compatible and clock properties for EPIT node.
Signed-off-by: Colin Didier <colin.didier@devialet.com>
Signed-off-by: Clément Peron <clement.peron@devialet.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/boot/dts/imx6qdl.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index c003e62bf290..75bbaca34cbc 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -844,13 +844,23 @@
};
epit1: epit@20d0000 { /* EPIT1 */
+ compatible = "fsl,imx6q-epit";
reg = <0x020d0000 0x4000>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_EPIT1>,
+ <&clks IMX6QDL_CLK_IPG_PER>;
+ clock-names = "ipg", "per";
+ status = "disabled";
};
epit2: epit@20d4000 { /* EPIT2 */
+ compatible = "fsl,imx6q-epit";
reg = <0x020d4000 0x4000>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_EPIT2>,
+ <&clks IMX6QDL_CLK_IPG_PER>;
+ clock-names = "ipg", "per";
+ status = "disabled";
};
src: src@20d8000 {
--
2.17.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v3 4/5] clocksource: add driver for i.MX EPIT timer
From: Clément Péron @ 2018-05-29 17:04 UTC (permalink / raw)
To: Colin Didier, linux-arm-kernel, devicetree, linux-clk
Cc: Rob Herring, Sascha Hauer, Clément Peron, NXP Linux Team,
Pengutronix Kernel Team, Fabio Estevam, Vladimir Zapolskiy
In-Reply-To: <20180529170436.22711-1-peron.clem@gmail.com>
From: Colin Didier <colin.didier@devialet.com>
Add driver for NXP's EPIT timer used in i.MX 6 family of SoC.
Signed-off-by: Colin Didier <colin.didier@devialet.com>
Signed-off-by: Clément Peron <clement.peron@devialet.com>
---
drivers/clocksource/Kconfig | 12 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-imx-epit.c | 283 +++++++++++++++++++++++++++
3 files changed, 296 insertions(+)
create mode 100644 drivers/clocksource/timer-imx-epit.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 8e8a09755d10..920a0874f3a4 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -576,6 +576,18 @@ config H8300_TPU
This enables the clocksource for the H8300 platform with the
H8S2678 cpu.
+config CLKSRC_IMX_EPIT
+ bool "Clocksource using i.MX EPIT"
+ depends on ARM && CLKDEV_LOOKUP && OF && (ARCH_MXC || COMPILE_TEST)
+ select TIMER_OF
+ select CLKSRC_MMIO
+ help
+ This enables EPIT support available on some i.MX platforms.
+ Normally you don't have a reason to do so as the EPIT has
+ the same features and uses the same clocks as the GPT.
+ Anyway, on some systems the GPT may be in use for other
+ purposes.
+
config CLKSRC_IMX_GPT
bool "Clocksource using i.MX GPT" if COMPILE_TEST
depends on ARM && CLKDEV_LOOKUP
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 00caf37e52f9..d9426f69ec69 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_INTEGRATOR_AP_TIMER) += timer-integrator-ap.o
obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o
obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o
obj-$(CONFIG_CLKSRC_TANGO_XTAL) += tango_xtal.o
+obj-$(CONFIG_CLKSRC_IMX_EPIT) += timer-imx-epit.o
obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o
obj-$(CONFIG_CLKSRC_IMX_TPM) += timer-imx-tpm.o
obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o
diff --git a/drivers/clocksource/timer-imx-epit.c b/drivers/clocksource/timer-imx-epit.c
new file mode 100644
index 000000000000..87025d5f3a97
--- /dev/null
+++ b/drivers/clocksource/timer-imx-epit.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * i.MX EPIT Timer
+ *
+ * Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de>
+ * Copyright (C) 2018 Colin Didier <colin.didier@devialet.com>
+ * Copyright (C) 2018 Clément Péron <clement.peron@devialet.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of.h>
+#include <linux/sched_clock.h>
+#include <linux/slab.h>
+
+#define EPITCR 0x00
+#define EPITSR 0x04
+#define EPITLR 0x08
+#define EPITCMPR 0x0c
+#define EPITCNR 0x10
+
+#define EPITCR_EN BIT(0)
+#define EPITCR_ENMOD BIT(1)
+#define EPITCR_OCIEN BIT(2)
+#define EPITCR_RLD BIT(3)
+#define EPITCR_PRESC(x) (((x) & 0xfff) << 4)
+#define EPITCR_SWR BIT(16)
+#define EPITCR_IOVW BIT(17)
+#define EPITCR_DBGEN BIT(18)
+#define EPITCR_WAITEN BIT(19)
+#define EPITCR_RES BIT(20)
+#define EPITCR_STOPEN BIT(21)
+#define EPITCR_OM_DISCON (0 << 22)
+#define EPITCR_OM_TOGGLE (1 << 22)
+#define EPITCR_OM_CLEAR (2 << 22)
+#define EPITCR_OM_SET (3 << 22)
+#define EPITCR_CLKSRC_OFF (0 << 24)
+#define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
+#define EPITCR_CLKSRC_REF_HIGH (2 << 24)
+#define EPITCR_CLKSRC_REF_LOW (3 << 24)
+
+#define EPITSR_OCIF BIT(0)
+
+struct epit_timer {
+ void __iomem *base;
+ int irq;
+ struct clk *clk_per;
+ struct clock_event_device ced;
+ struct irqaction act;
+};
+
+static void __iomem *sched_clock_reg;
+
+static inline struct epit_timer *to_epit_timer(struct clock_event_device *ced)
+{
+ return container_of(ced, struct epit_timer, ced);
+}
+
+static inline void epit_irq_disable(struct epit_timer *epittm)
+{
+ u32 val;
+
+ val = readl_relaxed(epittm->base + EPITCR);
+ writel_relaxed(val & ~EPITCR_OCIEN, epittm->base + EPITCR);
+}
+
+static inline void epit_irq_enable(struct epit_timer *epittm)
+{
+ u32 val;
+
+ val = readl_relaxed(epittm->base + EPITCR);
+ writel_relaxed(val | EPITCR_OCIEN, epittm->base + EPITCR);
+}
+
+static void epit_irq_acknowledge(struct epit_timer *epittm)
+{
+ writel_relaxed(EPITSR_OCIF, epittm->base + EPITSR);
+}
+
+static u64 notrace epit_read_sched_clock(void)
+{
+ return ~readl_relaxed(sched_clock_reg);
+}
+
+static int __init epit_clocksource_init(struct epit_timer *epittm)
+{
+ unsigned int c = clk_get_rate(epittm->clk_per);
+
+ sched_clock_reg = epittm->base + EPITCNR;
+ sched_clock_register(epit_read_sched_clock, 32, c);
+
+ return clocksource_mmio_init(epittm->base + EPITCNR, "epit", c, 200, 32,
+ clocksource_mmio_readl_down);
+}
+
+static int epit_set_next_event(unsigned long cycles,
+ struct clock_event_device *ced)
+{
+ struct epit_timer *epittm = to_epit_timer(ced);
+ unsigned long tcmp;
+
+ tcmp = readl_relaxed(epittm->base + EPITCNR) - cycles;
+ writel_relaxed(tcmp, epittm->base + EPITCMPR);
+
+ return 0;
+}
+
+/* Left event sources disabled, no more interrupts appear */
+static int epit_shutdown(struct clock_event_device *ced)
+{
+ struct epit_timer *epittm = to_epit_timer(ced);
+ unsigned long flags;
+
+ /*
+ * The timer interrupt generation is disabled at least
+ * for enough time to call epit_set_next_event()
+ */
+ local_irq_save(flags);
+
+ /* Disable interrupt in EPIT module */
+ epit_irq_disable(epittm);
+
+ /* Clear pending interrupt */
+ epit_irq_acknowledge(epittm);
+
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static int epit_set_oneshot(struct clock_event_device *ced)
+{
+ struct epit_timer *epittm = to_epit_timer(ced);
+ unsigned long flags;
+
+ /*
+ * The timer interrupt generation is disabled at least
+ * for enough time to call epit_set_next_event()
+ */
+ local_irq_save(flags);
+
+ /* Disable interrupt in EPIT module */
+ epit_irq_disable(epittm);
+
+ /* Clear pending interrupt, only while switching mode */
+ if (!clockevent_state_oneshot(ced))
+ epit_irq_acknowledge(epittm);
+
+ /*
+ * Do not put overhead of interrupt enable/disable into
+ * epit_set_next_event(), the core has about 4 minutes
+ * to call epit_set_next_event() or shutdown clock after
+ * mode switching
+ */
+ epit_irq_enable(epittm);
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *ced = dev_id;
+ struct epit_timer *epittm = to_epit_timer(ced);
+
+ epit_irq_acknowledge(epittm);
+
+ ced->event_handler(ced);
+
+ return IRQ_HANDLED;
+}
+
+static int __init epit_clockevent_init(struct epit_timer *epittm)
+{
+ struct clock_event_device *ced = &epittm->ced;
+ struct irqaction *act = &epittm->act;
+
+ ced->name = "epit";
+ ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
+ ced->set_state_shutdown = epit_shutdown;
+ ced->tick_resume = epit_shutdown;
+ ced->set_state_oneshot = epit_set_oneshot;
+ ced->set_next_event = epit_set_next_event;
+ ced->rating = 200;
+ ced->cpumask = cpumask_of(0);
+ ced->irq = epittm->irq;
+ clockevents_config_and_register(ced, clk_get_rate(epittm->clk_per),
+ 0xff, 0xfffffffe);
+
+ act->name = "i.MX EPIT Timer Tick",
+ act->flags = IRQF_TIMER | IRQF_IRQPOLL;
+ act->handler = epit_timer_interrupt;
+ act->dev_id = ced;
+
+ /* Make irqs happen */
+ return setup_irq(epittm->irq, act);
+}
+
+static int __init epit_timer_init(struct device_node *np)
+{
+ struct epit_timer *epittm;
+ struct clk *clk_ipg;
+ int ret;
+
+ epittm = kzalloc(sizeof(*epittm), GFP_KERNEL);
+ if (!epittm)
+ return -ENOMEM;
+
+ epittm->base = of_iomap(np, 0);
+ if (!epittm->base) {
+ ret = -ENXIO;
+ goto out_kfree;
+ }
+
+ epittm->irq = irq_of_parse_and_map(np, 0);
+ if (!epittm->irq) {
+ ret = -EINVAL;
+ goto out_iounmap;
+ }
+
+ clk_ipg = of_clk_get_by_name(np, "ipg");
+ if (IS_ERR(clk_ipg)) {
+ pr_err("i.MX EPIT: unable to get clk_ipg\n");
+ ret = PTR_ERR(clk_ipg);
+ goto out_iounmap;
+ }
+
+ ret = clk_prepare_enable(clk_ipg);
+ if (ret) {
+ pr_err("i.MX EPIT: unable to prepare+enable clk_ipg\n");
+ goto out_clk_ipg_disable;
+ }
+
+ epittm->clk_per = of_clk_get_by_name(np, "per");
+ if (IS_ERR(epittm->clk_per)) {
+ pr_err("i.MX EPIT: unable to get clk_per\n");
+ ret = PTR_ERR(epittm->clk_per);
+ goto out_clk_ipg_disable;
+ }
+
+ ret = clk_prepare_enable(epittm->clk_per);
+ if (ret) {
+ pr_err("i.MX EPIT: unable to prepare+enable clk_per\n");
+ goto out_clk_ipg_disable;
+ }
+
+ /* Initialise to a known state (all timers off, and timing reset) */
+ writel_relaxed(0x0, epittm->base + EPITCR);
+ writel_relaxed(0xffffffff, epittm->base + EPITLR);
+ writel_relaxed(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
+ epittm->base + EPITCR);
+
+ ret = epit_clocksource_init(epittm);
+ if(ret) {
+ pr_err("i.MX EPIT: failed to init clocksource\n");
+ goto out_clk_per_disable;
+ }
+
+ ret = epit_clockevent_init(epittm);
+ if(ret) {
+ pr_err("i.MX EPIT: failed to init clockevent\n");
+ goto out_clk_per_disable;
+ }
+
+ return 0;
+
+out_clk_per_disable:
+ clk_disable_unprepare(epittm->clk_per);
+out_clk_ipg_disable:
+ clk_disable_unprepare(clk_ipg);
+out_iounmap:
+ iounmap(epittm->base);
+out_kfree:
+ kfree(epittm);
+
+ return ret;
+}
+TIMER_OF_DECLARE(mx6q_timer, "fsl,imx6q-epit", epit_timer_init);
--
2.17.0
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* [PATCH v3 3/5] Documentation: DT: add i.MX EPIT timer binding
From: Clément Péron @ 2018-05-29 17:04 UTC (permalink / raw)
To: Colin Didier, linux-arm-kernel, devicetree, linux-clk
Cc: Rob Herring, Sascha Hauer, Clément Peron, NXP Linux Team,
Pengutronix Kernel Team, Fabio Estevam, Vladimir Zapolskiy
In-Reply-To: <20180529170436.22711-1-peron.clem@gmail.com>
From: Clément Peron <clement.peron@devialet.com>
Add devicetree binding document for NXP's i.MX SoC specific
EPIT timer driver.
Signed-off-by: Clément Peron <clement.peron@devialet.com>
---
.../devicetree/bindings/clock/imx6q,epit.txt | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx6q,epit.txt
diff --git a/Documentation/devicetree/bindings/clock/imx6q,epit.txt b/Documentation/devicetree/bindings/clock/imx6q,epit.txt
new file mode 100644
index 000000000000..a84a60c6ae35
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6q,epit.txt
@@ -0,0 +1,24 @@
+Binding for the i.MX6 EPIT timer
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: should be "fsl,imx6q-epit"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: Should contain EPIT controller interrupt
+- clocks: list of clock specifiers, must contain an entry for each required
+ entry in clock-names
+- clock-names : should include entries "ipg", "per"
+
+Example:
+ epit1: epit@20d0000 {
+ compatible = "fsl,imx6q-epit";
+ reg = <0x020d0000 0x4000>;
+ interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_EPIT1>,
+ <&clks IMX6QDL_CLK_IPG_PER>;
+ clock-names = "ipg", "per";
+ };
--
2.17.0
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^ permalink raw reply related
* [PATCH v3 2/5] clk: imx6: add EPIT clock support
From: Clément Péron @ 2018-05-29 17:04 UTC (permalink / raw)
To: Colin Didier, linux-arm-kernel, devicetree, linux-clk
Cc: Rob Herring, Sascha Hauer, Clément Peron, NXP Linux Team,
Pengutronix Kernel Team, Fabio Estevam, Vladimir Zapolskiy
In-Reply-To: <20180529170436.22711-1-peron.clem@gmail.com>
From: Colin Didier <colin.didier@devialet.com>
Add EPIT clock support to the i.MX6Q clocking infrastructure.
Signed-off-by: Colin Didier <colin.didier@devialet.com>
Signed-off-by: Clément Peron <clement.peron@devialet.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
drivers/clk/imx/clk-imx6q.c | 2 ++
include/dt-bindings/clock/imx6qdl-clock.h | 4 +++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 8d518ad5dc13..b9ea7037e193 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -753,6 +753,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
else
clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
+ clk[IMX6QDL_CLK_EPIT1] = imx_clk_gate2("epit1", "ipg", base + 0x6c, 12);
+ clk[IMX6QDL_CLK_EPIT2] = imx_clk_gate2("epit2", "ipg", base + 0x6c, 14);
clk[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index da59fd9cdb5e..7ad171b8f3bf 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -271,6 +271,8 @@
#define IMX6QDL_CLK_PRE_AXI 258
#define IMX6QDL_CLK_MLB_SEL 259
#define IMX6QDL_CLK_MLB_PODF 260
-#define IMX6QDL_CLK_END 261
+#define IMX6QDL_CLK_EPIT1 261
+#define IMX6QDL_CLK_EPIT2 262
+#define IMX6QDL_CLK_END 263
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
--
2.17.0
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* [PATCH v3 1/5] ARM: imx: remove inexistant EPIT timer init
From: Clément Péron @ 2018-05-29 17:04 UTC (permalink / raw)
To: Colin Didier, linux-arm-kernel, devicetree, linux-clk
Cc: Rob Herring, Sascha Hauer, Clément Peron, NXP Linux Team,
Pengutronix Kernel Team, Fabio Estevam, Vladimir Zapolskiy
In-Reply-To: <20180529170436.22711-1-peron.clem@gmail.com>
From: Clément Peron <clement.peron@devialet.com>
i.MX EPIT timer has been removed but not the init function declaration.
Signed-off-by: Clément Peron <clement.peron@devialet.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/mach-imx/common.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c8d68e918b2f..18aae76fa2da 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -38,7 +38,6 @@ void imx21_soc_init(void);
void imx27_soc_init(void);
void imx31_soc_init(void);
void imx35_soc_init(void);
-void epit_timer_init(void __iomem *base, int irq);
int mx21_clocks_init(unsigned long lref, unsigned long fref);
int mx27_clocks_init(unsigned long fref);
int mx31_clocks_init(unsigned long fref);
--
2.17.0
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* [PATCH v3 0/5] Reintroduce i.MX EPIT Timer
From: Clément Péron @ 2018-05-29 17:04 UTC (permalink / raw)
To: Colin Didier, linux-arm-kernel, devicetree, linux-clk
Cc: Rob Herring, Sascha Hauer, Clément Peron, NXP Linux Team,
Pengutronix Kernel Team, Fabio Estevam, Vladimir Zapolskiy
From: Clément Peron <clement.peron@devialet.com>
As suggested in the commit message we have added the device tree support,
proper bindings and we moved the driver into the correct folder.
Moreover we made some changes like use of relaxed IO accesor,
implement sched_clock, delay_timer and reduce the clockevents min_delta.
Changes since v2 (Thanks Fabio Estevam):
- Removed unused "ckil" clock
- Add out_iounmap
- Check and handle if clk_prepare_enable failed
- Fix comment typo
Changes since v1 (Thanks Vladimir Zapolskiy):
- Add OF dependency in Kconfig
- Sort header
- Use BIT macro
- Remove useless comments
- Fix incorrect indent
- Fix memory leak
- Add check and handle possible returned error
Clément Peron (2):
ARM: imx: remove inexistant EPIT timer init
Documentation: DT: add i.MX EPIT timer binding
Colin Didier (3):
clk: imx6: add EPIT clock support
clocksource: add driver for i.MX EPIT timer
ARM: dts: imx6qdl: add missing compatible and clock properties for
EPIT
.../devicetree/bindings/clock/imx6q,epit.txt | 24 ++
arch/arm/boot/dts/imx6qdl.dtsi | 10 +
arch/arm/mach-imx/common.h | 1 -
drivers/clk/imx/clk-imx6q.c | 2 +
drivers/clocksource/Kconfig | 12 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-imx-epit.c | 283 ++++++++++++++++++
include/dt-bindings/clock/imx6qdl-clock.h | 4 +-
8 files changed, 335 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/imx6q,epit.txt
create mode 100644 drivers/clocksource/timer-imx-epit.c
--
2.17.0
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^ permalink raw reply
* Re: [PATCH v1 1/2] dt-binding: hwmon: Add NPCM7xx PWM documentation
From: Guenter Roeck @ 2018-05-29 16:57 UTC (permalink / raw)
To: Tomer Maimon
Cc: robh+dt, mark.rutland, jdelvare, avifishman70, yuenn,
brendanhiggins, venture, joel, devicetree, linux-kernel,
linux-hwmon, openbmc
In-Reply-To: <1527588141-18639-2-git-send-email-tmaimon77@gmail.com>
On Tue, May 29, 2018 at 01:02:20PM +0300, Tomer Maimon wrote:
> Added device tree binding documentation for Nuvoton BMC
> NPCM7xx Pulse Width Modulation (PWM) controller.
>
As mentioned in the other commit, this should be a pwm driver,
not a hwmon driver.
Guenter
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
> .../devicetree/bindings/hwmon/npcm7xx-pwm.txt | 25 ++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/hwmon/npcm7xx-pwm.txt
>
> diff --git a/Documentation/devicetree/bindings/hwmon/npcm7xx-pwm.txt b/Documentation/devicetree/bindings/hwmon/npcm7xx-pwm.txt
> new file mode 100644
> index 000000000000..2d8a7ccdc8cf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/hwmon/npcm7xx-pwm.txt
> @@ -0,0 +1,25 @@
> +Nuvoton NPCM7xx Pulse-width modulation (PWM) controller device driver
> +
> +The NPCM7xx has two identical PWM controller modules,
> +Each module has four PWM controller outputs.
> +NPCM7xx PWM controller module 0 outputs PWM0-3 and NPCM7xx PWM controller
> +module 1 outputs PWM4-7.
> +
> +Required properties:
> +- compatible : "nuvoton,npcm750-pwm" for Poleg NPCM7XX.
> +- reg : Offset and length of the registers set for the device.
> +- clocks : phandle of pwm reference clock.
> +- pinctrl-names : a pinctrl state named "default" must be defined.
> +- pinctrl-0 : phandle referencing pin configuration of the PWM ports.
> +
> +pwm:pwm@f0103000 {
> + compatible = "nuvoton,npcm750-pwm";
> + reg = <0xf0103000 0x50
> + 0xf0104000 0x50>;
> + clocks = <&clk NPCM7XX_CLK_APB3>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm0_pins &pwm1_pins
> + &pwm2_pins &pwm3_pins
> + &pwm4_pins &pwm5_pins
> + &pwm6_pins &pwm7_pins>;
> +};
> --
> 2.14.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-hwmon" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v1 2/2] hwmon: npcm-pwm: add NPCM7xx PWM driver
From: Guenter Roeck @ 2018-05-29 16:56 UTC (permalink / raw)
To: Tomer Maimon
Cc: robh+dt, mark.rutland, jdelvare, avifishman70, yuenn,
brendanhiggins, venture, joel, devicetree, linux-kernel,
linux-hwmon, openbmc, linux-pwm, Thierry Reding
In-Reply-To: <1527588141-18639-3-git-send-email-tmaimon77@gmail.com>
On Tue, May 29, 2018 at 01:02:21PM +0300, Tomer Maimon wrote:
> Add Nuvoton BMC NPCM7xx Pulse Width Modulation (PWM) driver.
>
> The Nuvoton BMC NPCM7xx has two identical PWM controller modules,
> each module has four PWM controller outputs.
>
I don't see it guaranteed that all future NPCM7xx devices will be PWM
controllers, much less that they will be compatible to the chip really
supported here. NPCM750, I presume ? I would suggest name the driver
accordingly.
As a generic pwm driver, not specifically tied to a fan controller,
this driver does not belong into hwmon. It should be added to the pwm
subsystem. Copying the maintainer and mailing list.
If the pwm chip is used to control fans, the existing pwm-fan driver can
then be used to create the necessary mapping from pwm controls to fans.
Guenter
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
> drivers/hwmon/Kconfig | 6 +
> drivers/hwmon/Makefile | 1 +
> drivers/hwmon/npcm7xx-pwm.c | 363 ++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 370 insertions(+)
> create mode 100644 drivers/hwmon/npcm7xx-pwm.c
>
> diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
> index 6ec307c93ece..693ba09cff8e 100644
> --- a/drivers/hwmon/Kconfig
> +++ b/drivers/hwmon/Kconfig
> @@ -1891,6 +1891,12 @@ config SENSORS_XGENE
> If you say yes here you get support for the temperature
> and power sensors for APM X-Gene SoC.
>
> +config SENSORS_NPCM7XX
> + tristate "Nuvoton NPCM7XX PWM driver"
> + help
> + This driver provides support for Nuvoton NPCM7XX PWM
> + controller.
> +
> if ACPI
>
> comment "ACPI drivers"
> diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
> index e7d52a36e6c4..24aad895a3bb 100644
> --- a/drivers/hwmon/Makefile
> +++ b/drivers/hwmon/Makefile
> @@ -174,6 +174,7 @@ obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o
> obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o
> obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o
> obj-$(CONFIG_SENSORS_XGENE) += xgene-hwmon.o
> +obj-$(CONFIG_SENSORS_NPCM7XX) += npcm7xx-pwm.o
>
> obj-$(CONFIG_PMBUS) += pmbus/
>
> diff --git a/drivers/hwmon/npcm7xx-pwm.c b/drivers/hwmon/npcm7xx-pwm.c
> new file mode 100644
> index 000000000000..6122ca82b94d
> --- /dev/null
> +++ b/drivers/hwmon/npcm7xx-pwm.c
> @@ -0,0 +1,363 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2014-2018 Nuvoton Technology corporation.
> +
> +#include <linux/module.h>
> +#include <linux/kernel.h>
> +#include <linux/device.h>
> +#include <linux/clk.h>
> +#include <linux/platform_device.h>
> +#include <linux/hwmon.h>
> +#include <linux/hwmon-sysfs.h>
> +#include <linux/sysfs.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
> +
> +/* NPCM7XX PWM port base address */
> +#define NPCM7XX_PWM_REG_PR 0x0
> +#define NPCM7XX_PWM_REG_CSR 0x4
> +#define NPCM7XX_PWM_REG_CR 0x8
> +#define NPCM7XX_PWM_REG_CNRx(PORT) (0xC + (12 * PORT))
> +#define NPCM7XX_PWM_REG_CMRx(PORT) (0x10 + (12 * PORT))
> +#define NPCM7XX_PWM_REG_PDRx(PORT) (0x14 + (12 * PORT))
> +#define NPCM7XX_PWM_REG_PIER 0x3C
> +#define NPCM7XX_PWM_REG_PIIR 0x40
> +
> +#define NPCM7XX_PWM_CTRL_CH0_MODE_BIT BIT(3)
> +#define NPCM7XX_PWM_CTRL_CH1_MODE_BIT BIT(11)
> +#define NPCM7XX_PWM_CTRL_CH2_MODE_BIT BIT(15)
> +#define NPCM7XX_PWM_CTRL_CH3_MODE_BIT BIT(19)
> +
> +#define NPCM7XX_PWM_CTRL_CH0_INV_BIT BIT(2)
> +#define NPCM7XX_PWM_CTRL_CH1_INV_BIT BIT(10)
> +#define NPCM7XX_PWM_CTRL_CH2_INV_BIT BIT(14)
> +#define NPCM7XX_PWM_CTRL_CH3_INV_BIT BIT(18)
> +
> +#define NPCM7XX_PWM_CTRL_CH0_EN_BIT BIT(0)
> +#define NPCM7XX_PWM_CTRL_CH1_EN_BIT BIT(8)
> +#define NPCM7XX_PWM_CTRL_CH2_EN_BIT BIT(12)
> +#define NPCM7XX_PWM_CTRL_CH3_EN_BIT BIT(16)
> +
> +/* Define the maximum PWM channel number */
> +#define NPCM7XX_PWM_MAX_CHN_NUM 8
> +#define NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE 4
> +#define NPCM7XX_PWM_MAX_MODULES 2
> +
> +/* Define the Counter Register, value = 100 for match 100% */
> +#define NPCM7XX_PWM_COUNTER_DEFALUT_NUM 255
> +#define NPCM7XX_PWM_COMPARATOR_DEFALUT_NUM 127
> +
> +#define NPCM7XX_PWM_COMPARATOR_MAX 255
> +
> +
> +/* default all PWM channels PRESCALE2 = 1 */
> +#define NPCM7XX_PWM_PRESCALE2_DEFALUT_CH0 0x4
> +#define NPCM7XX_PWM_PRESCALE2_DEFALUT_CH1 0x40
> +#define NPCM7XX_PWM_PRESCALE2_DEFALUT_CH2 0x400
> +#define NPCM7XX_PWM_PRESCALE2_DEFALUT_CH3 0x4000
> +
> +#define PWM_OUTPUT_FREQ_25KHZ 25000
> +#define PWN_CNT_DEFAULT 256
> +#define MIN_PRESCALE1 2
> +#define NPCM7XX_PWM_PRESCALE_SHIFT_CH01 8
> +
> +#define NPCM7XX_PWM_PRESCALE2_DEFALUT (NPCM7XX_PWM_PRESCALE2_DEFALUT_CH0 | \
> + NPCM7XX_PWM_PRESCALE2_DEFALUT_CH1 | \
> + NPCM7XX_PWM_PRESCALE2_DEFALUT_CH2 | \
> + NPCM7XX_PWM_PRESCALE2_DEFALUT_CH3)
> +
> +#define NPCM7XX_PWM_CTRL_MODE_DEFALUT (NPCM7XX_PWM_CTRL_CH0_MODE_BIT | \
> + NPCM7XX_PWM_CTRL_CH1_MODE_BIT | \
> + NPCM7XX_PWM_CTRL_CH2_MODE_BIT | \
> + NPCM7XX_PWM_CTRL_CH3_MODE_BIT)
> +
> +#define NPCM7XX_PWM_CTRL_EN_DEFALUT (NPCM7XX_PWM_CTRL_CH0_EN_BIT | \
> + NPCM7XX_PWM_CTRL_CH1_EN_BIT | \
> + NPCM7XX_PWM_CTRL_CH2_EN_BIT | \
> + NPCM7XX_PWM_CTRL_CH3_EN_BIT)
> +
> +struct npcm7xx_pwm_data {
> + unsigned long clk_freq;
> + void __iomem *pwm_base[NPCM7XX_PWM_MAX_MODULES];
> + struct mutex npcm7xx_pwm_lock[NPCM7XX_PWM_MAX_CHN_NUM];
> +};
> +
> +static const struct of_device_id pwm_dt_id[];
> +
> +static int npcm7xx_pwm_config_set(struct npcm7xx_pwm_data *data, int channel,
> + u16 val)
> +{
> + u32 PWMChannel = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
> + u32 n_module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
> + u32 u32TmpBuf = 0, ctrl_en_bit;
> +
> + /*
> + * Config PWM Comparator register for setting duty cycle
> + */
> + if (val < 0 || val > NPCM7XX_PWM_COMPARATOR_MAX)
> + return -EINVAL;
> +
> + /* write new CMR value */
> + iowrite32(val, data->pwm_base[n_module] +
> + NPCM7XX_PWM_REG_CMRx(PWMChannel));
> +
> + u32TmpBuf = ioread32(data->pwm_base[n_module] + NPCM7XX_PWM_REG_CR);
> +
> + switch (PWMChannel) {
> + case 0:
> + ctrl_en_bit = NPCM7XX_PWM_CTRL_CH0_EN_BIT;
> + break;
> + case 1:
> + ctrl_en_bit = NPCM7XX_PWM_CTRL_CH1_EN_BIT;
> + break;
> + case 2:
> + ctrl_en_bit = NPCM7XX_PWM_CTRL_CH2_EN_BIT;
> + break;
> + case 3:
> + ctrl_en_bit = NPCM7XX_PWM_CTRL_CH3_EN_BIT;
> + break;
> + default:
> + return -ENODEV;
> + }
> +
> + if (val == 0)
> + /* Disable PWM */
> + u32TmpBuf &= ~(ctrl_en_bit);
> + else
> + /* Enable PWM */
> + u32TmpBuf |= ctrl_en_bit;
> +
> + mutex_lock(&data->npcm7xx_pwm_lock[n_module]);
> + iowrite32(u32TmpBuf, data->pwm_base[n_module] + NPCM7XX_PWM_REG_CR);
> + mutex_unlock(&data->npcm7xx_pwm_lock[n_module]);
> +
> + return 0;
> +}
> +
> +static int npcm7xx_read_pwm(struct device *dev, u32 attr, int channel,
> + long *val)
> +{
> + struct npcm7xx_pwm_data *data = dev_get_drvdata(dev);
> + u32 PWMChannel = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
> + u32 n_module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
> +
> + if (IS_ERR(data))
> + return PTR_ERR(data);
> +
> + switch (attr) {
> + case hwmon_pwm_input:
> + *val = (long)ioread32(data->pwm_base[n_module] +
> + NPCM7XX_PWM_REG_CMRx(PWMChannel));
> + return 0;
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static int npcm7xx_write_pwm(struct device *dev, u32 attr, int channel,
> + long val)
> +{
> + struct npcm7xx_pwm_data *data = dev_get_drvdata(dev);
> + int err = 0;
> +
> + switch (attr) {
> + case hwmon_pwm_input:
> + err = npcm7xx_pwm_config_set(data, channel, (u16)val);
> + break;
> + default:
> + err = -EOPNOTSUPP;
> + break;
> + }
> +
> + return err;
> +}
> +
> +static umode_t npcm7xx_pwm_is_visible(const void *_data, u32 attr, int channel)
> +{
> + switch (attr) {
> + case hwmon_pwm_input:
> + return 0644;
> + default:
> + return 0;
> + }
> +}
> +
> +static int npcm7xx_read(struct device *dev, enum hwmon_sensor_types type,
> + u32 attr, int channel, long *val)
> +{
> + switch (type) {
> + case hwmon_pwm:
> + return npcm7xx_read_pwm(dev, attr, channel, val);
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static int npcm7xx_write(struct device *dev, enum hwmon_sensor_types type,
> + u32 attr, int channel, long val)
> +{
> + switch (type) {
> + case hwmon_pwm:
> + return npcm7xx_write_pwm(dev, attr, channel, val);
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static umode_t npcm7xx_is_visible(const void *data,
> + enum hwmon_sensor_types type,
> + u32 attr, int channel)
> +{
> + switch (type) {
> + case hwmon_pwm:
> + return npcm7xx_pwm_is_visible(data, attr, channel);
> + default:
> + return 0;
> + }
> +}
> +
> +static const u32 npcm7xx_pwm_config[] = {
> + HWMON_PWM_INPUT,
> + HWMON_PWM_INPUT,
> + HWMON_PWM_INPUT,
> + HWMON_PWM_INPUT,
> + HWMON_PWM_INPUT,
> + HWMON_PWM_INPUT,
> + HWMON_PWM_INPUT,
> + HWMON_PWM_INPUT,
> + 0
> +};
> +
> +static const struct hwmon_channel_info npcm7xx_pwm = {
> + .type = hwmon_pwm,
> + .config = npcm7xx_pwm_config,
> +};
> +
> +static const struct hwmon_channel_info *npcm7xx_info[] = {
> + &npcm7xx_pwm,
> + NULL
> +};
> +
> +static const struct hwmon_ops npcm7xx_hwmon_ops = {
> + .is_visible = npcm7xx_is_visible,
> + .read = npcm7xx_read,
> + .write = npcm7xx_write,
> +};
> +
> +static const struct hwmon_chip_info npcm7xx_chip_info = {
> + .ops = &npcm7xx_hwmon_ops,
> + .info = npcm7xx_info,
> +};
> +
> +static int npcm7xx_pwm_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct npcm7xx_pwm_data *data;
> + struct resource res[NPCM7XX_PWM_MAX_MODULES];
> + struct device *hwmon;
> + struct clk *clk;
> + int m, ch, res_cnt, ret;
> + u32 Prescale_val, output_freq;
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + for (res_cnt = 0; res_cnt < NPCM7XX_PWM_MAX_MODULES ; res_cnt++) {
> + ret = of_address_to_resource(dev->of_node, res_cnt,
> + &res[res_cnt]);
> + if (ret) {
> + pr_err("PWM of_address_to_resource fail ret %d\n",
> + ret);
> + return -EINVAL;
> + }
> +
> + data->pwm_base[res_cnt] =
> + devm_ioremap_resource(dev, &(res[res_cnt]));
> + pr_debug("pwm%d base is 0x%08X, res.start 0x%08X , size 0x%08X\n",
> + res_cnt, (u32)data->pwm_base[res_cnt],
> + res[res_cnt].start, resource_size(&(res[res_cnt])));
> +
> + if (!data->pwm_base[res_cnt]) {
> + pr_err("pwm probe failed: can't read pwm base address for resource %d.\n",
> + res_cnt);
> + return -ENOMEM;
> + }
> +
> + mutex_init(&data->npcm7xx_pwm_lock[res_cnt]);
> + }
> +
> + clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(clk))
> + return -ENODEV;
> +
> + data->clk_freq = clk_get_rate(clk);
> +
> + /* Adjust NPCM7xx PWMs output frequency to ~25Khz */
> + output_freq = data->clk_freq / PWN_CNT_DEFAULT;
> + Prescale_val = DIV_ROUND_CLOSEST(output_freq, PWM_OUTPUT_FREQ_25KHZ);
> +
> + /* If Prescale_val = 0, then the prescale output clock is stopped */
> + if (Prescale_val < MIN_PRESCALE1)
> + Prescale_val = MIN_PRESCALE1;
> + /*
> + * Prescale_val need to decrement in one because in the PWM Prescale
> + * register the Prescale value increment by one
> + */
> + Prescale_val--;
> +
> + /* Setting PWM Prescale Register value register to both modules */
> + Prescale_val |= (Prescale_val << NPCM7XX_PWM_PRESCALE_SHIFT_CH01);
> +
> + for (m = 0; m < NPCM7XX_PWM_MAX_MODULES ; m++) {
> + iowrite32(Prescale_val,
> + data->pwm_base[m] + NPCM7XX_PWM_REG_PR);
> + iowrite32(NPCM7XX_PWM_PRESCALE2_DEFALUT,
> + data->pwm_base[m] + NPCM7XX_PWM_REG_CSR);
> + iowrite32(NPCM7XX_PWM_CTRL_MODE_DEFALUT,
> + data->pwm_base[m] + NPCM7XX_PWM_REG_CR);
> +
> + for (ch = 0; ch < NPCM7XX_PWM_MAX_CHN_NUM; ch++) {
> + iowrite32(NPCM7XX_PWM_COUNTER_DEFALUT_NUM,
> + data->pwm_base[m] + NPCM7XX_PWM_REG_CNRx(ch));
> + iowrite32(NPCM7XX_PWM_COMPARATOR_DEFALUT_NUM,
> + data->pwm_base[m] + NPCM7XX_PWM_REG_CMRx(ch));
> + }
> +
> + iowrite32(NPCM7XX_PWM_CTRL_MODE_DEFALUT |
> + NPCM7XX_PWM_CTRL_EN_DEFALUT,
> + data->pwm_base[m] + NPCM7XX_PWM_REG_CR);
> + }
> +
> + hwmon = devm_hwmon_device_register_with_info(dev, "npcm7xx_pwm", data,
> + &npcm7xx_chip_info, NULL);
> +
> + if (IS_ERR(hwmon)) {
> + pr_err("PWM Driver failed - devm_hwmon_device_register_with_groups failed\n");
> + return PTR_ERR(hwmon);
> + }
> +
> + pr_info("NPCM7XX PWM Driver probed, PWM output Freq %dHz\n",
> + output_freq / ((Prescale_val & 0xf) + 1));
> +
> + return 0;
> +}
> +
> +static const struct of_device_id of_pwm_match_table[] = {
> + { .compatible = "nuvoton,npcm750-pwm", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, of_pwm_match_table);
> +
> +static struct platform_driver npcm7xx_pwm_driver = {
> + .probe = npcm7xx_pwm_probe,
> + .driver = {
> + .name = "npcm7xx_pwm",
> + .of_match_table = of_pwm_match_table,
> + },
> +};
> +
> +module_platform_driver(npcm7xx_pwm_driver);
> +
> +MODULE_DESCRIPTION("Nuvoton NPCM7XX PWM Driver");
> +MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
> +MODULE_LICENSE("GPL v2");
> --
> 2.14.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-hwmon" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
From: Geert Uytterhoeven @ 2018-05-29 16:42 UTC (permalink / raw)
To: Simon Horman
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Sergei Shtylyov, Catalin Marinas, Will Deacon,
Linux-Renesas, Rob Herring, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20180529130504.lpkpgads7lfomois@verge.net.au>
Hi Simon,
On Tue, May 29, 2018 at 3:05 PM, Simon Horman <horms@verge.net.au> wrote:
> On Mon, May 28, 2018 at 11:13:08PM +0300, Sergei Shtylyov wrote:
>> Define the generic R8A77980 parts of the I2C[0-5] device node.
>>
>> Based on the original (and large) patch by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>> + i2c3: i2c@e66d0000 {
>> + compatible = "renesas,i2c-r8a77980",
>> + "renesas,rcar-gen3-i2c";
>> + reg = <0 0xe66d0000 0 0x40>;
>> + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 928>;
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 928>;
>> + dmas = <&dmac1 0x97>, <&dmac1 0x96>,
>> + <&dmac2 0x97>, <&dmac2 0x96>;
>> + dma-names = "tx", "rx", "tx", "rx";
>> + i2c-scl-internal-delay-ns = <6>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + status = "disabled";
>> + };
>
> DMA for i2c3 and i2c4 seems unclear in v0.80 and v1.00 of the User's Manual.
> Although what is described here does match v0.55E of the User's Manual.
> Have you been able to confirm what is correct here?
Given they bothered adding rows to the table, I assume they just forgot to
add checkmarks in the V3H column.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
From: Geert Uytterhoeven @ 2018-05-29 16:41 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Catalin Marinas, Will Deacon, Rob Herring,
Linux-Renesas, Simon Horman, linux-arm-kernel@lists.infradead.org
In-Reply-To: <3675b19f-b800-172f-9472-c47a37760fa9@cogentembedded.com>
On Mon, May 28, 2018 at 10:13 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Define the generic R8A77980 parts of the I2C[0-5] device node.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH] i2c: rcar: document R8A77980 bindings
From: Geert Uytterhoeven @ 2018-05-29 16:34 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, Linux I2C,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Mark Rutland, Linux-Renesas
In-Reply-To: <95b945f7-1e6c-39f1-e101-06ed748ccec2@cogentembedded.com>
On Mon, May 28, 2018 at 9:39 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> R-Car V3H (R8A77980) SoC also has the R-Car gen3 compatible I2C controller,
> so document the SoC specific bindings.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> The patch is against Wolfram Sang's 'linux.git' repo's 'i2c/for-next' branch
> but I wouldn't mind if it was applied to the 'i2c/for-current' branch. :-)
Who cares? A trivial DT binding update is not critical.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v2 5/5] arm64: dts: renesas: r8a7795: add ccree binding
From: Simon Horman @ 2018-05-29 16:19 UTC (permalink / raw)
To: Gilad Ben-Yossef
Cc: Magnus Damm, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
Herbert Xu, David S. Miller, Ofir Drang, linux-renesas-soc,
devicetree, linux-arm-kernel, linux-kernel, linux-clk,
linux-crypto
In-Reply-To: <1527171551-21979-6-git-send-email-gilad@benyossef.com>
On Thu, May 24, 2018 at 03:19:10PM +0100, Gilad Ben-Yossef wrote:
> Add bindings for CryptoCell instance in the SoC.
>
> Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
In so far as I can review the details of this (which is not much) this
looks fine to me. I am, however, a little unclear in when it should be
accepted.
> ---
> arch/arm64/boot/dts/renesas/r8a7795.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index d842940..3ac75db 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -528,6 +528,15 @@
> status = "disabled";
> };
>
> + arm_cc630p: crypto@e6601000 {
> + compatible = "arm,cryptocell-630p-ree";
> + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0xe6601000 0 0x1000>;
> + clocks = <&cpg CPG_MOD 229>;
> + resets = <&cpg 229>;
> + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
> + };
> +
> i2c3: i2c@e66d0000 {
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH v2 3/5] crypto: ccree: silence debug prints
From: Simon Horman @ 2018-05-29 16:13 UTC (permalink / raw)
To: Gilad Ben-Yossef
Cc: Magnus Damm, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
Herbert Xu, David S. Miller, Ofir Drang, linux-renesas-soc,
devicetree, linux-arm-kernel, linux-kernel, linux-clk,
linux-crypto
In-Reply-To: <1527171551-21979-4-git-send-email-gilad@benyossef.com>
On Thu, May 24, 2018 at 03:19:08PM +0100, Gilad Ben-Yossef wrote:
> The cache parameter register configuration was being too verbose.
> Use dev_dbg() to only provide the information if needed.
>
> Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply
* Re: [PATCH v2 2/5] crypto: ccree: better clock handling
From: Simon Horman @ 2018-05-29 16:13 UTC (permalink / raw)
To: Gilad Ben-Yossef
Cc: Magnus Damm, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
Herbert Xu, David S. Miller, Ofir Drang, linux-renesas-soc,
devicetree, linux-arm-kernel, linux-kernel, linux-clk,
linux-crypto
In-Reply-To: <1527171551-21979-3-git-send-email-gilad@benyossef.com>
On Thu, May 24, 2018 at 03:19:07PM +0100, Gilad Ben-Yossef wrote:
> Use managed clock handling, differentiate between no clock (possibly OK)
> and clock init failure (never OK) and correctly handle clock detection
> being deferred.
>
> Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> drivers/crypto/ccree/cc_driver.c | 20 +++++++++++++++++++-
> 1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/crypto/ccree/cc_driver.c b/drivers/crypto/ccree/cc_driver.c
> index 6f93ce7..b266657 100644
> --- a/drivers/crypto/ccree/cc_driver.c
> +++ b/drivers/crypto/ccree/cc_driver.c
> @@ -190,6 +190,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
> u64 dma_mask;
> const struct cc_hw_data *hw_rev;
> const struct of_device_id *dev_id;
> + struct clk *clk;
> int rc = 0;
>
> new_drvdata = devm_kzalloc(dev, sizeof(*new_drvdata), GFP_KERNEL);
> @@ -219,7 +220,24 @@ static int init_cc_resources(struct platform_device *plat_dev)
> platform_set_drvdata(plat_dev, new_drvdata);
> new_drvdata->plat_dev = plat_dev;
>
> - new_drvdata->clk = of_clk_get(np, 0);
> + clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(clk))
> + switch (PTR_ERR(clk)) {
> + /* Clock is optional so this might be fine */
> + case -ENOENT:
> + break;
> +
> + /* Clock not available, let's try again soon */
> + case -EPROBE_DEFER:
> + return -EPROBE_DEFER;
> +
> + default:
> + dev_err(dev, "Error getting clock: %ld\n",
> + PTR_ERR(clk));
> + return PTR_ERR(clk);
> + }
> + new_drvdata->clk = clk;
> +
> new_drvdata->coherent = of_dma_is_coherent(np);
>
> /* Get device resources */
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH v2 1/5] crypto: ccree: correct host regs offset
From: Simon Horman @ 2018-05-29 16:12 UTC (permalink / raw)
To: Gilad Ben-Yossef
Cc: Magnus Damm, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
Herbert Xu, David S. Miller, Ofir Drang, stable,
linux-renesas-soc, devicetree, linux-arm-kernel, linux-kernel,
linux-clk, linux-crypto
In-Reply-To: <1527171551-21979-2-git-send-email-gilad@benyossef.com>
On Thu, May 24, 2018 at 03:19:06PM +0100, Gilad Ben-Yossef wrote:
> The product signature and HW revision register have different offset on the
> older HW revisions.
> This fixes the problem of the driver failing sanity check on silicon
> despite working on the FPGA emulation systems.
>
> Fixes: 27b3b22dd98c ("crypto: ccree - add support for older HW revs")
Did the above introduce a regression that is fixed by this patch
or did it add a feature that only works with this patch?
In the case of the latter I would drop the Fixes tag,
but I don't feel strongly about it.
> Cc: stable@vger.kernel.org
> Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Minor not below not withstanding,
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> drivers/crypto/ccree/cc_debugfs.c | 7 +++++--
> drivers/crypto/ccree/cc_driver.c | 8 ++++++--
> drivers/crypto/ccree/cc_driver.h | 2 ++
> drivers/crypto/ccree/cc_host_regs.h | 6 ++++--
> 4 files changed, 17 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/crypto/ccree/cc_debugfs.c b/drivers/crypto/ccree/cc_debugfs.c
> index 08f8db4..5ca184e 100644
> --- a/drivers/crypto/ccree/cc_debugfs.c
> +++ b/drivers/crypto/ccree/cc_debugfs.c
> @@ -26,7 +26,8 @@ struct cc_debugfs_ctx {
> static struct dentry *cc_debugfs_dir;
>
> static struct debugfs_reg32 debug_regs[] = {
> - CC_DEBUG_REG(HOST_SIGNATURE),
> + { .name = "SIGNATURE" }, /* Must be 0th */
> + { .name = "VERSION" }, /* Must be 1st */
> CC_DEBUG_REG(HOST_IRR),
> CC_DEBUG_REG(HOST_POWER_DOWN_EN),
> CC_DEBUG_REG(AXIM_MON_ERR),
> @@ -34,7 +35,6 @@ static struct debugfs_reg32 debug_regs[] = {
> CC_DEBUG_REG(HOST_IMR),
> CC_DEBUG_REG(AXIM_CFG),
> CC_DEBUG_REG(AXIM_CACHE_PARAMS),
> - CC_DEBUG_REG(HOST_VERSION),
> CC_DEBUG_REG(GPR_HOST),
> CC_DEBUG_REG(AXIM_MON_COMP),
> };
> @@ -58,6 +58,9 @@ int cc_debugfs_init(struct cc_drvdata *drvdata)
> struct debugfs_regset32 *regset;
> struct dentry *file;
>
> + debug_regs[0].offset = drvdata->sig_offset;
> + debug_regs[1].offset = drvdata->ver_offset;
> +
> ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
> if (!ctx)
> return -ENOMEM;
> diff --git a/drivers/crypto/ccree/cc_driver.c b/drivers/crypto/ccree/cc_driver.c
> index 89ce013..6f93ce7 100644
> --- a/drivers/crypto/ccree/cc_driver.c
> +++ b/drivers/crypto/ccree/cc_driver.c
> @@ -207,9 +207,13 @@ static int init_cc_resources(struct platform_device *plat_dev)
> if (hw_rev->rev >= CC_HW_REV_712) {
> new_drvdata->hash_len_sz = HASH_LEN_SIZE_712;
> new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP);
> + new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_712);
> + new_drvdata->ver_offset = CC_REG(HOST_VERSION_712);
> } else {
> new_drvdata->hash_len_sz = HASH_LEN_SIZE_630;
> new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP8);
> + new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_630);
> + new_drvdata->ver_offset = CC_REG(HOST_VERSION_630);
> }
>
> platform_set_drvdata(plat_dev, new_drvdata);
> @@ -276,7 +280,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
> }
>
> /* Verify correct mapping */
> - signature_val = cc_ioread(new_drvdata, CC_REG(HOST_SIGNATURE));
> + signature_val = cc_ioread(new_drvdata, new_drvdata->sig_offset);
> if (signature_val != hw_rev->sig) {
> dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n",
> signature_val, hw_rev->sig);
> @@ -287,7 +291,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
>
> /* Display HW versions */
> dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X, Driver version %s\n",
> - hw_rev->name, cc_ioread(new_drvdata, CC_REG(HOST_VERSION)),
> + hw_rev->name, cc_ioread(new_drvdata, new_drvdata->ver_offset),
> DRV_MODULE_VERSION);
>
> rc = init_cc_regs(new_drvdata, true);
> diff --git a/drivers/crypto/ccree/cc_driver.h b/drivers/crypto/ccree/cc_driver.h
> index 2048fde..95f82b2 100644
> --- a/drivers/crypto/ccree/cc_driver.h
> +++ b/drivers/crypto/ccree/cc_driver.h
> @@ -129,6 +129,8 @@ struct cc_drvdata {
This patch doesn't make things (much) worse
but struct cc_drvdata has a rather incomplete kdoc.
> enum cc_hw_rev hw_rev;
> u32 hash_len_sz;
> u32 axim_mon_offset;
> + u32 sig_offset;
> + u32 ver_offset;
> };
>
> struct cc_crypto_alg {
> diff --git a/drivers/crypto/ccree/cc_host_regs.h b/drivers/crypto/ccree/cc_host_regs.h
> index f510018..616b2e1 100644
> --- a/drivers/crypto/ccree/cc_host_regs.h
> +++ b/drivers/crypto/ccree/cc_host_regs.h
> @@ -45,7 +45,8 @@
> #define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE 0x1UL
> #define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT 0x17UL
> #define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE 0x1UL
> -#define CC_HOST_SIGNATURE_REG_OFFSET 0xA24UL
> +#define CC_HOST_SIGNATURE_712_REG_OFFSET 0xA24UL
> +#define CC_HOST_SIGNATURE_630_REG_OFFSET 0xAC8UL
> #define CC_HOST_SIGNATURE_VALUE_BIT_SHIFT 0x0UL
> #define CC_HOST_SIGNATURE_VALUE_BIT_SIZE 0x20UL
> #define CC_HOST_BOOT_REG_OFFSET 0xA28UL
> @@ -105,7 +106,8 @@
> #define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE 0x1UL
> #define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT 0x1EUL
> #define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE 0x1UL
> -#define CC_HOST_VERSION_REG_OFFSET 0xA40UL
> +#define CC_HOST_VERSION_712_REG_OFFSET 0xA40UL
> +#define CC_HOST_VERSION_630_REG_OFFSET 0xAD8UL
> #define CC_HOST_VERSION_VALUE_BIT_SHIFT 0x0UL
> #define CC_HOST_VERSION_VALUE_BIT_SIZE 0x20UL
> #define CC_HOST_KFDE0_VALID_REG_OFFSET 0xA60UL
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH RESEND] display: panel: Add KOE tx14d24vm1bpa display support (320x240)
From: Thierry Reding @ 2018-05-29 16:12 UTC (permalink / raw)
To: Lukasz Majewski
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Rob Herring
In-Reply-To: <20180529173338.5ec631ee@jawa>
[-- Attachment #1.1: Type: text/plain, Size: 1588 bytes --]
On Tue, May 29, 2018 at 05:33:38PM +0200, Lukasz Majewski wrote:
> Hi Thierry,
>
> > On Tue, May 29, 2018 at 05:01:48PM +0200, Lukasz Majewski wrote:
> > > Hi Thierry,
> > >
> > > > On Mon, May 28, 2018 at 09:55:19AM +0200, Lukasz Majewski wrote:
> > > > > Hi,
> > > > >
> > > > > > Hi Thierry,
> > > > > >
> > > > > > > This commit adds support for KOE's 5.7" display.
> > > > > > >
> > > > > >
> > > > > > Thierry, shall I perform some more work on this code, or is it
> > > > > > eligible for applying to your tree?
> > > > >
> > > > > Gentle ping. If Thierry is overworked - maybe there is a
> > > > > co-maintainer so he/she could apply this patch?
> > > >
> > > > Please use the proper prefix for the commit subject to increase
> > > > the chances of this being noticed.
> > >
> > > Ok. Is there any list of prefixes in the kernel repository, so I
> > > could look for them (like get_prefix.py - similar to get_maintainer
> > > script)?
> >
> > I don't think there is. A good rule of thumb that I use is to go over
> > the git log for the last couple of commits and see if there's a clear
> > pattern. This doesn't work for every subsystem, but drm/panel is very
> > consistent in this regard, on purpose.
>
> I see.
>
> Is the DRM/panel tree hosted on git.kernel.org?
>
> The tree maintained by you there seems to be:
> kernel/git/thierry.reding/linux-pwm.git
>
> IIRC it is hosted elsewhere. Am I right?
drm/panel is part of drm-misc:
https://cgit.freedesktop.org/drm/drm-misc/
Thierry
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dri-devel mailing list
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^ permalink raw reply
* Re: [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
From: Sergei Shtylyov @ 2018-05-29 16:04 UTC (permalink / raw)
To: Simon Horman
Cc: Mark Rutland, devicetree, Magnus Damm, Catalin Marinas,
Will Deacon, linux-renesas-soc, Rob Herring,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20180529130504.lpkpgads7lfomois@verge.net.au>
On 05/29/2018 04:05 PM, Simon Horman wrote:
>> Define the generic R8A77980 parts of the I2C[0-5] device node.
>>
>> Based on the original (and large) patch by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 111 ++++++++++++++++++++++++++++++
>> 1 file changed, 111 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> ===================================================================
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
[...]
>> @@ -135,6 +144,108 @@
[...]
>> + i2c3: i2c@e66d0000 {
>> + compatible = "renesas,i2c-r8a77980",
>> + "renesas,rcar-gen3-i2c";
>> + reg = <0 0xe66d0000 0 0x40>;
>> + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 928>;
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 928>;
>> + dmas = <&dmac1 0x97>, <&dmac1 0x96>,
>> + <&dmac2 0x97>, <&dmac2 0x96>;
>> + dma-names = "tx", "rx", "tx", "rx";
>> + i2c-scl-internal-delay-ns = <6>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + status = "disabled";
>> + };
>
> DMA for i2c3 and i2c4 seems unclear in v0.80 and v1.00 of the User's Manual.
> Although what is described here does match v0.55E of the User's Manual.
Hm, looking at all these manuals, I'm not even seeing V3H I2C3/4 having DMA
in v0.55E!
> Have you been able to confirm what is correct here?
No. Probably need to drop I2C3/4 DMA altogether...
> Other than that this patch looks fine to me.
TY!
[...]
MBR, Sergei
^ permalink raw reply
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