* [PATCH v2] thermal: qcom: tsens: Allow number of sensors to come from DT
From: Bjorn Andersson @ 2018-06-02 19:32 UTC (permalink / raw)
To: Zhang Rui, Eduardo Valentin
Cc: Rob Herring, Mark Rutland, Amit Kucheria, linux-pm, devicetree,
linux-kernel, linux-arm-msm
For platforms that has multiple copies of the TSENS hardware block it's
convenient to specify the number of sensors per block in DeviceTree.
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org> [binding]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v1:
- Added comment as suggested by Amit
- Picked up Amit and Rob's R-b
.../devicetree/bindings/thermal/qcom-tsens.txt | 1 +
drivers/thermal/qcom/tsens.c | 13 ++++++++++---
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt
index 292ed89d900b..06195e8f35e2 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt
+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt
@@ -8,6 +8,7 @@ Required properties:
- reg: Address range of the thermal registers
- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description.
+- #qcom,sensors: Number of sensors in tsens block
- Refer to Documentation/devicetree/bindings/nvmem/nvmem.txt to know how to specify
nvmem cells
diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c
index 3f9fe6aa51cc..b212bebcfc36 100644
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -116,6 +116,7 @@ static int tsens_probe(struct platform_device *pdev)
struct tsens_device *tmdev;
const struct tsens_data *data;
const struct of_device_id *id;
+ u32 num_sensors;
if (pdev->dev.of_node)
dev = &pdev->dev;
@@ -130,18 +131,24 @@ static int tsens_probe(struct platform_device *pdev)
else
data = &data_8960;
- if (data->num_sensors <= 0) {
+ num_sensors = data->num_sensors;
+
+ /* Override driver provided num_sensors, if specified in DT */
+ if (np)
+ of_property_read_u32(np, "#qcom,sensors", &num_sensors);
+
+ if (num_sensors <= 0) {
dev_err(dev, "invalid number of sensors\n");
return -EINVAL;
}
tmdev = devm_kzalloc(dev, sizeof(*tmdev) +
- data->num_sensors * sizeof(*s), GFP_KERNEL);
+ num_sensors * sizeof(*s), GFP_KERNEL);
if (!tmdev)
return -ENOMEM;
tmdev->dev = dev;
- tmdev->num_sensors = data->num_sensors;
+ tmdev->num_sensors = num_sensors;
tmdev->ops = data->ops;
for (i = 0; i < tmdev->num_sensors; i++) {
if (data->hw_ids)
--
2.17.0
^ permalink raw reply related
* Re: [PATCH v2] thermal: qcom: tsens: Allow number of sensors to come from DT
From: Bjorn Andersson @ 2018-06-02 19:38 UTC (permalink / raw)
To: Zhang Rui, Eduardo Valentin
Cc: Rob Herring, Mark Rutland, Amit Kucheria, linux-pm, devicetree,
linux-kernel, linux-arm-msm
In-Reply-To: <20180602193211.25731-1-bjorn.andersson@linaro.org>
On Sat 02 Jun 12:32 PDT 2018, Bjorn Andersson wrote:
> For platforms that has multiple copies of the TSENS hardware block it's
> convenient to specify the number of sensors per block in DeviceTree.
>
> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
> Reviewed-by: Rob Herring <robh@kernel.org> [binding]
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Please ignore, after sending this I saw that Eduardo picked up v1
yesterday.
Thanks Eduardo,
Bjorn
> ---
>
> Changes since v1:
> - Added comment as suggested by Amit
> - Picked up Amit and Rob's R-b
>
> .../devicetree/bindings/thermal/qcom-tsens.txt | 1 +
> drivers/thermal/qcom/tsens.c | 13 ++++++++++---
> 2 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt
> index 292ed89d900b..06195e8f35e2 100644
> --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt
> +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt
> @@ -8,6 +8,7 @@ Required properties:
>
> - reg: Address range of the thermal registers
> - #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description.
> +- #qcom,sensors: Number of sensors in tsens block
> - Refer to Documentation/devicetree/bindings/nvmem/nvmem.txt to know how to specify
> nvmem cells
>
> diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c
> index 3f9fe6aa51cc..b212bebcfc36 100644
> --- a/drivers/thermal/qcom/tsens.c
> +++ b/drivers/thermal/qcom/tsens.c
> @@ -116,6 +116,7 @@ static int tsens_probe(struct platform_device *pdev)
> struct tsens_device *tmdev;
> const struct tsens_data *data;
> const struct of_device_id *id;
> + u32 num_sensors;
>
> if (pdev->dev.of_node)
> dev = &pdev->dev;
> @@ -130,18 +131,24 @@ static int tsens_probe(struct platform_device *pdev)
> else
> data = &data_8960;
>
> - if (data->num_sensors <= 0) {
> + num_sensors = data->num_sensors;
> +
> + /* Override driver provided num_sensors, if specified in DT */
> + if (np)
> + of_property_read_u32(np, "#qcom,sensors", &num_sensors);
> +
> + if (num_sensors <= 0) {
> dev_err(dev, "invalid number of sensors\n");
> return -EINVAL;
> }
>
> tmdev = devm_kzalloc(dev, sizeof(*tmdev) +
> - data->num_sensors * sizeof(*s), GFP_KERNEL);
> + num_sensors * sizeof(*s), GFP_KERNEL);
> if (!tmdev)
> return -ENOMEM;
>
> tmdev->dev = dev;
> - tmdev->num_sensors = data->num_sensors;
> + tmdev->num_sensors = num_sensors;
> tmdev->ops = data->ops;
> for (i = 0; i < tmdev->num_sensors; i++) {
> if (data->hw_ids)
> --
> 2.17.0
>
^ permalink raw reply
* Re: [PATCH] ARM: dts: imx51-zii-rdu1: add rave-sp subdevices
From: Chris Healy @ 2018-06-02 19:46 UTC (permalink / raw)
To: Nikita Yushchenko
Cc: Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Mark Rutland, Lucas Stach, Andrey Smirnov,
Marco Franchi, linux ARM, devicetree, linux-kernel
In-Reply-To: <20180517191923.16212-1-nikita.yoush@cogentembedded.com>
On Thu, May 17, 2018 at 12:19 PM, Nikita Yushchenko
<nikita.yoush@cogentembedded.com> wrote:
> This adds rave-sp powerbutton and backlight devices to RDU1 device tree.
>
> Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
> ---
Tested-by: Chris Healy <cphealy@gmail.com>
Tested on an 8.9" RDU1.
^ permalink raw reply
* RE: [PATCH 1/2] clk: imx6ul: add GPIO clock gates
From: Anson Huang @ 2018-06-03 1:36 UTC (permalink / raw)
To: Stephen Boyd, Stefan Wahren, Fabio Estevam, kernel@pengutronix.de,
mark.rutland@arm.com, matteo.lisi@engicam.com,
michael@amarulasolutions.com, mturquette@baylibre.com,
robh+dt@kernel.org, shawnguo@kernel.org
Cc: linux-clk@vger.kernel.org, dl-linux-imx,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <152792036327.225090.14543251343485084840@swboyd.mtv.corp.google.com>
Hi, Stephen
Anson Huang
Best Regards!
> -----Original Message-----
> From: Stephen Boyd [mailto:sboyd@kernel.org]
> Sent: Saturday, June 2, 2018 2:19 PM
> To: Anson Huang <anson.huang@nxp.com>; Stefan Wahren
> <stefan.wahren@i2se.com>; Fabio Estevam <fabio.estevam@nxp.com>;
> kernel@pengutronix.de; mark.rutland@arm.com; matteo.lisi@engicam.com;
> michael@amarulasolutions.com; mturquette@baylibre.com;
> robh+dt@kernel.org; shawnguo@kernel.org
> Cc: linux-clk@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH 1/2] clk: imx6ul: add GPIO clock gates
>
> Quoting Stefan Wahren (2018-05-22 05:25:35)
> > > +++ b/include/dt-bindings/clock/imx6ul-clock.h
> > > @@ -242,20 +242,25 @@
> > > #define IMX6UL_CLK_CKO2_PODF 229
> > > #define IMX6UL_CLK_CKO2 230
> > > #define IMX6UL_CLK_CKO 231
> > > +#define IMX6UL_CLK_GPIO1 232
> > > +#define IMX6UL_CLK_GPIO2 233
> > > +#define IMX6UL_CLK_GPIO3 234
> > > +#define IMX6UL_CLK_GPIO4 235
> > > +#define IMX6UL_CLK_GPIO5 236
> >
> > this change looks like a breakage of devicetree ABI. You are changing the
> mean of the existing clock IDs on i.MX6ULL, which probably regress the
> combination of older DTBs with newer kernel.
> >
>
> Agreed. Why can't we just tack on more numbers at the end?
Ah, yes, I saw 6ULL are at the end of 6UL, so added them in 6UL, but did NOT consider the old dtb support.
Will send out a V2 patch to fix it, and I saw Fabio also sent a patch to fix the clko1/2 definition, I will do the
V2 patch based on his patch.
Anson.
>
> > >
> > > /* For i.MX6ULL */
> > > -#define IMX6ULL_CLK_ESAI_PRED 232
^ permalink raw reply
* [PATCH V2 1/2] clk: imx6ul: add GPIO clock gates
From: Anson Huang @ 2018-06-03 1:44 UTC (permalink / raw)
To: shawnguo, kernel, fabio.estevam, robh+dt, mark.rutland,
mturquette, sboyd, michael, matteo.lisi
Cc: Linux-imx, linux-arm-kernel, devicetree, linux-kernel, linux-clk
i.MX6UL has GPIO clock gates in CCM CCGR,
add them into clock tree for clock management.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
changes since V1:
Move IMX6UL_CLK_GPIOx definition to end of clock table;
Based on Fabio's patch "[v2] dt-bindings: clock: imx6ul: Do not change the clock definition order".
drivers/clk/imx/clk-imx6ul.c | 5 +++++
include/dt-bindings/clock/imx6ul-clock.h | 8 +++++++-
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index ba563ba..3ea2d97 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -360,6 +360,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28);
if (clk_on_imx6ull())
clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x80, 18);
+ clks[IMX6UL_CLK_GPIO2] = imx_clk_gate2("gpio2", "ipg", base + 0x68, 30);
/* CCGR1 */
clks[IMX6UL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
@@ -376,6 +377,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clks[IMX6UL_CLK_GPT1_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22);
clks[IMX6UL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24);
clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serial", "uart_podf", base + 0x6c, 24);
+ clks[IMX6UL_CLK_GPIO1] = imx_clk_gate2("gpio1", "ipg", base + 0x6c, 26);
+ clks[IMX6UL_CLK_GPIO5] = imx_clk_gate2("gpio5", "ipg", base + 0x6c, 30);
/* CCGR2 */
if (clk_on_imx6ull()) {
@@ -389,6 +392,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clks[IMX6UL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
clks[IMX6UL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
clks[IMX6UL_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif_podf", base + 0x70, 14);
+ clks[IMX6UL_CLK_GPIO3] = imx_clk_gate2("gpio3", "ipg", base + 0x70, 26);
clks[IMX6UL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28);
clks[IMX6UL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30);
@@ -405,6 +409,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clks[IMX6UL_CLK_UART6_IPG] = imx_clk_gate2("uart6_ipg", "ipg", base + 0x74, 6);
clks[IMX6UL_CLK_UART6_SERIAL] = imx_clk_gate2("uart6_serial", "uart_podf", base + 0x74, 6);
clks[IMX6UL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10);
+ clks[IMX6UL_CLK_GPIO4] = imx_clk_gate2("gpio4", "ipg", base + 0x74, 12);
clks[IMX6UL_CLK_QSPI] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14);
clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16);
clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20);
diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
index 0aa1d9c..f8e0476 100644
--- a/include/dt-bindings/clock/imx6ul-clock.h
+++ b/include/dt-bindings/clock/imx6ul-clock.h
@@ -254,6 +254,12 @@
#define IMX6UL_CLK_CKO2_PODF 241
#define IMX6UL_CLK_CKO2 242
#define IMX6UL_CLK_CKO 243
-#define IMX6UL_CLK_END 244
+#define IMX6UL_CLK_GPIO1 244
+#define IMX6UL_CLK_GPIO2 245
+#define IMX6UL_CLK_GPIO3 246
+#define IMX6UL_CLK_GPIO4 247
+#define IMX6UL_CLK_GPIO5 248
+
+#define IMX6UL_CLK_END 249
#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
--
2.7.4
^ permalink raw reply related
* [PATCH V2 2/2] ARM: dts: imx6ul: add GPIO clocks
From: Anson Huang @ 2018-06-03 1:44 UTC (permalink / raw)
To: shawnguo, kernel, fabio.estevam, robh+dt, mark.rutland,
mturquette, sboyd, michael, matteo.lisi
Cc: Linux-imx, linux-arm-kernel, devicetree, linux-kernel, linux-clk
In-Reply-To: <1527990245-13619-1-git-send-email-Anson.Huang@nxp.com>
i.MX6UL has GPIO clock gates in CCM CCGR, add
clock property for GPIO driver to make sure all
GPIO banks work as expected.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
no changes since V1.
arch/arm/boot/dts/imx6ul.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 1241972..405e068 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -437,6 +437,7 @@
reg = <0x0209c000 0x4000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -450,6 +451,7 @@
reg = <0x020a0000 0x4000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -462,6 +464,7 @@
reg = <0x020a4000 0x4000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -474,6 +477,7 @@
reg = <0x020a8000 0x4000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -486,6 +490,7 @@
reg = <0x020ac000 0x4000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO5>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
--
2.7.4
^ permalink raw reply related
* Re: [PATCH V2 1/2] clk: imx6ul: add GPIO clock gates
From: Fabio Estevam @ 2018-06-03 2:06 UTC (permalink / raw)
To: Anson Huang
Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Rob Herring, Mark Rutland,
Michael Turquette, Stephen Boyd, Michael Trimarchi, Matteo Lisi,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-clk, NXP Linux Team,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-kernel
In-Reply-To: <1527990245-13619-1-git-send-email-Anson.Huang@nxp.com>
On Sat, Jun 2, 2018 at 10:44 PM, Anson Huang <Anson.Huang@nxp.com> wrote:
> i.MX6UL has GPIO clock gates in CCM CCGR,
> add them into clock tree for clock management.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* Re: [PATCH V2 2/2] ARM: dts: imx6ul: add GPIO clocks
From: Fabio Estevam @ 2018-06-03 2:06 UTC (permalink / raw)
To: Anson Huang
Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Rob Herring, Mark Rutland,
Michael Turquette, Stephen Boyd, Michael Trimarchi, Matteo Lisi,
NXP Linux Team,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel, linux-clk
In-Reply-To: <1527990245-13619-2-git-send-email-Anson.Huang@nxp.com>
On Sat, Jun 2, 2018 at 10:44 PM, Anson Huang <Anson.Huang@nxp.com> wrote:
> i.MX6UL has GPIO clock gates in CCM CCGR, add
> clock property for GPIO driver to make sure all
> GPIO banks work as expected.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* 答复: [PATCH v10 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC
From: liwei (CM) @ 2018-06-03 7:12 UTC (permalink / raw)
To: liwei (CM), robh+dt@kernel.org, mark.rutland@arm.com,
catalin.marinas@arm.com, will.deacon@arm.com,
vinholikatti@gmail.com, jejb@linux.vnet.ibm.com,
martin.petersen@oracle.com, khilman@baylibre.com, arnd@arndb.de,
gregory.clement@free-electrons.com,
thomas.petazzoni@free-electrons.com,
yamada.masahiro@socionext.com, riku.voipio@linaro.org,
treding@nvidia.com, krzk@kernel.org, devicetree@vger.kernel.org,
linux-ke
Cc: guodong.xu@linaro.org, Chenfeng (puck), Gengjianfeng, zangleigang,
Fengbaopeng (kevin, Kirin Solution Dept), john.stultz@linaro.org
In-Reply-To: <20180525091712.37227-1-liwei213@huawei.com>
Hi, all
Sorry to bother you. Anybody else have any comments?
Hi, Philippe
This patch has been submitted for a long time, can it be merged?
Reviews and tests for previous versions of the patch are as follows:
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Riku Voipio <riku.voipio@linaro.org>
Thank you all for your attention and look forward to your reply.
Thanks!
-----邮件原件-----
发件人: liwei (CM)
发送时间: 2018年5月25日 17:17
收件人: robh+dt@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com; will.deacon@arm.com; vinholikatti@gmail.com; jejb@linux.vnet.ibm.com; martin.petersen@oracle.com; khilman@baylibre.com; arnd@arndb.de; gregory.clement@free-electrons.com; thomas.petazzoni@free-electrons.com; yamada.masahiro@socionext.com; riku.voipio@linaro.org; treding@nvidia.com; krzk@kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-scsi@vger.kernel.org
抄送: zangleigang; Gengjianfeng; guodong.xu@linaro.org; Chenfeng (puck); john.stultz@linaro.org; liwei (CM); Fengbaopeng (kevin, Kirin Solution Dept)
主题: [PATCH v10 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC
This patchset adds driver support for UFS for Hi3660 SoC. It is verified on HiKey960 board.
Li Wei (5):
scsi: ufs: add Hisilicon ufs driver code
dt-bindings: scsi: ufs: add document for hisi-ufs
arm64: dts: add ufs dts node
arm64: defconfig: enable configs for Hisilicon ufs
arm64: defconfig: enable f2fs and squashfs
Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 41 ++
.../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 10 +-
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 18 +
arch/arm64/configs/defconfig | 11 +
drivers/scsi/ufs/Kconfig | 9 +
drivers/scsi/ufs/Makefile | 1 +
drivers/scsi/ufs/ufs-hisi.c | 619 +++++++++++++++++++++
drivers/scsi/ufs/ufs-hisi.h | 115 ++++
8 files changed, 821 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-hisi.txt
create mode 100644 drivers/scsi/ufs/ufs-hisi.c
create mode 100644 drivers/scsi/ufs/ufs-hisi.h
Major changes in v10:
- solve review comments from Rob Herring.
*Modify the "reset-names" describe in ufs-hisi.txt binding file.
*List clocks in ufs-hisi.txt binding file.
*remove the "arst" and keep only "rst" in the binging files.
*remove the "arst" member from both dts and c code.
Major changes in v9:
- solve review comments from Rob Herring.
*remove freq-table-hz in ufs-hisi.txt binding file.
*Move the rst to the ufshcd_pltfm.txt common binding file.
*Modify the member "assert" of UFS host structure to "arst".
Major changes in v8:
- solve review comments from zhangfei.
*Add Version history.
- solve review comments from Rob Herring.
*remove freq-table-hz.
- solve review comments from Riku Voipio.
*Add MODULE_DEVICE_TABLE for ufs driver.
--
Major changes in v7:
- solve review comments from Philippe Ombredanne.
*use the new SPDX license ids instead of the GNU General Public License.
--
2.15.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 3/3] pinctrl: actions: Add interrupt support for OWL S900 SoC
From: Andy Shevchenko @ 2018-06-03 8:37 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Linus Walleij, Rob Herring, Andreas Färber, 刘炜,
mp-cs, 96boards, devicetree, Daniel Thompson, amit.kucheria,
linux-arm Mailing List, open list:GPIO SUBSYSTEM,
Linux Kernel Mailing List, hzhang, bdong, Mani Sadhasivam,
Thomas Liau, jeff.chen
In-Reply-To: <20180602165415.30956-4-manivannan.sadhasivam@linaro.org>
On Sat, Jun 2, 2018 at 7:54 PM, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
> Add interrupt support for Actions Semi OWL S900 SoC.
> + port = owl_gpio_get_port(pctrl, &gpio);
> + if (WARN_ON(port == NULL))
> + return;
At which circumstances the above possible?
> + port = owl_gpio_get_port(pctrl, &gpio);
> + if (WARN_ON(port == NULL))
> + return;
Ditto.
> + port = owl_gpio_get_port(pctrl, &gpio);
> + if (WARN_ON(port == NULL))
> + return;
Ditto.
> + port = owl_gpio_get_port(pctrl, &gpio);
> + if (WARN_ON(port == NULL))
> + return -ENODEV;
Ditto.
> + for (i = 0; i < chip->ngpio; i++) {
> + irqno = irq_create_mapping(pctrl->domain, i);
> + irq_set_chip_and_handler(irqno, &owl_gpio_irq_chip,
> + handle_edge_irq);
> + irq_set_chip_data(irqno, pctrl);
> + }
I'm not sure the handle_edge_irq() is a correct handler here. It would
be handle_bad_irq() until IRQ has been requested properly.
No?
> +/* GPIO TYPE Bit Definition */
> +#define OWL_GPIO_INT_LEVEL_HIGH 0
> +#define OWL_GPIO_INT_LEVEL_LOW 1
> +#define OWL_GPIO_INT_EDGE_RISING 2
> +#define OWL_GPIO_INT_EDGE_FALLING 3
> +#define OWL_GPIO_INT_MASK 3
GENMASK?
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH 3/3] pinctrl: actions: Add interrupt support for OWL S900 SoC
From: Manivannan Sadhasivam @ 2018-06-03 16:57 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Linus Walleij, Rob Herring, Andreas Färber, 刘炜,
mp-cs, 96boards, devicetree, Daniel Thompson, amit.kucheria,
linux-arm Mailing List, open list:GPIO SUBSYSTEM,
Linux Kernel Mailing List, hzhang, bdong, Mani Sadhasivam,
Thomas Liau, jeff.chen
In-Reply-To: <CAHp75Ve8ZCbEqnYK0KqtCHQm-EOUWRSyMzi51P+3_7brtXq6dA@mail.gmail.com>
Hi Andy,
On Sun, Jun 03, 2018 at 11:37:53AM +0300, Andy Shevchenko wrote:
> On Sat, Jun 2, 2018 at 7:54 PM, Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
> > Add interrupt support for Actions Semi OWL S900 SoC.
>
> > + port = owl_gpio_get_port(pctrl, &gpio);
> > + if (WARN_ON(port == NULL))
> > + return;
>
> At which circumstances the above possible?
>
Only possible when the requested GPIO exceeds chip->ngpio. I know it is
a kind of redundant check, but it is good to have this during development.
> > + port = owl_gpio_get_port(pctrl, &gpio);
> > + if (WARN_ON(port == NULL))
> > + return;
>
> Ditto.
>
Same as above.
> > + port = owl_gpio_get_port(pctrl, &gpio);
> > + if (WARN_ON(port == NULL))
> > + return;
>
> Ditto.
>
Same as above.
> > + port = owl_gpio_get_port(pctrl, &gpio);
> > + if (WARN_ON(port == NULL))
> > + return -ENODEV;
>
> Ditto.
>
Same as above.
>
> > + for (i = 0; i < chip->ngpio; i++) {
> > + irqno = irq_create_mapping(pctrl->domain, i);
> > + irq_set_chip_and_handler(irqno, &owl_gpio_irq_chip,
> > + handle_edge_irq);
> > + irq_set_chip_data(irqno, pctrl);
> > + }
>
> I'm not sure the handle_edge_irq() is a correct handler here. It would
> be handle_bad_irq() until IRQ has been requested properly.
> No?
>
Hmmm, good question. Since the handler used in irq_set_chip_and_handler
is superseded by irq_set_chained_handler_and_data, this doesn't matter
anyway. But I would like to hear what Linus suggests here!
> > +/* GPIO TYPE Bit Definition */
> > +#define OWL_GPIO_INT_LEVEL_HIGH 0
> > +#define OWL_GPIO_INT_LEVEL_LOW 1
> > +#define OWL_GPIO_INT_EDGE_RISING 2
> > +#define OWL_GPIO_INT_EDGE_FALLING 3
>
> > +#define OWL_GPIO_INT_MASK 3
>
> GENMASK?
>
Ack.
Thanks,
Mani
> --
> With Best Regards,
> Andy Shevchenko
^ permalink raw reply
* Re: [PATCH V2 2/2] ARM: dts: imx6ul: add GPIO clocks
From: Fabio Estevam @ 2018-06-03 20:57 UTC (permalink / raw)
To: Anson Huang
Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Rob Herring, Mark Rutland,
Michael Turquette, Stephen Boyd, Michael Trimarchi, Matteo Lisi,
NXP Linux Team,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel, linux-clk
In-Reply-To: <1527990245-13619-2-git-send-email-Anson.Huang@nxp.com>
On Sat, Jun 2, 2018 at 10:44 PM, Anson Huang <Anson.Huang@nxp.com> wrote:
> i.MX6UL has GPIO clock gates in CCM CCGR, add
> clock property for GPIO driver to make sure all
> GPIO banks work as expected.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* Re: [PATCH v2 0/4] drm/tinydrm: new dirver for ILI9341 displays
From: Noralf Trønnes @ 2018-06-03 22:00 UTC (permalink / raw)
To: David Lechner, dri-devel, devicetree
Cc: Rob Herring, Mark Rutland, limor, Nitin Patil, linux-kernel
In-Reply-To: <20180525193623.15533-1-david@lechnology.com>
Den 25.05.2018 21.36, skrev David Lechner:
> This series adds a new tinydrm driver for the Ilitek ILI9341 controller and
> a 2.4" display panel that uses this controller.
David, do you have commit rights now?
Noralf.
> A few things to note here:
> * The datasheet for this display[1] doesn't have a vendor mentioned on it
> anywhere, so I have used "adafruit" as the vendor prefix. If someone has a
> better suggestion, please speak up.
> * The MAINTAINERS patch for ili9225 is included so we don't end up with a merge
> conflict later on.
>
> v2 changes:
> * change vendor prefix from "noname" to "adafruit"
> * new patch for "adafruit" vendor prefix
> * minor style changes
> * drop regulator from driver (instead of adding to DT bindings)
>
> [1]: https://cdn-learn.adafruit.com/assets/assets/000/046/879/original/SPEC-YX240QV29-T_Rev.A__1_.pdf
>
>
> David Lechner (4):
> MAINTAINERS: fix path to ilitek,ili9225 device tree bindings
> dt-bindings: Add vendor prefix for Adafruit
> dt-bindings: new binding for Ilitek ILI9341 display panels
> drm/tinydrm: new driver for ILI9341 display panels
>
> .../bindings/display/ilitek,ili9341.txt | 27 ++
> .../devicetree/bindings/vendor-prefixes.txt | 1 +
> MAINTAINERS | 8 +-
> drivers/gpu/drm/tinydrm/Kconfig | 10 +
> drivers/gpu/drm/tinydrm/Makefile | 1 +
> drivers/gpu/drm/tinydrm/ili9341.c | 233 ++++++++++++++++++
> 6 files changed, 279 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9341.txt
> create mode 100644 drivers/gpu/drm/tinydrm/ili9341.c
>
^ permalink raw reply
* [PATCH v2 0/5] Tegra20 External Memory Controller driver
From: Dmitry Osipenko @ 2018-06-03 22:36 UTC (permalink / raw)
To: Thierry Reding, Peter De Schrijver, Jonathan Hunter,
Prashant Gaikwad, Michael Turquette, Stephen Boyd, Rob Herring,
Mark Rutland
Cc: linux-tegra, linux-clk, devicetree, linux-kernel
Hello,
Couple years ago the Tegra20 EMC driver was removed from the kernel
due to incompatible changes in the Tegra's clock driver. This patchset
introduces a modernized EMC driver. Currently the sole purpose of the
driver is to initialize DRAM frequency to maximum rate during of the
kernels boot-up. Later we may consider implementing dynamic memory
frequency scaling, utilizing functionality provided by this driver.
Changelog:
v2:
- Minor code cleanups like consistent use of writel_relaxed instead
of non-relaxed version, reworded error messages, etc.
- Factored out use_pllm_ud bit checking into a standalone patch for
consistency.
Dmitry Osipenko (5):
dt: bindings: tegra20-emc: Document interrupt property
ARM: dts: tegra20: Add interrupt to External Memory Controller
clk: tegra20: Turn EMC clock gate into divider
clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC
memory: tegra: Introduce Tegra20 EMC driver
.../bindings/arm/tegra/nvidia,tegra20-emc.txt | 2 +
arch/arm/boot/dts/tegra20.dtsi | 1 +
drivers/clk/tegra/clk-tegra20.c | 46 +-
drivers/memory/tegra/Kconfig | 10 +
drivers/memory/tegra/Makefile | 1 +
drivers/memory/tegra/tegra20-emc.c | 586 ++++++++++++++++++
6 files changed, 636 insertions(+), 10 deletions(-)
create mode 100644 drivers/memory/tegra/tegra20-emc.c
--
2.17.0
^ permalink raw reply
* [PATCH v2 1/5] dt: bindings: tegra20-emc: Document interrupt property
From: Dmitry Osipenko @ 2018-06-03 22:36 UTC (permalink / raw)
To: Thierry Reding, Peter De Schrijver, Jonathan Hunter,
Prashant Gaikwad, Michael Turquette, Stephen Boyd, Rob Herring,
Mark Rutland
Cc: linux-tegra, linux-clk, devicetree, linux-kernel
In-Reply-To: <20180603223654.23324-1-digetx@gmail.com>
EMC has a dedicated interrupt that is used to notify about completion of
HW operations. Document the interrupt property.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
.../devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt
index 4c33b29dc660..a6fe401d0d48 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt
@@ -10,6 +10,7 @@ Properties:
and chosen using the ramcode board selector. If omitted, only one
set of tables can be present and said tables will be used
irrespective of ram-code configuration.
+- interrupts : Should contain EMC General interrupt.
Child device nodes describe the memory settings for different configurations and clock rates.
@@ -20,6 +21,7 @@ Example:
#size-cells = < 0 >;
compatible = "nvidia,tegra20-emc";
reg = <0x7000f4000 0x200>;
+ interrupts = <0 78 0x04>;
}
--
2.17.0
^ permalink raw reply related
* [PATCH v2 2/5] ARM: dts: tegra20: Add interrupt to External Memory Controller
From: Dmitry Osipenko @ 2018-06-03 22:36 UTC (permalink / raw)
To: Thierry Reding, Peter De Schrijver, Jonathan Hunter,
Prashant Gaikwad, Michael Turquette, Stephen Boyd, Rob Herring,
Mark Rutland
Cc: linux-tegra, linux-clk, devicetree, linux-kernel
In-Reply-To: <20180603223654.23324-1-digetx@gmail.com>
Add interrupt entry into the EMC DT node.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra20.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 983dd5c14794..3cd3cb28cfd9 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -609,6 +609,7 @@
memory-controller@7000f400 {
compatible = "nvidia,tegra20-emc";
reg = <0x7000f400 0x200>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
};
--
2.17.0
^ permalink raw reply related
* [PATCH v2 3/5] clk: tegra20: Turn EMC clock gate into divider
From: Dmitry Osipenko @ 2018-06-03 22:36 UTC (permalink / raw)
To: Thierry Reding, Peter De Schrijver, Jonathan Hunter,
Prashant Gaikwad, Michael Turquette, Stephen Boyd, Rob Herring,
Mark Rutland
Cc: linux-tegra, linux-clk, devicetree, linux-kernel
In-Reply-To: <20180603223654.23324-1-digetx@gmail.com>
Kernel should never gate the EMC clock as it causes immediate lockup, so
removing clk-gate functionality doesn't affect anything. Turning EMC clk
gate into divider allows to implement glitch-less EMC scaling, avoiding
reparenting to a backup clock.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/clk/tegra/clk-tegra20.c | 36 ++++++++++++++++++++++++---------
1 file changed, 26 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index cc857d4d4a86..2bd35418716a 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -578,7 +578,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
[tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },
[tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true },
[tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true },
- [tegra_clk_emc] = { .dt_id = TEGRA20_CLK_EMC, .present = true },
};
static unsigned long tegra20_clk_measure_input_freq(void)
@@ -799,6 +798,31 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2),
};
+static void __init tegra20_emc_clk_init(void)
+{
+ struct clk *clk;
+
+ clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
+ ARRAY_SIZE(mux_pllmcp_clkm),
+ CLK_SET_RATE_NO_REPARENT,
+ clk_base + CLK_SOURCE_EMC,
+ 30, 2, 0, &emc_lock);
+
+ clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
+ &emc_lock);
+ clks[TEGRA20_CLK_MC] = clk;
+
+ /*
+ * Note that 'emc_mux' source and 'emc' rate shouldn't be changed at
+ * the same time due to a HW bug, this won't happen because we're
+ * defining 'emc_mux' and 'emc' as a distinct clocks.
+ */
+ clk = clk_register_divider(NULL, "emc", "emc_mux", CLK_IS_CRITICAL,
+ clk_base + CLK_SOURCE_EMC, 0, 7,
+ 0, &emc_lock);
+ clks[TEGRA20_CLK_EMC] = clk;
+}
+
static void __init tegra20_periph_clk_init(void)
{
struct tegra_periph_init_data *data;
@@ -812,15 +836,7 @@ static void __init tegra20_periph_clk_init(void)
clks[TEGRA20_CLK_AC97] = clk;
/* emc */
- clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
- ARRAY_SIZE(mux_pllmcp_clkm),
- CLK_SET_RATE_NO_REPARENT,
- clk_base + CLK_SOURCE_EMC,
- 30, 2, 0, &emc_lock);
-
- clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
- &emc_lock);
- clks[TEGRA20_CLK_MC] = clk;
+ tegra20_emc_clk_init();
/* dsi */
clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
--
2.17.0
^ permalink raw reply related
* [PATCH v2 4/5] clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC
From: Dmitry Osipenko @ 2018-06-03 22:36 UTC (permalink / raw)
To: Thierry Reding, Peter De Schrijver, Jonathan Hunter,
Prashant Gaikwad, Michael Turquette, Stephen Boyd, Rob Herring,
Mark Rutland
Cc: linux-tegra, linux-clk, devicetree, linux-kernel
In-Reply-To: <20180603223654.23324-1-digetx@gmail.com>
Ensure that direct PLLM sourcing is turned off for EMC as we don't support
that configuration in the clk driver.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/clk/tegra/clk-tegra20.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 2bd35418716a..ca4eadb9520e 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -800,7 +800,9 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
static void __init tegra20_emc_clk_init(void)
{
+ const u32 use_pllm_ud = BIT(29);
struct clk *clk;
+ u32 emc_reg;
clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
ARRAY_SIZE(mux_pllmcp_clkm),
@@ -812,6 +814,14 @@ static void __init tegra20_emc_clk_init(void)
&emc_lock);
clks[TEGRA20_CLK_MC] = clk;
+ /* un-divided pll_m_out0 is currently unsupported */
+ emc_reg = readl_relaxed(clk_base + CLK_SOURCE_EMC);
+ if (emc_reg & use_pllm_ud) {
+ pr_err("%s: un-divided PllM_out0 used as clock source\n",
+ __func__);
+ return;
+ }
+
/*
* Note that 'emc_mux' source and 'emc' rate shouldn't be changed at
* the same time due to a HW bug, this won't happen because we're
--
2.17.0
^ permalink raw reply related
* [PATCH v2 5/5] memory: tegra: Introduce Tegra20 EMC driver
From: Dmitry Osipenko @ 2018-06-03 22:36 UTC (permalink / raw)
To: Thierry Reding, Peter De Schrijver, Jonathan Hunter,
Prashant Gaikwad, Michael Turquette, Stephen Boyd, Rob Herring,
Mark Rutland
Cc: linux-tegra, linux-clk, devicetree, linux-kernel
In-Reply-To: <20180603223654.23324-1-digetx@gmail.com>
Introduce driver for the External Memory Controller (EMC) found on Tegra20
chips, which controls the external DRAM on the board. The purpose of this
driver is to program memory timing for external memory on the EMC clock
rate change.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/memory/tegra/Kconfig | 10 +
drivers/memory/tegra/Makefile | 1 +
drivers/memory/tegra/tegra20-emc.c | 586 +++++++++++++++++++++++++++++
3 files changed, 597 insertions(+)
create mode 100644 drivers/memory/tegra/tegra20-emc.c
diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig
index 6d74e499e18d..34e0b70f5c5f 100644
--- a/drivers/memory/tegra/Kconfig
+++ b/drivers/memory/tegra/Kconfig
@@ -6,6 +6,16 @@ config TEGRA_MC
This driver supports the Memory Controller (MC) hardware found on
NVIDIA Tegra SoCs.
+config TEGRA20_EMC
+ bool "NVIDIA Tegra20 External Memory Controller driver"
+ default y
+ depends on ARCH_TEGRA_2x_SOC
+ help
+ This driver is for the External Memory Controller (EMC) found on
+ Tegra20 chips. The EMC controls the external DRAM on the board.
+ This driver is required to change memory timings / clock rate for
+ external memory.
+
config TEGRA124_EMC
bool "NVIDIA Tegra124 External Memory Controller driver"
default y
diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile
index 94ab16ba075b..3971a6b7c487 100644
--- a/drivers/memory/tegra/Makefile
+++ b/drivers/memory/tegra/Makefile
@@ -10,5 +10,6 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
+obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o
obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c
new file mode 100644
index 000000000000..26a18b5e7941
--- /dev/null
+++ b/drivers/memory/tegra/tegra20-emc.c
@@ -0,0 +1,586 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Tegra20 External Memory Controller driver
+ *
+ * Author: Dmitry Osipenko <digetx@gmail.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/sort.h>
+#include <linux/types.h>
+
+#include <soc/tegra/fuse.h>
+
+#define EMC_INTSTATUS 0x000
+#define EMC_INTMASK 0x004
+#define EMC_TIMING_CONTROL 0x028
+#define EMC_RC 0x02c
+#define EMC_RFC 0x030
+#define EMC_RAS 0x034
+#define EMC_RP 0x038
+#define EMC_R2W 0x03c
+#define EMC_W2R 0x040
+#define EMC_R2P 0x044
+#define EMC_W2P 0x048
+#define EMC_RD_RCD 0x04c
+#define EMC_WR_RCD 0x050
+#define EMC_RRD 0x054
+#define EMC_REXT 0x058
+#define EMC_WDV 0x05c
+#define EMC_QUSE 0x060
+#define EMC_QRST 0x064
+#define EMC_QSAFE 0x068
+#define EMC_RDV 0x06c
+#define EMC_REFRESH 0x070
+#define EMC_BURST_REFRESH_NUM 0x074
+#define EMC_PDEX2WR 0x078
+#define EMC_PDEX2RD 0x07c
+#define EMC_PCHG2PDEN 0x080
+#define EMC_ACT2PDEN 0x084
+#define EMC_AR2PDEN 0x088
+#define EMC_RW2PDEN 0x08c
+#define EMC_TXSR 0x090
+#define EMC_TCKE 0x094
+#define EMC_TFAW 0x098
+#define EMC_TRPAB 0x09c
+#define EMC_TCLKSTABLE 0x0a0
+#define EMC_TCLKSTOP 0x0a4
+#define EMC_TREFBW 0x0a8
+#define EMC_QUSE_EXTRA 0x0ac
+#define EMC_ODT_WRITE 0x0b0
+#define EMC_ODT_READ 0x0b4
+#define EMC_FBIO_CFG5 0x104
+#define EMC_FBIO_CFG6 0x114
+#define EMC_AUTO_CAL_INTERVAL 0x2a8
+#define EMC_CFG_2 0x2b8
+#define EMC_CFG_DIG_DLL 0x2bc
+#define EMC_DLL_XFORM_DQS 0x2c0
+#define EMC_DLL_XFORM_QUSE 0x2c4
+#define EMC_ZCAL_REF_CNT 0x2e0
+#define EMC_ZCAL_WAIT_CNT 0x2e4
+#define EMC_CFG_CLKTRIM_0 0x2d0
+#define EMC_CFG_CLKTRIM_1 0x2d4
+#define EMC_CFG_CLKTRIM_2 0x2d8
+
+#define EMC_CLKCHANGE_REQ_ENABLE BIT(0)
+#define EMC_CLKCHANGE_PD_ENABLE BIT(1)
+#define EMC_CLKCHANGE_SR_ENABLE BIT(2)
+
+#define EMC_TIMING_UPDATE BIT(0)
+
+#define EMC_CLKCHANGE_COMPLETE_INT BIT(4)
+
+static const unsigned long emc_timing_registers[] = {
+ EMC_RC,
+ EMC_RFC,
+ EMC_RAS,
+ EMC_RP,
+ EMC_R2W,
+ EMC_W2R,
+ EMC_R2P,
+ EMC_W2P,
+ EMC_RD_RCD,
+ EMC_WR_RCD,
+ EMC_RRD,
+ EMC_REXT,
+ EMC_WDV,
+ EMC_QUSE,
+ EMC_QRST,
+ EMC_QSAFE,
+ EMC_RDV,
+ EMC_REFRESH,
+ EMC_BURST_REFRESH_NUM,
+ EMC_PDEX2WR,
+ EMC_PDEX2RD,
+ EMC_PCHG2PDEN,
+ EMC_ACT2PDEN,
+ EMC_AR2PDEN,
+ EMC_RW2PDEN,
+ EMC_TXSR,
+ EMC_TCKE,
+ EMC_TFAW,
+ EMC_TRPAB,
+ EMC_TCLKSTABLE,
+ EMC_TCLKSTOP,
+ EMC_TREFBW,
+ EMC_QUSE_EXTRA,
+ EMC_FBIO_CFG6,
+ EMC_ODT_WRITE,
+ EMC_ODT_READ,
+ EMC_FBIO_CFG5,
+ EMC_CFG_DIG_DLL,
+ EMC_DLL_XFORM_DQS,
+ EMC_DLL_XFORM_QUSE,
+ EMC_ZCAL_REF_CNT,
+ EMC_ZCAL_WAIT_CNT,
+ EMC_AUTO_CAL_INTERVAL,
+ EMC_CFG_CLKTRIM_0,
+ EMC_CFG_CLKTRIM_1,
+ EMC_CFG_CLKTRIM_2,
+};
+
+struct emc_timing {
+ unsigned long rate;
+ u32 emc_registers_data[ARRAY_SIZE(emc_timing_registers)];
+};
+
+struct tegra_emc {
+ struct device *dev;
+ struct notifier_block clk_nb;
+ struct clk *backup_clk;
+ struct clk *emc_mux;
+ struct clk *pll_m;
+ struct clk *clk;
+ void __iomem *regs;
+
+ struct completion clk_handshake_complete;
+ int irq;
+
+ struct emc_timing *timings;
+ unsigned int num_timings;
+};
+
+static irqreturn_t tegra_emc_isr(int irq, void *data)
+{
+ struct tegra_emc *emc = data;
+ u32 intmask = EMC_CLKCHANGE_COMPLETE_INT;
+ u32 status;
+
+ status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
+ if (!status)
+ return IRQ_NONE;
+
+ /* clear interrupts */
+ writel_relaxed(status, emc->regs + EMC_INTSTATUS);
+
+ /* notify about EMC-CAR handshake completion */
+ complete(&emc->clk_handshake_complete);
+
+ return IRQ_HANDLED;
+}
+
+static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
+ unsigned long rate)
+{
+ struct emc_timing *timing = NULL;
+ unsigned int i;
+
+ for (i = 0; i < emc->num_timings; i++) {
+ if (emc->timings[i].rate >= rate) {
+ timing = &emc->timings[i];
+ break;
+ }
+ }
+
+ if (!timing) {
+ dev_err(emc->dev, "no timing for rate %lu\n", rate);
+ return NULL;
+ }
+
+ return timing;
+}
+
+static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
+{
+ struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
+ unsigned int i;
+
+ if (!timing)
+ return -ENOENT;
+
+ dev_dbg(emc->dev, "%s: timing rate %lu emc rate %lu\n",
+ __func__, timing->rate, rate);
+
+ /* program shadow registers */
+ for (i = 0; i < ARRAY_SIZE(timing->emc_registers_data); i++)
+ writel_relaxed(timing->emc_registers_data[i],
+ emc->regs + emc_timing_registers[i]);
+
+ /* wait until programming has settled */
+ readl_relaxed(emc->regs + emc_timing_registers[0]);
+
+ if (emc->irq < 0)
+ writel_relaxed(EMC_CLKCHANGE_COMPLETE_INT,
+ emc->regs + EMC_INTMASK);
+ else
+ reinit_completion(&emc->clk_handshake_complete);
+
+ return 0;
+}
+
+static int emc_complete_timing_change(struct tegra_emc *emc, bool flush)
+{
+ long timeout;
+ u32 value;
+ int err;
+
+ dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush);
+
+ if (flush) {
+ /* manually initiate memory timing update */
+ writel_relaxed(EMC_TIMING_UPDATE,
+ emc->regs + EMC_TIMING_CONTROL);
+ return 0;
+ }
+
+ if (emc->irq < 0) {
+ /* poll interrupt status if IRQ isn't available */
+ err = readl_relaxed_poll_timeout(emc->regs + EMC_INTSTATUS,
+ value, value & EMC_CLKCHANGE_COMPLETE_INT,
+ 1, 100);
+ if (err) {
+ dev_err(emc->dev, "EMC-CAR handshake failed\n");
+ return -EIO;
+ }
+
+ return 0;
+ }
+
+ timeout = wait_for_completion_timeout(&emc->clk_handshake_complete,
+ usecs_to_jiffies(100));
+ if (timeout == 0) {
+ dev_err(emc->dev, "EMC handshake failed\n");
+ return -EIO;
+ } else if (timeout < 0) {
+ dev_err(emc->dev, "failed to wait for EMC-CAR handshake: %ld\n",
+ timeout);
+ return timeout;
+ }
+
+ return 0;
+}
+
+static int load_one_timing_from_dt(struct tegra_emc *emc,
+ struct emc_timing *timing,
+ struct device_node *node)
+{
+ u32 rate;
+ int err;
+
+ if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) {
+ dev_err(emc->dev, "incompatible DT node \"%s\"\n",
+ node->name);
+ return -EINVAL;
+ }
+
+ err = of_property_read_u32(node, "clock-frequency", &rate);
+ if (err) {
+ dev_err(emc->dev, "timing %s: failed to read rate: %d\n",
+ node->name, err);
+ return err;
+ }
+
+ err = of_property_read_u32_array(node, "nvidia,emc-registers",
+ timing->emc_registers_data,
+ ARRAY_SIZE(emc_timing_registers));
+ if (err) {
+ dev_err(emc->dev,
+ "timing %s: failed to read emc timing data: %d\n",
+ node->name, err);
+ return err;
+ }
+
+ /*
+ * The EMC clock rate is twice the bus rate, and the bus rate is
+ * measured in kHz.
+ */
+ timing->rate = rate * 2 * 1000;
+
+ dev_dbg(emc->dev, "%s: emc rate %ld\n", __func__, timing->rate);
+
+ return 0;
+}
+
+static int cmp_timings(const void *_a, const void *_b)
+{
+ const struct emc_timing *a = _a;
+ const struct emc_timing *b = _b;
+
+ if (a->rate < b->rate)
+ return -1;
+ else if (a->rate == b->rate)
+ return 0;
+ else
+ return 1;
+}
+
+static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
+ struct device_node *node)
+{
+ struct device_node *child;
+ struct emc_timing *timing;
+ int child_count;
+ int err;
+
+ child_count = of_get_child_count(node);
+ if (!child_count) {
+ dev_err(emc->dev, "no memory timings in DT node\n");
+ return -ENOENT;
+ }
+
+ emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
+ GFP_KERNEL);
+ if (!emc->timings)
+ return -ENOMEM;
+
+ emc->num_timings = child_count;
+ timing = emc->timings;
+
+ for_each_child_of_node(node, child) {
+ err = load_one_timing_from_dt(emc, timing++, child);
+ if (err) {
+ of_node_put(child);
+ return err;
+ }
+ }
+
+ sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
+ NULL);
+
+ return 0;
+}
+
+static struct device_node *
+tegra_emc_find_node_by_ram_code(struct tegra_emc *emc, u32 ram_code)
+{
+ struct device_node *np;
+ int err;
+
+ for_each_child_of_node(emc->dev->of_node, np) {
+ u32 value;
+
+ err = of_property_read_u32(np, "nvidia,ram-code", &value);
+ if (err || value != ram_code)
+ continue;
+
+ return np;
+ }
+
+ dev_info(emc->dev, "no memory timings for RAM code %u found in DT\n",
+ ram_code);
+
+ return NULL;
+}
+
+static int tegra_emc_clk_change_notify(struct notifier_block *nb,
+ unsigned long msg, void *data)
+{
+ struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
+ struct clk_notifier_data *cnd = data;
+ int err;
+
+ switch (msg) {
+ case PRE_RATE_CHANGE:
+ err = emc_prepare_timing_change(emc, cnd->new_rate);
+ break;
+
+ case ABORT_RATE_CHANGE:
+ err = emc_prepare_timing_change(emc, cnd->old_rate);
+ if (err)
+ break;
+
+ err = emc_complete_timing_change(emc, true);
+ break;
+
+ case POST_RATE_CHANGE:
+ err = emc_complete_timing_change(emc, false);
+ break;
+
+ default:
+ return NOTIFY_DONE;
+ }
+
+ return notifier_from_errno(err);
+}
+
+static int emc_setup_hw(struct tegra_emc *emc)
+{
+ u32 emc_cfg;
+
+ emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
+
+ /*
+ * Depending on a memory type, DRAM should enter either self-refresh
+ * or power-down state on EMC clock change.
+ */
+ if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) &&
+ !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE))
+ {
+ dev_err(emc->dev,
+ "bootloader didn't specify DRAM auto-suspend mode\n");
+ return -EINVAL;
+ }
+
+ /* allow EMC and CAR to handshake on PLL divider/source changes */
+ emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE;
+ writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
+
+ /* initialize interrupt */
+ writel_relaxed(EMC_CLKCHANGE_COMPLETE_INT, emc->regs + EMC_INTMASK);
+ writel_relaxed(EMC_CLKCHANGE_COMPLETE_INT, emc->regs + EMC_INTSTATUS);
+
+ return 0;
+}
+
+static int emc_init(struct tegra_emc *emc, unsigned long rate)
+{
+ int err;
+
+ err = clk_set_parent(emc->emc_mux, emc->backup_clk);
+ if (err) {
+ dev_err(emc->dev,
+ "failed to reparent to backup source: %d\n", err);
+ return err;
+ }
+
+ err = clk_set_rate(emc->pll_m, rate);
+ if (err)
+ dev_err(emc->dev,
+ "failed to change pll_m rate: %d\n", err);
+
+ err = clk_set_parent(emc->emc_mux, emc->pll_m);
+ if (err) {
+ dev_err(emc->dev,
+ "failed to reparent to pll_m: %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+static int tegra_emc_probe(struct platform_device *pdev)
+{
+ struct device_node *np;
+ struct tegra_emc *emc;
+ struct resource *res;
+ u32 ram_code;
+ int err;
+
+ emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
+ if (!emc)
+ return -ENOMEM;
+
+ emc->dev = &pdev->dev;
+
+ ram_code = tegra_read_ram_code();
+
+ np = tegra_emc_find_node_by_ram_code(emc, ram_code);
+ if (!np)
+ return -ENOENT;
+
+ err = tegra_emc_load_timings_from_dt(emc, np);
+ of_node_put(np);
+ if (err)
+ return err;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ emc->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(emc->regs))
+ return PTR_ERR(emc->regs);
+
+ err = emc_setup_hw(emc);
+ if (err)
+ return err;
+
+ emc->irq = platform_get_irq(pdev, 0);
+ if (emc->irq < 0) {
+ dev_warn(&pdev->dev, "interrupt not specified\n");
+ dev_warn(&pdev->dev, "continuing, but please update your DT\n");
+ } else {
+ init_completion(&emc->clk_handshake_complete);
+
+ err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0,
+ dev_name(&pdev->dev), emc);
+ if (err < 0) {
+ dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
+ emc->irq, err);
+ return err;
+ }
+ }
+
+ emc->pll_m = clk_get_sys(NULL, "pll_m");
+ if (IS_ERR(emc->pll_m)) {
+ err = PTR_ERR(emc->pll_m);
+ dev_err(&pdev->dev, "failed to get pll_m: %d\n", err);
+ return err;
+ }
+
+ emc->backup_clk = clk_get_sys(NULL, "pll_p");
+ if (IS_ERR(emc->backup_clk)) {
+ err = PTR_ERR(emc->backup_clk);
+ dev_err(&pdev->dev, "failed to get pll_p: %d\n", err);
+ goto put_pll_m;
+ }
+
+ emc->clk = clk_get_sys(NULL, "emc");
+ if (IS_ERR(emc->clk)) {
+ err = PTR_ERR(emc->clk);
+ dev_err(&pdev->dev, "failed to get emc: %d\n", err);
+ goto put_backup;
+ }
+
+ emc->emc_mux = clk_get_parent(emc->clk);
+ if (IS_ERR(emc->emc_mux)) {
+ err = PTR_ERR(emc->emc_mux);
+ dev_err(&pdev->dev, "failed to get emc_mux: %d\n", err);
+ goto put_emc;
+ }
+
+ emc->clk_nb.notifier_call = tegra_emc_clk_change_notify;
+
+ err = clk_notifier_register(emc->clk, &emc->clk_nb);
+ if (err) {
+ dev_err(&pdev->dev, "failed to register clk notifier: %d\n",
+ err);
+ goto put_emc;
+ }
+
+ /* set DRAM clock rate to maximum */
+ err = emc_init(emc, emc->timings[emc->num_timings - 1].rate);
+ if (err) {
+ dev_err(&pdev->dev, "failed to initialize clk rate: %d\n",
+ err);
+ goto unreg_notifier;
+ }
+
+ return 0;
+
+unreg_notifier:
+ clk_notifier_unregister(emc->emc_mux, &emc->clk_nb);
+put_emc:
+ clk_put(emc->clk);
+put_backup:
+ clk_put(emc->backup_clk);
+put_pll_m:
+ clk_put(emc->pll_m);
+
+ return err;
+}
+
+static const struct of_device_id tegra_emc_of_match[] = {
+ { .compatible = "nvidia,tegra20-emc", },
+ {},
+};
+
+static struct platform_driver tegra_emc_driver = {
+ .probe = tegra_emc_probe,
+ .driver = {
+ .name = "tegra20-emc",
+ .of_match_table = tegra_emc_of_match,
+ .suppress_bind_attrs = true,
+ },
+};
+
+static int __init tegra_emc_init(void)
+{
+ return platform_driver_register(&tegra_emc_driver);
+}
+subsys_initcall(tegra_emc_init);
--
2.17.0
^ permalink raw reply related
* Re: [PATCH v2 0/4] drm/tinydrm: new dirver for ILI9341 displays
From: David Lechner @ 2018-06-04 1:21 UTC (permalink / raw)
To: Noralf Trønnes, dri-devel, devicetree
Cc: Rob Herring, Mark Rutland, limor, Nitin Patil, linux-kernel
In-Reply-To: <8840212b-fd46-e700-58a1-cb1b882c5771@tronnes.org>
On 6/3/18 5:00 PM, Noralf Trønnes wrote:
>
> Den 25.05.2018 21.36, skrev David Lechner:
>> This series adds a new tinydrm driver for the Ilitek ILI9341
>> controller and
>> a 2.4" display panel that uses this controller.
>
> David, do you have commit rights now?
No. Opened a bug a while back to request access, but I guess the
right person didn't see it.
https://bugs.freedesktop.org/show_bug.cgi?id=105166
>
> Noralf.
>
>> A few things to note here:
>> * The datasheet for this display[1] doesn't have a vendor mentioned on it
>> anywhere, so I have used "adafruit" as the vendor prefix. If
>> someone has a
>> better suggestion, please speak up.
>> * The MAINTAINERS patch for ili9225 is included so we don't end up
>> with a merge
>> conflict later on.
>>
>> v2 changes:
>> * change vendor prefix from "noname" to "adafruit"
>> * new patch for "adafruit" vendor prefix
>> * minor style changes
>> * drop regulator from driver (instead of adding to DT bindings)
>>
>> [1]:
>> https://cdn-learn.adafruit.com/assets/assets/000/046/879/original/SPEC-YX240QV29-T_Rev.A__1_.pdf
>>
>>
>>
>> David Lechner (4):
>> MAINTAINERS: fix path to ilitek,ili9225 device tree bindings
>> dt-bindings: Add vendor prefix for Adafruit
>> dt-bindings: new binding for Ilitek ILI9341 display panels
>> drm/tinydrm: new driver for ILI9341 display panels
>>
>> .../bindings/display/ilitek,ili9341.txt | 27 ++
>> .../devicetree/bindings/vendor-prefixes.txt | 1 +
>> MAINTAINERS | 8 +-
>> drivers/gpu/drm/tinydrm/Kconfig | 10 +
>> drivers/gpu/drm/tinydrm/Makefile | 1 +
>> drivers/gpu/drm/tinydrm/ili9341.c | 233 ++++++++++++++++++
>> 6 files changed, 279 insertions(+), 1 deletion(-)
>> create mode 100644
>> Documentation/devicetree/bindings/display/ilitek,ili9341.txt
>> create mode 100644 drivers/gpu/drm/tinydrm/ili9341.c
>>
>
^ permalink raw reply
* Re: [PATCH 1/2] thermal: tsens: Add support for SDM845 platform
From: Rajendra Nayak @ 2018-06-04 4:25 UTC (permalink / raw)
To: Amit Kucheria, linux-arm-msm
Cc: bjorn.andersson, edubezval, Zhang Rui, Rob Herring, Mark Rutland,
open list:THERMAL,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <7a0f33cff94f41110bdbff14d28d36074fae2a7d.1527937396.git.amit.kucheria@linaro.org>
On 06/02/2018 04:41 PM, Amit Kucheria wrote:
> There are two tsens blocks on the SDM845. These will be configured through
> the devicetree.
>
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> ---
> .../devicetree/bindings/thermal/qcom-tsens.txt | 1 +
> drivers/thermal/qcom/Makefile | 2 +-
> drivers/thermal/qcom/tsens-sdm845.c | 98 ++++++++++++++++++++++
> drivers/thermal/qcom/tsens.c | 3 +
> drivers/thermal/qcom/tsens.h | 1 +
> 5 files changed, 104 insertions(+), 1 deletion(-)
> create mode 100644 drivers/thermal/qcom/tsens-sdm845.c
>
> diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt
> index 292ed89..8652499 100644
> --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt
> +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt
> @@ -5,6 +5,7 @@ Required properties:
> - "qcom,msm8916-tsens" : For 8916 Family of SoCs
> - "qcom,msm8974-tsens" : For 8974 Family of SoCs
> - "qcom,msm8996-tsens" : For 8996 Family of SoCs
> + - "qcom,sdm845-tsens" : For SDM845 Family of SoCs
>
> - reg: Address range of the thermal registers
> - #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description.
> diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile
> index 2cc2193..dc9f169 100644
> --- a/drivers/thermal/qcom/Makefile
> +++ b/drivers/thermal/qcom/Makefile
> @@ -1,2 +1,2 @@
> obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o
> -qcom_tsens-y += tsens.o tsens-common.o tsens-8916.o tsens-8974.o tsens-8960.o tsens-8996.o
> +qcom_tsens-y += tsens.o tsens-common.o tsens-8916.o tsens-8974.o tsens-8960.o tsens-8996.o tsens-sdm845.o
> diff --git a/drivers/thermal/qcom/tsens-sdm845.c b/drivers/thermal/qcom/tsens-sdm845.c
> new file mode 100644
> index 0000000..5d78f0b
> --- /dev/null
> +++ b/drivers/thermal/qcom/tsens-sdm845.c
> @@ -0,0 +1,98 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, Linaro Limited
> + */
> +
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include "tsens.h"
> +
> +#define CNTL_OFFSET 4
> +/* CNTL_OFFSET bitmasks */
> +#define EN BIT(0)
> +#define SW_RST BIT(1)
> +
> +#define SENSOR0_SHIFT 3
> +
> +#define TRDY_OFFSET 0xe4
> +#define TRDY_READY_BIT BIT(1)
> +
> +#define STATUS_OFFSET 0xa0
> +#define LAST_TEMP_MASK 0xfff
> +#define STATUS_VALID_BIT BIT(21)
> +#define CODE_SIGN_BIT BIT(11)
> +
> +static int get_temp_sdm845(struct tsens_device *tmdev, int id, int *temp)
> +{
> + struct tsens_sensor *s = &tmdev->sensor[id];
> + u32 code;
> + unsigned int sensor_addr;
> + int last_temp = 0, last_temp2 = 0, last_temp3 = 0, ret;
> +
> + ret = regmap_read(tmdev->map, TRDY_OFFSET, &code);
> + if (ret)
> + return ret;
> + if (code & TRDY_READY_BIT)
> + return -ENODATA;
> +
> + sensor_addr = STATUS_OFFSET + s->hw_id * 4;
> + ret = regmap_read(tmdev->map, sensor_addr, &code);
> + if (ret)
> + return ret;
> + last_temp = code & LAST_TEMP_MASK;
> + if (code & STATUS_VALID_BIT)
> + goto done;
> +
> + /* Try a second time */
> + ret = regmap_read(tmdev->map, sensor_addr, &code);
> + if (ret)
> + return ret;
> + if (code & STATUS_VALID_BIT) {
> + last_temp = code & LAST_TEMP_MASK;
> + goto done;
> + } else {
> + last_temp2 = code & LAST_TEMP_MASK;
> + }
> +
> + /* Try a third/last time */
> + ret = regmap_read(tmdev->map, sensor_addr, &code);
> + if (ret)
> + return ret;
> + if (code & STATUS_VALID_BIT) {
> + last_temp = code & LAST_TEMP_MASK;
> + goto done;
> + } else {
> + last_temp3 = code & LAST_TEMP_MASK;
> + }
> +
> + if (last_temp == last_temp2)
> + last_temp = last_temp2;
> + else if (last_temp2 == last_temp3)
> + last_temp = last_temp3;
> +done:
> + /* Code sign bit is the sign extension for a negative value */
> + if (last_temp & CODE_SIGN_BIT)
> + last_temp |= ~CODE_SIGN_BIT;
> +
> + /* Temperatures are in deciCelicius */
> + *temp = last_temp * 100;
This looks the same as what we do for 8996. Does it make sense to move this
to tsens-common and reuse in both 8996 and 845?
> +
> + return 0;
> +}
> +
> +static const struct regmap_config tsens_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
> +
> +
> +static const struct tsens_ops ops_sdm845 = {
> + .init = init_common,
> + .get_temp = get_temp_sdm845,
> +};
> +
> +const struct tsens_data data_sdm845 = {
> + .ops = &ops_sdm845,
> +};
> diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c
> index 3f9fe6a..314a20f 100644
> --- a/drivers/thermal/qcom/tsens.c
> +++ b/drivers/thermal/qcom/tsens.c
> @@ -72,6 +72,9 @@ static const struct of_device_id tsens_table[] = {
> }, {
> .compatible = "qcom,msm8996-tsens",
> .data = &data_8996,
> + }, {
> + .compatible = "qcom,sdm845-tsens",
> + .data = &data_sdm845,
> },
> {}
> };
> diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h
> index 911c197..f15660d 100644
> --- a/drivers/thermal/qcom/tsens.h
> +++ b/drivers/thermal/qcom/tsens.h
> @@ -90,5 +90,6 @@ int init_common(struct tsens_device *);
> int get_temp_common(struct tsens_device *, int, int *);
>
> extern const struct tsens_data data_8916, data_8974, data_8960, data_8996;
> +extern const struct tsens_data data_sdm845;
>
> #endif /* __QCOM_TSENS_H__ */
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply
* RE: [PATCH v7 2/2] ARM: dts: imx: Add basic dts support for imx6sll EVK board
From: A.s. Dong @ 2018-06-04 5:27 UTC (permalink / raw)
To: Jacky Bai, shawnguo@kernel.org, robh+dt@kernel.org,
kernel@pengutronix.de
Cc: devicetree@vger.kernel.org, dl-linux-imx,
linux-arm-kernel@lists.infradead.org, jacky.baip@gmail.com
In-Reply-To: <AM0PR04MB42110126E2FA536C0EFE0E2F80690@AM0PR04MB4211.eurprd04.prod.outlook.com>
Gently ping...
> -----Original Message-----
> From: A.s. Dong
> Sent: Friday, May 25, 2018 3:56 PM
> To: Jacky Bai <ping.bai@nxp.com>; shawnguo@kernel.org;
> robh+dt@kernel.org; kernel@pengutronix.de
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; dl-
> linux-imx <linux-imx@nxp.com>; jacky.baip@gmail.com
> Subject: RE: [PATCH v7 2/2] ARM: dts: imx: Add basic dts support for imx6sll
> EVK board
>
> Hi Shawn,
>
> > -----Original Message-----
> > From: Jacky Bai
> > Sent: Friday, May 25, 2018 3:42 PM
> > To: shawnguo@kernel.org; robh+dt@kernel.org; kernel@pengutronix.de
> > Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > dl- linux-imx <linux-imx@nxp.com>; A.s. Dong <aisheng.dong@nxp.com>;
> > jacky.baip@gmail.com
> > Subject: [PATCH v7 2/2] ARM: dts: imx: Add basic dts support for
> > imx6sll EVK board
> >
> > Add dts file support for imx6sll EVK board.
> >
> > Signed-off-by: Bai Ping <ping.bai@nxp.com>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Acked-by: Dong Aisheng <Aisheng.dong@nxp.com>
>
> Would you help pick this patch series?
> It seems there's only DTS part left for MX6SLL support.
>
> Regards
> Dong Aisheng
^ permalink raw reply
* Re: [PATCH V2] mfd: dt: Add bindings for DA9063L
From: Lee Jones @ 2018-06-04 5:47 UTC (permalink / raw)
To: Marek Vasut
Cc: devicetree, Marek Vasut, Geert Uytterhoeven, Rob Herring,
Steve Twiss, Wolfram Sang, linux-renesas-soc
In-Reply-To: <20180523122140.6275-1-marek.vasut+renesas@gmail.com>
On Wed, 23 May 2018, Marek Vasut wrote:
> Add device tree bindings for the Dialog DA9063L. This is a
> variant of the DA9063 chip with smaller package, with less
> LDO regulators and without RTC block. The other properties
> of the chip are the same, including the content of the chip
> ID register.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Lee Jones <lee.jones@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Steve Twiss <stwiss.opensource@diasemi.com>
> Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Cc: linux-renesas-soc@vger.kernel.org
> ---
> V2: Merge the DA9063/DA9063L regulator lists and mark DA9063-only
> regulators in that single list
> ---
> Documentation/devicetree/bindings/mfd/da9063.txt | 32 +++++++++++++-----------
> 1 file changed, 17 insertions(+), 15 deletions(-)
Applied, thanks.
--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* Re: [PATCH v2 5/6] ARM: dts: Add generic interconnect target module node for MCAN
From: Faiz Abbas @ 2018-06-04 5:49 UTC (permalink / raw)
To: Stephen Boyd, devicetree, linux-arm-kernel, linux-clk,
linux-kernel, linux-omap
Cc: robh+dt, bcousson, tony, paul, t-kristo
In-Reply-To: <152792116258.225090.5279546677198775320@swboyd.mtv.corp.google.com>
Hi,
On Saturday 02 June 2018 12:02 PM, Stephen Boyd wrote:
> Quoting Faiz Abbas (2018-05-30 07:11:32)
>> diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi
>> index bfc82636999c..57b8dc0fe719 100644
>> --- a/arch/arm/boot/dts/dra76x.dtsi
>> +++ b/arch/arm/boot/dts/dra76x.dtsi
>> @@ -11,6 +11,25 @@
>> / {
>> compatible = "ti,dra762", "ti,dra7";
>>
>> + ocp {
>> +
>> + target-module@0x42c00000 {
>
> Drop the 0x on unit address. Also, it should match the first register
> property. And what is a "target-module"?
>
Will fix it. And please see
Documentation/devicetree/bindings/bus/ti-sysc.txt
Thanks,
Faiz
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: thermal: Add binding document for SR thermal
From: Srinath Mannam @ 2018-06-04 6:06 UTC (permalink / raw)
To: Rob Herring
Cc: Zhang Rui, Eduardo Valentin, Mark Rutland, devicetree,
linux-kernel@vger.kernel.org, BCM Kernel Feedback, Pramod Kumar
In-Reply-To: <CAL_JsqJsGouQjWAu01fR4LpwanKbSj1d_CvyPXyMBe2vVBHqdw@mail.gmail.com>
Hi Rob Herring,
Please find my comments in line..
On Fri, Jun 1, 2018 at 7:59 PM, Rob Herring <robh@kernel.org> wrote:
> On Fri, Jun 1, 2018 at 3:51 AM, Srinath Mannam
> <srinath.mannam@broadcom.com> wrote:
>> Hi Rob Herring,
>>
>> Thank you for the review.
>> Please find my answers inline..
>>
>> On Thu, May 31, 2018 at 10:18 PM, Rob Herring <robh@kernel.org> wrote:
>>> On Mon, May 28, 2018 at 11:11:22AM +0530, Srinath Mannam wrote:
>>>> From: Pramod Kumar <pramod.kumar@broadcom.com>
>>>>
>>>> Add binding document for supported thermal implementation
>>>> in Stingray.
>>>>
>>>> Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
>>>> Reviewed-by: Ray Jui <ray.jui@broadcom.com>
>>>> Reviewed-by: Scott Branden <scott.branden@broadcom.com>
>>>> Reviewed-by: Srinath Mannam <srinath.mannam@broadcom.com>
>>>> ---
>>>> .../bindings/thermal/brcm,sr-thermal.txt | 45 ++++++++++++++++++++++
>>>> 1 file changed, 45 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/thermal/brcm,sr-thermal.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/thermal/brcm,sr-thermal.txt b/Documentation/devicetree/bindings/thermal/brcm,sr-thermal.txt
>>>> new file mode 100644
>>>> index 0000000..33f9e11
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/thermal/brcm,sr-thermal.txt
>>>> @@ -0,0 +1,45 @@
>>>> +* Broadcom Stingray Thermal
>>>> +
>>>> +This binding describes thermal sensors that is part of Stingray SoCs.
>>>> +
>>>> +Required properties:
>>>> +- compatible : Must be "brcm,sr-thermal"
>>>> +- reg : memory where tmon data will be available.
>>>
>>> What type of memory is this?
>> This is shared memory(cache-able) which is shared between two micro controllers.
>
> What else is in this shared memory? You should probably be
> representing that as a whole somewhere in DT.
Nothing else except 4 byte memory containing temperature value of one
thermal zone.
At present we configured 6 thermal zones. So six separate 4byte
memories provided in
shared memory.
>
>> One micro controller update temperature of all thermal zones in this
>> shared memory.
>> thermal driver running on another micro controller monitors
>> temperature data of all thermal zones.
>>>
>>>> +
>>>> +Example:
>>>> + tmons {
>>>> + compatible = "simple-bus";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + ranges;
>>>> +
>>>> + tmon_ihost0: thermal@8f100000 {
>>>> + compatible = "brcm,sr-thermal";
>>>> + reg = <0x8f100000 0x4>;
>>>> + };
>>>
>>> Convince me that you need a node per register. This can all be
>>> accomplished with a single node and either a single reg entry or a
>>> series of reg entries.
>>>
>> In our system we have 6 different thermal zones. each node belongs to
>> one thermal zone.
>> thermal driver detects each node as separate thermal zone and monitors
>> separately.
>> register entry is only 4byte memory which contains the temperature
>> value of respective thermal zone.
>> Based on requirement we can increase or decrease the number thermal
>> zones need to monitor.
>
> Still, all this can be accomplished with a single node. Having a node
> per register in DT doesn't scale.
Our approach is like we have individual controllers have one driver
with multiple DT nodes.
In coming future we will add more thermal zones based on our
requirement. then we can just
add new DT node, instead of having driver changes.
With this approach we can configure each thermal zone at different trip values.
So we must have all thermal zones are independent.
>
> Rob
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox