* [PATCH v1 35/50] ARM: dts: exynos: change speed and parent of NoC clock in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
This patch changes speed and parent of NoC WCORE bus to 400MHz. The clock
is now attached to a branch were the root is the DPLL which speed is set to
1200MHz. The OPPs are aligned to this rate accordingly.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 25d95de15c9b..aaf18653d8ac 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -46,6 +46,13 @@
<&nocp_mem1_0>, <&nocp_mem1_1>;
vdd-supply = <&buck3_reg>;
exynos,saturation-ratio = <100>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK400_WCORE>,
+ <&clock CLK_MOUT_SW_ACLK400_WCORE>,
+ <&clock CLK_DOUT_ACLK400_WCORE>,
+ <&clock CLK_FOUT_DPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>,
+ <&clock CLK_DOUT_ACLK400_WCORE>;
+ assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>;
status = "okay";
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 34/50] ARM: dts: exynos: set parent clocks to PWM in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Change the parent of PWM clock to the CPLL which has 666MHz.
The PWM's divider uses /10 rate so it would set 66.6MHz.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 79f635043247..a361dd5a6036 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1473,6 +1473,8 @@
&pwm {
clocks = <&clock CLK_PWM>;
+ assigned-clocks = <&clock CLK_MOUT_PWM>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>;
clock-names = "timers";
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 33/50] ARM: dts: exynos: set parent clocks to UARTs in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Change the parents of UART clocks to the CPLL which has 666MHz.
The UARTs' dividers use /10 rate so they would have 66.6MHz.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 18c5273091bd..79f635043247 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1486,6 +1486,8 @@
&serial_0 {
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
+ assigned-clocks = <&clock CLK_MOUT_UART0>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>;
dmas = <&pdma0 13>, <&pdma0 14>;
dma-names = "rx", "tx";
};
@@ -1493,6 +1495,8 @@
&serial_1 {
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
+ assigned-clocks = <&clock CLK_MOUT_UART1>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>;
dmas = <&pdma1 15>, <&pdma1 16>;
dma-names = "rx", "tx";
};
@@ -1500,6 +1504,8 @@
&serial_2 {
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
+ assigned-clocks = <&clock CLK_MOUT_UART2>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>;
dmas = <&pdma0 15>, <&pdma0 16>;
dma-names = "rx", "tx";
};
@@ -1507,6 +1513,8 @@
&serial_3 {
clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
clock-names = "uart", "clk_uart_baud0";
+ assigned-clocks = <&clock CLK_MOUT_UART3>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>;
dmas = <&pdma1 17>, <&pdma1 18>;
dma-names = "rx", "tx";
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 32/50] ARM: dts: exynos: remove lowest OPP from bus_mfc in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Align number of OPPs with the number in bus_wcore OPP table.
The higher OPPs would not be set, thus clean them.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 0be799f843dc..18c5273091bd 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1171,18 +1171,15 @@
compatible = "operating-points-v2";
opp00 {
- opp-hz = /bits/ 64 <96000000>;
- };
- opp01 {
opp-hz = /bits/ 64 <111000000>;
};
- opp02 {
+ opp01 {
opp-hz = /bits/ 64 <167000000>;
};
- opp03 {
+ opp02 {
opp-hz = /bits/ 64 <222000000>;
};
- opp04 {
+ opp03 {
opp-hz = /bits/ 64 <333000000>;
};
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 31/50] ARM: dts: exynos: align lowest OPP in bus_jpeg in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Make the lowest OPP frequency possible to set using a clock divider keeping
in mind the master clock rate.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index f2e2e77a86d6..0be799f843dc 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1250,7 +1250,7 @@
compatible = "operating-points-v2";
opp00 {
- opp-hz = /bits/ 64 <75000000>;
+ opp-hz = /bits/ 64 <100000000>;
};
opp01 {
opp-hz = /bits/ 64 <150000000>;
--
2.17.1
^ permalink raw reply related
* [PATCH v1 30/50] ARM: dts: exynos: add bus_isp266 into Exynos5800
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The Exynos5420 SoC had one clock for two lines while Exynos5422/5800 have
dedicated clock tree for the ACLK266_ISP. The max frequency is 300MHz so
it shares the OPP table with bus_gen. The bus is added here and is enabled
in .dts file for proper board.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5800.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index 57d3b319fd65..3b9200db43b6 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -131,3 +131,13 @@
&mfc {
compatible = "samsung,mfc-v8";
};
+
+&soc {
+ bus_isp266: bus_isp266 {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK266_ISP>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_gen_opp_table>;
+ status = "disabled";
+ };
+};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 29/50] ARM: dts: exynos: align OPPs of bus_gen in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Align the OPPs' frequencies to the master clock rate such that the values
are possible to set using only a clock divider. Set max OPP frequency equal
to the max possible for that bus (according to the documentation).
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 3a128cd717e2..f2e2e77a86d6 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1191,16 +1191,16 @@
compatible = "operating-points-v2";
opp00 {
- opp-hz = /bits/ 64 <89000000>;
+ opp-hz = /bits/ 64 <100000000>;
};
opp01 {
- opp-hz = /bits/ 64 <133000000>;
+ opp-hz = /bits/ 64 <150000000>;
};
opp02 {
- opp-hz = /bits/ 64 <178000000>;
+ opp-hz = /bits/ 64 <200000000>;
};
opp03 {
- opp-hz = /bits/ 64 <267000000>;
+ opp-hz = /bits/ 64 <300000000>;
};
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 28/50] ARM: dts: exynos: change OPPs for g2d and g2d_acp buses in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Align the frequencies in OPPs to values which are possible to set using
a divider and parent clock rate. Keep the OPP number in the table equal
or less to the number in bus_wcore (any higher OPPs would not be set).
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index a355c76af5a5..3a128cd717e2 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1216,7 +1216,7 @@
compatible = "operating-points-v2";
opp00 {
- opp-hz = /bits/ 64 <84000000>;
+ opp-hz = /bits/ 64 <110000000>;
};
opp01 {
opp-hz = /bits/ 64 <167000000>;
@@ -1225,9 +1225,6 @@
opp-hz = /bits/ 64 <222000000>;
};
opp03 {
- opp-hz = /bits/ 64 <300000000>;
- };
- opp04 {
opp-hz = /bits/ 64 <333000000>;
};
};
@@ -1236,16 +1233,16 @@
compatible = "operating-points-v2";
opp00 {
- opp-hz = /bits/ 64 <67000000>;
+ opp-hz = /bits/ 64 <100000000>;
};
opp01 {
- opp-hz = /bits/ 64 <133000000>;
+ opp-hz = /bits/ 64 <150000000>;
};
opp02 {
- opp-hz = /bits/ 64 <178000000>;
+ opp-hz = /bits/ 64 <200000000>;
};
opp03 {
- opp-hz = /bits/ 64 <267000000>;
+ opp-hz = /bits/ 64 <300000000>;
};
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 27/50] ARM: dts: exynos: align bus_wcore OPPs in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
This is the most important bus in the Exynos5x SoC. The whole communication
inside SoC does through that bus (apart from direct requests from CCI to
DRAM controller). It is also modeled as a master bus in devfreq framework.
It is also the only one OPP table throughout other buses which has voltage
values. The devfreq software controls the speed of that bus and other
buses. The other buses follows the rate of the master. There is only one
regulator. The old lowest OPP had pair 925mV, 84MHz which is enough for
this frequency. However, due to the fact that the other buses follows the
WCORE bus by taking the OPP from their table with the same id, e.g. opp02,
the children frequency should be stable with the set voltage.
It could cause random faults very hard to debug.
Thus, the patch removes the lowest OPP to make other buses' lowest OPPs
working. The new lowest OPP has voltage high enough for buses working up
to 333MHz. It also changes the frequencies of the OPPs to align them to
PLL value such that it is possible to set them using only a divider without
reprogramming OPP. Reprogramming the PLL was not set, so the real frequency
values were not the one from the OPP table, which could confuse the
governor algorithms which relay on OPP speed values making the system to
behave weird.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index f8c36ff0d4c3..a355c76af5a5 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1107,22 +1107,18 @@
compatible = "operating-points-v2";
opp00 {
- opp-hz = /bits/ 64 <84000000>;
- opp-microvolt = <925000>;
+ opp-hz = /bits/ 64 <150000000>;
+ opp-microvolt = <950000>;
};
opp01 {
- opp-hz = /bits/ 64 <111000000>;
+ opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <950000>;
};
opp02 {
- opp-hz = /bits/ 64 <222000000>;
+ opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <950000>;
};
opp03 {
- opp-hz = /bits/ 64 <333000000>;
- opp-microvolt = <950000>;
- };
- opp04 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <987500>;
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 26/50] ARM: dts: exynos: align NOC100 bus OPPs in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The NOC100 has a parent which clock rate is set tot 400MHz. The OPPs which
are not possible to set are removed and new one is added.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 1097fa758d9e..f8c36ff0d4c3 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1135,12 +1135,9 @@
opp-hz = /bits/ 64 <67000000>;
};
opp01 {
- opp-hz = /bits/ 64 <75000000>;
+ opp-hz = /bits/ 64 <80000000>;
};
opp02 {
- opp-hz = /bits/ 64 <86000000>;
- };
- opp03 {
opp-hz = /bits/ 64 <100000000>;
};
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 25/50] ARM: dts: exynos: add 300MHz to bus_disp1_fimd in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
According to the documentation max frequency for ACLK300_DISP1 is 300MHz.
Add an OPP which makes it possible to use the full performance when needed.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 74d014f3eaa6..1097fa758d9e 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1299,6 +1299,9 @@
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
+ opp02 {
+ opp-hz = /bits/ 64 <300000000>;
+ };
};
bus_disp1_opp_table: opp_table14 {
--
2.17.1
^ permalink raw reply related
* [PATCH v1 24/50] ARM: dts: exynos: align OPPs with PLL rate for MSCL in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The OPPs must reflect possible values after dividing the master clock.
The old values 400 and 333, 222, etc does not have common parent rate.
Thus, align the values to parent rate such that they will be set exactly
using only a divider.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 0739e7bd4628..74d014f3eaa6 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1336,18 +1336,15 @@
compatible = "operating-points-v2";
opp00 {
- opp-hz = /bits/ 64 <84000000>;
+ opp-hz = /bits/ 64 <150000000>;
};
opp01 {
- opp-hz = /bits/ 64 <167000000>;
+ opp-hz = /bits/ 64 <200000000>;
};
opp02 {
- opp-hz = /bits/ 64 <222000000>;
+ opp-hz = /bits/ 64 <300000000>;
};
opp03 {
- opp-hz = /bits/ 64 <333000000>;
- };
- opp04 {
opp-hz = /bits/ 64 <400000000>;
};
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 23/50] ARM: dts: exynos: change lowest OPP in bus_disp1_fimd in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The lowest OPP must be aligned to possible value after division of parent
clock rate. Thus, change it to the value which is true for clock 1200MHz.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 6e82ffcbeacd..0739e7bd4628 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1294,7 +1294,7 @@
compatible = "operating-points-v2";
opp00 {
- opp-hz = /bits/ 64 <120000000>;
+ opp-hz = /bits/ 64 <150000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
--
2.17.1
^ permalink raw reply related
* [PATCH v1 22/50] ARM: dts: exynos: OPPs for bus_disp1 in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Update the bus_disp1 OPPs and add 400MHz which is max frequency for this
bus. The frequencies are aligned to parent clock such that it is not
needed to change the PLL rate.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 2b36c2f77a10..6e82ffcbeacd 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1305,7 +1305,7 @@
compatible = "operating-points-v2";
opp00 {
- opp-hz = /bits/ 64 <120000000>;
+ opp-hz = /bits/ 64 <150000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
@@ -1313,6 +1313,9 @@
opp02 {
opp-hz = /bits/ 64 <300000000>;
};
+ opp03 {
+ opp-hz = /bits/ 64 <400000000>;
+ };
};
bus_gscl_opp_table: opp_table15 {
--
2.17.1
^ permalink raw reply related
* [PATCH v1 21/50] ARM: dts: exynos: add OPP into FSYS APB bus in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Add an OPP for FSYS APB which reflects the real possible frequency.
The bus will have a new parent clock which speed has 600MHz, thus
a new possible frequency provided by the clock divider is 150MHz.
According to the documentation max possible frequency for this bus is
200MHz.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index c7fc4b829b2a..2b36c2f77a10 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1153,6 +1153,9 @@
opp-hz = /bits/ 64 <100000000>;
};
opp01 {
+ opp-hz = /bits/ 64 <150000000>;
+ };
+ opp02 {
opp-hz = /bits/ 64 <200000000>;
};
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 20/50] ARM: dts: exynos: change and rename FSYS OPP table in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The FSYS and FSYS2 buses have similar characteristics and both have max
frequency 240MHz. The old OPP table bus_fsys_apb_opp_table should be used
only to FSYS APB bus because APB max frequency is 200MHz.
The new OPPs for FSYS should increase its performance and related devices.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 941c58bdd809..c7fc4b829b2a 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -995,7 +995,7 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
clock-names = "bus";
- operating-points-v2 = <&bus_fsys_apb_opp_table>;
+ operating-points-v2 = <&bus_fsys_opp_table>;
status = "disabled";
};
@@ -1003,7 +1003,7 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
clock-names = "bus";
- operating-points-v2 = <&bus_fsys2_opp_table>;
+ operating-points-v2 = <&bus_fsys_opp_table>;
status = "disabled";
};
@@ -1157,7 +1157,7 @@
};
};
- bus_fsys2_opp_table: opp_table5 {
+ bus_fsys_opp_table: opp_table5 {
compatible = "operating-points-v2";
opp00 {
--
2.17.1
^ permalink raw reply related
* [PATCH v1 19/50] ARM: dts: exynos: change OPPs values for FSYS2 in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The OPPs values for FSYS2 does not reflect the real possible frequencies.
According to the documentation the maximum frequency is 240MHz. This clock
is important to MMC controller controlling the AXI data bus speed and
internal buses. The new OPP values are aligned to parent PLL rate so that
there is no need of reprogramming PLL and the integer values are possible
to get using only a clock divider.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 1b717c5c3b1a..941c58bdd809 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1161,13 +1161,13 @@
compatible = "operating-points-v2";
opp00 {
- opp-hz = /bits/ 64 <75000000>;
+ opp-hz = /bits/ 64 <150000000>;
};
opp01 {
- opp-hz = /bits/ 64 <100000000>;
+ opp-hz = /bits/ 64 <200000000>;
};
opp02 {
- opp-hz = /bits/ 64 <150000000>;
+ opp-hz = /bits/ 64 <240000000>;
};
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 18/50] ARM: dts: exynos: add bus_isp with OPP table
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Add bus_isp which controls ACLK400_ISP clock. The OPPs are aligned to
parent clock and PLL rate so that the PLL would not need to be
reprogrammed.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 5fb2326875dc..1b717c5c3b1a 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1095,6 +1095,14 @@
status = "disabled";
};
+ bus_isp: bus_isp {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK400_ISP>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_isp_opp_table>;
+ status = "disabled";
+ };
+
bus_wcore_opp_table: opp_table2 {
compatible = "operating-points-v2";
@@ -1337,6 +1345,23 @@
opp-hz = /bits/ 64 <400000000>;
};
};
+
+ bus_isp_opp_table: opp_table17 {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <150000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <300000000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <400000000>;
+ };
+ };
};
thermal-zones {
--
2.17.1
^ permalink raw reply related
* [PATCH v1 17/50] clk: samsung: add CLK_MOUT_MMC0 in the Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Add ID to mout_mmc0 MUX to make possible children connection in
the DT.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index ead569a164cf..8d58801baf2c 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -763,7 +763,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
/* FSYS Block */
MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
- MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
+ MUX(CLK_MOUT_MMC0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
--
2.17.1
^ permalink raw reply related
* [PATCH v1 16/50] clk: samsung: add SPLL rate table in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The MPLL has fixed frequency left by the bootloader and it is not possible
to change it. With this patch the SPLL gets rate table the same for the
whole PLL family (similar as APLL, KPLL according to RM) so the frequency
might be changed to one of the values defined there.
It is needed for further patches which change the MPLL frequency to feed
the clocks with proper base.
It also sets CLK_IS_CRITICAL for SCLK_SPLL due to some drivers which could
disable master clock, which is then populated higher and tries to disable
PLL, which casues system crash. The flag is needed for this kind of use
cases.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index cded46f360f1..ead569a164cf 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -690,7 +690,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX_F(CLK_MOUT_SCLK_MPLL, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1,
CLK_IS_CRITICAL, 0),
MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
- MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
+ MUX_F(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1,
+ CLK_IS_CRITICAL, 0),
MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
@@ -1520,6 +1521,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
exynos5x_plls[mpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ exynos5x_plls[spll].rate_table = exynos5420_pll2550x_24mhz_tbl;
}
if (soc == EXYNOS5420)
--
2.17.1
^ permalink raw reply related
* [PATCH v1 15/50] clk: samsung: add MPLL rate table in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The MPLL has fixed frequency left by the bootloader and it is not possible
to change it. With this patch the MPLL gets rate table the same for the
whole PLL family (similar as APLL, KPLL according to RM) so the frequency
might be changed to one of the values defined there.
It is needed for further patches which change the MPLL frequency to feed
the clocks with proper base.
It also sets CLK_IS_CRITICAL for SCLK_MPLL due to some drivers which could
disable master clock, which is then populated higher and tries to disable
PLL, which casues system crash. The flag is needed for this kind of use
cases.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 6d1a0ef9172e..cded46f360f1 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -687,7 +687,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
- MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
+ MUX_F(CLK_MOUT_SCLK_MPLL, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1,
+ CLK_IS_CRITICAL, 0),
MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
@@ -1518,6 +1519,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
exynos5x_plls[dpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ exynos5x_plls[mpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
}
if (soc == EXYNOS5420)
--
2.17.1
^ permalink raw reply related
* [PATCH v1 14/50] clk: samsung: add CLK_MOUT_SCLK_CPLL in the Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Add ID to mout_sclk_cpll MUX to make possible children connection in
the DT.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 2395b02ce8c5..6d1a0ef9172e 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -696,7 +696,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
CLK_SET_RATE_PARENT, 0),
MUX_F(CLK_MOUT_SCLK_DPLL, "mout_sclk_dpll", mout_dpll_p,
SRC_TOP6, 24, 1, CLK_IS_CRITICAL, 0),
- MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
+ MUX(CLK_MOUT_SCLK_CPLL, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
MUX(CLK_MOUT_SW_ACLK400_ISP, "mout_sw_aclk400_isp",
mout_sw_aclk400_isp_p, SRC_TOP10, 0, 1),
--
2.17.1
^ permalink raw reply related
* [PATCH v1 13/50] clk: samsung: add DPLL rate table in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The DPLL has fixed frequency left by the bootloader and it is not possible
to change it. With this patch the DPLL gets rate table the same for the
whole PLL family (similar as APLL, KPLL according to RM) so the frequency
might be changed to one of the values defined there.
It is needed for further patches which change the DPLL frequency to feed
the clocks with proper base.
It also sets CLK_IS_CRITICAL for SCLK_DPLL due to some drivers which could
disable master clock, which is then populated higher and tries to disable
PLL, which casues system crash. The flag is needed for this kind of use
cases.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 7f8221527633..2395b02ce8c5 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -694,7 +694,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
CLK_SET_RATE_PARENT, 0),
- MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
+ MUX_F(CLK_MOUT_SCLK_DPLL, "mout_sclk_dpll", mout_dpll_p,
+ SRC_TOP6, 24, 1, CLK_IS_CRITICAL, 0),
MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
MUX(CLK_MOUT_SW_ACLK400_ISP, "mout_sw_aclk400_isp",
@@ -1514,6 +1515,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
if (_get_rate("fin_pll") == 24 * MHZ) {
exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ exynos5x_plls[dpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
}
--
2.17.1
^ permalink raw reply related
* [PATCH v1 12/50] clk: add ID to PWM MUX in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Add ID to PWM MUX to manage it from DT to reflect proper topology.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 7bf74401c4e7..7f8221527633 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -772,7 +772,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX(CLK_MOUT_UART1, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
MUX(CLK_MOUT_UART2, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
MUX(CLK_MOUT_UART3, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
- MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
+ MUX(CLK_MOUT_PWM, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
--
2.17.1
^ permalink raw reply related
* [PATCH v1 11/50] clk: samsung: add IDs to UART clocks in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Add IDs to MUXes for UART to manage them from DT.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index c13f34d3d9a1..7bf74401c4e7 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -768,10 +768,10 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
/* PERIC Block */
- MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
- MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
- MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
- MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
+ MUX(CLK_MOUT_UART0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
+ MUX(CLK_MOUT_UART1, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
+ MUX(CLK_MOUT_UART2, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
+ MUX(CLK_MOUT_UART3, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
--
2.17.1
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox