* [PATCH v3 4/4] edac: Add support for Amazon's Annapurna Labs L2 EDAC
From: Hanna Hawa @ 2019-07-15 13:24 UTC (permalink / raw)
To: robh+dt, mark.rutland, bp, mchehab, james.morse, davem, gregkh,
linus.walleij, Jonathan.Cameron, nicolas.ferre, paulmck
Cc: dwmw, benh, ronenk, talel, jonnyc, hanochu, devicetree,
linux-kernel, linux-edac, hhhawa
In-Reply-To: <1563197049-12679-1-git-send-email-hhhawa@amazon.com>
Adds support for Amazon's Annapurna Labs L2 EDAC driver to detect and
report L2 errors.
Signed-off-by: Hanna Hawa <hhhawa@amazon.com>
---
MAINTAINERS | 6 ++
drivers/edac/Kconfig | 8 ++
drivers/edac/Makefile | 1 +
drivers/edac/al_l2_edac.c | 187 ++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 202 insertions(+)
create mode 100644 drivers/edac/al_l2_edac.c
diff --git a/MAINTAINERS b/MAINTAINERS
index fd29ea6..a6dcf3d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -749,6 +749,12 @@ S: Maintained
F: drivers/edac/al_l1_edac.c
F: Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt
+AMAZON ANNAPURNA LABS L2 EDAC
+M: Hanna Hawa <hhhawa@amazon.com>
+S: Maintained
+F: drivers/edac/al_l2_edac.c
+F: Documentation/devicetree/bindings/edac/amazon,al-l2-edac.txt
+
AMAZON ANNAPURNA LABS THERMAL MMIO DRIVER
M: Talel Shenhar <talel@amazon.com>
S: Maintained
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 58b92bc..8bbb745 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -82,6 +82,14 @@ config EDAC_AL_L1
for Amazon's Annapurna Labs SoCs.
This driver detects errors of L1 caches.
+config EDAC_AL_L2
+ bool "Amazon's Annapurna Labs L2 EDAC"
+ depends on ARCH_ALPINE
+ help
+ Support for L2 error detection and correction
+ for Amazon's Annapurna Labs SoCs.
+ This driver detects errors of L2 caches.
+
config EDAC_AMD64
tristate "AMD64 (Opteron, Athlon64)"
depends on AMD_NB && EDAC_DECODE_MCE
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index caa2dc9..60a6b8b 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -23,6 +23,7 @@ edac_mce_amd-y := mce_amd.o
obj-$(CONFIG_EDAC_DECODE_MCE) += edac_mce_amd.o
obj-$(CONFIG_EDAC_AL_L1) += al_l1_edac.o
+obj-$(CONFIG_EDAC_AL_L2) += al_l2_edac.o
obj-$(CONFIG_EDAC_AMD76X) += amd76x_edac.o
obj-$(CONFIG_EDAC_CPC925) += cpc925_edac.o
obj-$(CONFIG_EDAC_I5000) += i5000_edac.o
diff --git a/drivers/edac/al_l2_edac.c b/drivers/edac/al_l2_edac.c
new file mode 100644
index 0000000..bae1ea9
--- /dev/null
+++ b/drivers/edac/al_l2_edac.c
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/of.h>
+
+#include "edac_device.h"
+#include "edac_module.h"
+
+#define DRV_NAME "al_l2_edac"
+
+/* Same bit assignments of L2MERRSR_EL1 in ARM CA57/CA72 */
+#define ARM_CA57_L2MERRSR_EL1 sys_reg(3, 1, 15, 2, 3)
+#define ARM_CA57_L2MERRSR_RAMID GENMASK(30, 24)
+#define ARM_CA57_L2_TAG_RAM 0x10
+#define ARM_CA57_L2_DATA_RAM 0x11
+#define ARM_CA57_L2_SNOOP_RAM 0x12
+#define ARM_CA57_L2_DIRTY_RAM 0x14
+#define ARM_CA57_L2_INC_PF_RAM 0x18
+#define ARM_CA57_L2MERRSR_VALID BIT(31)
+#define ARM_CA57_L2MERRSR_REPEAT GENMASK_ULL(39, 32)
+#define ARM_CA57_L2MERRSR_OTHER GENMASK_ULL(47, 40)
+#define ARM_CA57_L2MERRSR_FATAL BIT_ULL(63)
+
+#define AL_L2_EDAC_MSG_MAX 256
+
+struct al_l2_edac {
+ cpumask_t cluster_cpus;
+};
+
+static void al_l2_edac_l2merrsr(void *arg)
+{
+ struct edac_device_ctl_info *edac_dev = arg;
+ int cpu, i;
+ u32 ramid, repeat, other, fatal;
+ u64 val = read_sysreg_s(ARM_CA57_L2MERRSR_EL1);
+ char msg[AL_L2_EDAC_MSG_MAX];
+ int space, count;
+ char *p;
+
+ if (!(FIELD_GET(ARM_CA57_L2MERRSR_VALID, val)))
+ return;
+
+ cpu = smp_processor_id();
+ ramid = FIELD_GET(ARM_CA57_L2MERRSR_RAMID, val);
+ repeat = FIELD_GET(ARM_CA57_L2MERRSR_REPEAT, val);
+ other = FIELD_GET(ARM_CA57_L2MERRSR_OTHER, val);
+ fatal = FIELD_GET(ARM_CA57_L2MERRSR_FATAL, val);
+
+ space = sizeof(msg);
+ p = msg;
+ count = snprintf(p, space, "CPU%d L2 %serror detected", cpu,
+ (fatal) ? "Fatal " : "");
+ p += count;
+ space -= count;
+
+ switch (ramid) {
+ case ARM_CA57_L2_TAG_RAM:
+ count = snprintf(p, space, " RAMID='L2 Tag RAM'");
+ break;
+ case ARM_CA57_L2_DATA_RAM:
+ count = snprintf(p, space, " RAMID='L2 Data RAM'");
+ break;
+ case ARM_CA57_L2_SNOOP_RAM:
+ count = snprintf(p, space, " RAMID='L2 Snoop RAM'");
+ break;
+ case ARM_CA57_L2_DIRTY_RAM:
+ count = snprintf(p, space, " RAMID='L2 Dirty RAM'");
+ break;
+ case ARM_CA57_L2_INC_PF_RAM:
+ count = snprintf(p, space, " RAMID='L2 internal metadat'");
+ break;
+ default:
+ count = snprintf(p, space, " RAMID='unknown'");
+ break;
+ }
+
+ p += count;
+ space -= count;
+
+ count = snprintf(p, space,
+ " repeat=%d, other=%d (L2MERRSR_EL1=0x%llx)",
+ repeat, other, val);
+
+ for (i = 0; i < repeat; i++) {
+ if (fatal)
+ edac_device_handle_ue(edac_dev, 0, 0, msg);
+ else
+ edac_device_handle_ce(edac_dev, 0, 0, msg);
+ }
+
+ write_sysreg_s(0, ARM_CA57_L2MERRSR_EL1);
+}
+
+static void al_l2_edac_check(struct edac_device_ctl_info *edac_dev)
+{
+ struct al_l2_edac *al_l2 = edac_dev->pvt_info;
+
+ smp_call_function_any(&al_l2->cluster_cpus, al_l2_edac_l2merrsr,
+ edac_dev, 1);
+}
+
+static int al_l2_edac_probe(struct platform_device *pdev)
+{
+ struct edac_device_ctl_info *edac_dev;
+ struct al_l2_edac *al_l2;
+ struct device *dev = &pdev->dev;
+ int ret, i;
+
+ edac_dev = edac_device_alloc_ctl_info(sizeof(*al_l2),
+ (char *)dev_name(dev), 1, "L", 1,
+ 2, NULL, 0,
+ edac_device_alloc_index());
+ if (IS_ERR(edac_dev))
+ return -ENOMEM;
+
+ al_l2 = edac_dev->pvt_info;
+ edac_dev->edac_check = al_l2_edac_check;
+ edac_dev->dev = dev;
+ edac_dev->mod_name = DRV_NAME;
+ edac_dev->dev_name = dev_name(dev);
+ edac_dev->ctl_name = "L2 cache";
+ platform_set_drvdata(pdev, edac_dev);
+
+ for_each_online_cpu(i) {
+ struct device_node *cpu;
+ struct device_node *cpu_cache, *l2_cache;
+
+ cpu = of_get_cpu_node(i, NULL);
+ cpu_cache = of_find_next_cache_node(cpu);
+ l2_cache = of_parse_phandle(dev->of_node, "l2-cache", 0);
+
+ if (cpu_cache == l2_cache)
+ cpumask_set_cpu(i, &al_l2->cluster_cpus);
+ }
+
+ if (cpumask_empty(&al_l2->cluster_cpus)) {
+ dev_err(dev, "CPU mask is empty for this L2 cache\n");
+ ret = -EINVAL;
+ goto err;
+ }
+
+ ret = edac_device_add_device(edac_dev);
+ if (ret) {
+ dev_err(dev, "Failed to add L2 edac device\n");
+ goto err;
+ }
+
+ return 0;
+
+err:
+ edac_device_free_ctl_info(edac_dev);
+
+ return ret;
+}
+
+static int al_l2_edac_remove(struct platform_device *pdev)
+{
+ struct edac_device_ctl_info *edac_dev = platform_get_drvdata(pdev);
+
+ edac_device_del_device(edac_dev->dev);
+ edac_device_free_ctl_info(edac_dev);
+
+ return 0;
+}
+
+static const struct of_device_id al_l2_edac_of_match[] = {
+ { .compatible = "amazon,al-l2-edac" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, al_l2_edac_of_match);
+
+static struct platform_driver al_l2_edac_driver = {
+ .probe = al_l2_edac_probe,
+ .remove = al_l2_edac_remove,
+ .driver = {
+ .name = DRV_NAME,
+ .of_match_table = al_l2_edac_of_match,
+ },
+};
+module_platform_driver(al_l2_edac_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Hanna Hawa <hhhawa@amazon.com>");
+MODULE_DESCRIPTION("Amazon's Annapurna Lab's L2 EDAC Driver");
--
2.7.4
^ permalink raw reply related
* [PATCH v3 3/4] dt-bindings: EDAC: Add Amazon's Annapurna Labs L2 EDAC
From: Hanna Hawa @ 2019-07-15 13:24 UTC (permalink / raw)
To: robh+dt, mark.rutland, bp, mchehab, james.morse, davem, gregkh,
linus.walleij, Jonathan.Cameron, nicolas.ferre, paulmck
Cc: dwmw, benh, ronenk, talel, jonnyc, hanochu, devicetree,
linux-kernel, linux-edac, hhhawa
In-Reply-To: <1563197049-12679-1-git-send-email-hhhawa@amazon.com>
Document Amazon's Annapurna Labs L2 EDAC SoC binding.
Signed-off-by: Hanna Hawa <hhhawa@amazon.com>
---
.../devicetree/bindings/edac/amazon,al-l2-edac.txt | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 Documentation/devicetree/bindings/edac/amazon,al-l2-edac.txt
diff --git a/Documentation/devicetree/bindings/edac/amazon,al-l2-edac.txt b/Documentation/devicetree/bindings/edac/amazon,al-l2-edac.txt
new file mode 100644
index 0000000..7b0b734
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/amazon,al-l2-edac.txt
@@ -0,0 +1,20 @@
+* Amazon's Annapurna Labs L2 EDAC
+
+Amazon's Annapurna Labs SoCs supports L2 single bit correction and
+two bits detection capability based on ARM implementation.
+
+Required properties:
+- compatible:
+ should be "amazon,al-l2-edac".
+- l2-cache:
+ Phandle to L2 cache handler.
+ This property is used to compare with the CPU node property
+ 'next-level-cache' to create cpu-mask with all CPUs that
+ share same L2 cache.
+
+Example:
+
+ al_l2_edac {
+ compatible = "amazon,al-l2-edac";
+ l2-cache = <&cluster0_l2>;
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH v3 2/4] edac: Add support for Amazon's Annapurna Labs L1 EDAC
From: Hanna Hawa @ 2019-07-15 13:24 UTC (permalink / raw)
To: robh+dt, mark.rutland, bp, mchehab, james.morse, davem, gregkh,
linus.walleij, Jonathan.Cameron, nicolas.ferre, paulmck
Cc: dwmw, benh, ronenk, talel, jonnyc, hanochu, devicetree,
linux-kernel, linux-edac, hhhawa
In-Reply-To: <1563197049-12679-1-git-send-email-hhhawa@amazon.com>
Adds support for Amazon's Annapurna Labs L1 EDAC driver to detect and
report L1 errors.
Signed-off-by: Hanna Hawa <hhhawa@amazon.com>
---
MAINTAINERS | 6 ++
drivers/edac/Kconfig | 8 +++
drivers/edac/Makefile | 1 +
drivers/edac/al_l1_edac.c | 156 ++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 171 insertions(+)
create mode 100644 drivers/edac/al_l1_edac.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 77eae44..fd29ea6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -743,6 +743,12 @@ F: drivers/tty/serial/altera_jtaguart.c
F: include/linux/altera_uart.h
F: include/linux/altera_jtaguart.h
+AMAZON ANNAPURNA LABS L1 EDAC
+M: Hanna Hawa <hhhawa@amazon.com>
+S: Maintained
+F: drivers/edac/al_l1_edac.c
+F: Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt
+
AMAZON ANNAPURNA LABS THERMAL MMIO DRIVER
M: Talel Shenhar <talel@amazon.com>
S: Maintained
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 200c04c..58b92bc 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -74,6 +74,14 @@ config EDAC_GHES
In doubt, say 'Y'.
+config EDAC_AL_L1
+ bool "Amazon's Annapurna Labs L1 EDAC"
+ depends on ARCH_ALPINE
+ help
+ Support for L1 error detection and correction
+ for Amazon's Annapurna Labs SoCs.
+ This driver detects errors of L1 caches.
+
config EDAC_AMD64
tristate "AMD64 (Opteron, Athlon64)"
depends on AMD_NB && EDAC_DECODE_MCE
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 165ca65e..caa2dc9 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_EDAC_GHES) += ghes_edac.o
edac_mce_amd-y := mce_amd.o
obj-$(CONFIG_EDAC_DECODE_MCE) += edac_mce_amd.o
+obj-$(CONFIG_EDAC_AL_L1) += al_l1_edac.o
obj-$(CONFIG_EDAC_AMD76X) += amd76x_edac.o
obj-$(CONFIG_EDAC_CPC925) += cpc925_edac.o
obj-$(CONFIG_EDAC_I5000) += i5000_edac.o
diff --git a/drivers/edac/al_l1_edac.c b/drivers/edac/al_l1_edac.c
new file mode 100644
index 0000000..70510ea
--- /dev/null
+++ b/drivers/edac/al_l1_edac.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ */
+
+#include <linux/bitfield.h>
+
+#include "edac_device.h"
+#include "edac_module.h"
+
+#define DRV_NAME "al_l1_edac"
+
+/* Same bit assignments of CPUMERRSR_EL1 in ARM CA57/CA72 */
+#define ARM_CA57_CPUMERRSR_EL1 sys_reg(3, 1, 15, 2, 2)
+#define ARM_CA57_CPUMERRSR_RAM_ID GENMASK(30, 24)
+#define ARM_CA57_L1_I_TAG_RAM 0x00
+#define ARM_CA57_L1_I_DATA_RAM 0x01
+#define ARM_CA57_L1_D_TAG_RAM 0x08
+#define ARM_CA57_L1_D_DATA_RAM 0x09
+#define ARM_CA57_L2_TLB_RAM 0x18
+#define ARM_CA57_CPUMERRSR_VALID BIT(31)
+#define ARM_CA57_CPUMERRSR_REPEAT GENMASK_ULL(39, 32)
+#define ARM_CA57_CPUMERRSR_OTHER GENMASK_ULL(47, 40)
+#define ARM_CA57_CPUMERRSR_FATAL BIT_ULL(63)
+
+#define AL_L1_EDAC_MSG_MAX 256
+
+static void al_l1_edac_cpumerrsr(void *arg)
+{
+ struct edac_device_ctl_info *edac_dev = arg;
+ int cpu, i;
+ u32 ramid, repeat, other, fatal;
+ u64 val = read_sysreg_s(ARM_CA57_CPUMERRSR_EL1);
+ char msg[AL_L1_EDAC_MSG_MAX];
+ int space, count;
+ char *p;
+
+ if (!(FIELD_GET(ARM_CA57_CPUMERRSR_VALID, val)))
+ return;
+
+ cpu = smp_processor_id();
+ ramid = FIELD_GET(ARM_CA57_CPUMERRSR_RAM_ID, val);
+ repeat = FIELD_GET(ARM_CA57_CPUMERRSR_REPEAT, val);
+ other = FIELD_GET(ARM_CA57_CPUMERRSR_OTHER, val);
+ fatal = FIELD_GET(ARM_CA57_CPUMERRSR_FATAL, val);
+
+ space = sizeof(msg);
+ p = msg;
+ count = snprintf(p, space, "CPU%d L1 %serror detected", cpu,
+ (fatal) ? "Fatal " : "");
+ p += count;
+ space -= count;
+
+ switch (ramid) {
+ case ARM_CA57_L1_I_TAG_RAM:
+ count = snprintf(p, space, " RAMID='L1-I Tag RAM'");
+ break;
+ case ARM_CA57_L1_I_DATA_RAM:
+ count = snprintf(p, space, " RAMID='L1-I Data RAM'");
+ break;
+ case ARM_CA57_L1_D_TAG_RAM:
+ count = snprintf(p, space, " RAMID='L1-D Tag RAM'");
+ break;
+ case ARM_CA57_L1_D_DATA_RAM:
+ count = snprintf(p, space, " RAMID='L1-D Data RAM'");
+ break;
+ case ARM_CA57_L2_TLB_RAM:
+ count = snprintf(p, space, " RAMID='L2 TLB RAM'");
+ break;
+ default:
+ count = snprintf(p, space, " RAMID='unknown'");
+ break;
+ }
+
+ p += count;
+ space -= count;
+ count = snprintf(p, space,
+ " repeat=%d, other=%d (CPUMERRSR_EL1=0x%llx)",
+ repeat, other, val);
+
+ for (i = 0; i < repeat; i++) {
+ if (fatal)
+ edac_device_handle_ue(edac_dev, 0, 0, msg);
+ else
+ edac_device_handle_ce(edac_dev, 0, 0, msg);
+ }
+
+ write_sysreg_s(0, ARM_CA57_CPUMERRSR_EL1);
+}
+
+static void al_l1_edac_check(struct edac_device_ctl_info *edac_dev)
+{
+ on_each_cpu(al_l1_edac_cpumerrsr, edac_dev, 1);
+}
+
+static int al_l1_edac_probe(struct platform_device *pdev)
+{
+ struct edac_device_ctl_info *edac_dev;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ edac_dev = edac_device_alloc_ctl_info(0, (char *)dev_name(dev), 1, "L",
+ 1, 1, NULL, 0,
+ edac_device_alloc_index());
+ if (IS_ERR(edac_dev))
+ return -ENOMEM;
+
+ edac_dev->edac_check = al_l1_edac_check;
+ edac_dev->dev = dev;
+ edac_dev->mod_name = DRV_NAME;
+ edac_dev->dev_name = dev_name(dev);
+ edac_dev->ctl_name = "L1 cache";
+ platform_set_drvdata(pdev, edac_dev);
+
+ ret = edac_device_add_device(edac_dev);
+ if (ret) {
+ dev_err(dev, "Failed to add L1 edac device\n");
+ goto err;
+ }
+
+ return 0;
+err:
+ edac_device_free_ctl_info(edac_dev);
+
+ return ret;
+}
+
+static int al_l1_edac_remove(struct platform_device *pdev)
+{
+ struct edac_device_ctl_info *edac_dev = platform_get_drvdata(pdev);
+
+ edac_device_del_device(edac_dev->dev);
+ edac_device_free_ctl_info(edac_dev);
+
+ return 0;
+}
+
+static const struct of_device_id al_l1_edac_of_match[] = {
+ { .compatible = "amazon,al-l1-edac" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, al_l1_edac_of_match);
+
+static struct platform_driver al_l1_edac_driver = {
+ .probe = al_l1_edac_probe,
+ .remove = al_l1_edac_remove,
+ .driver = {
+ .name = DRV_NAME,
+ .of_match_table = al_l1_edac_of_match,
+ },
+};
+module_platform_driver(al_l1_edac_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Hanna Hawa <hhhawa@amazon.com>");
+MODULE_DESCRIPTION("Amazon's Annapurna Lab's L1 EDAC Driver");
--
2.7.4
^ permalink raw reply related
* [PATCH v3 1/4] dt-bindings: EDAC: Add Amazon's Annapurna Labs L1 EDAC
From: Hanna Hawa @ 2019-07-15 13:24 UTC (permalink / raw)
To: robh+dt, mark.rutland, bp, mchehab, james.morse, davem, gregkh,
linus.walleij, Jonathan.Cameron, nicolas.ferre, paulmck
Cc: dwmw, benh, ronenk, talel, jonnyc, hanochu, devicetree,
linux-kernel, linux-edac, hhhawa
In-Reply-To: <1563197049-12679-1-git-send-email-hhhawa@amazon.com>
Document Amazon's Annapurna Labs L1 EDAC SoC binding.
Signed-off-by: Hanna Hawa <hhhawa@amazon.com>
---
.../devicetree/bindings/edac/amazon,al-l1-edac.txt | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt
diff --git a/Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt b/Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt
new file mode 100644
index 0000000..2ae8370
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt
@@ -0,0 +1,14 @@
+* Amazon's Annapurna Labs L1 EDAC
+
+Amazon's Annapurna Labs SoCs supports L1 single bit correction and
+two bits detection capability based on ARM implementation.
+
+Required properties:
+- compatible:
+ should be "amazon,al-l1-edac".
+
+Example:
+
+ al_l1_edac {
+ compatible = "amazon,al-l1-edac";
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH v3 0/4] Add support for Amazon's Annapurna Labs EDAC for L1/L2
From: Hanna Hawa @ 2019-07-15 13:24 UTC (permalink / raw)
To: robh+dt, mark.rutland, bp, mchehab, james.morse, davem, gregkh,
linus.walleij, Jonathan.Cameron, nicolas.ferre, paulmck
Cc: dwmw, benh, ronenk, talel, jonnyc, hanochu, devicetree,
linux-kernel, linux-edac, hhhawa
This series adds L1 and L2 caches support for error detection and
correction for Amazon's Annapurna Labs SoCs.
Alpine SoCs supports L1 and L2 single bit correction and two bits detection
capability based on ARM implementation.
Changes since v2:
-----------------
- Use BIT for single bit instead of GENMASK
- Use BIT_ULL and GENMASK_ULL for 64bit vector
- Fix the mod_name/ctrl_name.
Changes since v1:
-----------------
- Split into two drivers
- Get cpu-mask according to l2-cache handler from devicetree
- Remove parameter casting
- Use GENMASK() in bit mask
- Use FIELD_GET()
- Update define description PLRU_RAM -> PF_RAM
- Use sys_reg() and read_sysreg_s()
- Remove all write/read wrappers
- Check fatal field to set if the error correctable or not
- Remove un-relevant information from error prints.
- Update smp_call_function_single() call function to wait
- remove usage of get_online_cpus/put_online_cpus
- Use on_each_cpu() and smp_call_function_any() instead of loop with for_each_cpu.
- use buffer for error prints and pass to edac API
- Remove edac_op_state set
- Add for loop to report on repeated errors of the same type
- Fix error name of the TLB to be L2_TLB as written in ARM TRM
- Minor change in Kconfig
- Minor changes in commit message
Hanna Hawa (4):
dt-bindings: EDAC: Add Amazon's Annapurna Labs L1 EDAC
edac: Add support for Amazon's Annapurna Labs L1 EDAC
dt-bindings: EDAC: Add Amazon's Annapurna Labs L2 EDAC
edac: Add support for Amazon's Annapurna Labs L2 EDAC
.../devicetree/bindings/edac/amazon,al-l1-edac.txt | 14 ++
.../devicetree/bindings/edac/amazon,al-l2-edac.txt | 20 +++
MAINTAINERS | 12 ++
drivers/edac/Kconfig | 16 ++
drivers/edac/Makefile | 2 +
drivers/edac/al_l1_edac.c | 156 +++++++++++++++++
drivers/edac/al_l2_edac.c | 187 +++++++++++++++++++++
7 files changed, 407 insertions(+)
create mode 100644 Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt
create mode 100644 Documentation/devicetree/bindings/edac/amazon,al-l2-edac.txt
create mode 100644 drivers/edac/al_l1_edac.c
create mode 100644 drivers/edac/al_l2_edac.c
--
2.7.4
^ permalink raw reply
* Re: [PATCH 11/13] arm64: dts: qcom: qcs404: Add CPR and populate OPP table
From: Niklas Cassel @ 2019-07-15 13:24 UTC (permalink / raw)
To: Viresh Kumar
Cc: Andy Gross, linux-arm-msm, jorge.ramirez-ortiz, sboyd, vireshk,
bjorn.andersson, ulf.hansson, Rob Herring, Mark Rutland,
devicetree, linux-kernel
In-Reply-To: <20190710090303.tb5ue3wq6r7ofyev@vireshk-i7>
On Wed, Jul 10, 2019 at 02:33:03PM +0530, Viresh Kumar wrote:
> On 05-07-19, 11:57, Niklas Cassel wrote:
> > diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> > cpu_opp_table: cpu-opp-table {
> > - compatible = "operating-points-v2";
> > + compatible = "operating-points-v2-kryo-cpu";
> > opp-shared;
> >
> > opp-1094400000 {
> > opp-hz = /bits/ 64 <1094400000>;
> > - opp-microvolt = <1224000 1224000 1224000>;
> > + required-opps = <&cpr_opp1>;
> > };
> > opp-1248000000 {
> > opp-hz = /bits/ 64 <1248000000>;
> > - opp-microvolt = <1288000 1288000 1288000>;
> > + required-opps = <&cpr_opp2>;
> > };
> > opp-1401600000 {
> > opp-hz = /bits/ 64 <1401600000>;
> > - opp-microvolt = <1384000 1384000 1384000>;
> > + required-opps = <&cpr_opp3>;
> > + };
> > + };
> > +
> > + cpr_opp_table: cpr-opp-table {
> > + compatible = "operating-points-v2-qcom-level";
> > +
> > + cpr_opp1: opp1 {
> > + opp-level = <1>;
> > + qcom,opp-fuse-level = <1>;
> > + opp-hz = /bits/ 64 <1094400000>;
> > + };
> > + cpr_opp2: opp2 {
> > + opp-level = <2>;
> > + qcom,opp-fuse-level = <2>;
> > + opp-hz = /bits/ 64 <1248000000>;
> > + };
> > + cpr_opp3: opp3 {
> > + opp-level = <3>;
> > + qcom,opp-fuse-level = <3>;
> > + opp-hz = /bits/ 64 <1401600000>;
> > };
> > };
>
> - Do we ever have cases more complex than this for this version of CPR ?
For e.g. CPR on msm8916, we will have 7 different frequencies in the CPU
OPP table, but only 3 OPPs in the CPR OPP table.
Each of the 7 OPPs in the CPU OPP table will have a required-opps that
points to an OPP in the CPR OPP table.
On certain msm8916:s, the speedbin efuse will limit us to only have 6
OPPs in the CPU OPP table, but the required-opps are still the same.
So I would say that it is just slightly more complex..
>
> - What about multiple devices with same CPR table, not big LITTLE
> CPUs, but other devices like two different type of IO devices ? What
> will we do with opp-hz in those cases ?
On all SoCs where there is a CPR for e.g. GPU, there is an additional
CPR hardware block, so then there will also be an additional CPR OPP
table. So I don't think that this will be a problem.
>
> - If there are no such cases, can we live without opp-hz being used
> here and reverse-engineer the highest frequency by looking directly
> at CPUs OPP table ? i.e. by looking at required-opps field.
This was actually my initial thought when talking to you 6+ months ago.
However, the problem was that, from the CPR drivers' perspective, it
only sees the CPR OPP table.
So this is the order things are called,
from qcom-cpufreq-nvmem.c perspective:
1) dev_pm_opp_set_supported_hw()
2) dev_pm_opp_attach_genpd() ->
which results in
int cpr_pd_attach_dev(struct generic_pm_domain *domain,
struct device *dev)
being called.
This callback is inside the CPR driver, and here we have the
CPU's (genpd virtual) struct device, and this is where we would like to
know the opp-hz.
The problem here is that:
[ 3.114979] cpr_pd_attach_dev: dev_pm_opp_get_opp_count for dev: genpd:0:cpu0: -19
[ 3.119610] cpr_pd_attach_dev: dev_pm_opp_get_opp_count for dev: cpu0: 0
[ 3.126489] cpr_pd_attach_dev: dev_pm_opp_get_opp_count for dev: cpr@b018000: 3
While we have the CPR OPP table in the attach callback, we don't
have the CPU OPP table, neither in the CPU struct device or the genpd virtual
struct device.
Since we have called dev_pm_opp_attach_genpd(.., .., &virt_devs) which
attaches an OPP table to the CPU, I would have expected one of them to
be >= 0.
Especially since dev_name(virt_devs[0]) == genpd:0:cpu0
I guess it should still be possible to parse the required-opps manually here,
by iterating the OF nodes, however, we won't be able to use the CPU's struct
opp_table (which is the nice representation of the OF nodes).
Any suggestions?
Kind regards,
Niklas
^ permalink raw reply
* [PATCH 3/3] dt-bindings: iio: imu: st_lsm6dsx: add lsm9ds1 device bindings
From: Martin Kepplinger @ 2019-07-15 13:19 UTC (permalink / raw)
To: lorenzo.bianconi83, jic23, knaack.h, lars, pmeerw
Cc: linux-iio, devicetree, linux-kernel, Martin Kepplinger
In-Reply-To: <20190715131919.31938-1-martin.kepplinger@puri.sm>
Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
---
Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt b/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt
index efec9ece034a..c5ac1730ad22 100644
--- a/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt
+++ b/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt
@@ -11,6 +11,7 @@ Required properties:
"st,asm330lhh"
"st,lsm6dsox"
"st,lsm6dsr"
+ "st,lsm9ds1"
- reg: i2c address of the sensor / spi cs line
Optional properties:
--
2.20.1
^ permalink raw reply related
* [PATCH 2/3] iio: imu: st_lsm6dsx: add support for accel/gyro unit of lsm9sd1
From: Martin Kepplinger @ 2019-07-15 13:19 UTC (permalink / raw)
To: lorenzo.bianconi83, jic23, knaack.h, lars, pmeerw
Cc: linux-iio, devicetree, linux-kernel, Martin Kepplinger
In-Reply-To: <20190715131919.31938-1-martin.kepplinger@puri.sm>
The LSM9DS1's accelerometer / gyroscope unit and it's magnetometer (separately
supported in iio/magnetometer/st_magn*) are located on a separate i2c addresses
on the bus.
For the datasheet, see https://www.st.com/resource/en/datasheet/lsm9ds1.pdf
Treat it just like the LSM6* devices and, despite it's name, hook it up
to the st_lsm6dsx driver, using it's basic functionality.
Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
---
What do you think about an addition like this? How confusing is it to support
an LSM9 module by the lsm6 driver, despite it's name? It requires almost no
code, so why not think about it, right?
Oh, I'm not 100% convinced by my new "if" in probe(), but even that is
not too confusing I guess.
thanks,
martin
p.s.: todos:
* hook up the fifo / buffer / trigger functionality,
* (off-topic a bit) move the (currently strange) gyro-only support
for lsm9ds0 to this driver as well.
drivers/iio/imu/st_lsm6dsx/Kconfig | 3 +-
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h | 4 +
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c | 105 ++++++++++++++++++-
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c | 5 +
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c | 5 +
5 files changed, 117 insertions(+), 5 deletions(-)
diff --git a/drivers/iio/imu/st_lsm6dsx/Kconfig b/drivers/iio/imu/st_lsm6dsx/Kconfig
index 002a423eae52..0b5a568e4c16 100644
--- a/drivers/iio/imu/st_lsm6dsx/Kconfig
+++ b/drivers/iio/imu/st_lsm6dsx/Kconfig
@@ -10,7 +10,8 @@ config IIO_ST_LSM6DSX
help
Say yes here to build support for STMicroelectronics LSM6DSx imu
sensor. Supported devices: lsm6ds3, lsm6ds3h, lsm6dsl, lsm6dsm,
- ism330dlc, lsm6dso, lsm6dsox, asm330lhh, lsm6dsr
+ ism330dlc, lsm6dso, lsm6dsox, asm330lhh, lsm6dsr and the
+ accelerometer/gyroscope of lsm9ds1.
To compile this driver as a module, choose M here: the module
will be called st_lsm6dsx.
diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
index f072ac14f213..8af9641260fa 100644
--- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
+++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
@@ -22,6 +22,7 @@
#define ST_ASM330LHH_DEV_NAME "asm330lhh"
#define ST_LSM6DSOX_DEV_NAME "lsm6dsox"
#define ST_LSM6DSR_DEV_NAME "lsm6dsr"
+#define ST_LSM9DS1_DEV_NAME "lsm9ds1"
enum st_lsm6dsx_hw_id {
ST_LSM6DS3_ID,
@@ -33,6 +34,7 @@ enum st_lsm6dsx_hw_id {
ST_ASM330LHH_ID,
ST_LSM6DSOX_ID,
ST_LSM6DSR_ID,
+ ST_LSM9DS1_ID,
ST_LSM6DSX_MAX_ID,
};
@@ -230,6 +232,8 @@ enum st_lsm6dsx_sensor_id {
ST_LSM6DSX_ID_EXT0,
ST_LSM6DSX_ID_EXT1,
ST_LSM6DSX_ID_EXT2,
+ ST_LSM9DSX_ID_GYRO,
+ ST_LSM9DSX_ID_ACC,
ST_LSM6DSX_ID_MAX,
};
diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
index 7a4fe70a8f20..6acfe63073de 100644
--- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
+++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
@@ -10,6 +10,8 @@
* +-125/+-245/+-500/+-1000/+-2000 dps
* LSM6DSx series has an integrated First-In-First-Out (FIFO) buffer
* allowing dynamic batching of sensor data.
+ * LSM9DSx series is similar but includes an additional magnetometer, handled
+ * by a different driver.
*
* Supported sensors:
* - LSM6DS3:
@@ -30,6 +32,13 @@
* - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000
* - FIFO size: 3KB
*
+ * - LSM9DS1:
+ * - Accelerometer supported ODR [Hz]: 10, 50, 119, 238, 476, 952
+ * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16
+ * - Gyroscope supported ODR [Hz]: 15, 60, 119, 238, 476, 952
+ * - Gyroscope supported full-scale [dps]: +-245/+-500/+-2000
+ * - FIFO size: 32
+ *
* Copyright 2016 STMicroelectronics Inc.
*
* Lorenzo Bianconi <lorenzo.bianconi@st.com>
@@ -64,6 +73,10 @@
#define ST_LSM6DSX_REG_GYRO_OUT_Y_L_ADDR 0x24
#define ST_LSM6DSX_REG_GYRO_OUT_Z_L_ADDR 0x26
+#define ST_LSM9DSX_REG_GYRO_OUT_X_L_ADDR 0x18
+#define ST_LSM9DSX_REG_GYRO_OUT_Y_L_ADDR 0x1a
+#define ST_LSM9DSX_REG_GYRO_OUT_Z_L_ADDR 0x1c
+
static const struct st_lsm6dsx_odr_table_entry st_lsm6dsx_odr_table[] = {
[ST_LSM6DSX_ID_ACC] = {
.reg = {
@@ -88,6 +101,30 @@ static const struct st_lsm6dsx_odr_table_entry st_lsm6dsx_odr_table[] = {
.odr_avl[3] = { 104, 0x04 },
.odr_avl[4] = { 208, 0x05 },
.odr_avl[5] = { 416, 0x06 },
+ },
+ [ST_LSM9DSX_ID_ACC] = {
+ .reg = {
+ .addr = 0x20,
+ .mask = GENMASK(7, 5),
+ },
+ .odr_avl[0] = { 10, 0x01 },
+ .odr_avl[1] = { 50, 0x02 },
+ .odr_avl[2] = { 119, 0x03 },
+ .odr_avl[3] = { 238, 0x04 },
+ .odr_avl[4] = { 476, 0x05 },
+ .odr_avl[5] = { 952, 0x06 },
+ },
+ [ST_LSM9DSX_ID_GYRO] = {
+ .reg = {
+ .addr = 0x10,
+ .mask = GENMASK(7, 5),
+ },
+ .odr_avl[0] = { 15, 0x01 },
+ .odr_avl[1] = { 60, 0x02 },
+ .odr_avl[2] = { 119, 0x03 },
+ .odr_avl[3] = { 238, 0x04 },
+ .odr_avl[4] = { 476, 0x05 },
+ .odr_avl[5] = { 952, 0x06 },
}
};
@@ -111,10 +148,43 @@ static const struct st_lsm6dsx_fs_table_entry st_lsm6dsx_fs_table[] = {
.fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 },
.fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 },
.fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 },
+ },
+ [ST_LSM9DSX_ID_ACC] = {
+ .reg = {
+ .addr = 0x20,
+ .mask = GENMASK(4, 3),
+ },
+ .fs_avl[0] = { 599, 0x0 },
+ .fs_avl[1] = { 1197, 0x2 },
+ .fs_avl[2] = { 2394, 0x3 },
+ .fs_avl[3] = { 4788, 0x1 },
+ },
+ [ST_LSM9DSX_ID_GYRO] = {
+ .reg = {
+ .addr = 0x10,
+ .mask = GENMASK(4, 3),
+ },
+ .fs_avl[0] = { IIO_DEGREE_TO_RAD(245), 0x0 },
+ .fs_avl[1] = { IIO_DEGREE_TO_RAD(500), 0x1 },
+ .fs_avl[2] = { IIO_DEGREE_TO_RAD(0), 0x2 },
+ .fs_avl[3] = { IIO_DEGREE_TO_RAD(2000), 0x3 },
}
};
static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
+ {
+ .wai = 0x68,
+ .reg_int1_addr = 0x0c,
+ .reg_int2_addr = 0x0d,
+ .reg_reset_addr = 0x22,
+ .max_fifo_size = 32,
+ .id = {
+ {
+ .hw_id = ST_LSM9DS1_ID,
+ .name = ST_LSM9DS1_DEV_NAME,
+ },
+ },
+ },
{
.wai = 0x69,
.reg_int1_addr = 0x0d,
@@ -492,6 +562,16 @@ static const struct iio_chan_spec st_lsm6dsx_gyro_channels[] = {
IIO_CHAN_SOFT_TIMESTAMP(3),
};
+static const struct iio_chan_spec st_lsm9dsx_gyro_channels[] = {
+ ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, ST_LSM9DSX_REG_GYRO_OUT_X_L_ADDR,
+ IIO_MOD_X, 0),
+ ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, ST_LSM9DSX_REG_GYRO_OUT_Y_L_ADDR,
+ IIO_MOD_Y, 1),
+ ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, ST_LSM9DSX_REG_GYRO_OUT_Z_L_ADDR,
+ IIO_MOD_Z, 2),
+ IIO_CHAN_SOFT_TIMESTAMP(3),
+};
+
int st_lsm6dsx_set_page(struct st_lsm6dsx_hw *hw, bool enable)
{
const struct st_lsm6dsx_shub_settings *hub_settings;
@@ -1056,6 +1136,7 @@ static struct iio_dev *st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw *hw,
switch (id) {
case ST_LSM6DSX_ID_ACC:
+ case ST_LSM9DSX_ID_ACC:
iio_dev->channels = st_lsm6dsx_acc_channels;
iio_dev->num_channels = ARRAY_SIZE(st_lsm6dsx_acc_channels);
iio_dev->info = &st_lsm6dsx_acc_info;
@@ -1068,6 +1149,14 @@ static struct iio_dev *st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw *hw,
iio_dev->num_channels = ARRAY_SIZE(st_lsm6dsx_gyro_channels);
iio_dev->info = &st_lsm6dsx_gyro_info;
+ scnprintf(sensor->name, sizeof(sensor->name), "%s_gyro",
+ name);
+ break;
+ case ST_LSM9DSX_ID_GYRO:
+ iio_dev->channels = st_lsm9dsx_gyro_channels;
+ iio_dev->num_channels = ARRAY_SIZE(st_lsm9dsx_gyro_channels);
+ iio_dev->info = &st_lsm6dsx_gyro_info;
+
scnprintf(sensor->name, sizeof(sensor->name), "%s_gyro",
name);
break;
@@ -1109,10 +1198,18 @@ int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id,
if (err < 0)
return err;
- for (i = 0; i < ST_LSM6DSX_ID_EXT0; i++) {
- hw->iio_devs[i] = st_lsm6dsx_alloc_iiodev(hw, i, name);
- if (!hw->iio_devs[i])
- return -ENOMEM;
+ if (hw_id == ST_LSM9DS1_ID) {
+ for (i = ST_LSM9DSX_ID_GYRO; i <= ST_LSM9DSX_ID_ACC; i++) {
+ hw->iio_devs[i] = st_lsm6dsx_alloc_iiodev(hw, i, name);
+ if (!hw->iio_devs[i])
+ return -ENOMEM;
+ }
+ } else {
+ for (i = 0; i < ST_LSM6DSX_ID_EXT0; i++) {
+ hw->iio_devs[i] = st_lsm6dsx_alloc_iiodev(hw, i, name);
+ if (!hw->iio_devs[i])
+ return -ENOMEM;
+ }
}
err = st_lsm6dsx_init_device(hw);
diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c
index b3211e0ac07b..a684e7db1299 100644
--- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c
+++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c
@@ -75,6 +75,10 @@ static const struct of_device_id st_lsm6dsx_i2c_of_match[] = {
.compatible = "st,lsm6dsr",
.data = (void *)ST_LSM6DSR_ID,
},
+ {
+ .compatible = "st,lsm9ds1",
+ .data = (void *)ST_LSM9DS1_ID,
+ },
{},
};
MODULE_DEVICE_TABLE(of, st_lsm6dsx_i2c_of_match);
@@ -89,6 +93,7 @@ static const struct i2c_device_id st_lsm6dsx_i2c_id_table[] = {
{ ST_ASM330LHH_DEV_NAME, ST_ASM330LHH_ID },
{ ST_LSM6DSOX_DEV_NAME, ST_LSM6DSOX_ID },
{ ST_LSM6DSR_DEV_NAME, ST_LSM6DSR_ID },
+ { ST_LSM9DS1_DEV_NAME, ST_LSM9DS1_ID },
{},
};
MODULE_DEVICE_TABLE(i2c, st_lsm6dsx_i2c_id_table);
diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c
index c9d3c4711018..709769177e91 100644
--- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c
+++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c
@@ -75,6 +75,10 @@ static const struct of_device_id st_lsm6dsx_spi_of_match[] = {
.compatible = "st,lsm6dsr",
.data = (void *)ST_LSM6DSR_ID,
},
+ {
+ .compatible = "st,lsm9ds1",
+ .data = (void *)ST_LSM9DS1_ID,
+ },
{},
};
MODULE_DEVICE_TABLE(of, st_lsm6dsx_spi_of_match);
@@ -89,6 +93,7 @@ static const struct spi_device_id st_lsm6dsx_spi_id_table[] = {
{ ST_ASM330LHH_DEV_NAME, ST_ASM330LHH_ID },
{ ST_LSM6DSOX_DEV_NAME, ST_LSM6DSOX_ID },
{ ST_LSM6DSR_DEV_NAME, ST_LSM6DSR_ID },
+ { ST_LSM9DS1_DEV_NAME, ST_LSM9DS1_ID },
{},
};
MODULE_DEVICE_TABLE(spi, st_lsm6dsx_spi_id_table);
--
2.20.1
^ permalink raw reply related
* [PATCH 1/3] iio: imu: st_lsm6sdx: move some register definitions to sensor_settings struct
From: Martin Kepplinger @ 2019-07-15 13:19 UTC (permalink / raw)
To: lorenzo.bianconi83, jic23, knaack.h, lars, pmeerw
Cc: linux-iio, devicetree, linux-kernel, Martin Kepplinger
Move some register definitions to the per-device array of struct
st_lsm6dsx_sensor_settings in order to simplify adding new sensor
devices to the driver.
Also, remove completely unused register definitions.
Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
---
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h | 6 ++++
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c | 31 ++++++++++++++------
2 files changed, 28 insertions(+), 9 deletions(-)
diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
index c14bf533b66b..f072ac14f213 100644
--- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
+++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
@@ -196,6 +196,9 @@ struct st_lsm6dsx_ext_dev_settings {
/**
* struct st_lsm6dsx_settings - ST IMU sensor settings
* @wai: Sensor WhoAmI default value.
+ * @reg_int1_addr: Control Register address for INT1
+ * @reg_int2_addr: Control Register address for INT2
+ * @reg_reset_addr: register address for reset/reboot
* @max_fifo_size: Sensor max fifo length in FIFO words.
* @id: List of hw id/device name supported by the driver configuration.
* @decimator: List of decimator register info (addr + mask).
@@ -206,6 +209,9 @@ struct st_lsm6dsx_ext_dev_settings {
*/
struct st_lsm6dsx_settings {
u8 wai;
+ u8 reg_int1_addr;
+ u8 reg_int2_addr;
+ u8 reg_reset_addr;
u16 max_fifo_size;
struct {
enum st_lsm6dsx_hw_id hw_id;
diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
index a6702a74570e..7a4fe70a8f20 100644
--- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
+++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
@@ -49,17 +49,12 @@
#include "st_lsm6dsx.h"
-#define ST_LSM6DSX_REG_INT1_ADDR 0x0d
-#define ST_LSM6DSX_REG_INT2_ADDR 0x0e
#define ST_LSM6DSX_REG_FIFO_FTH_IRQ_MASK BIT(3)
#define ST_LSM6DSX_REG_WHOAMI_ADDR 0x0f
-#define ST_LSM6DSX_REG_RESET_ADDR 0x12
#define ST_LSM6DSX_REG_RESET_MASK BIT(0)
#define ST_LSM6DSX_REG_BOOT_MASK BIT(7)
#define ST_LSM6DSX_REG_BDU_ADDR 0x12
#define ST_LSM6DSX_REG_BDU_MASK BIT(6)
-#define ST_LSM6DSX_REG_INT2_ON_INT1_ADDR 0x13
-#define ST_LSM6DSX_REG_INT2_ON_INT1_MASK BIT(5)
#define ST_LSM6DSX_REG_ACC_OUT_X_L_ADDR 0x28
#define ST_LSM6DSX_REG_ACC_OUT_Y_L_ADDR 0x2a
@@ -122,6 +117,9 @@ static const struct st_lsm6dsx_fs_table_entry st_lsm6dsx_fs_table[] = {
static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
{
.wai = 0x69,
+ .reg_int1_addr = 0x0d,
+ .reg_int2_addr = 0x0e,
+ .reg_reset_addr = 0x12,
.max_fifo_size = 1365,
.id = {
{
@@ -172,6 +170,9 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
},
{
.wai = 0x69,
+ .reg_int1_addr = 0x0d,
+ .reg_int2_addr = 0x0e,
+ .reg_reset_addr = 0x12,
.max_fifo_size = 682,
.id = {
{
@@ -222,6 +223,9 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
},
{
.wai = 0x6a,
+ .reg_int1_addr = 0x0d,
+ .reg_int2_addr = 0x0e,
+ .reg_reset_addr = 0x12,
.max_fifo_size = 682,
.id = {
{
@@ -278,6 +282,9 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
},
{
.wai = 0x6c,
+ .reg_int1_addr = 0x0d,
+ .reg_int2_addr = 0x0e,
+ .reg_reset_addr = 0x12,
.max_fifo_size = 512,
.id = {
{
@@ -349,6 +356,9 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
},
{
.wai = 0x6b,
+ .reg_int1_addr = 0x0d,
+ .reg_int2_addr = 0x0e,
+ .reg_reset_addr = 0x12,
.max_fifo_size = 512,
.id = {
{
@@ -391,6 +401,9 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
},
{
.wai = 0x6b,
+ .reg_int1_addr = 0x0d,
+ .reg_int2_addr = 0x0e,
+ .reg_reset_addr = 0x12,
.max_fifo_size = 512,
.id = {
{
@@ -873,10 +886,10 @@ static int st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw, u8 *drdy_reg)
switch (drdy_pin) {
case 1:
- *drdy_reg = ST_LSM6DSX_REG_INT1_ADDR;
+ *drdy_reg = hw->settings->reg_int1_addr;
break;
case 2:
- *drdy_reg = ST_LSM6DSX_REG_INT2_ADDR;
+ *drdy_reg = hw->settings->reg_int2_addr;
break;
default:
dev_err(hw->dev, "unsupported data ready pin\n");
@@ -976,7 +989,7 @@ static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw)
int err;
/* device sw reset */
- err = regmap_update_bits(hw->regmap, ST_LSM6DSX_REG_RESET_ADDR,
+ err = regmap_update_bits(hw->regmap, hw->settings->reg_reset_addr,
ST_LSM6DSX_REG_RESET_MASK,
FIELD_PREP(ST_LSM6DSX_REG_RESET_MASK, 1));
if (err < 0)
@@ -985,7 +998,7 @@ static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw)
msleep(50);
/* reload trimming parameter */
- err = regmap_update_bits(hw->regmap, ST_LSM6DSX_REG_RESET_ADDR,
+ err = regmap_update_bits(hw->regmap, hw->settings->reg_reset_addr,
ST_LSM6DSX_REG_BOOT_MASK,
FIELD_PREP(ST_LSM6DSX_REG_BOOT_MASK, 1));
if (err < 0)
--
2.20.1
^ permalink raw reply related
* [PATCH v1 50/50] ARM: dts: exynos: change MMC0 clock parent in Exynos5800 Peach Pi
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Change MMC0 clock settings and set parent to MOUT_SPLL with proper rate.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5800-peach-pi.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 38edb00c7f1b..c8e02ecc6627 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -891,6 +891,9 @@
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
+ assigned-clocks = <&clock CLK_MOUT_MMC0>, <&clock CLK_FOUT_SPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_SPLL>;
+ assigned-clock-rates = <0>, <800000000>;
};
&nocp_mem0_0 {
--
2.17.1
^ permalink raw reply related
* [PATCH v1 49/50] ARM: dts: exynos: add buses support for Exynos5800 Peach Pi
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The patch adds SoC buses support. It also changes connections of the clocks
pinning to the rigth parent. There is also frequency set of the needed
clock to make it working at the right rate.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5800-peach-pi.dts | 172 ++++++++++++++++++++++
1 file changed, 172 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index e0f470fe54c8..38edb00c7f1b 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -151,6 +151,163 @@
vdd-supply = <&ldo9_reg>;
};
+&bus_wcore {
+ devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
+ <&nocp_mem1_0>, <&nocp_mem1_1>;
+ vdd-supply = <&buck3_reg>;
+ exynos,saturation-ratio = <100>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK400_WCORE>,
+ <&clock CLK_MOUT_SW_ACLK400_WCORE>,
+ <&clock CLK_DOUT_ACLK400_WCORE>,
+ <&clock CLK_FOUT_DPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>,
+ <&clock CLK_DOUT_ACLK400_WCORE>;
+ assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>;
+ status = "okay";
+};
+
+&bus_noc {
+ devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK100_NOC>,
+ <&clock CLK_DOUT_ACLK100_NOC>;
+ assigned-clock-parents = <&clock CLK_FF_DOUT_SPLL2>;
+ assigned-clock-rates = <0>, <100000000>;
+ status = "okay";
+};
+
+&bus_fsys_apb {
+ devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_PCLK200_FSYS>,
+ <&clock CLK_DOUT_PCLK200_FSYS>,
+ <&clock CLK_FOUT_MPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <200000000>,<600000000>;
+ status = "okay";
+};
+
+&bus_fsys {
+ devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS>,
+ <&clock CLK_DOUT_ACLK200_FSYS>,
+ <&clock CLK_FOUT_DPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
+ assigned-clock-rates = <0>, <240000000>,<1200000000>;
+ status = "okay";
+};
+
+&bus_fsys2 {
+ devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS2>,
+ <&clock CLK_DOUT_ACLK200_FSYS2>,
+ <&clock CLK_FOUT_DPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
+ assigned-clock-rates = <0>, <240000000>,<1200000000>;
+ status = "okay";
+};
+
+&bus_mfc {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_gen {
+ devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK266>,
+ <&clock CLK_DOUT_ACLK266>, <&clock CLK_FOUT_MPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <300000000>,<600000000>;
+ status = "okay";
+};
+
+&bus_peri {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_g2d {
+ devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK266_G2D>,
+ <&clock CLK_DOUT_ACLK266_G2D>,
+ <&clock CLK_FOUT_MPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <300000000>,<600000000>;
+ status = "okay";
+};
+
+&bus_g2d_acp {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_jpeg {
+ devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
+ assigned-clock-rates = <300000000>;
+ status = "okay";
+};
+
+&bus_jpeg_apb {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_disp1_fimd {
+ devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
+ assigned-clock-rates = <300000000>;
+ status = "okay";
+};
+
+&bus_disp1 {
+ devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_DOUT_ACLK200>,
+ <&clock CLK_DOUT_ACLK400_DISP1>;
+ assigned-clock-rates = <200000000>, <400000000>;
+ status = "okay";
+};
+
+&bus_gscl_scaler {
+ devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
+ assigned-clock-rates = <300000000>;
+ status = "okay";
+};
+
+&bus_mscl {
+ devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK400_MSCL>,
+ <&clock CLK_MOUT_SW_ACLK400_MSCL>,
+ <&clock CLK_DOUT_ACLK400_MSCL>,
+ <&clock CLK_FOUT_DPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>,
+ <&clock CLK_DOUT_ACLK400_MSCL>;
+ assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>;
+ status = "okay";
+};
+
+&bus_isp {
+ devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK400_ISP>,
+ <&clock CLK_MOUT_SW_ACLK400_ISP>,
+ <&clock CLK_DOUT_ACLK400_ISP>,
+ <&clock CLK_FOUT_DPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>,
+ <&clock CLK_DOUT_ACLK400_ISP>;
+ assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>;
+ status = "okay";
+};
+
+&bus_isp266 {
+ devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK266_ISP>,
+ <&clock CLK_MOUT_USER_ACLK266_ISP>,
+ <&clock CLK_DOUT_ACLK266_ISP>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>,
+ <&clock CLK_MOUT_SW_ACLK266_ISP>;
+ assigned-clock-rates = <0>, <0>,<300000000>;
+ status = "okay";
+};
+
&clock_audss {
assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>;
assigned-clock-parents = <&clock CLK_MAU_EPLL>;
@@ -736,6 +893,21 @@
bus-width = <4>;
};
+&nocp_mem0_0 {
+ status = "okay";
+};
+
+&nocp_mem0_1 {
+ status = "okay";
+};
+
+&nocp_mem1_0 {
+ status = "okay";
+};
+
+&nocp_mem1_1 {
+ status = "okay";
+};
&pinctrl_0 {
pinctrl-names = "default";
--
2.17.1
^ permalink raw reply related
* [PATCH v1 48/50] ARM: dts: exynos: set proper parents to bus_isp266 Exynos5422
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
On Exynos5422 there is a dedicated clock hierarchy for ACLK_266_ISP which
should be set to proper values to fully use the HW performance.
The old settings left after boot set minimal values to this bus.
In the Exynos5420 the bus is connected to ACLK_266 so there is no need for
aligning the values. In the Exynos5422 the proper hierarchy of these
clocks should be model in the software to use the full HW feature set.
The patch sets proper parent (MPLL) and initial frequency to the bus also
enabling it.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index d278339f259c..c770d17141e8 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -187,6 +187,17 @@
status = "okay";
};
+&bus_isp266 {
+ devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK266_ISP>,
+ <&clock CLK_MOUT_USER_ACLK266_ISP>,
+ <&clock CLK_DOUT_ACLK266_ISP>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>,
+ <&clock CLK_MOUT_SW_ACLK266_ISP>;
+ assigned-clock-rates = <0>, <0>,<300000000>;
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <&buck6_reg>;
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 47/50] ARM: dts: exynos: change rate of bus_gscl_scaler in Exynos5422
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The bus_gscl_scaler OPP table has been aligned to the new parent rate. This
patch sets the proper frequency before the devfreq governor starts working.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index fac5659516ad..d278339f259c 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -158,6 +158,8 @@
&bus_gscl_scaler {
devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
+ assigned-clock-rates = <300000000>;
status = "okay";
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 46/50] ARM: dts: exynos: change rates of bus_disp1 in Exynos5422
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The bus_disp1 OPP table has been aligned to the new parent rate. This patch
sets the proper frequencies before the devfreq governor starts working. It
sets 200MHz to bus ACLK_200_DISP1 which is controlled via CLK_DOUT_ACLK200
and 400MHz to ACLK400_DISP1 which is controlled via CLK_DOUT_ACLK400_DISP1.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 2cfe1effe290..fac5659516ad 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -150,6 +150,9 @@
&bus_disp1 {
devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_DOUT_ACLK200>,
+ <&clock CLK_DOUT_ACLK400_DISP1>;
+ assigned-clock-rates = <200000000>, <400000000>;
status = "okay";
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 45/50] ARM: dts: exynos: change rate of bus_disp1_fimd in Exynos5422
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The bus_disp1_fimd OPP table has been aligned to the new parent rate. This
patch sets the proper frequency before the devfreq governor starts working.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 27f6ed323ba1..2cfe1effe290 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -143,6 +143,8 @@
&bus_disp1_fimd {
devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
+ assigned-clock-rates = <300000000>;
status = "okay";
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 44/50] ARM: dts: exynos: change rate of bus_jpeg in Exynos5422
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The bus_gen OPP table has been aligned to the parent rate. This patch sets
the proper initial frequency before the devfreq governor starts working.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 852cb3dd495d..27f6ed323ba1 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -131,6 +131,8 @@
&bus_jpeg {
devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
+ assigned-clock-rates = <300000000>;
status = "okay";
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 43/50] ARM: dts: exynos: add bus_isp in Exynos5422
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Add bus_isp which changes ACLK400_ISP clock speed according to the bus
documentation in the documentation. The bus_isp OPP table has been
aligned to the new parent rate. This patch sets the proper parent and
picks the init frequency before the devfreq governor starts working.
It sets also parent rate (DPLL to 1200MHz).
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 990fe03fce75..852cb3dd495d 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -166,6 +166,18 @@
status = "okay";
};
+&bus_isp {
+ devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK400_ISP>,
+ <&clock CLK_MOUT_SW_ACLK400_ISP>,
+ <&clock CLK_DOUT_ACLK400_ISP>,
+ <&clock CLK_FOUT_DPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>,
+ <&clock CLK_DOUT_ACLK400_ISP>;
+ assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>;
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <&buck6_reg>;
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 42/50] ARM: dts: exynos: change parent and rate of bus_mscl in Exynos5422
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The bus_mscl OPP table has been aligned to the new parent rate. This patch
sets the proper parents in the clock tree and picks the init frequency
before the devfreq governor starts working. It sets also parent rate (MPLL
to 600MHz).
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 198e33cf115f..990fe03fce75 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -103,7 +103,8 @@
&bus_gen {
devfreq = <&bus_wcore>;
assigned-clocks = <&clock CLK_MOUT_ACLK266>,
- <&clock CLK_DOUT_ACLK266>, <&clock CLK_FOUT_MPLL>;
+ <&clock CLK_DOUT_ACLK266>,
+ <&clock CLK_FOUT_MPLL>;
assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>;
assigned-clock-rates = <0>, <300000000>,<600000000>;
status = "okay";
@@ -155,6 +156,13 @@
&bus_mscl {
devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK400_MSCL>,
+ <&clock CLK_MOUT_SW_ACLK400_MSCL>,
+ <&clock CLK_DOUT_ACLK400_MSCL>,
+ <&clock CLK_FOUT_DPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>,
+ <&clock CLK_DOUT_ACLK400_MSCL>;
+ assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>;
status = "okay";
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 41/50] ARM: dts: exynos: change parent and rate of bus_g2d in Exynos5422
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The bus_g2d OPP table has been aligned to the new parent rate. This patch
sets the proper parent and picks the init frequency before the devfreq
governor starts working. It sets also parent rate (MPLL to 600MHz).
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 75664ff6d966..198e33cf115f 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -116,6 +116,10 @@
&bus_g2d {
devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK266_G2D>,
+ <&clock CLK_DOUT_ACLK266_G2D>, <&clock CLK_FOUT_MPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <300000000>,<600000000>;
status = "okay";
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 40/50] ARM: dts: exynos: change parent and rate of bus_gen in Exynos5422
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The bus_gen OPP table has been aligned to the new parent rate. This patch
sets the proper parent and picks the init frequency before the devfreq
governor starts working. It sets also parent rate (MPLL to 600MHz).
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 6225d044d01c..75664ff6d966 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -102,6 +102,10 @@
&bus_gen {
devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK266>,
+ <&clock CLK_DOUT_ACLK266>, <&clock CLK_FOUT_MPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <300000000>,<600000000>;
status = "okay";
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 39/50] ARM: dts: exynos: change parent and rate of bus_fsys_acp in Exynos5422
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The FSYS APB bus OPP table has been aligned to the new parent rate. This
patch sets the proper parent and picks the init frequency before the
devfreq governor starts working. It sets also parent rate (MPLL to
600MHz).
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 0e71ba64a4fe..6225d044d01c 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -67,6 +67,11 @@
&bus_fsys_apb {
devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_PCLK200_FSYS>,
+ <&clock CLK_DOUT_PCLK200_FSYS>,
+ <&clock CLK_FOUT_MPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <200000000>,<600000000>;
status = "okay";
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 38/50] ARM: dts: exynos: change parent and rate of bus_fsys2 in Exynos5422
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The FSYS2 bus OPP table has been aligned to the new parent rate. The OPP
table is also shared with bus_fsys. This patch sets the proper parent and
picks the init frequency before the devfreq governor starts working. It
sets also parent rate (DPLL to 1200MHz).
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 6a82dd175b8a..0e71ba64a4fe 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -82,6 +82,11 @@
&bus_fsys2 {
devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS2>,
+ <&clock CLK_DOUT_ACLK200_FSYS2>,
+ <&clock CLK_FOUT_DPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
+ assigned-clock-rates = <0>, <240000000>,<1200000000>;
status = "okay";
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 37/50] ARM: dts: exynos: change parent and rate of bus_fsys in Exynos5422
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The FSYS bus OPP table has been aligned to the new parent rate. This patch
sets the proper parent and picks the init frequency before the devfreq
governor starts working. It sets also parent rate (DPLL to 1200MHz).
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index d460041f716c..6a82dd175b8a 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -72,6 +72,11 @@
&bus_fsys {
devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS>,
+ <&clock CLK_DOUT_ACLK200_FSYS>,
+ <&clock CLK_FOUT_DPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
+ assigned-clock-rates = <0>, <240000000>,<1200000000>;
status = "okay";
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 36/50] ARM: dts: exynos: change ACLK100_NOC config in Exynos5422
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
This patch changes NOC100 bus to proper parent and proper rate. The OPPs
have been align to reflect this parent and its clock rate.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index aaf18653d8ac..d460041f716c 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -58,6 +58,10 @@
&bus_noc {
devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK100_NOC>,
+ <&clock CLK_DOUT_ACLK100_NOC>;
+ assigned-clock-parents = <&clock CLK_FF_DOUT_SPLL2>;
+ assigned-clock-rates = <0>, <100000000>;
status = "okay";
};
--
2.17.1
^ permalink raw reply related
* [PATCH v1 35/50] ARM: dts: exynos: change speed and parent of NoC clock in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
This patch changes speed and parent of NoC WCORE bus to 400MHz. The clock
is now attached to a branch were the root is the DPLL which speed is set to
1200MHz. The OPPs are aligned to this rate accordingly.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 25d95de15c9b..aaf18653d8ac 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -46,6 +46,13 @@
<&nocp_mem1_0>, <&nocp_mem1_1>;
vdd-supply = <&buck3_reg>;
exynos,saturation-ratio = <100>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK400_WCORE>,
+ <&clock CLK_MOUT_SW_ACLK400_WCORE>,
+ <&clock CLK_DOUT_ACLK400_WCORE>,
+ <&clock CLK_FOUT_DPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>,
+ <&clock CLK_DOUT_ACLK400_WCORE>;
+ assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>;
status = "okay";
};
--
2.17.1
^ permalink raw reply related
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