* [PATCH v2 7/8] PCI: dw: Add validation that PCIe core is set to correct mode
From: Jonathan Chocron @ 2019-07-18 9:47 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas, jingoohan1, gustavo.pimentel,
robh+dt, mark.rutland
Cc: dwmw, benh, alisaidi, ronenk, barakw, talel, hanochu, hhhawa,
linux-pci, linux-kernel, devicetree, jonnyc
In-Reply-To: <20190718094531.21423-1-jonnyc@amazon.com>
Some PCIe controllers can be set to either Host or EP according to some
early boot FW. To make sure there is no discrepancy (e.g. FW configured
the port to EP mode while the DT specifies it as a host bridge or vice
versa), a check has been added for each mode.
Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 8 ++++++++
drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++
2 files changed, 16 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 2bf5a35c0570..00e59a134b93 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -531,6 +531,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
int ret;
u32 reg;
void *addr;
+ u8 hdr_type;
unsigned int nbars;
unsigned int offset;
struct pci_epc *epc;
@@ -543,6 +544,13 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
return -EINVAL;
}
+ hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
+ if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
+ dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
+ hdr_type);
+ return -EIO;
+ }
+
ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
if (ret < 0) {
dev_err(dev, "Unable to read *num-ib-windows* property\n");
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index f93252d0da5b..d2ca748e4c85 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -323,6 +323,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
struct pci_bus *child;
struct pci_host_bridge *bridge;
struct resource *cfg_res;
+ u8 hdr_type;
int ret;
raw_spin_lock_init(&pci->pp.lock);
@@ -396,6 +397,13 @@ int dw_pcie_host_init(struct pcie_port *pp)
}
}
+ hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
+ if (hdr_type != PCI_HEADER_TYPE_BRIDGE) {
+ dev_err(pci->dev, "PCIe controller is not set to bridge type (hdr_type: 0x%x)!\n",
+ hdr_type);
+ return -EIO;
+ }
+
pp->mem_base = pp->mem->start;
if (!pp->va_cfg0_base) {
--
2.17.1
^ permalink raw reply related
* [PATCH v2 6/8] PCI: al: Add support for DW based driver type
From: Jonathan Chocron @ 2019-07-18 9:47 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas, jingoohan1, gustavo.pimentel,
robh+dt, mark.rutland
Cc: dwmw, benh, alisaidi, ronenk, barakw, talel, hanochu, hhhawa,
linux-pci, linux-kernel, devicetree, jonnyc
In-Reply-To: <20190718094531.21423-1-jonnyc@amazon.com>
This driver is DT based and utilizes the DesignWare APIs.
It allows using a smaller ECAM range for a larger bus range -
usually an entire bus uses 1MB of address space, but the driver
can use it for a larger number of buses.
All link initializations are handled by the boot FW.
Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
---
drivers/pci/controller/dwc/Kconfig | 12 +
drivers/pci/controller/dwc/pcie-al.c | 373 +++++++++++++++++++++++++++
2 files changed, 385 insertions(+)
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index 6ea778ae4877..3c6094cbcc3b 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -230,4 +230,16 @@ config PCIE_UNIPHIER
Say Y here if you want PCIe controller support on UniPhier SoCs.
This driver supports LD20 and PXs3 SoCs.
+config PCIE_AL
+ bool "Amazon Annapurna Labs PCIe controller"
+ depends on OF && (ARM64 || COMPILE_TEST)
+ depends on PCI_MSI_IRQ_DOMAIN
+ select PCIE_DW_HOST
+ help
+ Say Y here to enable support of the Amazon's Annapurna Labs PCIe
+ controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
+ core plus Annapurna Labs proprietary hardware wrappers. This is
+ required only for DT-based platforms. ACPI platforms with the
+ Annapurna Labs PCIe controller don't need to enable this.
+
endmenu
diff --git a/drivers/pci/controller/dwc/pcie-al.c b/drivers/pci/controller/dwc/pcie-al.c
index 3ab58f0584a8..40555532fb9a 100644
--- a/drivers/pci/controller/dwc/pcie-al.c
+++ b/drivers/pci/controller/dwc/pcie-al.c
@@ -91,3 +91,376 @@ struct pci_ecam_ops al_pcie_ops = {
};
#endif /* defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) */
+
+#ifdef CONFIG_PCIE_AL
+
+#include <linux/of_pci.h>
+#include "pcie-designware.h"
+
+#define AL_PCIE_REV_ID_2 2
+#define AL_PCIE_REV_ID_3 3
+#define AL_PCIE_REV_ID_4 4
+
+#define AXI_BASE_OFFSET 0x0
+
+#define DEVICE_ID_OFFSET 0x16c
+
+#define DEVICE_REV_ID 0x0
+#define DEVICE_REV_ID_DEV_ID_MASK GENMASK(31, 16)
+
+#define DEVICE_REV_ID_DEV_ID_X4 0
+#define DEVICE_REV_ID_DEV_ID_X8 2
+#define DEVICE_REV_ID_DEV_ID_X16 4
+
+#define OB_CTRL_REV1_2_OFFSET 0x0040
+#define OB_CTRL_REV3_5_OFFSET 0x0030
+
+#define CFG_TARGET_BUS 0x0
+#define CFG_TARGET_BUS_MASK_MASK GENMASK(7, 0)
+#define CFG_TARGET_BUS_BUSNUM_MASK GENMASK(15, 8)
+
+#define CFG_CONTROL 0x4
+#define CFG_CONTROL_SUBBUS_MASK GENMASK(15, 8)
+#define CFG_CONTROL_SEC_BUS_MASK GENMASK(23, 16)
+
+struct al_pcie_reg_offsets {
+ unsigned int ob_ctrl;
+};
+
+struct al_pcie_target_bus_cfg {
+ u8 reg_val;
+ u8 reg_mask;
+ u8 ecam_mask;
+};
+
+struct al_pcie {
+ struct dw_pcie *pci;
+ void __iomem *controller_base; /* base of PCIe unit (not DW core) */
+ struct device *dev;
+ resource_size_t ecam_size;
+ unsigned int controller_rev_id;
+ struct al_pcie_reg_offsets reg_offsets;
+ struct al_pcie_target_bus_cfg target_bus_cfg;
+};
+
+#define PCIE_ECAM_DEVFN(x) (((x) & 0xff) << 12)
+
+#define to_al_pcie(x) dev_get_drvdata((x)->dev)
+
+static int al_pcie_rev_id_get(struct al_pcie *pcie, unsigned int *rev_id)
+{
+ void __iomem *dev_rev_id_addr;
+ u32 dev_rev_id;
+
+ dev_rev_id_addr = (void __iomem *)((uintptr_t)pcie->controller_base +
+ AXI_BASE_OFFSET + DEVICE_ID_OFFSET + DEVICE_REV_ID);
+
+ dev_rev_id = FIELD_GET(DEVICE_REV_ID_DEV_ID_MASK,
+ readl(dev_rev_id_addr));
+ switch (dev_rev_id) {
+ case DEVICE_REV_ID_DEV_ID_X4:
+ *rev_id = AL_PCIE_REV_ID_2;
+ break;
+ case DEVICE_REV_ID_DEV_ID_X8:
+ *rev_id = AL_PCIE_REV_ID_3;
+ break;
+ case DEVICE_REV_ID_DEV_ID_X16:
+ *rev_id = AL_PCIE_REV_ID_4;
+ break;
+ default:
+ dev_err(pcie->dev, "Unsupported dev_rev_id (0x%x)\n",
+ dev_rev_id);
+ return -EINVAL;
+ }
+
+ dev_dbg(pcie->dev, "dev_rev_id: 0x%x\n", dev_rev_id);
+
+ return 0;
+}
+
+static int al_pcie_reg_offsets_set(struct al_pcie *pcie)
+{
+ switch (pcie->controller_rev_id) {
+ case AL_PCIE_REV_ID_2:
+ pcie->reg_offsets.ob_ctrl = OB_CTRL_REV1_2_OFFSET;
+ break;
+ case AL_PCIE_REV_ID_3:
+ case AL_PCIE_REV_ID_4:
+ pcie->reg_offsets.ob_ctrl = OB_CTRL_REV3_5_OFFSET;
+ break;
+ default:
+ dev_err(pcie->dev, "Unsupported controller rev_id: 0x%x\n",
+ pcie->controller_rev_id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static inline void al_pcie_target_bus_set(struct al_pcie *pcie,
+ u8 target_bus,
+ u8 mask_target_bus)
+{
+ void __iomem *cfg_control_addr;
+ u32 reg;
+
+ reg = FIELD_PREP(CFG_TARGET_BUS_MASK_MASK, mask_target_bus) |
+ FIELD_PREP(CFG_TARGET_BUS_BUSNUM_MASK, target_bus);
+
+ cfg_control_addr = (void __iomem *)((uintptr_t)pcie->controller_base +
+ AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl +
+ CFG_TARGET_BUS);
+
+ writel(reg, cfg_control_addr);
+}
+
+static void __iomem *al_pcie_conf_addr_map(struct al_pcie *pcie,
+ unsigned int busnr,
+ unsigned int devfn)
+{
+ void __iomem *pci_base_addr;
+ struct pcie_port *pp = &pcie->pci->pp;
+ struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg;
+ unsigned int busnr_ecam = busnr & target_bus_cfg->ecam_mask;
+ unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask;
+
+ pci_base_addr = (void __iomem *)((uintptr_t)pp->va_cfg0_base +
+ (busnr_ecam << 20) +
+ PCIE_ECAM_DEVFN(devfn));
+
+ if (busnr_reg != target_bus_cfg->reg_val) {
+ dev_dbg(pcie->pci->dev, "Changing target bus busnum val from 0x%x to 0x%x\n",
+ target_bus_cfg->reg_val, busnr_reg);
+ target_bus_cfg->reg_val = busnr_reg;
+ al_pcie_target_bus_set(pcie,
+ target_bus_cfg->reg_val,
+ target_bus_cfg->reg_mask);
+ }
+
+ return pci_base_addr;
+}
+
+static int al_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
+ unsigned int devfn, int where, int size,
+ u32 *val)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct al_pcie *pcie = to_al_pcie(pci);
+ unsigned int busnr = bus->number;
+ void __iomem *pci_addr;
+ int rc;
+
+ pci_addr = al_pcie_conf_addr_map(pcie, busnr, devfn);
+
+ rc = dw_pcie_read(pci_addr + where, size, val);
+
+ dev_dbg(pci->dev, "%d-byte config read from %04x:%02x:%02x.%d offset 0x%x (pci_addr: 0x%px) - val:0x%x\n",
+ size, pci_domain_nr(bus), bus->number,
+ PCI_SLOT(devfn), PCI_FUNC(devfn), where,
+ (pci_addr + where), *val);
+
+ return rc;
+}
+
+static int al_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
+ unsigned int devfn, int where, int size,
+ u32 val)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct al_pcie *pcie = to_al_pcie(pci);
+ unsigned int busnr = bus->number;
+ void __iomem *pci_addr;
+ int rc;
+
+ pci_addr = al_pcie_conf_addr_map(pcie, busnr, devfn);
+
+ rc = dw_pcie_write(pci_addr + where, size, val);
+
+ dev_err(pci->dev, "%d-byte config write to %04x:%02x:%02x.%d offset 0x%x (pci_addr: 0x%px) - val:0x%x\n",
+ size, pci_domain_nr(bus), bus->number,
+ PCI_SLOT(devfn), PCI_FUNC(devfn), where,
+ (pci_addr + where), val);
+
+ return rc;
+}
+
+static int al_pcie_config_prepare(struct al_pcie *pcie)
+{
+ struct al_pcie_target_bus_cfg *target_bus_cfg;
+ struct pcie_port *pp = &pcie->pci->pp;
+ unsigned int ecam_bus_mask;
+ u8 secondary_bus;
+ u8 subordinate_bus;
+ void __iomem *cfg_control_addr;
+ u32 cfg_control;
+ u32 reg;
+
+ target_bus_cfg = &pcie->target_bus_cfg;
+
+ ecam_bus_mask = (pcie->ecam_size >> 20) - 1;
+ if (ecam_bus_mask > 255) {
+ dev_warn(pcie->dev, "ECAM window size is larger than 256MB. Cutting off at 256\n");
+ ecam_bus_mask = 255;
+ }
+
+ /* This portion is taken from the transaction address */
+ target_bus_cfg->ecam_mask = ecam_bus_mask;
+ /* This portion is taken from the cfg_target_bus reg */
+ target_bus_cfg->reg_mask = ~target_bus_cfg->ecam_mask;
+ target_bus_cfg->reg_val = pp->busn->start & target_bus_cfg->reg_mask;
+
+ al_pcie_target_bus_set(pcie, target_bus_cfg->reg_val,
+ target_bus_cfg->reg_mask);
+
+ secondary_bus = pp->busn->start + 1;
+ subordinate_bus = pp->busn->end;
+
+ /* Set the valid values of secondary and subordinate buses */
+ cfg_control_addr = pcie->controller_base + AXI_BASE_OFFSET +
+ pcie->reg_offsets.ob_ctrl + CFG_CONTROL;
+
+ cfg_control = readl(cfg_control_addr);
+
+ reg = cfg_control &
+ ~(CFG_CONTROL_SEC_BUS_MASK | CFG_CONTROL_SUBBUS_MASK);
+
+ reg |= FIELD_PREP(CFG_CONTROL_SUBBUS_MASK, subordinate_bus) |
+ FIELD_PREP(CFG_CONTROL_SEC_BUS_MASK, secondary_bus);
+
+ writel(reg, cfg_control_addr);
+
+ return 0;
+}
+
+static int al_pcie_host_init(struct pcie_port *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct al_pcie *pcie = to_al_pcie(pci);
+ int link_up;
+ int rc;
+
+ link_up = dw_pcie_link_up(pci);
+ if (!link_up) {
+ dev_err(pci->dev, "link is not up!\n");
+ return -ENOLINK;
+ }
+
+ dev_info(pci->dev, "link is up\n");
+
+ rc = al_pcie_rev_id_get(pcie, &pcie->controller_rev_id);
+ if (rc)
+ return rc;
+
+ rc = al_pcie_reg_offsets_set(pcie);
+ if (rc)
+ return rc;
+
+ rc = al_pcie_config_prepare(pcie);
+ if (rc)
+ return rc;
+
+ return 0;
+}
+
+static const struct dw_pcie_host_ops al_pcie_host_ops = {
+ .rd_other_conf = al_pcie_rd_other_conf,
+ .wr_other_conf = al_pcie_wr_other_conf,
+ .host_init = al_pcie_host_init,
+};
+
+static int al_add_pcie_port(struct pcie_port *pp,
+ struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ pp->ops = &al_pcie_host_ops;
+
+ ret = dw_pcie_host_init(pp);
+ if (ret) {
+ dev_err(dev, "failed to initialize host\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct dw_pcie_ops dw_pcie_ops = {
+};
+
+static int al_pcie_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct al_pcie *al_pcie;
+ struct dw_pcie *pci;
+ struct resource *dbi_res;
+ struct resource *controller_res;
+ struct resource *ecam_res;
+ int ret;
+
+ al_pcie = devm_kzalloc(dev, sizeof(*al_pcie), GFP_KERNEL);
+ if (!al_pcie)
+ return -ENOMEM;
+
+ pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+ if (!pci)
+ return -ENOMEM;
+
+ pci->dev = dev;
+ pci->ops = &dw_pcie_ops;
+
+ al_pcie->pci = pci;
+ al_pcie->dev = dev;
+
+ dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
+ pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res);
+ if (IS_ERR(pci->dbi_base)) {
+ dev_err(dev, "couldn't remap dbi base %pR\n", dbi_res);
+ return PTR_ERR(pci->dbi_base);
+ }
+
+ ecam_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
+ if (!ecam_res) {
+ dev_err(dev, "couldn't find 'config' reg in DT\n");
+ return -ENOENT;
+ }
+ al_pcie->ecam_size = resource_size(ecam_res);
+
+ controller_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "controller");
+ al_pcie->controller_base = devm_ioremap_resource(dev, controller_res);
+ if (IS_ERR(al_pcie->controller_base)) {
+ dev_err(dev, "couldn't remap controller base %pR\n",
+ controller_res);
+ return PTR_ERR(al_pcie->controller_base);
+ }
+
+ dev_dbg(dev, "From DT: dbi_base: %pR, controller_base: %pR\n",
+ dbi_res, controller_res);
+
+ platform_set_drvdata(pdev, al_pcie);
+
+ ret = al_add_pcie_port(&pci->pp, pdev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct of_device_id al_pcie_of_match[] = {
+ { .compatible = "amazon,al-pcie",
+ },
+ {},
+};
+
+static struct platform_driver al_pcie_driver = {
+ .driver = {
+ .name = "al-pcie",
+ .of_match_table = al_pcie_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = al_pcie_probe,
+};
+builtin_platform_driver(al_pcie_driver);
+
+#endif /* CONFIG_PCIE_AL*/
--
2.17.1
^ permalink raw reply related
* [PATCH v2 5/8] dt-bindings: PCI: Add Amazon's Annapurna Labs PCIe host bridge binding
From: Jonathan Chocron @ 2019-07-18 9:47 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas, jingoohan1, gustavo.pimentel,
robh+dt, mark.rutland
Cc: dwmw, benh, alisaidi, ronenk, barakw, talel, hanochu, hhhawa,
linux-pci, linux-kernel, devicetree, jonnyc
In-Reply-To: <20190718094531.21423-1-jonnyc@amazon.com>
Document Amazon's Annapurna Labs PCIe host bridge.
Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
---
.../devicetree/bindings/pci/pcie-al.txt | 45 +++++++++++++++++++
MAINTAINERS | 3 +-
2 files changed, 47 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/pci/pcie-al.txt
diff --git a/Documentation/devicetree/bindings/pci/pcie-al.txt b/Documentation/devicetree/bindings/pci/pcie-al.txt
new file mode 100644
index 000000000000..89876190eb5a
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/pcie-al.txt
@@ -0,0 +1,45 @@
+* Amazon Annapurna Labs PCIe host bridge
+
+Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
+PCI core.
+It shares common functions with the PCIe DesignWare core driver and inherits
+common properties defined in Documentation/devicetree/bindings/pci/designware-pcie.txt.
+Properties of the host controller node that differ from it are:
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Value should contain
+ - "amazon,al-pcie"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Register ranges as listed in the reg-names property
+
+- reg-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Must include the following entries
+ - "config" PCIe ECAM space
+ - "controller" AL proprietary registers
+ - "dbi" Designware PCIe registers
+
+Example:
+
+ pcie-external0: pcie@fb600000 {
+ compatible = "amazon,al-pcie";
+ reg = <0x0 0xfb600000 0x0 0x00100000
+ 0x0 0xfd800000 0x0 0x00010000
+ 0x0 0xfd810000 0x0 0x00001000>;
+ reg-names = "config", "controller", "dbi";
+ bus-range = <0 255>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x00 0 0 7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */
+ ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 5a6137df3f0e..29cca14a05a6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12201,10 +12201,11 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/
S: Supported
F: drivers/pci/controller/
-PCIE DRIVER FOR ANNAPURNA LABS
+PCIE DRIVER FOR AMAZON ANNAPURNA LABS
M: Jonathan Chocron <jonnyc@amazon.com>
L: linux-pci@vger.kernel.org
S: Maintained
+F: Documentation/devicetree/bindings/pci/pcie-al.txt
F: drivers/pci/controller/dwc/pcie-al.c
PCIE DRIVER FOR AMLOGIC MESON
--
2.17.1
^ permalink raw reply related
* [PATCH v2 4/8] PCI: Add quirk to disable MSI-X support for Amazon's Annapurna Labs Root Port
From: Jonathan Chocron @ 2019-07-18 9:45 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas, jingoohan1, gustavo.pimentel,
robh+dt, mark.rutland
Cc: dwmw, benh, alisaidi, ronenk, barakw, talel, hanochu, hhhawa,
linux-pci, linux-kernel, devicetree, jonnyc
In-Reply-To: <20190718094531.21423-1-jonnyc@amazon.com>
The Root Port (identified by [1c36:0032]) doesn't support MSI-X. On some
platforms it is configured to not advertise the capability at all, while
on others it (mistakenly) does. This causes a panic during
initialization by the pcieport driver, since it tries to configure the
MSI-X capability. Specifically, when trying to access the MSI-X table
a "non-existing addr" exception occurs.
Example stacktrace snippet:
[ 1.632363] SError Interrupt on CPU2, code 0xbf000000 -- SError
[ 1.632364] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.2.0-rc1-Jonny-14847-ge76f1d4a1828-dirty #33
[ 1.632365] Hardware name: Annapurna Labs Alpine V3 EVP (DT)
[ 1.632365] pstate: 80000005 (Nzcv daif -PAN -UAO)
[ 1.632366] pc : __pci_enable_msix_range+0x4e4/0x608
[ 1.632367] lr : __pci_enable_msix_range+0x498/0x608
[ 1.632367] sp : ffffff80117db700
[ 1.632368] x29: ffffff80117db700 x28: 0000000000000001
[ 1.632370] x27: 0000000000000001 x26: 0000000000000000
[ 1.632372] x25: ffffffd3e9d8c0b0 x24: 0000000000000000
[ 1.632373] x23: 0000000000000000 x22: 0000000000000000
[ 1.632375] x21: 0000000000000001 x20: 0000000000000000
[ 1.632376] x19: ffffffd3e9d8c000 x18: ffffffffffffffff
[ 1.632378] x17: 0000000000000000 x16: 0000000000000000
[ 1.632379] x15: ffffff80116496c8 x14: ffffffd3e9844503
[ 1.632380] x13: ffffffd3e9844502 x12: 0000000000000038
[ 1.632382] x11: ffffffffffffff00 x10: 0000000000000040
[ 1.632384] x9 : ffffff801165e270 x8 : ffffff801165e268
[ 1.632385] x7 : 0000000000000002 x6 : 00000000000000b2
[ 1.632387] x5 : ffffffd3e9d8c2c0 x4 : 0000000000000000
[ 1.632388] x3 : 0000000000000000 x2 : 0000000000000000
[ 1.632390] x1 : 0000000000000000 x0 : ffffffd3e9844680
[ 1.632392] Kernel panic - not syncing: Asynchronous SError Interrupt
[ 1.632393] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.2.0-rc1-Jonny-14847-ge76f1d4a1828-dirty #33
[ 1.632394] Hardware name: Annapurna Labs Alpine V3 EVP (DT)
[ 1.632394] Call trace:
[ 1.632395] dump_backtrace+0x0/0x140
[ 1.632395] show_stack+0x14/0x20
[ 1.632396] dump_stack+0xa8/0xcc
[ 1.632396] panic+0x140/0x334
[ 1.632397] nmi_panic+0x6c/0x70
[ 1.632398] arm64_serror_panic+0x74/0x88
[ 1.632398] __pte_error+0x0/0x28
[ 1.632399] el1_error+0x84/0xf8
[ 1.632400] __pci_enable_msix_range+0x4e4/0x608
[ 1.632400] pci_alloc_irq_vectors_affinity+0xdc/0x150
[ 1.632401] pcie_port_device_register+0x2b8/0x4e0
[ 1.632402] pcie_portdrv_probe+0x34/0xf0
Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
---
drivers/pci/quirks.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 23672680dba7..11f843aa96b3 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2925,6 +2925,21 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
quirk_msi_intx_disable_qca_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
quirk_msi_intx_disable_qca_bug);
+
+/*
+ * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
+ * should be disabled on platforms where the device (mistakenly) advertises it.
+ *
+ * The 0031 device id is reused for other non Root Port device types,
+ * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
+ */
+static void quirk_al_msi_disable(struct pci_dev *dev)
+{
+ dev->no_msi = 1;
+ pci_warn(dev, "Disabling MSI-X\n");
+}
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
+ PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
#endif /* CONFIG_PCI_MSI */
/*
--
2.17.1
^ permalink raw reply related
* [PATCH v2 3/8] PCI/VPD: Add VPD release quirk for Amazon's Annapurna Labs Root Port
From: Jonathan Chocron @ 2019-07-18 9:45 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas, jingoohan1, gustavo.pimentel,
robh+dt, mark.rutland
Cc: dwmw, benh, alisaidi, ronenk, barakw, talel, hanochu, hhhawa,
linux-pci, linux-kernel, devicetree, jonnyc
In-Reply-To: <20190718094531.21423-1-jonnyc@amazon.com>
The Amazon Annapurna Labs PCIe Root Port exposes the VPD capability,
but there is no actual support for it.
The reason for not using the already existing quirk_blacklist_vpd()
is that, although this fails pci_vpd_read/write, the 'vpd' sysfs
entry still exists. When running lspci -vv, for example, this
results in the following error:
pcilib: sysfs_read_vpd: read failed: Input/output error
This quirk removes the sysfs entry, which avoids the error print.
Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
---
drivers/pci/vpd.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/pci/vpd.c b/drivers/pci/vpd.c
index 4963c2e2bd4c..c23a8ec08db9 100644
--- a/drivers/pci/vpd.c
+++ b/drivers/pci/vpd.c
@@ -644,4 +644,20 @@ static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
quirk_chelsio_extend_vpd);
+static void quirk_al_vpd_release(struct pci_dev *dev)
+{
+ if (dev->vpd) {
+ pci_vpd_release(dev);
+ dev->vpd = NULL;
+ pci_warn(dev, FW_BUG "Releasing VPD capability (No support for VPD read/write transactions)\n");
+ }
+}
+
+/*
+ * The 0031 device id is reused for other non Root Port device types,
+ * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
+ */
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
+ PCI_CLASS_BRIDGE_PCI, 8, quirk_al_vpd_release);
+
#endif
--
2.17.1
^ permalink raw reply related
* [PATCH v2 2/8] PCI: Add ACS quirk for Amazon Annapurna Labs root ports
From: Jonathan Chocron @ 2019-07-18 9:45 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas, jingoohan1, gustavo.pimentel,
robh+dt, mark.rutland
Cc: dwmw, benh, alisaidi, ronenk, barakw, talel, hanochu, hhhawa,
linux-pci, linux-kernel, devicetree, jonnyc
In-Reply-To: <20190718094531.21423-1-jonnyc@amazon.com>
From: Ali Saidi <alisaidi@amazon.com>
The Amazon's Annapurna Labs root ports don't advertise an ACS
capability, but they don't allow peer-to-peer transactions and do
validate bus numbers through the SMMU. Additionally, it's not possible
for one RP to pass traffic to another RP.
Signed-off-by: Ali Saidi <alisaidi@amazon.com>
Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
---
drivers/pci/quirks.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 208aacf39329..23672680dba7 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -4366,6 +4366,23 @@ static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
return ret;
}
+static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
+{
+ /*
+ * Amazon's Annapurna Labs root ports don't include an ACS capability,
+ * but do include ACS-like functionality. The hardware doesn't support
+ * peer-to-peer transactions via the root port and each has a unique
+ * segment number.
+ * Additionally, the root ports cannot send traffic to each other.
+ */
+ acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);
+
+ if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
+ return -ENOTTY;
+
+ return acs_flags ? 0 : 1;
+}
+
/*
* Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
* the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
@@ -4559,6 +4576,8 @@ static const struct pci_dev_acs_enabled {
{ PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
{ PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
{ PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
+ /* Amazon Annapurna Labs */
+ { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
{ 0 }
};
--
2.17.1
^ permalink raw reply related
* [PATCH v2 1/8] PCI: Add Amazon's Annapurna Labs vendor ID
From: Jonathan Chocron @ 2019-07-18 9:45 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas, jingoohan1, gustavo.pimentel,
robh+dt, mark.rutland
Cc: dwmw, benh, alisaidi, ronenk, barakw, talel, hanochu, hhhawa,
linux-pci, linux-kernel, devicetree, jonnyc
In-Reply-To: <20190718094531.21423-1-jonnyc@amazon.com>
Add Amazon's Annapurna Labs vendor ID to pci_ids.h.
Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
---
include/linux/pci_ids.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 40015609c4b5..63dfa4bace57 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2569,6 +2569,8 @@
#define PCI_VENDOR_ID_ASMEDIA 0x1b21
+#define PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS 0x1c36
+
#define PCI_VENDOR_ID_CIRCUITCO 0x1cc8
#define PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD 0x0001
--
2.17.1
^ permalink raw reply related
* [PATCH v2 0/8] Amazon's Annapurna Labs DT-based PCIe host controller driver
From: Jonathan Chocron @ 2019-07-18 9:45 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas, jingoohan1, gustavo.pimentel,
robh+dt, mark.rutland
Cc: dwmw, benh, alisaidi, ronenk, barakw, talel, hanochu, hhhawa,
linux-pci, linux-kernel, devicetree, jonnyc
This series adds support for Amazon's Annapurna Labs DT-based PCIe host
controller driver.
Additionally, it adds 3 quirks (ACS, VPD and MSI-X) and 2 generic DWC patches.
Regarding the 2nd DWC patch (PCI flags support), do you think this should
be done in the context of a host-bridge driver at all (as opposed to PCI
system-wide code)?
Changes since v1:
- Added comment regarding 0x0031 being used as a dev_id for non root-port devices as well
- Fixed different message/comment/print wordings
- Added panic stacktrace to commit message of MSI-x quirk patch
- Changed to pci_warn() instead of dev_warn()
- Added unit_address after node_name in dt-binding
- Updated Kconfig help description
- Used GENMASK and FIELD_PREP/GET where appropriate
- Removed leftover field from struct al_pcie and moved all ptrs to
the beginning
- Re-wrapped function definitions and invocations to use fewer lines
- Change %p to %px in dbg prints in rd/wr_conf() functions
- Removed validation that the port is configured to RC mode (as this is
added generically in PATCH 7/8)
- Removed unnecessary variable initializations
- Swtiched to %pR for printing resources
Ali Saidi (1):
PCI: Add ACS quirk for Amazon Annapurna Labs root ports
Jonathan Chocron (7):
PCI: Add Amazon's Annapurna Labs vendor ID
PCI/VPD: Add VPD release quirk for Amazon's Annapurna Labs Root Port
PCI: Add quirk to disable MSI-X support for Amazon's Annapurna Labs
Root Port
dt-bindings: PCI: Add Amazon's Annapurna Labs PCIe host bridge binding
PCI: al: Add support for DW based driver type
PCI: dw: Add validation that PCIe core is set to correct mode
PCI: dw: Add support for PCI_PROBE_ONLY/PCI_REASSIGN_ALL_BUS flags
.../devicetree/bindings/pci/pcie-al.txt | 45 +++
MAINTAINERS | 3 +-
drivers/pci/controller/dwc/Kconfig | 12 +
drivers/pci/controller/dwc/pcie-al.c | 373 ++++++++++++++++++
.../pci/controller/dwc/pcie-designware-ep.c | 8 +
.../pci/controller/dwc/pcie-designware-host.c | 31 +-
drivers/pci/quirks.c | 34 ++
drivers/pci/vpd.c | 16 +
include/linux/pci_ids.h | 2 +
9 files changed, 519 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/pcie-al.txt
--
2.17.1
^ permalink raw reply
* Re: [PATCHv8 2/5] arm64: dts: qcom: msm8998: Add Coresight support
From: Suzuki K Poulose @ 2019-07-18 9:37 UTC (permalink / raw)
To: saiprakash.ranjan, gregkh, mathieu.poirier, leo.yan,
alexander.shishkin, mike.leach, robh+dt, bjorn.andersson,
devicetree, david.brown, mark.rutland
Cc: rnayak, vivek.gautam, sibis, linux-arm-kernel, linux-kernel,
linux-arm-msm, marc.w.gonzalez
In-Reply-To: <4854b0f7-6a81-bc87-3e63-d2b7c68a44f6@codeaurora.org>
On 18/07/2019 10:14, Sai Prakash Ranjan wrote:
> Hi Suzuki,
>
> On 7/18/2019 1:58 PM, Suzuki K Poulose wrote:
>> Hi Sai,
>>
>>
>> etr@6048000 {
>>> + compatible = "arm,coresight-tmc", "arm,primecell";
>>> + reg = <0x06048000 0x1000>;
>>> +
>>> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc
>>> RPM_SMD_QDSS_A_CLK>;
>>> + clock-names = "apb_pclk", "atclk";
>>> + arm,scatter-gather;
>>
>> Please could you confirm that you have tested the scatter-gather mode
>> with ETR ? Either via perf/sysfs. Please could you share your results ?
>> Unless verified
>> this is going to be fatal for the system.
>>
>> Similarly for other platforms.
>>
>
> Yes I have tested with scatter-gather mode with ETR on all platforms
> which I have posted via sysfs(not perf) before on previous versions of
> this patch series and no issues were found. And I suppose this was
> discussed in v2 of this patch series [1].
Using the sysfs doesn't guarantee that the ETR actually uses SG mode, unless
the buffer size selected is > 1M, which is why I am more interested in the
perf usage. Alternatively you may configure a larger buffer size (say, 8MB) via:
echo 0x800000 > /sys/bus/coresight/.../tmc_etr0/buffer_size
>
> As said in one of the series initially [1], QCOM msm downstream kernels
> have been using scatter gather mode and we haven't seen any fatal issues.
>
> [1] https://patchwork.kernel.org/patch/10769535/
I haven't seen any test results there either.
Cheers
Suzuki
^ permalink raw reply
* [PATCH] ARM: dts: meson8b: add ethernet fifo sizes
From: Jerome Brunet @ 2019-07-18 9:36 UTC (permalink / raw)
To: Kevin Hilman; +Cc: Jerome Brunet, linux-amlogic, devicetree, linux-kernel
If unspecified in DT, the fifo sizes are not automatically detected by
the dwmac1000 dma driver and the reported fifo sizes default to 0.
Because of this, flow control will be turned off on the device.
Add the fifo sizes provided by the datasheet in the SoC in DT so
flow control may be enabled if necessary.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
arch/arm/boot/dts/meson8b.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index fba2c70c2fda..b044ad78b475 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -410,6 +410,8 @@
<&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
+ rx-fifo-depth = <4096>;
+ tx-fifo-depth = <2048>;
resets = <&reset RESET_ETHERNET>;
reset-names = "stmmaceth";
--
2.21.0
^ permalink raw reply related
* Re: [PATCH v2] pinctrl: msm8998: Squash TSIF pins together
From: Marc Gonzalez @ 2019-07-18 9:30 UTC (permalink / raw)
To: Bjorn Andersson, Andy Gross
Cc: DT, Jeffrey Hugo, MSM, Linus Walleij, Jonathan Neuschäfer,
gpio, Rob Herring, Linux ARM
In-Reply-To: <20190704163527.GJ12249@tuxbook-pro>
On 04/07/2019 18:35, Bjorn Andersson wrote:
> On Thu 04 Jul 01:57 PDT 2019, Marc Gonzalez wrote:
>
>> TSIF is the Transport Stream Interface.
>> First, rename tsif1 to tsif0, and tsif2 to tsif1.
>> Then squash all 5 tsif0 pins into a single function.
>> Same for tsif1.
>>
>> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
>
> Thanks for the respin Marc.
>
> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Can you or Andy pick it up for inclusion in linux-next?
Regards.
^ permalink raw reply
* [PATCH 4/4] ARM: dts: imx6sll: move GIC to right location in DT
From: Anson.Huang @ 2019-07-18 9:15 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
devicetree, linux-arm-kernel, linux-kernel
Cc: Linux-imx
In-Reply-To: <20190718091508.3248-1-Anson.Huang@nxp.com>
From: Anson Huang <Anson.Huang@nxp.com>
GIC is inside of SoC from architecture perspective, it should
be located inside of soc node in DT.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
arch/arm/boot/dts/imx6sll.dtsi | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index b0a77ff..0e8116d 100644
--- a/arch/arm/boot/dts/imx6sll.dtsi
+++ b/arch/arm/boot/dts/imx6sll.dtsi
@@ -75,15 +75,6 @@
};
};
- intc: interrupt-controller@a01000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x00a01000 0x1000>,
- <0x00a00100 0x100>;
- interrupt-parent = <&intc>;
- };
-
ckil: clock-ckil {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -134,6 +125,15 @@
reg = <0x00900000 0x20000>;
};
+ intc: interrupt-controller@a01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a00100 0x100>;
+ interrupt-parent = <&intc>;
+ };
+
L2: l2-cache@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
--
2.7.4
^ permalink raw reply related
* [PATCH 3/4] ARM: dts: imx6ul: move GIC to right location in DT
From: Anson.Huang @ 2019-07-18 9:15 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
devicetree, linux-arm-kernel, linux-kernel
Cc: Linux-imx
In-Reply-To: <20190718091508.3248-1-Anson.Huang@nxp.com>
From: Anson Huang <Anson.Huang@nxp.com>
GIC is inside of SoC from architecture perspective, it should
be located inside of soc node in DT.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
arch/arm/boot/dts/imx6ul.dtsi | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 81d4b49..da1eae6 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -93,18 +93,6 @@
};
};
- intc: interrupt-controller@a01000 {
- compatible = "arm,gic-400", "arm,cortex-a7-gic";
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
- #interrupt-cells = <3>;
- interrupt-controller;
- interrupt-parent = <&intc>;
- reg = <0x00a01000 0x1000>,
- <0x00a02000 0x2000>,
- <0x00a04000 0x2000>,
- <0x00a06000 0x2000>;
- };
-
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
@@ -171,6 +159,18 @@
reg = <0x00900000 0x20000>;
};
+ intc: interrupt-controller@a01000 {
+ compatible = "arm,gic-400", "arm,cortex-a7-gic";
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ reg = <0x00a01000 0x1000>,
+ <0x00a02000 0x2000>,
+ <0x00a04000 0x2000>,
+ <0x00a06000 0x2000>;
+ };
+
dma_apbh: dma-apbh@1804000 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0x01804000 0x2000>;
--
2.7.4
^ permalink raw reply related
* [PATCH 2/4] ARM: dts: imx6sl: move GIC to right location in DT
From: Anson.Huang @ 2019-07-18 9:15 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
devicetree, linux-arm-kernel, linux-kernel
Cc: Linux-imx
In-Reply-To: <20190718091508.3248-1-Anson.Huang@nxp.com>
From: Anson Huang <Anson.Huang@nxp.com>
GIC is inside of SoC from architecture perspective, it should
be located inside of soc node in DT.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
arch/arm/boot/dts/imx6sl.dtsi | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index b36fc01..3a96b55 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -77,15 +77,6 @@
};
};
- intc: interrupt-controller@a01000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x00a01000 0x1000>,
- <0x00a00100 0x100>;
- interrupt-parent = <&intc>;
- };
-
clocks {
ckil {
compatible = "fixed-clock";
@@ -133,6 +124,15 @@
clocks = <&clks IMX6SL_CLK_OCRAM>;
};
+ intc: interrupt-controller@a01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a00100 0x100>;
+ interrupt-parent = <&intc>;
+ };
+
L2: l2-cache@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
--
2.7.4
^ permalink raw reply related
* [PATCH 1/4] ARM: dts: imx6sx: move GIC to right location in DT
From: Anson.Huang @ 2019-07-18 9:15 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
devicetree, linux-arm-kernel, linux-kernel
Cc: Linux-imx
From: Anson Huang <Anson.Huang@nxp.com>
GIC is inside of SoC from architecture perspective, it should
be located inside of soc node in DT.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
arch/arm/boot/dts/imx6sx.dtsi | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index bb25add..fe00f9a 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -90,15 +90,6 @@
};
};
- intc: interrupt-controller@a01000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x00a01000 0x1000>,
- <0x00a00100 0x100>;
- interrupt-parent = <&intc>;
- };
-
ckil: clock-ckil {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -181,6 +172,15 @@
clocks = <&clks IMX6SX_CLK_OCRAM>;
};
+ intc: interrupt-controller@a01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a00100 0x100>;
+ interrupt-parent = <&intc>;
+ };
+
L2: l2-cache@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
--
2.7.4
^ permalink raw reply related
* Re: [PATCHv8 2/5] arm64: dts: qcom: msm8998: Add Coresight support
From: Sai Prakash Ranjan @ 2019-07-18 9:14 UTC (permalink / raw)
To: Suzuki K Poulose, gregkh, mathieu.poirier, leo.yan,
alexander.shishkin, mike.leach, robh+dt, bjorn.andersson,
devicetree, david.brown, mark.rutland
Cc: rnayak, vivek.gautam, sibis, linux-arm-kernel, linux-kernel,
linux-arm-msm, marc.w.gonzalez
In-Reply-To: <3b192063-f31f-b861-d913-61d737cecc57@arm.com>
Hi Suzuki,
On 7/18/2019 1:58 PM, Suzuki K Poulose wrote:
> Hi Sai,
>
>
> etr@6048000 {
>> + compatible = "arm,coresight-tmc", "arm,primecell";
>> + reg = <0x06048000 0x1000>;
>> +
>> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc
>> RPM_SMD_QDSS_A_CLK>;
>> + clock-names = "apb_pclk", "atclk";
>> + arm,scatter-gather;
>
> Please could you confirm that you have tested the scatter-gather mode
> with ETR ? Either via perf/sysfs. Please could you share your results ?
> Unless verified
> this is going to be fatal for the system.
>
> Similarly for other platforms.
>
Yes I have tested with scatter-gather mode with ETR on all platforms
which I have posted via sysfs(not perf) before on previous versions of
this patch series and no issues were found. And I suppose this was
discussed in v2 of this patch series [1].
As said in one of the series initially [1], QCOM msm downstream kernels
have been using scatter gather mode and we haven't seen any fatal issues.
[1] https://patchwork.kernel.org/patch/10769535/
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* [PATCH] arm64: dts: meson: add ethernet fifo sizes
From: Jerome Brunet @ 2019-07-18 9:03 UTC (permalink / raw)
To: Kevin Hilman; +Cc: Jerome Brunet, devicetree, linux-amlogic, linux-kernel
If unspecified in DT, the fifo sizes are not automatically detected by
the dwmac1000 dma driver and the reported fifo sizes default to 0.
Because of this, flow control will be turned off on the device.
Add the fifo sizes provided by the datasheets in the SoC in DT so
flow control may be enabled if necessary.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 2 ++
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 2 ++
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 2 ++
3 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 6219337033a0..12bf959c17a7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -182,6 +182,8 @@
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
+ rx-fifo-depth = <4096>;
+ tx-fifo-depth = <2048>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 0bb9705a33f1..c8b9b9754598 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -150,6 +150,8 @@
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
+ rx-fifo-depth = <4096>;
+ tx-fifo-depth = <2048>;
status = "disabled";
mdio0: mdio {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 74d03fc706be..e62aad5bf867 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -493,6 +493,8 @@
0x0 0xc8834540 0x0 0x4>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
+ rx-fifo-depth = <4096>;
+ tx-fifo-depth = <2048>;
status = "disabled";
};
--
2.21.0
^ permalink raw reply related
* Re: [PATCHv8 2/5] arm64: dts: qcom: msm8998: Add Coresight support
From: Suzuki K Poulose @ 2019-07-18 8:28 UTC (permalink / raw)
To: saiprakash.ranjan, gregkh, mathieu.poirier, leo.yan,
alexander.shishkin, mike.leach, robh+dt, bjorn.andersson,
devicetree, david.brown, mark.rutland
Cc: rnayak, vivek.gautam, sibis, linux-arm-kernel, linux-kernel,
linux-arm-msm, marc.w.gonzalez
In-Reply-To: <e510df23f741205fac9030f2c95d06d607549caa.1562940244.git.saiprakash.ranjan@codeaurora.org>
Hi Sai,
On 12/07/2019 15:16, Sai Prakash Ranjan wrote:
> Enable coresight support by adding device nodes for the
> available source, sinks and channel blocks on MSM8998.
>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> arch/arm64/boot/dts/qcom/msm8998.dtsi | 435 ++++++++++++++++++++++++++
> 1 file changed, 435 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> index c13ed7aeb1e0..ad9cb5e8675d 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> @@ -822,6 +822,441 @@
etr@6048000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x06048000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> + arm,scatter-gather;
Please could you confirm that you have tested the scatter-gather mode with ETR ?
Either via perf/sysfs. Please could you share your results ? Unless verified
this is going to be fatal for the system.
Similarly for other platforms.
Kind regards
Suzuki
^ permalink raw reply
* Re: [PATCH 1/2] arm64: dts: imx8mq: Add gpio-ranges property
From: Shawn Guo @ 2019-07-18 8:14 UTC (permalink / raw)
To: Anson.Huang
Cc: robh+dt, mark.rutland, s.hauer, kernel, festevam, leonard.crestez,
viresh.kumar, ping.bai, daniel.baluta, l.stach, abel.vesa,
andrew.smirnov, angus, ccaione, agx, devicetree, linux-arm-kernel,
linux-kernel, Linux-imx
In-Reply-To: <20190702014400.33554-1-Anson.Huang@nxp.com>
On Tue, Jul 02, 2019 at 09:43:59AM +0800, Anson.Huang@nxp.com wrote:
> From: Anson Huang <Anson.Huang@nxp.com>
>
> Add "gpio-ranges" property to establish connections between GPIOs
> and PINs on i.MX8MQ pinctrl driver.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Applied both, thanks.
^ permalink raw reply
* Re: [PATCH V2 1/2] arm64: dts: imx8mm: Correct OPP table according to latest datasheet
From: Shawn Guo @ 2019-07-18 8:03 UTC (permalink / raw)
To: Anson.Huang
Cc: robh+dt, mark.rutland, s.hauer, kernel, festevam, leonard.crestez,
viresh.kumar, ping.bai, daniel.baluta, l.stach, abel.vesa,
andrew.smirnov, ccaione, angus, agx, devicetree, linux-arm-kernel,
linux-kernel, Linux-imx
In-Reply-To: <20190629102157.8026-1-Anson.Huang@nxp.com>
On Sat, Jun 29, 2019 at 06:21:56PM +0800, Anson.Huang@nxp.com wrote:
> From: Anson Huang <Anson.Huang@nxp.com>
>
> According to latest datasheet (Rev.0.2, 04/2019) from below links,
> 1.8GHz is ONLY available for consumer part, so the market segment
> bits for 1.8GHz opp should ONLY available for consumer part accordingly.
>
> https://www.nxp.com/docs/en/data-sheet/IMX8MMIEC.pdf
> https://www.nxp.com/docs/en/data-sheet/IMX8MMCEC.pdf
>
> Fixes: f403a26c865b (arm64: dts: imx8mm: Add cpu speed grading and all OPPs)
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Applied both, thanks.
^ permalink raw reply
* [PATCH v1 2/2] auxadc: mediatek: support efuse calibration in auxadc driver
From: Zhiyong Tao @ 2019-07-18 8:01 UTC (permalink / raw)
To: robh+dt, jic23, knaack.h, lars, pmeerw
Cc: srv_heupstream, hui.liu, jg_poxu, sj.huang, yingjoe.chen,
sean.wang, erin.lo, eddie.huang, matthias.bgg, s.hauer,
devicetree, linux-kernel, linux-arm-kernel, linux-iio,
linux-mediatek, Zhiyong Tao
In-Reply-To: <20190718080119.30707-1-zhiyong.tao@mediatek.com>
This patch support efuse calibration in auxadc driver
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: jg_poxu <jg_poxu@mediatek.com>
---
drivers/iio/adc/mt6577_auxadc.c | 71 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 71 insertions(+)
diff --git a/drivers/iio/adc/mt6577_auxadc.c b/drivers/iio/adc/mt6577_auxadc.c
index 95d76abb64ec..e30d9736b1a5 100644
--- a/drivers/iio/adc/mt6577_auxadc.c
+++ b/drivers/iio/adc/mt6577_auxadc.c
@@ -17,12 +17,14 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/iopoll.h>
#include <linux/io.h>
#include <linux/iio/iio.h>
+#include <linux/slab.h>
/* Register definitions */
#define MT6577_AUXADC_CON0 0x00
@@ -42,6 +44,13 @@
#define MT6577_AUXADC_POWER_READY_MS 1
#define MT6577_AUXADC_SAMPLE_READY_US 25
+#define ADC_GE_A_SHIFT 10
+#define ADC_GE_A_MASK (0x3ff << ADC_GE_A_SHIFT)
+#define ADC_OE_A_SHIFT 0
+#define ADC_OE_A_MASK (0x3ff << ADC_OE_A_SHIFT)
+#define ADC_CALI_EN_A_SHIFT 20
+#define ADC_CALI_EN_A_MASK (0x1 << ADC_CALI_EN_A_SHIFT)
+
struct mt6577_auxadc_device {
void __iomem *reg_base;
struct clk *adc_clk;
@@ -74,6 +83,64 @@ static const struct iio_chan_spec mt6577_auxadc_iio_channels[] = {
MT6577_AUXADC_CHANNEL(15),
};
+s32 cali_oe;
+s32 cali_ge;
+struct adc_cali_info {
+ u32 cali_ge_a;
+ u32 cali_oe_a;
+ u32 gain;
+};
+static struct adc_cali_info adc_cali;
+
+static int mt6577_auxadc_update_cali(struct device *dev)
+{
+ struct nvmem_cell *cell;
+ u32 *buf;
+ size_t len;
+ int ret = 0;
+
+ cali_oe = 0;
+ cali_ge = 0;
+
+ cell = nvmem_cell_get(dev, "calibration-data");
+ if (IS_ERR(cell)) {
+ if (PTR_ERR(cell) == -EPROBE_DEFER)
+ return PTR_ERR(cell);
+ return 0;
+ }
+
+ buf = (u32 *)nvmem_cell_read(cell, &len);
+
+ nvmem_cell_put(cell);
+
+ if (IS_ERR(buf))
+ return PTR_ERR(buf);
+
+ if (len < sizeof(u32)) {
+ dev_warn(dev, "invalid calibration data\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (((buf[0] & ADC_CALI_EN_A_MASK) >> ADC_CALI_EN_A_SHIFT) != 0) {
+ adc_cali.cali_oe_a =
+ (buf[0] & ADC_OE_A_MASK) >> ADC_OE_A_SHIFT;
+ adc_cali.cali_ge_a =
+ ((buf[0] & ADC_GE_A_MASK) >> ADC_GE_A_SHIFT);
+
+ cali_ge = adc_cali.cali_ge_a - 512;
+ cali_oe = adc_cali.cali_oe_a - 512;
+ adc_cali.gain = 1 + cali_ge;
+ } else {
+ dev_info(dev, "Device not calibrated, using default calibration values\n");
+ }
+
+out:
+ kfree(buf);
+
+ return ret;
+}
+
static inline void mt6577_auxadc_mod_reg(void __iomem *reg,
u32 or_mask, u32 and_mask)
{
@@ -274,6 +341,10 @@ static int mt6577_auxadc_probe(struct platform_device *pdev)
goto err_power_off;
}
+ ret = mt6577_auxadc_update_cali(&pdev->dev);
+ if (ret)
+ return ret;
+
return 0;
err_power_off:
--
2.12.5
^ permalink raw reply related
* [PATCH v1 1/2] arm64: dts: mt8183: auxadc: add efuse information in device tree
From: Zhiyong Tao @ 2019-07-18 8:01 UTC (permalink / raw)
To: robh+dt, jic23, knaack.h, lars, pmeerw
Cc: srv_heupstream, hui.liu, jg_poxu, sj.huang, yingjoe.chen,
sean.wang, erin.lo, eddie.huang, matthias.bgg, s.hauer,
devicetree, linux-kernel, linux-arm-kernel, linux-iio,
linux-mediatek, Zhiyong Tao
In-Reply-To: <20190718080119.30707-1-zhiyong.tao@mediatek.com>
The commit add add efuse information in device tree
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: jg_poxu <jg_poxu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index c2749c4631bc..59b4f3d933b5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -261,6 +261,8 @@
clocks = <&infracfg CLK_INFRA_AUXADC>;
clock-names = "main";
#io-channel-cells = <1>;
+ nvmem-cells = <&auxadc_calibration>;
+ nvmem-cell-names = "calibration-data";
status = "disabled";
};
@@ -382,6 +384,9 @@
compatible = "mediatek,mt8183-efuse",
"mediatek,efuse";
reg = <0 0x11f10000 0 0x1000>;
+ auxadc_calibration: auxadccali@1b4 {
+ reg = <0x1b4 0x4>;
+ };
};
mfgcfg: syscon@13000000 {
--
2.12.5
^ permalink raw reply related
* [PATCH v1 0/2] AUXADC: support efuse calibration on MT818
From: Zhiyong Tao @ 2019-07-18 8:01 UTC (permalink / raw)
To: robh+dt, jic23, knaack.h, lars, pmeerw
Cc: srv_heupstream, hui.liu, jg_poxu, sj.huang, yingjoe.chen,
sean.wang, erin.lo, eddie.huang, matthias.bgg, s.hauer,
devicetree, linux-kernel, linux-arm-kernel, linux-iio,
linux-mediatek
This series includes two patches:
1.Add mt8183 auxadc efuse information in device tree.
1.Add mt8183 efuse calibration function in auxadc driver.
Zhiyong Tao (2):
arm64: dts: mt8183: auxadc: add efuse information in device tree
auxadc: mediatek: support efuse calibration in auxadc driver
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 5 +++
drivers/iio/adc/mt6577_auxadc.c | 71 ++++++++++++++++++++++++++++++++
2 files changed, 76 insertions(+)
--
2.12.5
^ permalink raw reply
* Re: [PATCH v2 1/2] firmware: imx: Add DSP IPC protocol interface
From: Daniel Baluta @ 2019-07-18 6:40 UTC (permalink / raw)
To: Oleksij Rempel
Cc: Aisheng Dong, mark.rutland@arm.com, Anson Huang,
devicetree@vger.kernel.org, Daniel Baluta, s.hauer@pengutronix.de,
linux-kernel@vger.kernel.org, robh+dt@kernel.org, dl-linux-imx,
festevam@gmail.com, shawnguo@kernel.org, S.j. Wang,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190709120241.nlzy7o6etucn5udk@pengutronix.de>
I just made some minor changes and will send the patch right now.
Shawn please skip this.
On Tue, Jul 9, 2019 at 3:02 PM Oleksij Rempel <o.rempel@pengutronix.de> wrote:
>
> On Tue, Jul 09, 2019 at 08:48:20AM +0300, Daniel Baluta wrote:
> > Hi Oleksij,
> >
> > Any comments on this?
>
> Looks good for me. All my suggestions was fixed.
>
> Reviewed-by: <o.rempel@pengutronix.de>
>
> > On Thu, Jun 27, 2019 at 11:14 AM Daniel Baluta <daniel.baluta@nxp.com> wrote:
> > >
> > > Some of i.MX8 processors (e.g i.MX8QM, i.MX8QXP) contain
> > > the Tensilica HiFi4 DSP for advanced pre- and post-audio
> > > processing.
> > >
> > > The communication between Host CPU and DSP firmware is
> > > taking place using a shared memory area for message passing
> > > and a dedicated Messaging Unit for notifications.
> > >
> > > DSP IPC protocol driver offers a doorbell interface using
> > > imx-mailbox API.
> > >
> > > We use 4 MU channels (2 x TXDB, 2 x RXDB) to implement a
> > > request-reply protocol.
> > >
> > > Connection 0 (txdb0, rxdb0):
> > > - Host writes messasge to shared memory [SHMEM]
> > > - Host sends a request [MU]
> > > - DSP handles request [SHMEM]
> > > - DSP sends reply [MU]
> > >
> > > Connection 1 (txdb1, rxdb1):
> > > - DSP writes a message to shared memory [SHMEM]
> > > - DSP sends a request [MU]
> > > - Host handles request [SHMEM]
> > > - Host sends reply [MU]
> > >
> > > The protocol driver will be used by a Host client to
> > > communicate with the DSP. First client will be the i.MX8
> > > part from Sound Open Firmware infrastructure.
> > >
> > > The protocol drivers offers the following interface:
> > >
> > > On Tx:
> > > - imx_dsp_ring_doorbell, will be called to notify the DSP
> > > that it needs to handle a request.
> > >
> > > On Rx:
> > > - clients need to provide two callbacks:
> > > .handle_reply
> > > .handle_request
> > > - the callbacks will be used by the protocol driver on
> > > notification arrival from DSP.
> > >
> > > Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
> > > ---
> > > drivers/firmware/imx/Kconfig | 11 +++
> > > drivers/firmware/imx/Makefile | 1 +
> > > drivers/firmware/imx/imx-dsp.c | 142 +++++++++++++++++++++++++++++++
> > > include/linux/firmware/imx/dsp.h | 67 +++++++++++++++
> > > 4 files changed, 221 insertions(+)
> > > create mode 100644 drivers/firmware/imx/imx-dsp.c
> > > create mode 100644 include/linux/firmware/imx/dsp.h
> > >
> > > diff --git a/drivers/firmware/imx/Kconfig b/drivers/firmware/imx/Kconfig
> > > index 42b566f8903f..ddb241708c31 100644
> > > --- a/drivers/firmware/imx/Kconfig
> > > +++ b/drivers/firmware/imx/Kconfig
> > > @@ -1,4 +1,15 @@
> > > # SPDX-License-Identifier: GPL-2.0-only
> > > +config IMX_DSP
> > > + bool "IMX DSP Protocol driver"
> > > + depends on IMX_MBOX
> > > + help
> > > + This enables DSP IPC protocol between host CPU (Linux)
> > > + and the firmware running on DSP.
> > > + DSP exists on some i.MX8 processors (e.g i.MX8QM, i.MX8QXP).
> > > +
> > > + It acts like a doorbell. Client might use shared memory to
> > > + exchange information with DSP side.
> > > +
> > > config IMX_SCU
> > > bool "IMX SCU Protocol driver"
> > > depends on IMX_MBOX
> > > diff --git a/drivers/firmware/imx/Makefile b/drivers/firmware/imx/Makefile
> > > index 802c4ad8e8f9..08bc9ddfbdfb 100644
> > > --- a/drivers/firmware/imx/Makefile
> > > +++ b/drivers/firmware/imx/Makefile
> > > @@ -1,3 +1,4 @@
> > > # SPDX-License-Identifier: GPL-2.0
> > > +obj-$(CONFIG_IMX_DSP) += imx-dsp.o
> > > obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o
> > > obj-$(CONFIG_IMX_SCU_PD) += scu-pd.o
> > > diff --git a/drivers/firmware/imx/imx-dsp.c b/drivers/firmware/imx/imx-dsp.c
> > > new file mode 100644
> > > index 000000000000..c4d34a2fbff3
> > > --- /dev/null
> > > +++ b/drivers/firmware/imx/imx-dsp.c
> > > @@ -0,0 +1,142 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright 2019 NXP
> > > + * Author: Daniel Baluta <daniel.baluta@nxp.com>
> > > + *
> > > + * Implementation of the DSP IPC interface (host side)
> > > + */
> > > +
> > > +#include <linux/firmware/imx/dsp.h>
> > > +#include <linux/kernel.h>
> > > +#include <linux/mailbox_client.h>
> > > +#include <linux/module.h>
> > > +#include <linux/of_platform.h>
> > > +#include <linux/platform_device.h>
> > > +#include <linux/slab.h>
> > > +
> > > +/*
> > > + * imx_dsp_ring_doorbell - triggers an interrupt on the other side (DSP)
> > > + *
> > > + * @dsp: DSP IPC handle
> > > + * @chan_idx: index of the channel where to trigger the interrupt
> > > + *
> > > + * Returns non-negative value for success, negative value for error
> > > + */
> > > +int imx_dsp_ring_doorbell(struct imx_dsp_ipc *ipc, unsigned int idx)
> > > +{
> > > + int ret;
> > > + struct imx_dsp_chan *dsp_chan;
> > > +
> > > + if (idx >= DSP_MU_CHAN_NUM)
> > > + return -EINVAL;
> > > +
> > > + dsp_chan = &ipc->chans[idx];
> > > + ret = mbox_send_message(dsp_chan->ch, NULL);
> > > + if (ret < 0)
> > > + return ret;
> > > +
> > > + return 0;
> > > +}
> > > +EXPORT_SYMBOL(imx_dsp_ring_doorbell);
> > > +
> > > +/*
> > > + * imx_dsp_handle_rx - rx callback used by imx mailbox
> > > + *
> > > + * @c: mbox client
> > > + * @msg: message received
> > > + *
> > > + * Users of DSP IPC will need to privde handle_reply and handle_request
> > > + * callbacks.
> > > + */
> > > +static void imx_dsp_handle_rx(struct mbox_client *c, void *msg)
> > > +{
> > > + struct imx_dsp_chan *chan = container_of(c, struct imx_dsp_chan, cl);
> > > +
> > > + if (chan->idx == 0) {
> > > + chan->ipc->ops->handle_reply(chan->ipc);
> > > + } else {
> > > + chan->ipc->ops->handle_request(chan->ipc);
> > > + imx_dsp_ring_doorbell(chan->ipc, 1);
> > > + }
> > > +}
> > > +
> > > +static int imx_dsp_probe(struct platform_device *pdev)
> > > +{
> > > + struct device *dev = &pdev->dev;
> > > + struct imx_dsp_ipc *dsp_ipc;
> > > + struct imx_dsp_chan *dsp_chan;
> > > + struct mbox_client *cl;
> > > + char *chan_name;
> > > + int ret;
> > > + int i, j;
> > > +
> > > + dsp_ipc = devm_kzalloc(dev, sizeof(*dsp_ipc), GFP_KERNEL);
> > > + if (!dsp_ipc)
> > > + return -ENOMEM;
> > > +
> > > + for (i = 0; i < DSP_MU_CHAN_NUM; i++) {
> > > + if (i < 2)
> > > + chan_name = kasprintf(GFP_KERNEL, "txdb%d", i);
> > > + else
> > > + chan_name = kasprintf(GFP_KERNEL, "rxdb%d", i - 2);
> > > +
> > > + if (!chan_name)
> > > + return -ENOMEM;
> > > +
> > > + dsp_chan = &dsp_ipc->chans[i];
> > > + cl = &dsp_chan->cl;
> > > + cl->dev = dev;
> > > + cl->tx_block = false;
> > > + cl->knows_txdone = true;
> > > + cl->rx_callback = imx_dsp_handle_rx;
> > > +
> > > + dsp_chan->ipc = dsp_ipc;
> > > + dsp_chan->idx = i % 2;
> > > + dsp_chan->ch = mbox_request_channel_byname(cl, chan_name);
> > > + if (IS_ERR(dsp_chan->ch)) {
> > > + ret = PTR_ERR(dsp_chan->ch);
> > > + if (ret != -EPROBE_DEFER)
> > > + dev_err(dev, "Failed to request mbox chan %s ret %d\n",
> > > + chan_name, ret);
> > > + goto out;
> > > + }
> > > +
> > > + dev_dbg(dev, "request mbox chan %s\n", chan_name);
> > > + /* chan_name is not used anymore by framework */
> > > + kfree(chan_name);
> > > + }
> > > +
> > > + dsp_ipc->dev = dev;
> > > +
> > > + dev_set_drvdata(dev, dsp_ipc);
> > > +
> > > + dev_info(dev, "NXP i.MX DSP IPC initialized\n");
> > > +
> > > + return devm_of_platform_populate(dev);
> > > +out:
> > > + kfree(chan_name);
> > > + for (j = 0; j < i; j++) {
> > > + dsp_chan = &dsp_ipc->chans[j];
> > > + mbox_free_channel(dsp_chan->ch);
> > > + }
> > > +
> > > + return ret;
> > > +}
> > > +
> > > +static const struct of_device_id imx_dsp_match[] = {
> > > + { .compatible = "fsl,imx8qxp-dsp", },
> > > + { /* Sentinel */ }
> > > +};
> > > +
> > > +static struct platform_driver imx_dsp_driver = {
> > > + .driver = {
> > > + .name = "imx-dsp",
> > > + .of_match_table = imx_dsp_match,
> > > + },
> > > + .probe = imx_dsp_probe,
> > > +};
> > > +builtin_platform_driver(imx_dsp_driver);
> > > +
> > > +MODULE_AUTHOR("Daniel Baluta <daniel.baluta@nxp.com>");
> > > +MODULE_DESCRIPTION("IMX DSP IPC protocol driver");
> > > +MODULE_LICENSE("GPL v2");
> > > diff --git a/include/linux/firmware/imx/dsp.h b/include/linux/firmware/imx/dsp.h
> > > new file mode 100644
> > > index 000000000000..7562099c9e46
> > > --- /dev/null
> > > +++ b/include/linux/firmware/imx/dsp.h
> > > @@ -0,0 +1,67 @@
> > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > +/*
> > > + * Copyright 2019 NXP
> > > + *
> > > + * Header file for the DSP IPC implementation
> > > + */
> > > +
> > > +#ifndef _IMX_DSP_IPC_H
> > > +#define _IMX_DSP_IPC_H
> > > +
> > > +#include <linux/device.h>
> > > +#include <linux/types.h>
> > > +#include <linux/mailbox_client.h>
> > > +
> > > +#define DSP_MU_CHAN_NUM 4
> > > +
> > > +struct imx_dsp_chan {
> > > + struct imx_dsp_ipc *ipc;
> > > + struct mbox_client cl;
> > > + struct mbox_chan *ch;
> > > + char *name;
> > > + int idx;
> > > +};
> > > +
> > > +struct imx_dsp_ops {
> > > + void (*handle_reply)(struct imx_dsp_ipc *ipc);
> > > + void (*handle_request)(struct imx_dsp_ipc *ipc);
> > > +};
> > > +
> > > +struct imx_dsp_ipc {
> > > + /* Host <-> DSP communication uses 2 txdb and 2 rxdb channels */
> > > + struct imx_dsp_chan chans[DSP_MU_CHAN_NUM];
> > > + struct device *dev;
> > > + struct imx_dsp_ops *ops;
> > > + void *private_data;
> > > +};
> > > +
> > > +static inline void imx_dsp_set_data(struct imx_dsp_ipc *ipc, void *data)
> > > +{
> > > + if (!ipc)
> > > + return;
> > > +
> > > + ipc->private_data = data;
> > > +}
> > > +
> > > +static inline void *imx_dsp_get_data(struct imx_dsp_ipc *ipc)
> > > +{
> > > + if (!ipc)
> > > + return NULL;
> > > +
> > > + return ipc->private_data;
> > > +}
> > > +
> > > +#if IS_ENABLED(CONFIG_IMX_DSP)
> > > +
> > > +int imx_dsp_ring_doorbell(struct imx_dsp_ipc *dsp, unsigned int chan_idx);
> > > +
> > > +#else
> > > +
> > > +static inline int imx_dsp_ring_doorbell(struct imx_dsp_ipc *ipc,
> > > + unsigned int chan_idx)
> > > +{
> > > + return -ENOTSUPP;
> > > +}
> > > +
> > > +#endif
> > > +#endif /* _IMX_DSP_IPC_H */
> > > --
> > > 2.17.1
> > >
> >
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* Re: [PATCH 12/12] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC
From: gokulsri @ 2019-07-18 6:24 UTC (permalink / raw)
To: Stephen Boyd
Cc: agross, bjorn.andersson, david.brown, devicetree, jassisinghbrar,
linux-arm-msm, linux-clk, linux-kernel, linux-remoteproc,
mark.rutland, mturquette, ohad, robh+dt, sricharan
In-Reply-To: <20190717201326.DCEB520880@mail.kernel.org>
On 2019-07-18 01:43, Stephen Boyd wrote:
> Quoting Gokul Sriram Palanisamy (2019-07-11 08:41:08)
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> index 6a61a63..c24e3f6 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> @@ -10,6 +10,22 @@
>> model = "Qualcomm Technologies, Inc. IPQ8074";
>> compatible = "qcom,ipq8074";
>>
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + smem_region:smem@4ab00000 {
>
> Put a space between the colon and the node name. Also, just call it
> memory@4ab00000.
ok, will fix.
>
> smem_region: memory@4ab00000 {
>
>> + no-map;
>> + reg = <0x0 0x4ab00000 0x0 0x00100000>;
>> + };
>> +
>> + q6_region: q6@4b000000 {
>
> memory@
ok, will fix.
>
>> + no-map;
>> + reg = <0x0 0x4b000000 0x0 0x05f00000>;
>> + };
>> + };
>> +
>> firmware {
>> scm {
>> compatible = "qcom,scm-ipq8074", "qcom,scm";
>> @@ -431,6 +447,115 @@
>> "axi_m_sticky";
>> status = "disabled";
>> };
>> + apcs: syscon@b111000 {
>
> Add a newline between nodes please.
ok, will fix.
>
>> + compatible = "syscon";
>> + reg = <0x0B111000 0x1000>;
>> + };
>> +
>> + wcss: smp2p-wcss {
>
> This node should be outside the soc node because it doesn't have a reg
> property
ok, will fix.
>
>> + compatible = "qcom,smp2p";
>> + qcom,smem = <435>, <428>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <0 322 1>;
>> +
>> + qcom,ipc = <&apcs 8 9>;
>> +
>> + qcom,local-pid = <0>;
>> + qcom,remote-pid = <1>;
>> +
>> + wcss_smp2p_out: master-kernel {
>> + qcom,entry-name = "master-kernel";
>> + qcom,smp2p-feature-ssr-ack;
>> + #qcom,smem-state-cells = <1>;
>> + };
>> +
>> + wcss_smp2p_in: slave-kernel {
>> + qcom,entry-name = "slave-kernel";
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> + };
>> +
>> + tcsr_q6_block: syscon@1945000 {
>
> Do you really need _block in these aliases?
ok, will fix it to "tcsr_q6"
>
>> + compatible = "syscon";
>> + reg = <0x1945000 0xE000>;
>> + };
>> +
>> + tcsr_mutex_block: syscon@193d000 {
>> + compatible = "syscon";
>> + reg = <0x1905000 0x8000>;
>> + };
>> +
>> + tcsr_mutex: hwlock@193d000 {
>> + compatible = "qcom,tcsr-mutex";
>> + syscon = <&tcsr_mutex_block 0 0x80>;
>> + #hwlock-cells = <1>;
>> + };
>> +
>> + smem: qcom,smem@4AB00000 {
>
> lowercase please. And just 'smem' I guess.
ok, will fix.
>
>> + compatible = "qcom,smem";
>> + memory-region = <&smem_region>;
>> + hwlocks = <&tcsr_mutex 0>;
>> + };
>> +
>> + apcs_glb: mailbox@b111000 {
>> + compatible = "qcom,ipq8074-apcs-apps-global";
>> + reg = <0xb111000 0x1000>;
>
> These addresses should be padded out to 8 digits for the address part
> (not the size).
ok, will fix.
>
>> +
>> + #mbox-cells = <1>;
>> + };
>> +
>> + q6v5_wcss: q6v5_wcss@CD00000 {
>
> lowercase.
ok, will fix.
>
>> + compatible = "qcom,ipq8074-wcss-pil";
>> + reg = <0xCD00000 0x4040>,
>> + <0x4AB000 0x20>;
Regards,
Gokul
^ permalink raw reply
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