* Re: [PATCH 5/6] clk: imx8mq: Remove CLK_IS_CRITICAL flag for IMX8MQ_CLK_TMU_ROOT
From: Daniel Baluta @ 2019-07-26 22:26 UTC (permalink / raw)
To: Anson Huang
Cc: rui.zhang, edubezval, daniel.lezcano, Rob Herring, Mark Rutland,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Michael Turquette, Stephen Boyd, Lucas Stach, Abel Vesa,
Andrey Smirnov, Angus Ainslie (Purism), Carlo Caione,
Guido Günther, Leonard Crestez, linux-pm, Devicetree List
In-Reply-To: <20190705045612.27665-5-Anson.Huang@nxp.com>
Hi all,
latest linux-next hangs at boot.
commit fde50b96be821ac9673a7e00847cc4605bd88f34 (HEAD -> master, tag:
next-20190726, origin/master, origin/HEAD)
Author: Stephen Rothwell <sfr@canb.auug.org.au>
Date: Fri Jul 26 15:18:02 2019 +1000
Add linux-next specific files for 20190726
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
I know this is crazy but reverting commit:
commit 431bdd1df48ee2896ea9980d9153e3aeaf0c81ef (refs/bisect/bad)
Author: Anson Huang <Anson.Huang@nxp.com>
Date: Fri Jul 5 12:56:11 2019 +0800
clk: imx8mq: Remove CLK_IS_CRITICAL flag for IMX8MQ_CLK_TMU_ROOT
IMX8MQ_CLK_TMU_ROOT is ONLY used for thermal module, the driver
should manage this clock, so no need to have CLK_IS_CRITICAL flag
set.
makes the boot work again.
Any idea?
On Fri, Jul 5, 2019 at 8:07 AM <Anson.Huang@nxp.com> wrote:
>
> From: Anson Huang <Anson.Huang@nxp.com>
>
> IMX8MQ_CLK_TMU_ROOT is ONLY used for thermal module, the driver
> should manage this clock, so no need to have CLK_IS_CRITICAL flag
> set.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> drivers/clk/imx/clk-imx8mq.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
> index d407a07..91de69a 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -539,7 +539,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
> clks[IMX8MQ_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_dcss);
> clks[IMX8MQ_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_dcss);
> clks[IMX8MQ_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_dcss);
> - clks[IMX8MQ_CLK_TMU_ROOT] = imx_clk_gate4_flags("tmu_root_clk", "ipg_root", base + 0x4620, 0, CLK_IS_CRITICAL);
> + clks[IMX8MQ_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
> clks[IMX8MQ_CLK_VPU_DEC_ROOT] = imx_clk_gate2_flags("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
> clks[IMX8MQ_CLK_CSI1_ROOT] = imx_clk_gate4("csi1_root_clk", "csi1_core", base + 0x4650, 0);
> clks[IMX8MQ_CLK_CSI2_ROOT] = imx_clk_gate4("csi2_root_clk", "csi2_core", base + 0x4660, 0);
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH net-next 3/3] net: dsa: mt7530: Add support for port 5
From: David Miller @ 2019-07-26 21:04 UTC (permalink / raw)
To: opensource
Cc: netdev, frank-w, sean.wang, f.fainelli, linux, matthias.bgg,
andrew, vivien.didelot, john, linux-mediatek, linux-mips, robh+dt,
devicetree
In-Reply-To: <20190724192549.24615-4-opensource@vdorst.com>
From: René van Dorst <opensource@vdorst.com>
Date: Wed, 24 Jul 2019 21:25:49 +0200
> @@ -1167,6 +1236,10 @@ mt7530_setup(struct dsa_switch *ds)
> u32 id, val;
> struct device_node *dn;
> struct mt7530_dummy_poll p;
> + phy_interface_t interface;
> + struct device_node *mac_np;
> + struct device_node *phy_node;
> + const __be32 *_id;
Reverse christmas tree here please.
Thank you.
^ permalink raw reply
* Re: [PATCH net-next 1/3] net: ethernet: mediatek: Add basic PHYLINK support
From: David Miller @ 2019-07-26 21:02 UTC (permalink / raw)
To: opensource
Cc: netdev, frank-w, sean.wang, f.fainelli, linux, matthias.bgg,
andrew, vivien.didelot, john, linux-mediatek, linux-mips, robh+dt,
devicetree
In-Reply-To: <20190724192340.18978-1-opensource@vdorst.com>
From: René van Dorst <opensource@vdorst.com>
Date: Wed, 24 Jul 2019 21:23:40 +0200
> @@ -186,165 +187,219 @@ static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
> mtk_w32(eth, val, TRGMII_TCK_CTRL);
> }
>
> -static void mtk_phy_link_adjust(struct net_device *dev)
> +static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
> + const struct phylink_link_state *state)
> {
> - struct mtk_mac *mac = netdev_priv(dev);
> - u16 lcl_adv = 0, rmt_adv = 0;
> - u8 flowctrl;
> - u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
> - MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
> - MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
> - MAC_MCR_BACKPR_EN;
> + struct mtk_mac *mac = container_of(config, struct mtk_mac,
> + phylink_config);
> + struct mtk_eth *eth = mac->hw;
>
> - if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
> - return;
> + u32 ge_mode = 0, val, mcr_cur, mcr_new;
Please elminiate the empty line in the middle of the local variabel
declarations and adhere to reverse christmas tree ordering.
> @@ -1798,6 +1853,13 @@ static int mtk_open(struct net_device *dev)
> {
> struct mtk_mac *mac = netdev_priv(dev);
> struct mtk_eth *eth = mac->hw;
> + int err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
Reverse christmas tree please.
> @@ -2375,9 +2407,10 @@ static const struct net_device_ops mtk_netdev_ops = {
>
> static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
> {
> + struct phylink *phylink;
> struct mtk_mac *mac;
> const __be32 *_id = of_get_property(np, "reg", NULL);
> - int id, err;
> + int phy_mode, id, err;
While you are here please fix up the reverse christmas tree ordering, and
definitely don't make it worse :)
^ permalink raw reply
* [PATCH v3 2/2] iio: light: noa1305: Add support for NOA1305
From: Martyn Welch @ 2019-07-26 20:55 UTC (permalink / raw)
To: Mark Rutland, Jonathan Cameron
Cc: Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler,
linux-iio, linux-kernel, kernel, devicetree, Martyn Welch,
Sergei M
In-Reply-To: <20190726205513.31291-1-martyn.welch@collabora.com>
This driver adds the initial support for the ON Semiconductor
NOA1305 Ambient Light Sensor.
Originally written by Sergei Miroshnichenko. Found here:
https://github.com/EmcraftSystems/linux-upstream/commit/196d6cf897e632d2cb82d45484bd7a1bfdd5b6d9
Signed-off-by: Sergei M <fizik1@yandex.com>
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
---
Changes:
v2:
- Correcting authorship and SOB.
v3:
- Improve register define naming.
- Follow IIO convention of interleaving register bit definitions with
register defintions.
- Use proper endian swapping.
- Process raw sensor count into Lux.
- Avoid setting variables to zero when not needed.
- Check return value of i2c writes.
- Implement disabling of regulator as a devm action.
- Remove excessive white spacing.
drivers/iio/light/Kconfig | 10 ++
drivers/iio/light/Makefile | 1 +
drivers/iio/light/noa1305.c | 278 ++++++++++++++++++++++++++++++++++++
3 files changed, 289 insertions(+)
create mode 100644 drivers/iio/light/noa1305.c
diff --git a/drivers/iio/light/Kconfig b/drivers/iio/light/Kconfig
index 954c958cfc43..d1db0ec0d0f5 100644
--- a/drivers/iio/light/Kconfig
+++ b/drivers/iio/light/Kconfig
@@ -309,6 +309,16 @@ config MAX44009
To compile this driver as a module, choose M here:
the module will be called max44009.
+config NOA1305
+ tristate "ON Semiconductor NOA1305 ambient light sensor"
+ depends on I2C
+ help
+ Say Y here if you want to build support for the ON Semiconductor
+ NOA1305 ambient light sensor.
+
+ To compile this driver as a module, choose M here:
+ The module will be called noa1305.
+
config OPT3001
tristate "Texas Instruments OPT3001 Light Sensor"
depends on I2C
diff --git a/drivers/iio/light/Makefile b/drivers/iio/light/Makefile
index e40794fbb435..00d1f9b98f39 100644
--- a/drivers/iio/light/Makefile
+++ b/drivers/iio/light/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_LTR501) += ltr501.o
obj-$(CONFIG_LV0104CS) += lv0104cs.o
obj-$(CONFIG_MAX44000) += max44000.o
obj-$(CONFIG_MAX44009) += max44009.o
+obj-$(CONFIG_NOA1305) += noa1305.o
obj-$(CONFIG_OPT3001) += opt3001.o
obj-$(CONFIG_PA12203001) += pa12203001.o
obj-$(CONFIG_RPR0521) += rpr0521.o
diff --git a/drivers/iio/light/noa1305.c b/drivers/iio/light/noa1305.c
new file mode 100644
index 000000000000..02b0cf48c2be
--- /dev/null
+++ b/drivers/iio/light/noa1305.c
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Support for ON Semiconductor NOA1305 ambient light sensor
+ *
+ * Copyright (C) 2016 Emcraft Systems
+ * Copyright (C) 2019 Collabora Ltd.
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/iio/iio.h>
+#include <linux/iio/sysfs.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#define NOA1305_REG_POWER_CONTROL 0x0
+#define NOA1305_POWER_CONTROL_DOWN 0x00
+#define NOA1305_POWER_CONTROL_ON 0x08
+#define NOA1305_REG_RESET 0x1
+#define NOA1305_RESET_RESET 0x10
+#define NOA1305_REG_INTEGRATION_TIME 0x2
+#define NOA1305_INTEGR_TIME_800MS 0x00
+#define NOA1305_INTEGR_TIME_400MS 0x01
+#define NOA1305_INTEGR_TIME_200MS 0x02
+#define NOA1305_INTEGR_TIME_100MS 0x03
+#define NOA1305_INTEGR_TIME_50MS 0x04
+#define NOA1305_INTEGR_TIME_25MS 0x05
+#define NOA1305_INTEGR_TIME_12_5MS 0x06
+#define NOA1305_INTEGR_TIME_6_25MS 0x07
+#define NOA1305_REG_INT_SELECT 0x3
+#define NOA1305_INT_SEL_ACTIVE_HIGH 0x01
+#define NOA1305_INT_SEL_ACTIVE_LOW 0x02
+#define NOA1305_INT_SEL_INACTIVE 0x03
+#define NOA1305_REG_INT_THRESH_LSB 0x4
+#define NOA1305_REG_INT_THRESH_MSB 0x5
+#define NOA1305_REG_ALS_DATA_LSB 0x6
+#define NOA1305_REG_ALS_DATA_MSB 0x7
+#define NOA1305_REG_DEVICE_ID_LSB 0x8
+#define NOA1305_REG_DEVICE_ID_MSB 0x9
+
+#define NOA1305_DEVICE_ID 0x0519
+#define NOA1305_DRIVER_NAME "noa1305"
+
+struct noa1305_priv {
+ struct i2c_client *client;
+ struct regmap *regmap;
+ struct regulator *vin_reg;
+};
+
+static int noa1305_measure(struct noa1305_priv *priv)
+{
+ __le16 data;
+ int count;
+ int ret;
+
+ ret = regmap_bulk_read(priv->regmap, NOA1305_REG_ALS_DATA_LSB, &data,
+ 2);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * Lux = count / (<Integration Constant> * <Integration Time>)
+ *
+ * Integration Constant = 7.7
+ * Integration Time in Seconds (currently) = 800ms
+ */
+ return (le16_to_cpu(data) * 100) / (77 * 8);
+}
+
+static const struct iio_chan_spec noa1305_channels[] = {
+ {
+ .type = IIO_LIGHT,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
+ }
+};
+
+static int noa1305_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2, long mask)
+{
+ int ret = -EINVAL;
+ struct noa1305_priv *priv = iio_priv(indio_dev);
+
+ switch (mask) {
+ case IIO_CHAN_INFO_PROCESSED:
+ switch (chan->type) {
+ case IIO_LIGHT:
+ ret = noa1305_measure(priv);
+ if (ret < 0)
+ return ret;
+ *val = ret;
+ ret = IIO_VAL_INT;
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+static const struct iio_info noa1305_info = {
+ .read_raw = noa1305_read_raw,
+};
+
+static bool noa1305_writable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case NOA1305_REG_POWER_CONTROL:
+ case NOA1305_REG_RESET:
+ case NOA1305_REG_INTEGRATION_TIME:
+ case NOA1305_REG_INT_SELECT:
+ case NOA1305_REG_INT_THRESH_LSB:
+ case NOA1305_REG_INT_THRESH_MSB:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static const struct regmap_config noa1305_regmap_config = {
+ .name = NOA1305_DRIVER_NAME,
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = NOA1305_REG_DEVICE_ID_MSB,
+ .writeable_reg = noa1305_writable_reg,
+};
+
+static void noa1305_reg_remove(void *data)
+{
+ struct noa1305_priv *priv = data;
+
+ regulator_disable(priv->vin_reg);
+}
+
+static int noa1305_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct noa1305_priv *priv;
+ struct iio_dev *indio_dev;
+ struct regmap *regmap;
+ __le16 data;
+ unsigned int dev_id;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*priv));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ regmap = devm_regmap_init_i2c(client, &noa1305_regmap_config);
+ if (IS_ERR(regmap)) {
+ dev_err(&client->dev, "Regmap initialization failed.\n");
+ return PTR_ERR(regmap);
+ }
+
+ priv = iio_priv(indio_dev);
+
+ priv->vin_reg = devm_regulator_get(&client->dev, "vin");
+ if (IS_ERR(priv->vin_reg)) {
+ dev_err(&client->dev, "get regulator vin failed\n");
+ return PTR_ERR(priv->vin_reg);
+ }
+
+ ret = regulator_enable(priv->vin_reg);
+ if (ret) {
+ dev_err(&client->dev, "enable regulator vin failed\n");
+ return ret;
+ }
+
+ ret = devm_add_action_or_reset(&client->dev, noa1305_reg_remove, priv);
+ if (ret) {
+ dev_err(&client->dev, "addition of devm action failed\n");
+ return ret;
+ }
+
+ i2c_set_clientdata(client, indio_dev);
+ priv->client = client;
+ priv->regmap = regmap;
+
+ ret = regmap_bulk_read(regmap, NOA1305_REG_DEVICE_ID_LSB, &data, 2);
+ if (ret < 0) {
+ dev_err(&client->dev, "ID reading failed: %d\n", ret);
+ return ret;
+ }
+
+ dev_id = le16_to_cpu(data);
+ if (dev_id != NOA1305_DEVICE_ID) {
+ dev_err(&client->dev, "Unknown device ID: 0x%x\n", dev_id);
+ ret = -ENODEV;
+ return ret;
+ }
+
+ ret = regmap_write(regmap, NOA1305_REG_POWER_CONTROL,
+ NOA1305_POWER_CONTROL_ON);
+ if (ret < 0) {
+ dev_err(&client->dev, "Enabling power control failed\n");
+ return ret;
+ }
+
+ ret = regmap_write(regmap, NOA1305_REG_RESET, NOA1305_RESET_RESET);
+ if (ret < 0) {
+ dev_err(&client->dev, "Device reset failed\n");
+ return ret;
+ }
+
+ ret = regmap_write(regmap, NOA1305_REG_INTEGRATION_TIME,
+ NOA1305_INTEGR_TIME_800MS);
+ if (ret < 0) {
+ dev_err(&client->dev, "Setting integration time failed\n");
+ return ret;
+ }
+
+ ret = regmap_write(regmap, NOA1305_REG_INT_SELECT,
+ NOA1305_INT_SEL_INACTIVE);
+ if (ret < 0) {
+ dev_err(&client->dev, "Disabling interrupts failed\n");
+ return ret;
+ }
+
+ indio_dev->dev.parent = &client->dev;
+ indio_dev->info = &noa1305_info;
+ indio_dev->channels = noa1305_channels;
+ indio_dev->num_channels = ARRAY_SIZE(noa1305_channels);
+ indio_dev->name = NOA1305_DRIVER_NAME;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+
+ ret = devm_iio_device_register(&client->dev, indio_dev);
+ if (ret) {
+ dev_err(&client->dev, "registering device failed\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+static int noa1305_remove(struct i2c_client *client)
+{
+ struct iio_dev *indio_dev = i2c_get_clientdata(client);
+ struct noa1305_priv *priv = iio_priv(indio_dev);
+
+ regulator_disable(priv->vin_reg);
+
+ return 0;
+}
+
+static const struct of_device_id noa1305_of_match[] = {
+ { .compatible = "onnn,noa1305" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, noa1305_of_match);
+
+static const struct i2c_device_id noa1305_ids[] = {
+ { "noa1305", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, noa1305_id);
+
+static struct i2c_driver noa1305_driver = {
+ .driver = {
+ .name = NOA1305_DRIVER_NAME,
+ .of_match_table = noa1305_of_match,
+ },
+ .probe = noa1305_probe,
+ .remove = noa1305_remove,
+ .id_table = noa1305_ids,
+};
+
+module_i2c_driver(noa1305_driver);
+
+MODULE_AUTHOR("Sergei Miroshnichenko <sergeimir@emcraft.com>");
+MODULE_AUTHOR("Martyn Welch <martyn.welch@collabora.com");
+MODULE_DESCRIPTION("ON Semiconductor NOA1305 ambient light sensor");
+MODULE_LICENSE("GPL");
--
2.20.1
^ permalink raw reply related
* [PATCH v3 1/2] dt-bindings: Add binding document for NOA1305
From: Martyn Welch @ 2019-07-26 20:55 UTC (permalink / raw)
To: Mark Rutland, Jonathan Cameron
Cc: Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler,
linux-iio, linux-kernel, kernel, devicetree, Martyn Welch,
Rob Herring
Document the ON Semiconductor NOA1305 ambient light sensor devicetree
bindings.
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes:
v2: Same as v1.
v3: Same as v2.
.../bindings/iio/light/noa1305.yaml | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/light/noa1305.yaml
diff --git a/Documentation/devicetree/bindings/iio/light/noa1305.yaml b/Documentation/devicetree/bindings/iio/light/noa1305.yaml
new file mode 100644
index 000000000000..17e7f140b69b
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/light/noa1305.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/noa1305.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ON Semiconductor NOA1305 Ambient Light Sensor
+
+maintainers:
+ - Martyn Welch <martyn.welch@collabora.com>
+
+description: |
+ Ambient sensing with an i2c interface.
+
+ https://www.onsemi.com/pub/Collateral/NOA1305-D.PDF
+
+properties:
+ compatible:
+ enum:
+ - onnn,noa1305
+
+ reg:
+ maxItems: 1
+
+ vin-supply:
+ description: Regulator that provides power to the sensor
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ i2c {
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ light@39 {
+ compatible = "onnn,noa1305";
+ reg = <0x39>;
+ };
+ };
+...
--
2.20.1
^ permalink raw reply related
* Re: [PATCH 3/3] drm/bridge: Add NWL MIPI DSI host controller support
From: Fabio Estevam @ 2019-07-26 20:01 UTC (permalink / raw)
To: Guido Günther
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Jernej Skrabec, Pengutronix Kernel Team, Neil Armstrong,
David Airlie, Lee Jones, Jonas Karlman, linux-kernel,
DRI mailing list, Rob Herring, NXP Linux Team, Robert Chiras,
Chris Healy, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Laurent Pinchart
In-Reply-To: <3158f4f8c97c21f98c394e5631d74bc60d796522.1563983037.git.agx@sigxcpu.org>
Hi Guido,
Thanks for your work on this driver!
On Wed, Jul 24, 2019 at 12:52 PM Guido Günther <agx@sigxcpu.org> wrote:
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/imx-nwl/Kconfig
> @@ -0,0 +1,15 @@
> +config DRM_IMX_NWL_DSI
> + tristate "Support for Northwest Logic MIPI DSI Host controller"
> + depends on DRM && (ARCH_MXC || ARCH_MULTIPLATFORM || COMPILE_TEST)
This IP could potentially be found on other SoCs, so no need to make
it depend on ARCH_MXC.
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_print.h>
> +#include <drm/drm_probe_helper.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/gpio/consumer.h>
I did not find gpio AP used in this driver.
> +static void imx_nwl_dsi_set_clocks(struct imx_nwl_dsi *dsi, bool enable)
Better make it to return 'int' instead...
> +{
> + struct device *dev = dsi->dev;
> + const char *id;
> + struct clk *clk;
> + unsigned long new_rate, cur_rate;
> + bool enabled;
> + size_t i;
> + int ret;
> +
> + DRM_DEV_DEBUG_DRIVER(dev, "%sabling platform clocks",
Please remove the letter 's' from 'sabling'.
> + enable ? "en" : "dis");
> + ret = clk_prepare_enable(clk);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "Failed to enable clock %s",
> + id);
and propagate the error in case of clk_prepare_enable() failure.
> + }
> + dsi->clk_config[i].enabled = true;
> + cur_rate = clk_get_rate(clk);
> + DRM_DEV_DEBUG_DRIVER(
> + dev, "Enabled %s clk (rate: req=%lu act=%lu)\n",
> + id, new_rate, cur_rate);
> + } else if (enabled) {
> + clk_disable_unprepare(clk);
> + dsi->clk_config[i].enabled = false;
> + DRM_DEV_DEBUG_DRIVER(dev, "Disabled %s clk\n", id);
> + }
> + }
> +}
> +
> +static void imx_nwl_dsi_enable(struct imx_nwl_dsi *dsi)
Same here. Please return 'int' instead.
> +{
> + struct device *dev = dsi->dev;
> + int ret;
> +
> + imx_nwl_dsi_set_clocks(dsi, true);
> +
> + ret = dsi->pdata->poweron(dsi);
> + if (ret < 0)
> + DRM_DEV_ERROR(dev, "Failed to power on DSI (%d)\n", ret);
If the power domain failed to turn on, it is better to propagate the error.
> + phy_ref_rate = clk_get_rate(dsi->phy_ref_clk);
> + DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate);
> + if (ret < 0) {
This check looks wrong. At this point ret is always 0.
> + DRM_DEV_ERROR(dsi->dev,
> + "Cannot setup PHY for mode: %ux%u @%d Hz\n",
> + adjusted_mode->hdisplay, adjusted_mode->vdisplay,
> + adjusted_mode->clock);
> + DRM_DEV_ERROR(dsi->dev, "PHY ref clk: %lu, bit clk: %lu\n",
> + phy_ref_rate, new_cfg.mipi_dphy.hs_clk_rate);
> + } else {
> + /* Save the new desired phy config */
> + memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg));
> + }
> +
> + /* LCDIF + NWL needs active high sync */
Would this still work if DCSS is used instead?
> + adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
> + adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
> +
> + drm_display_mode_to_videomode(adjusted_mode, &dsi->vm);
> + drm_mode_debug_printmodeline(adjusted_mode);
> +
> + return ret == 0;
At this point ret is always 0.
> +static void imx_nwl_dsi_bridge_pre_enable(struct drm_bridge *bridge)
> +{
> + struct imx_nwl_dsi *dsi = bridge_to_dsi(bridge);
> +
> + if (dsi->dpms_mode == DRM_MODE_DPMS_ON)
> + return;
> +
> + imx_nwl_select_input_source(dsi);
This function is i.MX8M specific, so better protect it to run only for
the i.MX8M variant.
> + pm_runtime_get_sync(dsi->dev);
> + imx_nwl_dsi_enable(dsi);
> + nwl_dsi_enable(dsi);
Please check the error and propagate in the case of failure.
> + dsi->dpms_mode = DRM_MODE_DPMS_ON;
> +}
> +
> + dsi->csr = syscon_regmap_lookup_by_phandle(np, "csr");
> + if (IS_ERR(dsi->csr) && dsi->pdata->ext_regs & IMX_REG_CSR) {
> + ret = PTR_ERR(dsi->csr);
> + DRM_DEV_ERROR(dsi->dev, "Failed to get CSR regmap: %d\n",
In this function (and globally in the driver) there is a mix of
DRM_DEV_ERROR() and dev_err().
Can we just pick one of the two and use it consistently?
Not sure what is the norm in drm code, but IMHO dev_err() looks prettier :-)
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(dsi->dev, res);
Could use devm_platform_ioremap_resource(), which makes it simpler.
> +err_cleanup:
> + devm_free_irq(dev, dsi->irq, dsi);
No need to call devm_free_irq() here. The devm functions do not need
to be freed on probe.
> diff --git a/drivers/gpu/drm/bridge/imx-nwl/nwl-dsi.c b/drivers/gpu/drm/bridge/imx-nwl/nwl-dsi.c
> new file mode 100644
> index 000000000000..0e1463af162f
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/imx-nwl/nwl-dsi.c
> @@ -0,0 +1,745 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * NWL DSI host driver
> + *
> + * Copyright (C) 2017 NXP
> + * Copyright (C) 2019 Purism SPC
> + */
> +
> +#include <asm/unaligned.h>
Is this asm header required?
> +/*
> + * DSI Video mode
> + */
Single line comment would suffice.
> +#define VIDEO_MODE_BURST_MODE_WITH_SYNC_PULSES 0
> +#define VIDEO_MODE_NON_BURST_MODE_WITH_SYNC_EVENTS BIT(0)
> +#define VIDEO_MODE_BURST_MODE BIT(1)
> +
> +/*
> + * DPI color coding
> + */
Ditto.
> +#define DPI_16_BIT_565_PACKED 0
> +#define DPI_16_BIT_565_ALIGNED 1
> +#define DPI_16_BIT_565_SHIFTED 2
> +#define DPI_18_BIT_PACKED 3
> +#define DPI_18_BIT_ALIGNED 4
> +#define DPI_24_BIT 5
> +
> +/*
> + * DPI Pixel format
> + */
Ditto.
> +#define PIXEL_FORMAT_16 0
> +#define PIXEL_FORMAT_18 BIT(0)
> +#define PIXEL_FORMAT_18L BIT(1)
> +#define PIXEL_FORMAT_24 (BIT(0) | BIT(1))
> +
> +enum transfer_direction { DSI_PACKET_SEND, DSI_PACKET_RECEIVE };
> +
> +struct mipi_dsi_transfer {
> + const struct mipi_dsi_msg *msg;
> + struct mipi_dsi_packet packet;
> + struct completion completed;
> +
> + int status; /* status of transmission */
> + enum transfer_direction direction;
> + bool need_bta;
> + u8 cmd;
> + u16 rx_word_count;
> + size_t tx_len; /* bytes sent */
> + size_t rx_len; /* bytes received */
> +};
The comments here are kind of obvious, so I would just remove them.
> +static inline int nwl_dsi_write(struct imx_nwl_dsi *dsi, unsigned int reg,
inline can be dropped.
> + u32 val)
> +{
> + int ret;
> +
> + ret = regmap_write(dsi->regmap, reg, val);
> + if (ret < 0)
> + DRM_DEV_ERROR(dsi->dev,
> + "Failed to write NWL DSI reg 0x%x: %d\n", reg,
> + ret);
> + return ret;
> +}
> +
> +static inline u32 nwl_dsi_read(struct imx_nwl_dsi *dsi, u32 reg)
Same here.
> +{
> + unsigned int val;
> + int ret;
> +
> + ret = regmap_read(dsi->regmap, reg, &val);
> + if (ret < 0)
> + DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n",
> + reg, ret);
> +
> + return val;
> +}
It seems that we could simply use regmap_read/write() directly instead
of these functions.
> +int nwl_dsi_get_dphy_params(struct imx_nwl_dsi *dsi,
> + const struct drm_display_mode *mode,
> + union phy_configure_opts *phy_opts)
> +{
> + unsigned long rate;
> +
> + if (dsi->lanes < 1 || dsi->lanes > 4)
> + return -EINVAL;
> +
> + /*
> + * So far the DPHY spec minimal timings work for both mixel
> + * dphy and nwl dsi host
> + */
> + phy_mipi_dphy_get_default_config(
> + mode->crtc_clock * 1000,
> + mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes,
> + &phy_opts->mipi_dphy);
> + rate = clk_get_rate(dsi->tx_esc_clk);
> + DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate);
> + phy_opts->mipi_dphy.lp_clk_rate = rate;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(nwl_dsi_get_dphy_params);
Does it really need to be exported? Why can't it be placed inside
nwl-drv.c and be made static?
> +/**
/* is enough
> + * ui2bc - UI time periods to byte clock cycles
> + */
> +static u32 ui2bc(struct imx_nwl_dsi *dsi, unsigned long long ui)
> +{
> + int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
> +
> + return DIV_ROUND_UP(ui * dsi->lanes, dsi->vm.pixelclock * bpp);
> +}
> +
> +#define USEC_PER_SEC 1000000L
This definition already exists in include/linux/time64.h. No need to
redefine it.
> +static int nwl_dsi_enable_tx_clock(struct imx_nwl_dsi *dsi)
> +{
> + struct device *dev = dsi->dev;
> + int ret;
> +
> + ret = clk_prepare_enable(dsi->tx_esc_clk);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "Failed to enable tx_esc clk: %d\n", ret);
> + return ret;
> + }
> +
> + DRM_DEV_DEBUG_DRIVER(dev, "Enabled tx_esc clk @%lu Hz\n",
> + clk_get_rate(dsi->tx_esc_clk));
> + return 0;
> +}
Do we really need this function? It looks like it would be simpler
just to call clk_prepare_enable() directly.
> +
> +static int nwl_dsi_enable_rx_clock(struct imx_nwl_dsi *dsi)
> +{
> + struct device *dev = dsi->dev;
> + int ret;
> +
> + ret = clk_prepare_enable(dsi->rx_esc_clk);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "Failed to enable rx_esc clk: %d\n", ret);
> + return ret;
> + }
> +
> + DRM_DEV_DEBUG_DRIVER(dev, "Enabled rx_esc clk @%lu Hz\n",
> + clk_get_rate(dsi->rx_esc_clk));
> + return 0;
> +}
Same here.
> +static ssize_t nwl_dsi_host_transfer(struct mipi_dsi_host *dsi_host,
> + const struct mipi_dsi_msg *msg)
> +{
> + struct imx_nwl_dsi *dsi =
> + container_of(dsi_host, struct imx_nwl_dsi, dsi_host);
> + struct mipi_dsi_transfer xfer;
> + ssize_t ret = 0;
> +
> + /* Create packet to be sent */
> + dsi->xfer = &xfer;
> + ret = mipi_dsi_create_packet(&xfer.packet, msg);
> + if (ret < 0) {
> + dsi->xfer = NULL;
> + return ret;
> + }
> +
> + if ((msg->type & MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM ||
> + msg->type & MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM ||
> + msg->type & MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM ||
> + msg->type & MIPI_DSI_DCS_READ) &&
> + msg->rx_len > 0 && msg->rx_buf != NULL)
> + xfer.direction = DSI_PACKET_RECEIVE;
> + else
> + xfer.direction = DSI_PACKET_SEND;
> +
> + xfer.need_bta = (xfer.direction == DSI_PACKET_RECEIVE);
> + xfer.need_bta |= (msg->flags & MIPI_DSI_MSG_REQ_ACK) ? 1 : 0;
> + xfer.msg = msg;
> + xfer.status = -ETIMEDOUT;
> + xfer.rx_word_count = 0;
> + xfer.rx_len = 0;
> + xfer.cmd = 0x00;
> + if (msg->tx_len > 0)
> + xfer.cmd = ((u8 *)(msg->tx_buf))[0];
> + init_completion(&xfer.completed);
> +
> + nwl_dsi_enable_rx_clock(dsi);
This may fail, so better check the error.
ret = clk_prepare_enable()
if (ret < 0)
return ret;
> +irqreturn_t nwl_dsi_irq_handler(int irq, void *data)
> +{
> + u32 irq_status;
> + struct imx_nwl_dsi *dsi = data;
> +
> + irq_status = nwl_dsi_read(dsi, IRQ_STATUS);
> +
> + if (irq_status & TX_PKT_DONE || irq_status & RX_PKT_HDR_RCVD ||
> + irq_status & RX_PKT_PAYLOAD_DATA_RCVD)
> + nwl_dsi_finish_transmission(dsi, irq_status);
> +
> + return IRQ_HANDLED;
> +}
> +EXPORT_SYMBOL_GPL(nwl_dsi_irq_handler);
What about placing this function inside nwl-drv.c and make it static?
> +
> +int nwl_dsi_enable(struct imx_nwl_dsi *dsi)
> +{
> + struct device *dev = dsi->dev;
> + union phy_configure_opts *phy_cfg = &dsi->phy_cfg;
> + int ret;
> +
> + if (!dsi->lanes) {
> + DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes);
> + return -EINVAL;
> + }
> +
> + ret = phy_init(dsi->phy);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "Failed to init DSI phy: %d\n", ret);
> + return ret;
> + }
> +
> + ret = phy_configure(dsi->phy, phy_cfg);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", ret);
> + return ret;
> + }
> +
> + ret = nwl_dsi_enable_tx_clock(dsi);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "Failed to enable tx clock: %d\n", ret);
> + return ret;
> + }
> +
> + ret = nwl_dsi_config_host(dsi);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "Failed to set up DSI: %d", ret);
> + return ret;
> + }
> +
> + ret = nwl_dsi_config_dpi(dsi);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "Failed to set up DPI: %d", ret);
> + return ret;
> + }
> +
> + ret = phy_power_on(dsi->phy);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "Failed to power on DPHY (%d)\n", ret);
> + return ret;
> + }
> +
> + nwl_dsi_init_interrupts(dsi);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(nwl_dsi_enable);
Same here.
> +
> +int nwl_dsi_disable(struct imx_nwl_dsi *dsi)
> +{
> + struct device *dev = dsi->dev;
> +
> + DRM_DEV_DEBUG_DRIVER(dev, "Disabling clocks and phy\n");
> +
> + phy_power_off(dsi->phy);
> + phy_exit(dsi->phy);
> +
> + /* Disabling the clock before the phy breaks enabling dsi again */
> + clk_disable_unprepare(dsi->tx_esc_clk);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(nwl_dsi_disable);
Same here.
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH v5 2/7] dt-bindings: clock: qcom: Add QCOM Q6SSTOP clock controller bindings
From: Stephen Boyd @ 2019-07-26 19:43 UTC (permalink / raw)
To: Govind Singh, bjorn.andersson, linux-arm-msm, linux-clk,
linux-remoteproc
Cc: andy.gross, linux-soc, devicetree
In-Reply-To: <20190726092332.25202-3-govinds@codeaurora.org>
Quoting Govind Singh (2019-07-26 02:23:27)
> Add devicetree binding for the Q6SSTOP clock controller found in QCS404.
>
> Signed-off-by: Govind Singh <govinds@codeaurora.org>
If this patch goes again, please convert to YAML.
> ---
> .../bindings/clock/qcom,q6sstopcc.txt | 26 +++++++++++++++++++
> 1 file changed, 26 insertions(+)
> create mode 100755 Documentation/devicetree/bindings/clock/qcom,q6sstopcc.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.txt b/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.txt
> new file mode 100755
> index 000000000000..157bb52f9dc4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.txt
> @@ -0,0 +1,26 @@
> +Qualcomm Q6SSTOP Clock Controller Binding
> +-----------------------------------------------
> +
> +Required properties :
> +- compatible : shall contain "qcom,qcs404-q6sstopcc"
> +- #clock-cells : from common clock binding, shall contain 1
> +- reg : shall contain base register address and size,
> + in the order
> + Index 0 maps to Q6SSTOP clocks register region
> + Index 1 maps to Q6SSTOP_TCSR register region
> +
> +Optional properties :
> +- reg-names : register names of WCSS domain
> + "q6sstop_cc", "q6sstop_tcsr".
> +
> +Example:
> +The below node has to be defined in the cases where the WCSS peripheral loader
> +would bring the subsystem out of reset.
> +
> + q6sstopcc: clock-controller@7500000 {
> + compatible = "qcom,qcs404-q6sstopcc";
> + reg = <0x7500000 0x4e000>, <0x7550000 0x10000>;
> + reg-names = "q6sstop_cc", "q6sstop_tcsr";
> + clocks = <&gcc GCC_WCSS_Q6_AHB_CLK>;
This isn't described in the binding. Are there clocks that go here?
Please add them to the binding.
^ permalink raw reply
* Re: [PATCH v3 1/6] dt-bindings: opp: Introduce opp-peak-KBps and opp-avg-KBps bindings
From: Saravana Kannan @ 2019-07-26 19:08 UTC (permalink / raw)
To: Georgi Djakov
Cc: Rob Herring, Mark Rutland, Viresh Kumar, Nishanth Menon,
Stephen Boyd, Rafael J. Wysocki, Vincent Guittot, Sweeney, Sean,
David Dai, Rajendra Nayak, Sibi Sankar, Bjorn Andersson,
Evan Green, Android Kernel Team, Linux PM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML
In-Reply-To: <2befbd75-e0f4-dbcc-e9b1-9a9f99c084d3@linaro.org>
On Fri, Jul 26, 2019 at 9:24 AM Georgi Djakov <georgi.djakov@linaro.org> wrote:
>
> Hi Saravana,
>
> On 7/3/19 04:10, Saravana Kannan wrote:
> > Interconnects often quantify their performance points in terms of
> > bandwidth. So, add opp-peak-KBps (required) and opp-avg-KBps (optional) to
> > allow specifying Bandwidth OPP tables in DT.
> >
> > opp-peak-KBps is a required property that replace opp-hz for Bandwidth OPP
> > tables.
> >
> > opp-avg-KBps is an optional property that can be used in Bandwidth OPP
> > tables.
> >
> > Signed-off-by: Saravana Kannan <saravanak@google.com>
> > ---
> > Documentation/devicetree/bindings/opp/opp.txt | 15 ++++++++++++---
> > 1 file changed, 12 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt
> > index 76b6c79604a5..c869e87caa2a 100644
> > --- a/Documentation/devicetree/bindings/opp/opp.txt
> > +++ b/Documentation/devicetree/bindings/opp/opp.txt
> > @@ -83,9 +83,14 @@ properties.
> >
> > Required properties:
> > - opp-hz: Frequency in Hz, expressed as a 64-bit big-endian integer. This is a
> > - required property for all device nodes but devices like power domains. The
> > - power domain nodes must have another (implementation dependent) property which
> > - uniquely identifies the OPP nodes.
> > + required property for all device nodes but for devices like power domains or
> > + bandwidth opp tables. The power domain nodes must have another (implementation
> > + dependent) property which uniquely identifies the OPP nodes. The interconnect
> > + opps are required to have the opp-peak-bw property.
> > +
> > +- opp-peak-KBps: Peak bandwidth in kilobytes per second, expressed as a 32-bit
>
> As Rob already mentioned, KBps should be documented. See [1].
>
Will do. Thanks for the pointer.
-Saravana
^ permalink raw reply
* Re: [PATCH v3 6/6] interconnect: Add OPP table support for interconnects
From: Saravana Kannan @ 2019-07-26 19:08 UTC (permalink / raw)
To: Georgi Djakov
Cc: Rob Herring, Mark Rutland, Viresh Kumar, Nishanth Menon,
Stephen Boyd, Rafael J. Wysocki, Vincent Guittot, Sweeney, Sean,
David Dai, Rajendra Nayak, Sibi Sankar, Bjorn Andersson,
Evan Green, Android Kernel Team, Linux PM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML
In-Reply-To: <fde02417-dc72-acad-727d-452a3ae3cbd0@linaro.org>
On Fri, Jul 26, 2019 at 9:25 AM Georgi Djakov <georgi.djakov@linaro.org> wrote:
>
> Hi Saravana,
>
> On 7/3/19 04:10, Saravana Kannan wrote:
> > Interconnect paths can have different performance points. Now that OPP
> > framework supports bandwidth OPP tables, add OPP table support for
> > interconnects.
> >
> > Devices can use the interconnect-opp-table DT property to specify OPP
> > tables for interconnect paths. And the driver can obtain the OPP table for
> > an interconnect path by calling icc_get_opp_table().
> >
> > Signed-off-by: Saravana Kannan <saravanak@google.com>
> > ---
> > drivers/interconnect/core.c | 27 ++++++++++++++++++++++++++-
> > include/linux/interconnect.h | 7 +++++++
> > 2 files changed, 33 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c
> > index 871eb4bc4efc..881bac80bc1e 100644
> > --- a/drivers/interconnect/core.c
> > +++ b/drivers/interconnect/core.c
> > @@ -47,6 +47,7 @@ struct icc_req {
> > */
> > struct icc_path {
> > size_t num_nodes;
> > + struct opp_table *opp_table;
>
> I am a bit worried that these tables might be abused and size of the DT will
> grow with many OPP tables of all existing paths.
A ton of stuff can be abused in downstream code. We can't do anything
about that.
We just need to keep an eye on OPP table abuse in upstream (whether it
frequency or bw OPP).
> > struct icc_req reqs[];
> > };
> >
> > @@ -313,7 +314,7 @@ struct icc_path *of_icc_get(struct device *dev, const char *name)
> > {
> > struct icc_path *path = ERR_PTR(-EPROBE_DEFER);
> > struct icc_node *src_node, *dst_node;
> > - struct device_node *np = NULL;
> > + struct device_node *np = NULL, *opp_node;
> > struct of_phandle_args src_args, dst_args;
> > int idx = 0;
> > int ret;
> > @@ -381,10 +382,34 @@ struct icc_path *of_icc_get(struct device *dev, const char *name)
> > dev_err(dev, "%s: invalid path=%ld\n", __func__, PTR_ERR(path));
> > mutex_unlock(&icc_lock);
> >
> > + opp_node = of_parse_phandle(np, "interconnect-opp-table", idx);
>
> Can't we figure out if the device OPP table contains bandwidth even without this
> property?
>
Rob pointed out that the property isn't necessary because the device
binding should document which OPP table is used for what. That takes
care of my main concern of how do we know which OPP table is for what
path. So I'm dropping this patch.
-Saravana
^ permalink raw reply
* Re: [PATCH 07/11] mtd: rawnand: Drop obsolete JZ4740 NAND driver
From: Miquel Raynal @ 2019-07-26 18:57 UTC (permalink / raw)
To: Paul Cercueil
Cc: Ralf Baechle, Paul Burton, James Hogan, Rob Herring, Mark Rutland,
Vinod Koul, Jean Delvare, Guenter Roeck, Lee Jones,
Richard Weinberger, Sebastian Reichel, Bartlomiej Zolnierkiewicz,
Liam Girdwood, Mark Brown, od, devicetree, linux-mips,
linux-kernel, dmaengine, linux-hwmon, linux-mtd, linux-pm,
dri-devel
In-Reply-To: <20190725220215.460-8-paul@crapouillou.net>
Hi Paul,
Paul Cercueil <paul@crapouillou.net> wrote on Thu, 25 Jul 2019 18:02:11
-0400:
> It has been replaced with the newer Ingenic NAND driver.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> Tested-by: Artur Rojek <contact@artur-rojek.eu>
> ---
Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
Thanks,
Miquèl
^ permalink raw reply
* Re: [PATCH 00/11] JZ4740 SoC cleanup
From: Sam Ravnborg @ 2019-07-26 18:46 UTC (permalink / raw)
To: Paul Cercueil
Cc: Ralf Baechle, Paul Burton, James Hogan, Rob Herring, Mark Rutland,
Vinod Koul, Jean Delvare, Guenter Roeck, Lee Jones, Miquel Raynal,
Richard Weinberger, Sebastian Reichel, Bartlomiej Zolnierkiewicz,
Liam Girdwood, Mark Brown, linux-hwmon, devicetree, linux-fbdev,
alsa-devel, linux-pm, linux-mips, dri-devel
In-Reply-To: <20190725220215.460-1-paul@crapouillou.net>
Hi Paul.
On Thu, Jul 25, 2019 at 06:02:04PM -0400, Paul Cercueil wrote:
> Hi,
>
> This patchset converts the Qi LB60 MIPS board to devicetree and makes it
> use all the shiny new drivers that have been developed or updated
> recently.
>
> All the crappy old drivers and custom code can be dropped since they
> have been replaced by better alternatives.
The overall diffstat is missing.
Just for curiosity it would be nice to see what was dropped with this
patch.
Sam
^ permalink raw reply
* Re: [PATCH 05/11] video/fbdev: Drop JZ4740 driver
From: Sam Ravnborg @ 2019-07-26 18:45 UTC (permalink / raw)
To: Paul Cercueil
Cc: Mark Rutland, linux-fbdev, James Hogan, alsa-devel, dri-devel,
Liam Girdwood, od, linux-mtd, Miquel Raynal, Lee Jones,
Artur Rojek, Richard Weinberger, linux-pm, Paul Burton,
Guenter Roeck, devicetree, Jean Delvare,
Bartlomiej Zolnierkiewicz, Mark Brown, linux-hwmon, linux-mips,
Ralf Baechle, linux-kernel, Vinod Koul, Rob Herring,
Sebastian Reichel, dmaengine
In-Reply-To: <20190725220215.460-6-paul@crapouillou.net>
Hi Paul.
On Thu, Jul 25, 2019 at 06:02:09PM -0400, Paul Cercueil wrote:
> The JZ4740 fbdev driver has been replaced with the ingenic-drm driver.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> Tested-by: Artur Rojek <contact@artur-rojek.eu>
> ---
> drivers/video/fbdev/Kconfig | 9 -
> drivers/video/fbdev/Makefile | 1 -
> drivers/video/fbdev/jz4740_fb.c | 690 --------------------------------
> 3 files changed, 700 deletions(-)
> delete mode 100644 drivers/video/fbdev/jz4740_fb.c
Nice work of you and others involved.
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Sam
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* [PATCH 6/6] arm64: dts: allwinner: h6: Add PWM node
From: Jernej Skrabec @ 2019-07-26 18:40 UTC (permalink / raw)
To: thierry.reding, mripard, wens
Cc: robh+dt, mark.rutland, linux-pwm, devicetree, linux-arm-kernel,
linux-kernel, linux-sunxi
In-Reply-To: <20190726184045.14669-1-jernej.skrabec@siol.net>
Allwinner H6 PWM is similar to that in A20 except that it has additional
bus clock and reset line.
Note that first PWM channel is connected to output pin and second
channel is used internally, as a clock source to AC200 co-packaged chip.
This means that any combination of these two channels can be used and
thus it doesn't make sense to add pinctrl nodes at this point.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index e8bed58e7246..c1abd805cfdc 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -229,6 +229,16 @@
status = "disabled";
};
+ pwm: pwm@300a000 {
+ compatible = "allwinner,sun50i-h6-pwm";
+ reg = <0x0300a000 0x400>;
+ clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
+ clock-names = "pwm", "bus";
+ resets = <&ccu RST_BUS_PWM>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
pio: pinctrl@300b000 {
compatible = "allwinner,sun50i-h6-pinctrl";
reg = <0x0300b000 0x400>;
--
2.22.0
^ permalink raw reply related
* [PATCH 5/6] pwm: sun4i: Add support to output source clock directly
From: Jernej Skrabec @ 2019-07-26 18:40 UTC (permalink / raw)
To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
mripard-DgEjT+Ai2ygdnm+yROfE0A, wens-jdAy2FN1RRM
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-pwm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20190726184045.14669-1-jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
PWM core has an option to bypass whole logic and output unchanged source
clock as PWM output. This is achieved by enabling bypass bit.
Note that when bypass is enabled, no other setting has any meaning, not
even enable bit.
This mode of operation is needed to achieve high enough frequency to
serve as clock source for AC200 chip, which is integrated into same
package as H6 SoC.
Signed-off-by: Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
---
drivers/pwm/pwm-sun4i.c | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 9e0eca79ff88..848cff26f385 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -120,6 +120,19 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
+ /*
+ * PWM chapter in H6 manual has a diagram which explains that if bypass
+ * bit is set, no other setting has any meaning. Even more, experiment
+ * proved that also enable bit is ignored in this case.
+ */
+ if (val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) {
+ state->period = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, clk_rate);
+ state->duty_cycle = state->period / 2;
+ state->polarity = PWM_POLARITY_NORMAL;
+ state->enabled = true;
+ return;
+ }
+
if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
sun4i_pwm->data->has_prescaler_bypass)
prescaler = 1;
@@ -211,7 +224,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
{
struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
struct pwm_state cstate;
- u32 ctrl;
+ u32 ctrl, clk_rate;
+ bool bypass;
int ret;
unsigned int delay_us;
unsigned long now;
@@ -226,6 +240,16 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
}
}
+ /*
+ * Although it would make much more sense to check for bypass in
+ * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled".
+ * Period is allowed to be rounded up or down.
+ */
+ clk_rate = clk_get_rate(sun4i_pwm->clk);
+ bypass = (state->period == NSEC_PER_SEC / clk_rate ||
+ state->period == DIV_ROUND_UP(NSEC_PER_SEC, clk_rate)) &&
+ state->enabled;
+
spin_lock(&sun4i_pwm->ctrl_lock);
ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
@@ -273,6 +297,11 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
}
+ if (bypass)
+ ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
+ else
+ ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
+
sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
spin_unlock(&sun4i_pwm->ctrl_lock);
--
2.22.0
^ permalink raw reply related
* [PATCH 4/6] pwm: sun4i: Add support for H6 PWM
From: Jernej Skrabec @ 2019-07-26 18:40 UTC (permalink / raw)
To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
mripard-DgEjT+Ai2ygdnm+yROfE0A, wens-jdAy2FN1RRM
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-pwm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20190726184045.14669-1-jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
Now that sun4i PWM driver supports deasserting reset line and enabling
bus clock, support for H6 PWM can be added.
Note that while H6 PWM has two channels, only first one is wired to
output pin. Second channel is used as a clock source to companion AC200
chip which is bundled into same package.
Signed-off-by: Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
---
drivers/pwm/pwm-sun4i.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 7d3ac3f2dc3f..9e0eca79ff88 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -331,6 +331,13 @@ static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
.npwm = 1,
};
+static const struct sun4i_pwm_data sun50i_pwm_dual_bypass_clk_rst = {
+ .has_bus_clock = true,
+ .has_prescaler_bypass = true,
+ .has_reset = true,
+ .npwm = 2,
+};
+
static const struct of_device_id sun4i_pwm_dt_ids[] = {
{
.compatible = "allwinner,sun4i-a10-pwm",
@@ -347,6 +354,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = {
}, {
.compatible = "allwinner,sun8i-h3-pwm",
.data = &sun4i_pwm_single_bypass,
+ }, {
+ .compatible = "allwinner,sun50i-h6-pwm",
+ .data = &sun50i_pwm_dual_bypass_clk_rst,
}, {
/* sentinel */
},
--
2.22.0
^ permalink raw reply related
* [PATCH 3/6] pwm: sun4i: Add a quirk for bus clock
From: Jernej Skrabec @ 2019-07-26 18:40 UTC (permalink / raw)
To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
mripard-DgEjT+Ai2ygdnm+yROfE0A, wens-jdAy2FN1RRM
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-pwm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20190726184045.14669-1-jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
H6 PWM core needs bus clock to be enabled in order to work.
Add a quirk for it.
Signed-off-by: Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
---
drivers/pwm/pwm-sun4i.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 1b7be8fbde86..7d3ac3f2dc3f 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -72,6 +72,7 @@ static const u32 prescaler_table[] = {
};
struct sun4i_pwm_data {
+ bool has_bus_clock;
bool has_prescaler_bypass;
bool has_reset;
unsigned int npwm;
@@ -79,6 +80,7 @@ struct sun4i_pwm_data {
struct sun4i_pwm_chip {
struct pwm_chip chip;
+ struct clk *bus_clk;
struct clk *clk;
struct reset_control *rst;
void __iomem *base;
@@ -382,6 +384,16 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
reset_control_deassert(pwm->rst);
}
+ if (pwm->data->has_bus_clock) {
+ pwm->bus_clk = devm_clk_get(&pdev->dev, "bus");
+ if (IS_ERR(pwm->bus_clk)) {
+ ret = PTR_ERR(pwm->bus_clk);
+ goto err_bus;
+ }
+
+ clk_prepare_enable(pwm->bus_clk);
+ }
+
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &sun4i_pwm_ops;
pwm->chip.base = -1;
@@ -402,6 +414,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
return 0;
err_pwm_add:
+ clk_disable_unprepare(pwm->bus_clk);
+err_bus:
reset_control_assert(pwm->rst);
return ret;
@@ -416,6 +430,7 @@ static int sun4i_pwm_remove(struct platform_device *pdev)
if (ret)
return ret;
+ clk_disable_unprepare(pwm->bus_clk);
reset_control_assert(pwm->rst);
return 0;
--
2.22.0
^ permalink raw reply related
* [PATCH 2/6] pwm: sun4i: Add a quirk for reset line
From: Jernej Skrabec @ 2019-07-26 18:40 UTC (permalink / raw)
To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
mripard-DgEjT+Ai2ygdnm+yROfE0A, wens-jdAy2FN1RRM
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-pwm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20190726184045.14669-1-jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
H6 PWM core needs deasserted reset line in order to work.
Add a quirk for it.
Signed-off-by: Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
---
drivers/pwm/pwm-sun4i.c | 27 +++++++++++++++++++++++++--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index de78c824bbfd..1b7be8fbde86 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -16,6 +16,7 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
+#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/time.h>
@@ -72,12 +73,14 @@ static const u32 prescaler_table[] = {
struct sun4i_pwm_data {
bool has_prescaler_bypass;
+ bool has_reset;
unsigned int npwm;
};
struct sun4i_pwm_chip {
struct pwm_chip chip;
struct clk *clk;
+ struct reset_control *rst;
void __iomem *base;
spinlock_t ctrl_lock;
const struct sun4i_pwm_data *data;
@@ -371,6 +374,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
if (IS_ERR(pwm->clk))
return PTR_ERR(pwm->clk);
+ if (pwm->data->has_reset) {
+ pwm->rst = devm_reset_control_get(&pdev->dev, NULL);
+ if (IS_ERR(pwm->rst))
+ return PTR_ERR(pwm->rst);
+
+ reset_control_deassert(pwm->rst);
+ }
+
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &sun4i_pwm_ops;
pwm->chip.base = -1;
@@ -383,19 +394,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
ret = pwmchip_add(&pwm->chip);
if (ret < 0) {
dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
- return ret;
+ goto err_pwm_add;
}
platform_set_drvdata(pdev, pwm);
return 0;
+
+err_pwm_add:
+ reset_control_assert(pwm->rst);
+
+ return ret;
}
static int sun4i_pwm_remove(struct platform_device *pdev)
{
struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
+ int ret;
+
+ ret = pwmchip_remove(&pwm->chip);
+ if (ret)
+ return ret;
- return pwmchip_remove(&pwm->chip);
+ reset_control_assert(pwm->rst);
+
+ return 0;
}
static struct platform_driver sun4i_pwm_driver = {
--
2.22.0
^ permalink raw reply related
* [PATCH 1/6] dt-bindings: pwm: allwinner: Add H6 PWM description
From: Jernej Skrabec @ 2019-07-26 18:40 UTC (permalink / raw)
To: thierry.reding, mripard, wens
Cc: robh+dt, mark.rutland, linux-pwm, devicetree, linux-arm-kernel,
linux-kernel, linux-sunxi
In-Reply-To: <20190726184045.14669-1-jernej.skrabec@siol.net>
H6 PWM block is basically the same as A20 PWM, except that it also has
bus clock and reset line which needs to be handled accordingly.
Expand Allwinner PWM binding with H6 PWM specifics.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
.../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 36 ++++++++++++++++++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
index 0ac52f83a58c..deca5d81802f 100644
--- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
@@ -30,13 +30,47 @@ properties:
- items:
- const: allwinner,sun50i-h5-pwm
- const: allwinner,sun5i-a13-pwm
+ - const: allwinner,sun50i-h6-pwm
reg:
maxItems: 1
- clocks:
+ # Even though it only applies to subschemas under the conditionals,
+ # not listing them here will trigger a warning because of the
+ # additionalsProperties set to false.
+ clocks: true
+ clock-names: true
+ resets:
maxItems: 1
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: allwinner,sun50i-h6-pwm
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Module Clock
+ - description: Bus Clock
+
+ clock-names:
+ items:
+ - const: pwm
+ - const: bus
+
+ required:
+ - clock-names
+ - resets
+
+ else:
+ properties:
+ clocks:
+ maxItems: 1
+
required:
- "#pwm-cells"
- compatible
--
2.22.0
^ permalink raw reply related
* [PATCH 0/6] pwm: sun4i: Add support for Allwinner H6
From: Jernej Skrabec @ 2019-07-26 18:40 UTC (permalink / raw)
To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
mripard-DgEjT+Ai2ygdnm+yROfE0A, wens-jdAy2FN1RRM
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-pwm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
Allwinner H6 SoC has PWM core which is basically the same as that found
in A20, it's just depends on additional bus clock and reset line.
This series adds support for it and extends PWM driver functionality in
a way that it's now possible to bypass whole core and output PWM source
clock directly as a PWM signal. This functionality is needed by AC200
chip, which is bundled in same physical package as H6 SoC, to serve as a
clock source of 24 MHz. AC200 clock input pin is bonded internally to
the second PWM channel.
I would be grateful if anyone can test this patch series for any kind of
regression on other SoCs.
Please take a look.
Best regards,
Jernej
Jernej Skrabec (6):
dt-bindings: pwm: allwinner: Add H6 PWM description
pwm: sun4i: Add a quirk for reset line
pwm: sun4i: Add a quirk for bus clock
pwm: sun4i: Add support for H6 PWM
pwm: sun4i: Add support to output source clock directly
arm64: dts: allwinner: h6: Add PWM node
.../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 36 +++++++-
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 +++
drivers/pwm/pwm-sun4i.c | 83 ++++++++++++++++++-
3 files changed, 125 insertions(+), 4 deletions(-)
--
2.22.0
^ permalink raw reply
* How to add multiple example with conflicting includes
From: Corentin Labbe @ 2019-07-26 18:11 UTC (permalink / raw)
To: robh+dt, mark.rutland, devicetree, linux-kernel
Hello
When I try to check the following examples of a devicetree schema:
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
crypto: crypto@1c15000 {
compatible = "allwinner,sun8i-h3-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
clock-names = "ahb", "mod";
resets = <&ccu RST_BUS_CE>;
reset-names = "ahb";
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun50i-h6-ccu.h>
#include <dt-bindings/reset/sun50i-h6-ccu.h>
crypto: crypto@1904000 {
compatible = "allwinner,sun50i-h6-crypto";
reg = <0x01904000 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>;
clock-names = "ahb", "mod", "mbus";
resets = <&ccu RST_BUS_CE>;
reset-names = "ahb";
};
I get:
In file included from Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.example.dts:42:
/linux-next/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-h6-ccu.h:9: warning: "CLK_PLL_PERIPH0" redefined
#define CLK_PLL_PERIPH0 3
[...]
So how can I add multiple examples which need somes conflicting #include to be validated.
Thanks
Regards
^ permalink raw reply
* Re: [PATCH v2 2/2] ARM: dts: imx6ul-kontron-n6310: Add Kontron i.MX6UL N6310 SoM and boards
From: Fabio Estevam @ 2019-07-26 17:54 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Sascha Hauer, linux-kernel, Schrempf Frieder, Rob Herring,
NXP Linux Team, Pengutronix Kernel Team, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20190726061705.14764-2-krzk@kernel.org>
Hi Krzysztof,
On Fri, Jul 26, 2019 at 3:17 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index 7294ac36f4c0..afb61a55e26f 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -161,6 +161,10 @@ properties:
> items:
> - enum:
> - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
> + - kontron,n6310-som # Kontron N6310 SOM
> + - kontron,n6310-s # Kontron N6310 S Board
> + - kontron,n6310-s-43 # Kontron N6310 S 43 Board
> + - kontron,n6310-s-50 # Kontron N6310 S 50 Board
These entries should be:
imx6ul-kontron-n6310-s.dtb
imx6ul-kontron-n6310-s-43.dtb
imx6ul-kontron-n6310-s-50.dtb
> + panel {
> + compatible = "admatec,t043c004800272t2a";
I do not find this binding documented.
> +&i2c4 {
> + gt911@5d {
Node names should be generic according to the devicetree spec, so:
touchscreen@5d
> + compatible = "goodix,gt928";
> + reg = <0x5d>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_cap_touch>;
> + interrupt-parent = <&gpio5>;
> + interrupts = <6 8>;
It would be better to use a laber to indicate the irq type:
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
> + reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
> + irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
Active high?
Above you use "interrupts = <6 8>;" which means IRQ_TYPE_LEVEL_LOW.
> + };
> +};
> +
> +&iomuxc {
We tend to prefer putting iomuxc as the last node.
> + pinctrl_lcdif_dat: lcdifdatgrp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
> + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
> + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
> + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
> + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
> + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
> + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
> + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
> + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
> + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
> + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
> + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
> + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
> + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
> + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
> + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
> + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
> + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
> + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
> + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
> + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
> + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
> + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
> + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
> + >;
> + };
> +
> + pinctrl_lcdif_ctrl: lcdifctrlgrp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
> + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
> + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
> + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
> + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79
> + >;
> + };
> +
> + pinctrl_cap_touch: captouchgrp {
> + fsl,pins = <
> + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */
> + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */
> + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */
> + >;
> + };
> +
> + pinctrl_pwm7: pwm7grp {
> + fsl,pins = <
> + MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0
> + >;
> + };
> +};
> +
> +&lcdif {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lcdif_dat
> + &pinctrl_lcdif_ctrl>;
Could fit into a single line.
> + panel {
> + compatible = "admatec,t070p133t0s301";
Same here. Undocumented binding.
> + backlight = <&backlight>;
> +
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <&display_out>;
> + };
> + };
> + };
> +};
> +
> +&i2c4 {
> + gt911@5d {
Same comments as previously apply.
> +
> + regulators {
No need to have this regulators indent level.
> + reg_3v3: regulator1 {
You can place this one directly. The preferred format is:
reg_3v3: regulator-reg-3v3 {
> +&ecspi1 {
> + fsl,spi-num-chipselects = <1>;
This property is obsoleted. Please remove it.
> + cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi1>;
> + status = "okay";
> +
> + fram@0 {
Generic name please. eeprom@0
> + compatible = "atmel,at25";
Please use the recommended compatible scheme as per
Documentation/devicetree/bindings/eeprom/at25.txt.
> + reg = <0>;
> + spi-max-frequency = <20000000>;
> + spi-cpha;
> + spi-cpol;
> + pagesize = <1>;
> + size = <8192>;
> + address-width = <16>;
> + };
> +};
> +&usbotg1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbotg1>;
> + dr_mode = "otg";
> + status = "okay";
We prefer to put the 'status' property as the last one.
> + srp-disable;
> + hnp-disable;
> + adp-disable;
> + vbus-supply = <®_usb_otg1_vbus>;
> +};
> +/ {
> + model = "Kontron N6310 SOM";
> + compatible = "kontron,n6310-som", "fsl,imx6ul";
> +
> + memory@80000000 {
device_type = "memory"; is missing here.
> + reg = <0x80000000 0x10000000>;
> + };
> +};
> +
> +&cpu0 {
> + clock-frequency = <528000000>;
Is this one really needed?
> +&ecspi2 {
> + cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi2>;
> + status = "okay";
> +
> + flash: mx25v80@0 {
spi-flash@0
> +&qspi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_qspi>;
> + status = "okay";
> +
> + flash0: w25m02gv@0 {
generic name, please.
^ permalink raw reply
* Re: [PATCH 06/17] ARM: dts: swift: Cleanup gpio-keys-polled properties
From: Adriana Kobylak @ 2019-07-26 17:53 UTC (permalink / raw)
To: Andrew Jeffery
Cc: devicetree, joel, linux-arm-kernel, linux-aspeed, linux-kernel,
mark.rutland, robh+dt
In-Reply-To: <20190726053959.2003-7-andrew@aj.id.au>
[-- Attachment #1: Type: text/plain, Size: 1508 bytes --]
Andrew Jeffery <andrew@aj.id.au> wrote on 07/26/2019 12:39:48 AM:
> From: Andrew Jeffery <andrew@aj.id.au>
> To: linux-aspeed@lists.ozlabs.org
> Cc: Andrew Jeffery <andrew@aj.id.au>, robh+dt@kernel.org,
> mark.rutland@arm.com, joel@jms.id.au, devicetree@vger.kernel.org,
> linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
> Adriana Kobylak <anoo@us.ibm.com>
> Date: 07/26/2019 12:40 AM
> Subject: [EXTERNAL] [PATCH 06/17] ARM: dts: swift: Cleanup gpio-
> keys-polled properties
>
> dtbs_check gave the following warning:
>
> Warning (avoid_unnecessary_addr_size): /gpio-keys-polled:
> unnecessary #address-cells/#size-cells without "ranges" or child
> "reg" property
>
> Cc: Adriana Kobylak <anoo@us.ibm.com>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Adriana Kobylak <anoo@us.ibm.com>
Tested-by: Adriana Kobylak <anoo@us.ibm.com>
> ---
> arch/arm/boot/dts/aspeed-bmc-opp-swift.dts | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/
> boot/dts/aspeed-bmc-opp-swift.dts
> index 2077e8d0e096..9f934509ca1b 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
> @@ -82,8 +82,6 @@
>
> gpio-keys-polled {
> compatible = "gpio-keys-polled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> poll-interval = <1000>;
>
> scm0-presence {
> --
> 2.20.1
>
[-- Attachment #2: Type: text/html, Size: 2372 bytes --]
^ permalink raw reply
* Re: [PATCH v4 00/11] add thermal driver for h6
From: Vasily Khoruzhick @ 2019-07-26 17:46 UTC (permalink / raw)
To: Yangtao Li
Cc: rui.zhang, Eduardo Valentin, Daniel Lezcano, Rob Herring,
Mark Rutland, Maxime Ripard, Chen-Yu Tsai, David S. Miller,
Greg Kroah-Hartman, Mauro Carvalho Chehab, Linus Walleij,
Nicolas Ferre, paulmck, devicetree, linux-kernel, arm-linux,
Linux PM
In-Reply-To: <CA+E=qVdAUFJM27cNL6WRkk5moX=mEk7WUs6UBoX58Y7ove40oQ@mail.gmail.com>
Hey Yangtao,
Are you planning to send v5 anytime soon?
On Sat, Jul 13, 2019 at 11:01 AM Vasily Khoruzhick <anarsoul@gmail.com> wrote:
>
> On Wed, Jul 10, 2019 at 4:09 PM Vasily Khoruzhick <anarsoul@gmail.com> wrote:
> >
> > On Sun, Jun 23, 2019 at 9:42 AM Yangtao Li <tiny.windzz@gmail.com> wrote:
> > >
> > > This patchset add support for H3 and H6 thermal sensor.
> > >
> > > BTY, do a cleanup in thermal makfile.
> > >
> > > Yangtao Li (11):
> > > thermal: sun8i: add thermal driver for h6
> > > dt-bindings: thermal: add binding document for h6 thermal controller
> > > thermal: fix indentation in makefile
> > > thermal: sun8i: get ths sensor number from device compatible
> > > thermal: sun8i: rework for sun8i_ths_get_temp()
> > > thermal: sun8i: get ths init func from device compatible
> > > thermal: sun8i: rework for ths irq handler func
> > > thermal: sun8i: support ahb clocks
> > > thermal: sun8i: rework for ths calibrate func
> > > dt-bindings: thermal: add binding document for h3 thermal controller
> > > thermal: sun8i: add thermal driver for h3
> >
> > It would be nice to add dts changes to this series. It's unlikely that
> > you'll get any "Tested-by" otherwise.
>
> I added A64 support on top of this series, see
> https://github.com/anarsoul/linux-2.6/tree/v5.2-thermal
>
> Branch also contains patches to enable DVFS on A64, feel free to
> cherry pick only those related to thermal driver if you want to
> include A64 support into v5 series.
>
> >
> > > .../bindings/thermal/sun8i-thermal.yaml | 94 +++
> > > MAINTAINERS | 7 +
> > > drivers/thermal/Kconfig | 14 +
> > > drivers/thermal/Makefile | 9 +-
> > > drivers/thermal/sun8i_thermal.c | 534 ++++++++++++++++++
> > > 5 files changed, 654 insertions(+), 4 deletions(-)
> > > create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml
> > > create mode 100644 drivers/thermal/sun8i_thermal.c
> > >
> > > ---
> > > v4:
> > > -add h3 support
> > > -fix yaml file
> > > ---
> > > 2.17.1
> > >
> > >
> > > _______________________________________________
> > > linux-arm-kernel mailing list
> > > linux-arm-kernel@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [RFC PATCH 15/17] ipmi: kcs: aspeed: Implement v2 bindings
From: Wang, Haiyue @ 2019-07-26 17:30 UTC (permalink / raw)
To: Andrew Jeffery, linux-aspeed
Cc: robh+dt, mark.rutland, joel, devicetree, linux-arm-kernel,
linux-kernel, Corey Minyard, Arnd Bergmann, Greg Kroah-Hartman,
openipmi-developer
In-Reply-To: <20190726053959.2003-16-andrew@aj.id.au>
在 2019-07-26 13:39, Andrew Jeffery 写道:
> The v2 bindings allow us to extract the resources from the devicetree.
> The table in the driver is retained to derive the channel index, which
> removes the need for kcs_chan property from the v1 bindings. The v2
> bindings allow us to reduce the number of warnings generated by the
> existing devicetree nodes.
>
> Cc: Haiyue Wang<haiyue.wang@linux.intel.com>
> Cc: Corey Minyard<minyard@acm.org>
> Cc: Arnd Bergmann<arnd@arndb.de>
> Cc: Greg Kroah-Hartman<gregkh@linuxfoundation.org>
> Cc:openipmi-developer@lists.sourceforge.net
> Signed-off-by: Andrew Jeffery<andrew@aj.id.au>
> ---
> drivers/char/ipmi/kcs_bmc_aspeed.c | 156 +++++++++++++++++++++++------
> 1 file changed, 127 insertions(+), 29 deletions(-)
Looks good, thanks for the hard work, the code is more clean! :)
Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com>
^ permalink raw reply
* Re: [RFC PATCH 14/17] ipmi: kcs: Finish configuring ASPEED KCS device before enable
From: Wang, Haiyue @ 2019-07-26 17:24 UTC (permalink / raw)
To: Andrew Jeffery, linux-aspeed
Cc: robh+dt, mark.rutland, joel, devicetree, linux-arm-kernel,
linux-kernel, Corey Minyard, Arnd Bergmann, Greg Kroah-Hartman,
openipmi-developer
In-Reply-To: <29a2d999-23bd-8e95-a1b8-f00e25a11df5@linux.intel.com>
在 2019-07-27 01:04, Wang, Haiyue 写道:
> 在 2019-07-26 13:39, Andrew Jeffery 写道:
>> The currently interrupts are configured after the channel was enabled.
>>
>> Cc: Haiyue Wang<haiyue.wang@linux.intel.com>
>> Cc: Corey Minyard<minyard@acm.org>
>> Cc: Arnd Bergmann<arnd@arndb.de>
>> Cc: Greg Kroah-Hartman<gregkh@linuxfoundation.org>
>> Cc:openipmi-developer@lists.sourceforge.net
>> Signed-off-by: Andrew Jeffery<andrew@aj.id.au>
>> ---
>> drivers/char/ipmi/kcs_bmc_aspeed.c | 7 ++++---
>> 1 file changed, 4 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/char/ipmi/kcs_bmc_aspeed.c
>> b/drivers/char/ipmi/kcs_bmc_aspeed.c
>> index 3c955946e647..e3dd09022589 100644
>> --- a/drivers/char/ipmi/kcs_bmc_aspeed.c
>> +++ b/drivers/char/ipmi/kcs_bmc_aspeed.c
>> @@ -268,13 +268,14 @@ static int aspeed_kcs_probe(struct
>> platform_device *pdev)
>> kcs_bmc->io_inputb = aspeed_kcs_inb;
>> kcs_bmc->io_outputb = aspeed_kcs_outb;
>> + rc = aspeed_kcs_config_irq(kcs_bmc, pdev);
>> + if (rc)
>> + return rc;
>> +
>> dev_set_drvdata(dev, kcs_bmc);
>
>
> Thanks for catching this, for not miss the data.
>
Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com>
^ permalink raw reply
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