* [PATCH v14 1/5] dt-bindings: Add a binding for Mediatek SCP
From: Pi-Hsun Shih @ 2019-08-05 10:49 UTC (permalink / raw)
Cc: Pi-Hsun Shih, Erin Lo, Rob Herring, Ohad Ben-Cohen,
Bjorn Andersson, Rob Herring, Mark Rutland, Matthias Brugger,
open list:REMOTE PROCESSOR REMOTEPROC SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support, open list
In-Reply-To: <20190805104932.96745-1-pihsun@chromium.org>
From: Erin Lo <erin.lo@mediatek.com>
Add a DT binding documentation of SCP for the
MT8183 SoC from Mediatek.
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes from v13, v12, v11, v10, v9, v8, v7, v6:
- No change.
Changes from v5:
- Remove dependency on CONFIG_RPMSG_MTK_SCP.
Changes from v4:
- Add detail of more properties.
- Document the usage of mtk,rpmsg-name in subnode from the new design.
Changes from v3:
- No change.
Changes from v2:
- No change. I realized that for this patch series, there's no need to
add anything under the mt8183-scp node (neither the mt8183-rpmsg or
the cros-ec-rpmsg) for them to work, since mt8183-rpmsg is added
directly as a rproc_subdev by code, and cros-ec-rpmsg is dynamically
created by SCP name service.
Changes from v1:
- No change.
---
.../bindings/remoteproc/mtk,scp.txt | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/remoteproc/mtk,scp.txt
diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.txt b/Documentation/devicetree/bindings/remoteproc/mtk,scp.txt
new file mode 100644
index 000000000000..3ba668bab14b
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.txt
@@ -0,0 +1,36 @@
+Mediatek SCP Bindings
+----------------------------------------
+
+This binding provides support for ARM Cortex M4 Co-processor found on some
+Mediatek SoCs.
+
+Required properties:
+- compatible Should be "mediatek,mt8183-scp"
+- reg Should contain the address ranges for the two memory
+ regions, SRAM and CFG.
+- reg-names Contains the corresponding names for the two memory
+ regions. These should be named "sram" & "cfg".
+- clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
+- clock-names Contains the corresponding name for the clock. This
+ should be named "main".
+
+Subnodes
+--------
+
+Subnodes of the SCP represent rpmsg devices. The names of the devices are not
+important. The properties of these nodes are defined by the individual bindings
+for the rpmsg devices - but must contain the following property:
+
+- mtk,rpmsg-name Contains the name for the rpmsg device. Used to match
+ the subnode to rpmsg device announced by SCP.
+
+Example:
+
+ scp: scp@10500000 {
+ compatible = "mediatek,mt8183-scp";
+ reg = <0 0x10500000 0 0x80000>,
+ <0 0x105c0000 0 0x5000>;
+ reg-names = "sram", "cfg";
+ clocks = <&infracfg CLK_INFRA_SCPSYS>;
+ clock-names = "main";
+ };
--
2.22.0.770.g0f2c4a37fd-goog
^ permalink raw reply related
* [PATCH v14 0/5] Add support for mt8183 SCP.
From: Pi-Hsun Shih @ 2019-08-05 10:49 UTC (permalink / raw)
Cc: Pi-Hsun Shih,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/Mediatek SoC support, open list,
moderated list:ARM/Mediatek SoC support,
open list:REMOTE PROCESSOR REMOTEPROC SUBSYSTEM
Add support for controlling and communicating with mt8183's system
control processor (SCP), using the remoteproc & rpmsg framework.
And also add a cros_ec driver for CrOS EC host command over rpmsg.
The overall structure of the series is:
* remoteproc/mtk_scp.c: Control the start / stop of SCP (Patch 2, 3).
* remoteproc/mtk_scp_ipi.c: Communicates to SCP using inter-processor
interrupt (IPI) and shared memory (Patch 2, 3).
* rpmsg/mtk_rpmsg.c: Wrapper to wrap the IPI communication into a rpmsg
device. Supports name service for SCP firmware to
announce channels (Patch 4).
* add scp dts node to mt8183 platform (Patch 5).
Changes from v13:
- Move include/linux/platform_data/mtk_scp.h to
include/linux/remoteproc/mtk_scp.h.
- Rename scp_get_reserve_* to scp_get_reserved_*.
- Add lock for access of scp->ipi_desc.
- Lock the whole ipi_send function.
- Move more setting of cache size from SCP firmware to kernel driver,
to prevent problem while loading firmware onto DRAM.
- Minor fixes addressing comment.
Changes from v12:
- Initialize cache before firmware load, to avoid problem while loading
large firmware.
- Disable watchdog before stopping SCP, to avoid extra warning message.
- Fix new warnings by checkpatch.
Changes from v11:
- Fixed a bug that mtk_rpmsg_endpoint is not properly cleaned up if
rproc_boot fails.
- Add missing documentation in comment.
Changes from v10:
- Drop applied cros_ec_rpmsg patches.
- Add clock reset before loading SCP firmware.
- Fix some type mismatch warnings when printing debug messages.
Changes from v9:
- Remove reserve-memory-vpu_share node.
- Remove change to cros_ec_commands.h (That is already in
https://lore.kernel.org/lkml/20190518063949.GY4319@dell/T/)
Changes from v8:
- Rebased onto https://patchwork.kernel.org/cover/10962385/.
- Drop merged cros_ec_rpmsg patch, and add scp dts node patch.
- Add more reserved memory region.
Changes from v7:
- Rebase onto https://lore.kernel.org/patchwork/patch/1059196/.
- Fix clock enable/disable timing for SCP driver.
- Add more SCP IPI ID.
Changes from v6:
- Decouple mtk_rpmsg from mtk_scp.
- Change data of EC response to be aligned to 4 bytes.
Changes from v5:
- Add device tree binding document for cros_ec_rpmsg.
- Better document in comments for cros_ec_rpmsg.
- Remove dependency on CONFIG_ in binding tree document.
Changes from v4:
- Merge patch 6 (Load ELF firmware) into patch 2, so the driver loads
ELF firmware by default, and no longer accept plain binary.
- rpmsg_device listed in device tree (as a child of the SCP node) would
have it's device tree node mapped to the rpmsg_device, so the rpmsg
driver can use the properties on device tree.
Changes from v3:
- Make writing to SCP SRAM aligned.
- Add a new patch (Patch 6) to load ELF instead of bin firmware.
- Add host event support for EC driver.
- Fix some bugs found in testing (missing spin_lock_init,
rproc_subdev_unprepare to rproc_subdev_stop).
- Fix some coding style issue found by checkpatch.pl.
Changes from v2:
- Fold patch 3 into patch 2 in v2.
- Move IPI id around to support cross-testing for old and new firmware.
- Finish more TODO items.
Changes from v1:
- Extract functions and rename variables in mtk_scp.c.
- Do cleanup properly in mtk_rpmsg.c, which also removes the problem of
short-lived work items.
- Code format fix based on feedback for cros_ec_rpmsg.c.
- Extract feature detection for SCP into separate patch (Patch 6).
Eddie Huang (1):
arm64: dts: mt8183: add scp node
Erin Lo (3):
dt-bindings: Add a binding for Mediatek SCP
remoteproc/mediatek: add SCP support for mt8183
remoteproc: mt8183: add reserved memory manager API
Pi-Hsun Shih (1):
rpmsg: add rpmsg support for mt8183 SCP.
.../bindings/remoteproc/mtk,scp.txt | 36 +
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 11 +
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 12 +
drivers/remoteproc/Kconfig | 10 +
drivers/remoteproc/Makefile | 1 +
drivers/remoteproc/mtk_common.h | 92 +++
drivers/remoteproc/mtk_scp.c | 710 ++++++++++++++++++
drivers/remoteproc/mtk_scp_ipi.c | 159 ++++
drivers/rpmsg/Kconfig | 9 +
drivers/rpmsg/Makefile | 1 +
drivers/rpmsg/mtk_rpmsg.c | 414 ++++++++++
include/linux/remoteproc/mtk_scp.h | 168 +++++
include/linux/rpmsg/mtk_rpmsg.h | 38 +
13 files changed, 1661 insertions(+)
create mode 100644 Documentation/devicetree/bindings/remoteproc/mtk,scp.txt
create mode 100644 drivers/remoteproc/mtk_common.h
create mode 100644 drivers/remoteproc/mtk_scp.c
create mode 100644 drivers/remoteproc/mtk_scp_ipi.c
create mode 100644 drivers/rpmsg/mtk_rpmsg.c
create mode 100644 include/linux/remoteproc/mtk_scp.h
create mode 100644 include/linux/rpmsg/mtk_rpmsg.h
--
2.22.0.770.g0f2c4a37fd-goog
^ permalink raw reply
* Re: [PATCH 3/3] dt-bindings: aspeed: Remove mention of deprecated compatibles
From: Linus Walleij @ 2019-08-05 10:48 UTC (permalink / raw)
To: Andrew Jeffery
Cc: linux-aspeed, Lee Jones, Rob Herring, Mark Rutland, Joel Stanley,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, linux-kernel@vger.kernel.org, open list:GPIO SUBSYSTEM
In-Reply-To: <20190724081313.12934-4-andrew@aj.id.au>
On Wed, Jul 24, 2019 at 10:13 AM Andrew Jeffery <andrew@aj.id.au> wrote:
> Guide readers away from using the aspeed,g[45].* compatible patterns.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Patch applied to the pinctrl tree.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 2/3] pinctrl: aspeed: Document existence of deprecated compatibles
From: Linus Walleij @ 2019-08-05 10:47 UTC (permalink / raw)
To: Andrew Jeffery
Cc: linux-aspeed, Lee Jones, Rob Herring, Mark Rutland, Joel Stanley,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, linux-kernel@vger.kernel.org, open list:GPIO SUBSYSTEM
In-Reply-To: <20190724081313.12934-3-andrew@aj.id.au>
On Wed, Jul 24, 2019 at 10:13 AM Andrew Jeffery <andrew@aj.id.au> wrote:
> Otherwise they look odd in the face of not being listed in the bindings
> documents.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Patch applied to the pinctrl tree.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 0/3] ARM: dts: aspeed: Deprecate g[45]-style compatibles
From: Linus Walleij @ 2019-08-05 10:45 UTC (permalink / raw)
To: Joel Stanley
Cc: Andrew Jeffery, linux-aspeed, Lee Jones, Rob Herring,
Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, linux-kernel@vger.kernel.org, open list:GPIO SUBSYSTEM
In-Reply-To: <CACPK8XcWK9Gf=pW5ds=3muoXHAWnyYfHcVSVh+anaTigtMO8yA@mail.gmail.com>
On Fri, Aug 2, 2019 at 8:15 AM Joel Stanley <joel@jms.id.au> wrote:
> > Joel, do you mind if Linus takes this series through the pinctrl tree, given
> > the fix to the devicetrees is patch 1/3?
>
> It depends if you plan more changes to that part of the device tree
> this merge window :)
>
> Linus, perhaps the safer option is for me to take 1/3 through my tree
> and you can take the rest through yours?
OK let's proceed like that.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 2/3] rtc: sun6i: Add support for H6 RTC
From: Ondřej Jirman @ 2019-08-05 10:45 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Alessandro Zummo, Alexandre Belloni, Rob Herring, Mark Rutland,
Maxime Ripard, linux-rtc-u79uwXL29TY76Z2rM5mHXA, devicetree,
linux-arm-kernel, linux-kernel, linux-sunxi
In-Reply-To: <CAGb2v675j-aCLMgPJOzr9yx1XxsUvHRr_K7VnL=p8mSdwpu2jw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Mon, Aug 05, 2019 at 06:16:14PM +0800, Chen-Yu Tsai wrote:
> On Fri, Apr 12, 2019 at 8:07 PM megous via linux-sunxi
> <linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org> wrote:
> >
> > From: Ondrej Jirman <megous-5qf/QAjKc83QT0dZR+AlfA@public.gmane.org>
> >
> > RTC on H6 is mostly the same as on H5 and H3. It has slight differences
> > mostly in features that are not yet supported by this driver.
> >
> > Some differences are already stated in the comments in existing code.
> > One other difference is that H6 has extra bit in LOSC_CTRL_REG, called
> > EXT_LOSC_EN to enable/disable external low speed crystal oscillator.
> >
> > It also has bit EXT_LOSC_STA in LOSC_AUTO_SWT_STA_REG, to check whether
> > external low speed oscillator is working correctly.
> >
> > This patch adds support for enabling LOSC when necessary:
> >
> > - during reparenting
> > - when probing the clock
> >
> > H6 also has capacbility to automatically reparent RTC clock from
> > external crystal oscillator, to internal RC oscillator, if external
> > oscillator fails. This is enabled by default. Disable it during
> > probe.
> >
> > Signed-off-by: Ondrej Jirman <megous-5qf/QAjKc83QT0dZR+AlfA@public.gmane.org>
> > ---
> > drivers/rtc/rtc-sun6i.c | 40 ++++++++++++++++++++++++++++++++++++++--
> > 1 file changed, 38 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
> > index 11f56de52179..7375a530c565 100644
> > --- a/drivers/rtc/rtc-sun6i.c
> > +++ b/drivers/rtc/rtc-sun6i.c
> > @@ -41,9 +41,11 @@
> > /* Control register */
> > #define SUN6I_LOSC_CTRL 0x0000
> > #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16)
> > +#define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15)
>
> Manual says bit 14? Or is this different from LOSC_AUTO_SWT_EN?
>
> The rest looks ok.
To give you more information. This is a new thing in H6 BSP, compared
to BSPs for previous SoCs (H5/H3).
20 #define REG_CLK32K_AUTO_SWT_EN BIT(14)
21 #define REG_CLK32K_AUTO_SWT_BYPASS BIT(15)
Init sequence changed in H6 BSP to:
646 /*
647 * Step1: select RTC clock source
648 */
649 tmp_data = readl(chip->base + SUNXI_LOSC_CTRL);
650 tmp_data &= (~REG_CLK32K_AUTO_SWT_EN);
651
652 /* Disable auto switch function */
653 tmp_data |= REG_CLK32K_AUTO_SWT_BYPASS;
654 writel(tmp_data, chip->base + SUNXI_LOSC_CTRL);
655
656 tmp_data = readl(chip->base + SUNXI_LOSC_CTRL);
657 tmp_data |= (RTC_SOURCE_EXTERNAL | REG_LOSCCTRL_MAGIC);
658 writel(tmp_data, chip->base + SUNXI_LOSC_CTRL);
659
660 /* We need to set GSM after change clock source */
661 udelay(10);
662 tmp_data = readl(chip->base + SUNXI_LOSC_CTRL);
663 tmp_data |= (EXT_LOSC_GSM | REG_LOSCCTRL_MAGIC);
664 writel(tmp_data, chip->base + SUNXI_LOSC_CTRL);
665
For older BSPs, the init sequence looked like this:
482 /*
483 * Step1: select RTC clock source
484 */
485 tmp_data = sunxi_rtc_read(SUNXI_LOSC_CTRL_REG);
486 tmp_data &= (~REG_CLK32K_AUTO_SWT_EN);
487 tmp_data |= (RTC_SOURCE_EXTERNAL | REG_LOSCCTRL_MAGIC);
488 tmp_data |= (EXT_LOSC_GSM);
489 sunxi_rtc_write(tmp_data, SUNXI_LOSC_CTRL_REG);
490
EXT_LOSC_GSM has values 4 values from low to high, and I guess it configures
gain for the oscillator's amplifier in the feedback loop of the circuit.
So the new code, for some reason changed from single write to sequence
of individual writes/config steps:
1) disable auto-switch and enable auto-switch bypass
2) select RTC clock source (to LOSC)
(wait)
3) configure gain on the LOSC
regards,
o.
> ChenYu
^ permalink raw reply
* Re: [PATCH 0/6] pinctrl: aspeed: Add AST2600 pinmux support
From: Linus Walleij @ 2019-08-05 10:42 UTC (permalink / raw)
To: Andrew Jeffery
Cc: open list:GPIO SUBSYSTEM, Rob Herring, Mark Rutland, Joel Stanley,
ryanchen.aspeed, johnny_huang, linux-aspeed,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, linux-kernel@vger.kernel.org
In-Reply-To: <20190711041942.23202-1-andrew@aj.id.au>
I applied this series now!
Thanks Andrew.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH/RFC 12/12] arm64: dts: renesas: Add EK874 board with idk-2121wr display support
From: Laurent Pinchart @ 2019-08-05 10:36 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Kieran Bingham, Jacopo Mondi, Rob Herring, Mark Rutland,
Simon Horman, Magnus Damm, linux-renesas-soc@vger.kernel.org,
devicetree@vger.kernel.org, Geert Uytterhoeven, Chris Paterson,
Biju Das, ebiharaml@si-linux.co.jp
In-Reply-To: <TY1PR01MB177040DF4ADCF460CDA0D8AEC0DA0@TY1PR01MB1770.jpnprd01.prod.outlook.com>
Hi Fabrizio,
On Mon, Aug 05, 2019 at 09:37:29AM +0000, Fabrizio Castro wrote:
> On 02 August 2019 09:34 Laurent Pinchart wrote:
> > On Fri, Aug 02, 2019 at 08:34:09AM +0100, Fabrizio Castro wrote:
> > > The EK874 is advertised as compatible with panel IDK-2121WR from
> > > Advantech, however the panel isn't sold alongside the board.
> > > A new dts, adding everything that's required to get the panel to
> > > to work with the EK874, is the most convenient way to support the
> > > EK874 when it's connected to the IDK-2121WR.
> > >
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > ---
> > > arch/arm64/boot/dts/renesas/Makefile | 3 +-
> > > .../boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts | 112 +++++++++++++++++++++
> > > 2 files changed, 114 insertions(+), 1 deletion(-)
> > > create mode 100644 arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
> > > index 42b74c2..ce48478 100644
> > > --- a/arch/arm64/boot/dts/renesas/Makefile
> > > +++ b/arch/arm64/boot/dts/renesas/Makefile
> > > @@ -1,7 +1,8 @@
> > > # SPDX-License-Identifier: GPL-2.0
> > > dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb
> > > dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb
> > > -dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb
> > > +dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb \
> > > + r8a774c0-ek874-idk-2121wr.dtb
> > > dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
> > > dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb
> > > dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
> > > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-
> > 2121wr.dts
> > > new file mode 100644
> > > index 0000000..d989998
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts
> > > @@ -0,0 +1,112 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874),
> > > + * connected to an Advantech IDK-2121WR 21.5" LVDS panel
> > > + *
> > > + * Copyright (C) 2019 Renesas Electronics Corp.
> > > + */
> > > +
> > > +#include "r8a774c0-ek874.dts"
> > > +
> > > +/ {
> > > + backlight: backlight {
> > > + compatible = "pwm-backlight";
> > > + pwms = <&pwm5 0 50000>;
> > > +
> > > + brightness-levels = <0 4 8 16 32 64 128 255>;
> > > + default-brightness-level = <6>;
> > > +
> > > + power-supply = <®_12p0v>;
> > > + enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
> > > + };
> > > +
> > > + panel-lvds {
> > > + compatible = "advantech,idk-2121wr", "panel-lvds";
> > > +
> > > + width-mm = <476>;
> > > + height-mm = <268>;
> > > +
> > > + data-mapping = "vesa-24";
> > > +
> > > + panel-timing {
> > > + clock-frequency = <148500000>;
> > > + hactive = <1920>;
> > > + vactive = <1080>;
> > > + hsync-len = <44>;
> > > + hfront-porch = <88>;
> > > + hback-porch = <148>;
> > > + vfront-porch = <4>;
> > > + vback-porch = <36>;
> > > + vsync-len = <5>;
> > > + };
> > > +
> > > + ports {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + port@0 {
> > > + reg = <0>;
> > > + lvds0_panel_in: endpoint {
> > > + remote-endpoint = <&lvds0_out>;
> > > + };
> > > + };
> > > +
> > > + port@1 {
> > > + reg = <1>;
> > > + lvds1_panel_in: endpoint {
> > > + remote-endpoint = <&lvds1_out>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +};
> > > +
> > > +&gpio0 {
> > > + lvds-connector-en-gpio{
> > > + gpio-hog;
> > > + gpios = <17 GPIO_ACTIVE_HIGH>;
> > > + output-low;
> > > + line-name = "lvds-connector-en-gpio";
> > > + };
> >
> > Any chance to specify this as the panel's enable signal in the panel DT
> > node ?
>
> I am not too sure, as this is not exactly an enable signal. When GP0_17 is low
> then LVDS[01] are connected to the LVDS connector, when GP0_17 is high
> then LVDS[01] are connected to the LT8918L.
> Perhaps we should leave this fixed to low to avoid confusion?
The line-name was confusing me. A GPIO hog is thus indeed the best
option. A comment that explains what the signal is for could help.
> > > +};
> > > +
> > > +&lvds0 {
> > > + renesas,swap-data;
> >
> > Let's discuss this property in reply to the DT bindings patch.
> >
> > > +
> > > + ports {
> > > + port@1 {
> > > + lvds0_out: endpoint {
> > > + remote-endpoint = <&lvds0_panel_in>;
> > > + };
> > > + };
> > > + };
> > > +};
> > > +
> > > +&lvds1 {
> > > + status = "okay";
> > > +
> > > + clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>;
> > > + clock-names = "fck", "dclkin.0", "extal";
> > > +
> > > + ports {
> > > + port@1 {
> > > + lvds1_out: endpoint {
> > > + remote-endpoint = <&lvds1_panel_in>;
> > > + };
> > > + };
> > > + };
> > > +};
> > > +
> > > +&pfc {
> > > + pwm5_pins: pwm5 {
> > > + groups = "pwm5_a";
> > > + function = "pwm5";
> > > + };
> > > +};
> > > +
> > > +&pwm5 {
> > > + pinctrl-0 = <&pwm5_pins>;
> > > + pinctrl-names = "default";
> > > +
> > > + status = "okay";
> > > +};
> >
> > I haven't reviewed pinouts in detail, but the patch otherwise looks sane
> > to me. Another candidate for DT overlays though ;-)
--
Regards,
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH v2] arm64: dts: fast models: Remove clcd's max-memory-bandwidth
From: Linus Walleij @ 2019-08-05 10:31 UTC (permalink / raw)
To: Kevin Brodsky
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Pawel Moll, Ruben Ayrapetyan, Liviu Dudau,
open list:DRM PANEL DRIVERS, Sudeep Holla, Robin Murphy,
Linux ARM
In-Reply-To: <20190725171215.71801-1-kevin.brodsky@arm.com>
On Thu, Jul 25, 2019 at 7:12 PM Kevin Brodsky <kevin.brodsky@arm.com> wrote:
> It is unclear why max-memory-bandwidth should be set for CLCD on the
> fast model. Removing that property allows allocating and using 32bpp
> buffers, which may be desirable on certain platforms such as
> Android.
>
> Reported-by: Ruben Ayrapetyan <ruben.ayrapetyan@arm.com>
> Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH 2/2] DTS: ARM: gta04: introduce legacy spi-cs-high to make display work again
From: Linus Walleij @ 2019-08-05 10:29 UTC (permalink / raw)
To: Rob Herring
Cc: H. Nikolaus Schaller, Mark Brown, Mark Rutland,
Benoît Cousson, Tony Lindgren,
Discussions about the Letux Kernel, linux-spi, devicetree,
Linux Kernel Mailing List, Linux-OMAP, stable
In-Reply-To: <CAL_JsqLe_Y9Z6MRt7ojgSVKAb9n95S8j=eGidSVNz2T83j-zPQ@mail.gmail.com>
On Fri, Jul 26, 2019 at 12:43 AM Rob Herring <robh@kernel.org> wrote:
> On Thu, Jul 25, 2019 at 12:23 AM H. Nikolaus Schaller <hns@goldelico.com> wrote:
> > I tried to convince Linus that this is the right way but he convinced
> > me that a fix that handles all cases does not exist.
> >
> > There seem to be embedded devices with older DTB (potentially in ROM)
> > which provide a plain 0 value for a gpios definition. And either with
> > or without spi-cs-high.
> >
> > Since "0" is the same as "GPIO_ACTIVE_HIGH", the absence of
> > spi-cs-high was and must be interpreted as active low for these
> > devices. This leads to the inversion logic in code.
> >
> > AFAIR it boils down to the question if gpiolib and the bindings
> > should still support such legacy devices with out-of tree DTB,
> > but force in-tree DTS to add the legacy spi-cs-high property.
> >
> > Or if we should fix the 2 or 3 cases of in-tree legacy cases
> > and potentially break out-of tree DTBs.
>
> If it is small number of platforms, then the kernel could handle those
> cases explicitly as needed.
>
> > IMHO it is more general to keep the out-of-tree DTBs working
> > and "fix" what we can control (in-tree DTS).
>
> If we do this, then we need to not call spi-cs-high legacy because
> we're stuck with it forever.
I agree. The background on it is here:
https://lkml.org/lkml/2019/4/2/4
Not using the negatively defined (i.e. if it is no there, the line is
by default active low) spi-cs-high would break
PowerPC, who were AFAICT using this to ship devices.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v4] arm64: dts: ls1028a: Add esdhc node in dts
From: Yinbo Zhu @ 2019-08-05 10:26 UTC (permalink / raw)
To: Shawn Guo, Li Yang, Rob Herring
Cc: yinbo.zhu, xiaobo.xie, jiafei.pan, Mark Rutland, linux-arm-kernel,
devicetree, linux-kernel, linux-mmc, yangbo.lu, Ashish Kumar
From: Ashish Kumar <Ashish.Kumar@nxp.com>
This patch is to add esdhc node and enable SD UHS-I,
eMMC HS200 for ls1028ardb/ls1028aqds board.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
---
Change in v4:
put esdhc 'status' at end of property list.
sort the nodes in unit-address
Use IRQ_TYPE_LEVEL_HIGH represent 0x4 in "interrupts = <0 28 0x4>"
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 8 +++++++
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 13 +++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 27 +++++++++++++++++++++++
3 files changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index de6ef39..5e14e5a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -95,6 +95,14 @@
status = "okay";
};
+&esdhc {
+ status = "okay";
+};
+
+&esdhc1 {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 9fb9113..12c9cd3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -83,6 +83,19 @@
};
};
+&esdhc {
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
+ status = "okay";
+ };
+
+&esdhc1 {
+ mmc-hs200-1_8v;
+ status = "okay";
+ };
+
&i2c0 {
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 7975519..f299075 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -245,6 +245,33 @@
status = "disabled";
};
+ esdhc: mmc@2140000 {
+ compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
+ reg = <0x0 0x2140000 0x0 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>; /* fixed up by bootloader */
+ clocks = <&clockgen 2 1>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ little-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ esdhc1: mmc@2150000 {
+ compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
+ reg = <0x0 0x2150000 0x0 0x10000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>; /* fixed up by bootloader */
+ clocks = <&clockgen 2 1>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ broken-cd;
+ little-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
--
2.9.5
^ permalink raw reply related
* Re: [linux-sunxi] [PATCH 2/3] rtc: sun6i: Add support for H6 RTC
From: Ondřej Jirman @ 2019-08-05 10:20 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Alessandro Zummo, Alexandre Belloni, Rob Herring, Mark Rutland,
Maxime Ripard, linux-rtc, devicetree, linux-arm-kernel,
linux-kernel, linux-sunxi
In-Reply-To: <CAGb2v675j-aCLMgPJOzr9yx1XxsUvHRr_K7VnL=p8mSdwpu2jw@mail.gmail.com>
On Mon, Aug 05, 2019 at 06:16:14PM +0800, Chen-Yu Tsai wrote:
> On Fri, Apr 12, 2019 at 8:07 PM megous via linux-sunxi
> <linux-sunxi@googlegroups.com> wrote:
> >
> > From: Ondrej Jirman <megous@megous.com>
> >
> > RTC on H6 is mostly the same as on H5 and H3. It has slight differences
> > mostly in features that are not yet supported by this driver.
> >
> > Some differences are already stated in the comments in existing code.
> > One other difference is that H6 has extra bit in LOSC_CTRL_REG, called
> > EXT_LOSC_EN to enable/disable external low speed crystal oscillator.
> >
> > It also has bit EXT_LOSC_STA in LOSC_AUTO_SWT_STA_REG, to check whether
> > external low speed oscillator is working correctly.
> >
> > This patch adds support for enabling LOSC when necessary:
> >
> > - during reparenting
> > - when probing the clock
> >
> > H6 also has capacbility to automatically reparent RTC clock from
> > external crystal oscillator, to internal RC oscillator, if external
> > oscillator fails. This is enabled by default. Disable it during
> > probe.
> >
> > Signed-off-by: Ondrej Jirman <megous@megous.com>
> > ---
> > drivers/rtc/rtc-sun6i.c | 40 ++++++++++++++++++++++++++++++++++++++--
> > 1 file changed, 38 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
> > index 11f56de52179..7375a530c565 100644
> > --- a/drivers/rtc/rtc-sun6i.c
> > +++ b/drivers/rtc/rtc-sun6i.c
> > @@ -41,9 +41,11 @@
> > /* Control register */
> > #define SUN6I_LOSC_CTRL 0x0000
> > #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16)
> > +#define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15)
>
> Manual says bit 14? Or is this different from LOSC_AUTO_SWT_EN?
>
> The rest looks ok.
Yes, see H6 BSP:
drivers/rtc/rtc-sunxi.h
20 #define REG_CLK32K_AUTO_SWT_EN BIT(14)
21 #define REG_CLK32K_AUTO_SWT_BYPASS BIT(15)
regards,
Ondrej
> ChenYu
^ permalink raw reply
* [PATCH 2/2] dt-bindings: iio: imu: st_lsm6dsx: add ism330dhcx device bindings
From: Lorenzo Bianconi @ 2019-08-05 10:18 UTC (permalink / raw)
To: jic23; +Cc: lorenzo.bianconi, linux-iio, devicetree
In-Reply-To: <cover.1564999807.git.lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt b/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt
index 92b48f242356..87407d110bb7 100644
--- a/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt
+++ b/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt
@@ -12,6 +12,7 @@ Required properties:
"st,lsm6dsox"
"st,lsm6dsr"
"st,lsm6ds3tr-c"
+ "st,ism330dhcx"
- reg: i2c address of the sensor / spi cs line
Optional properties:
--
2.21.0
^ permalink raw reply related
* [PATCH 1/2] iio: imu: st_lsm6dsx: add support to ISM330DHCX
From: Lorenzo Bianconi @ 2019-08-05 10:18 UTC (permalink / raw)
To: jic23; +Cc: lorenzo.bianconi, linux-iio, devicetree
In-Reply-To: <cover.1564999807.git.lorenzo@kernel.org>
Add support to STM ISM330DHCX 6-axis (acc + gyro) Mems sensor
https://www.st.com/resource/en/datasheet/ism330dhcx.pdf
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/iio/imu/st_lsm6dsx/Kconfig | 3 ++-
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h | 2 ++
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c | 7 ++++---
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c | 5 ++++-
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c | 5 +++++
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c | 5 +++++
6 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/iio/imu/st_lsm6dsx/Kconfig b/drivers/iio/imu/st_lsm6dsx/Kconfig
index 6cbf65a7e11e..939058b27746 100644
--- a/drivers/iio/imu/st_lsm6dsx/Kconfig
+++ b/drivers/iio/imu/st_lsm6dsx/Kconfig
@@ -11,7 +11,8 @@ config IIO_ST_LSM6DSX
help
Say yes here to build support for STMicroelectronics LSM6DSx imu
sensor. Supported devices: lsm6ds3, lsm6ds3h, lsm6dsl, lsm6dsm,
- ism330dlc, lsm6dso, lsm6dsox, asm330lhh, lsm6dsr, lsm6ds3tr-c
+ ism330dlc, lsm6dso, lsm6dsox, asm330lhh, lsm6dsr, lsm6ds3tr-c,
+ ism330dhcx
To compile this driver as a module, choose M here: the module
will be called st_lsm6dsx.
diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
index 5090f1b3525a..4d47ba36de84 100644
--- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
+++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
@@ -23,6 +23,7 @@
#define ST_LSM6DSOX_DEV_NAME "lsm6dsox"
#define ST_LSM6DSR_DEV_NAME "lsm6dsr"
#define ST_LSM6DS3TRC_DEV_NAME "lsm6ds3tr-c"
+#define ST_ISM330DHCX_DEV_NAME "ism330dhcx"
enum st_lsm6dsx_hw_id {
ST_LSM6DS3_ID,
@@ -35,6 +36,7 @@ enum st_lsm6dsx_hw_id {
ST_LSM6DSOX_ID,
ST_LSM6DSR_ID,
ST_LSM6DS3TRC_ID,
+ ST_ISM330DHCX_ID,
ST_LSM6DSX_MAX_ID,
};
diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c
index 1be1cec2ab23..2c03a5b80f80 100644
--- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c
+++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c
@@ -14,9 +14,10 @@
* (e.g. Gx, Gy, Gz, Ax, Ay, Az), then data are repeated depending on the
* value of the decimation factor and ODR set for each FIFO data set.
*
- * LSM6DSO/LSM6DSOX/ASM330LHH/LSM6DSR: The FIFO buffer can be configured to
- * store data from gyroscope and accelerometer. Each sample is queued with
- * a tag (1B) indicating data source (gyroscope, accelerometer, hw timer).
+ * LSM6DSO/LSM6DSOX/ASM330LHH/LSM6DSR/ISM330DHCX: The FIFO buffer can be
+ * configured to store data from gyroscope and accelerometer. Each sample
+ * is queued with a tag (1B) indicating data source (gyroscope, accelerometer,
+ * hw timer).
*
* FIFO supported modes:
* - BYPASS: FIFO disabled
diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
index fc4d18b58c97..85824d6739ee 100644
--- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
+++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
@@ -24,7 +24,7 @@
* - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000
* - FIFO size: 4KB
*
- * - LSM6DSO/LSM6DSOX/ASM330LHH/LSM6DSR
+ * - LSM6DSO/LSM6DSOX/ASM330LHH/LSM6DSR/ISM330DHCX:
* - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416
* - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16
* - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000
@@ -645,6 +645,9 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
{
.hw_id = ST_LSM6DSR_ID,
.name = ST_LSM6DSR_DEV_NAME,
+ }, {
+ .hw_id = ST_ISM330DHCX_ID,
+ .name = ST_ISM330DHCX_DEV_NAME,
},
},
.channels = {
diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c
index 28581eb0532c..15c6aa5b6caa 100644
--- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c
+++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c
@@ -79,6 +79,10 @@ static const struct of_device_id st_lsm6dsx_i2c_of_match[] = {
.compatible = "st,lsm6ds3tr-c",
.data = (void *)ST_LSM6DS3TRC_ID,
},
+ {
+ .compatible = "st,ism330dhcx",
+ .data = (void *)ST_ISM330DHCX_ID,
+ },
{},
};
MODULE_DEVICE_TABLE(of, st_lsm6dsx_i2c_of_match);
@@ -94,6 +98,7 @@ static const struct i2c_device_id st_lsm6dsx_i2c_id_table[] = {
{ ST_LSM6DSOX_DEV_NAME, ST_LSM6DSOX_ID },
{ ST_LSM6DSR_DEV_NAME, ST_LSM6DSR_ID },
{ ST_LSM6DS3TRC_DEV_NAME, ST_LSM6DS3TRC_ID },
+ { ST_ISM330DHCX_DEV_NAME, ST_ISM330DHCX_ID },
{},
};
MODULE_DEVICE_TABLE(i2c, st_lsm6dsx_i2c_id_table);
diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c
index 0371e8b94a3e..a8430ee11310 100644
--- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c
+++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c
@@ -79,6 +79,10 @@ static const struct of_device_id st_lsm6dsx_spi_of_match[] = {
.compatible = "st,lsm6ds3tr-c",
.data = (void *)ST_LSM6DS3TRC_ID,
},
+ {
+ .compatible = "st,ism330dhcx",
+ .data = (void *)ST_ISM330DHCX_ID,
+ },
{},
};
MODULE_DEVICE_TABLE(of, st_lsm6dsx_spi_of_match);
@@ -94,6 +98,7 @@ static const struct spi_device_id st_lsm6dsx_spi_id_table[] = {
{ ST_LSM6DSOX_DEV_NAME, ST_LSM6DSOX_ID },
{ ST_LSM6DSR_DEV_NAME, ST_LSM6DSR_ID },
{ ST_LSM6DS3TRC_DEV_NAME, ST_LSM6DS3TRC_ID },
+ { ST_ISM330DHCX_DEV_NAME, ST_ISM330DHCX_ID },
{},
};
MODULE_DEVICE_TABLE(spi, st_lsm6dsx_spi_id_table);
--
2.21.0
^ permalink raw reply related
* [PATCH 0/2] add support to STM ISM330DHCX 6-axis Mems sensor
From: Lorenzo Bianconi @ 2019-08-05 10:18 UTC (permalink / raw)
To: jic23; +Cc: lorenzo.bianconi, linux-iio, devicetree
Add support to STM ISM330DHCX 6-axis sensor
https://www.st.com/resource/en/datasheet/ism330dhcx.pdf
This series is based on '[v2,0/4] st_lsm6dsx: move {odr,fs}_table in'
https://patchwork.kernel.org/cover/11064381/
Lorenzo Bianconi (2):
iio: imu: st_lsm6dsx: add support to ISM330DHCX
dt-bindings: iio: imu: st_lsm6dsx: add ism330dhcx device bindings
Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt | 1 +
drivers/iio/imu/st_lsm6dsx/Kconfig | 3 ++-
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h | 2 ++
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c | 7 ++++---
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c | 5 ++++-
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c | 5 +++++
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c | 5 +++++
7 files changed, 23 insertions(+), 5 deletions(-)
--
2.21.0
^ permalink raw reply
* Re: [PATCH] arm64: dts: fast models: Increase clcd's max-memory-bandwidth
From: Linus Walleij @ 2019-08-05 10:18 UTC (permalink / raw)
To: Robin Murphy
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Pawel Moll, Ruben Ayrapetyan, Kevin Brodsky, Liviu Dudau,
open list:DRM PANEL DRIVERS, Sudeep Holla, Brian Starkey,
Linux ARM
In-Reply-To: <042d5c3d-96fe-5466-3869-a0a3a08b964d@arm.com>
On Thu, Jul 25, 2019 at 5:15 PM Robin Murphy <robin.murphy@arm.com> wrote:
> Given that the property is optional anyway, would it hurt to just remove
> it? After trying to dig up any relevant internal email history, it's
> still far from clear how and why it got here in the first place.
Isn't it just my sloppy copy-paste when fixing up the device trees
for the DRM transition? I agree it should just be removed.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: Add compatible for H6 RTC
From: Chen-Yu Tsai @ 2019-08-05 10:16 UTC (permalink / raw)
To: Ondřej Jirman
Cc: Alessandro Zummo, Alexandre Belloni, Rob Herring, Mark Rutland,
Maxime Ripard, linux-rtc-u79uwXL29TY76Z2rM5mHXA, devicetree,
linux-arm-kernel, linux-kernel, linux-sunxi
In-Reply-To: <20190412120730.473-2-megous-5qf/QAjKc83QT0dZR+AlfA@public.gmane.org>
On Fri, Apr 12, 2019 at 8:07 PM megous via linux-sunxi
<linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org> wrote:
>
> From: Ondrej Jirman <megous-5qf/QAjKc83QT0dZR+AlfA@public.gmane.org>
>
> RTC on H6 is similar to the one on H5 SoC, but incompatible in small
> details. See the driver for description of differences. For example
> H6 RTC needs to enable the external low speed oscillator. Add new
> compatible for this RTC.
>
> Signed-off-by: Ondrej Jirman <megous-5qf/QAjKc83QT0dZR+AlfA@public.gmane.org>
Acked-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
^ permalink raw reply
* Re: [PATCH 2/3] rtc: sun6i: Add support for H6 RTC
From: Chen-Yu Tsai @ 2019-08-05 10:16 UTC (permalink / raw)
To: Ondřej Jirman
Cc: Alessandro Zummo, Alexandre Belloni, Rob Herring, Mark Rutland,
Maxime Ripard, linux-rtc-u79uwXL29TY76Z2rM5mHXA, devicetree,
linux-arm-kernel, linux-kernel, linux-sunxi
In-Reply-To: <20190412120730.473-3-megous-5qf/QAjKc83QT0dZR+AlfA@public.gmane.org>
On Fri, Apr 12, 2019 at 8:07 PM megous via linux-sunxi
<linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org> wrote:
>
> From: Ondrej Jirman <megous-5qf/QAjKc83QT0dZR+AlfA@public.gmane.org>
>
> RTC on H6 is mostly the same as on H5 and H3. It has slight differences
> mostly in features that are not yet supported by this driver.
>
> Some differences are already stated in the comments in existing code.
> One other difference is that H6 has extra bit in LOSC_CTRL_REG, called
> EXT_LOSC_EN to enable/disable external low speed crystal oscillator.
>
> It also has bit EXT_LOSC_STA in LOSC_AUTO_SWT_STA_REG, to check whether
> external low speed oscillator is working correctly.
>
> This patch adds support for enabling LOSC when necessary:
>
> - during reparenting
> - when probing the clock
>
> H6 also has capacbility to automatically reparent RTC clock from
> external crystal oscillator, to internal RC oscillator, if external
> oscillator fails. This is enabled by default. Disable it during
> probe.
>
> Signed-off-by: Ondrej Jirman <megous-5qf/QAjKc83QT0dZR+AlfA@public.gmane.org>
> ---
> drivers/rtc/rtc-sun6i.c | 40 ++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 38 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
> index 11f56de52179..7375a530c565 100644
> --- a/drivers/rtc/rtc-sun6i.c
> +++ b/drivers/rtc/rtc-sun6i.c
> @@ -41,9 +41,11 @@
> /* Control register */
> #define SUN6I_LOSC_CTRL 0x0000
> #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16)
> +#define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15)
Manual says bit 14? Or is this different from LOSC_AUTO_SWT_EN?
The rest looks ok.
ChenYu
^ permalink raw reply
* [PATCH 3/3] pinctrl: mvebu: add additional variant for standalone CP115
From: Miquel Raynal @ 2019-08-05 10:16 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai, linux-gpio,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
Linus Walleij, linux-arm-kernel
In-Reply-To: <20190805101607.29811-1-miquel.raynal@bootlin.com>
From: Grzegorz Jaszczyk <jaz@semihalf.com>
With CP115 standalone modules, all MPP configuration are
possible. Handle this new possibility thanks to the new
"marvell,cp115-standalone-pinctrl" compatible property.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
[<miquel.raynal@bootlin.com>: mention the new compatible in the
commit log]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/pinctrl/mvebu/pinctrl-armada-cp110.c | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
index 85ade9761885..17491b27e487 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
@@ -32,6 +32,7 @@ enum {
V_ARMADA_7K = BIT(0),
V_ARMADA_8K_CPM = BIT(1),
V_ARMADA_8K_CPS = BIT(2),
+ V_CP115_STANDALONE = BIT(3),
V_ARMADA_7K_8K_CPM = (V_ARMADA_7K | V_ARMADA_8K_CPM),
V_ARMADA_7K_8K_CPS = (V_ARMADA_7K | V_ARMADA_8K_CPS),
};
@@ -614,6 +615,10 @@ static const struct of_device_id armada_cp110_pinctrl_of_match[] = {
.compatible = "marvell,armada-8k-cps-pinctrl",
.data = (void *) V_ARMADA_8K_CPS,
},
+ {
+ .compatible = "marvell,cp115-standalone-pinctrl",
+ .data = (void *) V_CP115_STANDALONE,
+ },
{ },
};
@@ -655,16 +660,20 @@ static int armada_cp110_pinctrl_probe(struct platform_device *pdev)
switch (i) {
case 0 ... 31:
- mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPS);
+ mvebu_pinctrl_assign_variant(m, (V_ARMADA_7K_8K_CPS |
+ V_CP115_STANDALONE));
break;
case 32 ... 38:
- mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPM);
+ mvebu_pinctrl_assign_variant(m, (V_ARMADA_7K_8K_CPM |
+ V_CP115_STANDALONE));
break;
case 39 ... 43:
- mvebu_pinctrl_assign_variant(m, V_ARMADA_8K_CPM);
+ mvebu_pinctrl_assign_variant(m, (V_ARMADA_8K_CPM |
+ V_CP115_STANDALONE));
break;
case 44 ... 62:
- mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPM);
+ mvebu_pinctrl_assign_variant(m, (V_ARMADA_7K_8K_CPM |
+ V_CP115_STANDALONE));
break;
}
}
--
2.20.1
^ permalink raw reply related
* [PATCH 2/3] dt-bindings: cp110: document the new CP115 pinctrl compatible
From: Miquel Raynal @ 2019-08-05 10:16 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai, linux-gpio,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
Linus Walleij, linux-arm-kernel
In-Reply-To: <20190805101607.29811-1-miquel.raynal@bootlin.com>
From: Grzegorz Jaszczyk <jaz@semihalf.com>
A new compatible is going to be used for Armada CP115 pinctrl block,
document it.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
[<miquel.raynal@bootlin.com>: split the documentation out of the
driver commit]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../bindings/arm/marvell/cp110-system-controller.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt
index 4db4119a6d19..f982a8ed9396 100644
--- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt
@@ -78,8 +78,8 @@ Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
Required properties:
-- compatible: "marvell,armada-7k-pinctrl",
- "marvell,armada-8k-cpm-pinctrl" or "marvell,armada-8k-cps-pinctrl"
+- compatible: "marvell,armada-7k-pinctrl", "marvell,armada-8k-cpm-pinctrl",
+ "marvell,armada-8k-cps-pinctrl" or "marvell,cp115-standalone-pinctrl"
depending on the specific variant of the SoC being used.
Available mpp pins/groups and functions:
--
2.20.1
^ permalink raw reply related
* [PATCH 1/3] pinctrl: mvebu: Add CP110 missing pin functionality
From: Miquel Raynal @ 2019-08-05 10:16 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai, linux-gpio,
Thomas Petazzoni, Miquel Raynal, Konstantin Porotchkin,
Stefan Chulski, Marcin Wojtas, Linus Walleij, linux-arm-kernel
In-Reply-To: <20190805101607.29811-1-miquel.raynal@bootlin.com>
From: Konstantin Porotchkin <kostap@marvell.com>
Add missing definition for function 0xe on CP-110 MPP-62.
The pin function is Data Strobe for SDIO interface.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/pinctrl/mvebu/pinctrl-armada-cp110.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
index 584952b2ba47..85ade9761885 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
@@ -597,7 +597,8 @@ static struct mvebu_mpp_mode armada_cp110_mpp_modes[] = {
MPP_FUNCTION(7, "uart0", "rxd"),
MPP_FUNCTION(8, "uart2", "rxd"),
MPP_FUNCTION(9, "sata0", "present_act"),
- MPP_FUNCTION(10, "ge", "mdc")),
+ MPP_FUNCTION(10, "ge", "mdc"),
+ MPP_FUNCTION(14, "sdio", "ds")),
};
static const struct of_device_id armada_cp110_pinctrl_of_match[] = {
--
2.20.1
^ permalink raw reply related
* [PATCH 0/3] CP115 pinctrl support
From: Miquel Raynal @ 2019-08-05 10:16 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai, linux-gpio,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
Linus Walleij, linux-arm-kernel
Hello,
This is the second batch of changes (out of three) to support the brand
new Marvell CN9130 SoCs which are made of one AP807 and one CP115.
We add a new compatible (and the relevant support in the pinctrl
driver) before the addition in batch 3/3 of CN9130 SoCs DT using it.
1st batch was clocks support and is independent from this one.
Thanks,
Miquèl
Grzegorz Jaszczyk (2):
dt-bindings: cp110: document the new CP115 pinctrl compatible
pinctrl: mvebu: add additional variant for standalone CP115
Konstantin Porotchkin (1):
pinctrl: mvebu: Add CP110 missing pin functionality
.../arm/marvell/cp110-system-controller.txt | 4 ++--
drivers/pinctrl/mvebu/pinctrl-armada-cp110.c | 20 ++++++++++++++-----
2 files changed, 17 insertions(+), 7 deletions(-)
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v8 10/11] usb: common: add USB GPIO based connection detection driver
From: Linus Walleij @ 2019-08-05 10:10 UTC (permalink / raw)
To: Chunfeng Yun
Cc: Rob Herring, Greg Kroah-Hartman, Biju Das, Mark Rutland,
Matthias Brugger, Adam Thomson, Li Jun, Badhri Jagan Sridharan,
Heikki Krogerus, Hans de Goede, Andy Shevchenko, Min Guo,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org, linux-usb, Linux ARM, ARM/Mediatek
In-Reply-To: <1563958245-6321-11-git-send-email-chunfeng.yun@mediatek.com>
On Wed, Jul 24, 2019 at 10:51 AM Chunfeng Yun <chunfeng.yun@mediatek.com> wrote:
> Due to the requirement of usb-connector.txt binding, the old way
> using extcon to support USB Dual-Role switch is now deprecated
> when use Type-B connector.
> This patch introduces a driver of Type-B connector which typically
> uses an input GPIO to detect USB ID pin, and try to replace the
> function provided by extcon-usb-gpio driver
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> Tested-by: Nagarjuna Kristam <nkristam@nvidia.com>
> ---
> v8 changes:
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v8 02/11] dt-bindings: connector: add optional properties for Type-B
From: Linus Walleij @ 2019-08-05 10:09 UTC (permalink / raw)
To: Chunfeng Yun
Cc: Rob Herring, Greg Kroah-Hartman, Biju Das, Mark Rutland,
Matthias Brugger, Adam Thomson, Li Jun, Badhri Jagan Sridharan,
Heikki Krogerus, Hans de Goede, Andy Shevchenko, Min Guo,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org, linux-usb, Linux ARM, ARM/Mediatek
In-Reply-To: <1563958245-6321-3-git-send-email-chunfeng.yun@mediatek.com>
On Wed, Jul 24, 2019 at 10:51 AM Chunfeng Yun <chunfeng.yun@mediatek.com> wrote:
> Add id-gpios, vbus-gpios, vbus-supply and pinctrl properties for
> usb-b-connector
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> v8 no changes
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v8 03/11] dt-bindings: usb: add binding for USB GPIO based connection detection driver
From: Linus Walleij @ 2019-08-05 10:08 UTC (permalink / raw)
To: Chunfeng Yun
Cc: Rob Herring, Greg Kroah-Hartman, Biju Das, Mark Rutland,
Matthias Brugger, Adam Thomson, Li Jun, Badhri Jagan Sridharan,
Heikki Krogerus, Hans de Goede, Andy Shevchenko, Min Guo,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org, linux-usb, Linux ARM, ARM/Mediatek
In-Reply-To: <1563958245-6321-4-git-send-email-chunfeng.yun@mediatek.com>
On Wed, Jul 24, 2019 at 10:51 AM Chunfeng Yun <chunfeng.yun@mediatek.com> wrote:
> It's used to support dual role switch via GPIO when use Type-B
> receptacle, typically the USB ID pin is connected to an input
> GPIO, and also used to enable/disable device when the USB Vbus
> pin is connected to an input GPIO.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v8 changes:
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
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