* [PATCH v2 2/7] dt-bindings: firmware: scm: re-order compatible list
From: Sibi Sankar @ 2019-08-07 7:09 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, vkoul, aneela
Cc: mark.rutland, agross, linux-kernel, linux-arm-msm, devicetree,
jassisinghbrar, clew, Sibi Sankar
In-Reply-To: <20190807070957.30655-1-sibis@codeaurora.org>
re-order compatible list to maintain sort order.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
index 41f133a4e2fa7..d19be836df533 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
@@ -9,13 +9,13 @@ Required properties:
- compatible: must contain one of the following:
* "qcom,scm-apq8064"
* "qcom,scm-apq8084"
+ * "qcom,scm-ipq4019"
* "qcom,scm-msm8660"
* "qcom,scm-msm8916"
* "qcom,scm-msm8960"
* "qcom,scm-msm8974"
* "qcom,scm-msm8996"
* "qcom,scm-msm8998"
- * "qcom,scm-ipq4019"
* "qcom,scm-sdm845"
and:
* "qcom,scm"
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v2 3/7] dt-bindings: firmware: scm: Add SM8150 and SC7180 support
From: Sibi Sankar @ 2019-08-07 7:09 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, vkoul, aneela
Cc: mark.rutland, agross, linux-kernel, linux-arm-msm, devicetree,
jassisinghbrar, clew, Sibi Sankar
In-Reply-To: <20190807070957.30655-1-sibis@codeaurora.org>
Add compatible for SM8150 and SC7180 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
index d19be836df533..3f29ea04b5fe9 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
@@ -16,7 +16,9 @@ Required properties:
* "qcom,scm-msm8974"
* "qcom,scm-msm8996"
* "qcom,scm-msm8998"
+ * "qcom,scm-sc7180"
* "qcom,scm-sdm845"
+ * "qcom,scm-sm8150"
and:
* "qcom,scm"
- clocks: Specifies clocks needed by the SCM interface, if any:
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v2 4/7] dt-bindings: mailbox: Add APSS shared for SM8150 and SC7180 SoCs
From: Sibi Sankar @ 2019-08-07 7:09 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, vkoul, aneela
Cc: mark.rutland, agross, linux-kernel, linux-arm-msm, devicetree,
jassisinghbrar, clew, Sibi Sankar
In-Reply-To: <20190807070957.30655-1-sibis@codeaurora.org>
Add SM8150 and SC7180 APSS shared to the list of possible bindings.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
.../devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
index 1232fc9fc709c..e5a541a693e1b 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
@@ -12,7 +12,9 @@ platforms.
"qcom,msm8996-apcs-hmss-global"
"qcom,msm8998-apcs-hmss-global"
"qcom,qcs404-apcs-apps-global"
+ "qcom,sc7180-apss-shared"
"qcom,sdm845-apss-shared"
+ "qcom,sm8150-apss-shared"
- reg:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v2 5/7] mailbox: qcom: Add support for Qualcomm SM8150 and SC7180 SoCs
From: Sibi Sankar @ 2019-08-07 7:09 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, vkoul, aneela
Cc: mark.rutland, agross, linux-kernel, linux-arm-msm, devicetree,
jassisinghbrar, clew, Sibi Sankar
In-Reply-To: <20190807070957.30655-1-sibis@codeaurora.org>
Add the corresponding APSS shared offset for SM8150 and SC7180 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index 705e17a5479cc..2dfd288fe720d 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -118,7 +118,9 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {
{ .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 },
{ .compatible = "qcom,msm8998-apcs-hmss-global", .data = (void *)8 },
{ .compatible = "qcom,qcs404-apcs-apps-global", .data = (void *)8 },
+ { .compatible = "qcom,sc7180-apss-shared", .data = (void *)12 },
{ .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 },
+ { .compatible = "qcom,sm8150-apss-shared", .data = (void *)12 },
{}
};
MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v2 6/7] dt-bindings: soc: qcom: aoss: Add SM8150 and SC7180 support
From: Sibi Sankar @ 2019-08-07 7:09 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, vkoul, aneela
Cc: mark.rutland, agross, linux-kernel, linux-arm-msm, devicetree,
jassisinghbrar, clew, Sibi Sankar
In-Reply-To: <20190807070957.30655-1-sibis@codeaurora.org>
Add SM8150 and SC7180 AOSS QMP to the list of possible bindings.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
index 954ffee0a9c45..4fc571e78f018 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
@@ -15,7 +15,10 @@ power-domains.
- compatible:
Usage: required
Value type: <string>
- Definition: must be "qcom,sdm845-aoss-qmp"
+ Definition: must be one of:
+ "qcom,sc7180-aoss-qmp"
+ "qcom,sdm845-aoss-qmp"
+ "qcom,sm8150-aoss-qmp"
- reg:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v2 7/7] soc: qcom: aoss: Add AOSS QMP support
From: Sibi Sankar @ 2019-08-07 7:09 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, vkoul, aneela
Cc: mark.rutland, agross, linux-kernel, linux-arm-msm, devicetree,
jassisinghbrar, clew, Sibi Sankar
In-Reply-To: <20190807070957.30655-1-sibis@codeaurora.org>
Add AOSS QMP support for SM8150 and SC7180 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/soc/qcom/qcom_aoss.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c
index 5f885196f4d0f..6ae813837b74b 100644
--- a/drivers/soc/qcom/qcom_aoss.c
+++ b/drivers/soc/qcom/qcom_aoss.c
@@ -461,7 +461,9 @@ static int qmp_remove(struct platform_device *pdev)
}
static const struct of_device_id qmp_dt_match[] = {
+ { .compatible = "qcom,sc7180-aoss-qmp", },
{ .compatible = "qcom,sdm845-aoss-qmp", },
+ { .compatible = "qcom,sm8150-aoss-qmp", },
{}
};
MODULE_DEVICE_TABLE(of, qmp_dt_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH 0/8] soc: ti: Add OMAP PRM driver
From: Tero Kristo @ 2019-08-07 7:48 UTC (permalink / raw)
To: ssantosh, linux-arm-kernel, linux-omap, robh+dt; +Cc: tony, devicetree
Hi,
This series adds OMAP PRM driver which initially supports only reset
handling. Later on, power domain support can be added to this to get
rid of the current OMAP power domain handling code which resides
under the mach-omap2 platform directory. Initially, reset data is
added for AM3, OMAP4 and DRA7 SoCs.
I've been testing the reset handling logic with OMAP remoteproc
driver which has been converted to use generic reset framework. This
part is a work in progress, so will be posting patches from that part
later on.
-Tero
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply
* [PATCH 1/8] dt-bindings: omap: add new binding for PRM instances
From: Tero Kristo @ 2019-08-07 7:48 UTC (permalink / raw)
To: ssantosh, linux-arm-kernel, linux-omap, robh+dt; +Cc: tony, devicetree
In-Reply-To: <1565164139-21886-1-git-send-email-t-kristo@ti.com>
Add new binding for OMAP PRM (Power and Reset Manager) instances. Each
of these will act as a power domain controller and potentially as a reset
provider.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/arm/omap/prm-inst.txt | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/omap/prm-inst.txt
diff --git a/Documentation/devicetree/bindings/arm/omap/prm-inst.txt b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt
new file mode 100644
index 0000000..e0ae87b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt
@@ -0,0 +1,24 @@
+OMAP PRM instance bindings
+
+Power and Reset Manager is an IP block on OMAP family of devices which
+handle the power domains and their current state, and provide reset
+handling for the domains and/or separate IP blocks under the power domain
+hierarchy.
+
+Required properties:
+- compatible: Must be one of:
+ "ti,am3-prm-inst"
+ "ti,am4-prm-inst"
+ "ti,omap4-prm-inst"
+ "ti,omap5-prm-inst"
+ "ti,dra7-prm-inst"
+- reg: Contains PRM instance register address range
+ (base address and length)
+
+Example:
+
+prm_dsp2: prm@1b00 {
+ compatible = "ti,dra7-prm-inst";
+ reg = <0x1b00 0x40>;
+ #reset-cells = <1>;
+};
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related
* [PATCH 2/8] soc: ti: add initial PRM driver with reset control support
From: Tero Kristo @ 2019-08-07 7:48 UTC (permalink / raw)
To: ssantosh, linux-arm-kernel, linux-omap, robh+dt; +Cc: tony, devicetree
In-Reply-To: <1565164139-21886-1-git-send-email-t-kristo@ti.com>
Add initial PRM (Power and Reset Management) driver for TI OMAP class
SoCs. Initially this driver only supports reset control, but can be
extended to support rest of the functionality, like powerdomain
control, PRCM irq support etc.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/Kconfig | 1 +
drivers/soc/ti/Makefile | 1 +
drivers/soc/ti/omap_prm.c | 216 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 218 insertions(+)
create mode 100644 drivers/soc/ti/omap_prm.c
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index fdb6743..42ad063 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -109,6 +109,7 @@ config ARCH_OMAP2PLUS
select TI_SYSC
select OMAP_IRQCHIP
select CLKSRC_TI_32K
+ select RESET_CONTROLLER
help
Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile
index b3868d3..788b5cd 100644
--- a/drivers/soc/ti/Makefile
+++ b/drivers/soc/ti/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_KEYSTONE_NAVIGATOR_QMSS) += knav_qmss.o
knav_qmss-y := knav_qmss_queue.o knav_qmss_acc.o
obj-$(CONFIG_KEYSTONE_NAVIGATOR_DMA) += knav_dma.o
obj-$(CONFIG_AMX3_PM) += pm33xx.o
+obj-$(CONFIG_ARCH_OMAP2PLUS) += omap_prm.o
obj-$(CONFIG_WKUP_M3_IPC) += wkup_m3_ipc.o
obj-$(CONFIG_TI_SCI_PM_DOMAINS) += ti_sci_pm_domains.o
obj-$(CONFIG_TI_SCI_INTA_MSI_DOMAIN) += ti_sci_inta_msi.o
diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c
new file mode 100644
index 0000000..7c89eb8
--- /dev/null
+++ b/drivers/soc/ti/omap_prm.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * OMAP2+ PRM driver
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo <t-kristo@ti.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/delay.h>
+
+struct omap_rst_map {
+ s8 rst;
+ s8 st;
+};
+
+struct omap_prm_data {
+ u32 base;
+ const char *name;
+ u16 pwstctrl;
+ u16 pwstst;
+ u16 rstctl;
+ u16 rstst;
+ struct omap_rst_map *rstmap;
+ u8 flags;
+};
+
+struct omap_prm {
+ const struct omap_prm_data *data;
+ void __iomem *base;
+};
+
+struct omap_reset_data {
+ struct reset_controller_dev rcdev;
+ struct omap_prm *prm;
+};
+
+#define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev)
+
+#define OMAP_MAX_RESETS 8
+#define OMAP_RESET_MAX_WAIT 10000
+
+#define OMAP_PRM_NO_RSTST BIT(0)
+
+static const struct of_device_id omap_prm_id_table[] = {
+ { },
+};
+
+static int omap_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct omap_reset_data *reset = to_omap_reset_data(rcdev);
+ u32 v;
+
+ v = readl_relaxed(reset->prm->base + reset->prm->data->rstst);
+ v &= 1 << id;
+ v >>= id;
+
+ return v;
+}
+
+static int omap_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct omap_reset_data *reset = to_omap_reset_data(rcdev);
+ u32 v;
+
+ /* assert the reset control line */
+ v = readl_relaxed(reset->prm->base + reset->prm->data->rstctl);
+ v |= 1 << id;
+ writel_relaxed(v, reset->prm->base + reset->prm->data->rstctl);
+
+ return 0;
+}
+
+static int omap_reset_get_st_bit(struct omap_reset_data *reset,
+ unsigned long id)
+{
+ struct omap_rst_map *map = reset->prm->data->rstmap;
+
+ while (map && map->rst >= 0) {
+ if (map->rst == id)
+ return map->st;
+
+ map++;
+ }
+
+ return id;
+}
+
+/*
+ * Note that status will not change until clocks are on, and clocks cannot be
+ * enabled until reset is deasserted. Consumer drivers must check status
+ * separately after enabling clocks.
+ */
+static int omap_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct omap_reset_data *reset = to_omap_reset_data(rcdev);
+ u32 v;
+ int st_bit = id;
+ bool has_rstst;
+
+ /* check the current status to avoid de-asserting the line twice */
+ v = readl_relaxed(reset->prm->base + reset->prm->data->rstctl);
+ if (!(v & BIT(id)))
+ return -EEXIST;
+
+ has_rstst = !(reset->prm->data->flags & OMAP_PRM_NO_RSTST);
+
+ if (has_rstst) {
+ st_bit = omap_reset_get_st_bit(reset, id);
+
+ /* Clear the reset status by writing 1 to the status bit */
+ v = readl_relaxed(reset->prm->base + reset->prm->data->rstst);
+ v |= 1 << st_bit;
+ writel_relaxed(v, reset->prm->base + reset->prm->data->rstst);
+ }
+
+ /* de-assert the reset control line */
+ v = readl_relaxed(reset->prm->base + reset->prm->data->rstctl);
+ v &= ~(1 << id);
+ writel_relaxed(v, reset->prm->base + reset->prm->data->rstctl);
+
+ return 0;
+}
+
+static const struct reset_control_ops omap_reset_ops = {
+ .assert = omap_reset_assert,
+ .deassert = omap_reset_deassert,
+ .status = omap_reset_status,
+};
+
+static int omap_prm_reset_probe(struct platform_device *pdev,
+ struct omap_prm *prm)
+{
+ struct omap_reset_data *reset;
+
+ /*
+ * Check if we have resets. If either rstctl or rstst is
+ * non-zero, we have reset registers in place. Additionally
+ * the flag OMAP_PRM_NO_RSTST implies that we have resets.
+ */
+ if (!prm->data->rstctl && !prm->data->rstst &&
+ !(prm->data->flags & OMAP_PRM_NO_RSTST))
+ return 0;
+
+ reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
+ if (!reset)
+ return -ENOMEM;
+
+ reset->rcdev.owner = THIS_MODULE;
+ reset->rcdev.ops = &omap_reset_ops;
+ reset->rcdev.of_node = pdev->dev.of_node;
+ reset->rcdev.nr_resets = OMAP_MAX_RESETS;
+
+ reset->prm = prm;
+
+ return devm_reset_controller_register(&pdev->dev, &reset->rcdev);
+}
+
+static int omap_prm_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ const struct omap_prm_data *data;
+ struct omap_prm *prm;
+ const struct of_device_id *match;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
+
+ match = of_match_device(omap_prm_id_table, &pdev->dev);
+ if (!match)
+ return -ENOTSUPP;
+
+ prm = devm_kzalloc(&pdev->dev, sizeof(*prm), GFP_KERNEL);
+ if (!prm)
+ return -ENOMEM;
+
+ data = match->data;
+
+ while (data->base != res->start) {
+ if (!data->base)
+ return -EINVAL;
+ data++;
+ }
+
+ prm->data = data;
+
+ prm->base = devm_ioremap_resource(&pdev->dev, res);
+ if (!prm->base)
+ return -ENOMEM;
+
+ return omap_prm_reset_probe(pdev, prm);
+}
+
+static struct platform_driver omap_prm_driver = {
+ .probe = omap_prm_probe,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = omap_prm_id_table,
+ },
+};
+builtin_platform_driver(omap_prm_driver);
+
+MODULE_ALIAS("platform:prm");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("omap2+ prm driver");
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related
* [PATCH 3/8] soc: ti: omap-prm: poll for reset complete during de-assert
From: Tero Kristo @ 2019-08-07 7:48 UTC (permalink / raw)
To: ssantosh, linux-arm-kernel, linux-omap, robh+dt; +Cc: tony, devicetree
In-Reply-To: <1565164139-21886-1-git-send-email-t-kristo@ti.com>
Poll for reset completion status during de-assertion of reset, otherwise
the IP in question might be accessed before it has left reset properly.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/soc/ti/omap_prm.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c
index 7c89eb8..d412af3 100644
--- a/drivers/soc/ti/omap_prm.c
+++ b/drivers/soc/ti/omap_prm.c
@@ -107,6 +107,7 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev,
u32 v;
int st_bit = id;
bool has_rstst;
+ int timeout = 0;
/* check the current status to avoid de-asserting the line twice */
v = readl_relaxed(reset->prm->base + reset->prm->data->rstctl);
@@ -129,6 +130,22 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev,
v &= ~(1 << id);
writel_relaxed(v, reset->prm->base + reset->prm->data->rstctl);
+ if (!has_rstst)
+ return 0;
+
+ /* wait for the status to be set */
+ while (1) {
+ v = readl_relaxed(reset->prm->base + reset->prm->data->rstst);
+ v &= 1 << st_bit;
+ if (v)
+ break;
+ timeout++;
+ if (timeout > OMAP_RESET_MAX_WAIT)
+ return -EBUSY;
+
+ udelay(1);
+ }
+
return 0;
}
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related
* [PATCH 4/8] soc: ti: omap-prm: add support for denying idle for reset clockdomain
From: Tero Kristo @ 2019-08-07 7:48 UTC (permalink / raw)
To: ssantosh, linux-arm-kernel, linux-omap, robh+dt; +Cc: tony, devicetree
In-Reply-To: <1565164139-21886-1-git-send-email-t-kristo@ti.com>
TI SoCs hardware reset signals require the parent clockdomain to be
in force wakeup mode while de-asserting the reset, otherwise it may
never complete. To support this, add pdata hooks to control the
clockdomain directly.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/soc/ti/omap_prm.c | 32 ++++++++++++++++++++++++++++----
include/linux/platform_data/ti-prm.h | 21 +++++++++++++++++++++
2 files changed, 49 insertions(+), 4 deletions(-)
create mode 100644 include/linux/platform_data/ti-prm.h
diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c
index d412af3..870515e3 100644
--- a/drivers/soc/ti/omap_prm.c
+++ b/drivers/soc/ti/omap_prm.c
@@ -16,6 +16,8 @@
#include <linux/reset-controller.h>
#include <linux/delay.h>
+#include <linux/platform_data/ti-prm.h>
+
struct omap_rst_map {
s8 rst;
s8 st;
@@ -24,6 +26,7 @@ struct omap_rst_map {
struct omap_prm_data {
u32 base;
const char *name;
+ const char *clkdm_name;
u16 pwstctrl;
u16 pwstst;
u16 rstctl;
@@ -40,6 +43,8 @@ struct omap_prm {
struct omap_reset_data {
struct reset_controller_dev rcdev;
struct omap_prm *prm;
+ struct clockdomain *clkdm;
+ struct device *dev;
};
#define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev)
@@ -108,6 +113,8 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev,
int st_bit = id;
bool has_rstst;
int timeout = 0;
+ struct ti_prm_platform_data *pdata = dev_get_platdata(reset->dev);
+ int ret = 0;
/* check the current status to avoid de-asserting the line twice */
v = readl_relaxed(reset->prm->base + reset->prm->data->rstctl);
@@ -125,13 +132,16 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev,
writel_relaxed(v, reset->prm->base + reset->prm->data->rstst);
}
+ if (pdata->clkdm_deny_idle && reset->clkdm)
+ pdata->clkdm_deny_idle(reset->clkdm);
+
/* de-assert the reset control line */
v = readl_relaxed(reset->prm->base + reset->prm->data->rstctl);
v &= ~(1 << id);
writel_relaxed(v, reset->prm->base + reset->prm->data->rstctl);
if (!has_rstst)
- return 0;
+ goto exit;
/* wait for the status to be set */
while (1) {
@@ -140,13 +150,19 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev,
if (v)
break;
timeout++;
- if (timeout > OMAP_RESET_MAX_WAIT)
- return -EBUSY;
+ if (timeout > OMAP_RESET_MAX_WAIT) {
+ ret = -EBUSY;
+ goto exit;
+ }
udelay(1);
}
- return 0;
+exit:
+ if (pdata->clkdm_allow_idle && reset->clkdm)
+ pdata->clkdm_allow_idle(reset->clkdm);
+
+ return ret;
}
static const struct reset_control_ops omap_reset_ops = {
@@ -159,6 +175,8 @@ static int omap_prm_reset_probe(struct platform_device *pdev,
struct omap_prm *prm)
{
struct omap_reset_data *reset;
+ struct ti_prm_platform_data *pdata = dev_get_platdata(&pdev->dev);
+ char buf[32];
/*
* Check if we have resets. If either rstctl or rstst is
@@ -177,9 +195,15 @@ static int omap_prm_reset_probe(struct platform_device *pdev,
reset->rcdev.ops = &omap_reset_ops;
reset->rcdev.of_node = pdev->dev.of_node;
reset->rcdev.nr_resets = OMAP_MAX_RESETS;
+ reset->dev = &pdev->dev;
reset->prm = prm;
+ sprintf(buf, "%s_clkdm", prm->data->clkdm_name ? prm->data->clkdm_name :
+ prm->data->name);
+
+ reset->clkdm = pdata->clkdm_lookup(buf);
+
return devm_reset_controller_register(&pdev->dev, &reset->rcdev);
}
diff --git a/include/linux/platform_data/ti-prm.h b/include/linux/platform_data/ti-prm.h
new file mode 100644
index 0000000..28154c3
--- /dev/null
+++ b/include/linux/platform_data/ti-prm.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * TI PRM (Power & Reset Manager) platform data
+ *
+ * Copyright (C) 2019 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ */
+
+#ifndef _LINUX_PLATFORM_DATA_TI_PRM_H
+#define _LINUX_PLATFORM_DATA_TI_PRM_H
+
+struct clockdomain;
+
+struct ti_prm_platform_data {
+ void (*clkdm_deny_idle)(struct clockdomain *clkdm);
+ void (*clkdm_allow_idle)(struct clockdomain *clkdm);
+ struct clockdomain * (*clkdm_lookup)(const char *name);
+};
+
+#endif /* _LINUX_PLATFORM_DATA_TI_PRM_H */
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related
* [PATCH 5/8] soc: ti: omap-prm: add omap4 PRM data
From: Tero Kristo @ 2019-08-07 7:48 UTC (permalink / raw)
To: ssantosh, linux-arm-kernel, linux-omap, robh+dt; +Cc: tony, devicetree
In-Reply-To: <1565164139-21886-1-git-send-email-t-kristo@ti.com>
Add PRM data for omap4 family of SoCs.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/soc/ti/omap_prm.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c
index 870515e3..9b8d5945 100644
--- a/drivers/soc/ti/omap_prm.c
+++ b/drivers/soc/ti/omap_prm.c
@@ -54,7 +54,27 @@ struct omap_reset_data {
#define OMAP_PRM_NO_RSTST BIT(0)
+struct omap_prm_data omap4_prm_data[] = {
+ { .name = "mpu", .base = 0x4a306300, .pwstst = 0x4 },
+ { .name = "tesla", .base = 0x4a306400, .pwstst = 0x4, .rstctl = 0x10, .rstst = 0x14 },
+ { .name = "abe", .base = 0x4a306500, .pwstst = 0x4 },
+ { .name = "always_on_core", .base = 0x4a306600, .pwstst = 0x4 },
+ { .name = "core", .base = 0x4a306700, .pwstst = 0x4, .rstctl = 0x210, .rstst = 0x214 },
+ { .name = "ivahd", .base = 0x4a306f00, .pwstst = 0x4, .rstctl = 0x10, .rstst = 0x14 },
+ { .name = "cam", .base = 0x4a307000, .pwstst = 0x4 },
+ { .name = "dss", .base = 0x4a307100, .pwstst = 0x4 },
+ { .name = "gfx", .base = 0x4a307200, .pwstst = 0x4 },
+ { .name = "l3init", .base = 0x4a307300, .pwstst = 0x4 },
+ { .name = "l4per", .base = 0x4a307400, .pwstst = 0x4 },
+ { .name = "cefuse", .base = 0x4a307600, .pwstst = 0x4 },
+ { .name = "wkup", .base = 0x4a307700, .pwstst = 0x4 },
+ { .name = "emu", .base = 0x4a307900, .pwstst = 0x4 },
+ { .name = "device", .base = 0x4a307b00, .rstctl = 0x0, .rstst = 0x4 },
+ { },
+};
+
static const struct of_device_id omap_prm_id_table[] = {
+ { .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data },
{ },
};
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related
* [PATCH 6/8] soc: ti: omap_prm: add data for am33xx
From: Tero Kristo @ 2019-08-07 7:48 UTC (permalink / raw)
To: ssantosh, linux-arm-kernel, linux-omap, robh+dt; +Cc: tony, devicetree
In-Reply-To: <1565164139-21886-1-git-send-email-t-kristo@ti.com>
Add PRM instance data for AM33xx SoC. Includes some basic register
definitions and reset data for now.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/soc/ti/omap_prm.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c
index 9b8d5945..fadfc7f 100644
--- a/drivers/soc/ti/omap_prm.c
+++ b/drivers/soc/ti/omap_prm.c
@@ -73,8 +73,25 @@ struct omap_prm_data omap4_prm_data[] = {
{ },
};
+struct omap_rst_map am3_wkup_rst_map[] = {
+ { .rst = 3, .st = 5 },
+ { .rst = -1 },
+};
+
+struct omap_prm_data am3_prm_data[] = {
+ { .name = "per", .base = 0x44e00c00, .pwstctrl = 0xc, .pwstst = 0x8, .flags = OMAP_PRM_NO_RSTST },
+ { .name = "wkup", .base = 0x44e00d00, .pwstctrl = 0x4, .pwstst = 0x8, .rstst = 0xc, .rstmap = am3_wkup_rst_map },
+ { .name = "mpu", .base = 0x44e00e00, .pwstst = 0x4 },
+ { .name = "device", .base = 0x44e00f00, .rstctl = 0x0, .rstst = 0x8 },
+ { .name = "rtc", .base = 0x44e01000, .pwstst = 0x4 },
+ { .name = "gfx", .base = 0x44e01100, .pwstst = 0x10, .rstctl = 0x4, .rstst = 0x14 },
+ { .name = "cefuse", .base = 0x44e01200, .pwstst = 0x4 },
+ { },
+};
+
static const struct of_device_id omap_prm_id_table[] = {
{ .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data },
+ { .compatible = "ti,am3-prm-inst", .data = am3_prm_data },
{ },
};
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related
* [PATCH 7/8] soc: ti: omap-prm: add dra7 PRM data
From: Tero Kristo @ 2019-08-07 7:48 UTC (permalink / raw)
To: ssantosh, linux-arm-kernel, linux-omap, robh+dt; +Cc: tony, devicetree
In-Reply-To: <1565164139-21886-1-git-send-email-t-kristo@ti.com>
Add PRM data for dra7 family of SoCs.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/soc/ti/omap_prm.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c
index fadfc7f..05b7749 100644
--- a/drivers/soc/ti/omap_prm.c
+++ b/drivers/soc/ti/omap_prm.c
@@ -73,6 +73,31 @@ struct omap_prm_data omap4_prm_data[] = {
{ },
};
+static struct omap_prm_data dra7_prm_data[] = {
+ { .name = "mpu", .base = 0x4ae06300, .pwstst = 0x4 },
+ { .name = "dsp1", .base = 0x4ae06400, .pwstst = 0x4, .rstctl = 0x10, .rstst = 0x14 },
+ { .name = "ipu", .base = 0x4ae06500, .pwstst = 0x4, .rstctl = 0x10, .rstst = 0x14, .clkdm_name = "ipu1" },
+ { .name = "coreaon", .base = 0x4ae06628, .pwstst = 0x4 },
+ { .name = "core", .base = 0x4ae06700, .pwstst = 0x4, .rstctl = 0x210, .rstst = 0x214, .clkdm_name = "ipu2" },
+ { .name = "iva", .base = 0x4ae06f00, .pwstst = 0x4 },
+ { .name = "cam", .base = 0x4ae07000, .pwstst = 0x4 },
+ { .name = "dss", .base = 0x4ae07100, .pwstst = 0x4 },
+ { .name = "gpu", .base = 0x4ae07200, .pwstst = 0x4 },
+ { .name = "l3init", .base = 0x4ae07300, .pwstst = 0x4, .rstctl = 0x10, .rstst = 0x14 },
+ { .name = "l4per", .base = 0x4ae07400, .pwstst = 0x4 },
+ { .name = "custefuse", .base = 0x4ae07600, .pwstst = 0x4 },
+ { .name = "wkupaon", .base = 0x4ae07724, .pwstst = 0x4 },
+ { .name = "emu", .base = 0x4ae07900, .pwstst = 0x4 },
+ { .name = "dsp2", .base = 0x4ae07b00, .pwstst = 0x4, .rstctl = 0x10, .rstst = 0x14 },
+ { .name = "eve1", .base = 0x4ae07b40, .pwstst = 0x4 },
+ { .name = "eve2", .base = 0x4ae07b80, .pwstst = 0x4 },
+ { .name = "eve3", .base = 0x4ae07bc0, .pwstst = 0x4 },
+ { .name = "eve4", .base = 0x4ae07c00, .pwstst = 0x4 },
+ { .name = "rtc", .base = 0x4ae07c60, .pwstst = 0x4 },
+ { .name = "vpe", .base = 0x4ae07c80, .pwstst = 0x4 },
+ { },
+};
+
struct omap_rst_map am3_wkup_rst_map[] = {
{ .rst = 3, .st = 5 },
{ .rst = -1 },
@@ -91,6 +116,7 @@ struct omap_prm_data am3_prm_data[] = {
static const struct of_device_id omap_prm_id_table[] = {
{ .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data },
+ { .compatible = "ti,dra7-prm-inst", .data = dra7_prm_data },
{ .compatible = "ti,am3-prm-inst", .data = am3_prm_data },
{ },
};
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related
* [PATCH 8/8] ARM: OMAP2+: pdata-quirks: add PRM data for reset support
From: Tero Kristo @ 2019-08-07 7:48 UTC (permalink / raw)
To: ssantosh, linux-arm-kernel, linux-omap, robh+dt; +Cc: tony, devicetree
In-Reply-To: <1565164139-21886-1-git-send-email-t-kristo@ti.com>
The parent clockdomain for reset must be in force wakeup mode, otherwise
the reset may never complete. Add pdata quirks for this purpose for PRM
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/pdata-quirks.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 6c6f8fc..87e2457 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -25,6 +25,7 @@
#include <linux/platform_data/ti-sysc.h>
#include <linux/platform_data/wkup_m3.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <linux/platform_data/ti-prm.h>
#include "clockdomain.h"
#include "common.h"
@@ -565,6 +566,12 @@ void omap_pcs_legacy_init(int irq, void (*rearm)(void))
pcs_pdata.rearm = rearm;
}
+static struct ti_prm_platform_data ti_prm_pdata = {
+ .clkdm_deny_idle = clkdm_deny_idle,
+ .clkdm_allow_idle = clkdm_allow_idle,
+ .clkdm_lookup = clkdm_lookup,
+};
+
/*
* GPIOs for TWL are initialized by the I2C bus and need custom
* handing until DSS has device tree bindings.
@@ -664,6 +671,9 @@ static void __init omap3_mcbsp_init(void) {}
/* Common auxdata */
OF_DEV_AUXDATA("ti,sysc", 0, NULL, &ti_sysc_pdata),
OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata),
+ OF_DEV_AUXDATA("ti,omap4-prm-inst", 0, NULL, &ti_prm_pdata),
+ OF_DEV_AUXDATA("ti,dra7-prm-inst", 0, NULL, &ti_prm_pdata),
+ OF_DEV_AUXDATA("ti,am3-prm-inst", 0, NULL, &ti_prm_pdata),
{ /* sentinel */ },
};
--
1.9.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related
* Re: [PATCH 15/16] net: phy: adin: add ethtool get_stats support
From: Ardelean, Alexandru @ 2019-08-07 7:52 UTC (permalink / raw)
To: andrew@lunn.ch
Cc: davem@davemloft.net, hkallweit1@gmail.com, mark.rutland@arm.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
netdev@vger.kernel.org, f.fainelli@gmail.com, robh+dt@kernel.org
In-Reply-To: <20190806154658.GC20422@lunn.ch>
On Tue, 2019-08-06 at 17:46 +0200, Andrew Lunn wrote:
> [External]
>
> On Tue, Aug 06, 2019 at 07:11:57AM +0000, Ardelean, Alexandru wrote:
> > On Mon, 2019-08-05 at 17:28 +0200, Andrew Lunn wrote:
> > > [External]
> > >
> > > > +struct adin_hw_stat {
> > > > + const char *string;
> > > > +static void adin_get_strings(struct phy_device *phydev, u8 *data)
> > > > +{
> > > > + int i;
> > > > +
> > > > + for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++) {
> > > > + memcpy(data + i * ETH_GSTRING_LEN,
> > > > + adin_hw_stats[i].string, ETH_GSTRING_LEN);
> > >
> > > You define string as a char *. So it will be only as long as it should
> > > be. However memcpy always copies ETH_GSTRING_LEN bytes, doing off the
> > > end of the string and into whatever follows.
> > >
> >
> > hmm, will use strlcpy()
> > i blindedly copied memcpy() from some other driver
>
> Hopefully that driver used const char string[ETH_GSTRING_LEN]. Then a
> memcpy is safe. If not, please let me know what driver you copied.
It was an older Marvell PHY driver (marvell.c) ; in version 4.14.
I used that as an initial work-base for writing the driver.
Then I did the conversion to a newer kernel, then I also had to also consider an older kernel, then I got confused :)
Well, in any case, I am solely considering net-next master (now) for upstreaming this.
>
> > i'm afraid i don't understand about the snapshot feature you are mentioning;
> > i.e. i don't remember seeing it in other chips;
>
> It is frequency done at the MAC layer for statistics. You tell the
> hardware to snapshot all the statistics. It atomically makes a copy of
> all the statistics into a set of registers. These values are then
> static, and consistent between counters. You can read them out knowing
> they are not going to change.
>
> > regarding the danger that stat->reg1 rolls over, i guess that is
> > possible, but it's a bit hard to guard against;
>
> The normal solution is the read the MSB, the LSB and then the MSB
> again. If the MSB value has changed between the two reads, you know a
> roll over has happened, and you need to do it all again.
hmm; ok
I'll try to look for an existing example for this.
>
> Andrew
^ permalink raw reply
* Re: [PATCH 06/16] net: phy: adin: support PHY mode converters
From: Ardelean, Alexandru @ 2019-08-07 8:00 UTC (permalink / raw)
To: andrew@lunn.ch
Cc: davem@davemloft.net, hkallweit1@gmail.com, mark.rutland@arm.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
netdev@vger.kernel.org, f.fainelli@gmail.com, robh+dt@kernel.org
In-Reply-To: <20190806153910.GB20422@lunn.ch>
On Tue, 2019-08-06 at 17:39 +0200, Andrew Lunn wrote:
> [External]
>
> On Tue, Aug 06, 2019 at 06:47:08AM +0000, Ardelean, Alexandru wrote:
> > On Mon, 2019-08-05 at 16:51 +0200, Andrew Lunn wrote:
> > > [External]
> > >
> > > On Mon, Aug 05, 2019 at 07:54:43PM +0300, Alexandru Ardelean wrote:
> > > > Sometimes, the connection between a MAC and PHY is done via a
> > > > mode/interface converter. An example is a GMII-to-RGMII converter, which
> > > > would mean that the MAC operates in GMII mode while the PHY operates in
> > > > RGMII. In this case there is a discrepancy between what the MAC expects &
> > > > what the PHY expects and both need to be configured in their respective
> > > > modes.
> > > >
> > > > Sometimes, this converter is specified via a board/system configuration (in
> > > > the device-tree for example). But, other times it can be left unspecified.
> > > > The use of these converters is common in boards that have FPGA on them.
> > > >
> > > > This patch also adds support for a `adi,phy-mode-internal` property that
> > > > can be used in these (implicit convert) cases. The internal PHY mode will
> > > > be used to specify the correct register settings for the PHY.
> > > >
> > > > `fwnode_handle` is used, since this property may be specified via ACPI as
> > > > well in other setups, but testing has been done in DT context.
> > >
> > > Looking at the patch, you seems to assume phy-mode is what the MAC is
> > > using? That seems rather odd, given the name. It seems like a better
> > > solution would be to add a mac-mode, which the MAC uses to configure
> > > its side of the link. The MAC driver would then implement this
> > > property.
> > >
> >
> > actually, that's a pretty good idea;
> > i guess i was narrow-minded when writing the driver, and got stuck on phy specifics, and forgot about the MAC-side;
> > [ i also catch these design elements when reviewing, but i also seem to miss them when writing stuff sometimes ]
> >
>
> Hi Ardelean
>
> We should also consider the media converter itself. It is passive, or
> does it need a driver. You seems to be considering GMII-to-RGMII. But
> what about RGMII to SGMII? or RGMII to 1000Base-KX etc? Ideally we
> want a generic solution and we need to think about all the parts in
> the system.
In our case the GMII-to-RGMII converter is passive and does not need a driver.
It's an HDL/FPGA block.
There may be other converters that do need a driver.
To be honest, the multitude of possible configurations [given that it's FPGA] can be... a lot.
In one of our cases, specifying the MAC mode to be different than PHY mode [which assumes that there is an implicit
passive media converter in-between] works.
I admit that a generic solution would be nice.
Is it ok if we defer the solution for this drivers/patchset?
If you propose something, I can take a look as part of a different/new discussion.
No guarrantees about how soon it would be implemented.
Thanks
Alex
>
> Andrew
^ permalink raw reply
* Re: [PATCH v4 1/4] RISC-V: Remove per cpu clocksource
From: Daniel Lezcano @ 2019-08-07 8:04 UTC (permalink / raw)
To: Paul Walmsley, Atish Patra
Cc: linux-kernel, Alan Kao, Albert Ou, Anup Patel, devicetree,
Enrico Weigelt, Greg Kroah-Hartman, Johan Hovold, linux-riscv,
Mark Rutland, Palmer Dabbelt, Rob Herring, Thomas Gleixner
In-Reply-To: <alpine.DEB.2.21.9999.1908061437000.13971@viisi.sifive.com>
On 06/08/2019 23:37, Paul Walmsley wrote:
> On Fri, 2 Aug 2019, Atish Patra wrote:
>
>> There is only one clocksource in RISC-V. The boot cpu initializes
>> that clocksource. No need to keep a percpu data structure.
>>
>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
>
> Thanks, queued for v5.3-rc4.
Please, in the future wait for my:
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* next-20190806: arm64: adv7511 3-0039: failed to find dsi host
From: Naresh Kamboju @ 2019-08-07 8:17 UTC (permalink / raw)
To: Linux-Next Mailing List
Cc: Linus Walleij, Hans Verkuil, Hans Verkuil, mchehab, robh+dt,
Mark Rutland, linux-media, open list, devicetree, agross,
david.brown, lkft-triage
arm64 devices dragonboard 410c (QC410E) and hi6220-hikey running Linux
next-20190806 loading modules causing floods of kernel messages.
We have enabled few extra kernel configs for testing.
CONFIG_DRM_I2C_ADV7511=m
CONFIG_DRM_I2C_ADV7511_CEC=y
...
Please find below boot log and config file link.
[ 0.000000] Linux version 5.3.0-rc3-next-20190806 (oe-user@oe-host)
(gcc version 7.3.0 (GCC)) #1 SMP PREEMPT Tue Aug 6 05:49:36 UTC 2019
[ 0.000000] Machine model: Qualcomm Technologies, Inc. APQ 8016 SBC
....
[ 10.051193] adv7511 3-0039: 3-0039 supply dvdd not found, using
dummy regulator
[ 10.051633] adv7511 3-0039: 3-0039 supply pvdd not found, using
dummy regulator
[ 10.076257] adreno 1c00000.gpu: Adding to iommu group 0
[ 10.090929] adv7511 3-0039: 3-0039 supply a2vdd not found, using
dummy regulator
[ 10.101703] msm_mdp 1a01000.mdp: Adding to iommu group 1
[ 10.102563] msm_mdp 1a01000.mdp: No interconnect support may cause
display underflows!
[ 10.139492] adv7511 3-0039: failed to find dsi host
...
[ 33.065744] adv7511 3-0039: failed to find dsi host
[ 33.076721] msm 1a00000.mdss: 1a00000.mdss supply vdd not found,
using dummy regulator
[ 33.078344] msm_mdp 1a01000.mdp: [drm:mdp5_bind [msm]] MDP5 version v1.6
[ 33.083862] msm 1a00000.mdss: bound 1a01000.mdp (ops mdp5_ops [msm])
[ 33.090892] msm_dsi 1a98000.dsi: 1a98000.dsi supply gdsc not found,
using dummy regulator
[ 33.097756] msm_dsi 1a98000.dsi: 1a98000.dsi supply gdsc not found,
using dummy regulator
[ 33.106606] msm_dsi_manager_register: failed to register mipi dsi
host for DSI 0
[ 33.114579] msm 1a00000.mdss: failed to bind 1a98000.dsi (ops
dsi_ops [msm]): -517
[ 33.121263] msm 1a00000.mdss: master bind failed: -517
[ 33.135547] adv7511 3-0039: 3-0039 supply dvdd not found, using
dummy regulator
[ 33.139360] adv7511 3-0039: 3-0039 supply pvdd not found, using
dummy regulator
[ 33.143646] adv7511 3-0039: 3-0039 supply a2vdd not found, using
dummy regulator
Full test log
https://lkft.validation.linaro.org/scheduler/job/860208#L956
metadata:
git branch: master
git repo: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
git commit: 958eb4327c1761c609bde8e9f7c04e9d1c6fbb96
git describe: next-20190806
make_kernelversion: 5.3.0-rc3
kernel-config:
http://snapshots.linaro.org/openembedded/lkft/lkft/sumo/dragonboard-410c/lkft/linux-next/579/config
kernel-defconfig:
http://snapshots.linaro.org/openembedded/lkft/lkft/sumo/dragonboard-410c/lkft/linux-next/579/defconfig
build-location:
http://snapshots.linaro.org/openembedded/lkft/lkft/sumo/dragonboard-410c/lkft/linux-next/579
Best regards
Naresh Kamboju
^ permalink raw reply
* [PATCH v3 00/21] Common patches from downstream development
From: Philippe Schenker @ 2019-08-07 8:26 UTC (permalink / raw)
To: Marcel Ziswiler, Max Krummenacher, stefan@agner.ch,
devicetree@vger.kernel.org, Rob Herring, Shawn Guo, Mark Rutland,
Michal Vokáč, Fabio Estevam
Cc: Philippe Schenker, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, Pengutronix Kernel Team,
NXP Linux Team, Sascha Hauer
This patchset holds some common changes that were never upstreamed.
With latest downstream kernel upgrade, I took the aproach to select
mainline devicetrees and atomically add missing stuff for downstream.
These patches I send here are separated out with changes that also
have a benfit for mainline.
Philippe
Changes in v3:
- Add new commit message from Stefan's proposal on ML
- Fix commit message
- Fix commit title to "...imx6-apalis:..."
- New patch to make use of ARM: dts: imx7-colibri: fix 1.8V/UHS support
Changes in v2:
- Deleted touchrevolution downstream stuff
- Use generic node name
- Better comment
- Changed commit title to '...imx6qdl-apalis:...'
- Deleted touchrevolution downstream stuff
- Use generic node name
- Put a better comment in there
- Commit title
- Removed f0710a, that is downstream only
- Changed to generic node name
- Better comment
Marcel Ziswiler (1):
ARM: dts: imx7-colibri: make sure module supplies are always on
Max Krummenacher (2):
ARM: dts: imx6ull-colibri: reduce v_batt current in power off
ARM: dts: imx6ull: improve can templates
Oleksandr Suvorov (1):
ARM: dts: add recovery for I2C for iMX7
Philippe Schenker (14):
ARM: dts: imx7-colibri: prepare module device tree for FlexCAN
ARM: dts: imx7-colibri: Add sleep mode to ethernet
ARM: dts: imx7-colibri: Add touch controllers
ARM: dts: imx6qdl-colibri: add phy to fec
ARM: dts: imx6qdl-colibri: Add missing pin declaration in iomuxc
ARM: dts: imx6qdl-apalis: Add sleep state to can interfaces
ARM: dts: imx6-apalis: Add touchscreens used on Toradex eval boards
ARM: dts: imx6-colibri: Add missing pinmuxing to Toradex eval board
ARM: dts: imx6ull-colibri: Add sleep mode to fec
ARM: dts: imx6ull-colibri: Add watchdog
ARM: dts: imx6ull-colibri: Add general wakeup key used on Colibri
ARM: dts: imx6/7-colibri: switch dr_mode to otg
ARM: dts: imx6ull-colibri: Add touchscreen used with Eval Board
ARM: dts: imx7-colibri: Add UHS support to eval board
Stefan Agner (3):
ARM: dts: imx7-colibri: disable HS400
ARM: dts: imx7-colibri: add GPIO wakeup key
ARM: dts: imx7-colibri: fix 1.8V/UHS support
arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 39 ++++++
arch/arm/boot/dts/imx6q-apalis-eval.dts | 13 ++
arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts | 13 ++
arch/arm/boot/dts/imx6q-apalis-ixora.dts | 13 ++
arch/arm/boot/dts/imx6qdl-apalis.dtsi | 27 ++++-
arch/arm/boot/dts/imx6qdl-colibri.dtsi | 27 ++++-
.../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 50 ++++++++
.../arm/boot/dts/imx6ull-colibri-nonwifi.dtsi | 2 +-
arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 2 +-
arch/arm/boot/dts/imx6ull-colibri.dtsi | 52 +++++++-
arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi | 49 +++++++-
arch/arm/boot/dts/imx7-colibri.dtsi | 114 ++++++++++++++++--
12 files changed, 373 insertions(+), 28 deletions(-)
--
2.22.0
^ permalink raw reply
* [PATCH v3 01/21] ARM: dts: imx7-colibri: make sure module supplies are always on
From: Philippe Schenker @ 2019-08-07 8:26 UTC (permalink / raw)
To: Marcel Ziswiler, Max Krummenacher, stefan@agner.ch,
devicetree@vger.kernel.org, Rob Herring, Shawn Guo, Mark Rutland,
Michal Vokáč, Fabio Estevam
Cc: Philippe Schenker, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, Pengutronix Kernel Team,
NXP Linux Team, Sascha Hauer
In-Reply-To: <20190807082556.5013-1-philippe.schenker@toradex.com>
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Prevent regulators from being switched off.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/imx7-colibri.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index 895fbde4d433..f1c1971f2160 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -54,6 +54,7 @@
regulator-name = "+V3.3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ regulator-always-on;
};
reg_module_3v3_avdd: regulator-module-3v3-avdd {
@@ -61,6 +62,7 @@
regulator-name = "+V3.3_AVDD_AUDIO";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ regulator-always-on;
};
sound {
--
2.22.0
^ permalink raw reply related
* [PATCH v3 02/21] ARM: dts: imx7-colibri: disable HS400
From: Philippe Schenker @ 2019-08-07 8:26 UTC (permalink / raw)
To: Marcel Ziswiler, Max Krummenacher, stefan@agner.ch,
devicetree@vger.kernel.org, Rob Herring, Shawn Guo, Mark Rutland,
Michal Vokáč, Fabio Estevam
Cc: Stefan Agner, Philippe Schenker, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, Pengutronix Kernel Team,
NXP Linux Team, Sascha Hauer
In-Reply-To: <20190807082556.5013-1-philippe.schenker@toradex.com>
From: Stefan Agner <stefan.agner@toradex.com>
Force HS200 by masking bit 63 of the SDHCI capability register.
The i.MX ESDHC driver uses SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400. With
that the stack checks bit 63 to descide whether HS400 is available.
Using sdhci-caps-mask allows to mask bit 63. The stack then selects
HS200 as operating mode.
This prevents rare communication errors with minimal effect on
performance:
sdhci-esdhc-imx 30b60000.usdhc: warning! HS400 strobe DLL
status REF not lock!
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/imx7-colibri.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index f1c1971f2160..f7c9ce5bed47 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -325,6 +325,7 @@
vmmc-supply = <®_module_3v3>;
vqmmc-supply = <®_DCDC3>;
non-removable;
+ sdhci-caps-mask = <0x80000000 0x0>;
};
&iomuxc {
--
2.22.0
^ permalink raw reply related
* [PATCH v3 03/21] ARM: dts: imx7-colibri: prepare module device tree for FlexCAN
From: Philippe Schenker @ 2019-08-07 8:26 UTC (permalink / raw)
To: Marcel Ziswiler, Max Krummenacher, stefan@agner.ch,
devicetree@vger.kernel.org, Rob Herring, Shawn Guo, Mark Rutland,
Michal Vokáč, Fabio Estevam
Cc: Philippe Schenker, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, Pengutronix Kernel Team,
NXP Linux Team, Sascha Hauer
In-Reply-To: <20190807082556.5013-1-philippe.schenker@toradex.com>
Prepare FlexCAN use on SODIMM 55/63 178/188. Those SODIMM pins are
compatible for CAN bus use with several modules from the Colibri
family.
Add Better drivestrength and also add flexcan2.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/imx7-colibri.dtsi | 35 ++++++++++++++++++++++++-----
1 file changed, 30 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index f7c9ce5bed47..52046085ce6f 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -117,6 +117,18 @@
fsl,magic-packet;
};
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "disabled";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "disabled";
+};
+
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
@@ -330,12 +342,11 @@
&iomuxc {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>;
+ pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4
+ &pinctrl_gpio7>;
pinctrl_gpio1: gpio1-grp {
fsl,pins = <
- MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 55 */
- MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x74 /* SODIMM 63 */
MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */
MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */
MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */
@@ -416,6 +427,13 @@
>;
};
+ pinctrl_gpio7: gpio7-grp { /* Alternatively CAN1 */
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */
+ MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
+ >;
+ };
+
pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */
fsl,pins = <
MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
@@ -459,10 +477,17 @@
>;
};
+ pinctrl_flexcan1: flexcan1-grp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */
+ MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */
+ >;
+ };
+
pinctrl_flexcan2: flexcan2-grp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
- MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
+ MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */
+ MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */
>;
};
--
2.22.0
^ permalink raw reply related
* [PATCH v3 04/21] ARM: dts: imx7-colibri: Add sleep mode to ethernet
From: Philippe Schenker @ 2019-08-07 8:26 UTC (permalink / raw)
To: Marcel Ziswiler, Max Krummenacher, stefan@agner.ch,
devicetree@vger.kernel.org, Rob Herring, Shawn Guo, Mark Rutland,
Michal Vokáč, Fabio Estevam
Cc: Philippe Schenker, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, Pengutronix Kernel Team,
NXP Linux Team, Sascha Hauer
In-Reply-To: <20190807082556.5013-1-philippe.schenker@toradex.com>
Add sleep pinmux to the fec so it can properly sleep.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/imx7-colibri.dtsi | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index 52046085ce6f..a8d992f3e897 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -101,8 +101,9 @@
};
&fec1 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_enet1>;
+ pinctrl-1 = <&pinctrl_enet1_sleep>;
clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
<&clks IMX7D_ENET_AXI_ROOT_CLK>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
@@ -463,6 +464,22 @@
>;
};
+ pinctrl_enet1_sleep: enet1sleepgrp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0
+ MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0
+ MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0
+ MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0
+
+ MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0
+ MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0
+ MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0
+ MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0
+ MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x0
+ MX7D_PAD_SD2_WP__GPIO5_IO10 0x0
+ >;
+ };
+
pinctrl_ecspi3_cs: ecspi3-cs-grp {
fsl,pins = <
MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
--
2.22.0
^ permalink raw reply related
* [PATCH v3 05/21] ARM: dts: add recovery for I2C for iMX7
From: Philippe Schenker @ 2019-08-07 8:26 UTC (permalink / raw)
To: Marcel Ziswiler, Max Krummenacher, stefan@agner.ch,
devicetree@vger.kernel.org, Rob Herring, Shawn Guo, Mark Rutland,
Michal Vokáč, Fabio Estevam
Cc: Oleksandr Suvorov, Philippe Schenker,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, Pengutronix Kernel Team,
NXP Linux Team, Sascha Hauer
In-Reply-To: <20190807082556.5013-1-philippe.schenker@toradex.com>
From: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
- add recovery mode for applicable i2c buses for
Colibri iMX7 module.
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/imx7-colibri.dtsi | 25 +++++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index a8d992f3e897..2480623c92ff 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -140,8 +140,12 @@
&i2c1 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
+ pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>;
+ scl-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+
status = "okay";
codec: sgtl5000@a {
@@ -242,8 +246,11 @@
&i2c4 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_recovery>;
+ scl-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
};
&lcdif {
@@ -540,6 +547,13 @@
>;
};
+ pinctrl_i2c4_recovery: i2c4-recoverygrp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f
+ MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f
+ >;
+ };
+
pinctrl_lcdif_dat: lcdif-dat-grp {
fsl,pins = <
MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
@@ -740,6 +754,13 @@
>;
};
+ pinctrl_i2c1_recovery: i2c1-recoverygrp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f
+ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f
+ >;
+ };
+
pinctrl_cd_usdhc1: usdhc1-cd-grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */
--
2.22.0
^ permalink raw reply related
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