* [PATCH v3] arm64: dts: qcom: apq8016-sbc-d3: Add Qualcomm APQ8016 SBC + D3Camera mezzanine
From: Robert Foss @ 2020-05-18 8:21 UTC (permalink / raw)
To: Vinod Koul, Bjorn Andersson, Rob Herring, linux-arm-msm,
devicetree, linux-kernel
Cc: Nicolas Dechesne, Robert Foss
Add device treee support for the Qualcomm APQ8016 SBC, otherwise known as
the Dragonboard 410c with the D3Camera mezzanine expansion board.
The D3Camera mezzanine ships in a kit with a OmniVision 5640 sensor module,
which is what this DT targets.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
Changes since v2:
- Vinod: Change copyright assignment to Linaro
Changes since v1:
- Vinod: Changed license to GPL+BSD
- Vinod: Changed copyright year to 2020
- Nico: Changed name of mezzanine to d3camera
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/apq8016-sbc-d3camera.dts | 45 +++++++++++++++++++
2 files changed, 46 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-d3camera.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index cc103f7020fd..3f95b522694e 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
+dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-d3camera.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-d3camera.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc-d3camera.dts
new file mode 100644
index 000000000000..752e5ec47499
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-d3camera.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "apq8016-sbc.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. APQ 8016 SBC w/ D3Camera Mezzanine";
+ compatible = "qcom,apq8016-sbc", "qcom,apq8016", "qcom,sbc";
+};
+
+&cci_i2c0 {
+ /delete-node/ camera_rear@3b;
+
+ camera_rear@76 {
+ compatible = "ovti,ov5640";
+ reg = <0x76>;
+
+ enable-gpios = <&msmgpio 34 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&camera_rear_default>;
+
+ clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "xclk";
+ clock-frequency = <23880000>;
+
+ vdddo-supply = <&camera_vdddo_1v8>;
+ vdda-supply = <&camera_vdda_2v8>;
+ vddd-supply = <&camera_vddd_1v5>;
+
+ status = "ok";
+
+ port {
+ ov5640_ep: endpoint {
+ clock-lanes = <1>;
+ data-lanes = <0 2>;
+ remote-endpoint = <&csiphy0_ep>;
+ };
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related
* Re: [PATCH] arm: dts: am33xx-bone-common: add gpio-line-names
From: Felipe Balbi @ 2020-05-18 8:18 UTC (permalink / raw)
To: Linus Walleij, Drew Fustini
Cc: Grygorii Strashko, Benoît Cousson, Tony Lindgren,
Rob Herring, Linux-OMAP,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org, Jason Kridner, Robert Nelson
In-Reply-To: <CACRpkdb+ZP6rfjGg6Ef9_wYvNf6qmSc7LZyYBVKA3XWCtxPfqQ@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 810 bytes --]
Linus Walleij <linus.walleij@linaro.org> writes:
>> gpiochip0 - 32 lines:
>> line 0: "ethernet" unused input active-high
>> line 1: "ethernet" unused input active-high
>
> Why are the ethernet lines not tagged with respective signal name
> when right below the SPI lines are explicitly tagged with
> sclk, cs0 etc?
>
> Ethernet is usually RGMII and has signal names like
> tx_clk, tx_d0, tx_en etc.
>
> Also some lines seem to be tagged with the pin number
> like P9_22, P2_21 below, it seems a bit inconsistent
> to have much information on some pins and very sketchy
> information on some.
the pin names match the beagle bone documentation and would help users
figure out which pins on the expansion headers match to a gpio signal.
--
balbi
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 832 bytes --]
^ permalink raw reply
* [PATCH v2] dt-bindings: clock: renesas: cpg: Convert to json-schema
From: Geert Uytterhoeven @ 2020-05-18 8:16 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring
Cc: linux-renesas-soc, linux-clk, devicetree, Geert Uytterhoeven
Convert the Renesas Clock Pulse Generator (CPG) Device Tree
binding documentation to json-schema, combining support for:
- R-Mobile APE6 (R8A73A4) and A1 (R8A7740),
- R-Car M1 (R8A7778) and H1 (R8A7779),
- RZ/A1 (R7S72100),
- SH-Mobile AG5 (SH73A0).
Keep the example for R-Mobile A1, which shows most properties.
Drop the consumer examples, as they do not belong here.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2:
- Remove unneeded 'allOf' container around '$ref',
To be queued in clk-renesas-for-v5.8.
For a clean dtbs_check, this depends on commit e47cb97f153193d4 ("ARM:
dts: r8a7740: Add missing extal2 to CPG node") in v5.7-rc6.
As these bindings are very similar, I merged them into a single
document. SoC-specific differences are mostly limited to the "clocks"
and "clock-output-names" properties, and "#power-domain-cells" for clock
domain providers.
JFYI, the diffstat for the individual conversions would look like:
.../clock/renesas,r8a73a4-cpg-clocks.txt | 33 --------
.../clock/renesas,r8a73a4-cpg-clocks.yaml | 70 ++++++++++++++++
.../clock/renesas,r8a7740-cpg-clocks.txt | 41 ----------
.../clock/renesas,r8a7740-cpg-clocks.yaml | 81 +++++++++++++++++++
.../clock/renesas,r8a7778-cpg-clocks.txt | 47 -----------
.../clock/renesas,r8a7778-cpg-clocks.yaml | 64 +++++++++++++++
.../clock/renesas,r8a7779-cpg-clocks.txt | 49 -----------
.../clock/renesas,r8a7779-cpg-clocks.yaml | 65 +++++++++++++++
.../bindings/clock/renesas,rz-cpg-clocks.txt | 53 ------------
.../bindings/clock/renesas,rz-cpg-clocks.yaml | 66 +++++++++++++++
.../clock/renesas,sh73a0-cpg-clocks.txt | 35 --------
.../clock/renesas,sh73a0-cpg-clocks.yaml | 69 ++++++++++++++++
12 files changed, 415 insertions(+), 258 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt
create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.yaml
delete mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt
create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.yaml
delete mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.yaml
delete mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.yaml
delete mode 100644 Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
create mode 100644 Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.yaml
delete mode 100644 Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt
create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.yaml
---
.../bindings/clock/renesas,cpg-clocks.yaml | 241 ++++++++++++++++++
.../clock/renesas,r8a73a4-cpg-clocks.txt | 33 ---
.../clock/renesas,r8a7740-cpg-clocks.txt | 41 ---
.../clock/renesas,r8a7778-cpg-clocks.txt | 47 ----
.../clock/renesas,r8a7779-cpg-clocks.txt | 49 ----
.../bindings/clock/renesas,rz-cpg-clocks.txt | 53 ----
.../clock/renesas,sh73a0-cpg-clocks.txt | 35 ---
7 files changed, 241 insertions(+), 258 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml
delete mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt
delete mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt
delete mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
delete mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
delete mode 100644 Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
delete mode 100644 Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml
new file mode 100644
index 0000000000000000..b83f4138f2f8b149
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml
@@ -0,0 +1,241 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas Clock Pulse Generator (CPG)
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description:
+ The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
+ includes PLLs, and fixed and variable ratio dividers.
+
+ The CPG may also provide a Clock Domain for SoC devices, in combination with
+ the CPG Module Stop (MSTP) Clocks.
+
+properties:
+ compatible:
+ oneOf:
+ - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
+ - const: renesas,r8a7740-cpg-clocks # R-Mobile A1
+ - const: renesas,r8a7778-cpg-clocks # R-Car M1
+ - const: renesas,r8a7779-cpg-clocks # R-Car H1
+ - items:
+ - enum:
+ - renesas,r7s72100-cpg-clocks # RZ/A1H
+ - const: renesas,rz-cpg-clocks # RZ/A1
+ - const: renesas,sh73a0-cpg-clocks # SH-Mobile AG5
+
+ reg:
+ maxItems: 1
+
+ clocks: true
+
+ '#clock-cells':
+ const: 1
+
+ clock-output-names: true
+
+ renesas,mode:
+ description: Board-specific settings of the MD_CK* bits on R-Mobile A1
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 7
+
+ '#power-domain-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+ - clock-output-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r8a73a4-cpg-clocks
+ then:
+ properties:
+ clocks:
+ items:
+ - description: extal1
+ - description: extal2
+
+ clock-output-names:
+ items:
+ - const: main
+ - const: pll0
+ - const: pll1
+ - const: pll2
+ - const: pll2s
+ - const: pll2h
+ - const: z
+ - const: z2
+ - const: i
+ - const: m3
+ - const: b
+ - const: m1
+ - const: m2
+ - const: zx
+ - const: zs
+ - const: hp
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r8a7740-cpg-clocks
+ then:
+ properties:
+ clocks:
+ items:
+ - description: extal1
+ - description: extal2
+ - description: extalr
+
+ clock-output-names:
+ items:
+ - const: system
+ - const: pllc0
+ - const: pllc1
+ - const: pllc2
+ - const: r
+ - const: usb24s
+ - const: i
+ - const: zg
+ - const: b
+ - const: m1
+ - const: hp
+ - const: hpp
+ - const: usbp
+ - const: s
+ - const: zb
+ - const: m3
+ - const: cp
+
+ required:
+ - renesas,mode
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r8a7778-cpg-clocks
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ clock-output-names:
+ items:
+ - const: plla
+ - const: pllb
+ - const: b
+ - const: out
+ - const: p
+ - const: s
+ - const: s1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r8a7779-cpg-clocks
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ clock-output-names:
+ items:
+ - const: plla
+ - const: z
+ - const: zs
+ - const: s
+ - const: s1
+ - const: p
+ - const: b
+ - const: out
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r7s72100-cpg-clocks
+ then:
+ properties:
+ clocks:
+ items:
+ - description: extal1
+ - description: usb_x1
+
+ clock-output-names:
+ items:
+ - const: pll
+ - const: i
+ - const: g
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,sh73a0-cpg-clocks
+ then:
+ properties:
+ clocks:
+ items:
+ - description: extal1
+ - description: extal2
+
+ clock-output-names:
+ items:
+ - const: main
+ - const: pll0
+ - const: pll1
+ - const: pll2
+ - const: pll3
+ - const: dsi0phy
+ - const: dsi1phy
+ - const: zg
+ - const: m3
+ - const: b
+ - const: m1
+ - const: m2
+ - const: z
+ - const: zx
+ - const: hp
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r8a7778-cpg-clocks
+ - renesas,r8a7779-cpg-clocks
+ - renesas,rz-cpg-clocks
+ then:
+ required:
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7740-clock.h>
+ cpg_clocks: cpg_clocks@e6150000 {
+ compatible = "renesas,r8a7740-cpg-clocks";
+ reg = <0xe6150000 0x10000>;
+ clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
+ #clock-cells = <1>;
+ clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",
+ "usb24s", "i", "zg", "b", "m1", "hp", "hpp",
+ "usbp", "s", "zb", "m3", "cp";
+ renesas,mode = <0x05>;
+ };
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt
deleted file mode 100644
index ece92393e80d4648..0000000000000000
--- a/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-* Renesas R8A73A4 Clock Pulse Generator (CPG)
-
-The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs
-and several fixed ratio dividers.
-
-Required Properties:
-
- - compatible: Must be "renesas,r8a73a4-cpg-clocks"
-
- - reg: Base address and length of the memory resource used by the CPG
-
- - clocks: Reference to the parent clocks ("extal1" and "extal2")
-
- - #clock-cells: Must be 1
-
- - clock-output-names: The names of the clocks. Supported clocks are "main",
- "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
- "m1", "m2", "zx", "zs", and "hp".
-
-
-Example
--------
-
- cpg_clocks: cpg_clocks@e6150000 {
- compatible = "renesas,r8a73a4-cpg-clocks";
- reg = <0 0xe6150000 0 0x10000>;
- clocks = <&extal1_clk>, <&extal2_clk>;
- #clock-cells = <1>;
- clock-output-names = "main", "pll0", "pll1", "pll2",
- "pll2s", "pll2h", "z", "z2",
- "i", "m3", "b", "m1", "m2",
- "zx", "zs", "hp";
- };
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt
deleted file mode 100644
index 2c03302f86edfb83..0000000000000000
--- a/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-These bindings should be considered EXPERIMENTAL for now.
-
-* Renesas R8A7740 Clock Pulse Generator (CPG)
-
-The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs
-and several fixed ratio and variable ratio dividers.
-
-Required Properties:
-
- - compatible: Must be "renesas,r8a7740-cpg-clocks"
-
- - reg: Base address and length of the memory resource used by the CPG
-
- - clocks: Reference to the three parent clocks
- - #clock-cells: Must be 1
- - clock-output-names: The names of the clocks. Supported clocks are
- "system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b",
- "m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp".
-
- - renesas,mode: board-specific settings of the MD_CK* bits
-
-
-Example
--------
-
-cpg_clocks: cpg_clocks@e6150000 {
- compatible = "renesas,r8a7740-cpg-clocks";
- reg = <0xe6150000 0x10000>;
- clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
- #clock-cells = <1>;
- clock-output-names = "system", "pllc0", "pllc1",
- "pllc2", "r",
- "usb24s",
- "i", "zg", "b", "m1", "hp",
- "hpp", "usbp", "s", "zb", "m3",
- "cp";
-};
-
-&cpg_clocks {
- renesas,mode = <0x05>;
-};
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
deleted file mode 100644
index 7cc4c0330b534660..0000000000000000
--- a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-* Renesas R8A7778 Clock Pulse Generator (CPG)
-
-The CPG generates core clocks for the R8A7778. It includes two PLLs and
-several fixed ratio dividers.
-The CPG also provides a Clock Domain for SoC devices, in combination with the
-CPG Module Stop (MSTP) Clocks.
-
-Required Properties:
-
- - compatible: Must be "renesas,r8a7778-cpg-clocks"
- - reg: Base address and length of the memory resource used by the CPG
- - #clock-cells: Must be 1
- - clock-output-names: The names of the clocks. Supported clocks are
- "plla", "pllb", "b", "out", "p", "s", and "s1".
- - #power-domain-cells: Must be 0
-
-SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
-through an MSTP clock should refer to the CPG device node in their
-"power-domains" property, as documented by the generic PM domain bindings in
-Documentation/devicetree/bindings/power/power_domain.txt.
-
-
-Examples
---------
-
- - CPG device node:
-
- cpg_clocks: cpg_clocks@ffc80000 {
- compatible = "renesas,r8a7778-cpg-clocks";
- reg = <0xffc80000 0x80>;
- #clock-cells = <1>;
- clocks = <&extal_clk>;
- clock-output-names = "plla", "pllb", "b",
- "out", "p", "s", "s1";
- #power-domain-cells = <0>;
- };
-
-
- - CPG/MSTP Clock Domain member device node:
-
- sdhi0: sd@ffe4c000 {
- compatible = "renesas,sdhi-r8a7778";
- reg = <0xffe4c000 0x100>;
- interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
- power-domains = <&cpg_clocks>;
- };
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
deleted file mode 100644
index 8c81547c29f568e8..0000000000000000
--- a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-* Renesas R8A7779 Clock Pulse Generator (CPG)
-
-The CPG generates core clocks for the R8A7779. It includes one PLL and
-several fixed ratio dividers.
-The CPG also provides a Clock Domain for SoC devices, in combination with the
-CPG Module Stop (MSTP) Clocks.
-
-Required Properties:
-
- - compatible: Must be "renesas,r8a7779-cpg-clocks"
- - reg: Base address and length of the memory resource used by the CPG
-
- - clocks: Reference to the parent clock
- - #clock-cells: Must be 1
- - clock-output-names: The names of the clocks. Supported clocks are "plla",
- "z", "zs", "s", "s1", "p", "b", "out".
- - #power-domain-cells: Must be 0
-
-SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
-through an MSTP clock should refer to the CPG device node in their
-"power-domains" property, as documented by the generic PM domain bindings in
-Documentation/devicetree/bindings/power/power_domain.txt.
-
-
-Examples
---------
-
- - CPG device node:
-
- cpg_clocks: cpg_clocks@ffc80000 {
- compatible = "renesas,r8a7779-cpg-clocks";
- reg = <0xffc80000 0x30>;
- clocks = <&extal_clk>;
- #clock-cells = <1>;
- clock-output-names = "plla", "z", "zs", "s", "s1", "p",
- "b", "out";
- #power-domain-cells = <0>;
- };
-
-
- - CPG/MSTP Clock Domain member device node:
-
- sata: sata@fc600000 {
- compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
- reg = <0xfc600000 0x2000>;
- interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp1_clks R8A7779_CLK_SATA>;
- power-domains = <&cpg_clocks>;
- };
diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
deleted file mode 100644
index 8ff3e2774ed8d1d0..0000000000000000
--- a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
+++ /dev/null
@@ -1,53 +0,0 @@
-* Renesas RZ/A1 Clock Pulse Generator (CPG)
-
-The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable
-CPU and GPU clocks, and several fixed ratio dividers.
-The CPG also provides a Clock Domain for SoC devices, in combination with the
-CPG Module Stop (MSTP) Clocks.
-
-Required Properties:
-
- - compatible: Must be one of
- - "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
- and "renesas,rz-cpg-clocks" as a fallback.
- - reg: Base address and length of the memory resource used by the CPG
- - clocks: References to possible parent clocks. Order must match clock modes
- in the datasheet. For the r7s72100, this is extal, usb_x1.
- - #clock-cells: Must be 1
- - clock-output-names: The names of the clocks. Supported clocks are "pll",
- "i", and "g"
- - #power-domain-cells: Must be 0
-
-SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
-through an MSTP clock should refer to the CPG device node in their
-"power-domains" property, as documented by the generic PM domain bindings in
-Documentation/devicetree/bindings/power/power_domain.txt.
-
-
-Examples
---------
-
- - CPG device node:
-
- cpg_clocks: cpg_clocks@fcfe0000 {
- #clock-cells = <1>;
- compatible = "renesas,r7s72100-cpg-clocks",
- "renesas,rz-cpg-clocks";
- reg = <0xfcfe0000 0x18>;
- clocks = <&extal_clk>, <&usb_x1_clk>;
- clock-output-names = "pll", "i", "g";
- #power-domain-cells = <0>;
- };
-
-
- - CPG/MSTP Clock Domain member device node:
-
- mtu2: timer@fcff0000 {
- compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
- reg = <0xfcff0000 0x400>;
- interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tgi0a";
- clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
- clock-names = "fck";
- power-domains = <&cpg_clocks>;
- };
diff --git a/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt
deleted file mode 100644
index a8978ec94831fc6b..0000000000000000
--- a/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-These bindings should be considered EXPERIMENTAL for now.
-
-* Renesas SH73A0 Clock Pulse Generator (CPG)
-
-The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs
-and several fixed ratio dividers.
-
-Required Properties:
-
- - compatible: Must be "renesas,sh73a0-cpg-clocks"
-
- - reg: Base address and length of the memory resource used by the CPG
-
- - clocks: Reference to the parent clocks ("extal1" and "extal2")
-
- - #clock-cells: Must be 1
-
- - clock-output-names: The names of the clocks. Supported clocks are "main",
- "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
- "m1", "m2", "z", "zx", and "hp".
-
-
-Example
--------
-
- cpg_clocks: cpg_clocks@e6150000 {
- compatible = "renesas,sh73a0-cpg-clocks";
- reg = <0 0xe6150000 0 0x10000>;
- clocks = <&extal1_clk>, <&extal2_clk>;
- #clock-cells = <1>;
- clock-output-names = "main", "pll0", "pll1", "pll2",
- "pll3", "dsi0phy", "dsi1phy",
- "zg", "m3", "b", "m1", "m2",
- "z", "zx", "hp";
- };
--
2.17.1
^ permalink raw reply related
* Re: [PATCH v3 00/20] dts/dt-bindings: Fix Arm Ltd. ARMv8 "boards"
From: Sudeep Holla @ 2020-05-18 8:15 UTC (permalink / raw)
To: Andre Przywara, Lorenzo Pieralisi, Rob Herring, Liviu Dudau
Cc: Sudeep Holla, Mark Rutland, linux-arm-kernel, Marc Zyngier,
devicetree
In-Reply-To: <20200513103016.130417-1-andre.przywara@arm.com>
On Wed, 13 May 2020 11:29:56 +0100, Andre Przywara wrote:
> A few updates compared to v2. The most important is to fix the
> interrupt-maps, triggered by changing the number of address-cells in
> the GIC node. For this I split the former patch 07/17 into two (09/20
> and 10/20), one for the foundation model, the other for Juno.
> Also I fixed a dtc complaint about device nodes without reg properties
> being inside simple-bus nodes, those are the new patches 04-06/20.
> Will took patch 01/17 from v2 already, so I removed this from this
> series.
> The rest of the patches stayed the same.
> -----------------------------------
>
> [...]
Applied to sudeep.holla/linux tree (for-next/juno), thanks!
[02/20] arm64: dts: fvp/juno: Fix node address fields
https://git.kernel.org/sudeep.holla/c/bb5cce12ac
[03/20] arm64: dts: fvp: Move fixed devices out of bus node
https://git.kernel.org/sudeep.holla/c/849bfc3dfc
[04/20] arm64: dts: vexpress: Move fixed devices out of bus node
https://git.kernel.org/sudeep.holla/c/d9258898ad
[05/20] arm64: dts: fvp: Move fixed clocks out of bus node
https://git.kernel.org/sudeep.holla/c/feebdc3f79
[06/20] arm64: dts: juno: Move fixed devices out of bus node
https://git.kernel.org/sudeep.holla/c/948204a1bf
[07/20] arm64: dts: juno: Fix mem-timer
https://git.kernel.org/sudeep.holla/c/0e529dae51
[08/20] arm64: dts: fvp: Fix GIC compatible names
https://git.kernel.org/sudeep.holla/c/336edacfb9
[09/20] arm64: dts: juno: Fix GIC child nodes
https://git.kernel.org/sudeep.holla/c/a78aee9e43
[10/20] arm64: dts: fvp: Fix GIC child nodes
https://git.kernel.org/sudeep.holla/c/78631aecc5
[11/20] arm64: dts: fvp: Fix ITS node names and #msi-cells
https://git.kernel.org/sudeep.holla/c/fac959c93f
[12/20] arm64: dts: juno: Use proper DT node name for USB
https://git.kernel.org/sudeep.holla/c/17a37ff76e
[13/20] arm64: dts: fvp/juno: Fix serial node names
https://git.kernel.org/sudeep.holla/c/fa51a2a1ed
[14/20] arm64: dts: fvp: Fix SMMU DT node
https://git.kernel.org/sudeep.holla/c/19650d681b
[15/20] arm64: dts: fvp/juno: Fix bus node names
https://git.kernel.org/sudeep.holla/c/b68d15c0e6
[16/20] arm64: dts: juno: Fix GPU interrupt order
https://git.kernel.org/sudeep.holla/c/2dd42335f8
[17/20] arm64: dts: vexpress: Fix VExpress LED names
https://git.kernel.org/sudeep.holla/c/bf3f0ccf35
[18/20] arm64: dts: juno: Fix SCPI shared mem node name
https://git.kernel.org/sudeep.holla/c/93f6027abe
--
Regards,
Sudeep
^ permalink raw reply
* [PATCH v3] dt-bindings: timer: renesas: tmu: Convert to json-schema
From: Geert Uytterhoeven @ 2020-05-18 8:15 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Rob Herring
Cc: devicetree, linux-renesas-soc, linux-kernel, Geert Uytterhoeven
Convert the Renesas R-Mobile/R-Car Timer Unit (TMU) Device Tree binding
documentation to json-schema.
Document missing properties.
Update the example to match reality.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v3:
- Remove unneeded 'allOf' container around '$ref',
v2:
- Add missing "additionalProperties: false",
- Add Reviewed-by.
---
.../devicetree/bindings/timer/renesas,tmu.txt | 49 ----------
.../bindings/timer/renesas,tmu.yaml | 98 +++++++++++++++++++
2 files changed, 98 insertions(+), 49 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/timer/renesas,tmu.txt
create mode 100644 Documentation/devicetree/bindings/timer/renesas,tmu.yaml
diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.txt b/Documentation/devicetree/bindings/timer/renesas,tmu.txt
deleted file mode 100644
index 29159f4e65abece9..0000000000000000
--- a/Documentation/devicetree/bindings/timer/renesas,tmu.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-* Renesas R-Mobile/R-Car Timer Unit (TMU)
-
-The TMU is a 32-bit timer/counter with configurable clock inputs and
-programmable compare match.
-
-Channels share hardware resources but their counter and compare match value
-are independent. The TMU hardware supports up to three channels.
-
-Required Properties:
-
- - compatible: must contain one or more of the following:
- - "renesas,tmu-r8a7740" for the r8a7740 TMU
- - "renesas,tmu-r8a774a1" for the r8a774A1 TMU
- - "renesas,tmu-r8a774b1" for the r8a774B1 TMU
- - "renesas,tmu-r8a774c0" for the r8a774C0 TMU
- - "renesas,tmu-r8a7778" for the r8a7778 TMU
- - "renesas,tmu-r8a7779" for the r8a7779 TMU
- - "renesas,tmu-r8a77970" for the r8a77970 TMU
- - "renesas,tmu-r8a77980" for the r8a77980 TMU
- - "renesas,tmu" for any TMU.
- This is a fallback for the above renesas,tmu-* entries
-
- - reg: base address and length of the registers block for the timer module.
-
- - interrupts: interrupt-specifier for the timer, one per channel.
-
- - clocks: a list of phandle + clock-specifier pairs, one for each entry
- in clock-names.
- - clock-names: must contain "fck" for the functional clock.
-
-Optional Properties:
-
- - #renesas,channels: number of channels implemented by the timer, must be 2
- or 3 (if not specified the value defaults to 3).
-
-
-Example: R8A7779 (R-Car H1) TMU0 node
-
- tmu0: timer@ffd80000 {
- compatible = "renesas,tmu-r8a7779", "renesas,tmu";
- reg = <0xffd80000 0x30>;
- interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
- <0 33 IRQ_TYPE_LEVEL_HIGH>,
- <0 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
- clock-names = "fck";
-
- #renesas,channels = <3>;
- };
diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml
new file mode 100644
index 0000000000000000..2f7bd31f0dfe0607
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/renesas,tmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Mobile/R-Car Timer Unit (TMU)
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+description:
+ The TMU is a 32-bit timer/counter with configurable clock inputs and
+ programmable compare match.
+
+ Channels share hardware resources but their counter and compare match value
+ are independent. The TMU hardware supports up to three channels.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,tmu-r8a7740 # R-Mobile A1
+ - renesas,tmu-r8a774a1 # RZ/G2M
+ - renesas,tmu-r8a774b1 # RZ/G2N
+ - renesas,tmu-r8a774c0 # RZ/G2E
+ - renesas,tmu-r8a7778 # R-Car M1A
+ - renesas,tmu-r8a7779 # R-Car H1
+ - renesas,tmu-r8a77970 # R-Car V3M
+ - renesas,tmu-r8a77980 # R-Car V3H
+ - const: renesas,tmu
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 2
+ maxItems: 3
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: fck
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ '#renesas,channels':
+ description:
+ Number of channels implemented by the timer.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 2, 3 ]
+ default: 3
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+
+if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,tmu-r8a7740
+ - renesas,tmu-r8a7778
+ - renesas,tmu-r8a7779
+then:
+ required:
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7779-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7779-sysc.h>
+ tmu0: timer@ffd80000 {
+ compatible = "renesas,tmu-r8a7779", "renesas,tmu";
+ reg = <0xffd80000 0x30>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
+ #renesas,channels = <3>;
+ };
--
2.17.1
^ permalink raw reply related
* RE: [PATCH V2] dt-bindings: interrupt-controller: Convert imx irqsteer to json-schema
From: Aisheng Dong @ 2020-05-18 8:07 UTC (permalink / raw)
To: Anson Huang, tglx@linutronix.de, jason@lakedaemon.net,
maz@kernel.org, robh+dt@kernel.org, l.stach@pengutronix.de,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Cc: dl-linux-imx
In-Reply-To: <1589782336-17289-1-git-send-email-Anson.Huang@nxp.com>
> From: Anson Huang <Anson.Huang@nxp.com>
> Sent: Monday, May 18, 2020 2:12 PM
>
> Convert the i.MX IRQSTEER binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
A few minor comments, otherwise:
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
BTW, we probably better add ref to the common interrupt-controller.yaml to inherit
the common constraints. E.g. nodename.
But I noted some exist binding also did not include it, so maybe we can wait for Rob's
comments.
Other minor comments inline.
> ---
> Changes since V1:
> - Add "fsl,imx8m-irqsteer" compatible back.
> - Use "Multiplexer" instead of "multiplexer" for title.
> ---
> .../bindings/interrupt-controller/fsl,irqsteer.txt | 35 ---------
> .../interrupt-controller/fsl,irqsteer.yaml | 89
> ++++++++++++++++++++++
> 2 files changed, 89 insertions(+), 35 deletions(-) delete mode 100644
> Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt
> create mode 100644
> Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt
> b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt
> deleted file mode 100644
> index 582991c..0000000
> --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt
> +++ /dev/null
> @@ -1,35 +0,0 @@
> -Freescale IRQSTEER Interrupt multiplexer
> -
> -Required properties:
> -
> -- compatible: should be:
> - - "fsl,imx8m-irqsteer"
> - - "fsl,imx-irqsteer"
> -- reg: Physical base address and size of registers.
> -- interrupts: Should contain the up to 8 parent interrupt lines used to
> - multiplex the input interrupts. They should be specified sequentially
> - from output 0 to 7.
> -- clocks: Should contain one clock for entry in clock-names
> - see Documentation/devicetree/bindings/clock/clock-bindings.txt
> -- clock-names:
> - - "ipg": main logic clock
> -- interrupt-controller: Identifies the node as an interrupt controller.
> -- #interrupt-cells: Specifies the number of cells needed to encode an
> - interrupt source. The value must be 1.
> -- fsl,channel: The output channel that all input IRQs should be steered into.
> -- fsl,num-irqs: Number of input interrupts of this channel.
> - Should be multiple of 32 input interrupts and up to 512 interrupts.
> -
> -Example:
> -
> - interrupt-controller@32e2d000 {
> - compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
> - reg = <0x32e2d000 0x1000>;
> - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
> - clock-names = "ipg";
> - fsl,channel = <0>;
> - fsl,num-irqs = <64>;
> - interrupt-controller;
> - #interrupt-cells = <1>;
> - };
> diff --git
> a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
> b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
> new file mode 100644
> index 0000000..5242c97
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqstee
> +++ r.yaml
> @@ -0,0 +1,89 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> +---
[...]
> +title: Freescale IRQSTEER Interrupt Multiplexer
> +
> +maintainers:
> + - Lucas Stach <l.stach@pengutronix.de>
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,imx8m-irqsteer
> + - fsl,imx-irqsteer
> +
Original compatible string definition seems not accurate.
It does not cover the case of using both together.
Anyway, that's exist issue, you can submit an extra patch to fix it later.
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + description: |
> + should contain the up to 8 parent interrupt lines used to multiplex
> + the input interrupts. They should be specified sequentially from
> + output 0 to 7.
> + items:
> + - description: irqsteer channel 0
> + - description: irqsteer channel 1
> + - description: irqsteer channel 2
> + - description: irqsteer channel 3
> + - description: irqsteer channel 4
> + - description: irqsteer channel 5
> + - description: irqsteer channel 6
> + - description: irqsteer channel 7
'channel' is confusing here, it's actually output interrupt 0-7 for one channel.
s/irqsteer channel/output interrupt x
Regards
Aisheng
> + minItems: 1
> + maxItems: 8
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: ipg
> +
> + interrupt-controller: true
> +
> + "#interrupt-cells":
> + const: 1
> +
> + fsl,channel:
> + $ref: '/schemas/types.yaml#/definitions/uint32'
> + description: |
> + u32 value representing the output channel that all input IRQs should be
> + steered into.
> +
> + fsl,num-irqs:
> + $ref: '/schemas/types.yaml#/definitions/uint32'
> + description: |
> + u32 value representing the number of input interrupts of this channel,
> + should be multiple of 32 input interrupts and up to 512 interrupts.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - interrupt-controller
> + - "#interrupt-cells"
> + - fsl,channel
> + - fsl,num-irqs
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx8mq-clock.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + interrupt-controller@32e2d000 {
> + compatible = "fsl,imx-irqsteer";
> + reg = <0x32e2d000 0x1000>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
> + clock-names = "ipg";
> + fsl,channel = <0>;
> + fsl,num-irqs = <64>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> --
> 2.7.4
^ permalink raw reply
* [PATCH] dt-bindings: regulator: Convert anatop regulator to json-schema
From: Anson Huang @ 2020-05-18 7:55 UTC (permalink / raw)
To: lgirdwood, broonie, robh+dt, paul.liu, linux-kernel, devicetree; +Cc: Linux-imx
Convert the anatop regulator binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
.../bindings/regulator/anatop-regulator.txt | 40 ---------
.../bindings/regulator/anatop-regulator.yaml | 94 ++++++++++++++++++++++
2 files changed, 94 insertions(+), 40 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/regulator/anatop-regulator.txt
create mode 100644 Documentation/devicetree/bindings/regulator/anatop-regulator.yaml
diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
deleted file mode 100644
index a3106c7..0000000
--- a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-Anatop Voltage regulators
-
-Required properties:
-- compatible: Must be "fsl,anatop-regulator"
-- regulator-name: A string used as a descriptive name for regulator outputs
-- anatop-reg-offset: Anatop MFD register offset
-- anatop-vol-bit-shift: Bit shift for the register
-- anatop-vol-bit-width: Number of bits used in the register
-- anatop-min-bit-val: Minimum value of this register
-- anatop-min-voltage: Minimum voltage of this regulator
-- anatop-max-voltage: Maximum voltage of this regulator
-
-Optional properties:
-- anatop-delay-reg-offset: Anatop MFD step time register offset
-- anatop-delay-bit-shift: Bit shift for the step time register
-- anatop-delay-bit-width: Number of bits used in the step time register
-- vin-supply: The supply for this regulator
-- anatop-enable-bit: Regulator enable bit offset
-
-Any property defined as part of the core regulator
-binding, defined in regulator.txt, can also be used.
-
-Example:
-
- regulator-vddpu {
- compatible = "fsl,anatop-regulator";
- regulator-name = "vddpu";
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1300000>;
- regulator-always-on;
- anatop-reg-offset = <0x140>;
- anatop-vol-bit-shift = <9>;
- anatop-vol-bit-width = <5>;
- anatop-delay-reg-offset = <0x170>;
- anatop-delay-bit-shift = <24>;
- anatop-delay-bit-width = <2>;
- anatop-min-bit-val = <1>;
- anatop-min-voltage = <725000>;
- anatop-max-voltage = <1300000>;
- };
diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.yaml b/Documentation/devicetree/bindings/regulator/anatop-regulator.yaml
new file mode 100644
index 0000000..a8c9dd0
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Anatop Voltage Regulators
+
+maintainers:
+ - Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
+
+allOf:
+ - $ref: "regulator.yaml#"
+
+properties:
+ compatible:
+ const: fsl,anatop-regulator
+
+ regulator-name:
+ $ref: '/schemas/types.yaml#/definitions/string'
+ description: string used as a descriptive name for regulator outputs
+
+ anatop-reg-offset:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the anatop MFD register offset.
+
+ anatop-vol-bit-shift:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the bit shift for the register.
+
+ anatop-vol-bit-width:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the number of bits used in the register.
+
+ anatop-min-bit-val:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the minimum value of this register.
+
+ anatop-min-voltage:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the minimum voltage of this regulator.
+
+ anatop-max-voltage:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the maximum voltage of this regulator.
+
+ anatop-delay-reg-offset:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the anatop MFD step time register offset.
+
+ anatop-delay-bit-shift:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the bit shift for the step time register.
+
+ anatop-delay-bit-width:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the number of bits used in the step time register.
+
+ anatop-enable-bit:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing regulator enable bit offset.
+
+ vin-supply:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: input supply phandle.
+
+required:
+ - compatible
+ - regulator-name
+ - anatop-reg-offset
+ - anatop-vol-bit-shift
+ - anatop-vol-bit-width
+ - anatop-min-bit-val
+ - anatop-min-voltage
+ - anatop-max-voltage
+
+examples:
+ - |
+ regulator-vddpu {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vddpu";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <9>;
+ anatop-vol-bit-width = <5>;
+ anatop-delay-reg-offset = <0x170>;
+ anatop-delay-bit-shift = <24>;
+ anatop-delay-bit-width = <2>;
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1300000>;
+ };
--
2.7.4
^ permalink raw reply related
* Re: [PATCH 06/14] arm64: dts: sparx5: Add basic cpu support
From: Lars Povlsen @ 2020-05-18 7:43 UTC (permalink / raw)
To: Robin Murphy
Cc: Lars Povlsen, Marc Zyngier, devicetree, Alexandre Belloni,
Arnd Bergmann, Stephen Boyd, Linus Walleij, linux-kernel,
linux-clk, linux-gpio, SoC Team, Michael Turquette,
linux-arm-kernel, Olof Johansson, Microchip Linux Driver Support,
Steen Hegelund
In-Reply-To: <18c0d9ef-9a2b-31d0-b317-f051bb26a907@arm.com>
Robin Murphy writes:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 2020-05-15 16:09, Lars Povlsen wrote:
> [...]
>>>> + cpu0: cpu@0 {
>>>> + compatible = "arm,cortex-a53", "arm,armv8";
>
> Side note: only one compatible string for the real CPU please, running a
> DT bindings check should complain about that.
>
I'll change this.
>>>> + device_type = "cpu";
>>>> + reg = <0x0 0x0>;
>>>> + enable-method = "spin-table";
>>>
>>> Really? This is 2020, not 2012 any more. Surely a new platform
>>> boots using PSCI, and not *this*.
>>>
>>
>> We don't currently support PSCI. The platform does not have TrustZone,
>> hence we don't use ATF.
> AIUI, part of the purpose of ATF is to provide a nice standardised
> platform interface regardless of whether you care about Secure software
> or not. It shouldn't take much to knock up a trivial ATF port that just
> uses an internal spin-table for its PSCI backend - in fact I suspect
> that's probably just a copy-paste from the RPi3 port ;)
>
I'll change this to PSCI if that's whats expected these days. We
actually already have an ATF port. I fully understand the desire to
standardize on PSCI.
> Robin.
--
Lars Povlsen,
Microchip
^ permalink raw reply
* Re: [RFC] dt-bindings: mailbox: add doorbell support to ARM MHU
From: Viresh Kumar @ 2020-05-18 7:35 UTC (permalink / raw)
To: Jassi Brar
Cc: Arnd Bergmann, Rob Herring, Frank Rowand, Bjorn Andersson,
Vincent Guittot, linux-arm-kernel, Sudeep Holla, Devicetree List,
Linux Kernel Mailing List
In-Reply-To: <CABb+yY1wJMzakpz0h6ZxAh4Z3OB718f+Wq3RP0R4NZ_U=vRMkw@mail.gmail.com>
On 15-05-20, 11:46, Jassi Brar wrote:
> As I asked you yesterday over the call, it may help if you could share
> some numbers to back up the doomsday scenario.
Yes, I have already asked Sudeep to get some numbers for this. He will
get back to us.
> > - With the current approach it isn't possible to assign different bits
> > (or doorbell numbers) to clients from DT and the only way of doing
> > that without adding new bindings is by extending #mbox-cells to accept
> > a value of 2 as done in this patch.
> >
> I am afraid you are confused. You can use bit/doorbell-6 by passing
> 0x40 to mhu as the data to send.
That's how the code will do it, right I agree. What I was asking was
the way this information is passed from DT.
--
viresh
^ permalink raw reply
* Re: [PATCH v2 20/20] cpufreq: Return zero on success in boost sw setting
From: Viresh Kumar @ 2020-05-18 7:41 UTC (permalink / raw)
To: Serge Semin
Cc: Rafael J. Wysocki, Serge Semin, Thomas Bogendoerfer,
Rafael J. Wysocki, Ulf Hansson, Matthias Kaehlcke, Alexey Malahov,
Paul Burton, Ralf Baechle, Arnd Bergmann, Rob Herring, linux-mips,
devicetree, stable, Frederic Weisbecker, Ingo Molnar, Yue Hu,
linux-pm, linux-kernel
In-Reply-To: <20200516125203.et5gkv6ullkerjyd@mobilestation>
On 16-05-20, 15:52, Serge Semin wrote:
> On Fri, May 15, 2020 at 05:58:47PM +0200, Rafael J. Wysocki wrote:
> > > @@ -2554,7 +2554,7 @@ static int cpufreq_boost_set_sw(int state)
> > > break;
> > > }
> > > - return ret;
> > > + return ret < 0 ? ret : 0;
> > > }
> > > int cpufreq_boost_trigger_state(int state)
> >
> > IMO it is better to update the caller of this function to handle the
> > positive value possibly returned by it correctly.
>
> Could you elaborate why? Viresh seems to be ok with this solution.
And it is absolutely fine for Rafael to not agree with it :)
> As I see it the caller doesn't expect the positive value returned by the
> original freq_qos_update_request(). It just doesn't need to know whether the
> effective policy has been updated or not, it only needs to make sure the
> operations has been successful. Moreover the positive value is related only
> to the !last! active policy, which doesn't give the caller a full picture
> of the policy change anyway. So taking all of these into account I'd leave the
> fix as is.
Rafael: This function is called via a function pointer, which can call
this or a platform dependent routine (like in acpi-cpufreq.c), and it
would be reasonable IMO for the return of that callback to only look
for 0 or negative values, as is generally done in the kernel. And so
this solution looked okay to me as the positive return is coming from
the implementation detail here.
--
viresh
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: pinctrl: Add bindings for mscc,ocelot-sgpio
From: Linus Walleij @ 2020-05-18 7:40 UTC (permalink / raw)
To: Lars Povlsen
Cc: SoC Team, Rob Herring, Microchip Linux Driver Support,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:GPIO SUBSYSTEM, Linux ARM, linux-kernel@vger.kernel.org,
Alexandre Belloni
In-Reply-To: <20200513141134.25819-2-lars.povlsen@microchip.com>
On Wed, May 13, 2020 at 4:11 PM Lars Povlsen <lars.povlsen@microchip.com> wrote:
> This adds DT bindings for the Microsemi SGPIO controller, bindings
> mscc,ocelot-sgpio and mscc,luton-sgpio.
>
> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
> + microchip,sgpio-ports:
> + description: This is a 32-bit bitmask, configuring whether a
> + particular port in the controller is enabled or not. This allows
> + unused ports to be removed from the bitstream and reduce latency.
> + $ref: "/schemas/types.yaml#/definitions/uint32"
I don't know about this.
You are saying this pin controller can have up to 32 GPIO "ports"
(also known as banks).
Why can't you just represent each such port as a separate GPIO
node:
pinctrl@nnn {
gpio@0 {
....
};
gpio@1 {
....
};
....
gpio@31 {
....
};
};
Then if some of them are unused just set it to status = "disabled";
This also makes your Linux driver simpler because each GPIO port
just becomes a set of 32bit registers and you can use
select GPIO_GENERIC and bgpio_init() and save a whole
slew of standard stock code.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 07/14] dt-bindings: pinctrl: ocelot: Add Sparx5 SoC support
From: Linus Walleij @ 2020-05-18 7:33 UTC (permalink / raw)
To: Lars Povlsen
Cc: SoC Team, Arnd Bergmann, Stephen Boyd, Rob Herring,
Steen Hegelund, Microchip Linux Driver Support, Olof Johansson,
Michael Turquette,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-clk, open list:GPIO SUBSYSTEM, Linux ARM,
linux-kernel@vger.kernel.org, Alexandre Belloni
In-Reply-To: <20200513125532.24585-8-lars.povlsen@microchip.com>
On Wed, May 13, 2020 at 2:56 PM Lars Povlsen <lars.povlsen@microchip.com> wrote:
> This adds documentation for the "compatible" value designated for Sparx5
>
> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
This patch applied to the pinctrl tree.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v9 4/4] media: i2c: Add RDACM20 driver
From: Jacopo Mondi @ 2020-05-18 7:35 UTC (permalink / raw)
To: Sakari Ailus
Cc: Kieran Bingham, linux-renesas-soc, linux-media, devicetree,
linux-kernel, Mauro Carvalho Chehab, Kieran Bingham,
Laurent Pinchart, Niklas Söderlund, Hans Verkuil, Hyun Kwon,
Manivannan Sadhasivam, Rob Herring, Jacopo Mondi,
Laurent Pinchart, Niklas Söderlund, Rob Herring
In-Reply-To: <20200516223656.GB857@valkosipuli.retiisi.org.uk>
Hi Sakari
On Sun, May 17, 2020 at 01:36:57AM +0300, Sakari Ailus wrote:
> Hi Kieran,
>
[snip]
> > +
> > +/*
> > + * As the drivers supports a single MEDIA_BUS_FMT_UYVY8_2X8 format we
> > + * can harcode the pixel rate.
>
> Is this somehow the property of RDACM20? Or could you use other
> configurations here? (I'm not suggesting you should do now.)
>
As per the device datasheet RAW10 and YUYV10 is also supported.
The driver currently supports YUYV8_2X8 only.
> > + *
> > + * PCLK is fed through the system clock, programmed @88MHz.
> > + * MEDIA_BUS_FMT_UYVY8_2X8 format = 2 samples per pixel.
> > + *
> > + * Pixelrate = PCLK / 2
> > + * FPS = (OV10635_VTS * OV10635_HTS) / PixelRate
> > + * = 29,9998
> > + */
> > +#define OV10635_PIXEL_RATE (44000000)
> > +
> > +static const struct ov10635_reg {
> > + u16 reg;
> > + u8 val;
> > +} ov10635_regs_wizard[] = {
> > + { 0x301b, 0xff }, { 0x301c, 0xff }, { 0x301a, 0xff }, { 0x3011, 0x42 },
> > + { 0x6900, 0x0c }, { 0x6901, 0x19 }, { 0x3503, 0x10 }, { 0x3025, 0x03 },
> > + { 0x3003, 0x16 }, { 0x3004, 0x30 }, { 0x3005, 0x40 }, { 0x3006, 0x91 },
> > + { 0x3600, 0x74 }, { 0x3601, 0x2b }, { 0x3612, 0x00 }, { 0x3611, 0x67 },
> > + { 0x3633, 0xca }, { 0x3602, 0xaf }, { 0x3603, 0x04 }, { 0x3630, 0x28 },
> > + { 0x3631, 0x16 }, { 0x3714, 0x10 }, { 0x371d, 0x01 }, { 0x4300, 0x3a },
> > + { 0x3007, 0x01 }, { 0x3024, 0x03 }, { 0x3020, 0x0a }, { 0x3702, 0x0d },
> > + { 0x3703, 0x20 }, { 0x3704, 0x15 }, { 0x3709, 0xa8 }, { 0x370c, 0xc7 },
> > + { 0x370d, 0x80 }, { 0x3712, 0x00 }, { 0x3713, 0x20 }, { 0x3715, 0x04 },
> > + { 0x381d, 0x40 }, { 0x381c, 0x00 }, { 0x3822, 0x50 }, { 0x3824, 0x10 },
> > + { 0x3815, 0x8c }, { 0x3804, 0x05 }, { 0x3805, 0x1f }, { 0x3800, 0x00 },
> > + { 0x3801, 0x00 }, { 0x3806, 0x03 }, { 0x3807, 0x28 }, { 0x3802, 0x00 },
> > + { 0x3803, 0x07 }, { 0x3808, 0x05 }, { 0x3809, 0x00 }, { 0x380a, 0x03 },
> > + { 0x380b, 0x20 }, { 0x380c, OV10635_HTS >> 8 },
> > + { 0x380d, OV10635_HTS & 0xff }, { 0x380e, OV10635_VTS >> 8 },
> > + { 0x380f, OV10635_VTS & 0xff }, { 0x3813, 0x02 }, { 0x3811, 0x08 },
> > + { 0x381f, 0x0c }, { 0x3819, 0x04 }, { 0x3804, 0x01 }, { 0x3805, 0x00 },
> > + { 0x3828, 0x03 }, { 0x3829, 0x10 }, { 0x382a, 0x10 }, { 0x3621, 0x63 },
> > + { 0x5005, 0x08 }, { 0x56d5, 0x00 }, { 0x56d6, 0x80 }, { 0x56d7, 0x00 },
> > + { 0x56d8, 0x00 }, { 0x56d9, 0x00 }, { 0x56da, 0x80 }, { 0x56db, 0x00 },
> > + { 0x56dc, 0x00 }, { 0x56e8, 0x00 }, { 0x56e9, 0x7f }, { 0x56ea, 0x00 },
> > + { 0x56eb, 0x7f }, { 0x5100, 0x00 }, { 0x5101, 0x80 }, { 0x5102, 0x00 },
> > + { 0x5103, 0x80 }, { 0x5104, 0x00 }, { 0x5105, 0x80 }, { 0x5106, 0x00 },
> > + { 0x5107, 0x80 }, { 0x5108, 0x00 }, { 0x5109, 0x00 }, { 0x510a, 0x00 },
> > + { 0x510b, 0x00 }, { 0x510c, 0x00 }, { 0x510d, 0x00 }, { 0x510e, 0x00 },
> > + { 0x510f, 0x00 }, { 0x5110, 0x00 }, { 0x5111, 0x80 }, { 0x5112, 0x00 },
> > + { 0x5113, 0x80 }, { 0x5114, 0x00 }, { 0x5115, 0x80 }, { 0x5116, 0x00 },
> > + { 0x5117, 0x80 }, { 0x5118, 0x00 }, { 0x5119, 0x00 }, { 0x511a, 0x00 },
> > + { 0x511b, 0x00 }, { 0x511c, 0x00 }, { 0x511d, 0x00 }, { 0x511e, 0x00 },
> > + { 0x511f, 0x00 }, { 0x56d0, 0x00 }, { 0x5006, 0x04 }, { 0x5608, 0x05 },
> > + { 0x52d7, 0x06 }, { 0x528d, 0x08 }, { 0x5293, 0x12 }, { 0x52d3, 0x12 },
> > + { 0x5288, 0x06 }, { 0x5289, 0x20 }, { 0x52c8, 0x06 }, { 0x52c9, 0x20 },
> > + { 0x52cd, 0x04 }, { 0x5381, 0x00 }, { 0x5382, 0xff }, { 0x5589, 0x76 },
> > + { 0x558a, 0x47 }, { 0x558b, 0xef }, { 0x558c, 0xc9 }, { 0x558d, 0x49 },
> > + { 0x558e, 0x30 }, { 0x558f, 0x67 }, { 0x5590, 0x3f }, { 0x5591, 0xf0 },
> > + { 0x5592, 0x10 }, { 0x55a2, 0x6d }, { 0x55a3, 0x55 }, { 0x55a4, 0xc3 },
> > + { 0x55a5, 0xb5 }, { 0x55a6, 0x43 }, { 0x55a7, 0x38 }, { 0x55a8, 0x5f },
> > + { 0x55a9, 0x4b }, { 0x55aa, 0xf0 }, { 0x55ab, 0x10 }, { 0x5581, 0x52 },
> > + { 0x5300, 0x01 }, { 0x5301, 0x00 }, { 0x5302, 0x00 }, { 0x5303, 0x0e },
> > + { 0x5304, 0x00 }, { 0x5305, 0x0e }, { 0x5306, 0x00 }, { 0x5307, 0x36 },
> > + { 0x5308, 0x00 }, { 0x5309, 0xd9 }, { 0x530a, 0x00 }, { 0x530b, 0x0f },
> > + { 0x530c, 0x00 }, { 0x530d, 0x2c }, { 0x530e, 0x00 }, { 0x530f, 0x59 },
> > + { 0x5310, 0x00 }, { 0x5311, 0x7b }, { 0x5312, 0x00 }, { 0x5313, 0x22 },
> > + { 0x5314, 0x00 }, { 0x5315, 0xd5 }, { 0x5316, 0x00 }, { 0x5317, 0x13 },
> > + { 0x5318, 0x00 }, { 0x5319, 0x18 }, { 0x531a, 0x00 }, { 0x531b, 0x26 },
> > + { 0x531c, 0x00 }, { 0x531d, 0xdc }, { 0x531e, 0x00 }, { 0x531f, 0x02 },
> > + { 0x5320, 0x00 }, { 0x5321, 0x24 }, { 0x5322, 0x00 }, { 0x5323, 0x56 },
> > + { 0x5324, 0x00 }, { 0x5325, 0x85 }, { 0x5326, 0x00 }, { 0x5327, 0x20 },
> > + { 0x5609, 0x01 }, { 0x560a, 0x40 }, { 0x560b, 0x01 }, { 0x560c, 0x40 },
> > + { 0x560d, 0x00 }, { 0x560e, 0xfa }, { 0x560f, 0x00 }, { 0x5610, 0xfa },
> > + { 0x5611, 0x02 }, { 0x5612, 0x80 }, { 0x5613, 0x02 }, { 0x5614, 0x80 },
> > + { 0x5615, 0x01 }, { 0x5616, 0x2c }, { 0x5617, 0x01 }, { 0x5618, 0x2c },
> > + { 0x563b, 0x01 }, { 0x563c, 0x01 }, { 0x563d, 0x01 }, { 0x563e, 0x01 },
> > + { 0x563f, 0x03 }, { 0x5640, 0x03 }, { 0x5641, 0x03 }, { 0x5642, 0x05 },
> > + { 0x5643, 0x09 }, { 0x5644, 0x05 }, { 0x5645, 0x05 }, { 0x5646, 0x05 },
> > + { 0x5647, 0x05 }, { 0x5651, 0x00 }, { 0x5652, 0x80 }, { 0x521a, 0x01 },
> > + { 0x521b, 0x03 }, { 0x521c, 0x06 }, { 0x521d, 0x0a }, { 0x521e, 0x0e },
> > + { 0x521f, 0x12 }, { 0x5220, 0x16 }, { 0x5223, 0x02 }, { 0x5225, 0x04 },
> > + { 0x5227, 0x08 }, { 0x5229, 0x0c }, { 0x522b, 0x12 }, { 0x522d, 0x18 },
> > + { 0x522f, 0x1e }, { 0x5241, 0x04 }, { 0x5242, 0x01 }, { 0x5243, 0x03 },
> > + { 0x5244, 0x06 }, { 0x5245, 0x0a }, { 0x5246, 0x0e }, { 0x5247, 0x12 },
> > + { 0x5248, 0x16 }, { 0x524a, 0x03 }, { 0x524c, 0x04 }, { 0x524e, 0x08 },
> > + { 0x5250, 0x0c }, { 0x5252, 0x12 }, { 0x5254, 0x18 }, { 0x5256, 0x1e },
> > + /* fifo_line_length = 2*hts */
> > + { 0x4606, (2 * OV10635_HTS) >> 8 }, { 0x4607, (2 * OV10635_HTS) & 0xff },
> > + /* fifo_hsync_start = 2*(hts - xres) */
> > + { 0x460a, (2 * (OV10635_HTS - OV10635_WIDTH)) >> 8 },
> > + { 0x460b, (2 * (OV10635_HTS - OV10635_WIDTH)) & 0xff },
> > + { 0x460c, 0x00 }, { 0x4620, 0x0e },
> > + /* BT601: 0x08 is also acceptable as HS/VS mode */
> > + { 0x4700, 0x04 }, { 0x4701, 0x00 }, { 0x4702, 0x01 }, { 0x4004, 0x04 },
> > + { 0x4005, 0x18 }, { 0x4001, 0x06 }, { 0x4050, 0x22 }, { 0x4051, 0x24 },
> > + { 0x4052, 0x02 }, { 0x4057, 0x9c }, { 0x405a, 0x00 }, { 0x4202, 0x02 },
> > + { 0x3023, 0x10 }, { 0x0100, 0x01 }, { 0x0100, 0x01 }, { 0x6f10, 0x07 },
> > + { 0x6f11, 0x82 }, { 0x6f12, 0x04 }, { 0x6f13, 0x00 }, { 0xd000, 0x19 },
> > + { 0xd001, 0xa0 }, { 0xd002, 0x00 }, { 0xd003, 0x01 }, { 0xd004, 0xa9 },
> > + { 0xd005, 0xad }, { 0xd006, 0x10 }, { 0xd007, 0x40 }, { 0xd008, 0x44 },
> > + { 0xd009, 0x00 }, { 0xd00a, 0x68 }, { 0xd00b, 0x00 }, { 0xd00c, 0x15 },
> > + { 0xd00d, 0x00 }, { 0xd00e, 0x00 }, { 0xd00f, 0x00 }, { 0xd040, 0x9c },
> > + { 0xd041, 0x21 }, { 0xd042, 0xff }, { 0xd043, 0xf8 }, { 0xd044, 0xd4 },
> > + { 0xd045, 0x01 }, { 0xd046, 0x48 }, { 0xd047, 0x00 }, { 0xd048, 0xd4 },
> > + { 0xd049, 0x01 }, { 0xd04a, 0x50 }, { 0xd04b, 0x04 }, { 0xd04c, 0x18 },
> > + { 0xd04d, 0x60 }, { 0xd04e, 0x00 }, { 0xd04f, 0x01 }, { 0xd050, 0xa8 },
> > + { 0xd051, 0x63 }, { 0xd052, 0x02 }, { 0xd053, 0xa4 }, { 0xd054, 0x85 },
> > + { 0xd055, 0x43 }, { 0xd056, 0x00 }, { 0xd057, 0x00 }, { 0xd058, 0x18 },
> > + { 0xd059, 0x60 }, { 0xd05a, 0x00 }, { 0xd05b, 0x01 }, { 0xd05c, 0xa8 },
> > + { 0xd05d, 0x63 }, { 0xd05e, 0x03 }, { 0xd05f, 0xf0 }, { 0xd060, 0x98 },
> > + { 0xd061, 0xa3 }, { 0xd062, 0x00 }, { 0xd063, 0x00 }, { 0xd064, 0x8c },
> > + { 0xd065, 0x6a }, { 0xd066, 0x00 }, { 0xd067, 0x6e }, { 0xd068, 0xe5 },
> > + { 0xd069, 0x85 }, { 0xd06a, 0x18 }, { 0xd06b, 0x00 }, { 0xd06c, 0x10 },
> > + { 0xd06d, 0x00 }, { 0xd06e, 0x00 }, { 0xd06f, 0x10 }, { 0xd070, 0x9c },
> > + { 0xd071, 0x80 }, { 0xd072, 0x00 }, { 0xd073, 0x03 }, { 0xd074, 0x18 },
> > + { 0xd075, 0x60 }, { 0xd076, 0x00 }, { 0xd077, 0x01 }, { 0xd078, 0xa8 },
> > + { 0xd079, 0x63 }, { 0xd07a, 0x07 }, { 0xd07b, 0x80 }, { 0xd07c, 0x07 },
> > + { 0xd07d, 0xff }, { 0xd07e, 0xf9 }, { 0xd07f, 0x03 }, { 0xd080, 0x8c },
> > + { 0xd081, 0x63 }, { 0xd082, 0x00 }, { 0xd083, 0x00 }, { 0xd084, 0xa5 },
> > + { 0xd085, 0x6b }, { 0xd086, 0x00 }, { 0xd087, 0xff }, { 0xd088, 0x18 },
> > + { 0xd089, 0x80 }, { 0xd08a, 0x00 }, { 0xd08b, 0x01 }, { 0xd08c, 0xa8 },
> > + { 0xd08d, 0x84 }, { 0xd08e, 0x01 }, { 0xd08f, 0x04 }, { 0xd090, 0xe1 },
> > + { 0xd091, 0x6b }, { 0xd092, 0x58 }, { 0xd093, 0x00 }, { 0xd094, 0x94 },
> > + { 0xd095, 0x6a }, { 0xd096, 0x00 }, { 0xd097, 0x70 }, { 0xd098, 0xe1 },
> > + { 0xd099, 0x6b }, { 0xd09a, 0x20 }, { 0xd09b, 0x00 }, { 0xd09c, 0x95 },
> > + { 0xd09d, 0x6b }, { 0xd09e, 0x00 }, { 0xd09f, 0x00 }, { 0xd0a0, 0xe4 },
> > + { 0xd0a1, 0x8b }, { 0xd0a2, 0x18 }, { 0xd0a3, 0x00 }, { 0xd0a4, 0x0c },
> > + { 0xd0a5, 0x00 }, { 0xd0a6, 0x00 }, { 0xd0a7, 0x23 }, { 0xd0a8, 0x15 },
> > + { 0xd0a9, 0x00 }, { 0xd0aa, 0x00 }, { 0xd0ab, 0x00 }, { 0xd0ac, 0x18 },
> > + { 0xd0ad, 0x60 }, { 0xd0ae, 0x80 }, { 0xd0af, 0x06 }, { 0xd0b0, 0xa8 },
> > + { 0xd0b1, 0x83 }, { 0xd0b2, 0x40 }, { 0xd0b3, 0x08 }, { 0xd0b4, 0xa8 },
> > + { 0xd0b5, 0xe3 }, { 0xd0b6, 0x38 }, { 0xd0b7, 0x2a }, { 0xd0b8, 0xa8 },
> > + { 0xd0b9, 0xc3 }, { 0xd0ba, 0x40 }, { 0xd0bb, 0x09 }, { 0xd0bc, 0xa8 },
> > + { 0xd0bd, 0xa3 }, { 0xd0be, 0x38 }, { 0xd0bf, 0x29 }, { 0xd0c0, 0x8c },
> > + { 0xd0c1, 0x65 }, { 0xd0c2, 0x00 }, { 0xd0c3, 0x00 }, { 0xd0c4, 0xd8 },
> > + { 0xd0c5, 0x04 }, { 0xd0c6, 0x18 }, { 0xd0c7, 0x00 }, { 0xd0c8, 0x8c },
> > + { 0xd0c9, 0x67 }, { 0xd0ca, 0x00 }, { 0xd0cb, 0x00 }, { 0xd0cc, 0xd8 },
> > + { 0xd0cd, 0x06 }, { 0xd0ce, 0x18 }, { 0xd0cf, 0x00 }, { 0xd0d0, 0x18 },
> > + { 0xd0d1, 0x60 }, { 0xd0d2, 0x80 }, { 0xd0d3, 0x06 }, { 0xd0d4, 0xa8 },
> > + { 0xd0d5, 0xe3 }, { 0xd0d6, 0x67 }, { 0xd0d7, 0x02 }, { 0xd0d8, 0xa9 },
> > + { 0xd0d9, 0x03 }, { 0xd0da, 0x67 }, { 0xd0db, 0x03 }, { 0xd0dc, 0xa8 },
> > + { 0xd0dd, 0xc3 }, { 0xd0de, 0x3d }, { 0xd0df, 0x05 }, { 0xd0e0, 0x8c },
> > + { 0xd0e1, 0x66 }, { 0xd0e2, 0x00 }, { 0xd0e3, 0x00 }, { 0xd0e4, 0xb8 },
> > + { 0xd0e5, 0x63 }, { 0xd0e6, 0x00 }, { 0xd0e7, 0x18 }, { 0xd0e8, 0xb8 },
> > + { 0xd0e9, 0x63 }, { 0xd0ea, 0x00 }, { 0xd0eb, 0x98 }, { 0xd0ec, 0xbc },
> > + { 0xd0ed, 0x03 }, { 0xd0ee, 0x00 }, { 0xd0ef, 0x00 }, { 0xd0f0, 0x10 },
> > + { 0xd0f1, 0x00 }, { 0xd0f2, 0x00 }, { 0xd0f3, 0x16 }, { 0xd0f4, 0xb8 },
> > + { 0xd0f5, 0x83 }, { 0xd0f6, 0x00 }, { 0xd0f7, 0x19 }, { 0xd0f8, 0x8c },
> > + { 0xd0f9, 0x67 }, { 0xd0fa, 0x00 }, { 0xd0fb, 0x00 }, { 0xd0fc, 0xb8 },
> > + { 0xd0fd, 0xa4 }, { 0xd0fe, 0x00 }, { 0xd0ff, 0x98 }, { 0xd100, 0xb8 },
> > + { 0xd101, 0x83 }, { 0xd102, 0x00 }, { 0xd103, 0x08 }, { 0xd104, 0x8c },
> > + { 0xd105, 0x68 }, { 0xd106, 0x00 }, { 0xd107, 0x00 }, { 0xd108, 0xe0 },
> > + { 0xd109, 0x63 }, { 0xd10a, 0x20 }, { 0xd10b, 0x04 }, { 0xd10c, 0xe0 },
> > + { 0xd10d, 0x65 }, { 0xd10e, 0x18 }, { 0xd10f, 0x00 }, { 0xd110, 0xa4 },
> > + { 0xd111, 0x83 }, { 0xd112, 0xff }, { 0xd113, 0xff }, { 0xd114, 0xb8 },
> > + { 0xd115, 0x64 }, { 0xd116, 0x00 }, { 0xd117, 0x48 }, { 0xd118, 0xd8 },
> > + { 0xd119, 0x07 }, { 0xd11a, 0x18 }, { 0xd11b, 0x00 }, { 0xd11c, 0xd8 },
> > + { 0xd11d, 0x08 }, { 0xd11e, 0x20 }, { 0xd11f, 0x00 }, { 0xd120, 0x9c },
> > + { 0xd121, 0x60 }, { 0xd122, 0x00 }, { 0xd123, 0x00 }, { 0xd124, 0xd8 },
> > + { 0xd125, 0x06 }, { 0xd126, 0x18 }, { 0xd127, 0x00 }, { 0xd128, 0x00 },
> > + { 0xd129, 0x00 }, { 0xd12a, 0x00 }, { 0xd12b, 0x08 }, { 0xd12c, 0x15 },
> > + { 0xd12d, 0x00 }, { 0xd12e, 0x00 }, { 0xd12f, 0x00 }, { 0xd130, 0x8c },
> > + { 0xd131, 0x6a }, { 0xd132, 0x00 }, { 0xd133, 0x76 }, { 0xd134, 0xbc },
> > + { 0xd135, 0x23 }, { 0xd136, 0x00 }, { 0xd137, 0x00 }, { 0xd138, 0x13 },
> > + { 0xd139, 0xff }, { 0xd13a, 0xff }, { 0xd13b, 0xe6 }, { 0xd13c, 0x18 },
> > + { 0xd13d, 0x60 }, { 0xd13e, 0x80 }, { 0xd13f, 0x06 }, { 0xd140, 0x03 },
> > + { 0xd141, 0xff }, { 0xd142, 0xff }, { 0xd143, 0xdd }, { 0xd144, 0xa8 },
> > + { 0xd145, 0x83 }, { 0xd146, 0x40 }, { 0xd147, 0x08 }, { 0xd148, 0x85 },
> > + { 0xd149, 0x21 }, { 0xd14a, 0x00 }, { 0xd14b, 0x00 }, { 0xd14c, 0x85 },
> > + { 0xd14d, 0x41 }, { 0xd14e, 0x00 }, { 0xd14f, 0x04 }, { 0xd150, 0x44 },
> > + { 0xd151, 0x00 }, { 0xd152, 0x48 }, { 0xd153, 0x00 }, { 0xd154, 0x9c },
> > + { 0xd155, 0x21 }, { 0xd156, 0x00 }, { 0xd157, 0x08 }, { 0x6f0e, 0x03 },
> > + { 0x6f0f, 0x00 }, { 0x460e, 0x08 }, { 0x460f, 0x01 }, { 0x4610, 0x00 },
> > + { 0x4611, 0x01 }, { 0x4612, 0x00 }, { 0x4613, 0x01 },
> > + /* 8 bits */
> > + { 0x4605, 0x08 },
> > + /* Swap data bits order [9:0] -> [0:9] */
> > + { 0x4709, 0x10 }, { 0x4608, 0x00 }, { 0x4609, 0x08 }, { 0x6804, 0x00 },
> > + { 0x6805, 0x06 }, { 0x6806, 0x00 }, { 0x5120, 0x00 }, { 0x3510, 0x00 },
> > + { 0x3504, 0x00 }, { 0x6800, 0x00 }, { 0x6f0d, 0x01 },
> > + /* PCLK falling edge */
> > + { 0x4708, 0x01 }, { 0x5000, 0xff }, { 0x5001, 0xbf }, { 0x5002, 0x7e },
> > + { 0x503d, 0x00 }, { 0xc450, 0x01 }, { 0xc452, 0x04 }, { 0xc453, 0x00 },
> > + { 0xc454, 0x00 }, { 0xc455, 0x01 }, { 0xc456, 0x01 }, { 0xc457, 0x00 },
> > + { 0xc458, 0x00 }, { 0xc459, 0x00 }, { 0xc45b, 0x00 }, { 0xc45c, 0x01 },
> > + { 0xc45d, 0x00 }, { 0xc45e, 0x00 }, { 0xc45f, 0x00 }, { 0xc460, 0x00 },
> > + { 0xc461, 0x01 }, { 0xc462, 0x01 }, { 0xc464, 0x03 }, { 0xc465, 0x00 },
> > + { 0xc466, 0x8a }, { 0xc467, 0x00 }, { 0xc468, 0x86 }, { 0xc469, 0x00 },
> > + { 0xc46a, 0x40 }, { 0xc46b, 0x50 }, { 0xc46c, 0x30 }, { 0xc46d, 0x28 },
> > + { 0xc46e, 0x60 }, { 0xc46f, 0x40 }, { 0xc47c, 0x01 }, { 0xc47d, 0x38 },
> > + { 0xc47e, 0x00 }, { 0xc47f, 0x00 }, { 0xc480, 0x00 }, { 0xc481, 0xff },
> > + { 0xc482, 0x00 }, { 0xc483, 0x40 }, { 0xc484, 0x00 }, { 0xc485, 0x18 },
> > + { 0xc486, 0x00 }, { 0xc487, 0x18 },
> > + { 0xc488, (OV10635_VTS - 8) * 16 >> 8},
> > + { 0xc489, (OV10635_VTS - 8) * 16 & 0xff},
> > + { 0xc48a, (OV10635_VTS - 8) * 16 >> 8},
> > + { 0xc48b, (OV10635_VTS - 8) * 16 & 0xff}, { 0xc48c, 0x00 },
> > + { 0xc48d, 0x04 }, { 0xc48e, 0x00 }, { 0xc48f, 0x04 }, { 0xc490, 0x03 },
> > + { 0xc492, 0x20 }, { 0xc493, 0x08 }, { 0xc498, 0x02 }, { 0xc499, 0x00 },
> > + { 0xc49a, 0x02 }, { 0xc49b, 0x00 }, { 0xc49c, 0x02 }, { 0xc49d, 0x00 },
> > + { 0xc49e, 0x02 }, { 0xc49f, 0x60 }, { 0xc4a0, 0x03 }, { 0xc4a1, 0x00 },
> > + { 0xc4a2, 0x04 }, { 0xc4a3, 0x00 }, { 0xc4a4, 0x00 }, { 0xc4a5, 0x10 },
> > + { 0xc4a6, 0x00 }, { 0xc4a7, 0x40 }, { 0xc4a8, 0x00 }, { 0xc4a9, 0x80 },
> > + { 0xc4aa, 0x0d }, { 0xc4ab, 0x00 }, { 0xc4ac, 0x0f }, { 0xc4ad, 0xc0 },
> > + { 0xc4b4, 0x01 }, { 0xc4b5, 0x01 }, { 0xc4b6, 0x00 }, { 0xc4b7, 0x01 },
> > + { 0xc4b8, 0x00 }, { 0xc4b9, 0x01 }, { 0xc4ba, 0x01 }, { 0xc4bb, 0x00 },
> > + { 0xc4bc, 0x01 }, { 0xc4bd, 0x60 }, { 0xc4be, 0x02 }, { 0xc4bf, 0x33 },
> > + { 0xc4c8, 0x03 }, { 0xc4c9, 0xd0 }, { 0xc4ca, 0x0e }, { 0xc4cb, 0x00 },
> > + { 0xc4cc, 0x0e }, { 0xc4cd, 0x51 }, { 0xc4ce, 0x0e }, { 0xc4cf, 0x51 },
> > + { 0xc4d0, 0x04 }, { 0xc4d1, 0x80 }, { 0xc4e0, 0x04 }, { 0xc4e1, 0x02 },
> > + { 0xc4e2, 0x01 }, { 0xc4e4, 0x10 }, { 0xc4e5, 0x20 }, { 0xc4e6, 0x30 },
> > + { 0xc4e7, 0x40 }, { 0xc4e8, 0x50 }, { 0xc4e9, 0x60 }, { 0xc4ea, 0x70 },
> > + { 0xc4eb, 0x80 }, { 0xc4ec, 0x90 }, { 0xc4ed, 0xa0 }, { 0xc4ee, 0xb0 },
> > + { 0xc4ef, 0xc0 }, { 0xc4f0, 0xd0 }, { 0xc4f1, 0xe0 }, { 0xc4f2, 0xf0 },
> > + { 0xc4f3, 0x80 }, { 0xc4f4, 0x00 }, { 0xc4f5, 0x20 }, { 0xc4f6, 0x02 },
> > + { 0xc4f7, 0x00 }, { 0xc4f8, 0x00 }, { 0xc4f9, 0x00 }, { 0xc4fa, 0x00 },
> > + { 0xc4fb, 0x01 }, { 0xc4fc, 0x01 }, { 0xc4fd, 0x00 }, { 0xc4fe, 0x04 },
> > + { 0xc4ff, 0x02 }, { 0xc500, 0x48 }, { 0xc501, 0x74 }, { 0xc502, 0x58 },
> > + { 0xc503, 0x80 }, { 0xc504, 0x05 }, { 0xc505, 0x80 }, { 0xc506, 0x03 },
> > + { 0xc507, 0x80 }, { 0xc508, 0x01 }, { 0xc509, 0xc0 }, { 0xc50a, 0x01 },
> > + { 0xc50b, 0xa0 }, { 0xc50c, 0x01 }, { 0xc50d, 0x2c }, { 0xc50e, 0x01 },
> > + { 0xc50f, 0x0a }, { 0xc510, 0x00 }, { 0xc511, 0x00 }, { 0xc512, 0xe5 },
> > + { 0xc513, 0x14 }, { 0xc514, 0x04 }, { 0xc515, 0x00 }, { 0xc518, OV10635_VTS >> 8},
> > + { 0xc519, OV10635_VTS & 0xff}, { 0xc51a, OV10635_HTS >> 8},
> > + { 0xc51b, OV10635_HTS & 0xff}, { 0xc2e0, 0x00 }, { 0xc2e1, 0x51 },
> > + { 0xc2e2, 0x00 }, { 0xc2e3, 0xd6 }, { 0xc2e4, 0x01 }, { 0xc2e5, 0x5e },
> > + { 0xc2e9, 0x01 }, { 0xc2ea, 0x7a }, { 0xc2eb, 0x90 }, { 0xc2ed, 0x00 },
> > + { 0xc2ee, 0x7a }, { 0xc2ef, 0x64 }, { 0xc308, 0x00 }, { 0xc309, 0x00 },
> > + { 0xc30a, 0x00 }, { 0xc30c, 0x00 }, { 0xc30d, 0x01 }, { 0xc30e, 0x00 },
> > + { 0xc30f, 0x00 }, { 0xc310, 0x01 }, { 0xc311, 0x60 }, { 0xc312, 0xff },
> > + { 0xc313, 0x08 }, { 0xc314, 0x01 }, { 0xc315, 0x00 }, { 0xc316, 0xff },
> > + { 0xc317, 0x0b }, { 0xc318, 0x00 }, { 0xc319, 0x0c }, { 0xc31a, 0x00 },
> > + { 0xc31b, 0xe0 }, { 0xc31c, 0x00 }, { 0xc31d, 0x14 }, { 0xc31e, 0x00 },
> > + { 0xc31f, 0xc5 }, { 0xc320, 0xff }, { 0xc321, 0x4b }, { 0xc322, 0xff },
> > + { 0xc323, 0xf0 }, { 0xc324, 0xff }, { 0xc325, 0xe8 }, { 0xc326, 0x00 },
> > + { 0xc327, 0x46 }, { 0xc328, 0xff }, { 0xc329, 0xd2 }, { 0xc32a, 0xff },
> > + { 0xc32b, 0xe4 }, { 0xc32c, 0xff }, { 0xc32d, 0xbb }, { 0xc32e, 0x00 },
> > + { 0xc32f, 0x61 }, { 0xc330, 0xff }, { 0xc331, 0xf9 }, { 0xc332, 0x00 },
> > + { 0xc333, 0xd9 }, { 0xc334, 0x00 }, { 0xc335, 0x2e }, { 0xc336, 0x00 },
> > + { 0xc337, 0xb1 }, { 0xc338, 0xff }, { 0xc339, 0x64 }, { 0xc33a, 0xff },
> > + { 0xc33b, 0xeb }, { 0xc33c, 0xff }, { 0xc33d, 0xe8 }, { 0xc33e, 0x00 },
> > + { 0xc33f, 0x48 }, { 0xc340, 0xff }, { 0xc341, 0xd0 }, { 0xc342, 0xff },
> > + { 0xc343, 0xed }, { 0xc344, 0xff }, { 0xc345, 0xad }, { 0xc346, 0x00 },
> > + { 0xc347, 0x66 }, { 0xc348, 0x01 }, { 0xc349, 0x00 }, { 0x6700, 0x04 },
> > + { 0x6701, 0x7b }, { 0x6702, 0xfd }, { 0x6703, 0xf9 }, { 0x6704, 0x3d },
> > + { 0x6705, 0x71 }, { 0x6706, 0x78 }, { 0x6708, 0x05 }, { 0x6f06, 0x6f },
> > + { 0x6f07, 0x00 }, { 0x6f0a, 0x6f }, { 0x6f0b, 0x00 }, { 0x6f00, 0x03 },
> > + { 0xc34c, 0x01 }, { 0xc34d, 0x00 }, { 0xc34e, 0x46 }, { 0xc34f, 0x55 },
> > + { 0xc350, 0x00 }, { 0xc351, 0x40 }, { 0xc352, 0x00 }, { 0xc353, 0xff },
> > + { 0xc354, 0x04 }, { 0xc355, 0x08 }, { 0xc356, 0x01 }, { 0xc357, 0xef },
> > + { 0xc358, 0x30 }, { 0xc359, 0x01 }, { 0xc35a, 0x64 }, { 0xc35b, 0x46 },
> > + { 0xc35c, 0x00 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 },
> > + { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 },
> > + { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 },
> > + { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 },
> > + { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 },
> > + { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 },
> > + { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0xc261, 0x01 },
> > + { 0x301b, 0xf0 }, { 0x301c, 0xf0 }, { 0x301a, 0xf0 }, { 0x6f00, 0xc3 },
> > + { 0xc46a, 0x30 }, { 0xc46d, 0x20 }, { 0xc464, 0x84 }, { 0xc465, 0x00 },
> > + { 0x6f00, 0x03 }, { 0x6f00, 0x43 }, { 0x381c, 0x00 }, { 0x381d, 0x40 },
> > + { 0xc454, 0x01 }, { 0x6f00, 0xc3 }, { 0xc454, 0x00 }, { 0xc4b1, 0x02 },
> > + { 0xc4b2, 0x01 }, { 0xc4b3, 0x03 }, { 0x6f00, 0x03 }, { 0x6f00, 0x43 },
> > + /* enable FSIN (FRAMESYNC input) functionality */
> > + { 0x3832, (0x0d + 2 * 0x20 + 0x15 + 38) >> 8 },
> > + { 0x3833, (0x0d + 2 * 0x20 + 0x15 + 38) & 0xff },
> > + { 0x3834, OV10635_VTS >> 8 }, { 0x3835, OV10635_VTS & 0xff },
> > + { 0x302e, 0x01 },
>
> Ergh.
>
I know :(
> > +};
> > +
> > +struct rdacm20_device {
> > + struct device *dev;
> > + struct max9271_device *serializer;
> > + struct i2c_client *sensor;
> > + struct v4l2_subdev sd;
> > + struct media_pad pad;
> > + struct v4l2_ctrl_handler ctrls;
> > + u32 addrs[2];
> > +};
> > +
> > +static inline struct rdacm20_device *sd_to_rdacm20(struct v4l2_subdev *sd)
> > +{
> > + return container_of(sd, struct rdacm20_device, sd);
> > +}
> > +
> > +static inline struct rdacm20_device *i2c_to_rdacm20(struct i2c_client *client)
> > +{
> > + return sd_to_rdacm20(i2c_get_clientdata(client));
> > +}
> > +
> > +static int ov10635_read16(struct rdacm20_device *dev, u16 reg)
> > +{
> > + u8 buf[2] = { reg >> 8, reg & 0xff };
> > + int ret;
> > +
> > + ret = i2c_master_send(dev->sensor, buf, 2);
> > + if (ret != 2) {
> > + dev_dbg(dev->dev, "%s: register 0x%04x write failed (%d)\n",
> > + __func__, reg, ret);
> > + return ret;
> > + }
> > +
> > + ret = i2c_master_recv(dev->sensor, buf, 2);
> > + if (ret < 0) {
> > + dev_dbg(dev->dev, "%s: register 0x%04x read failed (%d)\n",
> > + __func__, reg, ret);
> > + return ret;
> > + }
> > +
> > + return (buf[0] << 8) | buf[1];
> > +}
> > +
> > +static int __ov10635_write(struct rdacm20_device *dev, u16 reg, u8 val)
> > +{
> > + u8 buf[3] = { reg >> 8, reg & 0xff, val };
> > + int ret;
> > +
> > + dev_dbg(dev->dev, "%s(0x%04x, 0x%02x)\n", __func__, reg, val);
> > +
> > + ret = i2c_master_send(dev->sensor, buf, 3);
> > + return ret < 0 ? ret : 0;
> > +}
> > +
> > +static int ov10635_write(struct rdacm20_device *dev, u16 reg, u8 val)
> > +{
> > + int ret;
> > +
> > + ret = __ov10635_write(dev, reg, val);
> > + if (ret < 0)
> > + dev_err(dev->dev, "%s: register 0x%04x write failed (%d)\n",
> > + __func__, reg, ret);
> > +
> > + return ret;
> > +}
> > +
> > +static int ov10635_set_regs(struct rdacm20_device *dev,
> > + const struct ov10635_reg *regs,
> > + unsigned int nr_regs)
> > +{
> > + unsigned int i;
> > + int ret;
> > +
> > + for (i = 0; i < nr_regs; i++) {
> > + ret = __ov10635_write(dev, regs[i].reg, regs[i].val);
> > + if (ret) {
> > + dev_err(dev->dev,
> > + "%s: register %u (0x%04x) write failed (%d)\n",
> > + __func__, i, regs[i].reg, ret);
> > + return ret;
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int rdacm20_s_stream(struct v4l2_subdev *sd, int enable)
> > +{
> > + struct rdacm20_device *dev = sd_to_rdacm20(sd);
> > +
> > + return max9271_set_serial_link(dev->serializer, enable);
> > +}
> > +
> > +static int rdacm20_enum_mbus_code(struct v4l2_subdev *sd,
> > + struct v4l2_subdev_pad_config *cfg,
> > + struct v4l2_subdev_mbus_code_enum *code)
> > +{
> > + if (code->pad || code->index > 0)
> > + return -EINVAL;
> > +
> > + code->code = MEDIA_BUS_FMT_UYVY8_2X8;
> > +
> > + return 0;
> > +}
> > +
> > +static int rdacm20_get_fmt(struct v4l2_subdev *sd,
> > + struct v4l2_subdev_pad_config *cfg,
> > + struct v4l2_subdev_format *format)
> > +{
> > + struct v4l2_mbus_framefmt *mf = &format->format;
> > +
> > + if (format->pad)
> > + return -EINVAL;
> > +
> > + mf->width = OV10635_WIDTH;
> > + mf->height = OV10635_HEIGHT;
> > + mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
> > + mf->colorspace = V4L2_COLORSPACE_RAW;
> > + mf->field = V4L2_FIELD_NONE;
> > + mf->ycbcr_enc = V4L2_YCBCR_ENC_601;
> > + mf->quantization = V4L2_QUANTIZATION_FULL_RANGE;
> > + mf->xfer_func = V4L2_XFER_FUNC_NONE;
> > +
> > + return 0;
> > +}
> > +
> > +static struct v4l2_subdev_video_ops rdacm20_video_ops = {
> > + .s_stream = rdacm20_s_stream,
> > +};
> > +
> > +static const struct v4l2_subdev_pad_ops rdacm20_subdev_pad_ops = {
> > + .enum_mbus_code = rdacm20_enum_mbus_code,
> > + .get_fmt = rdacm20_get_fmt,
> > + .set_fmt = rdacm20_get_fmt,
> > +};
> > +
> > +static struct v4l2_subdev_ops rdacm20_subdev_ops = {
> > + .video = &rdacm20_video_ops,
> > + .pad = &rdacm20_subdev_pad_ops,
> > +};
> > +
> > +static int rdacm20_initialize(struct rdacm20_device *dev)
> > +{
> > + unsigned int retry = 3;
> > + int ret;
> > +
> > + /* Verify communication with the MAX9271: ping to wakeup. */
> > + dev->serializer->client->addr = MAX9271_DEFAULT_ADDR;
> > + i2c_smbus_read_byte(dev->serializer->client);
> > +
> > + /* Serial link disabled during config as it needs a valid pixel clock. */
> > + ret = max9271_set_serial_link(dev->serializer, false);
> > + if (ret)
> > + return ret;
> > +
> > + /*
> > + * Ensure that we have a good link configuration before attempting to
> > + * identify the device.
> > + */
> > + max9271_configure_i2c(dev->serializer, MAX9271_I2CSLVSH_469NS_234NS |
> > + MAX9271_I2CSLVTO_1024US |
> > + MAX9271_I2CMSTBT_105KBPS);
> > +
> > + max9271_configure_gmsl_link(dev->serializer);
> > +
> > + ret = max9271_verify_id(dev->serializer);
> > + if (ret < 0)
> > + return ret;
> > +
> > + ret = max9271_set_address(dev->serializer, dev->addrs[0]);
> > + if (ret < 0)
> > + return ret;
> > + dev->serializer->client->addr = dev->addrs[0];
> > +
> > + /*
> > + * Reset the sensor by cycling the OV10635 reset signal connected to the
> > + * MAX9271 GPIO1 and verify communication with the OV10635.
> > + */
> > + max9271_clear_gpios(dev->serializer, MAX9271_GPIO1OUT);
> > + mdelay(10);
>
> Why mdelay(), a busy loop and not msleep()??? Same below.
>
As I don't recall a reason that could very well be a leftover from the
BSP driver. I'll fix it.
Thanks
j
> > + max9271_set_gpios(dev->serializer, MAX9271_GPIO1OUT);
> > + mdelay(10);
> > +
> > +again:
> > + ret = ov10635_read16(dev, OV10635_PID);
> > + if (ret < 0) {
> > + if (retry--)
> > + goto again;
> > +
> > + dev_err(dev->dev, "OV10635 ID read failed (%d)\n",
> > + ret);
> > + return -ENXIO;
> > + }
> > +
> > + if (ret != OV10635_VERSION) {
> > + if (retry--)
> > + goto again;
> > +
> > + dev_err(dev->dev, "OV10635 ID mismatch (0x%04x)\n",
> > + ret);
> > + return -ENXIO;
> > + }
> > +
> > + /* Change the sensor I2C address. */
> > + ret = ov10635_write(dev, OV10635_SC_CMMN_SCCB_ID,
> > + (dev->addrs[1] << 1) |
> > + OV10635_SC_CMMN_SCCB_ID_SELECT);
> > + if (ret < 0) {
> > + dev_err(dev->dev,
> > + "OV10635 I2C address change failed (%d)\n", ret);
> > + return ret;
> > + }
> > + dev->sensor->addr = dev->addrs[1];
> > + usleep_range(3500, 5000);
> > +
> > + /* Program the 0V10635 initial configuration. */
> > + ret = ov10635_set_regs(dev, ov10635_regs_wizard,
> > + ARRAY_SIZE(ov10635_regs_wizard));
> > + if (ret)
> > + return ret;
> > +
> > + dev_info(dev->dev, "Identified MAX9271 + OV10635 device\n");
> > +
> > + return 0;
> > +}
> > +
> > +static int rdacm20_probe(struct i2c_client *client)
> > +{
> > + struct rdacm20_device *dev;
> > + struct fwnode_handle *ep;
> > + int ret;
> > +
> > + dev = devm_kzalloc(&client->dev, sizeof(*dev), GFP_KERNEL);
> > + if (!dev)
> > + return -ENOMEM;
> > + dev->dev = &client->dev;
> > +
> > + dev->serializer = devm_kzalloc(&client->dev, sizeof(*dev->serializer),
> > + GFP_KERNEL);
> > + if (!dev->serializer)
> > + return -ENOMEM;
> > +
> > + dev->serializer->client = client;
> > +
> > + ret = of_property_read_u32_array(client->dev.of_node, "reg",
> > + dev->addrs, 2);
> > + if (ret < 0) {
> > + dev_err(dev->dev, "Invalid DT reg property: %d\n", ret);
> > + return -EINVAL;
> > + }
> > +
> > + /* Create the dummy I2C client for the sensor. */
> > + dev->sensor = i2c_new_dummy_device(client->adapter,
> > + OV10635_I2C_ADDRESS);
> > + if (IS_ERR(dev->sensor)) {
> > + ret = PTR_ERR(dev->sensor);
> > + goto error;
> > + }
> > +
> > + /* Initialize the hardware. */
> > + ret = rdacm20_initialize(dev);
> > + if (ret < 0)
> > + goto error;
> > +
> > + /* Initialize and register the subdevice. */
> > + v4l2_i2c_subdev_init(&dev->sd, client, &rdacm20_subdev_ops);
> > + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
> > +
> > + v4l2_ctrl_handler_init(&dev->ctrls, 1);
> > + v4l2_ctrl_new_std(&dev->ctrls, NULL, V4L2_CID_PIXEL_RATE,
> > + OV10635_PIXEL_RATE, OV10635_PIXEL_RATE, 1,
> > + OV10635_PIXEL_RATE);
> > + dev->sd.ctrl_handler = &dev->ctrls;
> > +
> > + ret = dev->ctrls.error;
> > + if (ret)
> > + goto error_free_ctrls;
> > +
> > + dev->pad.flags = MEDIA_PAD_FL_SOURCE;
> > + dev->sd.entity.flags |= MEDIA_ENT_F_CAM_SENSOR;
> > + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad);
> > + if (ret < 0)
> > + goto error_free_ctrls;
> > +
> > + ep = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL);
> > + if (!ep) {
> > + dev_err(&client->dev,
> > + "Unable to get endpoint in node %pOF\n",
> > + client->dev.of_node);
> > + ret = -ENOENT;
> > + goto error_free_ctrls;
> > + }
> > + dev->sd.fwnode = ep;
> > +
> > + ret = v4l2_async_register_subdev(&dev->sd);
> > + if (ret)
> > + goto error_put_node;
> > +
> > + return 0;
> > +
> > +error_put_node:
> > + fwnode_handle_put(ep);
> > +error_free_ctrls:
> > + v4l2_ctrl_handler_free(&dev->ctrls);
> > +error:
> > + media_entity_cleanup(&dev->sd.entity);
> > + if (dev->sensor)
> > + i2c_unregister_device(dev->sensor);
> > +
> > + dev_err(&client->dev, "probe failed\n");
> > +
> > + return ret;
> > +}
> > +
> > +static int rdacm20_remove(struct i2c_client *client)
> > +{
> > + struct rdacm20_device *dev = i2c_to_rdacm20(client);
> > +
> > + fwnode_handle_put(dev->sd.fwnode);
> > + v4l2_async_unregister_subdev(&dev->sd);
> > + v4l2_ctrl_handler_free(&dev->ctrls);
> > + media_entity_cleanup(&dev->sd.entity);
> > + i2c_unregister_device(dev->sensor);
> > +
> > + return 0;
> > +}
> > +
> > +static void rdacm20_shutdown(struct i2c_client *client)
> > +{
> > + struct rdacm20_device *dev = i2c_to_rdacm20(client);
> > +
> > + /* make sure stream off during shutdown (reset/reboot) */
> > + rdacm20_s_stream(&dev->sd, 0);
> > +}
> > +
> > +static const struct of_device_id rdacm20_of_ids[] = {
> > + { .compatible = "imi,rdacm20", },
> > + { }
> > +};
> > +MODULE_DEVICE_TABLE(of, rdacm20_of_ids);
> > +
> > +static struct i2c_driver rdacm20_i2c_driver = {
> > + .driver = {
> > + .name = "rdacm20",
> > + .of_match_table = rdacm20_of_ids,
> > + },
> > + .probe_new = rdacm20_probe,
> > + .remove = rdacm20_remove,
> > + .shutdown = rdacm20_shutdown,
> > +};
> > +
> > +module_i2c_driver(rdacm20_i2c_driver);
> > +
> > +MODULE_DESCRIPTION("GMSL Camera driver for RDACM20");
> > +MODULE_AUTHOR("Vladimir Barinov");
> > +MODULE_LICENSE("GPL");
>
> --
> Regards,
>
> Sakari Ailus
^ permalink raw reply
* Re: [PATCH 03/14] pinctrl: ocelot: Fix GPIO interrupt decoding on Jaguar2
From: Linus Walleij @ 2020-05-18 7:31 UTC (permalink / raw)
To: Lars Povlsen
Cc: SoC Team, Arnd Bergmann, Stephen Boyd, Steen Hegelund,
Microchip Linux Driver Support, Olof Johansson, Michael Turquette,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-clk, open list:GPIO SUBSYSTEM, Linux ARM,
linux-kernel@vger.kernel.org, Alexandre Belloni
In-Reply-To: <20200513125532.24585-4-lars.povlsen@microchip.com>
On Wed, May 13, 2020 at 2:56 PM Lars Povlsen <lars.povlsen@microchip.com> wrote:
> This fixes a problem with using the GPIO as an interrupt on Jaguar2
> (and similar), as the register layout of the platforms with 64 GPIO's
> are pairwise, such that the original offset must be multiplied with
> the platform stride.
>
> Fixes: da801ab56ad8 pinctrl: ocelot: add MSCC Jaguar2 support.
> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
This patch applied to the pinctrl tree.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 02/14] pinctrl: ocelot: Remove instance number from pin functions
From: Linus Walleij @ 2020-05-18 7:31 UTC (permalink / raw)
To: Lars Povlsen
Cc: SoC Team, Arnd Bergmann, Stephen Boyd, Steen Hegelund,
Microchip Linux Driver Support, Olof Johansson, Michael Turquette,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-clk, open list:GPIO SUBSYSTEM, Linux ARM,
linux-kernel@vger.kernel.org, Alexandre Belloni
In-Reply-To: <20200513125532.24585-3-lars.povlsen@microchip.com>
On Wed, May 13, 2020 at 2:56 PM Lars Povlsen <lars.povlsen@microchip.com> wrote:
> This patch removes the instance number from the "miim", "reco_clk" and
> "sfp" pin function.
>
> The change needed is to prepare the driver for adding new platforms
> with more of these instances. The instance number is also redundant,
> as this is implicit for each pin.
>
> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
This patch applied to the pinctrl tree.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 01/14] pinctrl: ocelot: Should register GPIO's even if not irq controller
From: Linus Walleij @ 2020-05-18 7:29 UTC (permalink / raw)
To: Lars Povlsen
Cc: SoC Team, Arnd Bergmann, Stephen Boyd, Steen Hegelund,
Microchip Linux Driver Support, Olof Johansson, Michael Turquette,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-clk, open list:GPIO SUBSYSTEM, Linux ARM,
linux-kernel@vger.kernel.org, Alexandre Belloni
In-Reply-To: <20200513125532.24585-2-lars.povlsen@microchip.com>
On Wed, May 13, 2020 at 2:56 PM Lars Povlsen <lars.povlsen@microchip.com> wrote:
> This fixes the situation where the GPIO controller is not used as an
> interrupt controller as well.
>
> Previously, the driver would silently fail to register even the
> GPIO's. With this change, the driver will only register as an
> interrupt controller if a parent interrupt is provided.
>
> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
This patch applied to the pinctrl tree.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v3 6/7] pinctrl: madera: Move binding over to dtschema
From: Linus Walleij @ 2020-05-18 7:27 UTC (permalink / raw)
To: Charles Keepax
Cc: Chanwoo Choi, Rob Herring, Lee Jones, Mark Brown, MyungJoo Ham,
Liam Girdwood, linux-kernel@vger.kernel.org,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
patches
In-Reply-To: <20200513095720.8867-6-ckeepax@opensource.cirrus.com>
On Wed, May 13, 2020 at 11:57 AM Charles Keepax
<ckeepax@opensource.cirrus.com> wrote:
> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Looks good to me.
I assume Rob will apply this?
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* Re: [Linux-stm32] [PATCH v3 1/2] dt-bindings: serial: Document CTS/RTS gpios in STM32 UART
From: Erwan LE RAY @ 2020-05-18 7:25 UTC (permalink / raw)
To: Geert Uytterhoeven, mani@kernel.org
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Greg KH, Linux Kernel Mailing List, Andy Shevchenko, Rob Herring,
Maxime Coquelin, open list:SERIAL DRIVERS, Fabrice GASNIER,
linux-stm32@st-md-mailman.stormreply.com, Linux ARM
In-Reply-To: <CAMuHMdVGem_2BGQK4dqZQb3sOd0LZk+RS_z4SvSRcNECEJHdwA@mail.gmail.com>
Hi Geert,
On 5/18/20 9:04 AM, Geert Uytterhoeven wrote:
> Hi Mani,
>
> On Mon, Apr 20, 2020 at 7:02 PM <mani@kernel.org> wrote:
>> From: Manivannan Sadhasivam <mani@kernel.org>
>>
>> Document the use of CTS/RTS gpios for flow control in STM32 UART
>> controller. These properties can be used instead of 'st,hw-flow-ctrl'
>> for making use of any gpio pins for flow control instead of dedicated
>> pins. It should be noted that both CTS/RTS and 'st,hw-flow-ctrl'
>> properties cannot co-exist in a design.
>>
>> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
>> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
>> --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
>> +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
>> @@ -55,6 +61,14 @@ properties:
>> linux,rs485-enabled-at-boot-time: true
>> rs485-rx-during-tx: true
>>
>> +if:
>> + required:
>> + - st,hw-flow-ctrl
> Perhaps "st,hw-flow-ctrl" should be deprecated, in favor of the standard
> "uart-has-rtscts" property?
> Of course the driver needs to gain support for the latter first.
You're fully right, the patch to deprecate "st, hw-flow-ctrl" and
introduce generic "uart-has-rtscts" property in the driver is ready and
will be sent this week on top of Mani patch.
>
>> +then:
>> + properties:
>> + cts-gpios: false
>> + rts-gpios: false
>> +
>> required:
>> - compatible
>> - reg
> Gr{oetje,eeting}s,
>
> Geert
>
^ permalink raw reply
* Re: [PATCH V4 1/5] iio: adc: Convert the QCOM SPMI ADC bindings to .yaml format
From: Linus Walleij @ 2020-05-18 7:25 UTC (permalink / raw)
To: Jishnu Prakash
Cc: Andy Gross, Bjorn Andersson,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org, Matthias Kaehlcke, Jonathan Cameron,
Andy Shevchenko, Amit Kucheria, smohanad, Kiran Gunda, aghayal,
Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, Rob Herring, Mark Rutland, Amit Kucheria,
linux-iio, MSM, linux-arm-msm-owner
In-Reply-To: <1589361736-816-2-git-send-email-jprakash@codeaurora.org>
On Wed, May 13, 2020 at 11:22 AM Jishnu Prakash <jprakash@codeaurora.org> wrote:
> Convert the adc bindings from .txt to .yaml format.
>
> Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 3/3] include: dt-bindings: rockchip: remove unused defines
From: Linus Walleij @ 2020-05-18 7:22 UTC (permalink / raw)
To: Johan Jonker
Cc: Heiko Stübner, Rob Herring, open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, open list:ARM/Rockchip SoC...,
linux-kernel@vger.kernel.org
In-Reply-To: <20200512203524.7317-3-jbx6244@gmail.com>
On Tue, May 12, 2020 at 10:35 PM Johan Jonker <jbx6244@gmail.com> wrote:
> The Rockchip dtsi and dts files have been bulk-converted for the
> remaining raw gpio numbers into their descriptive counterparts and
> also got rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x
> mappings, so remove the unused defines in 'rockchip.h' to prevent
> that someone start using them again.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
I think patch 1 & 3 needs to be applied to the Rockchip tree.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 2/3] dt-bindings: pinctrl: rockchip: update example
From: Linus Walleij @ 2020-05-18 7:20 UTC (permalink / raw)
To: Johan Jonker
Cc: Heiko Stübner, Rob Herring, open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, open list:ARM/Rockchip SoC...,
linux-kernel@vger.kernel.org
In-Reply-To: <20200512203524.7317-2-jbx6244@gmail.com>
On Tue, May 12, 2020 at 10:35 PM Johan Jonker <jbx6244@gmail.com> wrote:
> The Rockchip dtsi and dts files have been bulk-converted for the
> remaining raw gpio numbers into their descriptive counterparts and
> also got rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x
> mappings, so update the example as well.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
This patch applied to the pinctrl tree.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 2/2] platform/chrome: typec: Register Type C switches
From: Prashant Malani @ 2020-05-18 7:19 UTC (permalink / raw)
To: Enric Balletbo i Serra
Cc: linux-kernel, heikki.krogerus, twawrzynczak, Benson Leung,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Guenter Roeck, Rob Herring
In-Reply-To: <542cfe8f-04a5-8dbb-b498-90254bb4c54e@collabora.com>
Hi Enric,
On Thu, Apr 30, 2020 at 12:25:10AM +0200, Enric Balletbo i Serra wrote:
> Hi Prashant,
>
> Following my previous comments ...
>
> On 23/4/20 0:22, Prashant Malani wrote:
> > Register Type C mux and switch handles, when provided via firmware
> > bindings. These will allow the cros-ec-typec driver, and also alternate
> > mode drivers to configure connected Muxes correctly, according to PD
> > information retrieved from the Chrome OS EC.
> >
> > Signed-off-by: Prashant Malani <pmalani@chromium.org>
> > ---
> > drivers/platform/chrome/cros_ec_typec.c | 47 +++++++++++++++++++++++++
> > 1 file changed, 47 insertions(+)
> >
> > diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
> > index eda57db26f8d..324ead297c4d 100644
> > --- a/drivers/platform/chrome/cros_ec_typec.c
> > +++ b/drivers/platform/chrome/cros_ec_typec.c
> > @@ -14,6 +14,8 @@
> > #include <linux/platform_data/cros_usbpd_notify.h>
> > #include <linux/platform_device.h>
> > #include <linux/usb/typec.h>
> > +#include <linux/usb/typec_mux.h>
> > +#include <linux/usb/role.h>
> >
> > #define DRV_NAME "cros-ec-typec"
> >
> > @@ -25,6 +27,9 @@ struct cros_typec_port {
> > struct typec_partner *partner;
> > /* Port partner PD identity info. */
> > struct usb_pd_identity p_identity;
> > + struct typec_switch *ori_sw;
> > + struct typec_mux *mux;
> > + struct usb_role_switch *role_sw;
> > };
> >
> > /* Platform-specific data for the Chrome OS EC Type C controller. */
> > @@ -84,6 +89,40 @@ static int cros_typec_parse_port_props(struct typec_capability *cap,
> > return 0;
> > }
> >
> > +static int cros_typec_get_switch_handles(struct cros_typec_port *port,
> > + struct fwnode_handle *fwnode,
> > + struct device *dev)
> > +{
> > + port->mux = fwnode_typec_mux_get(fwnode, NULL);
> > + if (IS_ERR(port->mux)) {
> > + dev_info(dev, "Mux handle not found.\n");
>
> Be quiet also here, dev_dbg at most, as you're ignoring the error anyway at the end.
>
Done.
> > + goto mux_err;
> > + }
> > +
> > + port->ori_sw = fwnode_typec_switch_get(fwnode);
> > + if (IS_ERR(port->ori_sw)) {
> > + dev_info(dev, "Orientation switch handle not found.\n");
>
> Same here
>
Done.
> > + goto ori_sw_err;
> > + }
> > +
> > + port->role_sw = fwnode_usb_role_switch_get(fwnode);
> > + if (IS_ERR(port->role_sw)) {
> > + dev_info(dev, "USB role switch handle not found.\n");
>
> And here.
>
Done.
Thanks for the review. I've uploaded a new version of the patches.
Best regards,
-Prashant
> > + goto role_sw_err;
> > + }
> > +
> > + return 0;
> > +
> > +role_sw_err:
> > + usb_role_switch_put(port->role_sw);
> > +ori_sw_err:
> > + typec_switch_put(port->ori_sw);
> > +mux_err:
> > + typec_mux_put(port->mux);
> > +
> > + return -ENODEV;
> > +}
> > +
> > static void cros_unregister_ports(struct cros_typec_data *typec)
> > {
> > int i;
> > @@ -91,6 +130,9 @@ static void cros_unregister_ports(struct cros_typec_data *typec)
> > for (i = 0; i < typec->num_ports; i++) {
> > if (!typec->ports[i])
> > continue;
> > + usb_role_switch_put(typec->ports[i]->role_sw);
> > + typec_switch_put(typec->ports[i]->ori_sw);
> > + typec_mux_put(typec->ports[i]->mux);
> > typec_unregister_port(typec->ports[i]->port);
> > }
> > }
> > @@ -153,6 +195,11 @@ static int cros_typec_init_ports(struct cros_typec_data *typec)
> > ret = PTR_ERR(cros_port->port);
> > goto unregister_ports;
> > }
> > +
> > + ret = cros_typec_get_switch_handles(cros_port, fwnode, dev);
> > + if (ret)
> > + dev_info(dev, "No switch control for port %d\n",
> > + port_num);
> > }
> >
> > return 0;
> >
^ permalink raw reply
* [PATCH v2 2/2] platform/chrome: typec: Register Type C switches
From: Prashant Malani @ 2020-05-18 7:17 UTC (permalink / raw)
To: linux-kernel
Cc: heikki.krogerus, Prashant Malani, Heikki Krogerus, Benson Leung,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Enric Balletbo i Serra, Guenter Roeck, Rob Herring
In-Reply-To: <20200518071707.161843-1-pmalani@chromium.org>
Register Type C mux and switch handles, when provided via firmware
bindings. These will allow the cros-ec-typec driver, and also alternate
mode drivers to configure connected Muxes correctly, according to PD
information retrieved from the Chrome OS EC.
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Reviewed-by: Heikki Krogerus <heikki.krogerus@intel.linux.com>
---
Changes in v2:
- Changed dev_info prints to dev_dbg.
drivers/platform/chrome/cros_ec_typec.c | 47 +++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
index 66b8d21092af..6e79f917314b 100644
--- a/drivers/platform/chrome/cros_ec_typec.c
+++ b/drivers/platform/chrome/cros_ec_typec.c
@@ -14,6 +14,8 @@
#include <linux/platform_data/cros_usbpd_notify.h>
#include <linux/platform_device.h>
#include <linux/usb/typec.h>
+#include <linux/usb/typec_mux.h>
+#include <linux/usb/role.h>
#define DRV_NAME "cros-ec-typec"
@@ -25,6 +27,9 @@ struct cros_typec_port {
struct typec_partner *partner;
/* Port partner PD identity info. */
struct usb_pd_identity p_identity;
+ struct typec_switch *ori_sw;
+ struct typec_mux *mux;
+ struct usb_role_switch *role_sw;
};
/* Platform-specific data for the Chrome OS EC Type C controller. */
@@ -84,6 +89,40 @@ static int cros_typec_parse_port_props(struct typec_capability *cap,
return 0;
}
+static int cros_typec_get_switch_handles(struct cros_typec_port *port,
+ struct fwnode_handle *fwnode,
+ struct device *dev)
+{
+ port->mux = fwnode_typec_mux_get(fwnode, NULL);
+ if (IS_ERR(port->mux)) {
+ dev_dbg(dev, "Mux handle not found.\n");
+ goto mux_err;
+ }
+
+ port->ori_sw = fwnode_typec_switch_get(fwnode);
+ if (IS_ERR(port->ori_sw)) {
+ dev_dbg(dev, "Orientation switch handle not found.\n");
+ goto ori_sw_err;
+ }
+
+ port->role_sw = fwnode_usb_role_switch_get(fwnode);
+ if (IS_ERR(port->role_sw)) {
+ dev_dbg(dev, "USB role switch handle not found.\n");
+ goto role_sw_err;
+ }
+
+ return 0;
+
+role_sw_err:
+ usb_role_switch_put(port->role_sw);
+ori_sw_err:
+ typec_switch_put(port->ori_sw);
+mux_err:
+ typec_mux_put(port->mux);
+
+ return -ENODEV;
+}
+
static void cros_unregister_ports(struct cros_typec_data *typec)
{
int i;
@@ -91,6 +130,9 @@ static void cros_unregister_ports(struct cros_typec_data *typec)
for (i = 0; i < typec->num_ports; i++) {
if (!typec->ports[i])
continue;
+ usb_role_switch_put(typec->ports[i]->role_sw);
+ typec_switch_put(typec->ports[i]->ori_sw);
+ typec_mux_put(typec->ports[i]->mux);
typec_unregister_port(typec->ports[i]->port);
}
}
@@ -153,6 +195,11 @@ static int cros_typec_init_ports(struct cros_typec_data *typec)
ret = PTR_ERR(cros_port->port);
goto unregister_ports;
}
+
+ ret = cros_typec_get_switch_handles(cros_port, fwnode, dev);
+ if (ret)
+ dev_dbg(dev, "No switch control for port %d\n",
+ port_num);
}
return 0;
--
2.26.2.761.g0e0b3e54be-goog
^ permalink raw reply related
* [PATCH v2 1/2] dt-bindings: chrome: Add cros-ec-typec mux props
From: Prashant Malani @ 2020-05-18 7:17 UTC (permalink / raw)
To: linux-kernel
Cc: heikki.krogerus, Prashant Malani, Benson Leung,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Enric Balletbo i Serra, Guenter Roeck, Rob Herring
Add properties for mode, orientation and USB data role switches for
Type C connectors. When available, these will allow the Type C connector
class port driver to configure the various switches according to USB PD
information (like orientation, alt mode etc.) provided by the Chrome OS
EC controller.
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Acked-By: Benson Leung <bleung@chromium.org>
---
Changes in v2:
- Added more text to the switch descriptions, explaining their purpose,
and relation to the Type C connector class framework.
.../bindings/chrome/google,cros-ec-typec.yaml | 40 ++++++++++++++++++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml b/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
index 6d7396ab8bee..800c005a0e44 100644
--- a/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
+++ b/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
@@ -21,7 +21,34 @@ properties:
const: google,cros-ec-typec
connector:
- $ref: /schemas/connector/usb-connector.yaml#
+ allOf:
+ - $ref: /schemas/connector/usb-connector.yaml#
+ - type: object
+ properties:
+ mode-switch:
+ description: Reference to a DT node for the USB Type C Multiplexer
+ for this connector. This switch controls the data lines routing
+ for this connector for various operation modes, including
+ Alternate Modes. This switch is assumed registered with the Type C
+ connector class framework by its driver. The Type C connector
+ class framework assumes that the mode switch property uses this
+ name.
+
+ orientation-switch:
+ description: Reference to a DT node for the USB Type C orientation
+ switch for this connector. This switch controls routing the
+ correct data pairs depending on the cable plug orientation from
+ this connector to the USB / Alternate Mode controllers. This
+ switch is assumed registered with the Type C connector class
+ framework by its driver. The Type C connector class framework
+ assumes that the orientation switch property uses this name.
+
+ usb-role-switch:
+ description: Reference to a DT node for the USB Data role switch
+ for this connector. This switch is assumed registered with the
+ Type C connector class framework by its driver. The Type C
+ connector class framework assumes that the USB role switch
+ property uses this name.
required:
- compatible
@@ -49,6 +76,17 @@ examples:
data-role = "dual";
try-power-role = "source";
};
+
+ connector@1 {
+ compatible = "usb-c-connector";
+ reg = <1>;
+ power-role = "dual";
+ data-role = "host";
+ try-power-role = "source";
+ mode-switch = <&typec_mux>;
+ orientation-switch = <&typec_orientation_switch>;
+ usb-role-switch = <&typec_mux>;
+ };
};
};
};
--
2.26.2.761.g0e0b3e54be-goog
^ permalink raw reply related
* Re: [PATCH] arm: dts: am33xx-bone-common: add gpio-line-names
From: Linus Walleij @ 2020-05-18 7:11 UTC (permalink / raw)
To: Drew Fustini
Cc: Grygorii Strashko, Benoît Cousson, Tony Lindgren,
Rob Herring, Linux-OMAP,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org, Jason Kridner, Robert Nelson
In-Reply-To: <20200508165821.GA14555@x1>
On Fri, May 8, 2020 at 6:57 PM Drew Fustini <drew@beagleboard.org> wrote:
> Add gpio-line-names properties to the gpio controller nodes.
> BeagleBone boards have P8 and P9 headers [0] which expose many the
> AM3358 SoC balls to stacking expansion boards called "capes", or to
> other external connections like jumper wires to a breadboard.
>
> Many of the P8/P9 header pins can muxed to a gpio line. The
> gpio-line-names describe which P8/P9 pin that line goes to and the
> default mux for that P8/P9 pin. Some lines are not routed to the
> P8/P9 headers, but instead are dedicated to some functionality such as
> status LEDs. The line name will indicate this. Some line names are
> left empty as the corresponding AM3358 balls are not connected.
>
> The goal is to make it easier for a user viewing the output of gpioinfo
> to determine which P8/P9 pin is connected to a line. The output of
> gpioinfo on a BeagleBone Black will now look like this:
>
> gpiochip0 - 32 lines:
> line 0: "ethernet" unused input active-high
> line 1: "ethernet" unused input active-high
Why are the ethernet lines not tagged with respective signal name
when right below the SPI lines are explicitly tagged with
sclk, cs0 etc?
Ethernet is usually RGMII and has signal names like
tx_clk, tx_d0, tx_en etc.
Also some lines seem to be tagged with the pin number
like P9_22, P2_21 below, it seems a bit inconsistent
to have much information on some pins and very sketchy
information on some.
> line 18: "usb" unused input active-high
> line 19: "hdmi" unused input active-high
Similar comments for these.
Yours,
Linus Walleij
^ permalink raw reply
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