* [PATCH] ARM: dts: bcm: HR2: Fix PPI interrupt types
From: Hamish Martin @ 2020-05-20 4:30 UTC (permalink / raw)
To: robh+dt, rjui, sbranden
Cc: devicetree, linux-arm-kernel, f.fainelli, Hamish Martin
These error messages are output when booting on a BCM HR2 system:
GIC: PPI11 is secure or misconfigured
GIC: PPI13 is secure or misconfigured
Per ARM documentation these interrupts are triggered on a rising edge.
See ARM Cortex A-9 MPCore Technical Reference Manual, Revision r4p1,
Section 3.3.8 Interrupt Configuration Registers.
The same issue was resolved for NSP systems in commit 5f1aa51c7a1e
("ARM: dts: NSP: Fix PPI interrupt types").
Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
---
arch/arm/boot/dts/bcm-hr2.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi
index 6142c672811e..5e5f5ca3c86f 100644
--- a/arch/arm/boot/dts/bcm-hr2.dtsi
+++ b/arch/arm/boot/dts/bcm-hr2.dtsi
@@ -75,7 +75,7 @@ a9pll: arm_clk@0 {
timer@20200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x20200 0x100>;
- interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
clocks = <&periph_clk>;
};
@@ -83,7 +83,7 @@ twd-timer@20600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x20600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
- IRQ_TYPE_LEVEL_HIGH)>;
+ IRQ_TYPE_EDGE_RISING)>;
clocks = <&periph_clk>;
};
@@ -91,7 +91,7 @@ twd-watchdog@20620 {
compatible = "arm,cortex-a9-twd-wdt";
reg = <0x20620 0x20>;
interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
- IRQ_TYPE_LEVEL_HIGH)>;
+ IRQ_TYPE_EDGE_RISING)>;
clocks = <&periph_clk>;
};
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v1 4/4] of: platform: Batch fwnode parsing when adding all top level devices
From: Marek Szyprowski @ 2020-05-20 4:21 UTC (permalink / raw)
To: Saravana Kannan
Cc: Greg Kroah-Hartman, Rafael J. Wysocki, Rob Herring, Frank Rowand,
Len Brown, Android Kernel Team, LKML,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
ACPI Devel Maling List, Ji Luo, Linux Samsung SOC
In-Reply-To: <CAGETcx_VtJXCqih4ZadZ0dFVJwKOBEQnnrr9JxxmGNh7HX_vNQ@mail.gmail.com>
Hi Saravana,
On 19.05.2020 20:02, Saravana Kannan wrote:
> On Tue, May 19, 2020 at 3:32 AM Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
>> On 19.05.2020 09:11, Marek Szyprowski wrote:
>>> On 19.05.2020 08:48, Saravana Kannan wrote:
>>>> On Mon, May 18, 2020 at 11:25 PM Marek Szyprowski
>>>> <m.szyprowski@samsung.com> wrote:
>>>>> On 15.05.2020 07:35, Saravana Kannan wrote:
>>>>>> The fw_devlink_pause() and fw_devlink_resume() APIs allow batching the
>>>>>> parsing of the device tree nodes when a lot of devices are added. This
>>>>>> will significantly cut down parsing time (as much a 1 second on some
>>>>>> systems). So, use them when adding devices for all the top level
>>>>>> device
>>>>>> tree nodes in a system.
>>>>>>
>>>>>> Signed-off-by: Saravana Kannan <saravanak@google.com>
>>>>> This patch recently landed in linux-next 20200518. Sadly, it causes
>>>>> regression on Samsung Exynos5433-based TM2e board:
>>>>>
>>>>> ...
>>>>>
>>>>> Both issues, the lack of DMA for SPI device and Synchronous abort in
>>>>> I2S
>>>>> probe are new after applying this patch. I'm trying to investigate
>>>>> which
>>>>> resources are missing and why. The latter issue means typically that
>>>>> the
>>>>> registers for the given device has been accessed without enabling the
>>>>> needed clocks or power domains.
>>>> Did you try this copy-pasta fix that I sent later?
>>>> https://lore.kernel.org/lkml/20200517173453.157703-1-saravanak@google.com/
>>>>
>>>>
>>>> Not every system would need it (my test setup didn't), but it helps
>>>> some cases.
>>>>
>>>> If that fix doesn't help, then some tips for debugging the failing
>>>> drivers.
>>>> What this pause/resume patch effectively (not explicitly) does is:
>>>> 1. Doesn't immediately probe the devices as they are added in
>>>> of_platform_default_populate_init()
>>>> 2. Adds them in order to the deferred probe list.
>>>> 3. Then kicks off deferred probe on them in the order they were added.
>>>>
>>>> These drivers are just not handling -EPROBE_DEFER correctly or
>>>> assuming probe order and that's causing these issues.
>>>>
>>>> So, we can either fix that or you can try adding some code to flush
>>>> the deferred probe workqueue at the end of fw_devlink_resume().
>>>>
>>>> Let me know how it goes.
>>> So far it looks that your patch revealed a hidden issue in exynos5433
>>> clocks configuration, because adding clk_ignore_unused parameter to
>>> kernel command line fixes the boot. I'm still investigating it, so
>>> probable you can ignore my regression report. I will let you know asap
>>> I finish checking it.
>>>
>> Okay, I confirm that the issue is in the Exynos I2S driver and
>> Exynos5433 clock provider. I've posted a quick workaround. I'm sorry for
>> the noise, your patch is fine.
> Thanks for debugging and finding the real issue. I tried finding your
> patches, but couldn't. Can you point me to a lore.kernel.org link? I'm
> just curious to see what the issue was.
https://lore.kernel.org/linux-samsung-soc/f67db8c1-453b-4c70-67b9-59762ac34f64@kernel.org/T/#t
It looks that one more clock has to be enabled to properly read init
configuration. So far it worked, because that device was probed much
earlier, before the unused clocks are turned off. Your patch changed the
probe order, so that device is probed later.
> I'm guessing you didn't need to pick up this one?
> https://lore.kernel.org/lkml/20200517173453.157703-1-saravanak@google.com/
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
^ permalink raw reply
* [PATCH v3 2/2] arm64: dts: Add ds26522 node to dts to ls1043ardb
From: Qiang Zhao @ 2020-05-20 4:02 UTC (permalink / raw)
To: shawnguo; +Cc: leoyang.li, devicetree, linux-kernel, Zhao Qiang
In-Reply-To: <20200520040221.10536-1-qiang.zhao@nxp.com>
From: Zhao Qiang <qiang.zhao@nxp.com>
Add ds26522 node to fsl-ls1043a-rdb.dts
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
v3:
- use "arm64: dts:" format for subject
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index 44d9343..1cb265f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -94,6 +94,22 @@
reg = <0>;
spi-max-frequency = <1000000>; /* input clock */
};
+
+ slic@2 {
+ compatible = "maxim,ds26522";
+ reg = <2>;
+ spi-max-frequency = <2000000>;
+ fsl,spi-cs-sck-delay = <100>;
+ fsl,spi-sck-cs-delay = <50>;
+ };
+
+ slic@3 {
+ compatible = "maxim,ds26522";
+ reg = <3>;
+ spi-max-frequency = <2000000>;
+ fsl,spi-cs-sck-delay = <100>;
+ fsl,spi-sck-cs-delay = <50>;
+ };
};
&duart0 {
--
2.7.4
^ permalink raw reply related
* [PATCH v3 1/2] arm64: dts: add qe node to ls1043ardb
From: Qiang Zhao @ 2020-05-20 4:02 UTC (permalink / raw)
To: shawnguo; +Cc: leoyang.li, devicetree, linux-kernel, Zhao Qiang
From: Zhao Qiang <qiang.zhao@nxp.com>
Add qe node to fsl-ls1043a.dtsi and fsl-ls1043a-rdb.dts
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
v2:
- add commit msg and drop a new blank line
v3:
- Keep labeling node sort alphabetically
- remove unused device_type
- use GIC_SPI and IRQ_TYPE_LEVEL_HIGH
- use "arm64: dts:" format for subject
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 16 ++++++
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 65 +++++++++++++++++++++++
2 files changed, 81 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index dde50c8..44d9343 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -176,3 +176,19 @@
};
};
};
+
+&uqe {
+ ucc_hdlc: ucc@2000 {
+ compatible = "fsl,ucc-hdlc";
+ rx-clock-name = "clk8";
+ tx-clock-name = "clk9";
+ fsl,rx-sync-clock = "rsync_pin";
+ fsl,tx-sync-clock = "tsync_pin";
+ fsl,tx-timeslot-mask = <0xfffffffe>;
+ fsl,rx-timeslot-mask = <0xfffffffe>;
+ fsl,tdm-framer-type = "e1";
+ fsl,tdm-id = <0>;
+ fsl,siram-entry-id = <0>;
+ fsl,tdm-interface;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index c084c7a4..3b641bd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -525,6 +525,71 @@
#interrupt-cells = <2>;
};
+ uqe: uqe@2400000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe", "simple-bus";
+ ranges = <0x0 0x0 0x2400000 0x40000>;
+ reg = <0x0 0x2400000 0x0 0x480>;
+ brg-frequency = <100000000>;
+ bus-frequency = <200000000>;
+ fsl,qe-num-riscs = <1>;
+ fsl,qe-num-snums = <28>;
+
+ qeic: qeic@80 {
+ compatible = "fsl,qe-ic";
+ reg = <0x80 0x80>;
+ #address-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ si1: si@700 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,ls1043-qe-si",
+ "fsl,t1040-qe-si";
+ reg = <0x700 0x80>;
+ };
+
+ siram1: siram@1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1043-qe-siram",
+ "fsl,t1040-qe-siram";
+ reg = <0x1000 0x800>;
+ };
+
+ ucc@2000 {
+ cell-index = <1>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
+ interrupt-parent = <&qeic>;
+ };
+
+ ucc@2200 {
+ cell-index = <3>;
+ reg = <0x2200 0x200>;
+ interrupts = <34>;
+ interrupt-parent = <&qeic>;
+ };
+
+ muram@10000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0x0 0x10000 0x6000>;
+
+ data-only@0 {
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0x0 0x6000>;
+ };
+ };
+ };
+
lpuart0: serial@2950000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2950000 0x0 0x1000>;
--
2.7.4
^ permalink raw reply related
* Re: [PATCH 00/12] Add cpufreq and cci devfreq for mt8183, and SVS support
From: Chanwoo Choi @ 2020-05-20 4:10 UTC (permalink / raw)
To: Andrew-sh.Cheng, MyungJoo Ham, Kyungmin Park, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J . Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Liam Girdwood, Mark Brown
Cc: linux-pm, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, srv_heupstream
In-Reply-To: <20200520034307.20435-1-andrew-sh.cheng@mediatek.com>
Hi Andrew,
Could you explain the base commit of these patches?
When I tried to apply them to v5.7-rc1 for testing,
the merge conflict occurs.
Thanks,
Chanwoo Choi
On 5/20/20 12:42 PM, Andrew-sh.Cheng wrote:
> MT8183 supports CPU DVFS and CCI DVFS, and LITTLE cpus and CCI are in the same voltage domain.
> So, this series is to add drivers to handle the voltage coupling between CPU and CCI DVFS.
>
> For SVS support, need OPP_EVENT_ADJUST_VOLTAGE and corresponding reaction.
>
> Change since v5:
> - Changing dt-binding format to yaml.
> - Extending current devfreq passive_governor instead of create a new one.
> - Resend depending patches of Sravana Kannan base on kernel-5.7
>
>
> Andrew-sh.Cheng (6):
> cpufreq: mediatek: add clock and regulator enable for intermediate
> clock
> dt-bindings: devfreq: add compatible for mt8183 cci devfreq
> devfreq: add mediatek cci devfreq
> opp: Modify opp API, dev_pm_opp_get_freq(), find freq in opp, even it
> is disabled
> cpufreq: mediatek: add opp notification for SVS support
> devfreq: mediatek: cci devfreq register opp notification for SVS
> support
>
> Saravana Kannan (6):
> OPP: Allow required-opps even if the device doesn't have power-domains
> OPP: Add function to look up required OPP's for a given OPP
> OPP: Improve required-opps linking
> PM / devfreq: Cache OPP table reference in devfreq
> PM / devfreq: Add required OPPs support to passive governor
> PM / devfreq: Add cpu based scaling support to passive_governor
>
> .../devicetree/bindings/devfreq/mt8183-cci.yaml | 51 ++++
> drivers/cpufreq/mediatek-cpufreq.c | 122 ++++++++-
> drivers/devfreq/Kconfig | 12 +
> drivers/devfreq/Makefile | 1 +
> drivers/devfreq/devfreq.c | 6 +
> drivers/devfreq/governor_passive.c | 298 +++++++++++++++++++--
> drivers/devfreq/mt8183-cci-devfreq.c | 233 ++++++++++++++++
> drivers/opp/core.c | 85 +++++-
> drivers/opp/of.c | 108 ++++----
> drivers/opp/opp.h | 5 +
> include/linux/devfreq.h | 42 ++-
> include/linux/pm_opp.h | 11 +
> 12 files changed, 874 insertions(+), 100 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/devfreq/mt8183-cci.yaml
> create mode 100644 drivers/devfreq/mt8183-cci-devfreq.c
>
^ permalink raw reply
* [PATCH v11] arm64: dts: qcom: sc7180: Add WCN3990 WLAN module device node
From: Rakesh Pillai @ 2020-05-20 3:56 UTC (permalink / raw)
To: devicetree; +Cc: linux-arm-kernel, linux-kernel, linux-arm-msm, Rakesh Pillai
Add device node for the ath10k SNOC platform driver probe
and add resources required for WCN3990 on sc7180 soc.
Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
---
Changes from v10:
- Corrected the position of wifi node, as per address
- Removed the wlan_fw_mem from reserved memory, since
its already added as reserved memory in board DT file.
---
arch/arm64/boot/dts/qcom/sc7180-idp.dts | 7 +++++++
arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++++++++++++++++++++++
2 files changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index 4e9149d..38b102e 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -389,6 +389,13 @@
};
};
+&wifi {
+ status = "okay";
+ wifi-firmware {
+ iommus = <&apps_smmu 0xc2 0x1>;
+ };
+};
+
/* PINCTRL - additions to nodes defined in sc7180.dtsi */
&qspi_clk {
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 6b12c60..da79f8f 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2811,6 +2811,28 @@
#freq-domain-cells = <1>;
};
+
+ wifi: wifi@18800000 {
+ compatible = "qcom,wcn3990-wifi";
+ reg = <0 0x18800000 0 0x800000>;
+ reg-names = "membase";
+ iommus = <&apps_smmu 0xc0 0x1>;
+ interrupts =
+ <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
+ <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
+ <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
+ memory-region = <&wlan_mem>;
+ status = "disabled";
+ };
};
thermal-zones {
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v10] arm64: dts: qcom: sc7180: Add WCN3990 WLAN module device node
From: Sibi Sankar @ 2020-05-20 3:34 UTC (permalink / raw)
To: Rakesh Pillai
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
linux-arm-msm-owner
In-Reply-To: <1589914405-6674-1-git-send-email-pillair@codeaurora.org>
Hey Rakesh,
On 2020-05-20 00:23, Rakesh Pillai wrote:
> Add device node for the ath10k SNOC platform driver probe
> and add resources required for WCN3990 on sc7180 soc.
>
> Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
> ---
> Changes from v9:
> - Place the wlan_fw_mem under reserved-memory node
> ---
> arch/arm64/boot/dts/qcom/sc7180-idp.dts | 7 +++++++
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 27
> +++++++++++++++++++++++++++
> 2 files changed, 34 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> index 4e9149d..38b102e 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> @@ -389,6 +389,13 @@
> };
> };
>
> +&wifi {
> + status = "okay";
> + wifi-firmware {
> + iommus = <&apps_smmu 0xc2 0x1>;
> + };
> +};
> +
> /* PINCTRL - additions to nodes defined in sc7180.dtsi */
>
> &qspi_clk {
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index f1280e0..19bd7d0 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -106,6 +106,11 @@
> no-map;
> };
>
> + wlan_fw_mem: memory@94100000 {
> + reg = <0 0x94100000 0 0x200000>;
> + no-map;
> + };
> +
You can skip ^^, its already
present as wlan_mem in the
board dts.
> rmtfs_mem: memory@84400000 {
> compatible = "qcom,rmtfs-mem";
> reg = <0x0 0x84400000 0x0 0x200000>;
> @@ -944,6 +949,28 @@
> };
> };
>
> + wifi: wifi@18800000 {
> + compatible = "qcom,wcn3990-wifi";
> + reg = <0 0x18800000 0 0x800000>;
> + reg-names = "membase";
> + iommus = <&apps_smmu 0xc0 0x1>;
> + interrupts =
> + <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
> + <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
> + <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
> + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
> + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
> + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
> + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
> + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
> + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
> + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
> + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
> + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
> + memory-region = <&wlan_fw_mem>;
Its named as wlan_mem in sc7180-idp.dts
> + status = "disabled";
> + };
> +
> config_noc: interconnect@1500000 {
> compatible = "qcom,sc7180-config-noc";
> reg = <0 0x01500000 0 0x28000>;
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply
* RE: [PATCH 3/3] arm64: dts: imx8mp: add mu node
From: Peng Fan @ 2020-05-20 3:06 UTC (permalink / raw)
To: Fabio Estevam
Cc: Shawn Guo, Fabio Estevam, Sascha Hauer, Aisheng Dong, Rob Herring,
Stephen Boyd,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-kernel, dl-linux-imx, Leonard Crestez, Daniel Baluta,
Lucas Stach,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-clk
In-Reply-To: <CAOMZO5DmiQbfJjTLKPiv6uUNaQ8ae-0h7uOpPf2J9ZMwDoE+Eg@mail.gmail.com>
> Subject: Re: [PATCH 3/3] arm64: dts: imx8mp: add mu node
>
> Hi Peng,
>
> On Wed, May 20, 2020 at 12:01 AM Peng Fan <peng.fan@nxp.com> wrote:
>
> > Nothing specific in i.MX8MP for the mu part, so do we really need add
> > "fsl,imx8mp-mu"?
>
> It is good practice to add a more specific option.
>
> Let's say in future a bug is found that affects imx8mp MU, then you could fix
> the MU driver and keep the dtb compatibility.
Got it. Thanks for the tips.
Thanks,
Peng.
^ permalink raw reply
* Re: [PATCH 3/3] arm64: dts: imx8mp: add mu node
From: Fabio Estevam @ 2020-05-20 3:06 UTC (permalink / raw)
To: Peng Fan
Cc: Shawn Guo, Fabio Estevam, Sascha Hauer, Aisheng Dong, Rob Herring,
Stephen Boyd,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-kernel, dl-linux-imx, Leonard Crestez, Daniel Baluta,
Lucas Stach,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-clk
In-Reply-To: <DB6PR0402MB27602682E90E4CED55244BCC88B60@DB6PR0402MB2760.eurprd04.prod.outlook.com>
Hi Peng,
On Wed, May 20, 2020 at 12:01 AM Peng Fan <peng.fan@nxp.com> wrote:
> Nothing specific in i.MX8MP for the mu part, so do we really need
> add "fsl,imx8mp-mu"?
It is good practice to add a more specific option.
Let's say in future a bug is found that affects imx8mp MU, then you
could fix the MU driver and keep the dtb compatibility.
^ permalink raw reply
* RE: [PATCH 3/3] arm64: dts: imx8mp: add mu node
From: Peng Fan @ 2020-05-20 3:01 UTC (permalink / raw)
To: Fabio Estevam
Cc: Shawn Guo, Fabio Estevam, Sascha Hauer, Aisheng Dong, Rob Herring,
Stephen Boyd,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-kernel, dl-linux-imx, Leonard Crestez, Daniel Baluta,
Lucas Stach,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-clk
In-Reply-To: <CAOMZO5BPPRy_XGHHyZfE3eOrmCwW_VytueY-An8qqke6HU06TQ@mail.gmail.com>
> Subject: Re: [PATCH 3/3] arm64: dts: imx8mp: add mu node
>
> Hi Peng,
>
> On Tue, May 19, 2020 at 11:15 PM <peng.fan@nxp.com> wrote:
>
> > + mu: mailbox@30aa0000 {
> > + compatible = "fsl,imx6sx-mu";
>
> This should be better described as:
>
> compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
>
> From Documentation/devicetree/bindings/mailbox/fsl,mu.txt:
>
> "The "fsl,imx6sx-mu" compatible is seen as generic and should be included
> together with SoC specific compatible."
Nothing specific in i.MX8MP for the mu part, so do we really need
add "fsl,imx8mp-mu"?
Thanks,
Peng.
^ permalink raw reply
* [PATCH V2 3/3] arm64: dts: imx8/8mm/8mn/8mq: add identifier for DDR perf
From: Joakim Zhang @ 2020-05-20 2:56 UTC (permalink / raw)
To: john.garry, will, mark.rutland, robh+dt, shawnguo
Cc: linux-imx, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20200520025619.687-1-qiangqing.zhang@nxp.com>
Add identifier property for DDR perf.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
4 files changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 1e5e11592f7b..ee14a6ecdb93 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -898,6 +898,7 @@
reg = <0x3d800000 0x400000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ identifier = "i.mx8mm";
};
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index a44b5438e842..b93e56ebf9a7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -796,6 +796,7 @@
compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
reg = <0x3d800000 0x400000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ identifier = "i.mx8mn";
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 6a1e83922c71..38cc93af35ac 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1217,6 +1217,7 @@
reg = <0x3d800000 0x400000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ identifier = "i.mx8mq";
};
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index fb5f752b15fe..0c294b549806 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -436,6 +436,7 @@
compatible = "fsl,imx8-ddr-pmu";
reg = <0x5c020000 0x10000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ identifier = "i.mx8";
};
};
--
2.17.1
^ permalink raw reply related
* [PATCH V2 2/3] perf/imx_ddr: Add system PMU identifier for userspace
From: Joakim Zhang @ 2020-05-20 2:56 UTC (permalink / raw)
To: john.garry, will, mark.rutland, robh+dt, shawnguo
Cc: linux-imx, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20200520025619.687-1-qiangqing.zhang@nxp.com>
The DDR Perf for i.MX8 is a system PMU whose axi id would different from
SoC to SoC. Need expose system PMU identifier for userspace which refer
to /sys/bus/event_source/devices/<PMU DEVICE>/identifier.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
drivers/perf/fsl_imx8_ddr_perf.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
index 90884d14f95f..ba523a94f4d7 100644
--- a/drivers/perf/fsl_imx8_ddr_perf.c
+++ b/drivers/perf/fsl_imx8_ddr_perf.c
@@ -76,6 +76,7 @@ struct ddr_pmu {
unsigned int cpu;
struct hlist_node node;
struct device *dev;
+ const char *identifier;
struct perf_event *events[NUM_COUNTERS];
int active_events;
enum cpuhp_state cpuhp_state;
@@ -84,6 +85,27 @@ struct ddr_pmu {
int id;
};
+static ssize_t ddr_perf_identifier_show(struct device *dev,
+ struct device_attribute *attr,
+ char *page)
+{
+ struct ddr_pmu *pmu = dev_get_drvdata(dev);
+
+ return sprintf(page, "%s\n", pmu->identifier);
+}
+
+static struct device_attribute ddr_perf_identifier_attr =
+ __ATTR(identifier, 0444, ddr_perf_identifier_show, NULL);
+
+static struct attribute *ddr_perf_identifier_attrs[] = {
+ &ddr_perf_identifier_attr.attr,
+ NULL,
+};
+
+static struct attribute_group ddr_perf_identifier_attr_group = {
+ .attrs = ddr_perf_identifier_attrs,
+};
+
enum ddr_perf_filter_capabilities {
PERF_CAP_AXI_ID_FILTER = 0,
PERF_CAP_AXI_ID_FILTER_ENHANCED,
@@ -237,6 +259,7 @@ static const struct attribute_group *attr_groups[] = {
&ddr_perf_format_attr_group,
&ddr_perf_cpumask_attr_group,
&ddr_perf_filter_cap_attr_group,
+ &ddr_perf_identifier_attr_group,
NULL,
};
@@ -601,6 +624,7 @@ static int ddr_perf_probe(struct platform_device *pdev)
struct ddr_pmu *pmu;
struct device_node *np;
void __iomem *base;
+ const char *identifier = NULL;
char *name;
int num;
int ret;
@@ -620,6 +644,11 @@ static int ddr_perf_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pmu);
+ ret = of_property_read_string(np, "identifier", &identifier);
+ if (ret < 0)
+ dev_warn(&pdev->dev, "Failed to get identifier\n");
+ pmu->identifier = identifier;
+
name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d",
num);
if (!name)
--
2.17.1
^ permalink raw reply related
* [PATCH V2 1/3] bindings: perf: imx8_ddr: add identifier property
From: Joakim Zhang @ 2020-05-20 2:56 UTC (permalink / raw)
To: john.garry, will, mark.rutland, robh+dt, shawnguo
Cc: linux-imx, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20200520025619.687-1-qiangqing.zhang@nxp.com>
Add "identifier" property for DDR Perf which used to identity system pmu.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
index 7822a806ea0a..ebb9a40094c5 100644
--- a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
+++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
@@ -12,6 +12,8 @@ Required properties:
- interrupts: single interrupt
generated by the control block
+- identifier: identify system pmu
+
Example:
ddr-pmu@5c020000 {
@@ -19,4 +21,5 @@ Example:
reg = <0x5c020000 0x10000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ identifier = "i.mx8mm";
};
--
2.17.1
^ permalink raw reply related
* [PATCH V2 0/3] perf/imx_ddr: Add system PMU support
From: Joakim Zhang @ 2020-05-20 2:56 UTC (permalink / raw)
To: john.garry, will, mark.rutland, robh+dt, shawnguo
Cc: linux-imx, linux-arm-kernel, devicetree, linux-kernel
The patch set adds system PMU support for i.MX8 DDR Perf.
The sysfs location for userspace to get the PMU identifier under the
directory:
/sys/bus/event_source/devices/<PMU DEVICE>/identifier
ChangeLogs:
V1 -> V2:
*add property in dt instead of changing compatible string.
Joakim Zhang (3):
bindings: perf: imx8_ddr: add identifier property
perf/imx_ddr: Add system PMU identifier for userspace
arm64: dts: imx8/8mm/8mn/8mq: add identifier for DDR perf
.../devicetree/bindings/perf/fsl-imx-ddr.txt | 3 ++
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
drivers/perf/fsl_imx8_ddr_perf.c | 29 +++++++++++++++++++
6 files changed, 36 insertions(+)
--
2.17.1
^ permalink raw reply
* Re: [PATCH 3/3] arm64: dts: imx8mp: add mu node
From: Fabio Estevam @ 2020-05-20 2:59 UTC (permalink / raw)
To: Peng Fan
Cc: Shawn Guo, Fabio Estevam, Sascha Hauer, Dong Aisheng, Rob Herring,
Stephen Boyd,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-kernel, NXP Linux Team, Leonard Crestez, Daniel Baluta,
Lucas Stach,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-clk
In-Reply-To: <1589940278-3680-4-git-send-email-peng.fan@nxp.com>
Hi Peng,
On Tue, May 19, 2020 at 11:15 PM <peng.fan@nxp.com> wrote:
> + mu: mailbox@30aa0000 {
> + compatible = "fsl,imx6sx-mu";
This should be better described as:
compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
From Documentation/devicetree/bindings/mailbox/fsl,mu.txt:
"The "fsl,imx6sx-mu" compatible is seen as generic and should
be included together with SoC specific compatible."
^ permalink raw reply
* Re: [PATCH v2 2/4] ARM: dts: ims53: Group port definitions for the dvi-converter
From: Shawn Guo @ 2020-05-20 2:57 UTC (permalink / raw)
To: Ricardo Cañuelo
Cc: Laurent.pinchart, kernel, devicetree, dri-devel, linux-arm-kernel,
jason, tomi.valkeinen, robh+dt, airlied
In-Reply-To: <20200514143612.2094-3-ricardo.canuelo@collabora.com>
On Thu, May 14, 2020 at 04:36:10PM +0200, Ricardo Cañuelo wrote:
> Group the port definitions of the dvi-converter in a 'ports' node to
> make it compliant with the ti,tfp410 binding.
>
> Signed-off-by: Ricardo Cañuelo <ricardo.canuelo@collabora.com>
s/ims53/imx53-cx9020 in subject.
I fixed it up and applied the patch.
Shawn
^ permalink raw reply
* RE: [PATCH V1 RESEND 1/3] perf/imx_ddr: Add system PMU identifier for userspace
From: Joakim Zhang @ 2020-05-20 2:56 UTC (permalink / raw)
To: Rob Herring
Cc: john.garry@huawei.com, will@kernel.org, mark.rutland@arm.com,
shawnguo@kernel.org, dl-linux-imx,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <20200519185125.GB453195@bogus>
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 2020年5月20日 2:51
> To: Joakim Zhang <qiangqing.zhang@nxp.com>
> Cc: john.garry@huawei.com; will@kernel.org; mark.rutland@arm.com;
> shawnguo@kernel.org; dl-linux-imx <linux-imx@nxp.com>;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH V1 RESEND 1/3] perf/imx_ddr: Add system PMU identifier
> for userspace
>
> On Tue, May 12, 2020 at 03:31:13PM +0800, Joakim Zhang wrote:
> > The DDR Perf for i.MX8 is a system PMU whose axi id would different
> > from SoC to SoC. Need expose system PMU identifier for userspace which
> > refer to /sys/bus/event_source/devices/<PMU DEVICE>/identifier.
>
> Why not just expose the AXI ID if that's what's different?
Hi Rob,
Each master has their own AXI ID, such as USB, GPU, VPU etc, it is various from different SoCs. We want to add system PMU support in perf tool, so we want to expose something from perf driver to identify each SoC.
When we know which SoC it is, we can get each master AXI ID. If this patch can be accepted, /sys/bus/event_source/devices/<PMU DEVICE>/identifier could be a common interface for all system PMUs.
I will change to add a property to identify SoC, to see if it is better. Thanks.
Best Regards,
Joakim Zhang
> >
> > Reviewed-by: John Garry <john.garry@huawei.com>
> > Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
> > ---
> > drivers/perf/fsl_imx8_ddr_perf.c | 45
> > +++++++++++++++++++++++++++++---
> > 1 file changed, 42 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/perf/fsl_imx8_ddr_perf.c
> > b/drivers/perf/fsl_imx8_ddr_perf.c
> > index 95dca2cb5265..88addbffbbd0 100644
> > --- a/drivers/perf/fsl_imx8_ddr_perf.c
> > +++ b/drivers/perf/fsl_imx8_ddr_perf.c
> > @@ -50,21 +50,38 @@ static DEFINE_IDA(ddr_ida);
> >
> > struct fsl_ddr_devtype_data {
> > unsigned int quirks; /* quirks needed for different DDR Perf core */
> > + const char *identifier; /* system PMU identifier for userspace */
> > };
> >
> > -static const struct fsl_ddr_devtype_data imx8_devtype_data;
> > +static const struct fsl_ddr_devtype_data imx8_devtype_data = {
> > + .identifier = "i.MX8",
> > +};
> > +
> > +static const struct fsl_ddr_devtype_data imx8mq_devtype_data = {
> > + .quirks = DDR_CAP_AXI_ID_FILTER,
> > + .identifier = "i.MX8MQ",
> > +};
> > +
> > +static const struct fsl_ddr_devtype_data imx8mm_devtype_data = {
> > + .quirks = DDR_CAP_AXI_ID_FILTER,
> > + .identifier = "i.MX8MM",
> > +};
> >
> > -static const struct fsl_ddr_devtype_data imx8m_devtype_data = {
> > +static const struct fsl_ddr_devtype_data imx8mn_devtype_data = {
> > .quirks = DDR_CAP_AXI_ID_FILTER,
> > + .identifier = "i.MX8MN",
> > };
> >
> > static const struct fsl_ddr_devtype_data imx8mp_devtype_data = {
> > .quirks = DDR_CAP_AXI_ID_FILTER_ENHANCED,
> > + .identifier = "i.MX8MP",
> > };
> >
> > static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
> > { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
> > - { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
>
> You need to keep the old one for compatibility.
>
> > + { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
> > + { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
> > + { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
> > { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
> > { /* sentinel */ }
> > };
> > @@ -84,6 +101,27 @@ struct ddr_pmu {
> > int id;
> > };
> >
> > +static ssize_t ddr_perf_identifier_show(struct device *dev,
> > + struct device_attribute *attr,
> > + char *page)
> > +{
> > + struct ddr_pmu *pmu = dev_get_drvdata(dev);
> > +
> > + return sprintf(page, "%s\n", pmu->devtype_data->identifier);
>
> Why do we need yet another way to identify the SoC from userspace?
>
> > +}
> > +
> > +static struct device_attribute ddr_perf_identifier_attr =
> > + __ATTR(identifier, 0444, ddr_perf_identifier_show, NULL);
>
> sysfs attributes are supposed to be documented.
>
> > +
> > +static struct attribute *ddr_perf_identifier_attrs[] = {
> > + &ddr_perf_identifier_attr.attr,
> > + NULL,
> > +};
> > +
> > +static struct attribute_group ddr_perf_identifier_attr_group = {
> > + .attrs = ddr_perf_identifier_attrs,
> > +};
> > +
> > enum ddr_perf_filter_capabilities {
> > PERF_CAP_AXI_ID_FILTER = 0,
> > PERF_CAP_AXI_ID_FILTER_ENHANCED,
> > @@ -237,6 +275,7 @@ static const struct attribute_group *attr_groups[] = {
> > &ddr_perf_format_attr_group,
> > &ddr_perf_cpumask_attr_group,
> > &ddr_perf_filter_cap_attr_group,
> > + &ddr_perf_identifier_attr_group,
> > NULL,
> > };
> >
> > --
> > 2.17.1
> >
^ permalink raw reply
* Re: [PATCH 1/2] ARM: dts: imx50: Add src node interrupt
From: Shawn Guo @ 2020-05-20 2:52 UTC (permalink / raw)
To: Anson Huang
Cc: robh+dt, s.hauer, kernel, festevam, devicetree, linux-arm-kernel,
linux-kernel, Linux-imx
In-Reply-To: <1589806460-19592-1-git-send-email-Anson.Huang@nxp.com>
On Mon, May 18, 2020 at 08:54:19PM +0800, Anson Huang wrote:
> Interrupt is a required property according to SRC binding, add
> it for SRC node.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Applied both, thanks.
^ permalink raw reply
* Re: [PATCH] ARM: dts: imx: make src node name generic
From: Shawn Guo @ 2020-05-20 2:52 UTC (permalink / raw)
To: Anson Huang
Cc: robh+dt, s.hauer, kernel, festevam, devicetree, linux-arm-kernel,
linux-kernel, Linux-imx
In-Reply-To: <1589805593-14164-1-git-send-email-Anson.Huang@nxp.com>
On Mon, May 18, 2020 at 08:39:53PM +0800, Anson Huang wrote:
> Node name should be generic, use "reset-controller" instead of "src" for
> i.MX6/i.MX7 SoCs src nodes.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Applied, thanks.
^ permalink raw reply
* Re: [PATCHv1] ARM: dts/imx6q-bx50v3: Set display interface clock parents
From: Shawn Guo @ 2020-05-20 2:48 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Sebastian Reichel, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Rob Herring, devicetree,
linux-kernel, kernel, Robert Beckett, stable, Ian Ray
In-Reply-To: <20200514170236.24814-1-sebastian.reichel@collabora.com>
On Thu, May 14, 2020 at 07:02:37PM +0200, Sebastian Reichel wrote:
> From: Robert Beckett <bob.beckett@collabora.com>
>
> Avoid LDB and IPU DI clocks both using the same parent. LDB requires
> pasthrough clock to avoid breaking timing while IPU DI does not.
>
> Force IPU DI clocks to use IMX6QDL_CLK_PLL2_PFD0_352M as parent
> and LDB to use IMX6QDL_CLK_PLL5_VIDEO_DIV.
>
> This fixes an issue where attempting atomic modeset while using
> HDMI and display port at the same time causes LDB clock programming
> to destroy the programming of HDMI that was done during the same
> modeset.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
> [Use IMX6QDL_CLK_PLL2_PFD0_352M instead of IMX6QDL_CLK_PLL2_PFD2_396M
> originally chosen by Robert Beckett to avoid affecting eMMC clock
> by DRM atomic updates]
> Signed-off-by: Ian Ray <ian.ray@ge.com>
> [Squash Robert's and Ian's commits for bisectability, update patch
> description and add stable tag]
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Applied, thanks.
^ permalink raw reply
* Re: [PATCH v7 03/24] iommu/sva: Add PASID helpers
From: Lu Baolu @ 2020-05-20 2:41 UTC (permalink / raw)
To: Jean-Philippe Brucker, iommu, devicetree, linux-arm-kernel,
linux-pci, linux-mm
Cc: baolu.lu, joro, catalin.marinas, will, robin.murphy, kevin.tian,
Jonathan.Cameron, jacob.jun.pan, christian.koenig, felix.kuehling,
zhangfei.gao, jgg, xuzaibo, fenghua.yu, hch
In-Reply-To: <20200519175502.2504091-4-jean-philippe@linaro.org>
On 5/20/20 1:54 AM, Jean-Philippe Brucker wrote:
> Let IOMMU drivers allocate a single PASID per mm. Store the mm in the
> IOASID set to allow refcounting and searching mm by PASID, when handling
> an I/O page fault.
>
> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
> ---
> drivers/iommu/Kconfig | 5 +++
> drivers/iommu/Makefile | 1 +
> drivers/iommu/iommu-sva.h | 15 +++++++
> drivers/iommu/iommu-sva.c | 85 +++++++++++++++++++++++++++++++++++++++
> 4 files changed, 106 insertions(+)
> create mode 100644 drivers/iommu/iommu-sva.h
> create mode 100644 drivers/iommu/iommu-sva.c
>
> diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
> index 2ab07ce17abb..d9fa5b410015 100644
> --- a/drivers/iommu/Kconfig
> +++ b/drivers/iommu/Kconfig
> @@ -102,6 +102,11 @@ config IOMMU_DMA
> select IRQ_MSI_IOMMU
> select NEED_SG_DMA_LENGTH
>
> +# Shared Virtual Addressing library
> +config IOMMU_SVA
This looks too generic. It doesn't match the code it actually controls.
How about IOMMU_SVA_LIB?
> + bool
> + select IOASID > +
> config FSL_PAMU
> bool "Freescale IOMMU support"
> depends on PCI
> diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
> index 9f33fdb3bb05..40c800dd4e3e 100644
> --- a/drivers/iommu/Makefile
> +++ b/drivers/iommu/Makefile
> @@ -37,3 +37,4 @@ obj-$(CONFIG_S390_IOMMU) += s390-iommu.o
> obj-$(CONFIG_QCOM_IOMMU) += qcom_iommu.o
> obj-$(CONFIG_HYPERV_IOMMU) += hyperv-iommu.o
> obj-$(CONFIG_VIRTIO_IOMMU) += virtio-iommu.o
> +obj-$(CONFIG_IOMMU_SVA) += iommu-sva.o
> diff --git a/drivers/iommu/iommu-sva.h b/drivers/iommu/iommu-sva.h
> new file mode 100644
> index 000000000000..78f806fcacbe
> --- /dev/null
> +++ b/drivers/iommu/iommu-sva.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * SVA library for IOMMU drivers
> + */
> +#ifndef _IOMMU_SVA_H
> +#define _IOMMU_SVA_H
> +
> +#include <linux/ioasid.h>
> +#include <linux/mm_types.h>
> +
> +int iommu_sva_alloc_pasid(struct mm_struct *mm, ioasid_t min, ioasid_t max);
> +void iommu_sva_free_pasid(struct mm_struct *mm);
> +struct mm_struct *iommu_sva_find(ioasid_t pasid);
> +
> +#endif /* _IOMMU_SVA_H */
> diff --git a/drivers/iommu/iommu-sva.c b/drivers/iommu/iommu-sva.c
> new file mode 100644
> index 000000000000..442644a1ade0
> --- /dev/null
> +++ b/drivers/iommu/iommu-sva.c
> @@ -0,0 +1,85 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Helpers for IOMMU drivers implementing SVA
> + */
> +#include <linux/mutex.h>
> +#include <linux/sched/mm.h>
> +
> +#include "iommu-sva.h"
> +
> +static DEFINE_MUTEX(iommu_sva_lock);
> +static DECLARE_IOASID_SET(shared_pasid);
NIT: how about iommu_sva_pasid?
> +
> +/**
> + * iommu_sva_alloc_pasid - Allocate a PASID for the mm
> + * @mm: the mm
> + * @min: minimum PASID value (inclusive)
> + * @max: maximum PASID value (inclusive)
> + *
> + * Try to allocate a PASID for this mm, or take a reference to the existing one
> + * provided it fits within the [min, max] range. On success the PASID is
> + * available in mm->pasid, and must be released with iommu_sva_free_pasid().
> + *
> + * Returns 0 on success and < 0 on error.
> + */
> +int iommu_sva_alloc_pasid(struct mm_struct *mm, ioasid_t min, ioasid_t max)
> +{
> + int ret = 0;
> + ioasid_t pasid;
> +
> + if (min == INVALID_IOASID || max == INVALID_IOASID ||
> + min == 0 || max < min)
> + return -EINVAL;
> +
> + mutex_lock(&iommu_sva_lock);
> + if (mm->pasid) {
> + if (mm->pasid >= min && mm->pasid <= max)
> + ioasid_get(mm->pasid);
> + else
> + ret = -EOVERFLOW;
> + } else {
> + pasid = ioasid_alloc(&shared_pasid, min, max, mm);
> + if (pasid == INVALID_IOASID)
> + ret = -ENOMEM;
> + else
> + mm->pasid = pasid;
> + }
> + mutex_unlock(&iommu_sva_lock);
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(iommu_sva_alloc_pasid);
> +
> +/**
> + * iommu_sva_free_pasid - Release the mm's PASID
> + * @mm: the mm.
> + *
> + * Drop one reference to a PASID allocated with iommu_sva_alloc_pasid()
> + */
> +void iommu_sva_free_pasid(struct mm_struct *mm)
> +{
> + mutex_lock(&iommu_sva_lock);
> + if (ioasid_put(mm->pasid))
> + mm->pasid = 0;
> + mutex_unlock(&iommu_sva_lock);
> +}
> +EXPORT_SYMBOL_GPL(iommu_sva_free_pasid);
> +
> +/* ioasid wants a void * argument */
> +static bool __mmget_not_zero(void *mm)
> +{
> + return mmget_not_zero(mm);
> +}
> +
> +/**
> + * iommu_sva_find() - Find mm associated to the given PASID
> + * @pasid: Process Address Space ID assigned to the mm
> + *
> + * On success a reference to the mm is taken, and must be released with mmput().
> + *
> + * Returns the mm corresponding to this PASID, or an error if not found.
> + */
> +struct mm_struct *iommu_sva_find(ioasid_t pasid)
> +{
> + return ioasid_find(&shared_pasid, pasid, __mmget_not_zero);
> +}
> +EXPORT_SYMBOL_GPL(iommu_sva_find);
>
Best regards,
baolu
^ permalink raw reply
* Re: [PATCH v7 02/24] iommu/ioasid: Add ioasid references
From: Lu Baolu @ 2020-05-20 2:31 UTC (permalink / raw)
To: Jean-Philippe Brucker, iommu, devicetree, linux-arm-kernel,
linux-pci, linux-mm
Cc: baolu.lu, joro, catalin.marinas, will, robin.murphy, kevin.tian,
Jonathan.Cameron, jacob.jun.pan, christian.koenig, felix.kuehling,
zhangfei.gao, jgg, xuzaibo, fenghua.yu, hch
In-Reply-To: <20200519175502.2504091-3-jean-philippe@linaro.org>
On 5/20/20 1:54 AM, Jean-Philippe Brucker wrote:
> Let IOASID users take references to existing ioasids with ioasid_get().
> ioasid_put() drops a reference and only frees the ioasid when its
> reference number is zero. It returns true if the ioasid was freed.
> For drivers that don't call ioasid_get(), ioasid_put() is the same as
> ioasid_free().
>
> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
> ---
> v6->v7: rename ioasid_free() to ioasid_put(), add WARN in ioasid_get()
> ---
> include/linux/ioasid.h | 10 ++++++++--
> drivers/iommu/intel-iommu.c | 4 ++--
> drivers/iommu/intel-svm.c | 6 +++---
> drivers/iommu/ioasid.c | 38 +++++++++++++++++++++++++++++++++----
> 4 files changed, 47 insertions(+), 11 deletions(-)
>
> diff --git a/include/linux/ioasid.h b/include/linux/ioasid.h
> index 6f000d7a0ddc..e9dacd4b9f6b 100644
> --- a/include/linux/ioasid.h
> +++ b/include/linux/ioasid.h
> @@ -34,7 +34,8 @@ struct ioasid_allocator_ops {
> #if IS_ENABLED(CONFIG_IOASID)
> ioasid_t ioasid_alloc(struct ioasid_set *set, ioasid_t min, ioasid_t max,
> void *private);
> -void ioasid_free(ioasid_t ioasid);
> +void ioasid_get(ioasid_t ioasid);
> +bool ioasid_put(ioasid_t ioasid);
> void *ioasid_find(struct ioasid_set *set, ioasid_t ioasid,
> bool (*getter)(void *));
> int ioasid_register_allocator(struct ioasid_allocator_ops *allocator);
> @@ -48,10 +49,15 @@ static inline ioasid_t ioasid_alloc(struct ioasid_set *set, ioasid_t min,
> return INVALID_IOASID;
> }
>
> -static inline void ioasid_free(ioasid_t ioasid)
> +static inline void ioasid_get(ioasid_t ioasid)
> {
> }
>
> +static inline bool ioasid_put(ioasid_t ioasid)
> +{
> + return false;
> +}
> +
> static inline void *ioasid_find(struct ioasid_set *set, ioasid_t ioasid,
> bool (*getter)(void *))
> {
> diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
> index ed21ce6d1238..0230f35480ee 100644
> --- a/drivers/iommu/intel-iommu.c
> +++ b/drivers/iommu/intel-iommu.c
> @@ -5432,7 +5432,7 @@ static void auxiliary_unlink_device(struct dmar_domain *domain,
> domain->auxd_refcnt--;
>
> if (!domain->auxd_refcnt && domain->default_pasid > 0)
> - ioasid_free(domain->default_pasid);
> + ioasid_put(domain->default_pasid);
> }
>
> static int aux_domain_add_dev(struct dmar_domain *domain,
> @@ -5494,7 +5494,7 @@ static int aux_domain_add_dev(struct dmar_domain *domain,
> spin_unlock(&iommu->lock);
> spin_unlock_irqrestore(&device_domain_lock, flags);
> if (!domain->auxd_refcnt && domain->default_pasid > 0)
> - ioasid_free(domain->default_pasid);
> + ioasid_put(domain->default_pasid);
>
> return ret;
> }
> diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c
> index 2998418f0a38..86f1264bd07c 100644
> --- a/drivers/iommu/intel-svm.c
> +++ b/drivers/iommu/intel-svm.c
> @@ -353,7 +353,7 @@ int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_
> if (mm) {
> ret = mmu_notifier_register(&svm->notifier, mm);
> if (ret) {
> - ioasid_free(svm->pasid);
> + ioasid_put(svm->pasid);
> kfree(svm);
> kfree(sdev);
> goto out;
> @@ -371,7 +371,7 @@ int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_
> if (ret) {
> if (mm)
> mmu_notifier_unregister(&svm->notifier, mm);
> - ioasid_free(svm->pasid);
> + ioasid_put(svm->pasid);
> kfree(svm);
> kfree(sdev);
> goto out;
> @@ -447,7 +447,7 @@ int intel_svm_unbind_mm(struct device *dev, int pasid)
> kfree_rcu(sdev, rcu);
>
> if (list_empty(&svm->devs)) {
> - ioasid_free(svm->pasid);
> + ioasid_put(svm->pasid);
> if (svm->mm)
> mmu_notifier_unregister(&svm->notifier, svm->mm);
> list_del(&svm->list);
> diff --git a/drivers/iommu/ioasid.c b/drivers/iommu/ioasid.c
> index 0f8dd377aada..50ee27bbd04e 100644
> --- a/drivers/iommu/ioasid.c
> +++ b/drivers/iommu/ioasid.c
> @@ -2,7 +2,7 @@
> /*
> * I/O Address Space ID allocator. There is one global IOASID space, split into
> * subsets. Users create a subset with DECLARE_IOASID_SET, then allocate and
> - * free IOASIDs with ioasid_alloc and ioasid_free.
> + * free IOASIDs with ioasid_alloc and ioasid_put.
> */
> #include <linux/ioasid.h>
> #include <linux/module.h>
> @@ -15,6 +15,7 @@ struct ioasid_data {
> struct ioasid_set *set;
> void *private;
> struct rcu_head rcu;
> + refcount_t refs;
> };
>
> /*
> @@ -314,6 +315,7 @@ ioasid_t ioasid_alloc(struct ioasid_set *set, ioasid_t min, ioasid_t max,
>
> data->set = set;
> data->private = private;
> + refcount_set(&data->refs, 1);
>
> /*
> * Custom allocator needs allocator data to perform platform specific
> @@ -346,11 +348,34 @@ ioasid_t ioasid_alloc(struct ioasid_set *set, ioasid_t min, ioasid_t max,
> EXPORT_SYMBOL_GPL(ioasid_alloc);
>
> /**
> - * ioasid_free - Free an IOASID
> + * ioasid_get - obtain a reference to the IOASID
> + */
> +void ioasid_get(ioasid_t ioasid)
> +{
> + struct ioasid_data *ioasid_data;
> +
> + spin_lock(&ioasid_allocator_lock);
> + ioasid_data = xa_load(&active_allocator->xa, ioasid);
> + if (ioasid_data)
> + refcount_inc(&ioasid_data->refs);
> + else
> + WARN_ON(1);
> + spin_unlock(&ioasid_allocator_lock);
> +}
> +EXPORT_SYMBOL_GPL(ioasid_get);
> +
> +/**
> + * ioasid_put - Release a reference to an ioasid
> * @ioasid: the ID to remove
> + *
> + * Put a reference to the IOASID, free it when the number of references drops to
> + * zero.
> + *
> + * Return: %true if the IOASID was freed, %false otherwise.
> */
> -void ioasid_free(ioasid_t ioasid)
> +bool ioasid_put(ioasid_t ioasid)
> {
> + bool free = false;
> struct ioasid_data *ioasid_data;
>
> spin_lock(&ioasid_allocator_lock);
> @@ -360,6 +385,10 @@ void ioasid_free(ioasid_t ioasid)
> goto exit_unlock;
> }
>
> + free = refcount_dec_and_test(&ioasid_data->refs);
> + if (!free)
> + goto exit_unlock;
> +
> active_allocator->ops->free(ioasid, active_allocator->ops->pdata);
> /* Custom allocator needs additional steps to free the xa element */
> if (active_allocator->flags & IOASID_ALLOCATOR_CUSTOM) {
> @@ -369,8 +398,9 @@ void ioasid_free(ioasid_t ioasid)
>
> exit_unlock:
> spin_unlock(&ioasid_allocator_lock);
> + return free;
> }
> -EXPORT_SYMBOL_GPL(ioasid_free);
> +EXPORT_SYMBOL_GPL(ioasid_put);
>
> /**
> * ioasid_find - Find IOASID data
>
Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com>
Best regards,
baolu
^ permalink raw reply
* Re: [PATCH 1/2] ARM: dts: imx6qdl: Use nvmem interface to get fuse data
From: Shawn Guo @ 2020-05-20 2:21 UTC (permalink / raw)
To: Anson Huang
Cc: robh+dt, s.hauer, kernel, festevam, devicetree, linux-arm-kernel,
linux-kernel, Linux-imx
In-Reply-To: <1589418528-26410-1-git-send-email-Anson.Huang@nxp.com>
On Thu, May 14, 2020 at 09:08:47AM +0800, Anson Huang wrote:
> Although ocotp clock is always ON for i.MX6QDL, OCOTP can be
> accessed directly, but since i.MX6QDL nvmem interface is supported,
> and fsl,tempmon-data is deprecated, use it instead of getting fuse
> data by reading ocotp directly, this makes all i.MX6 SoCs aligned.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Applied both, thanks.
^ permalink raw reply
* Re: [PATCH] ARM: dts: imx6qdl-gw5910: fix wlan regulator
From: Shawn Guo @ 2020-05-20 2:19 UTC (permalink / raw)
To: Tim Harvey
Cc: Rob Herring, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <1589320954-25219-1-git-send-email-tharvey@gateworks.com>
On Tue, May 12, 2020 at 03:02:34PM -0700, Tim Harvey wrote:
> Connect the wl_reg regulator to usdhc2 such that it can be enabled
> and disabled as needed. There is no need for this to be always-on.
>
> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Applied, thanks.
^ permalink raw reply
* Re: [PATCH] ARM: dts: imx6qdl-gw5910: add support for bcm4330-bt
From: Shawn Guo @ 2020-05-20 2:18 UTC (permalink / raw)
To: Tim Harvey
Cc: Rob Herring, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <1589320455-23844-1-git-send-email-tharvey@gateworks.com>
On Tue, May 12, 2020 at 02:54:15PM -0700, Tim Harvey wrote:
> The Sterling-LWB has a BCM4330 which has a UART based bluetooth
> HCI. Add support for binding to the bcm_hci driver to take care
> of handling the shutdown gpio and loading firmware.
>
> Because the shutdown gpio is more of an enable than a regulator
> go ahead and replace the regulator with a shutdown-gpio.
>
> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Applied, thanks.
^ permalink raw reply
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