* [PATCH v3 0/3] Add Qualcomm IPCC driver support
From: Manivannan Sadhasivam @ 2020-05-20 8:48 UTC (permalink / raw)
To: jassisinghbrar, robh+dt
Cc: bjorn.andersson, linux-arm-msm, linux-kernel, devicetree,
Manivannan Sadhasivam
Hello,
This series adds mailbox driver support for Qualcomm Inter Processor
Communications Controller (IPCC) block found in MSM chipsets. This block
is used to route interrupts between modems, DSPs and APSS (Application
Processor Subsystem).
The driver is modeled as a mailbox+irqchip driver. The irqchip part helps
in receiving the interrupts from the IPCC clients such as modems, DSPs,
PCI-E etc... and forwards them to respective entities in APSS.
On the other hand, the mailbox part is used to send interrupts to the IPCC
clients from the entities of APSS.
This series is tested on SM8250-MTP board.
Thanks,
Mani
Changes in v3:
* Added Bjorn's review tags
* Few changes to DT binding as suggested by Rob
Changes in v2:
* Moved from soc/ to mailbox/
* Switched to static mbox channels
* Some misc cleanups
Manivannan Sadhasivam (3):
dt-bindings: mailbox: Add devicetree binding for Qcom IPCC
mailbox: Add support for Qualcomm IPCC
MAINTAINERS: Add entry for Qualcomm IPCC driver
.../bindings/mailbox/qcom-ipcc.yaml | 80 +++++
MAINTAINERS | 8 +
drivers/mailbox/Kconfig | 10 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/qcom-ipcc.c | 286 ++++++++++++++++++
include/dt-bindings/mailbox/qcom-ipcc.h | 33 ++
6 files changed, 419 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
create mode 100644 drivers/mailbox/qcom-ipcc.c
create mode 100644 include/dt-bindings/mailbox/qcom-ipcc.h
--
2.26.GIT
^ permalink raw reply
* Re: [PATCH v2 2/2] i2c: mediatek: Add i2c ac-timing adjust support
From: Qii Wang @ 2020-05-20 8:41 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Joe Perches,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
srv_heupstream, Wolfram Sang, leilk.liu,
Linux Kernel Mailing List, linux-mediatek, Linux I2C, Linux ARM
In-Reply-To: <CAMuHMdXgp85PVteunxrHYcMTqFgQWHmXXCVJM_KX76xkCADMpw@mail.gmail.com>
Hi Geert,
On Tue, 2020-05-19 at 09:14 +0200, Geert Uytterhoeven wrote:
> Hi Qii,
>
> On Tue, May 19, 2020 at 4:59 AM Qii Wang <qii.wang@mediatek.com> wrote:
> > On Mon, 2020-05-18 at 17:44 +0200, Geert Uytterhoeven wrote:
> > > On Thu, May 14, 2020 at 3:13 PM Qii Wang <qii.wang@mediatek.com> wrote:
> > > > This patch adds a algorithm to calculate some ac-timing parameters
> > > > which can fully meet I2C Spec.
> > > >
> > > > Signed-off-by: Qii Wang <qii.wang@mediatek.com>
> > > > ---
> > > > drivers/i2c/busses/i2c-mt65xx.c | 328 +++++++++++++++++++++++++++++++++-------
> > > > 1 file changed, 277 insertions(+), 51 deletions(-)
> > > >
> > > > diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> > > > index 0ca6c38a..7020618 100644
> > > > --- a/drivers/i2c/busses/i2c-mt65xx.c
> > > > +++ b/drivers/i2c/busses/i2c-mt65xx.c
> > >
> > > > +/*
> > > > + * Check and Calculate i2c ac-timing
> > > > + *
> > > > + * Hardware design:
> > > > + * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
> > > > + * xxx_cnt_div = spec->min_xxx_ns / sample_ns
> > > > + *
> > > > + * Sample_ns is rounded down for xxx_cnt_div would be greater
> > > > + * than the smallest spec.
> > > > + * The sda_timing is chosen as the middle value between
> > > > + * the largest and smallest.
> > > > + */
> > > > +static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c,
> > > > + unsigned int clk_src,
> > > > + unsigned int check_speed,
> > > > + unsigned int step_cnt,
> > > > + unsigned int sample_cnt)
> > > > +{
> > > > + const struct i2c_spec_values *spec;
> > > > + unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
> > > > + unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f;
> > > > + long long sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src;
> > >
> > > So sample_ns is a 64-bit value. Is that really needed?
> > >
> >
> > (1000000000 * (sample_cnt + 1)) / clk_src value is a 32-bit, (1000000000
> > * (sample_cnt + 1)) will over 32-bit if sample_cnt is 7.
>
> The intermediate value will indeed not fit in 32-bit.
> But that doesn't mean the end result won't fit in 32-bit.
> As you divide spec->min_low_ns and spec->min_su_dat_ns (which I assume
> are small numbers) by sample_ns below, sample_ns cannot be very large,
> or the quotient will be zero anyway.
> So just doing the multiplication in 64-bit, followed by a 64-by-32
> division is probably fine:
>
> unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1), clk_src);
>
> You may want to take precautions for the case where the passed value of
> clk_src is a small number (can that happen?).
>
> BTW, clk_get_rate() returns "unsigned long", while mtk_i2c_set_speed()
> takes an "unsigned int" parent_clk, which may cause future issues.
> You may want to change that to "unsigned long", along the whole
> propagation path, and use div64_ul() instead of div_u64() above.
>
The return type of div_u64 is u64(unsigned long long), there is a
compulsory type conversion operator. Do you think it is needed?
BTW, we just need to change the type of sample_ns to unsigned int, no
matter which method is used, what is your opinion?
> > I think 1000000000 and clk_src is too big, maybe I can reduce then with
> > be divided all by 1000.
> > example:
> >
> > unsigned int sample_ns;
> > unsigned int clk_src_khz = clk_src / 1000;
>
> That may cause too much loss of precision.
>
clk_src is more than MHz and less than GHZ for MTK i2c controller, so it
wouldn't cause too much loss of precision.
> >
> > if(clk_src_khz)
> > sample_ns = (1000000 * (sample_cnt + 1)) / clk_src_khz;
> > else
> > return -EINVAL;
> >
> > > > + if (!i2c->dev_comp->timing_adjust)
> > > > + return 0;
> > > > +
> > > > + if (i2c->dev_comp->ltiming_adjust)
> > > > + max_sta_cnt = 0x100;
> > > > +
> > > > + spec = mtk_i2c_get_spec(check_speed);
> > > > +
> > > > + if (i2c->dev_comp->ltiming_adjust)
> > > > + clk_ns = 1000000000 / clk_src;
> > > > + else
> > > > + clk_ns = sample_ns / 2;
> > > > +
> > > > + su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns);
> > > > + if (su_sta_cnt > max_sta_cnt)
> > > > + return -1;
> > > > +
> > > > + low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
> > >
> > > So this is a 32-bit by 64-bit division (indeed, not 64-by-32!)
>
> Gr{oetje,eeting}s,
>
> Geert
>
^ permalink raw reply
* Re: [PATCH 2/4] dt-bindings: sram: add documentation for reserved-only flag
From: Thierry Reding @ 2020-05-20 8:40 UTC (permalink / raw)
To: Mian Yousaf Kaukab
Cc: Stephen Warren, robh+dt, robin.murphy, devicetree, talho,
jonathanh, linux-tegra, linux-kernel, linux-arm-kernel, afaerber,
arnd, gregkh
In-Reply-To: <20200513104127.GA2309@suse.de>
[-- Attachment #1: Type: text/plain, Size: 3083 bytes --]
On Wed, May 13, 2020 at 12:41:27PM +0200, Mian Yousaf Kaukab wrote:
> On Tue, May 12, 2020 at 01:45:28PM -0600, Stephen Warren wrote:
> > On 5/12/20 8:48 AM, Mian Yousaf Kaukab wrote:
> > > Add documentation for the new optional flag added for SRAM driver.
> >
> > > diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml
> >
> > > + reserved-only:
> > > + description:
> > > + The flag indicating, that only SRAM reserved regions have to be remapped.
> > > + remapping type is selected depending upon no-memory-wc as usual.
> > > + type: boolean
> >
> > This feels a bit like a SW flag rather than a HW description, so I'm not
> > sure it's appropriate to put it into DT.
>
> Reserved regions themselves are software descriptions, no? Then we have 'pool'
> flag which is again a software flag and so on. This flag falls into same
> category and nothing out of ordinary.
> >
> > Are there any cases where the SW should map all of the SRAM, i.e. where
> > we wouldn't expect to set reserved-only? [...]
>
> Yes, here are a few examples:
> arch/arm/boot/dts/aspeed-g*.dtsi
Looking at the implementation of the sole user of this, which is in
drivers/fsi/fsi-master-ast-cf.c, it looks like this really should've
specified a partition because the driver basically goes on to allocate
a fixed 4 KiB region of memory anyway.
> arch/arm/boot/dts/at91*.dtsi
While these define SRAM nodes, I don't see them referenced anywhere.
> arch/arm/boot/dts/bcm7445.dtsi
> Then arch/arm/boot/dts/dra7.dtsi is an example where we should map everything
> except the reserved region.
The driver currently maps everything, so if this relies on this
particular reserved region not being mapped then that's already broken
anyway.
> > [...] I'd expect reserved-only to be
> > the default, and perhaps only, mode of operation for the SRAM driver.
>
> It will break compatibility with existing dtbs.
Yes, that's a bit unfortunate. I think this driver may suffer from a
slightly ambiguous device tree binding and then people just trying to
fit it to their use-cases.
However, I think we could preserve DTB backwards-compatibility while at
the same time correcting course and establish some sort of consistency.
Looking at the examples that you've provided and others, there are two
classes of users: users that don't specify any partitions either use all
of the available SRAM exclusively or manually allocate some part of it,
whereas users that have specified partitions all seem to use only the
defined partitions.
Given that, I think what we could do is check if there are any child
nodes and if not, keep the existing behaviour of mapping the whole SRAM
area. For cases where child nodes exist we could decide to go with the
default that Stephen suggested and only map regions for which a child
node has been defined.
This should allow both categories of users to work the way that they
were probably expected to work.
Any thoughts?
Thierry
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^ permalink raw reply
* [PATCH net 4/4] ARM: dts: imx6qdl-sabresd: enable fec wake-on-lan
From: fugang.duan @ 2020-05-20 8:31 UTC (permalink / raw)
To: davem; +Cc: netdev, martin.fuzzey, robh+dt, shawnguo, devicetree, fugang.duan
In-Reply-To: <1589963516-26703-1-git-send-email-fugang.duan@nxp.com>
From: Fugang Duan <fugang.duan@nxp.com>
Enable ethernet wake-on-lan feature for imx6q/dl/qp sabresd
boards since the PHY clock is supplied by exteranl osc.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
---
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index fe59dde..28b35cc 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -204,6 +204,7 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ fsl,magic-packet;
status = "okay";
};
--
2.7.4
^ permalink raw reply related
* [PATCH net 3/4] ARM: dts: imx6: update fec gpr property to match new format
From: fugang.duan @ 2020-05-20 8:31 UTC (permalink / raw)
To: davem; +Cc: netdev, martin.fuzzey, robh+dt, shawnguo, devicetree, fugang.duan
In-Reply-To: <1589963516-26703-1-git-send-email-fugang.duan@nxp.com>
From: Fugang Duan <fugang.duan@nxp.com>
Update the gpr property to define gpr register offset and
bit in DT.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
---
arch/arm/boot/dts/imx6qdl.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 98da446..a4a68b7 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1045,7 +1045,7 @@
<&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "ptp";
- gpr = <&gpr>;
+ gpr = <&gpr 0x34 27>;
status = "disabled";
};
--
2.7.4
^ permalink raw reply related
* [PATCH net 2/4] dt-bindings: fec: update the gpr property
From: fugang.duan @ 2020-05-20 8:31 UTC (permalink / raw)
To: davem; +Cc: netdev, martin.fuzzey, robh+dt, shawnguo, devicetree, fugang.duan
In-Reply-To: <1589963516-26703-1-git-send-email-fugang.duan@nxp.com>
From: Fugang Duan <fugang.duan@nxp.com>
Update the gpr property to define gpr register offset and
bit in DT, since different instance have different gpr bit,
and differnet SOC may have different gpr reigster offset.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
---
Documentation/devicetree/bindings/net/fsl-fec.txt | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt
index 26c492a..c2ea818 100644
--- a/Documentation/devicetree/bindings/net/fsl-fec.txt
+++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
@@ -23,7 +23,12 @@ Optional properties:
the hardware workaround for ERR006687 applied and does not need a software
workaround.
- gpr: phandle of SoC general purpose register mode. Required for wake on LAN
- on some SoCs
+ on some SoCs. Register bits of stop mode control, the format is
+ <&gpr req_gpr req_bit>.
+ gpr is the phandle to general purpose register node.
+ req_gpr is the gpr register offset for ENET stop request.
+ req_bit is the gpr bit offset for ENET stop request.
+
-interrupt-names: names of the interrupts listed in interrupts property in
the same order. The defaults if not specified are
__Number of interrupts__ __Default__
--
2.7.4
^ permalink raw reply related
* [PATCH net 1/4] net: ethernet: fec: move GPR register offset and bit into DT
From: fugang.duan @ 2020-05-20 8:31 UTC (permalink / raw)
To: davem; +Cc: netdev, martin.fuzzey, robh+dt, shawnguo, devicetree, fugang.duan
In-Reply-To: <1589963516-26703-1-git-send-email-fugang.duan@nxp.com>
From: Fugang Duan <fugang.duan@nxp.com>
The commit da722186f654(net: fec: set GPR bit on suspend by DT
configuration) set the GPR reigster offset and bit in driver for
wake on lan feature.
But it introduces two issues here:
- one SOC has two instances, they have different bit
- different SOCs may have different offset and bit
So to support wake-on-lan feature on other i.MX platforms, it should
configure the GPR reigster offset and bit from DT.
Fixes: da722186f654(net: fec: set GPR bit on suspend by DT configuration)
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
---
drivers/net/ethernet/freescale/fec_main.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
index 2e20914..9606411 100644
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -88,8 +88,6 @@ static void fec_enet_itr_coal_init(struct net_device *ndev);
struct fec_devinfo {
u32 quirks;
- u8 stop_gpr_reg;
- u8 stop_gpr_bit;
};
static const struct fec_devinfo fec_imx25_info = {
@@ -112,8 +110,6 @@ static const struct fec_devinfo fec_imx6q_info = {
FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
FEC_QUIRK_HAS_RACC,
- .stop_gpr_reg = 0x34,
- .stop_gpr_bit = 27,
};
static const struct fec_devinfo fec_mvf600_info = {
@@ -3476,19 +3472,23 @@ static int fec_enet_get_irq_cnt(struct platform_device *pdev)
}
static int fec_enet_init_stop_mode(struct fec_enet_private *fep,
- struct fec_devinfo *dev_info,
struct device_node *np)
{
struct device_node *gpr_np;
+ u32 out_val[3];
int ret = 0;
- if (!dev_info)
- return 0;
-
gpr_np = of_parse_phandle(np, "gpr", 0);
if (!gpr_np)
return 0;
+ ret = of_property_read_u32_array(np, "gpr", out_val,
+ ARRAY_SIZE(out_val));
+ if (ret) {
+ dev_dbg(&fep->pdev->dev, "no stop mode property\n");
+ return ret;
+ }
+
fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np);
if (IS_ERR(fep->stop_gpr.gpr)) {
dev_err(&fep->pdev->dev, "could not find gpr regmap\n");
@@ -3497,8 +3497,8 @@ static int fec_enet_init_stop_mode(struct fec_enet_private *fep,
goto out;
}
- fep->stop_gpr.reg = dev_info->stop_gpr_reg;
- fep->stop_gpr.bit = dev_info->stop_gpr_bit;
+ fep->stop_gpr.reg = out_val[1];
+ fep->stop_gpr.bit = out_val[2];
out:
of_node_put(gpr_np);
@@ -3575,7 +3575,7 @@ fec_probe(struct platform_device *pdev)
if (of_get_property(np, "fsl,magic-packet", NULL))
fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
- ret = fec_enet_init_stop_mode(fep, dev_info, np);
+ ret = fec_enet_init_stop_mode(fep, np);
if (ret)
goto failed_stop_mode;
--
2.7.4
^ permalink raw reply related
* [PATCH net 0/4] net: ethernet: fec: move GPR reigster offset and bit into DT
From: fugang.duan @ 2020-05-20 8:31 UTC (permalink / raw)
To: davem; +Cc: netdev, martin.fuzzey, robh+dt, shawnguo, devicetree, fugang.duan
From: Fugang Duan <fugang.duan@nxp.com>
The commit da722186f654(net: fec: set GPR bit on suspend by DT configuration)
set the GPR reigster offset and bit in driver for wake on lan feature.
It bring trouble to enable wake-on-lan feature on other i.MX platforms
because imx6ul/imx7d/imx8 has two instances, they have different gpr bit.
So to support wake-on-lan feature on other i.MX platforms, it should
configure the GPR reigster offset and bit from DT.
Fugang Duan (4):
net: ethernet: fec: move GPR register offset and bit into DT
dt-bindings: fec: update the gpr property
ARM: dts: imx6: update fec gpr property to match new format
ARM: dts: imx6qdl-sabresd: enable fec wake-on-lan
Documentation/devicetree/bindings/net/fsl-fec.txt | 7 ++++++-
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 1 +
arch/arm/boot/dts/imx6qdl.dtsi | 2 +-
drivers/net/ethernet/freescale/fec_main.c | 22 +++++++++++-----------
4 files changed, 19 insertions(+), 13 deletions(-)
--
2.7.4
^ permalink raw reply
* RE: [RESEND 1/4] arm64: dts: lx2160a: add ftm_alarm0 DT node
From: Biwen Li (OSS) @ 2020-05-20 8:27 UTC (permalink / raw)
To: Shawn Guo, Biwen Li (OSS)
Cc: Ran Wang, robh+dt@kernel.org, mark.rutland@arm.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Jiafei Pan
In-Reply-To: <20200511141649.GA26831@dragon>
> > > > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > > > b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > > > index e5ee5591e52b..e0d8d68ce070 100644
> > > > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > > > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > > > @@ -16,6 +16,10 @@
> > > > #address-cells = <2>;
> > > > #size-cells = <2>;
> > > >
> > > > + aliases {
> > > > + rtc1 = &ftm_alarm0;
> > > > + };
> > > > +
> > > > cpus {
> > > > #address-cells = <1>;
> > > > #size-cells = <0>;
> > > > @@ -768,6 +772,20 @@
> > > > timeout-sec = <30>;
> > > > };
> > > >
> > > > + rcpm: rcpm@1e34040 {
> > >
> > > Keep the node sort in unit-address. Also, try to use a generic node name.
> > Hi Shawn,
> > Sorry for late reply.
> > The node sort will be updated in v2.
> > rcpm is called as Run Control and Power Management. Don't Have a
> > generic node name, any suggestions?
>
> It sounds like some sort of power controller, so maybe 'power-controller'?
Okay, How about replace it with "rcpm: power-controller@1e34040 {"?
>
> Shawn
^ permalink raw reply
* [PATCH V3] dt-bindings: thermal: Convert i.MX to json-schema
From: Anson Huang @ 2020-05-20 8:16 UTC (permalink / raw)
To: rui.zhang, daniel.lezcano, amit.kucheria, robh+dt, shawnguo,
s.hauer, kernel, festevam, linux-pm, devicetree, linux-arm-kernel,
linux-kernel
Cc: Linux-imx
Convert the i.MX thermal binding to DT schema format using json-schema
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Changes since V2:
- remove unnecessary property in compatible;
- add detail description for interrupts;
- add description for each item of nvmem-cells;
- add more detail for "fsl,tempmon" description.
---
.../devicetree/bindings/thermal/imx-thermal.txt | 61 ------------
.../devicetree/bindings/thermal/imx-thermal.yaml | 102 +++++++++++++++++++++
2 files changed, 102 insertions(+), 61 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/thermal/imx-thermal.txt
create mode 100644 Documentation/devicetree/bindings/thermal/imx-thermal.yaml
diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.txt b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
deleted file mode 100644
index 823e417..0000000
--- a/Documentation/devicetree/bindings/thermal/imx-thermal.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-* Temperature Monitor (TEMPMON) on Freescale i.MX SoCs
-
-Required properties:
-- compatible : must be one of following:
- - "fsl,imx6q-tempmon" for i.MX6Q,
- - "fsl,imx6sx-tempmon" for i.MX6SX,
- - "fsl,imx7d-tempmon" for i.MX7S/D.
-- interrupts : the interrupt output of the controller:
- i.MX6Q has one IRQ which will be triggered when temperature is higher than high threshold,
- i.MX6SX and i.MX7S/D have two more IRQs than i.MX6Q, one is IRQ_LOW and the other is IRQ_PANIC,
- when temperature is below than low threshold, IRQ_LOW will be triggered, when temperature
- is higher than panic threshold, system will auto reboot by SRC module.
-- fsl,tempmon : phandle pointer to system controller that contains TEMPMON
- control registers, e.g. ANATOP on imx6q.
-- nvmem-cells: A phandle to the calibration cells provided by ocotp.
-- nvmem-cell-names: Should be "calib", "temp_grade".
-
-Deprecated properties:
-- fsl,tempmon-data : phandle pointer to fuse controller that contains TEMPMON
- calibration data, e.g. OCOTP on imx6q. The details about calibration data
- can be found in SoC Reference Manual.
-
-Direct access to OCOTP via fsl,tempmon-data is incorrect on some newer chips
-because it does not handle OCOTP clock requirements.
-
-Optional properties:
-- clocks : thermal sensor's clock source.
-
-Example:
-ocotp: ocotp@21bc000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,imx6sx-ocotp", "syscon";
- reg = <0x021bc000 0x4000>;
- clocks = <&clks IMX6SX_CLK_OCOTP>;
-
- tempmon_calib: calib@38 {
- reg = <0x38 4>;
- };
-
- tempmon_temp_grade: temp-grade@20 {
- reg = <0x20 4>;
- };
-};
-
-tempmon: tempmon {
- compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- fsl,tempmon = <&anatop>;
- nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
- nvmem-cell-names = "calib", "temp_grade";
- clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
-};
-
-Legacy method (Deprecated):
-tempmon {
- compatible = "fsl,imx6q-tempmon";
- fsl,tempmon = <&anatop>;
- fsl,tempmon-data = <&ocotp>;
- clocks = <&clks 172>;
-};
diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.yaml b/Documentation/devicetree/bindings/thermal/imx-thermal.yaml
new file mode 100644
index 0000000..8bfd9f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/imx-thermal.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/imx-thermal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX Thermal Binding
+
+maintainers:
+ - Shawn Guo <shawn.guo@linaro.org>
+ - Anson Huang <Anson.Huang@nxp.com>
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx6q-tempmon
+ - fsl,imx6sx-tempmon
+ - fsl,imx7d-tempmon
+
+ interrupts:
+ description: |
+ The interrupt output of the controller, i.MX6Q has IRQ_HIGH which
+ will be triggered when temperature is higher than high threshold,
+ i.MX6SX and i.MX7S/D have two more IRQs than i.MX6Q, one is IRQ_LOW
+ and the other is IRQ_PANIC, when temperature is lower than low
+ threshold, IRQ_LOW will be triggered, when temperature is higher
+ than panic threshold, IRQ_PANIC will be triggered, and system can
+ be configured to auto reboot by SRC module for IRQ_PANIC. IRQ_HIGH,
+ IRQ_LOW and IRQ_PANIC share same interrupt output of controller.
+ maxItems: 1
+
+ nvmem-cells:
+ items:
+ - description: Phandle to the calibration data provided by ocotp
+ - description: Phandle to the temperature grade provided by ocotp
+
+ nvmem-cell-names:
+ items:
+ - const: calib
+ - const: temp_grade
+
+ fsl,tempmon:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: Phandle to the temperature sensor register map node.
+
+ fsl,tempmon-data:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: |
+ Deprecated property, phandle pointer to fuse controller that contains
+ TEMPMON calibration data, e.g. OCOTP on imx6q. The details about
+ calibration data can be found in SoC Reference Manual.
+ deprecated: true
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - interrupts
+ - fsl,tempmon
+ - nvmem-cells
+ - nvmem-cell-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx6sx-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ efuse@21bc000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,imx6sx-ocotp", "syscon";
+ reg = <0x021bc000 0x4000>;
+ clocks = <&clks IMX6SX_CLK_OCOTP>;
+
+ tempmon_calib: calib@38 {
+ reg = <0x38 4>;
+ };
+
+ tempmon_temp_grade: temp-grade@20 {
+ reg = <0x20 4>;
+ };
+ };
+
+ anatop@20c8000 {
+ compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
+ reg = <0x020c8000 0x1000>;
+ interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
+ <0 54 IRQ_TYPE_LEVEL_HIGH>,
+ <0 127 IRQ_TYPE_LEVEL_HIGH>;
+
+ tempmon {
+ compatible = "fsl,imx6sx-tempmon";
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tempmon = <&anatop>;
+ nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
+ nvmem-cell-names = "calib", "temp_grade";
+ clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
+ };
+ };
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v4 1/4] dt-bindings: iio: magnetometer: ak8975: convert txt format to yaml
From: Andy Shevchenko @ 2020-05-20 8:23 UTC (permalink / raw)
To: Jonathan Albrieux
Cc: Linux Kernel Mailing List, ~postmarketos/upstreaming,
Allison Randal, Andy Shevchenko,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Greg Kroah-Hartman, Hartmut Knaack, Jilayne Lovejoy,
Jonathan Cameron, Kate Stewart, Lars-Peter Clausen, Linus Walleij,
open list:IIO SUBSYSTEM AND DRIVERS, Peter Meerwald-Stadler,
Thomas Gleixner, Jonathan Cameron, Rob Herring
In-Reply-To: <20200520073125.30808-2-jonathan.albrieux@gmail.com>
On Wed, May 20, 2020 at 10:32 AM Jonathan Albrieux
<jonathan.albrieux@gmail.com> wrote:
> +maintainers:
> + - can't find a maintainer, author is Laxman Dewangan <ldewangan@nvidia.com>
Alas, you'll never go forward with this.
One (easiest way) is to drop this patch completely if you won't be a
maintainer of the binding.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* RE: [PATCH] ARM: dts: imx: Make tempmon node as child of anatop node
From: Anson Huang @ 2020-05-20 8:11 UTC (permalink / raw)
To: Aisheng Dong, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: dl-linux-imx
In-Reply-To: <AM6PR04MB496661BDF6B5F966A218092380B60@AM6PR04MB4966.eurprd04.prod.outlook.com>
> Subject: RE: [PATCH] ARM: dts: imx: Make tempmon node as child of anatop
> node
>
> > From: Anson Huang <anson.huang@nxp.com>
> > Sent: Wednesday, May 20, 2020 3:47 PM
> >
> > > Subject: RE: [PATCH] ARM: dts: imx: Make tempmon node as child of
> > > anatop node
> > >
> > > > From: Anson Huang <Anson.Huang@nxp.com>
> > > > Sent: Wednesday, May 20, 2020 2:30 PM
> > > >
> > > > i.MX6/7 SoCs' temperature sensor is inside anatop module from HW
> > > > perspective, so it should be a child node of anatop.
> > > >
> > > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> > >
> > > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
> > >
> > > BTW, I think you also need a binding doc for this change.
> >
> > The binding doc is the imx-thermal.yaml I sent out, it is suggested by
> > Rob to move tempmon into anatop node, that is why I did this patch to
> > align with the binding doc.
>
> That's thermal binding doc.
> We need a binding doc to describe the constraints for anatop as well.
anatop includes PMU, thermal etc., need to think about
how to add it and where to put it, will think about it later.
Anson
^ permalink raw reply
* RE: [PATCH] ARM: dts: imx: Make tempmon node as child of anatop node
From: Aisheng Dong @ 2020-05-20 8:06 UTC (permalink / raw)
To: Anson Huang, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: dl-linux-imx
In-Reply-To: <DB3PR0402MB39167A0961963B73758F6CA9F5B60@DB3PR0402MB3916.eurprd04.prod.outlook.com>
> From: Anson Huang <anson.huang@nxp.com>
> Sent: Wednesday, May 20, 2020 3:47 PM
>
> > Subject: RE: [PATCH] ARM: dts: imx: Make tempmon node as child of
> > anatop node
> >
> > > From: Anson Huang <Anson.Huang@nxp.com>
> > > Sent: Wednesday, May 20, 2020 2:30 PM
> > >
> > > i.MX6/7 SoCs' temperature sensor is inside anatop module from HW
> > > perspective, so it should be a child node of anatop.
> > >
> > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> >
> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
> >
> > BTW, I think you also need a binding doc for this change.
>
> The binding doc is the imx-thermal.yaml I sent out, it is suggested by Rob to
> move tempmon into anatop node, that is why I did this patch to align with the
> binding doc.
That's thermal binding doc.
We need a binding doc to describe the constraints for anatop as well.
Regards
Aisheng
> Anson
^ permalink raw reply
* RE: [PATCH V2] dt-bindings: thermal: Convert i.MX to json-schema
From: Anson Huang @ 2020-05-20 8:03 UTC (permalink / raw)
To: Aisheng Dong, rui.zhang@intel.com, daniel.lezcano@linaro.org,
amit.kucheria@verdurent.com, robh+dt@kernel.org,
shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: dl-linux-imx
In-Reply-To: <AM6PR04MB4966F875F2E04D0F6FC3AE3A80B60@AM6PR04MB4966.eurprd04.prod.outlook.com>
> Subject: RE: [PATCH V2] dt-bindings: thermal: Convert i.MX to json-schema
>
> > From: Anson Huang <Anson.Huang@nxp.com>
> > Sent: Wednesday, May 20, 2020 2:03 PM
> >
> > Convert the i.MX thermal binding to DT schema format using json-schema
> >
> > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> > ---
> > Changes since V1:
> > - move tempmon node into its parent node anatop in example;
> > - improve "fsl,tempmon" description.
> > ---
> > .../devicetree/bindings/thermal/imx-thermal.txt | 61 -------------
> > .../devicetree/bindings/thermal/imx-thermal.yaml | 100
>
> [...]
>
> > +title: NXP i.MX Thermal Binding
> > +
> > +maintainers:
> > + - Shawn Guo <shawn.guo@linaro.org>
> > + - Anson Huang <Anson.Huang@nxp.com>
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
>
> Drop Unnecessary properties
Will use enum directly.
>
> > + - enum:
> > + - fsl,imx6q-tempmon
> > + - fsl,imx6sx-tempmon
> > + - fsl,imx7d-tempmon
> > +
> > + interrupts:
> > + description: |
> > + The interrupt output of the controller, the IRQ will be triggered
> > + when temperature is higher than high threshold.
> > + maxItems: 1
>
> You'd better explain why interrupts number is changed in the new binding
> compared to the original one. Probably add in commit message if really
> needed.
There is ONLY 1 interrupt output from temperature to GIC, some platforms like
i.MX6SX/i.MX7D has 2 more secondary interrupts inside anatop which shares same output
interrupt to GIC, these 2 interrupts are NOT used for now, so from the high level
description of the interrupt, should be ONLY 1 interrupt item I think.
>
> > +
> > + nvmem-cells:
> > + description: |
> > + Phandle to the calibration cells provided by ocotp for calibration
> > + data and temperature grade.
>
> Better describe for each of them as you did for clocks
Will do in V3.
>
> > + maxItems: 2
> > +
> > + nvmem-cell-names:
> > + maxItems: 2
> > + items:
> > + - const: calib
> > + - const: temp_grade
> > +
> > + fsl,tempmon:
> > + $ref: '/schemas/types.yaml#/definitions/phandle'
> > + description: Phandle to the register map node.
>
> What register map? A bit ambiguous..
Temperature sensor registers, will add more detail in V3.
Anson
^ permalink raw reply
* Re: linux-next: build warning after merge of the aspeed tree
From: Joel Stanley @ 2020-05-20 7:56 UTC (permalink / raw)
To: Rob Herring, Arnd Bergmann
Cc: Stephen Rothwell, devicetree, Devicetree Compiler,
Linux Next Mailing List, Linux Kernel Mailing List,
Manikandan Elumalai, Andrew Jeffery, Vijay Khemka
In-Reply-To: <CAL_JsqJWXH4JMZgRQa9r_aPLW6Muz6BRtf_NmeqJv21Aefji1A@mail.gmail.com>
On Mon, 11 May 2020 at 15:19, Rob Herring <robh+dt@kernel.org> wrote:
>
> On Fri, May 8, 2020 at 1:40 AM Joel Stanley <joel@jms.id.au> wrote:
> >
> > On Wed, 6 May 2020 at 23:13, Joel Stanley <joel@jms.id.au> wrote:
> > >
> > > Hi Rob,
> > >
> > > On Wed, 6 May 2020 at 23:10, Stephen Rothwell <sfr@canb.auug.org.au> wrote:
> > > >
> > > > Hi all,
> > > >
> > > > After merging the aspeed tree, today's linux-next build (arm
> > > > multi_v7_defconfig) produced this warning:
> > >
> > > Thanks Stephen.
> > >
> > > > arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:126.11-130.4: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@80/ipmb1@10: I2C bus unit address format error, expected "40000010"
> > > > arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:128.3-30: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@80/ipmb1@10:reg: I2C address must be less than 10-bits, got "0x40000010"
> > > > arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:137.11-141.4: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@100/ipmb3@10: I2C bus unit address format error, expected "40000010"
> > > > arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:139.3-30: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@100/ipmb3@10:reg: I2C address must be less than 10-bits, got "0x40000010"
> > > > arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:148.11-152.4: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@180/ipmb5@10: I2C bus unit address format error, expected "40000010"
> > > > arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:150.3-30: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@180/ipmb5@10:reg: I2C address must be less than 10-bits, got "0x40000010"
> > > > arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:159.11-163.4: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@300/ipmb7@10: I2C bus unit address format error, expected "40000010"
> > > > arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:161.3-30: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@300/ipmb7@10:reg: I2C address must be less than 10-bits, got "0x40000010"
> > >
> > > These are IPMB nodes with the SLAVE_ADDRESS bit set:
> > >
> > > +&i2c5 {
> > > + //Host3 IPMB bus
> > > + status = "okay";
> > > + multi-master;
> > > + ipmb5@10 {
> > > + compatible = "ipmb-dev";
> > > + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
> > > + i2c-protocol;
> > > + };
> > >
> > > This is a correct entry, so dtc should not warn about it.
> >
> > I sent a patch for dtc here:
> > https://lore.kernel.org/lkml/20200508063904.60162-1-joel@jms.id.au/
>
> Patches for dtc need to be against upstream dtc. There's already a
> similar patch posted for it which I commented on and never saw a
> respin.
Can I suggest some instructions in scsripts/dtc explaining that you
don't take patches in the kernel tree for this code?
I've sent the patch so it applies to the dtc tree. It would be good to
see that change propagate over to -next as others have reported this
warning.
Cheers,
Joel
^ permalink raw reply
* Re: [PATCH v11 13/13] dt-bindings: Add media properties
From: Jacopo Mondi @ 2020-05-20 7:52 UTC (permalink / raw)
To: Hans Verkuil
Cc: open list:MEDIA INPUT INFRASTRUCTURE (V4L/DVB), libcamera-devel,
Mauro Carvalho Chehab, Sakari Ailus, Laurent Pinchart,
Rob Herring, tfiga, pavel, devicetree
In-Reply-To: <6a8add4e-c1f6-bd08-8928-3c8884eeda2c@xs4all.nl>
Hi Hans,
On Mon, May 11, 2020 at 09:27:57AM +0200, Hans Verkuil wrote:
> On 09/05/2020 11:04, Jacopo Mondi wrote:
> > Add a DT header file to contain definitions for standard media properties.
> >
> > The file is named after:
> > Documentation/devicetree/bindings/media/video-interfaces.txt
> > which contains the standard media properties definitions.
> >
> > Initially add three macros to define the supported 'orientation'
> > property values.
> >
> > Signed-off-by: Jacopo Mondi <jacopo@jmondi.org>
> > ---
> >
> > I currently don't have users in mainline for this, I understand this implies
> > this is probably not going to be accepted. At the same time we don't have a
> > common place for media-related definitions, which support properties defined in
> > video-interfaces.txt
> >
> > I leave it here at the end of the series for discussions, but I'm fine dropping
> > it from the series.
> >
> > Thanks
> > j
> >
> > ---
> > include/dt-bindings/media/video-interfaces.h | 15 +++++++++++++++
> > 1 file changed, 15 insertions(+)
> > create mode 100644 include/dt-bindings/media/video-interfaces.h
> >
> > diff --git a/include/dt-bindings/media/video-interfaces.h b/include/dt-bindings/media/video-interfaces.h
> > new file mode 100644
> > index 0000000000000..404c697d6bd6e
> > --- /dev/null
> > +++ b/include/dt-bindings/media/video-interfaces.h
> > @@ -0,0 +1,15 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * include/dt-bindings/media/video-interfaces.h
> > + *
> > + * Copyright (C) 2020 Jacopo Mondi <jacopo@jmondi.org>
> > + */
> > +
> > +#ifndef __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__
> > +#define __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__
> > +
> > +#define FRONT_CAMERA <0>
> > +#define BACK_CAMERA <1>
> > +#define EXTERNAL_CAMERA <2>
>
> Uh, shouldn't that be 0, 1 and 2 instead of <0>, <1> and <2> ?
I used that notation to be able to write
orientation = FRONT_CAMERA
in place of
orientation = <FRONT_CAMERA>
Do you think it's wrong ?
Thanks
j
>
> I'm skipping this patch for the PR.
>
> Regards,
>
> Hans
>
> > +
> > +#endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */
> > --
> > 2.26.1
> >
>
^ permalink raw reply
* RE: [PATCH] ARM: dts: imx: Make tempmon node as child of anatop node
From: Anson Huang @ 2020-05-20 7:46 UTC (permalink / raw)
To: Aisheng Dong, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: dl-linux-imx
In-Reply-To: <AM6PR04MB49663B517C218072B2845DBF80B60@AM6PR04MB4966.eurprd04.prod.outlook.com>
> Subject: RE: [PATCH] ARM: dts: imx: Make tempmon node as child of anatop
> node
>
> > From: Anson Huang <Anson.Huang@nxp.com>
> > Sent: Wednesday, May 20, 2020 2:30 PM
> >
> > i.MX6/7 SoCs' temperature sensor is inside anatop module from HW
> > perspective, so it should be a child node of anatop.
> >
> > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
>
> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
>
> BTW, I think you also need a binding doc for this change.
The binding doc is the imx-thermal.yaml I sent out, it is suggested by Rob
to move tempmon into anatop node, that is why I did this patch to align
with the binding doc.
Anson
^ permalink raw reply
* RE: [PATCH] ARM: dts: imx: Make tempmon node as child of anatop node
From: Aisheng Dong @ 2020-05-20 7:43 UTC (permalink / raw)
To: Anson Huang, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: dl-linux-imx
In-Reply-To: <1589956216-22499-1-git-send-email-Anson.Huang@nxp.com>
> From: Anson Huang <Anson.Huang@nxp.com>
> Sent: Wednesday, May 20, 2020 2:30 PM
>
> i.MX6/7 SoCs' temperature sensor is inside anatop module from HW perspective,
> so it should be a child node of anatop.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
BTW, I think you also need a binding doc for this change.
Regards
Aisheng
> ---
> arch/arm/boot/dts/imx6qdl.dtsi | 22 +++++++++++-----------
> arch/arm/boot/dts/imx6sl.dtsi | 20 ++++++++++----------
> arch/arm/boot/dts/imx6sll.dtsi | 20 ++++++++++----------
> arch/arm/boot/dts/imx6sx.dtsi | 20 ++++++++++----------
> arch/arm/boot/dts/imx6ul.dtsi | 20 ++++++++++----------
> arch/arm/boot/dts/imx7s.dtsi | 20 ++++++++++----------
> 6 files changed, 61 insertions(+), 61 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> index 39d4afd..43d44d5 100644
> --- a/arch/arm/boot/dts/imx6qdl.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> @@ -69,17 +69,6 @@
> };
> };
>
> - tempmon: tempmon {
> - compatible = "fsl,imx6q-tempmon";
> - interrupt-parent = <&gpc>;
> - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
> - fsl,tempmon = <&anatop>;
> - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
> - nvmem-cell-names = "calib", "temp_grade";
> - clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
> - #thermal-sensor-cells = <0>;
> - };
> -
> ldb: ldb {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -795,6 +784,17 @@
> anatop-min-voltage = <725000>;
> anatop-max-voltage = <1450000>;
> };
> +
> + tempmon: tempmon {
> + compatible = "fsl,imx6q-tempmon";
> + interrupt-parent = <&gpc>;
> + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
> + fsl,tempmon = <&anatop>;
> + nvmem-cells = <&tempmon_calib>,
> <&tempmon_temp_grade>;
> + nvmem-cell-names = "calib", "temp_grade";
> + clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
> + #thermal-sensor-cells = <0>;
> + };
> };
>
> usbphy1: usbphy@20c9000 {
> diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
> index 911d8cf..d8efc0a 100644
> --- a/arch/arm/boot/dts/imx6sl.dtsi
> +++ b/arch/arm/boot/dts/imx6sl.dtsi
> @@ -93,16 +93,6 @@
> };
> };
>
> - tempmon: tempmon {
> - compatible = "fsl,imx6q-tempmon";
> - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-parent = <&gpc>;
> - fsl,tempmon = <&anatop>;
> - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
> - nvmem-cell-names = "calib", "temp_grade";
> - clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
> - };
> -
> pmu {
> compatible = "arm,cortex-a9-pmu";
> interrupt-parent = <&gpc>;
> @@ -628,6 +618,16 @@
> anatop-min-voltage = <725000>;
> anatop-max-voltage = <1450000>;
> };
> +
> + tempmon: tempmon {
> + compatible = "fsl,imx6q-tempmon";
> + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gpc>;
> + fsl,tempmon = <&anatop>;
> + nvmem-cells = <&tempmon_calib>,
> <&tempmon_temp_grade>;
> + nvmem-cell-names = "calib", "temp_grade";
> + clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
> + };
> };
>
> usbphy1: usbphy@20c9000 {
> diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
> index edd3abb..bf7f048 100644
> --- a/arch/arm/boot/dts/imx6sll.dtsi
> +++ b/arch/arm/boot/dts/imx6sll.dtsi
> @@ -105,16 +105,6 @@
> clock-output-names = "ipp_di1";
> };
>
> - tempmon: temperature-sensor {
> - compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
> - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-parent = <&gpc>;
> - fsl,tempmon = <&anatop>;
> - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
> - nvmem-cell-names = "calib", "temp_grade";
> - clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
> - };
> -
> soc {
> #address-cells = <1>;
> #size-cells = <1>;
> @@ -531,6 +521,16 @@
> anatop-max-voltage = <3400000>;
> anatop-enable-bit = <0>;
> };
> +
> + tempmon: temperature-sensor {
> + compatible = "fsl,imx6sll-tempmon",
> "fsl,imx6sx-tempmon";
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gpc>;
> + fsl,tempmon = <&anatop>;
> + nvmem-cells = <&tempmon_calib>,
> <&tempmon_temp_grade>;
> + nvmem-cell-names = "calib", "temp_grade";
> + clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
> + };
> };
>
> usbphy1: usb-phy@20c9000 {
> diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
> index e031337..8c4473b 100644
> --- a/arch/arm/boot/dts/imx6sx.dtsi
> +++ b/arch/arm/boot/dts/imx6sx.dtsi
> @@ -134,16 +134,6 @@
> clock-output-names = "anaclk2";
> };
>
> - tempmon: tempmon {
> - compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
> - interrupt-parent = <&gpc>;
> - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> - fsl,tempmon = <&anatop>;
> - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
> - nvmem-cell-names = "calib", "temp_grade";
> - clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
> - };
> -
> pmu {
> compatible = "arm,cortex-a9-pmu";
> interrupt-parent = <&gpc>;
> @@ -696,6 +686,16 @@
> anatop-min-voltage = <725000>;
> anatop-max-voltage = <1450000>;
> };
> +
> + tempmon: tempmon {
> + compatible = "fsl,imx6sx-tempmon",
> "fsl,imx6q-tempmon";
> + interrupt-parent = <&gpc>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + fsl,tempmon = <&anatop>;
> + nvmem-cells = <&tempmon_calib>,
> <&tempmon_temp_grade>;
> + nvmem-cell-names = "calib", "temp_grade";
> + clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
> + };
> };
>
> usbphy1: usbphy@20c9000 {
> diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
> index 35e7301..505fd4f 100644
> --- a/arch/arm/boot/dts/imx6ul.dtsi
> +++ b/arch/arm/boot/dts/imx6ul.dtsi
> @@ -131,16 +131,6 @@
> clock-output-names = "ipp_di1";
> };
>
> - tempmon: tempmon {
> - compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
> - interrupt-parent = <&gpc>;
> - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> - fsl,tempmon = <&anatop>;
> - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
> - nvmem-cell-names = "calib", "temp_grade";
> - clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
> - };
> -
> pmu {
> compatible = "arm,cortex-a7-pmu";
> interrupt-parent = <&gpc>;
> @@ -611,6 +601,16 @@
> anatop-min-voltage = <725000>;
> anatop-max-voltage = <1450000>;
> };
> +
> + tempmon: tempmon {
> + compatible = "fsl,imx6ul-tempmon",
> "fsl,imx6sx-tempmon";
> + interrupt-parent = <&gpc>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + fsl,tempmon = <&anatop>;
> + nvmem-cells = <&tempmon_calib>,
> <&tempmon_temp_grade>;
> + nvmem-cell-names = "calib", "temp_grade";
> + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
> + };
> };
>
> usbphy1: usbphy@20c9000 {
> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index
> 8bac491..3904558 100644
> --- a/arch/arm/boot/dts/imx7s.dtsi
> +++ b/arch/arm/boot/dts/imx7s.dtsi
> @@ -147,16 +147,6 @@
> };
> };
>
> - tempmon: tempmon {
> - compatible = "fsl,imx7d-tempmon";
> - interrupt-parent = <&gpc>;
> - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> - fsl,tempmon = <&anatop>;
> - nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
> - nvmem-cell-names = "calib", "temp_grade";
> - clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
> - };
> -
> timer {
> compatible = "arm,armv7-timer";
> interrupt-parent = <&intc>;
> @@ -586,6 +576,16 @@
> anatop-max-voltage = <1300000>;
> anatop-enable-bit = <0>;
> };
> +
> + tempmon: tempmon {
> + compatible = "fsl,imx7d-tempmon";
> + interrupt-parent = <&gpc>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + fsl,tempmon = <&anatop>;
> + nvmem-cells = <&tempmon_calib>,
> <&fuse_grade>;
> + nvmem-cell-names = "calib", "temp_grade";
> + clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
> + };
> };
>
> snvs: snvs@30370000 {
> --
> 2.7.4
^ permalink raw reply
* RE: [PATCH V2] dt-bindings: thermal: Convert i.MX to json-schema
From: Aisheng Dong @ 2020-05-20 7:42 UTC (permalink / raw)
To: Anson Huang, rui.zhang@intel.com, daniel.lezcano@linaro.org,
amit.kucheria@verdurent.com, robh+dt@kernel.org,
shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: dl-linux-imx
In-Reply-To: <1589954560-10810-1-git-send-email-Anson.Huang@nxp.com>
> From: Anson Huang <Anson.Huang@nxp.com>
> Sent: Wednesday, May 20, 2020 2:03 PM
>
> Convert the i.MX thermal binding to DT schema format using json-schema
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> Changes since V1:
> - move tempmon node into its parent node anatop in example;
> - improve "fsl,tempmon" description.
> ---
> .../devicetree/bindings/thermal/imx-thermal.txt | 61 -------------
> .../devicetree/bindings/thermal/imx-thermal.yaml | 100
[...]
> +title: NXP i.MX Thermal Binding
> +
> +maintainers:
> + - Shawn Guo <shawn.guo@linaro.org>
> + - Anson Huang <Anson.Huang@nxp.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
Drop Unnecessary properties
> + - enum:
> + - fsl,imx6q-tempmon
> + - fsl,imx6sx-tempmon
> + - fsl,imx7d-tempmon
> +
> + interrupts:
> + description: |
> + The interrupt output of the controller, the IRQ will be triggered
> + when temperature is higher than high threshold.
> + maxItems: 1
You'd better explain why interrupts number is changed in the new binding compared to
the original one. Probably add in commit message if really needed.
> +
> + nvmem-cells:
> + description: |
> + Phandle to the calibration cells provided by ocotp for calibration
> + data and temperature grade.
Better describe for each of them as you did for clocks
> + maxItems: 2
> +
> + nvmem-cell-names:
> + maxItems: 2
> + items:
> + - const: calib
> + - const: temp_grade
> +
> + fsl,tempmon:
> + $ref: '/schemas/types.yaml#/definitions/phandle'
> + description: Phandle to the register map node.
What register map? A bit ambiguous..
Regards
Aisheng
> +
> + fsl,tempmon-data:
> + $ref: '/schemas/types.yaml#/definitions/phandle'
> + description: |
> + Deprecated property, phandle pointer to fuse controller that contains
> + TEMPMON calibration data, e.g. OCOTP on imx6q. The details about
> + calibration data can be found in SoC Reference Manual.
> + deprecated: true
> +
> + clocks:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - interrupts
> + - fsl,tempmon
> + - nvmem-cells
> + - nvmem-cell-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx6sx-clock.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + efuse@21bc000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,imx6sx-ocotp", "syscon";
> + reg = <0x021bc000 0x4000>;
> + clocks = <&clks IMX6SX_CLK_OCOTP>;
> +
> + tempmon_calib: calib@38 {
> + reg = <0x38 4>;
> + };
> +
> + tempmon_temp_grade: temp-grade@20 {
> + reg = <0x20 4>;
> + };
> + };
> +
> + anatop@20c8000 {
> + compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
> + reg = <0x020c8000 0x1000>;
> + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
> + <0 54 IRQ_TYPE_LEVEL_HIGH>,
> + <0 127 IRQ_TYPE_LEVEL_HIGH>;
> +
> + tempmon {
> + compatible = "fsl,imx6sx-tempmon";
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + fsl,tempmon = <&anatop>;
> + nvmem-cells = <&tempmon_calib>,
> <&tempmon_temp_grade>;
> + nvmem-cell-names = "calib", "temp_grade";
> + clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
> + };
> + };
> --
> 2.7.4
^ permalink raw reply
* Re: [PATCH V2 2/3] perf/imx_ddr: Add system PMU identifier for userspace
From: Will Deacon @ 2020-05-20 7:41 UTC (permalink / raw)
To: Joakim Zhang
Cc: john.garry, mark.rutland, robh+dt, shawnguo, linux-imx,
linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20200520025619.687-3-qiangqing.zhang@nxp.com>
On Wed, May 20, 2020 at 10:56:18AM +0800, Joakim Zhang wrote:
> The DDR Perf for i.MX8 is a system PMU whose axi id would different from
> SoC to SoC. Need expose system PMU identifier for userspace which refer
> to /sys/bus/event_source/devices/<PMU DEVICE>/identifier.
>
> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
> ---
> drivers/perf/fsl_imx8_ddr_perf.c | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
> index 90884d14f95f..ba523a94f4d7 100644
> --- a/drivers/perf/fsl_imx8_ddr_perf.c
> +++ b/drivers/perf/fsl_imx8_ddr_perf.c
> @@ -76,6 +76,7 @@ struct ddr_pmu {
> unsigned int cpu;
> struct hlist_node node;
> struct device *dev;
> + const char *identifier;
> struct perf_event *events[NUM_COUNTERS];
> int active_events;
> enum cpuhp_state cpuhp_state;
> @@ -84,6 +85,27 @@ struct ddr_pmu {
> int id;
> };
>
> +static ssize_t ddr_perf_identifier_show(struct device *dev,
> + struct device_attribute *attr,
> + char *page)
> +{
> + struct ddr_pmu *pmu = dev_get_drvdata(dev);
> +
> + return sprintf(page, "%s\n", pmu->identifier);
> +}
> +
> +static struct device_attribute ddr_perf_identifier_attr =
> + __ATTR(identifier, 0444, ddr_perf_identifier_show, NULL);
> +
> +static struct attribute *ddr_perf_identifier_attrs[] = {
> + &ddr_perf_identifier_attr.attr,
> + NULL,
> +};
> +
> +static struct attribute_group ddr_perf_identifier_attr_group = {
> + .attrs = ddr_perf_identifier_attrs,
> +};
> +
> enum ddr_perf_filter_capabilities {
> PERF_CAP_AXI_ID_FILTER = 0,
> PERF_CAP_AXI_ID_FILTER_ENHANCED,
> @@ -237,6 +259,7 @@ static const struct attribute_group *attr_groups[] = {
> &ddr_perf_format_attr_group,
> &ddr_perf_cpumask_attr_group,
> &ddr_perf_filter_cap_attr_group,
> + &ddr_perf_identifier_attr_group,
> NULL,
> };
>
> @@ -601,6 +624,7 @@ static int ddr_perf_probe(struct platform_device *pdev)
> struct ddr_pmu *pmu;
> struct device_node *np;
> void __iomem *base;
> + const char *identifier = NULL;
> char *name;
> int num;
> int ret;
> @@ -620,6 +644,11 @@ static int ddr_perf_probe(struct platform_device *pdev)
>
> platform_set_drvdata(pdev, pmu);
>
> + ret = of_property_read_string(np, "identifier", &identifier);
> + if (ret < 0)
> + dev_warn(&pdev->dev, "Failed to get identifier\n");
> + pmu->identifier = identifier;
I think this is exactly what Rob was objecting to when he said "yet another
way to identify the SoC from userspace". I've asked him on the other thread
as to what the best way to do this is.
Will
^ permalink raw reply
* [PATCH] dt-bindings: input: touchscreen: edt-ft5x06: change reg property
From: Johan Jonker @ 2020-05-20 7:33 UTC (permalink / raw)
To: heiko
Cc: robh+dt, dmitry.torokhov, linux-input, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
A test with the command below gives this error:
arch/arm/boot/dts/rk3188-bqedison2qc.dt.yaml:
touchscreen@3e: reg:0:0: 56 was expected
The touchscreen chip on 'rk3188-bqedison2qc' and other BQ models
was shipped with different addresses then the binding currently allows.
Change the reg property that any address will pass.
make ARCH=arm dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/input/touchscreen/
edt-ft5x06.yaml
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml
index 383d64a91..baa8e8f7e 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml
+++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml
@@ -42,7 +42,7 @@ properties:
- focaltech,ft6236
reg:
- const: 0x38
+ maxItems: 1
interrupts:
maxItems: 1
--
2.11.0
^ permalink raw reply related
* Re: [PATCH V1 RESEND 1/3] perf/imx_ddr: Add system PMU identifier for userspace
From: Will Deacon @ 2020-05-20 7:33 UTC (permalink / raw)
To: Rob Herring
Cc: Joakim Zhang, john.garry, mark.rutland, shawnguo, linux-imx,
linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20200519185125.GB453195@bogus>
On Tue, May 19, 2020 at 12:51:25PM -0600, Rob Herring wrote:
> On Tue, May 12, 2020 at 03:31:13PM +0800, Joakim Zhang wrote:
> > +static ssize_t ddr_perf_identifier_show(struct device *dev,
> > + struct device_attribute *attr,
> > + char *page)
> > +{
> > + struct ddr_pmu *pmu = dev_get_drvdata(dev);
> > +
> > + return sprintf(page, "%s\n", pmu->devtype_data->identifier);
>
> Why do we need yet another way to identify the SoC from userspace?
I also really dislike this. What's the preferred way to identify the SoC
from userspace? It's needed so that the perf userspace tool can describe
perf events that are supported for the PMU, as this isn't probe-able
directly from the hardware. We have the same issue with the SMMUv3 PMCG [1],
and so we need to solve the problem for both DT and ACPI.
Will
[1] https://lore.kernel.org/r/1587120634-19666-1-git-send-email-john.garry@huawei.com
^ permalink raw reply
* [PATCH v4 4/4] iio: magnetometer: ak8975: Add gpio reset support
From: Jonathan Albrieux @ 2020-05-20 7:31 UTC (permalink / raw)
To: linux-kernel
Cc: ~postmarketos/upstreaming, Jonathan Albrieux, Allison Randal,
Andy Shevchenko,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Greg Kroah-Hartman, Hartmut Knaack, Jilayne Lovejoy,
Jonathan Cameron, Kate Stewart, Lars-Peter Clausen, Linus Walleij,
open list:IIO SUBSYSTEM AND DRIVERS, Peter Meerwald-Stadler,
Thomas Gleixner, Jonathan Cameron
In-Reply-To: <20200520073125.30808-1-jonathan.albrieux@gmail.com>
According to AK09911 datasheet, if reset gpio is provided then
deassert reset on ak8975_power_on() and assert reset on ak8975_power_off().
Without reset's deassertion during ak8975_power_on(), driver's probe fails
on ak8975_who_i_am() while checking for device identity for AK09911 chip.
AK09911 has an active low reset gpio to handle register's reset.
AK09911 datasheet says that, if not used, reset pin should be connected
to VID. This patch emulates this situation.
Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
---
drivers/iio/magnetometer/ak8975.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/iio/magnetometer/ak8975.c b/drivers/iio/magnetometer/ak8975.c
index fd368455cd7b..a23422aad97d 100644
--- a/drivers/iio/magnetometer/ak8975.c
+++ b/drivers/iio/magnetometer/ak8975.c
@@ -358,6 +358,7 @@ struct ak8975_data {
u8 asa[3];
long raw_to_gauss[3];
struct gpio_desc *eoc_gpiod;
+ struct gpio_desc *reset_gpiod;
int eoc_irq;
wait_queue_head_t data_ready_queue;
unsigned long flags;
@@ -384,6 +385,9 @@ static int ak8975_power_on(const struct ak8975_data *data)
"Failed to enable specified Vid supply\n");
return ret;
}
+
+ gpiod_set_value_cansleep(data->reset_gpiod, 0);
+
/*
* According to the datasheet the power supply rise time is 200us
* and the minimum wait time before mode setting is 100us, in
@@ -396,6 +400,8 @@ static int ak8975_power_on(const struct ak8975_data *data)
/* Disable attached power regulator if any. */
static void ak8975_power_off(const struct ak8975_data *data)
{
+ gpiod_set_value_cansleep(data->reset_gpiod, 1);
+
regulator_disable(data->vid);
regulator_disable(data->vdd);
}
@@ -839,6 +845,7 @@ static int ak8975_probe(struct i2c_client *client,
struct ak8975_data *data;
struct iio_dev *indio_dev;
struct gpio_desc *eoc_gpiod;
+ struct gpio_desc *reset_gpiod;
const void *match;
unsigned int i;
int err;
@@ -856,6 +863,16 @@ static int ak8975_probe(struct i2c_client *client,
if (eoc_gpiod)
gpiod_set_consumer_name(eoc_gpiod, "ak_8975");
+ /*
+ * According to AK09911 datasheet, if reset GPIO is provided then
+ * deassert reset on ak8975_power_on() and assert reset on
+ * ak8975_power_off().
+ */
+ reset_gpiod = devm_gpiod_get_optional(&client->dev,
+ "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(reset_gpiod))
+ return PTR_ERR(reset_gpiod);
+
/* Register with IIO */
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (indio_dev == NULL)
@@ -866,6 +883,7 @@ static int ak8975_probe(struct i2c_client *client,
data->client = client;
data->eoc_gpiod = eoc_gpiod;
+ data->reset_gpiod = reset_gpiod;
data->eoc_irq = 0;
err = iio_read_mount_matrix(&client->dev, "mount-matrix", &data->orientation);
--
2.17.1
^ permalink raw reply related
* [PATCH v4 3/4] iio: magnetometer: ak8975: Fix typo, uniform measurement unit style
From: Jonathan Albrieux @ 2020-05-20 7:31 UTC (permalink / raw)
To: linux-kernel
Cc: ~postmarketos/upstreaming, Jonathan Albrieux, Allison Randal,
Andy Shevchenko,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Greg Kroah-Hartman, Hartmut Knaack, Jilayne Lovejoy,
Jonathan Cameron, Kate Stewart, Lars-Peter Clausen, Linus Walleij,
open list:IIO SUBSYSTEM AND DRIVERS, Peter Meerwald-Stadler,
Thomas Gleixner, Jonathan Cameron
In-Reply-To: <20200520073125.30808-1-jonathan.albrieux@gmail.com>
Minor comment style edits.
Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/iio/magnetometer/ak8975.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/magnetometer/ak8975.c b/drivers/iio/magnetometer/ak8975.c
index 3c881541ae72..fd368455cd7b 100644
--- a/drivers/iio/magnetometer/ak8975.c
+++ b/drivers/iio/magnetometer/ak8975.c
@@ -385,9 +385,9 @@ static int ak8975_power_on(const struct ak8975_data *data)
return ret;
}
/*
- * According to the datasheet the power supply rise time i 200us
+ * According to the datasheet the power supply rise time is 200us
* and the minimum wait time before mode setting is 100us, in
- * total 300 us. Add some margin and say minimum 500us here.
+ * total 300us. Add some margin and say minimum 500us here.
*/
usleep_range(500, 1000);
return 0;
--
2.17.1
^ permalink raw reply related
* [PATCH v4 2/4] dt-bindings: iio: magnetometer: ak8975: add gpio reset support
From: Jonathan Albrieux @ 2020-05-20 7:31 UTC (permalink / raw)
To: linux-kernel
Cc: ~postmarketos/upstreaming, Jonathan Albrieux, Allison Randal,
Andy Shevchenko,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Greg Kroah-Hartman, Hartmut Knaack, Jilayne Lovejoy,
Jonathan Cameron, Kate Stewart, Lars-Peter Clausen, Linus Walleij,
open list:IIO SUBSYSTEM AND DRIVERS, Peter Meerwald-Stadler,
Thomas Gleixner, Jonathan Cameron, Rob Herring
In-Reply-To: <20200520073125.30808-1-jonathan.albrieux@gmail.com>
Add reset-gpio support.
Without reset's deassertion during ak8975_power_on(), driver's probe fails
on ak8975_who_i_am() while checking for device identity for AK09911 chip.
AK09911 has an active low reset gpio to handle register's reset.
AK09911 datasheet says that, if not used, reset pin should be connected
to VID. This patch emulates this situation.
Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
---
.../devicetree/bindings/iio/magnetometer/ak8975.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/iio/magnetometer/ak8975.yaml b/Documentation/devicetree/bindings/iio/magnetometer/ak8975.yaml
index 9d5b1e6908d1..d83f7e212658 100644
--- a/Documentation/devicetree/bindings/iio/magnetometer/ak8975.yaml
+++ b/Documentation/devicetree/bindings/iio/magnetometer/ak8975.yaml
@@ -41,6 +41,11 @@ properties:
mount-matrix:
description: an optional 3x3 mounting rotation matrix
+ reset-gpio:
+ description: |
+ an optional pin needed for AK09911 to set the reset state. This should
+ be usually active low
+
required:
- compatible
- reg
@@ -58,6 +63,7 @@ examples:
reg = <0x0c>;
gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>;
vdd-supply = <&ldo_3v3_gnss>;
+ reset-gpio = <&msmgpio 111 GPIO_ACTIVE_LOW>;
mount-matrix = "-0.984807753012208", /* x0 */
"0", /* y0 */
"-0.173648177666930", /* z0 */
--
2.17.1
^ permalink raw reply related
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