* Re: [PATCH v25 03/16] dt: bindings: lp50xx: Introduce the lp50xx family of RGB drivers
From: Rob Herring @ 2020-05-27 1:59 UTC (permalink / raw)
To: Dan Murphy; +Cc: jacek.anaszewski, pavel, devicetree, linux-leds, linux-kernel
In-Reply-To: <20200526164652.2331-4-dmurphy@ti.com>
On Tue, May 26, 2020 at 11:46:39AM -0500, Dan Murphy wrote:
> Introduce the bindings for the Texas Instruments LP5036, LP5030, LP5024,
> LP5018, LP5012 and LP5009 RGB LED device driver. The LP5036/30/24/18/12/9
> can control RGB LEDs individually or as part of a control bank group.
> These devices have the ability to adjust the mixing control for the RGB
> LEDs to obtain different colors independent of the overall brightness of
> the LED grouping.
>
> Datasheet:
> http://www.ti.com/lit/ds/symlink/lp5012.pdf
> http://www.ti.com/lit/ds/symlink/lp5024.pdf
> http://www.ti.com/lit/ds/symlink/lp5036.pdf
>
> Acked-by: Jacek Anaszewski <jacek.anaszewski@gmail.com>
> Signed-off-by: Dan Murphy <dmurphy@ti.com>
> ---
> .../devicetree/bindings/leds/leds-lp50xx.yaml | 180 ++++++++++++++++++
> 1 file changed, 180 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/leds/leds-lp50xx.yaml
>
> diff --git a/Documentation/devicetree/bindings/leds/leds-lp50xx.yaml b/Documentation/devicetree/bindings/leds/leds-lp50xx.yaml
> new file mode 100644
> index 000000000000..a2ea03e07f6d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/leds/leds-lp50xx.yaml
> @@ -0,0 +1,180 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/leds/leds-lp50xx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: LED driver for LP50XX RGB LED from Texas Instruments.
> +
> +maintainers:
> + - Dan Murphy <dmurphy@ti.com>
> +
> +description: |
> + The LP50XX is multi-channel, I2C RGB LED Drivers that can group RGB LEDs into
> + a LED group or control them individually.
> +
> + The difference in these RGB LED drivers is the number of supported RGB
> + modules.
> +
> + For more product information please see the link below:
> + http://www.ti.com/lit/ds/symlink/lp5012.pdf
> + http://www.ti.com/lit/ds/symlink/lp5024.pdf
> + http://www.ti.com/lit/ds/symlink/lp5036.pdf
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: ti,lp5009
> + - const: ti,lp5012
> + - const: ti,lp5018
> + - const: ti,lp5024
> + - const: ti,lp5030
> + - const: ti,lp5036
Use enum rather than oneOf+const.
> +
> + reg:
> + maxItems: 1
> + description:
> + I2C slave address
> + lp5009/12 - 0x14, 0x15, 0x16, 0x17
> + lp5018/24 - 0x28, 0x29, 0x2a, 0x2b
> + lp5030/36 - 0x30, 0x31, 0x32, 0x33
> +
> + enable-gpios:
> + description: GPIO pin to enable/disable the device.
How many? (maxItems: 1)
> +
> + vled-supply:
> + description: LED supply.
> +
> + child-node:
This literally requires a node called 'child-node'. Not what you want.
You need a $ref to the multi-color schema in here and then only define
what's specific to this chip.
> + type: object
> + properties:
> + reg:
> + description: This is the LED module number.
Constraints?
> +
> + color:
> + description: Must be LED_COLOR_ID_MULTI
> +
> + function:
> + description: see Documentation/devicetree/bindings/leds/common.txt
> +
> + ti,led-bank:
> + description:
> + This property denotes the LED module numbers that will be controlled as
> + a single RGB cluster. Each LED module number will be controlled by a
> + single LED class instance.
> + There can only be one instance of the ti,led-bank
> + property for each device node. This is a required node is the LED
> + modules are to be backed.
> + $ref: /schemas/types.yaml#definitions/uint32-array
What is reg then? Some made up index? Can't you do:
reg = <1 2 3>;
led@1 {};
led@2 {};
led@2 {};
> +
> + required:
> + - reg
> + - color
> + - function
> +
> + grandchild-node:
Again, no.
> + type: object
> + properties:
> + reg:
> + description:
> + A single entry denoting the LED output that controls the monochrome LED.
Constraints?
> +
> + color:
> + description:
> + see Documentation/devicetree/bindings/leds/common.txt
Have you read this file recently? Don't add new references to it. (And
generally freeform references to other files are wrong with schemas).
> +
> + led-sources:
> + description:
> + see Documentation/devicetree/bindings/leds/common.txt
> + The LED outputs associated with the LED modules are defined in Table 1
> + of the corresponding data sheets.
> + LP5009 - 3 Total RGB cluster LED outputs 0-2
> + LP5012 - 4 Total RGB cluster LED outputs 0-3
> + LP5018 - 6 Total RGB cluster LED outputs 0-5
> + LP5024 - 8 Total RGB cluster LED outputs 0-7
> + LP5030 - 10 Total RGB cluster LED outputs 0-9
> + LP5036 - 12 Total RGB cluster LED outputs 0-11
> +
> + label:
> + description: |
> + Optional node - see Documentation/devicetree/bindings/leds/common.txt
> +
> + linux,default-trigger:
> + description: |
> + Optional node - see Documentation/devicetree/bindings/leds/common.txt
> +
> + required:
> + - reg
> + - color
> +
> +required:
> + - compatible
> + - reg
> +
> +examples:
> + - |
> + #include <dt-bindings/gpio/gpio.h>
> + #include <dt-bindings/leds/common.h>
> + i2c {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + led-controller@14 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "ti,lp5009";
> + reg = <0x14>;
> + enable-gpios = <&gpio1 16>;
> + multi-led@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + color = <LED_COLOR_ID_MULTI>;
> + function = LED_FUNCTION_CHARGING;
> +
> + led@0 {
> + reg = <0>;
> + color = <LED_COLOR_ID_RED>;
> + };
> +
> + led@1 {
> + reg = <1>;
> + color = <LED_COLOR_ID_GREEN>;
> + };
> +
> + led@2 {
> + reg = <2>;
> + color = <LED_COLOR_ID_BLUE>;
> + };
> + };
> +
> + multi-led@2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + color = <LED_COLOR_ID_MULTI>;
> + function = LED_FUNCTION_STANDBY;
> + ti,led-bank = <2 3 5>;
> +
> + led@6 {
> + reg = <0x6>;
> + color = <LED_COLOR_ID_RED>;
> + led-sources = <6 9 15>;
> + };
> +
> + led@7 {
> + reg = <0x7>;
> + color = <LED_COLOR_ID_GREEN>;
> + led-sources = <7 10 16>;
> + };
> +
> + led@8 {
> + reg = <0x8>;
> + color = <LED_COLOR_ID_BLUE>;
> + led-sources = <8 11 17>;
> + };
> + };
> + };
> + };
> +
> +...
> --
> 2.25.1
>
^ permalink raw reply
* Re: [PATCH v25 05/16] dt: bindings: lp55xx: Be consistent in the document with LED acronym
From: Rob Herring @ 2020-05-27 1:59 UTC (permalink / raw)
To: Dan Murphy; +Cc: pavel, linux-kernel, jacek.anaszewski, linux-leds, devicetree
In-Reply-To: <20200526164652.2331-6-dmurphy@ti.com>
On Tue, 26 May 2020 11:46:41 -0500, Dan Murphy wrote:
> Update the document to be consistent in case when using "LED".
> This acronym should be capital throughout the document.
>
> Acked-by: Pavel Machek <pavel@ucw.cz>
> Acked-by: Jacek Anaszewski <jacek.anaszewski@gmail.com>
> Signed-off-by: Dan Murphy <dmurphy@ti.com>
> ---
> Documentation/devicetree/bindings/leds/leds-lp55xx.txt | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v25 06/16] dt: bindings: lp55xx: Update binding for Multicolor Framework
From: Rob Herring @ 2020-05-27 2:01 UTC (permalink / raw)
To: Dan Murphy
Cc: jacek.anaszewski, pavel, devicetree, linux-leds, linux-kernel,
Linus Walleij, Tony Lindgren, Benoît Cousson, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team
In-Reply-To: <20200526164652.2331-7-dmurphy@ti.com>
On Tue, May 26, 2020 at 11:46:42AM -0500, Dan Murphy wrote:
> Update the DT binding to include the properties to use the
> multicolor framework for the devices that use the LP55xx
> framework.
>
> Acked-by: Jacek Anaszewski <jacek.anaszewski@gmail.com>
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
> Signed-off-by: Dan Murphy <dmurphy@ti.com>
> CC: Tony Lindgren <tony@atomide.com>
> CC: "Benoît Cousson" <bcousson@baylibre.com>
> CC: Linus Walleij <linus.walleij@linaro.org>
> CC: Shawn Guo <shawnguo@kernel.org>
> CC: Sascha Hauer <s.hauer@pengutronix.de>
> CC: Pengutronix Kernel Team <kernel@pengutronix.de>
> CC: Fabio Estevam <festevam@gmail.com>
> CC: NXP Linux Team <linux-imx@nxp.com>
> ---
> .../devicetree/bindings/leds/leds-lp55xx.txt | 149 +++++++++++++++---
> 1 file changed, 124 insertions(+), 25 deletions(-)
Convert this to schema first because it's going to need to reference
the multi-color schema.
Rob
^ permalink raw reply
* Re: [PATCH v8 2/2] clk: intel: Add CGU clock driver for a new SoC
From: Stephen Boyd @ 2020-05-27 2:10 UTC (permalink / raw)
To: Rahul Tanwar, linux-clk, mturquette
Cc: robh, mark.rutland, linux-kernel, devicetree, andriy.shevchenko,
qi-ming.wu, yixin.zhu, cheol.yong.kim, rtanwar, Rahul Tanwar
In-Reply-To: <42a4f71847714df482bacffdcd84341a4052800b.1587102634.git.rahul.tanwar@linux.intel.com>
Quoting Rahul Tanwar (2020-04-16 22:54:47)
> From: rtanwar <rahul.tanwar@intel.com>
>
> Clock Generation Unit(CGU) is a new clock controller IP of a forthcoming
> Intel network processor SoC named Lightning Mountain(LGM). It provides
> programming interfaces to control & configure all CPU & peripheral clocks.
> Add common clock framework based clock controller driver for CGU.
>
> Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
> ---
Applied to clk-next
^ permalink raw reply
* Re: [PATCH v8 2/2] clk: intel: Add CGU clock driver for a new SoC
From: Stephen Boyd @ 2020-05-27 2:10 UTC (permalink / raw)
To: Rahul Tanwar, linux-clk, mturquette
Cc: robh, mark.rutland, linux-kernel, devicetree, andriy.shevchenko,
qi-ming.wu, yixin.zhu, cheol.yong.kim, rtanwar, Rahul Tanwar
In-Reply-To: <42a4f71847714df482bacffdcd84341a4052800b.1587102634.git.rahul.tanwar@linux.intel.com>
Quoting Rahul Tanwar (2020-04-16 22:54:47)
> diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c
> new file mode 100644
> index 000000000000..802a7fa88535
> --- /dev/null
> +++ b/drivers/clk/x86/clk-cgu.c
> @@ -0,0 +1,636 @@
[...]
> +
> +static unsigned long
> +lgm_clk_ddiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw);
> + unsigned int div0, div1, exdiv;
> + unsigned long flags;
> + u64 prate;
> +
> + spin_lock_irqsave(&ddiv->lock, flags);
Is there any reason to take the lock here? We should be able to
calculate the new rate and not care what the values are "right now"
because they can change in the interim. Instead we should recalculate a
rate that is possible regardless of the current state of the clk.
> + div0 = lgm_get_clk_val(ddiv->membase, ddiv->reg,
> + ddiv->shift0, ddiv->width0) + 1;
> + div1 = lgm_get_clk_val(ddiv->membase, ddiv->reg,
> + ddiv->shift1, ddiv->width1) + 1;
> + exdiv = lgm_get_clk_val(ddiv->membase, ddiv->reg,
> + ddiv->shift2, ddiv->width2);
> + spin_unlock_irqrestore(&ddiv->lock, flags);
> +
> + prate = (u64)parent_rate;
> + do_div(prate, div0);
> + do_div(prate, div1);
> +
> + if (exdiv) {
> + do_div(prate, ddiv->div);
> + prate *= ddiv->mult;
> + }
> +
> + return prate;
> +}
[...]
> +
> +static long
> +lgm_clk_ddiv_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *prate)
> +{
> + struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw);
> + u32 div, ddiv1, ddiv2;
> + unsigned long flags;
> + u64 rate64 = rate;
> +
> + div = DIV_ROUND_CLOSEST_ULL((u64)*prate, rate);
> +
> + /* if predivide bit is enabled, modify div by factor of 2.5 */
> + spin_lock_irqsave(&ddiv->lock, flags);
> + if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) {
> + div = div * 2;
> + div = DIV_ROUND_CLOSEST_ULL((u64)div, 5);
> + }
> +
> + if (div <= 0) {
> + spin_unlock_irqrestore(&ddiv->lock, flags);
> + return *prate;
> + }
> +
> + if (lgm_clk_get_ddiv_val(div, &ddiv1, &ddiv2) != 0) {
> + if (lgm_clk_get_ddiv_val(div + 1, &ddiv1, &ddiv2) != 0) {
> + spin_unlock_irqrestore(&ddiv->lock, flags);
> + return -EINVAL;
> + }
> + }
> +
> + rate64 = *prate;
> + do_div(rate64, ddiv1);
> + do_div(rate64, ddiv2);
> +
> + /* if predivide bit is enabled, modify rounded rate by factor of 2.5 */
> + if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) {
> + rate64 = rate64 * 2;
> + rate64 = DIV_ROUND_CLOSEST_ULL(rate64, 5);
> + }
> + spin_unlock_irqrestore(&ddiv->lock, flags);
There's a lot of locking in here that can probably be tightened up.
Please look into only holding the spinlock as long as you need to.
> +
> + return rate64;
> +}
> +
> +static const struct clk_ops lgm_clk_ddiv_ops = {
> + .recalc_rate = lgm_clk_ddiv_recalc_rate,
> + .enable = lgm_clk_ddiv_enable,
> + .disable = lgm_clk_ddiv_disable,
> + .set_rate = lgm_clk_ddiv_set_rate,
> + .round_rate = lgm_clk_ddiv_round_rate,
> +};
> +
> +int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
> + const struct lgm_clk_ddiv_data *list,
> + unsigned int nr_clk)
> +{
> + struct device *dev = ctx->dev;
> + struct clk_init_data init = {};
> + struct lgm_clk_ddiv *ddiv;
> + struct clk_hw *hw;
> + unsigned int idx;
> + int ret;
> +
> + for (idx = 0; idx < nr_clk; idx++, list++) {
> + ddiv = NULL;
Why assign to NULL?
> + ddiv = devm_kzalloc(dev, sizeof(*ddiv), GFP_KERNEL);
And then assign to it?
> + if (!ddiv)
> + return -ENOMEM;
> +
> + memset(&init, 0, sizeof(init));
Maybe 'init' and 'ddiv' should declared inside the for loop so that
they're automatically allocated again each time through the loop. Then
it would avoid the memset call and we wouldn't worry about 'ddiv'
needing to be NULL?
> + init.name = list->name;
> + init.ops = &lgm_clk_ddiv_ops;
> + init.flags = list->flags;
> + init.parent_data = list->parent_data;
> + init.num_parents = 1;
> +
> + ddiv->membase = ctx->membase;
> + ddiv->lock = ctx->lock;
> + ddiv->reg = list->reg;
> + ddiv->shift0 = list->shift0;
> + ddiv->width0 = list->width0;
> + ddiv->shift1 = list->shift1;
> + ddiv->width1 = list->width1;
> + ddiv->shift_gate = list->shift_gate;
> + ddiv->width_gate = list->width_gate;
> + ddiv->shift2 = list->ex_shift;
> + ddiv->width2 = list->ex_width;
> + ddiv->flags = list->div_flags;
> + ddiv->mult = 2;
> + ddiv->div = 5;
> + ddiv->hw.init = &init;
> +
> + hw = &ddiv->hw;
> + ret = clk_hw_register(dev, hw);
> + if (ret) {
> + dev_err(dev, "register clk: %s failed!\n", list->name);
> + return ret;
> + }
> + ctx->clk_data.hws[list->id] = hw;
> + }
> +
> + return 0;
> +}
> diff --git a/drivers/clk/x86/clk-cgu.h b/drivers/clk/x86/clk-cgu.h
> new file mode 100644
> index 000000000000..4e22bfb22312
> --- /dev/null
> +++ b/drivers/clk/x86/clk-cgu.h
> @@ -0,0 +1,335 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + * Zhu YiXin <yixin.zhu@intel.com>
> + * Rahul Tanwar <rahul.tanwar@intel.com>
> + */
> +
> +#ifndef __CLK_CGU_H
> +#define __CLK_CGU_H
> +
> +#include <linux/io.h>
> +
> +struct lgm_clk_mux {
> + struct clk_hw hw;
> + void __iomem *membase;
> + unsigned int reg;
> + u8 shift;
> + u8 width;
> + unsigned long flags;
> + spinlock_t lock;
> +};
> +
> +struct lgm_clk_divider {
> + struct clk_hw hw;
> + void __iomem *membase;
> + unsigned int reg;
> + u8 shift;
> + u8 width;
> + u8 shift_gate;
> + u8 width_gate;
> + unsigned long flags;
> + const struct clk_div_table *table;
> + spinlock_t lock;
> +};
> +
> +struct lgm_clk_ddiv {
> + struct clk_hw hw;
> + void __iomem *membase;
> + unsigned int reg;
> + u8 shift0;
> + u8 width0;
> + u8 shift1;
> + u8 width1;
> + u8 shift2;
> + u8 width2;
> + u8 shift_gate;
> + u8 width_gate;
> + unsigned int mult;
> + unsigned int div;
> + unsigned long flags;
> + spinlock_t lock;
> +};
> +
> +struct lgm_clk_gate {
> + struct clk_hw hw;
> + void __iomem *membase;
> + unsigned int reg;
> + u8 shift;
> + unsigned long flags;
> + spinlock_t lock;
> +};
> +
> +enum lgm_clk_type {
> + CLK_TYPE_FIXED,
> + CLK_TYPE_MUX,
> + CLK_TYPE_DIVIDER,
> + CLK_TYPE_FIXED_FACTOR,
> + CLK_TYPE_GATE,
> + CLK_TYPE_NONE,
> +};
> +
> +/**
> + * struct lgm_clk_provider
> + * @membase: IO mem base address for CGU.
> + * @np: device node
> + * @dev: device
> + * @clk_data: array of hw clocks and clk number.
> + */
> +struct lgm_clk_provider {
> + void __iomem *membase;
> + struct device_node *np;
> + struct device *dev;
> + struct clk_hw_onecell_data clk_data;
> + spinlock_t lock;
> +};
> +
> +enum pll_type {
> + TYPE_ROPLL,
> + TYPE_LJPLL,
> + TYPE_NONE,
> +};
> +
> +struct lgm_clk_pll {
> + struct clk_hw hw;
> + void __iomem *membase;
> + unsigned int reg;
> + unsigned long flags;
> + enum pll_type type;
> + spinlock_t lock;
> +};
> +
> +/**
> + * struct lgm_pll_clk_data
> + * @id: platform specific id of the clock.
> + * @name: name of this pll clock.
> + * @parent_data: parent clock data.
> + * @num_parents: number of parents.
> + * @flags: optional flags for basic clock.
> + * @type: platform type of pll.
> + * @reg: offset of the register.
> + */
> +struct lgm_pll_clk_data {
> + unsigned int id;
> + const char *name;
> + const struct clk_parent_data *parent_data;
> + u8 num_parents;
> + unsigned long flags;
> + enum pll_type type;
> + int reg;
> +};
> +
> +#define LGM_PLL(_id, _name, _pdata, _flags, \
> + _reg, _type) \
> + { \
> + .id = _id, \
> + .name = _name, \
> + .parent_data = _pdata, \
> + .num_parents = ARRAY_SIZE(_pdata), \
> + .flags = _flags, \
> + .reg = _reg, \
> + .type = _type, \
> + }
> +
> +struct lgm_clk_ddiv_data {
> + unsigned int id;
> + const char *name;
> + const struct clk_parent_data *parent_data;
> + u8 flags;
> + unsigned long div_flags;
> + unsigned int reg;
> + u8 shift0;
> + u8 width0;
> + u8 shift1;
> + u8 width1;
> + u8 shift_gate;
> + u8 width_gate;
> + u8 ex_shift;
> + u8 ex_width;
> +};
> +
> +#define LGM_DDIV(_id, _name, _pname, _flags, _reg, \
> + _shft0, _wdth0, _shft1, _wdth1, \
> + _shft_gate, _wdth_gate, _xshft, _df) \
> + { \
> + .id = _id, \
> + .name = _name, \
> + .parent_data = &(const struct clk_parent_data){ \
> + .fw_name = _pname, \
> + .name = _pname, \
> + }, \
> + .flags = _flags, \
> + .reg = _reg, \
> + .shift0 = _shft0, \
> + .width0 = _wdth0, \
> + .shift1 = _shft1, \
> + .width1 = _wdth1, \
> + .shift_gate = _shft_gate, \
> + .width_gate = _wdth_gate, \
> + .ex_shift = _xshft, \
> + .ex_width = 1, \
> + .div_flags = _df, \
> + }
> +
> +struct lgm_clk_branch {
> + unsigned int id;
> + enum lgm_clk_type type;
> + const char *name;
> + const struct clk_parent_data *parent_data;
> + u8 num_parents;
> + unsigned long flags;
> + unsigned int mux_off;
> + u8 mux_shift;
> + u8 mux_width;
> + unsigned long mux_flags;
> + unsigned int mux_val;
> + unsigned int div_off;
> + u8 div_shift;
> + u8 div_width;
> + u8 div_shift_gate;
> + u8 div_width_gate;
> + unsigned long div_flags;
> + unsigned int div_val;
> + const struct clk_div_table *div_table;
> + unsigned int gate_off;
> + u8 gate_shift;
> + unsigned long gate_flags;
> + unsigned int gate_val;
> + unsigned int mult;
> + unsigned int div;
> +};
> +
> +/* clock flags definition */
> +#define CLOCK_FLAG_VAL_INIT BIT(16)
> +#define MUX_CLK_SW BIT(17)
> +
> +#define LGM_MUX(_id, _name, _pdata, _f, _reg, \
> + _shift, _width, _cf, _v) \
> + { \
> + .id = _id, \
> + .type = CLK_TYPE_MUX, \
> + .name = _name, \
> + .parent_data = _pdata, \
> + .num_parents = ARRAY_SIZE(_pdata), \
> + .flags = _f, \
> + .mux_off = _reg, \
> + .mux_shift = _shift, \
> + .mux_width = _width, \
> + .mux_flags = _cf, \
> + .mux_val = _v, \
> + }
> +
> +#define LGM_DIV(_id, _name, _pname, _f, _reg, _shift, _width, \
> + _shift_gate, _width_gate, _cf, _v, _dtable) \
> + { \
> + .id = _id, \
> + .type = CLK_TYPE_DIVIDER, \
> + .name = _name, \
> + .parent_data = &(const struct clk_parent_data){ \
> + .fw_name = _pname, \
> + .name = _pname, \
> + }, \
> + .num_parents = 1, \
> + .flags = _f, \
> + .div_off = _reg, \
> + .div_shift = _shift, \
> + .div_width = _width, \
> + .div_shift_gate = _shift_gate, \
> + .div_width_gate = _width_gate, \
> + .div_flags = _cf, \
> + .div_val = _v, \
> + .div_table = _dtable, \
> + }
> +
> +#define LGM_GATE(_id, _name, _pname, _f, _reg, \
> + _shift, _cf, _v) \
> + { \
> + .id = _id, \
> + .type = CLK_TYPE_GATE, \
> + .name = _name, \
> + .parent_data = &(const struct clk_parent_data){ \
> + .fw_name = _pname, \
> + .name = _pname, \
> + }, \
> + .num_parents = !_pname ? 0 : 1, \
> + .flags = _f, \
> + .gate_off = _reg, \
> + .gate_shift = _shift, \
> + .gate_flags = _cf, \
> + .gate_val = _v, \
> + }
> +
> +#define LGM_FIXED(_id, _name, _pname, _f, _reg, \
> + _shift, _width, _cf, _freq, _v) \
> + { \
> + .id = _id, \
> + .type = CLK_TYPE_FIXED, \
> + .name = _name, \
> + .parent_data = &(const struct clk_parent_data){ \
> + .fw_name = _pname, \
> + .name = _pname, \
> + }, \
> + .num_parents = !_pname ? 0 : 1, \
> + .flags = _f, \
> + .div_off = _reg, \
> + .div_shift = _shift, \
> + .div_width = _width, \
> + .div_flags = _cf, \
> + .div_val = _v, \
> + .mux_flags = _freq, \
> + }
> +
> +#define LGM_FIXED_FACTOR(_id, _name, _pname, _f, _reg, \
> + _shift, _width, _cf, _v, _m, _d) \
> + { \
> + .id = _id, \
> + .type = CLK_TYPE_FIXED_FACTOR, \
> + .name = _name, \
> + .parent_data = &(const struct clk_parent_data){ \
> + .fw_name = _pname, \
> + .name = _pname, \
> + }, \
> + .num_parents = 1, \
> + .flags = _f, \
> + .div_off = _reg, \
> + .div_shift = _shift, \
> + .div_width = _width, \
> + .div_flags = _cf, \
> + .div_val = _v, \
> + .mult = _m, \
> + .div = _d, \
> + }
> +
> +static inline void lgm_set_clk_val(void __iomem *membase, u32 reg,
> + u8 shift, u8 width, u32 set_val)
> +{
> + u32 mask = (GENMASK(width - 1, 0) << shift);
> + u32 regval;
> +
> + regval = readl(membase + reg);
> + regval = (regval & ~mask) | ((set_val << shift) & mask);
> + writel(regval, membase + reg);
> +}
> +
> +static inline u32 lgm_get_clk_val(void __iomem *membase, u32 reg,
> + u8 shift, u8 width)
> +{
> + u32 mask = (GENMASK(width - 1, 0) << shift);
> + u32 val;
> +
> + val = readl(membase + reg);
> + val = (val & mask) >> shift;
> +
> + return val;
> +}
> +
> +int lgm_clk_register_branches(struct lgm_clk_provider *ctx,
> + const struct lgm_clk_branch *list,
> + unsigned int nr_clk);
> +int lgm_clk_register_plls(struct lgm_clk_provider *ctx,
> + const struct lgm_pll_clk_data *list,
> + unsigned int nr_clk);
> +int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
> + const struct lgm_clk_ddiv_data *list,
> + unsigned int nr_clk);
> +#endif /* __CLK_CGU_H */
> diff --git a/drivers/clk/x86/clk-lgm.c b/drivers/clk/x86/clk-lgm.c
> new file mode 100644
> index 000000000000..ffbd2c425dc3
> --- /dev/null
> +++ b/drivers/clk/x86/clk-lgm.c
> @@ -0,0 +1,492 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Intel Corporation.
> + * Zhu YiXin <yixin.zhu@intel.com>
> + * Rahul Tanwar <rahul.tanwar@intel.com>
> + */
> +#include <linux/clk-provider.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/intel,lgm-clk.h>
> +#include "clk-cgu.h"
> +
> +#define PLL_DIV_WIDTH 4
> +#define PLL_DDIV_WIDTH 3
> +
> +/* Gate0 clock shift */
> +#define G_C55_SHIFT 7
> +#define G_QSPI_SHIFT 9
> +#define G_EIP197_SHIFT 11
> +#define G_VAULT130_SHIFT 12
> +#define G_TOE_SHIFT 13
> +#define G_SDXC_SHIFT 14
> +#define G_EMMC_SHIFT 15
> +#define G_SPIDBG_SHIFT 17
> +#define G_DMA3_SHIFT 28
> +
> +/* Gate1 clock shift */
> +#define G_DMA0_SHIFT 0
> +#define G_LEDC0_SHIFT 1
> +#define G_LEDC1_SHIFT 2
> +#define G_I2S0_SHIFT 3
> +#define G_I2S1_SHIFT 4
> +#define G_EBU_SHIFT 5
> +#define G_PWM_SHIFT 6
> +#define G_I2C0_SHIFT 7
> +#define G_I2C1_SHIFT 8
> +#define G_I2C2_SHIFT 9
> +#define G_I2C3_SHIFT 10
> +
> +#define G_SSC0_SHIFT 12
> +#define G_SSC1_SHIFT 13
> +#define G_SSC2_SHIFT 14
> +#define G_SSC3_SHIFT 15
> +
> +#define G_GPTC0_SHIFT 17
> +#define G_GPTC1_SHIFT 18
> +#define G_GPTC2_SHIFT 19
> +#define G_GPTC3_SHIFT 20
> +
> +#define G_ASC0_SHIFT 22
> +#define G_ASC1_SHIFT 23
> +#define G_ASC2_SHIFT 24
> +#define G_ASC3_SHIFT 25
> +
> +#define G_PCM0_SHIFT 27
> +#define G_PCM1_SHIFT 28
> +#define G_PCM2_SHIFT 29
> +
> +/* Gate2 clock shift */
> +#define G_PCIE10_SHIFT 1
> +#define G_PCIE11_SHIFT 2
> +#define G_PCIE30_SHIFT 3
> +#define G_PCIE31_SHIFT 4
> +#define G_PCIE20_SHIFT 5
> +#define G_PCIE21_SHIFT 6
> +#define G_PCIE40_SHIFT 7
> +#define G_PCIE41_SHIFT 8
> +
> +#define G_XPCS0_SHIFT 10
> +#define G_XPCS1_SHIFT 11
> +#define G_XPCS2_SHIFT 12
> +#define G_XPCS3_SHIFT 13
> +#define G_SATA0_SHIFT 14
> +#define G_SATA1_SHIFT 15
> +#define G_SATA2_SHIFT 16
> +#define G_SATA3_SHIFT 17
> +
> +/* Gate3 clock shift */
> +#define G_ARCEM4_SHIFT 0
> +#define G_IDMAR1_SHIFT 2
> +#define G_IDMAT0_SHIFT 3
> +#define G_IDMAT1_SHIFT 4
> +#define G_IDMAT2_SHIFT 5
> +
> +#define G_PPV4_SHIFT 8
> +#define G_GSWIPO_SHIFT 9
> +#define G_CQEM_SHIFT 10
> +#define G_XPCS5_SHIFT 14
> +#define G_USB1_SHIFT 25
> +#define G_USB2_SHIFT 26
> +
> +
> +/* Register definition */
> +#define CGU_PLL0CZ_CFG0 0x000
> +#define CGU_PLL0CM0_CFG0 0x020
> +#define CGU_PLL0CM1_CFG0 0x040
> +#define CGU_PLL0B_CFG0 0x060
> +#define CGU_PLL1_CFG0 0x080
> +#define CGU_PLL2_CFG0 0x0A0
> +#define CGU_PLLPP_CFG0 0x0C0
> +#define CGU_LJPLL3_CFG0 0x0E0
> +#define CGU_LJPLL4_CFG0 0x100
> +#define CGU_C55_PCMCR 0x18C
> +#define CGU_PCMCR 0x190
> +#define CGU_IF_CLK1 0x1A0
> +#define CGU_IF_CLK2 0x1A4
> +#define CGU_GATE0 0x300
> +#define CGU_GATE1 0x310
> +#define CGU_GATE2 0x320
> +#define CGU_GATE3 0x310
> +
> +#define PLL_DIV(x) ((x) + 0x04)
> +#define PLL_SSC(x) ((x) + 0x10)
> +
> +#define CLK_NR_CLKS (LGM_GCLK_USB2 + 1)
> +
> +/*
> + * Below table defines the pair's of regval & effective dividers.
> + * It's more efficient to provide an explicit table due to non-linear
> + * relation between values.
> + */
> +static const struct clk_div_table pll_div[] = {
> + { .val = 0, .div = 1 },
> + { .val = 1, .div = 2 },
> + { .val = 2, .div = 3 },
> + { .val = 3, .div = 4 },
> + { .val = 4, .div = 5 },
> + { .val = 5, .div = 6 },
> + { .val = 6, .div = 8 },
> + { .val = 7, .div = 10 },
> + { .val = 8, .div = 12 },
> + { .val = 9, .div = 16 },
> + { .val = 10, .div = 20 },
> + { .val = 11, .div = 24 },
> + { .val = 12, .div = 32 },
> + { .val = 13, .div = 40 },
> + { .val = 14, .div = 48 },
> + { .val = 15, .div = 64 },
> + {}
> +};
> +
> +static const struct clk_div_table dcl_div[] = {
> + { .val = 0, .div = 6 },
> + { .val = 1, .div = 12 },
> + { .val = 2, .div = 24 },
> + { .val = 3, .div = 32 },
> + { .val = 4, .div = 48 },
> + { .val = 5, .div = 96 },
> + {}
> +};
> +
> +static const struct clk_parent_data pll_p[] = {
> + { .fw_name = "osc", .name = "osc" },
> +};
> +static const struct clk_parent_data pllcm_p[] = {
> + { .fw_name = "cpu_cm", .name = "cpu_cm" },
> +};
> +static const struct clk_parent_data emmc_p[] = {
> + { .fw_name = "emmc4", .name = "emmc4" },
> + { .fw_name = "noc4", .name = "noc4" },
> +};
> +static const struct clk_parent_data sdxc_p[] = {
> + { .fw_name = "sdxc3", .name = "sdxc3" },
> + { .fw_name = "sdxc2", .name = "sdxc2" },
> +};
> +static const struct clk_parent_data pcm_p[] = {
> + { .fw_name = "v_docsis", .name = "v_docsis" },
> + { .fw_name = "dcl", .name = "dcl" },
> +};
> +static const struct clk_parent_data cbphy_p[] = {
> + { .fw_name = "dd_serdes", .name = "dd_serdes" },
> + { .fw_name = "dd_pcie", .name = "dd_pcie" },
> +};
> +
> +static const struct lgm_pll_clk_data lgm_pll_clks[] = {
> + LGM_PLL(LGM_CLK_PLL0CZ, "pll0cz", pll_p, CLK_IGNORE_UNUSED,
> + CGU_PLL0CZ_CFG0, TYPE_ROPLL),
> + LGM_PLL(LGM_CLK_PLL0CM0, "pll0cm0", pllcm_p, CLK_IGNORE_UNUSED,
> + CGU_PLL0CM0_CFG0, TYPE_ROPLL),
> + LGM_PLL(LGM_CLK_PLL0CM1, "pll0cm1", pllcm_p, CLK_IGNORE_UNUSED,
> + CGU_PLL0CM1_CFG0, TYPE_ROPLL),
> + LGM_PLL(LGM_CLK_PLL0B, "pll0b", pll_p, CLK_IGNORE_UNUSED,
> + CGU_PLL0B_CFG0, TYPE_ROPLL),
> + LGM_PLL(LGM_CLK_PLL1, "pll1", pll_p, 0, CGU_PLL1_CFG0, TYPE_ROPLL),
> + LGM_PLL(LGM_CLK_PLL2, "pll2", pll_p, CLK_IGNORE_UNUSED,
> + CGU_PLL2_CFG0, TYPE_ROPLL),
> + LGM_PLL(LGM_CLK_PLLPP, "pllpp", pll_p, 0, CGU_PLLPP_CFG0, TYPE_ROPLL),
> + LGM_PLL(LGM_CLK_LJPLL3, "ljpll3", pll_p, 0, CGU_LJPLL3_CFG0, TYPE_LJPLL),
> + LGM_PLL(LGM_CLK_LJPLL4, "ljpll4", pll_p, 0, CGU_LJPLL4_CFG0, TYPE_LJPLL),
> +};
> +
> +static const struct lgm_clk_branch lgm_branch_clks[] = {
> + LGM_DIV(LGM_CLK_PP_HW, "pp_hw", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
> + 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
> + LGM_DIV(LGM_CLK_PP_UC, "pp_uc", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
> + 4, PLL_DIV_WIDTH, 25, 1, 0, 0, pll_div),
> + LGM_DIV(LGM_CLK_PP_FXD, "pp_fxd", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
> + 8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
> + LGM_DIV(LGM_CLK_PP_TBM, "pp_tbm", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
> + 12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
> + LGM_DIV(LGM_CLK_DDR, "ddr", "pll2", CLK_IGNORE_UNUSED,
> + PLL_DIV(CGU_PLL2_CFG0), 0, PLL_DIV_WIDTH, 24, 1, 0, 0,
> + pll_div),
> + LGM_DIV(LGM_CLK_CM, "cpu_cm", "pll0cz", 0, PLL_DIV(CGU_PLL0CZ_CFG0),
> + 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
> +
> + LGM_DIV(LGM_CLK_IC, "cpu_ic", "pll0cz", CLK_IGNORE_UNUSED,
> + PLL_DIV(CGU_PLL0CZ_CFG0), 4, PLL_DIV_WIDTH, 25,
> + 1, 0, 0, pll_div),
> +
> + LGM_DIV(LGM_CLK_SDXC3, "sdxc3", "pll0cz", 0, PLL_DIV(CGU_PLL0CZ_CFG0),
> + 8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
> +
> + LGM_DIV(LGM_CLK_CPU0, "cm0", "pll0cm0",
> + CLK_IGNORE_UNUSED, PLL_DIV(CGU_PLL0CM0_CFG0),
> + 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
> + LGM_DIV(LGM_CLK_CPU1, "cm1", "pll0cm1",
> + CLK_IGNORE_UNUSED, PLL_DIV(CGU_PLL0CM1_CFG0),
> + 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
> +
> + /*
> + * Marking ngi_clk (next generation interconnect) and noc_clk
> + * (network on chip peripheral clk) as critical clocks because
> + * these are shared parent clock sources for many different
> + * peripherals.
> + */
> + LGM_DIV(LGM_CLK_NGI, "ngi", "pll0b",
> + (CLK_IGNORE_UNUSED|CLK_IS_CRITICAL), PLL_DIV(CGU_PLL0B_CFG0),
> + 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
> + LGM_DIV(LGM_CLK_NOC4, "noc4", "pll0b",
> + (CLK_IGNORE_UNUSED|CLK_IS_CRITICAL), PLL_DIV(CGU_PLL0B_CFG0),
> + 4, PLL_DIV_WIDTH, 25, 1, 0, 0, pll_div),
> + LGM_DIV(LGM_CLK_SW, "switch", "pll0b", 0, PLL_DIV(CGU_PLL0B_CFG0),
> + 8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
> + LGM_DIV(LGM_CLK_QSPI, "qspi", "pll0b", 0, PLL_DIV(CGU_PLL0B_CFG0),
> + 12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
> + LGM_DIV(LGM_CLK_CT, "v_ct", "pll1", 0, PLL_DIV(CGU_PLL1_CFG0),
> + 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
> + LGM_DIV(LGM_CLK_DSP, "v_dsp", "pll1", 0, PLL_DIV(CGU_PLL1_CFG0),
> + 8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
> + LGM_DIV(LGM_CLK_VIF, "v_ifclk", "pll1", 0, PLL_DIV(CGU_PLL1_CFG0),
> + 12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
> +
> + LGM_FIXED_FACTOR(LGM_CLK_EMMC4, "emmc4", "sdxc3", 0, 0,
> + 0, 0, 0, 0, 1, 4),
> + LGM_FIXED_FACTOR(LGM_CLK_SDXC2, "sdxc2", "noc4", 0, 0,
> + 0, 0, 0, 0, 1, 4),
> + LGM_MUX(LGM_CLK_EMMC, "emmc", emmc_p, 0, CGU_IF_CLK1,
> + 0, 1, CLK_MUX_ROUND_CLOSEST, 0),
> + LGM_MUX(LGM_CLK_SDXC, "sdxc", sdxc_p, 0, CGU_IF_CLK1,
> + 1, 1, CLK_MUX_ROUND_CLOSEST, 0),
> + LGM_FIXED(LGM_CLK_OSC, "osc", NULL, 0, 0, 0, 0, 0, 40000000, 0),
> + LGM_FIXED(LGM_CLK_SLIC, "slic", NULL, 0, CGU_IF_CLK1,
> + 8, 2, CLOCK_FLAG_VAL_INIT, 8192000, 2),
> + LGM_FIXED(LGM_CLK_DOCSIS, "v_docsis", NULL, 0, 0, 0, 0, 0, 16000000, 0),
> + LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", 0, CGU_PCMCR,
> + 25, 3, 0, 0, 0, 0, dcl_div),
> + LGM_MUX(LGM_CLK_PCM, "pcm", pcm_p, 0, CGU_C55_PCMCR,
> + 0, 1, CLK_MUX_ROUND_CLOSEST, 0),
> + LGM_FIXED_FACTOR(LGM_CLK_DDR_PHY, "ddr_phy", "ddr",
> + CLK_IGNORE_UNUSED, 0,
> + 0, 0, 0, 0, 2, 1),
> + LGM_FIXED_FACTOR(LGM_CLK_PONDEF, "pondef", "dd_pool",
> + CLK_SET_RATE_PARENT, 0, 0, 0, 0, 0, 1, 2),
> + LGM_MUX(LGM_CLK_CBPHY0, "cbphy0", cbphy_p, 0, 0,
> + 0, 0, MUX_CLK_SW | CLK_MUX_ROUND_CLOSEST, 0),
> + LGM_MUX(LGM_CLK_CBPHY1, "cbphy1", cbphy_p, 0, 0,
> + 0, 0, MUX_CLK_SW | CLK_MUX_ROUND_CLOSEST, 0),
> + LGM_MUX(LGM_CLK_CBPHY2, "cbphy2", cbphy_p, 0, 0,
> + 0, 0, MUX_CLK_SW | CLK_MUX_ROUND_CLOSEST, 0),
> + LGM_MUX(LGM_CLK_CBPHY3, "cbphy3", cbphy_p, 0, 0,
> + 0, 0, MUX_CLK_SW | CLK_MUX_ROUND_CLOSEST, 0),
> +
> + LGM_GATE(LGM_GCLK_C55, "g_c55", NULL, 0, CGU_GATE0,
> + G_C55_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_QSPI, "g_qspi", "qspi", 0, CGU_GATE0,
> + G_QSPI_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_EIP197, "g_eip197", NULL, 0, CGU_GATE0,
> + G_EIP197_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_VAULT, "g_vault130", NULL, 0, CGU_GATE0,
> + G_VAULT130_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_TOE, "g_toe", NULL, 0, CGU_GATE0,
> + G_TOE_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_SDXC, "g_sdxc", "sdxc", 0, CGU_GATE0,
> + G_SDXC_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_EMMC, "g_emmc", "emmc", 0, CGU_GATE0,
> + G_EMMC_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_SPI_DBG, "g_spidbg", NULL, 0, CGU_GATE0,
> + G_SPIDBG_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_DMA3, "g_dma3", NULL, 0, CGU_GATE0,
> + G_DMA3_SHIFT, 0, 0),
> +
> + LGM_GATE(LGM_GCLK_DMA0, "g_dma0", NULL, 0, CGU_GATE1,
> + G_DMA0_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_LEDC0, "g_ledc0", NULL, 0, CGU_GATE1,
> + G_LEDC0_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_LEDC1, "g_ledc1", NULL, 0, CGU_GATE1,
> + G_LEDC1_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_I2S0, "g_i2s0", NULL, 0, CGU_GATE1,
> + G_I2S0_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_I2S1, "g_i2s1", NULL, 0, CGU_GATE1,
> + G_I2S1_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_EBU, "g_ebu", NULL, 0, CGU_GATE1,
> + G_EBU_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_PWM, "g_pwm", NULL, 0, CGU_GATE1,
> + G_PWM_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_I2C0, "g_i2c0", NULL, 0, CGU_GATE1,
> + G_I2C0_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_I2C1, "g_i2c1", NULL, 0, CGU_GATE1,
> + G_I2C1_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_I2C2, "g_i2c2", NULL, 0, CGU_GATE1,
> + G_I2C2_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_I2C3, "g_i2c3", NULL, 0, CGU_GATE1,
> + G_I2C3_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_SSC0, "g_ssc0", "noc4", 0, CGU_GATE1,
> + G_SSC0_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_SSC1, "g_ssc1", "noc4", 0, CGU_GATE1,
> + G_SSC1_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_SSC2, "g_ssc2", "noc4", 0, CGU_GATE1,
> + G_SSC2_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_SSC3, "g_ssc3", "noc4", 0, CGU_GATE1,
> + G_SSC3_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_GPTC0, "g_gptc0", "noc4", 0, CGU_GATE1,
> + G_GPTC0_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_GPTC1, "g_gptc1", "noc4", 0, CGU_GATE1,
> + G_GPTC1_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_GPTC2, "g_gptc2", "noc4", 0, CGU_GATE1,
> + G_GPTC2_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_GPTC3, "g_gptc3", "osc", 0, CGU_GATE1,
> + G_GPTC3_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_ASC0, "g_asc0", "noc4", 0, CGU_GATE1,
> + G_ASC0_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_ASC1, "g_asc1", "noc4", 0, CGU_GATE1,
> + G_ASC1_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_ASC2, "g_asc2", "noc4", 0, CGU_GATE1,
> + G_ASC2_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_ASC3, "g_asc3", "osc", 0, CGU_GATE1,
> + G_ASC3_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_PCM0, "g_pcm0", NULL, 0, CGU_GATE1,
> + G_PCM0_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_PCM1, "g_pcm1", NULL, 0, CGU_GATE1,
> + G_PCM1_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_PCM2, "g_pcm2", NULL, 0, CGU_GATE1,
> + G_PCM2_SHIFT, 0, 0),
> +
> + LGM_GATE(LGM_GCLK_PCIE10, "g_pcie10", NULL, 0, CGU_GATE2,
> + G_PCIE10_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_PCIE11, "g_pcie11", NULL, 0, CGU_GATE2,
> + G_PCIE11_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_PCIE30, "g_pcie30", NULL, 0, CGU_GATE2,
> + G_PCIE30_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_PCIE31, "g_pcie31", NULL, 0, CGU_GATE2,
> + G_PCIE31_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_PCIE20, "g_pcie20", NULL, 0, CGU_GATE2,
> + G_PCIE20_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_PCIE21, "g_pcie21", NULL, 0, CGU_GATE2,
> + G_PCIE21_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_PCIE40, "g_pcie40", NULL, 0, CGU_GATE2,
> + G_PCIE40_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_PCIE41, "g_pcie41", NULL, 0, CGU_GATE2,
> + G_PCIE41_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_XPCS0, "g_xpcs0", NULL, 0, CGU_GATE2,
> + G_XPCS0_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_XPCS1, "g_xpcs1", NULL, 0, CGU_GATE2,
> + G_XPCS1_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_XPCS2, "g_xpcs2", NULL, 0, CGU_GATE2,
> + G_XPCS2_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_XPCS3, "g_xpcs3", NULL, 0, CGU_GATE2,
> + G_XPCS3_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_SATA0, "g_sata0", NULL, 0, CGU_GATE2,
> + G_SATA0_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_SATA1, "g_sata1", NULL, 0, CGU_GATE2,
> + G_SATA1_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_SATA2, "g_sata2", NULL, 0, CGU_GATE2,
> + G_SATA2_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_SATA3, "g_sata3", NULL, 0, CGU_GATE2,
> + G_SATA3_SHIFT, 0, 0),
> +
> + LGM_GATE(LGM_GCLK_ARCEM4, "g_arcem4", NULL, 0, CGU_GATE3,
> + G_ARCEM4_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_IDMAR1, "g_idmar1", NULL, 0, CGU_GATE3,
> + G_IDMAR1_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_IDMAT0, "g_idmat0", NULL, 0, CGU_GATE3,
> + G_IDMAT0_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_IDMAT1, "g_idmat1", NULL, 0, CGU_GATE3,
> + G_IDMAT1_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_IDMAT2, "g_idmat2", NULL, 0, CGU_GATE3,
> + G_IDMAT2_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_PPV4, "g_ppv4", NULL, 0, CGU_GATE3,
> + G_PPV4_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_GSWIPO, "g_gswipo", "switch", 0, CGU_GATE3,
> + G_GSWIPO_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_CQEM, "g_cqem", "switch", 0, CGU_GATE3,
> + G_CQEM_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_XPCS5, "g_xpcs5", NULL, 0, CGU_GATE3,
> + G_XPCS5_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_USB1, "g_usb1", NULL, 0, CGU_GATE3,
> + G_USB1_SHIFT, 0, 0),
> + LGM_GATE(LGM_GCLK_USB2, "g_usb2", NULL, 0, CGU_GATE3,
> + G_USB2_SHIFT, 0, 0),
> +};
> +
> +
> +static const struct lgm_clk_ddiv_data lgm_ddiv_clks[] = {
> + LGM_DDIV(LGM_CLK_CML, "dd_cml", "ljpll3", 0,
> + PLL_DIV(CGU_LJPLL3_CFG0), 0, PLL_DDIV_WIDTH,
> + 3, PLL_DDIV_WIDTH, 24, 1, 29, 0),
> + LGM_DDIV(LGM_CLK_SERDES, "dd_serdes", "ljpll3", 0,
> + PLL_DIV(CGU_LJPLL3_CFG0), 6, PLL_DDIV_WIDTH,
> + 9, PLL_DDIV_WIDTH, 25, 1, 28, 0),
> + LGM_DDIV(LGM_CLK_POOL, "dd_pool", "ljpll3", 0,
> + PLL_DIV(CGU_LJPLL3_CFG0), 12, PLL_DDIV_WIDTH,
> + 15, PLL_DDIV_WIDTH, 26, 1, 28, 0),
> + LGM_DDIV(LGM_CLK_PTP, "dd_ptp", "ljpll3", 0,
> + PLL_DIV(CGU_LJPLL3_CFG0), 18, PLL_DDIV_WIDTH,
> + 21, PLL_DDIV_WIDTH, 27, 1, 28, 0),
> + LGM_DDIV(LGM_CLK_PCIE, "dd_pcie", "ljpll4", 0,
> + PLL_DIV(CGU_LJPLL4_CFG0), 0, PLL_DDIV_WIDTH,
> + 3, PLL_DDIV_WIDTH, 24, 1, 29, 0),
> +};
> +
> +static inline struct lgm_clk_provider *
> +lgm_clk_init(struct device *dev, unsigned int nr_clks)
> +{
> + struct lgm_clk_provider *ctx;
> +
> + ctx = devm_kzalloc(dev, struct_size(ctx, clk_data.hws, nr_clks),
> + GFP_KERNEL);
> + if (!ctx)
> + return ERR_PTR(-ENOMEM);
> +
> + ctx->clk_data.num = nr_clks;
> +
> + return ctx;
> +}
> +
> +static int lgm_cgu_probe(struct platform_device *pdev)
> +{
[...]
> +
> + ctx->membase = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(ctx->membase))
> + return PTR_ERR(ctx->membase);
> +
> + ctx->np = np;
> + ctx->dev = dev;
> + spin_lock_init(&ctx->lock);
> +
> + ret = lgm_clk_register_plls(ctx, lgm_pll_clks,
> + ARRAY_SIZE(lgm_pll_clks));
> + if (ret)
> + return ret;
> +
> + ret = lgm_clk_register_branches(ctx, lgm_branch_clks,
> + ARRAY_SIZE(lgm_branch_clks));
> + if (ret)
> + return ret;
> +
> + ret = lgm_clk_register_ddiv(ctx, lgm_ddiv_clks,
> + ARRAY_SIZE(lgm_ddiv_clks));
> + if (ret)
> + return ret;
> +
> + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> + &ctx->clk_data);
> + if (ret)
> + return ret;
Are any of the clks unregistered on failure? It looks like devm_ isn't
used for registration so nothing can be undone? Please fix this in a
future patch.
^ permalink raw reply
* Re: [PATCH V5 0/8] Add APSS clock controller support for IPQ6018
From: Stephen Boyd @ 2020-05-27 2:25 UTC (permalink / raw)
To: Sivaprakash Murugesan, agross, bjorn.andersson, devicetree,
jassisinghbrar, linux-arm-msm, linux-clk, linux-kernel,
mturquette, robh+dt
Cc: Sivaprakash Murugesan
In-Reply-To: <1590314686-11749-1-git-send-email-sivaprak@codeaurora.org>
Quoting Sivaprakash Murugesan (2020-05-24 03:04:38)
> The CPU on Qualcomm's IPQ6018 devices are primarily fed by APSS PLL and XO,
> these are connected to a clock mux and enable block.
>
> This patch series adds support for these clocks and inturn enables clocks
> required for CPU freq.
What is your intended merge path? You sent this to qcom SoC maintainers,
mailbox maintainers, and clk maintainers. Who is supposed to apply the
series? Should it be split up and taken through various trees? Are there
dependencies? Please add more details to help us.
^ permalink raw reply
* Re: [PATCH V5 2/8] dt-bindings: clock: add ipq6018 a53 pll compatible
From: Stephen Boyd @ 2020-05-27 2:26 UTC (permalink / raw)
To: Sivaprakash Murugesan, agross, bjorn.andersson, devicetree,
jassisinghbrar, linux-arm-msm, linux-clk, linux-kernel,
mturquette, robh+dt
Cc: Sivaprakash Murugesan
In-Reply-To: <1590314686-11749-3-git-send-email-sivaprak@codeaurora.org>
Quoting Sivaprakash Murugesan (2020-05-24 03:04:40)
> cpus on ipq6018 are clocked by a53 pll, add device compatible for a53
> pll found on ipq6018 devices.
>
> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
> ---
> [V5]
> * Addressed Bjorn's review comment.
> now the a53 dt-binding represents ipq a53 pll as well.
> .../devicetree/bindings/clock/qcom,a53pll.yaml | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
> index 20d2638..972db15 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
> @@ -16,6 +16,7 @@ description:
> properties:
> compatible:
> const: qcom,msm8916-a53pll
> + const: qcom,ipq6018-a53pll
Sort alphabetical?
>
> reg:
> maxItems: 1
^ permalink raw reply
* Re: [PATCH V5 3/8] clk: qcom: Add ipq apss pll driver
From: Stephen Boyd @ 2020-05-27 2:29 UTC (permalink / raw)
To: Sivaprakash Murugesan, agross, bjorn.andersson, devicetree,
jassisinghbrar, linux-arm-msm, linux-clk, linux-kernel,
mturquette, robh+dt
Cc: Sivaprakash Murugesan
In-Reply-To: <1590314686-11749-4-git-send-email-sivaprak@codeaurora.org>
Quoting Sivaprakash Murugesan (2020-05-24 03:04:41)
> diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
> new file mode 100644
> index 0000000..aafdaa7
> --- /dev/null
> +++ b/drivers/clk/qcom/apss-ipq-pll.c
> @@ -0,0 +1,97 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/module.h>
Sort the includes above, also add clk-provider.h because this is a clk
provider.
> +
> +#include "clk-alpha-pll.h"
> +
> +static const u8 ipq_pll_offsets[] = {
[...]
> +
> +static int apss_ipq_pll_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct regmap *regmap;
> + struct resource *res;
> + void __iomem *base;
> + int ret;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(dev, res);
Use devm_platform_ioremap_resource()?
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + regmap = devm_regmap_init_mmio(&pdev->dev, base,
> + &ipq_pll_regmap_config);
Tabbing is off here. &ipq_pll_regmap_config should line up with the (
above.
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
^ permalink raw reply
* Re: [PATCH V5 4/8] clk: qcom: Add DT bindings for ipq6018 apss clock controller
From: Stephen Boyd @ 2020-05-27 2:30 UTC (permalink / raw)
To: Sivaprakash Murugesan, agross, bjorn.andersson, devicetree,
jassisinghbrar, linux-arm-msm, linux-clk, linux-kernel,
mturquette, robh+dt
Cc: Sivaprakash Murugesan
In-Reply-To: <1590314686-11749-5-git-send-email-sivaprak@codeaurora.org>
Quoting Sivaprakash Murugesan (2020-05-24 03:04:42)
> add dt-binding for ipq6018 apss clock controller
Capitalize 'add' because it starts the sentence.
>
> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
> ---
> include/dt-bindings/clock/qcom,apss-ipq.h | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
> create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h
>
> diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h
> new file mode 100644
> index 0000000..77b6e05
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,apss-ipq.h
> @@ -0,0 +1,12 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H
> +#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H
> +
> +#define APCS_ALIAS0_CLK_SRC 0
> +#define APCS_ALIAS0_CORE_CLK 1
Will this be extended in the future? I hope that this is the only two
clks we expect to see in this file.
^ permalink raw reply
* Re: [PATCH V5 5/8] clk: qcom: Add ipq6018 apss clock controller
From: Stephen Boyd @ 2020-05-27 2:33 UTC (permalink / raw)
To: Sivaprakash Murugesan, agross, bjorn.andersson, devicetree,
jassisinghbrar, linux-arm-msm, linux-clk, linux-kernel,
mturquette, robh+dt
Cc: Sivaprakash Murugesan
In-Reply-To: <1590314686-11749-6-git-send-email-sivaprak@codeaurora.org>
Quoting Sivaprakash Murugesan (2020-05-24 03:04:43)
> The CPU on Qualcomm ipq6018 devices are clocked primarily by a aplha PLL
> and xo which are connected to a mux and enable block.
>
> Add support for the mux and enable block which feeds the CPU on ipq6018
> devices.
>
> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply
* Re: [PATCH v5 1/2] clk: qcom: Add DT bindings for MSM8939 GCC
From: Stephen Boyd @ 2020-05-27 2:39 UTC (permalink / raw)
To: Bryan O'Donoghue, agross, bjorn.andersson, mturquette,
robh+dt
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, shawn.guo,
p.zabel, vincent.knecht, konradybcio, bryan.odonoghue
In-Reply-To: <20200517131348.688405-2-bryan.odonoghue@linaro.org>
Quoting Bryan O'Donoghue (2020-05-17 06:13:47)
> Add compatible strings and the include files for the MSM8939 GCC.
>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-arm-msm@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Tested-by: Vincent Knecht <vincent.knecht@mailoo.org>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
Applied to clk-next
^ permalink raw reply
* Re: [PATCH v5 2/2] clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller
From: Stephen Boyd @ 2020-05-27 2:40 UTC (permalink / raw)
To: Bryan O'Donoghue, agross, bjorn.andersson, mturquette,
robh+dt
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, shawn.guo,
p.zabel, vincent.knecht, konradybcio, bryan.odonoghue
In-Reply-To: <20200517131348.688405-3-bryan.odonoghue@linaro.org>
Quoting Bryan O'Donoghue (2020-05-17 06:13:48)
> This patch adds support for the MSM8939 GCC. The MSM8939 is based on the
> MSM8916. MSM8939 is compatible in several ways with MSM8916 but, has
> additional functional blocks added which require additional PLL sources. In
> some cases functional blocks from the MSM8916 have different clock sources
> or different supported frequencies.
>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Philipp Zabel <p.zabel@pengutronix.de>
> Cc: linux-arm-msm@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Co-developed-by: Shawn Guo <shawn.guo@linaro.org>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> Tested-by: Vincent Knecht <vincent.knecht@mailoo.org>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
Applied to clk-next
^ permalink raw reply
* Re: [PATCH] dt-bindings: clock: Add YAML schemas for QCOM A53 PLL
From: Stephen Boyd @ 2020-05-27 2:41 UTC (permalink / raw)
To: Sivaprakash Murugesan, agross, bjorn.andersson, devicetree,
linux-arm-msm, linux-clk, linux-kernel, mturquette, robh+dt
Cc: Sivaprakash Murugesan
In-Reply-To: <1588573803-3823-1-git-send-email-sivaprak@codeaurora.org>
Quoting Sivaprakash Murugesan (2020-05-03 23:30:03)
> This patch adds schema for primary CPU PLL found on few Qualcomm
> platforms.
>
> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
> ---
Applied to clk-next
^ permalink raw reply
* Re: [PATCH v7 18/24] iommu/arm-smmu-v3: Add support for Hardware Translation Table Update
From: Xiang Zheng @ 2020-05-27 3:00 UTC (permalink / raw)
To: Jean-Philippe Brucker, iommu, devicetree, linux-arm-kernel,
linux-pci, linux-mm
Cc: fenghua.yu, kevin.tian, jacob.jun.pan, jgg, catalin.marinas, joro,
robin.murphy, hch, zhangfei.gao, Jonathan.Cameron, felix.kuehling,
xuzaibo, will, christian.koenig, baolu.lu, Wang Haibin
In-Reply-To: <20200519175502.2504091-19-jean-philippe@linaro.org>
Hi Jean,
This patch only enables HTTU bits in CDs. Is it also neccessary to enable
HTTU bits in STEs in this patch?
On 2020/5/20 1:54, Jean-Philippe Brucker wrote:
> If the SMMU supports it and the kernel was built with HTTU support,
> enable hardware update of access and dirty flags. This is essential for
> shared page tables, to reduce the number of access faults on the fault
> queue. Normal DMA with io-pgtables doesn't currently use the access or
> dirty flags.
>
> We can enable HTTU even if CPUs don't support it, because the kernel
> always checks for HW dirty bit and updates the PTE flags atomically.
>
> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
> ---
> drivers/iommu/arm-smmu-v3.c | 24 +++++++++++++++++++++++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
> index 1386d4d2bc60..6a368218f54c 100644
> --- a/drivers/iommu/arm-smmu-v3.c
> +++ b/drivers/iommu/arm-smmu-v3.c
> @@ -58,6 +58,8 @@
> #define IDR0_ASID16 (1 << 12)
> #define IDR0_ATS (1 << 10)
> #define IDR0_HYP (1 << 9)
> +#define IDR0_HD (1 << 7)
> +#define IDR0_HA (1 << 6)
> #define IDR0_BTM (1 << 5)
> #define IDR0_COHACC (1 << 4)
> #define IDR0_TTF GENMASK(3, 2)
> @@ -311,6 +313,9 @@
> #define CTXDESC_CD_0_TCR_IPS GENMASK_ULL(34, 32)
> #define CTXDESC_CD_0_TCR_TBI0 (1ULL << 38)
>
> +#define CTXDESC_CD_0_TCR_HA (1UL << 43)
> +#define CTXDESC_CD_0_TCR_HD (1UL << 42)
> +
> #define CTXDESC_CD_0_AA64 (1UL << 41)
> #define CTXDESC_CD_0_S (1UL << 44)
> #define CTXDESC_CD_0_R (1UL << 45)
> @@ -663,6 +668,8 @@ struct arm_smmu_device {
> #define ARM_SMMU_FEAT_E2H (1 << 16)
> #define ARM_SMMU_FEAT_BTM (1 << 17)
> #define ARM_SMMU_FEAT_SVA (1 << 18)
> +#define ARM_SMMU_FEAT_HA (1 << 19)
> +#define ARM_SMMU_FEAT_HD (1 << 20)
> u32 features;
>
> #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0)
> @@ -1718,10 +1725,17 @@ static int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain,
> * this substream's traffic
> */
> } else { /* (1) and (2) */
> + u64 tcr = cd->tcr;
> +
> cdptr[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK);
> cdptr[2] = 0;
> cdptr[3] = cpu_to_le64(cd->mair);
>
> + if (!(smmu->features & ARM_SMMU_FEAT_HD))
> + tcr &= ~CTXDESC_CD_0_TCR_HD;
> + if (!(smmu->features & ARM_SMMU_FEAT_HA))
> + tcr &= ~CTXDESC_CD_0_TCR_HA;
> +
> /*
> * STE is live, and the SMMU might read dwords of this CD in any
> * order. Ensure that it observes valid values before reading
> @@ -1729,7 +1743,7 @@ static int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain,
> */
> arm_smmu_sync_cd(smmu_domain, ssid, true);
>
> - val = cd->tcr |
> + val = tcr |
> #ifdef __BIG_ENDIAN
> CTXDESC_CD_0_ENDI |
> #endif
> @@ -1958,10 +1972,12 @@ static struct arm_smmu_ctx_desc *arm_smmu_alloc_shared_cd(struct mm_struct *mm)
> return old_cd;
> }
>
> + /* HA and HD will be filtered out later if not supported by the SMMU */
> tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, 64ULL - VA_BITS) |
> FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, ARM_LPAE_TCR_RGN_WBWA) |
> FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, ARM_LPAE_TCR_RGN_WBWA) |
> FIELD_PREP(CTXDESC_CD_0_TCR_SH0, ARM_LPAE_TCR_SH_IS) |
> + CTXDESC_CD_0_TCR_HA | CTXDESC_CD_0_TCR_HD |
> CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64;
>
> switch (PAGE_SIZE) {
> @@ -4454,6 +4470,12 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
> smmu->features |= ARM_SMMU_FEAT_E2H;
> }
>
> + if (reg & (IDR0_HA | IDR0_HD)) {
> + smmu->features |= ARM_SMMU_FEAT_HA;
> + if (reg & IDR0_HD)
> + smmu->features |= ARM_SMMU_FEAT_HD;
> + }
> +
> /*
> * If the CPU is using VHE, but the SMMU doesn't support it, the SMMU
> * will create TLB entries for NH-EL1 world and will miss the
>
--
Thanks,
Xiang
^ permalink raw reply
* Re: [PATCH 1/3] clk: qcom: smd: Add support for MSM8936 rpm clocks
From: Stephen Boyd @ 2020-05-27 3:01 UTC (permalink / raw)
To: Konrad Dybcio, skrzynka
Cc: Vincent Knecht, Andy Gross, Bjorn Andersson, Michael Turquette,
Rob Herring, linux-arm-msm, linux-clk, devicetree, linux-kernel
In-Reply-To: <20200501205728.152048-1-konradybcio@gmail.com>
Quoting Konrad Dybcio (2020-05-01 13:57:26)
> From: Vincent Knecht <vincent.knecht@mailoo.org>
>
> Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
> ---
Applied to clk-next
^ permalink raw reply
* Re: [PATCH 2/3] dt-bindings: clock: rpmcc: Document MSM8936 compatible
From: Stephen Boyd @ 2020-05-27 3:01 UTC (permalink / raw)
To: Konrad Dybcio, skrzynka
Cc: Vincent Knecht, Andy Gross, Bjorn Andersson, Michael Turquette,
Rob Herring, linux-arm-msm, linux-clk, devicetree, linux-kernel
In-Reply-To: <20200501205728.152048-2-konradybcio@gmail.com>
Quoting Konrad Dybcio (2020-05-01 13:57:27)
> From: Vincent Knecht <vincent.knecht@mailoo.org>
>
> Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
> ---
Applied to clk-next
^ permalink raw reply
* Re: [PATCH 3/3] dt-bindings: soc: qcom: Document MSM8936 SMD RPM compatible
From: Stephen Boyd @ 2020-05-27 3:01 UTC (permalink / raw)
To: Konrad Dybcio, skrzynka
Cc: Vincent Knecht, Andy Gross, Bjorn Andersson, Michael Turquette,
Rob Herring, linux-arm-msm, linux-clk, devicetree, linux-kernel
In-Reply-To: <20200501205728.152048-3-konradybcio@gmail.com>
Quoting Konrad Dybcio (2020-05-01 13:57:28)
> From: Vincent Knecht <vincent.knecht@mailoo.org>
>
> Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
> ---
Applied to clk-next
^ permalink raw reply
* Re: [PATCH 4/4] dt-bindings: soc: qcom: Document MSM8936 SMD RPM compatible
From: Stephen Boyd @ 2020-05-27 3:03 UTC (permalink / raw)
To: Konrad Dybcio, Rob Herring
Cc: Michael Turquette, linux-kernel, Vincent Knecht, Andy Gross,
linux-clk, linux-arm-msm, Bjorn Andersson, devicetree,
Rob Herring
In-Reply-To: <20200512224522.GA13463@bogus>
Quoting Rob Herring (2020-05-12 15:45:22)
> On Sat, 2 May 2020 00:32:32 +0200, Konrad Dybcio wrote:
> > From: Vincent Knecht <vincent.knecht@mailoo.org>
> >
> > Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
> > ---
> > Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt | 1 +
> > 1 file changed, 1 insertion(+)
> >
>
> Acked-by: Rob Herring <robh@kernel.org>
I picked these ones up actually, not the other ones, but my MUA totally
failed to open anything because the patches weren't sent To: anyone. O
well!
^ permalink raw reply
* Re: [PATCH 4/4] dt-bindings: soc: qcom: Document MSM8936 SMD RPM compatible
From: Stephen Boyd @ 2020-05-27 3:06 UTC (permalink / raw)
To: Konrad Dybcio, Rob Herring
Cc: Michael Turquette, linux-kernel, Vincent Knecht, Andy Gross,
linux-clk, linux-arm-msm, Bjorn Andersson, devicetree,
Rob Herring
In-Reply-To: <159054862230.88029.9004999082945050815@swboyd.mtv.corp.google.com>
Quoting Stephen Boyd (2020-05-26 20:03:42)
> Quoting Rob Herring (2020-05-12 15:45:22)
> > On Sat, 2 May 2020 00:32:32 +0200, Konrad Dybcio wrote:
> > > From: Vincent Knecht <vincent.knecht@mailoo.org>
> > >
> > > Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
> > > ---
> > > Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> >
> > Acked-by: Rob Herring <robh@kernel.org>
>
> I picked these ones up actually, not the other ones, but my MUA totally
> failed to open anything because the patches weren't sent To: anyone. O
> well!
Oh and now I've dropped them because:
drivers/clk/qcom/clk-smd-rpm.c:478:4: error: ‘RPM_SMD_SYSMMNOC_A_CLK’ undeclared here (not in a function); did you mean ‘RPM_SMD_SNOC_A_CLK’?
478 | [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_sysmmnoc_a_clk,
| ^~~~~~~~~~~~~~~~~~~~~~
| RPM_SMD_SNOC_A_CLK
So please fix that and resend with proper To.
^ permalink raw reply
* Re: [PATCH v2 4/4] clk: qcom: lpass: Add support for LPASS clock controller for SC7180
From: Stephen Boyd @ 2020-05-27 3:10 UTC (permalink / raw)
To: Michael Turquette, Taniya Das
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Andy Gross, devicetree, robh, robh+dt, Taniya Das
In-Reply-To: <1589707344-8871-5-git-send-email-tdas@codeaurora.org>
Quoting Taniya Das (2020-05-17 02:22:24)
> diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c b/drivers/clk/qcom/lpasscorecc-sc7180.c
> new file mode 100644
> index 0000000..86e3599
> --- /dev/null
> +++ b/drivers/clk/qcom/lpasscorecc-sc7180.c
> @@ -0,0 +1,479 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/pm_clock.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/of.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "common.h"
> +#include "gdsc.h"
> +
> +enum {
> + P_BI_TCXO,
> + P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD,
> + P_SLEEP_CLK,
> +};
> +
> +static struct pll_vco fabia_vco[] = {
> + { 249600000, 2000000000, 0 },
> +};
> +
> +static const struct alpha_pll_config lpass_lpaaudio_dig_pll_config = {
> + .l = 0x20,
[...]
> +
> +static struct regmap_config lpass_core_cc_sc7180_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .fast_io = true,
> +};
> +
> +static const struct qcom_cc_desc lpass_core_hm_sc7180_desc = {
> + .config = &lpass_core_cc_sc7180_regmap_config,
> + .gdscs = lpass_core_hm_sc7180_gdscs,
> + .num_gdscs = ARRAY_SIZE(lpass_core_hm_sc7180_gdscs),
> +};
> +
> +static const struct qcom_cc_desc lpass_core_cc_sc7180_desc = {
> + .config = &lpass_core_cc_sc7180_regmap_config,
> + .clks = lpass_core_cc_sc7180_clocks,
> + .num_clks = ARRAY_SIZE(lpass_core_cc_sc7180_clocks),
> +};
> +
> +static const struct qcom_cc_desc lpass_audio_hm_sc7180_desc = {
> + .config = &lpass_core_cc_sc7180_regmap_config,
> + .gdscs = lpass_audio_hm_sc7180_gdscs,
> + .num_gdscs = ARRAY_SIZE(lpass_audio_hm_sc7180_gdscs),
> +};
> +
> +
Drop double newline please.
> +static int lpass_core_cc_sc7180_probe(struct platform_device *pdev)
> +{
> + const struct qcom_cc_desc *desc;
> + struct regmap *regmap;
> + int ret;
> +
> + lpass_core_cc_sc7180_regmap_config.name = "lpass_audio_cc";
> + desc = &lpass_audio_hm_sc7180_desc;
> + ret = qcom_cc_probe_by_index(pdev, 1, desc);
> + if (ret)
> + return ret;
> +
> + lpass_core_cc_sc7180_regmap_config.name = "lpass_core_cc";
> + regmap = qcom_cc_map(pdev, &lpass_core_cc_sc7180_desc);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + /*
> + * Keep the CLK always-ON
Why? Presumably to make sure we can access the lpass sysnoc path all the
time?
> + * LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK
> + */
> + regmap_update_bits(regmap, 0x24000, BIT(0), BIT(0));
> +
> + /* PLL settings */
> + regmap_write(regmap, 0x1008, 0x20);
> + regmap_update_bits(regmap, 0x1014, BIT(0), BIT(0));
> +
> + clk_fabia_pll_configure(&lpass_lpaaudio_dig_pll, regmap,
> + &lpass_lpaaudio_dig_pll_config);
> +
> + return qcom_cc_really_probe(pdev, &lpass_core_cc_sc7180_desc, regmap);
> +}
> +
> +static int lpass_hm_core_probe(struct platform_device *pdev)
> +{
> + const struct qcom_cc_desc *desc;
> + int ret;
> +
> + lpass_core_cc_sc7180_regmap_config.name = "lpass_hm_core";
> + desc = &lpass_core_hm_sc7180_desc;
> +
> + return qcom_cc_probe_by_index(pdev, 0, desc);
> +}
> +
> +static const struct of_device_id lpass_core_cc_sc7180_match_table[] = {
> + {
> + .compatible = "qcom,sc7180-lpasshm",
> + .data = lpass_hm_core_probe,
> + },
> + {
> + .compatible = "qcom,sc7180-lpasscorecc",
> + .data = lpass_core_cc_sc7180_probe,
> + },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, lpass_core_cc_sc7180_match_table);
> +
> +static int lpass_core_sc7180_probe(struct platform_device *pdev)
> +{
> + int (*clk_probe)(struct platform_device *p);
> + int ret;
> +
> + pm_runtime_enable(&pdev->dev);
> + ret = pm_clk_create(&pdev->dev);
> + if (ret)
> + return ret;
> +
> + ret = pm_clk_add(&pdev->dev, "gcc_lpass_sway");
> + if (ret < 0) {
> + dev_err(&pdev->dev, "failed to acquire iface clock\n");
Can the clk name be 'iface' if it's actually the interface clk?
"gcc_lpass_sway" looks to be the actual clk name which we shouldn't care
about here. It should be whatever clk name we consider it to be, which
would mean iface probably.
> + goto disable_pm_runtime;
> + }
> +
> + clk_probe = of_device_get_match_data(&pdev->dev);
> + if (!clk_probe)
> + return -EINVAL;
> +
> + ret = clk_probe(pdev);
> + if (ret)
> + goto destroy_pm_clk;
> +
> + return 0;
^ permalink raw reply
* Re: [PATCH v2 2/4] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
From: Stephen Boyd @ 2020-05-27 3:11 UTC (permalink / raw)
To: Michael Turquette, Taniya Das
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Andy Gross, devicetree, robh, robh+dt, Taniya Das
In-Reply-To: <1589707344-8871-3-git-send-email-tdas@codeaurora.org>
Quoting Taniya Das (2020-05-17 02:22:22)
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml
> new file mode 100644
> index 0000000..c025a0ae
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml
> @@ -0,0 +1,101 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm LPASS Core Clock Controller Binding for SC7180
> +
> +maintainers:
> + - Taniya Das <tdas@codeaurora.org>
> +
> +description: |
> + Qualcomm LPASS core clock control module which supports the clocks and
> + power domains on SC7180.
> +
> + See also:
> + - dt-bindings/clock/qcom,lpasscorecc-sc7180.h
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,sc7180-lpasshm
> + - qcom,sc7180-lpasscorecc
> +
> + clocks:
> + items:
> + - description: gcc_lpass_sway clock from GCC
> +
> + clock-names:
> + items:
> + - const: gcc_lpass_sway
As said on patch #4, maybe "iface" instead?
> +
> + power-domains:
> + items:
> + - description: LPASS CORE HM GSDCR
> +
^ permalink raw reply
* Re: [PATCH net v3 0/4] net: ethernet: fec: move GPR reigster offset and bit into DT
From: David Miller @ 2020-05-27 3:22 UTC (permalink / raw)
To: fugang.duan
Cc: andrew, martin.fuzzey, s.hauer, netdev, robh+dt, shawnguo,
devicetree, kuba
In-Reply-To: <1590424033-16906-1-git-send-email-fugang.duan@nxp.com>
From: fugang.duan@nxp.com
Date: Tue, 26 May 2020 00:27:09 +0800
> From: Fugang Duan <fugang.duan@nxp.com>
>
> The commit da722186f654 (net: fec: set GPR bit on suspend by
> DT configuration) set the GPR reigster offset and bit in driver
> for wol feature support.
>
> It brings trouble to enable wol feature on imx6sx/imx6ul/imx7d
> platforms that have multiple ethernet instances with different
> GPR bit for stop mode control. So the patch set is to move GPR
> register offset and bit define into DT, and enable imx6q/imx6dl
> imx6qp/imx6sx/imx6ul/imx7d stop mode support.
>
> Currently, below NXP i.MX boards support wol:
> - imx6q/imx6dl/imx6qp sabresd
> - imx6sx sabreauto
> - imx7d sdb
>
> imx6q/imx6dl/imx6qp sabresd board dts file miss the property
> "fsl,magic-packet;", so patch#4 is to add the property for stop
> mode support.
>
>
> v1 -> v2:
> - driver: switch back to store the quirks bitmask in driver_data
> - dt-bindings: rename 'gpr' property string to 'fsl,stop-mode'
> - imx6/7 dtsi: add imx6sx/imx6ul/imx7d ethernet stop mode property
> v2 -> v3:
> - driver: suggested by Sascha Hauer, use a struct fec_devinfo for
> abstracting differences between different hardware variants,
> it can give more freedom to describe the differences.
> - imx6/7 dtsi: correct one typo pointed out by Andrew.
>
> Thanks Martin, Andrew and Sascha Hauer for the review.
Series applied to net-next, thanks.
^ permalink raw reply
* Re: [PATCH v5 5/8] clk: stm32: Fix stm32f429's ltdc driver hang in set clock rate, fix duplicated ltdc clock register to 'clk_core' case ltdc's clock turn off by clk_disable_unused()
From: dillon min @ 2020-05-27 3:30 UTC (permalink / raw)
To: Stephen Boyd
Cc: Mark Brown, Linus Walleij,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, Linux Kernel Mailing List, linux-spi, linux-stm32,
open list:DRM PANEL DRIVERS, linux-clk
In-Reply-To: <159054389592.88029.12389551390229328953@swboyd.mtv.corp.google.com>
Hi Stephen,
Thanks for reviewing.
On Wed, May 27, 2020 at 9:44 AM Stephen Boyd <sboyd@kernel.org> wrote:
>
> Quoting dillon.minfei@gmail.com (2020-05-24 20:45:45)
> > From: dillon min <dillon.minfei@gmail.com>
> >
> > ltdc set clock rate crashed
> > 'post_div_data[]''s pll_num is PLL_I2S, PLL_SAI (number is 1,2). but,
>
> Please write "post_div_data[]'s" if it is possessive. "But" doesn't
> start a sentence. This is one sentence, not two.
Ok.
>
> > as pll_num is offset of 'clks[]' input to clk_register_pll_div(), which
> > is FCLK, CLK_LSI, defined in 'include/dt-bindings/clock/stm32fx-clock.h'
> > so, this is a null object at the register time.
> > then, in ltdc's clock is_enabled(), enable(), will call to_clk_gate().
> > will return a null object, cause kernel crashed.
> > need change pll_num to PLL_VCO_I2S, PLL_VCO_SAI for 'post_div_data[]'
> >
> > duplicated ltdc clock
> > 'stm32f429_gates[]' has a member 'ltdc' register to 'clk_core', but no
> > upper driver use it, ltdc driver use the lcd-tft defined in
> > 'stm32f429_aux_clk[]'. after system startup, as stm32f429_gates[]'s ltdc
> > enable_count is zero, so turn off by clk_disable_unused()
>
> I sort of follow this. Is this another patch? Seems like two things are
> going on here.
This patch fix two bugs about stm32's clock.
bug1: ltdc driver loading hang in clk_set_rate(), this is due to
misuse ‘PLL_VCO_SAI' and
'PLL_SAI'.
speak in short, from the below code,
’PLL_SAI' is 2, 'PLL_VCO_SAI' is 7.
'post_div' point to 'post_div_data[]', 'post_div->pll_num' is
PLL_I2S, PLL_SAI.
'clks[PLL_VCOM_SAI' has vaild 'struct clk_hw* ' return from
stm32f4_rcc_register_pll()
but, at line 1776, use the 'clks[post_div->pll_num]', equal to
'clks[PLL_SAI]', this is invaild
at that time.
include/dt-bindings/clock/stm32fx-clock.h
29 #define PLL_VCO_SAI 7
drivers/clk/clk-stm32f4.c
494 enum {
495 PLL,
496 PLL_I2S,
497 PLL_SAI,
498 };
558 static const struct stm32f4_pll_post_div_data
post_div_data[MAX_POST_DIV] = {
559 { CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q",
560 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
561
562 { CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q",
563 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
564
565 { NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
566 STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },
567 };
1759 clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll("vco_in",
1760 &data->pll_data[2], &stm32f4_clk_lock);
1761
1762 for (n = 0; n < MAX_POST_DIV; n++) {
1763 const struct stm32f4_pll_post_div_data *post_div;
1764 struct clk_hw *hw;
1765
1766 post_div = &post_div_data[n];
1767
1768 hw = clk_register_pll_div(post_div->name,
1769 post_div->parent,
1770 post_div->flag,
1771 base + post_div->offset,
1772 post_div->shift,
1773 post_div->width,
1774 post_div->flag_div,
1775 post_div->div_table,
1776 clks[post_div->pll_num],
1777 &stm32f4_clk_lock);
1778
1779 if (post_div->idx != NO_IDX)
1780 clks[post_div->idx] = hw;
1781 }
bug2: ltdc's clock turn off by clk_disable_unused()
from your comments at '[PATCH v3 4/5] clk: stm32: Fix stm32f429 ltdc
driver loading hang
in clk set rate. keep ltdc clk running after kernel startup' , i go
deep into the code, found
stm32's clk driver register two gate clk to clk core by
clk_hw_register_gate() and
clk_hw_register_composite()
first: 'stm32f429_gates[]', clk name is 'ltdc', this is no user used.
second: 'stm32f429_aux_clk[]', clk name is 'lcd-tft', this is used by
ltdc driver
both of them point to the same offset of stm32's RCC register. after
kernel enter console,
clk core turn off ltdc's clk as 'stm32f429_gates[]' is unused. but,
actually 'stm32f429_aux_clk[]'
is in use.
i can separate this patch to two, each bug a patch if necessary
>
> >
> > Changes since V3:
> > 1 drop last wrong changes about 'CLK_IGNORE_UNUSED' patch
> > 2 fix PLL_SAI mismatch with PLL_VCO_SAI
>
> This change log goes under the --- below.
ok
>
> >
> > Signed-off-by: dillon min <dillon.minfei@gmail.com>
>
> Any Fixes tag?
ok, will add --fixup in git commit next time, this patch fix two bugs,
i should make two commit, each one has a
fixes tag, right?
first point to '517633e clk: stm32f4: Add post divisor for I2S & SAI PLLs'
second point to 'daf2d11 clk: stm32f4: Add lcd-tft clock'
^ permalink raw reply
* [v3 2/2] dts: ppc: t1024rdb: remove interrupts property
From: Biwen Li @ 2020-05-27 3:42 UTC (permalink / raw)
To: leoyang.li, robh+dt, mpe, benh, a.zummo, alexandre.belloni
Cc: devicetree, linuxppc-dev, linux-kernel, linux-rtc, Biwen Li
In-Reply-To: <20200527034228.23793-1-biwen.li@oss.nxp.com>
From: Biwen Li <biwen.li@nxp.com>
Since the interrupt pin for RTC DS1339 is not connected
to the CPU on T1024RDB, remove the interrupt property
from the device tree.
This also fix the following warning for hwclock.util-linux:
$ hwclock.util-linux
hwclock.util-linux: select() to /dev/rtc0
to wait for clock tick timed out
Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
arch/powerpc/boot/dts/fsl/t1024rdb.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1024rdb.dts b/arch/powerpc/boot/dts/fsl/t1024rdb.dts
index 645caff98ed1..605ceec66af3 100644
--- a/arch/powerpc/boot/dts/fsl/t1024rdb.dts
+++ b/arch/powerpc/boot/dts/fsl/t1024rdb.dts
@@ -161,7 +161,6 @@
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
- interrupts = <0x1 0x1 0 0>;
};
};
--
2.17.1
^ permalink raw reply related
* [v3 1/2] dts: ppc: t4240rdb: remove interrupts property
From: Biwen Li @ 2020-05-27 3:42 UTC (permalink / raw)
To: leoyang.li, robh+dt, mpe, benh, a.zummo, alexandre.belloni
Cc: devicetree, linuxppc-dev, linux-kernel, linux-rtc, Biwen Li
From: Biwen Li <biwen.li@nxp.com>
Since the interrupt pin for RTC DS1374 is not connected
to the CPU on T4240RDB, remove the interrupt property
from the device tree.
This also fix the following warning for hwclock.util-linux:
$ hwclock.util-linux
hwclock.util-linux: select() to /dev/rtc0
to wait for clock tick timed out
Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
arch/powerpc/boot/dts/fsl/t4240rdb.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/fsl/t4240rdb.dts b/arch/powerpc/boot/dts/fsl/t4240rdb.dts
index a56a705d41f7..145896f2eef6 100644
--- a/arch/powerpc/boot/dts/fsl/t4240rdb.dts
+++ b/arch/powerpc/boot/dts/fsl/t4240rdb.dts
@@ -144,7 +144,6 @@
rtc@68 {
compatible = "dallas,ds1374";
reg = <0x68>;
- interrupts = <0x1 0x1 0 0>;
};
};
--
2.17.1
^ permalink raw reply related
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