* Re: [PATCH v2 2/4] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
From: Rob Herring @ 2020-05-28 20:25 UTC (permalink / raw)
To: Taniya Das
Cc: Stephen Boyd, Michael Turquette , David Brown,
Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk, linux-kernel,
Andy Gross, devicetree
In-Reply-To: <1589707344-8871-3-git-send-email-tdas@codeaurora.org>
On Sun, May 17, 2020 at 02:52:22PM +0530, Taniya Das wrote:
> The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic
> properties that are needed in a device tree. Also add clock ids for GCC
> LPASS and LPASS Core clock IDs for LPASS client to request for the clocks.
>
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---
> .../bindings/clock/qcom,sc7180-lpasscorecc.yaml | 101 +++++++++++++++++++++
> include/dt-bindings/clock/qcom,gcc-sc7180.h | 1 +
> .../dt-bindings/clock/qcom,lpasscorecc-sc7180.h | 29 ++++++
> 3 files changed, 131 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml
> create mode 100644 include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml
> new file mode 100644
> index 0000000..c025a0ae
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml
> @@ -0,0 +1,101 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm LPASS Core Clock Controller Binding for SC7180
> +
> +maintainers:
> + - Taniya Das <tdas@codeaurora.org>
> +
> +description: |
> + Qualcomm LPASS core clock control module which supports the clocks and
> + power domains on SC7180.
> +
> + See also:
> + - dt-bindings/clock/qcom,lpasscorecc-sc7180.h
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,sc7180-lpasshm
> + - qcom,sc7180-lpasscorecc
> +
> + clocks:
> + items:
> + - description: gcc_lpass_sway clock from GCC
> +
> + clock-names:
> + items:
> + - const: gcc_lpass_sway
> +
> + power-domains:
> + items:
> + - description: LPASS CORE HM GSDCR
For single entry, 'maxItems: 1' is enough.
> +
> + '#clock-cells':
> + const: 1
> +
> + '#power-domain-cells':
> + const: 1
> +
> + reg:
> + minItems: 1
> + maxItems: 2
> + items:
> + - description: lpass audio cc register
> + - description: lpass core cc register
audio then core
> +
> + reg-names:
> + items:
> + - const: lpass_core_cc
> + - const: lpass_audio_cc
core then audio?
2 reg-names required, but 1 reg allowed?
> +
> +if:
> + properties:
> + compatible:
> + contains:
> + const: qcom,sc7180-lpasshm
> +then:
> + properties:
> + reg:
> + items:
> + - description: lpass hm core register
reg-names allowed in this case?
Ideally, this would have just 'maxItems: 1' to just disallow the 2nd
entry above.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - '#clock-cells'
> + - '#power-domain-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-sc7180.h>
> + #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
> + clock-controller@63000000 {
> + compatible = "qcom,sc7180-lpasshm";
> + reg = <0 0x63000000 0 0x28>;
> + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>;
> + clock-names = "gcc_lpass_sway";
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> + - |
> + clock-controller@62d00000 {
> + compatible = "qcom,sc7180-lpasscorecc";
> + reg = <0 0x62d00000 0 0x50000>,
> + <0 0x62780000 0 0x30000>;
> + reg-names = "lpass_core_cc", "lpass_audio_cc";
> + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>;
> + clock-names = "gcc_lpass_sway";
> + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +...
> diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h
> index 1258fd0..439476c 100644
> --- a/include/dt-bindings/clock/qcom,gcc-sc7180.h
> +++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h
> @@ -137,6 +137,7 @@
> #define GCC_MSS_NAV_AXI_CLK 127
> #define GCC_MSS_Q6_MEMNOC_AXI_CLK 128
> #define GCC_MSS_SNOC_AXI_CLK 129
> +#define GCC_LPASS_CFG_NOC_SWAY_CLK 130
>
> /* GCC resets */
> #define GCC_QUSB2PHY_PRIM_BCR 0
> diff --git a/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h b/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
> new file mode 100644
> index 0000000..a55d01d
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H
> +#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H
> +
> +/* LPASS_CORE_CC clocks */
> +#define LPASS_LPAAUDIO_DIG_PLL 0
> +#define LPASS_LPAAUDIO_DIG_PLL_OUT_ODD 1
> +#define CORE_CLK_SRC 2
> +#define EXT_MCLK0_CLK_SRC 3
> +#define LPAIF_PRI_CLK_SRC 4
> +#define LPAIF_SEC_CLK_SRC 5
> +#define LPASS_AUDIO_CORE_CORE_CLK 6
> +#define LPASS_AUDIO_CORE_EXT_MCLK0_CLK 7
> +#define LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK 8
> +#define LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK 9
> +#define LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK 10
> +
> +/* LPASS Core power domains */
> +#define LPASS_CORE_HM_GDSCR 0
> +
> +/* LPASS Audio power domains */
> +#define LPASS_AUDIO_HM_GDSCR 0
> +#define LPASS_PDC_HM_GDSCR 1
> +
> +#endif
> --
> Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
> of the Code Aurora Forum, hosted by the Linux Foundation.
>
^ permalink raw reply
* Re: [PATCH 01/12] dt-bindings: display: Convert ingenic,lcd.txt to YAML
From: Rob Herring @ 2020-05-28 20:17 UTC (permalink / raw)
To: Paul Cercueil
Cc: Rob Herring, David Airlie, Daniel Vetter, devicetree, od,
linux-kernel, Greg Kroah-Hartman, dri-devel, Rafael J . Wysocki
In-Reply-To: <20200516215057.392609-1-paul@crapouillou.net>
On Sat, 16 May 2020 23:50:46 +0200, Paul Cercueil wrote:
> Convert the ingenic,lcd.txt to a new ingenic,lcd.yaml file.
>
> In the process, the new ingenic,jz4780-lcd compatible string has been
> added.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
>
> Notes:
> This patch comes from a different patchset so it's effectively a V2.
>
> Changes were:
> - lcd_pclk and lcd clocks are in the correct order now,
> - Add 'port' and 'ports' properties, and document the valid ports.
>
> .../bindings/display/ingenic,lcd.txt | 45 -------
> .../bindings/display/ingenic,lcd.yaml | 126 ++++++++++++++++++
> 2 files changed, 126 insertions(+), 45 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/ingenic,lcd.txt
> create mode 100644 Documentation/devicetree/bindings/display/ingenic,lcd.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: iio: adc: Add binding for current-from-voltage
From: Jonathan Bakker @ 2020-05-28 20:16 UTC (permalink / raw)
To: Rob Herring
Cc: jic23, knaack.h, lars, pmeerw, linux-iio, linux-kernel,
devicetree, linus.walleij
In-Reply-To: <20200528201306.GA594238@bogus>
Hi Rob,
On 2020-05-28 1:13 p.m., Rob Herring wrote:
> On Fri, May 15, 2020 at 07:26:18PM -0700, Jonathan Bakker wrote:
>> Some devices may require a current adc, but only have a voltage
>> ADC onboard. In order to read the current, they have a resistor
>> connected to the ADC. Add bindings for this possibility.
>>
>> Signed-off-by: Jonathan Bakker <xc-racer2@live.ca>
>> ---
>> .../iio/adc/linux,current-from-voltage.yaml | 47 +++++++++++++++++++
>> 1 file changed, 47 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/iio/adc/linux,current-from-voltage.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/iio/adc/linux,current-from-voltage.yaml b/Documentation/devicetree/bindings/iio/adc/linux,current-from-voltage.yaml
>> new file mode 100644
>> index 000000000000..385d317607c3
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/iio/adc/linux,current-from-voltage.yaml
>> @@ -0,0 +1,47 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/iio/adc/linux,current-from-voltage.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Current ADC from voltage ADC and resistor
>> +
>> +maintainers:
>> + - Jonathan Bakker <xc-racer2@live.ca>
>> +
>> +properties:
>> + compatible:
>> + const: linux,current-from-voltage
>
> How is an ADC with a resistor attached a Linux thing? So you don't need
> 'linux', but then 'current-from-voltage' isn't the best naming. I don't
> have a suggestion ATM.
>
The good/bad news is that I was re-implementing an existing driver under a new name :)
The compatible is current-sense-shunt for this exact same purpose.
Thanks,
Jonathan
>> +
>> + io-channel-names:
>> + const: adc
>> +
>> + io-channels:
>> + maxItems: 1
>> + description: Voltage ADC channel
>> +
>> + linux,resistor-ohms:
>> + description: Strength of resistor connected to voltage ADC
>
> Wouldn't you need this to be micro-ohms? Otherwise, there'd be too much
> voltage drop?
>
> Rob
>
^ permalink raw reply
* Re: [PATCH v4 4/6] dt-bindings: interrupt-controller: Add Loongson PCH PIC
From: Rob Herring @ 2020-05-28 20:15 UTC (permalink / raw)
To: Jiaxun Yang
Cc: linux-kernel, devicetree, Thomas Gleixner, Rob Herring,
Jason Cooper, linux-mips, maz, Huacai Chen
In-Reply-To: <20200516082912.3673033-4-jiaxun.yang@flygoat.com>
On Sat, 16 May 2020 16:29:04 +0800, Jiaxun Yang wrote:
> Add binding for Loongson PCH PIC Controller.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> --
> v2:
> - Fix naming
> - Mark loongson,pic-base-vec as required
> ---
> .../loongson,pch-pic.yaml | 53 +++++++++++++++++++
> 1 file changed, 53 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,pch-pic.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v4 2/6] dt-bindings: interrupt-controller: Add Loongson HTVEC
From: Rob Herring @ 2020-05-28 20:14 UTC (permalink / raw)
To: Jiaxun Yang
Cc: Thomas Gleixner, linux-kernel, Rob Herring, Huacai Chen,
Jason Cooper, linux-mips, devicetree, maz
In-Reply-To: <20200516082912.3673033-2-jiaxun.yang@flygoat.com>
On Sat, 16 May 2020 16:29:02 +0800, Jiaxun Yang wrote:
> Add binding for Loongson-3 HyperTransport Interrupt Vector Controller.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> --
> v4: Drop ref, '|', add additionalProperties, fix example
> ---
> .../interrupt-controller/loongson,htvec.yaml | 58 +++++++++++++++++++
> 1 file changed, 58 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: iio: adc: Add binding for current-from-voltage
From: Rob Herring @ 2020-05-28 20:13 UTC (permalink / raw)
To: Jonathan Bakker
Cc: jic23, knaack.h, lars, pmeerw, linux-iio, linux-kernel,
devicetree, linus.walleij
In-Reply-To: <BN6PR04MB06600A3AFE160C6E07BF5B2CA3BA0@BN6PR04MB0660.namprd04.prod.outlook.com>
On Fri, May 15, 2020 at 07:26:18PM -0700, Jonathan Bakker wrote:
> Some devices may require a current adc, but only have a voltage
> ADC onboard. In order to read the current, they have a resistor
> connected to the ADC. Add bindings for this possibility.
>
> Signed-off-by: Jonathan Bakker <xc-racer2@live.ca>
> ---
> .../iio/adc/linux,current-from-voltage.yaml | 47 +++++++++++++++++++
> 1 file changed, 47 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/linux,current-from-voltage.yaml
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/linux,current-from-voltage.yaml b/Documentation/devicetree/bindings/iio/adc/linux,current-from-voltage.yaml
> new file mode 100644
> index 000000000000..385d317607c3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/linux,current-from-voltage.yaml
> @@ -0,0 +1,47 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/adc/linux,current-from-voltage.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Current ADC from voltage ADC and resistor
> +
> +maintainers:
> + - Jonathan Bakker <xc-racer2@live.ca>
> +
> +properties:
> + compatible:
> + const: linux,current-from-voltage
How is an ADC with a resistor attached a Linux thing? So you don't need
'linux', but then 'current-from-voltage' isn't the best naming. I don't
have a suggestion ATM.
> +
> + io-channel-names:
> + const: adc
> +
> + io-channels:
> + maxItems: 1
> + description: Voltage ADC channel
> +
> + linux,resistor-ohms:
> + description: Strength of resistor connected to voltage ADC
Wouldn't you need this to be micro-ohms? Otherwise, there'd be too much
voltage drop?
Rob
^ permalink raw reply
* Re: [PATCH v3] dt-bindings: gpio: renesas,rcar-gpio: Add r8a7742 (RZ/G1H) support
From: Rob Herring @ 2020-05-28 20:06 UTC (permalink / raw)
To: Lad Prabhakar
Cc: devicetree, linux-gpio, Rob Herring, Linus Walleij, linux-kernel,
Geert Uytterhoeven, Prabhakar, Bartosz Golaszewski
In-Reply-To: <1589557527-6057-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Fri, 15 May 2020 16:45:27 +0100, Lad Prabhakar wrote:
> Renesas RZ/G1H (R8A7742) SoC GPIO blocks are identical to the R-Car Gen2
> family. Add support for its GPIO controllers.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2->v3:
> 1: Rebased the patch as binding were converted into json format.
> I have restored the Acks' from Geert and Rob
> (https://patchwork.kernel.org/patch/11518759/).
>
> v1->v2:
> * No change
> ---
> Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH 14/17] dt-bindings: power: renesas,apmu: Document r8a7742 support
From: Rob Herring @ 2020-05-28 20:05 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Ulf Hansson, linux-watchdog, Prabhakar, linux-kernel, linux-i2c,
Wim Van Sebroeck, netdev, Wolfram Sang, linux-mmc,
Geert Uytterhoeven, David S. Miller, linux-renesas-soc,
Rob Herring, Sergei Shtylyov, Guenter Roeck, Jens Axboe,
devicetree, linux-ide
In-Reply-To: <1589555337-5498-15-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Fri, 15 May 2020 16:08:54 +0100, Lad Prabhakar wrote:
> Document APMU and SMP enable method for RZ/G1H (also known as r8a7742)
> SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/power/renesas,apmu.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH 11/17] dt-bindings: net: renesas,ether: Document R8A7742 SoC
From: Rob Herring @ 2020-05-28 20:04 UTC (permalink / raw)
To: Lad Prabhakar
Cc: David S. Miller, Jens Axboe, Rob Herring, netdev, linux-watchdog,
Wolfram Sang, Prabhakar, Wim Van Sebroeck, linux-kernel,
linux-renesas-soc, linux-mmc, Ulf Hansson, linux-i2c,
Geert Uytterhoeven, Guenter Roeck, linux-ide, Sergei Shtylyov,
devicetree
In-Reply-To: <1589555337-5498-12-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Fri, 15 May 2020 16:08:51 +0100, Lad Prabhakar wrote:
> Document RZ/G1H (R8A7742) SoC bindings.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/net/renesas,ether.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH 10/17] dt-bindings: net: renesas,ravb: Add support for r8a7742 SoC
From: Rob Herring @ 2020-05-28 20:04 UTC (permalink / raw)
To: Lad Prabhakar
Cc: devicetree, netdev, linux-renesas-soc, linux-mmc, Prabhakar,
linux-watchdog, Guenter Roeck, Ulf Hansson, Jens Axboe,
Sergei Shtylyov, Wim Van Sebroeck, David S. Miller, linux-kernel,
linux-i2c, linux-ide, Rob Herring, Wolfram Sang,
Geert Uytterhoeven
In-Reply-To: <1589555337-5498-11-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Fri, 15 May 2020 16:08:50 +0100, Lad Prabhakar wrote:
> Document RZ/G1H (R8A7742) SoC bindings.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH 08/17] dt-bindings: ata: renesas,rcar-sata: Add r8a7742 support
From: Rob Herring @ 2020-05-28 20:04 UTC (permalink / raw)
To: Lad Prabhakar
Cc: linux-renesas-soc, Rob Herring, Guenter Roeck, Wolfram Sang,
David S. Miller, Sergei Shtylyov, linux-kernel, linux-ide,
Ulf Hansson, Geert Uytterhoeven, Prabhakar, netdev, Jens Axboe,
devicetree, linux-watchdog, linux-i2c, Wim Van Sebroeck,
linux-mmc
In-Reply-To: <1589555337-5498-9-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Fri, 15 May 2020 16:08:48 +0100, Lad Prabhakar wrote:
> Document SATA support for the RZ/G1H, which is compatible with
> R-Car Gen2 SoC family.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH 02/17] dt-bindings: i2c: renesas,iic: Document r8a7742 support
From: Rob Herring @ 2020-05-28 20:03 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Geert Uytterhoeven, Rob Herring, Ulf Hansson, Jens Axboe,
Wolfram Sang, Sergei Shtylyov, David S. Miller, linux-mmc,
linux-i2c, linux-ide, Prabhakar, devicetree, Guenter Roeck,
linux-watchdog, netdev, Wim Van Sebroeck, linux-renesas-soc,
linux-kernel
In-Reply-To: <1589555337-5498-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Fri, 15 May 2020 16:08:42 +0100, Lad Prabhakar wrote:
> Document IIC controller for RZ/G1H (R8A7742) SoC, which is compatible
> with R-Car Gen2 SoC family.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/i2c/renesas,iic.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH 01/17] dt-bindings: i2c: renesas,i2c: Document r8a7742 support
From: Rob Herring @ 2020-05-28 20:03 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Geert Uytterhoeven, Ulf Hansson, Guenter Roeck, linux-renesas-soc,
linux-kernel, Jens Axboe, linux-mmc, David S. Miller, netdev,
Wolfram Sang, Wim Van Sebroeck, devicetree, Prabhakar,
Rob Herring, linux-i2c, linux-ide, linux-watchdog,
Sergei Shtylyov
In-Reply-To: <1589555337-5498-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Fri, 15 May 2020 16:08:41 +0100, Lad Prabhakar wrote:
> Document i2c controller for RZ/G1H (R8A7742) SoC, which is compatible
> with R-Car Gen2 SoC family.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/i2c/renesas,i2c.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Applied, thanks!
^ permalink raw reply
* Re: [RFC PATCH 3/6] dt-bindings: display/bridge/nwl-dsi: Drop mux handling
From: Rob Herring @ 2020-05-28 19:59 UTC (permalink / raw)
To: Guido Günther
Cc: Laurent Pinchart, David Airlie, Daniel Vetter, Shawn Guo,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Andrzej Hajda, Sam Ravnborg, Anson Huang, Leonard Crestez,
Lucas Stach, Peng Fan, Robert Chiras, dri-devel, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <9884c56219e9bdbeec179c27ea2b734dbb5f1289.1589548223.git.agx@sigxcpu.org>
On Fri, May 15, 2020 at 03:12:12PM +0200, Guido Günther wrote:
> No need to encode the SoC specifics in the bridge driver. For the
> imx8mq we can use the mux-input-bridge.
You can't just change bindings like this. You'd still have to support
the "old" way. But IMO, this way is the right way.
>
> Signed-off-by: Guido Günther <agx@sigxcpu.org>
> ---
> .../devicetree/bindings/display/bridge/nwl-dsi.yaml | 6 ------
> 1 file changed, 6 deletions(-)
^ permalink raw reply
* Re: [RFC PATCH 4/6] drm/bridge/nwl-dsi: Drop mux handling
From: Rob Herring @ 2020-05-28 19:57 UTC (permalink / raw)
To: Guido Günther
Cc: Laurent Pinchart, David Airlie, Daniel Vetter, Shawn Guo,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Andrzej Hajda, Sam Ravnborg, Anson Huang, Leonard Crestez,
Lucas Stach, Peng Fan, Robert Chiras, dri-devel, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <951688795f969ebcbf9fb3c38065ccce6f488235.1589548223.git.agx@sigxcpu.org>
On Fri, May 15, 2020 at 03:12:13PM +0200, Guido Günther wrote:
> This will be handled via the mux-input-bridge.
You can't do this. What happens booting a kernel with this change and an
un-modified dtb? You just broke it.
>
> Signed-off-by: Guido Günther <agx@sigxcpu.org>
> ---
> drivers/gpu/drm/bridge/Kconfig | 1 -
> drivers/gpu/drm/bridge/nwl-dsi.c | 61 --------------------------------
> 2 files changed, 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index 3886c0f41bdd..11444f841e35 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -78,7 +78,6 @@ config DRM_NWL_MIPI_DSI
> select DRM_PANEL_BRIDGE
> select GENERIC_PHY_MIPI_DPHY
> select MFD_SYSCON
> - select MULTIPLEXER
> select REGMAP_MMIO
> help
> This enables the Northwest Logic MIPI DSI Host controller as
> diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c
> index b14d725bf609..8839f333f39c 100644
> --- a/drivers/gpu/drm/bridge/nwl-dsi.c
> +++ b/drivers/gpu/drm/bridge/nwl-dsi.c
> @@ -12,7 +12,6 @@
> #include <linux/math64.h>
> #include <linux/mfd/syscon.h>
> #include <linux/module.h>
> -#include <linux/mux/consumer.h>
> #include <linux/of.h>
> #include <linux/of_platform.h>
> #include <linux/phy/phy.h>
> @@ -44,9 +43,6 @@ enum transfer_direction {
> DSI_PACKET_RECEIVE,
> };
>
> -#define NWL_DSI_ENDPOINT_LCDIF 0
> -#define NWL_DSI_ENDPOINT_DCSS 1
> -
> struct nwl_dsi_plat_clk_config {
> const char *id;
> struct clk *clk;
> @@ -94,7 +90,6 @@ struct nwl_dsi {
> struct reset_control *rst_esc;
> struct reset_control *rst_dpi;
> struct reset_control *rst_pclk;
> - struct mux_control *mux;
>
> /* DSI clocks */
> struct clk *phy_ref_clk;
> @@ -1018,14 +1013,6 @@ static int nwl_dsi_parse_dt(struct nwl_dsi *dsi)
> }
> dsi->tx_esc_clk = clk;
>
> - dsi->mux = devm_mux_control_get(dsi->dev, NULL);
> - if (IS_ERR(dsi->mux)) {
> - ret = PTR_ERR(dsi->mux);
> - if (ret != -EPROBE_DEFER)
> - DRM_DEV_ERROR(dsi->dev, "Failed to get mux: %d\n", ret);
> - return ret;
> - }
> -
> base = devm_platform_ioremap_resource(pdev, 0);
> if (IS_ERR(base))
> return PTR_ERR(base);
> @@ -1073,47 +1060,6 @@ static int nwl_dsi_parse_dt(struct nwl_dsi *dsi)
> return 0;
> }
>
> -static int nwl_dsi_select_input(struct nwl_dsi *dsi)
> -{
> - struct device_node *remote;
> - u32 use_dcss = 1;
> - int ret;
> -
> - remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
> - NWL_DSI_ENDPOINT_LCDIF);
> - if (remote) {
> - use_dcss = 0;
> - } else {
> - remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
> - NWL_DSI_ENDPOINT_DCSS);
> - if (!remote) {
> - DRM_DEV_ERROR(dsi->dev,
> - "No valid input endpoint found\n");
> - return -EINVAL;
> - }
> - }
> -
> - DRM_DEV_INFO(dsi->dev, "Using %s as input source\n",
> - (use_dcss) ? "DCSS" : "LCDIF");
> - ret = mux_control_try_select(dsi->mux, use_dcss);
> - if (ret < 0)
> - DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret);
> -
> - of_node_put(remote);
> - return ret;
> -}
You could however make these functions generic for any bridge to use.
Define a function that checks for mux-control property and if found sets
up the mux (IIRC, there's already a concept of a default state). That
should be callable from somewhere generic too.
Rob
^ permalink raw reply
* Re: [PATCH v3 09/10] dmaengine: dw: Introduce max burst length hw config
From: Serge Semin @ 2020-05-28 19:53 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Vinod Koul, Viresh Kumar, Dan Williams,
Alexey Malahov, Thomas Bogendoerfer, Arnd Bergmann, Rob Herring,
linux-mips, devicetree, dmaengine, linux-kernel
In-Reply-To: <20200528154022.3reghhjcd4dnsr3g@mobilestation>
On Thu, May 28, 2020 at 06:40:22PM +0300, Serge Semin wrote:
> On Thu, May 28, 2020 at 05:52:24PM +0300, Andy Shevchenko wrote:
> > On Wed, May 27, 2020 at 01:50:20AM +0300, Serge Semin wrote:
> > > IP core of the DW DMA controller may be synthesized with different
> > > max burst length of the transfers per each channel. According to Synopsis
> > > having the fixed maximum burst transactions length may provide some
> > > performance gain. At the same time setting up the source and destination
> > > multi size exceeding the max burst length limitation may cause a serious
> > > problems. In our case the DMA transaction just hangs up. In order to fix
> > > this lets introduce the max burst length platform config of the DW DMA
> > > controller device and don't let the DMA channels configuration code
> > > exceed the burst length hardware limitation.
> > >
> > > Note the maximum burst length parameter can be detected either in runtime
> > > from the DWC parameter registers or from the dedicated DT property.
> > > Depending on the IP core configuration the maximum value can vary from
> > > channel to channel so by overriding the channel slave max_burst capability
> > > we make sure a DMA consumer will get the channel-specific max burst
> > > length.
> >
> > ...
> >
> > > static void dwc_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
> > > {
> > > + struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
> > >
> >
>
> > Perhaps,
> >
> > /* DesignWare DMA supports burst value from 0 */
> > caps->min_burst = 0;
>
> Regarding min_burst being zero. I don't fully understand what it means.
> It means no burst or burst with minimum length or what?
> In fact DW DMA burst length starts from 1. Remember the burst-length run-time
> parameter we were arguing about? Anyway the driver makes sure that both
> 0 and 1 requested burst length are setup as burst length of 1 in the
> CTLx.SRC_MSIZE, CTLx.DST_MSIZE fields.
>
> I agree with the rest of your comments below.
>
> -Sergey
>
> >
It would be also better to initialize the dw->dma.min_burst field instead
of setting caps->min_burst in the dwc_caps callback, since the min burst length
can't vary from channel to channel and it will be copied to the caps->min_burst
field anyway in the dma_get_slave_caps() method.
-Sergey
^ permalink raw reply
* [PATCH] ARM: dts: imx6qdl-gw54xx: allow boot firmware to set eth1 MAC
From: Tim Harvey @ 2020-05-28 19:53 UTC (permalink / raw)
To: Shawn Guo, Sascha Hauer
Cc: Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
devicetree, linux-arm-kernel, linux-kernel, Rob Herring,
Tim Harvey
The GW54xx has a PCIe based GbE as the 2nd ethernet device. The
boot firmware will populate the local-mac-address field of the
device aliased to ethernet1 thus adding the PCIe device to
dt allows boot firmware to set its MAC address.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index c40583d..5527f95 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -9,6 +9,7 @@
/ {
/* these are used by bootloader for disabling nodes */
aliases {
+ ethernet1 = ð1;
led0 = &led0;
led1 = &led1;
led2 = &led2;
@@ -398,6 +399,23 @@
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ pcie@0,0,0 {
+ reg = <0x0000 0 0 0 0>;
+
+ pcie@1,0,0 {
+ reg = <0x0000 0 0 0 0>;
+
+ pcie@2,8,0 {
+ reg = <0x4000 0 0 0 0>;
+
+ eth1: pcie@8,0,0 {
+ reg = <0x0000 0 0 0 0>;
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ };
+ };
+ };
};
&pwm1 {
--
2.7.4
^ permalink raw reply related
* [PATCH] ARM: dts: imx6qdl-gw53xx: allow boot firmware to set eth1 MAC
From: Tim Harvey @ 2020-05-28 19:53 UTC (permalink / raw)
To: Shawn Guo, Sascha Hauer
Cc: Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
devicetree, linux-arm-kernel, linux-kernel, Rob Herring,
Tim Harvey
The GW53xx has a PCIe based GbE as the 2nd ethernet device. The
boot firmware will populate the local-mac-address field of the
device aliased to ethernet1 thus adding the PCIe device to
dt allows boot firmware to set its MAC address.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 8942bec..6601d07 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -8,6 +8,7 @@
/ {
/* these are used by bootloader for disabling nodes */
aliases {
+ ethernet1 = ð1;
led0 = &led0;
led1 = &led1;
led2 = &led2;
@@ -341,6 +342,23 @@
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ pcie@0,0,0 {
+ reg = <0x0000 0 0 0 0>;
+
+ pcie@1,0,0 {
+ reg = <0x0000 0 0 0 0>;
+
+ pcie@2,4,0 {
+ reg = <0x2000 0 0 0 0>;
+
+ eth1: pcie@4,0,0 {
+ reg = <0x0000 0 0 0 0>;
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ };
+ };
+ };
};
&pwm2 {
--
2.7.4
^ permalink raw reply related
* Re: [RFC PATCH 1/6] dt-bindings: display/bridge: Add binding for input mux bridge
From: Rob Herring @ 2020-05-28 19:48 UTC (permalink / raw)
To: Guido Günther
Cc: Laurent Pinchart, David Airlie, Daniel Vetter, Shawn Guo,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Andrzej Hajda, Sam Ravnborg, Anson Huang, Leonard Crestez,
Lucas Stach, Peng Fan, Robert Chiras, dri-devel, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <14a44a664f40584ffa25c1764aab5ebf97809c71.1589548223.git.agx@sigxcpu.org>
On Fri, May 15, 2020 at 03:12:10PM +0200, Guido Günther wrote:
> The bridge allows to select the input source via a mux controller.
>
> Signed-off-by: Guido Günther <agx@sigxcpu.org>
> ---
> .../display/bridge/mux-input-bridge.yaml | 123 ++++++++++++++++++
> 1 file changed, 123 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/mux-input-bridge.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/mux-input-bridge.yaml b/Documentation/devicetree/bindings/display/bridge/mux-input-bridge.yaml
> new file mode 100644
> index 000000000000..4029cf63ee5c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/mux-input-bridge.yaml
> @@ -0,0 +1,123 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/mux-input-bridge.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: DRM input source selection via multiplexer
DRM is not a hardware thing.
The graph binding is already designed to support muxing. Generally,
multiple endpoints on an input node is a mux. So either the device with
the input ports knows how to select the input, or you just need a
mux-control property for the port to have some other device implement
the control.
You could do it like you have below. That would be appropriate if
there's a separate h/w device controlling the muxing. Say for example
some board level device controlled by i2c.
Rob
^ permalink raw reply
* Re: [PATCH 5/5] dt-bindings: timer: Add CLINT bindings
From: Sean Anderson @ 2020-05-28 19:37 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: anup, Anup Patel, Paul Walmsley, aou, robh+dt, daniel.lezcano,
tglx, devicetree, Damien Le Moal, linux-kernel, Atish Patra,
Alistair Francis, linux-riscv
In-Reply-To: <mhng-0995a264-b39c-4790-9aa5-b8c598b43ffd@palmerdabbelt-glaptop1>
On 5/26/20 8:32 PM, Palmer Dabbelt wrote:
> On Thu, 21 May 2020 23:29:36 PDT (-0700), seanga2@gmail.com wrote:
>> On 5/22/20 1:54 AM, Anup Patel wrote:
>>> On Fri, May 22, 2020 at 1:35 AM Sean Anderson <seanga2@gmail.com> wrote:
>>>>
>>>> On 5/21/20 9:45 AM, Anup Patel wrote:
>>>>> +Required properties:
>>>>> +- compatible : "sifive,clint-1.0.0" and a string identifying the actual
>>>>> + detailed implementation in case that specific bugs need to be worked around.
>>>>
>>>> Should the "riscv,clint0" compatible string be documented here? This
>>>
>>> Yes, I forgot to add this compatible string. I will add in v2.
>>>
>>>> peripheral is not really specific to sifive, as it is present in most
>>>> rocket-chip cores.
>>>
>>> I agree that CLINT is present in a lot of non-SiFive RISC-V SOCs and
>>> FPGAs but this IP is only documented as part of SiFive FU540 SOC.
>>> (Refer, https://static.dev.sifive.com/FU540-C000-v1.0.pdf)
>>>
>>> The RISC-V foundation should host the CLINT spec independently
>>> under https://github.com/riscv and make CLINT spec totally open.
>>>
>>> For now, I have documented it just like PLIC DT bindings found at:
>>> Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt
>>
>> The PLIC seems to have its own RISC-V-sponsored documentation [1] which
>> was split off from the older privileged specs. By your logic above,
>> should it be renamed to riscv,plic0.txt (with a corresponding change in
>> the documented compatible strings)?
>>
>> [1] https://github.com/riscv/riscv-plic-spec
>
> Let's propose tagging that PLIC spec as v1.0.0 in the platform spec group, but
> I don't see a reason why that wouldn't be viable. Assuming that's all OK, we
> can start calling this a RISC-V PLIC (in addition to a SiFive PLIC, as they'll
> be compatible).
Is there a version anyewhere in that spec? I looked around a bit and
couldn't find one.
>>>
>>> If RISC-V maintainers agree then I will document it as "RISC-V CLINT".
>>>
>>> @Palmer ?? @Paul ??
>
> The CLINT is a SiFive spec. It has open source RTL so it's been implemented in
> other designs, but it's not a RISC-V spec. The CLIC, which is a superset of
> the CLINT, is a RISC-V spec. IIRC it's not finished yet (it's the fast
> interrupts task group), but presumably we should have a "riscv,clic-2.0.0" (or
> whatever it ends up being called) compat string to go along with the
> specification.
The rocket chip is a Chips Alliance project on github; presumably the
"proper" compatibility string would be something like
"chips-alliance,clint"? Alternatively, it is already referred to as
"riscv,clint0" in U-Boot, following the pattern of the plic.
--Sean
^ permalink raw reply
* Re: [PATCH v2 03/10] dt-bindings: serial: renesas,scifa: Document r8a7742 bindings
From: Rob Herring @ 2020-05-28 19:36 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Linus Walleij, linux-renesas-soc, linux-mmc, linux-serial,
Greg Kroah-Hartman, Vinod Koul, Prabhakar, devicetree, dmaengine,
Magnus Damm, Geert Uytterhoeven, Ulf Hansson, linux-kernel,
linux-gpio
In-Reply-To: <20200512222056.GA7267@bogus>
On Tue, May 12, 2020 at 05:20:56PM -0500, Rob Herring wrote:
> On Sun, 3 May 2020 22:46:47 +0100, Lad Prabhakar wrote:
> > RZ/G1H (R8A7742) SoC also has the R-Car gen2 compatible SCIFA ports,
> > so document the SoC specific bindings.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > Documentation/devicetree/bindings/serial/renesas,scifa.yaml | 1 +
> > 1 file changed, 1 insertion(+)
> >
>
> Acked-by: Rob Herring <robh@kernel.org>
Geert asked me to apply this one, so I have now.
Rob
^ permalink raw reply
* Re: [PATCH v2 2/7] dt-bindings: usb: atmel: Update DT bindings documentation for sam9x60
From: Rob Herring @ 2020-05-28 19:26 UTC (permalink / raw)
To: cristian.birsan
Cc: linux-kernel, ludovic.desroches, alexandre.belloni,
linux-arm-kernel, balbi, robh+dt, devicetree, mark.rutland,
linux-usb, gregkh, nicolas.ferre
In-Reply-To: <20200515111631.31210-3-cristian.birsan@microchip.com>
On Fri, 15 May 2020 14:16:26 +0300, cristian.birsan@microchip.com wrote:
> From: Cristian Birsan <cristian.birsan@microchip.com>
>
> Add sam9x60 binding.
>
> Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com>
> ---
> Documentation/devicetree/bindings/usb/atmel-usb.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 3/5] dt-bindings: PCI: uniphier: Add iATU register description
From: Rob Herring @ 2020-05-28 19:25 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: linux-kernel, Gustavo Pimentel, devicetree, Lorenzo Pieralisi,
Bjorn Helgaas, Masahiro Yamada, Rob Herring, linux-arm-kernel,
Jassi Brar, linux-pci, Jingoo Han, Masami Hiramatsu
In-Reply-To: <1589536743-6684-4-git-send-email-hayashi.kunihiko@socionext.com>
On Fri, 15 May 2020 18:59:01 +0900, Kunihiko Hayashi wrote:
> In the dt-bindings, "atu" reg-names is required to get the register space
> for iATU in Synopsis DWC version 4.80 or later.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
> Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 2/4] dt-binding: phy: convert ti,omap-usb2 to YAML
From: Rob Herring @ 2020-05-28 19:24 UTC (permalink / raw)
To: Roger Quadros; +Cc: kishon, b-liu, devicetree, vigneshr, nsekhar
In-Reply-To: <20200515080518.26870-3-rogerq@ti.com>
On Fri, May 15, 2020 at 11:05:16AM +0300, Roger Quadros wrote:
> Move ti,omap-usb2 to its own YAML schema.
>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
> .../devicetree/bindings/phy/ti,omap-usb2.yaml | 73 +++++++++++++++++++
> .../devicetree/bindings/phy/ti-phy.txt | 37 ----------
> 2 files changed, 73 insertions(+), 37 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml b/Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml
> new file mode 100644
> index 000000000000..ecfb28f714ea
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml
> @@ -0,0 +1,73 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/ti,omap-usb2.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: OMAP USB2 PHY
> +
> +maintainers:
> + - Kishon Vijay Abraham I <kishon@ti.com>
> + - Roger Quadros <rogerq@ti.com>
> +
> +properties:
> + compatible:
> + anyOf:
Only 1 entry, don't need anyOf.
> + - items:
> + - enum:
> + - "ti,dra7x-usb2"
> + - "ti,dra7x-usb2-phy2"
> + - "ti,am654-usb2"
> + - enum:
> + - "ti,omap-usb2"
> +
> + reg:
> + maxItems: 1
> + description: address and length of the register set for the device.
Drop. That's every 'reg'.
> +
> + '#phy-cells':
> + description:
> + Number of cells in a PHY specifier. The meaning of all those
> + cells is defined by the binding for the phy node. The PHY
> + provider can use the values in cells to find the appropriate PHY.
Yes, and this is a phy bindings, so you need to define the value.
> + $ref: /schemas/types.yaml#/definitions/uint32
#*-cells already has a type.
> +
> + clocks:
> + minItems: 1
> + items:
> + - description: wakeup clock
> + - description: reference clock
> +
> + clock-names:
> + minItems: 1
> + items:
> + - const: "wkupclk"
> + - const: "refclk"
Don't need quotes.
> +
> + syscon-phy-power:
> + description:
> + phandle/offset pair. Phandle to the system control module
> + register offset to power on/off the PHY.
> +
> + ctrl-module:
> + description:
> + (deprecated) phandle of the control module used by PHY driver
> + to power on the PHY. Use syscon-phy-power instead.
These 2 need a type reference.
> +
> +required:
> + - compatible
> + - reg
> + - '#phy-cells'
> + - clocks
> + - clock-names
> +
> +examples:
> + - |
> + usb0_phy: phy@4100000 {
> + compatible = "ti,am654-usb2", "ti,omap-usb2";
> + reg = <0x0 0x4100000 0x0 0x54>;
> + syscon-phy-power = <&scm_conf 0x4000>;
> + clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
> + clock-names = "wkupclk", "refclk";
> + #phy-cells = <0>;
> + };
> diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt
> index 8f93c3b694a7..60c9d0ac75e6 100644
> --- a/Documentation/devicetree/bindings/phy/ti-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
> @@ -27,43 +27,6 @@ omap_control_usb: omap-control-usb@4a002300 {
> reg-names = "otghs_control";
> };
>
> -OMAP USB2 PHY
> -
> -Required properties:
> - - compatible: Should be "ti,omap-usb2"
> - Should be "ti,dra7x-usb2" for the 1st instance of USB2 PHY on
> - DRA7x
> - Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY
> - in DRA7x
> - Should be "ti,am654-usb2" for the USB2 PHYs on AM654.
> - - reg : Address and length of the register set for the device.
> - - #phy-cells: determine the number of cells that should be given in the
> - phandle while referencing this phy.
> - - clocks: a list of phandles and clock-specifier pairs, one for each entry in
> - clock-names.
> - - clock-names: should include:
> - * "wkupclk" - wakeup clock.
> - * "refclk" - reference clock (optional).
> -
> -Deprecated properties:
> - - ctrl-module : phandle of the control module used by PHY driver to power on
> - the PHY.
> -
> -Recommended properies:
> -- syscon-phy-power : phandle/offset pair. Phandle to the system control
> - module and the register offset to power on/off the PHY.
> -
> -This is usually a subnode of ocp2scp to which it is connected.
> -
> -usb2phy@4a0ad080 {
> - compatible = "ti,omap-usb2";
> - reg = <0x4a0ad080 0x58>;
> - ctrl-module = <&omap_control_usb>;
> - #phy-cells = <0>;
> - clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
> - clock-names = "wkupclk", "refclk";
> -};
> -
> TI PIPE3 PHY
>
> Required properties:
> --
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
>
^ permalink raw reply
* [PATCH 2/4] dt-bindings: pinctrl: Document optional BCM7211 wake-up interrupts
From: Florian Fainelli @ 2020-05-28 19:21 UTC (permalink / raw)
To: linux-kernel
Cc: Florian Fainelli, Linus Walleij, Rob Herring, Ray Jui,
Scott Branden,
maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...,
Nicolas Saenz Julienne, Stefan Wahren, Geert Uytterhoeven,
Matti Vaittinen, open list:PIN CONTROL SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
In-Reply-To: <20200528192112.26123-1-f.fainelli@gmail.com>
BCM7211 supports wake-up interrupts in the form of optional interrupt
lines, one per bank, plus the "all banks" interrupt line.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt
index dfc67b90591c..5682b2010e50 100644
--- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt
+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt
@@ -16,7 +16,9 @@ Required properties:
second cell is used to specify optional parameters:
- bit 0 specifies polarity (0 for normal, 1 for inverted)
- interrupts : The interrupt outputs from the controller. One interrupt per
- individual bank followed by the "all banks" interrupt.
+ individual bank followed by the "all banks" interrupt. For BCM7211, an
+ additional set of per-bank interrupt line and an "all banks" wake-up
+ interrupt may be specified.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells : Should be 2.
The first cell is the GPIO number.
--
2.17.1
^ permalink raw reply related
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