* Re: [PATCH v4 03/11] dmaengine: Introduce min burst length capability
From: Andy Shevchenko @ 2020-05-29 12:07 UTC (permalink / raw)
To: Serge Semin
Cc: Vinod Koul, Viresh Kumar, Dan Williams, Serge Semin,
Alexey Malahov, Thomas Bogendoerfer, Arnd Bergmann, Rob Herring,
linux-mips, devicetree, dmaengine, linux-kernel
In-Reply-To: <20200528222401.26941-4-Sergey.Semin@baikalelectronics.ru>
On Fri, May 29, 2020 at 01:23:53AM +0300, Serge Semin wrote:
> Some hardware aside from default 0/1 may have greater minimum burst
> transactions length constraints. Here we introduce the DMA device
> and slave capability, which if required can be initialized by the DMA
> engine driver with the device-specific value.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
>
> ---
>
> Changelog v3:
> - This is a new patch created as a result of the discussion with Vinud and
> Andy in the framework of DW DMA burst and LLP capabilities.
> ---
> drivers/dma/dmaengine.c | 1 +
> include/linux/dmaengine.h | 4 ++++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
> index d31076d9ef25..b332ffe52780 100644
> --- a/drivers/dma/dmaengine.c
> +++ b/drivers/dma/dmaengine.c
> @@ -590,6 +590,7 @@ int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
> caps->src_addr_widths = device->src_addr_widths;
> caps->dst_addr_widths = device->dst_addr_widths;
> caps->directions = device->directions;
> + caps->min_burst = device->min_burst;
> caps->max_burst = device->max_burst;
> caps->residue_granularity = device->residue_granularity;
> caps->descriptor_reuse = device->descriptor_reuse;
> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
> index e1c03339918f..0c7403b27133 100644
> --- a/include/linux/dmaengine.h
> +++ b/include/linux/dmaengine.h
> @@ -465,6 +465,7 @@ enum dma_residue_granularity {
> * Since the enum dma_transfer_direction is not defined as bit flag for
> * each type, the dma controller should set BIT(<TYPE>) and same
> * should be checked by controller as well
> + * @min_burst: min burst capability per-transfer
> * @max_burst: max burst capability per-transfer
> * @cmd_pause: true, if pause is supported (i.e. for reading residue or
> * for resume later)
> @@ -478,6 +479,7 @@ struct dma_slave_caps {
> u32 src_addr_widths;
> u32 dst_addr_widths;
> u32 directions;
> + u32 min_burst;
> u32 max_burst;
> bool cmd_pause;
> bool cmd_resume;
> @@ -769,6 +771,7 @@ struct dma_filter {
> * Since the enum dma_transfer_direction is not defined as bit flag for
> * each type, the dma controller should set BIT(<TYPE>) and same
> * should be checked by controller as well
> + * @min_burst: min burst capability per-transfer
> * @max_burst: max burst capability per-transfer
> * @residue_granularity: granularity of the transfer residue reported
> * by tx_status
> @@ -839,6 +842,7 @@ struct dma_device {
> u32 src_addr_widths;
> u32 dst_addr_widths;
> u32 directions;
> + u32 min_burst;
> u32 max_burst;
> bool descriptor_reuse;
> enum dma_residue_granularity residue_granularity;
> --
> 2.26.2
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: Fwd: [PATCH v3 2/2] media: cec: i2c: ch7322: Add ch7322 CEC controller driver
From: Hans Verkuil @ 2020-05-29 12:01 UTC (permalink / raw)
To: Jeff Chase, linux-media; +Cc: mchehab, robh+dt, devicetree
In-Reply-To: <CALTkaQ0NLgjS7H7De=7jy9jRG1xMFSbzdmxrFNerNU+o1rRzpg@mail.gmail.com>
On 29/05/2020 08:10, Jeff Chase wrote:
> (Resending as plain text, sorry)
>
>> +static int ch7322_cec_adap_enable(struct cec_adapter *adap, bool enable)
>> +{
>> + struct ch7322 *ch7322 = cec_get_drvdata(adap);
>> + int ret;
>> +
>> + if (enable)
>> + ret = ch7322_unmask_interrupt(ch7322);
>> + else
>> + ret = ch7322_mask_interrupt(ch7322);
>> +
>> + return ret;
>> +}
>> +
>
> I just realized that doing this here is broken -- the driver depends
> on the interrupt to detect when the physical address changes. I could
> mask only the tx/rx interrupt here instead but that is starting to
> feel a bit pointless.
Ah, OK. Just drop this then.
>
> I haven't looked into the cec notifier mechanism yet but would it be
> better to try to use that instead if possible and just ignore this
> device's physical address detection? Then I could do more of a proper
> reset in this enable op. But I'm not sure if I can properly associate
> the device with an HDMI port on my platform unless I make some changes
> to coreboot.
I don't think this is useful: it's nice to have the CEC adapter do the
physical address detection.
One question about that though: if there is no physical address, can this
driver still transmit CEC messages? Specifically Image View On. This is
important to wake up displays that pull down the HPD when in standby.
The easiest way to test this is with a Pulse-Eight CEC adapter.
See also the section "CEC Without HPD" here:
https://hverkuil.home.xs4all.nl/cec-status.txt
Regards,
Hans
^ permalink raw reply
* Re: [PATCH v8 04/10] OPP: Add support for parsing interconnect bandwidth
From: Sibi Sankar @ 2020-05-29 11:39 UTC (permalink / raw)
To: Viresh Kumar
Cc: Georgi Djakov, vireshk, nm, sboyd, rjw, saravanak, mka, robh+dt,
rnayak, bjorn.andersson, vincent.guittot, jcrouse, evgreen,
linux-pm, devicetree, linux-kernel
In-Reply-To: <20200529044437.5wmbbews2vn66dia@vireshk-i7>
On 2020-05-29 10:14, Viresh Kumar wrote:
> On 12-05-20, 15:53, Georgi Djakov wrote:
>> struct dev_pm_opp *_opp_allocate(struct opp_table *table)
>> {
>> struct dev_pm_opp *opp;
>> - int count, supply_size;
>> + int supply_count, supply_size, icc_size;
>>
>> /* Allocate space for at least one supply */
>> - count = table->regulator_count > 0 ? table->regulator_count : 1;
>> - supply_size = sizeof(*opp->supplies) * count;
>> + supply_count = table->regulator_count > 0 ? table->regulator_count :
>> 1;
>> + supply_size = sizeof(*opp->supplies) * supply_count;
>> + icc_size = sizeof(*opp->bandwidth) * table->path_count;
>>
>> /* allocate new OPP node and supplies structures */
>> - opp = kzalloc(sizeof(*opp) + supply_size, GFP_KERNEL);
>> + opp = kzalloc(sizeof(*opp) + supply_size + icc_size, GFP_KERNEL);
>> +
>> if (!opp)
>> return NULL;
>>
>> /* Put the supplies at the end of the OPP structure as an empty
>> array */
>> opp->supplies = (struct dev_pm_opp_supply *)(opp + 1);
>> + opp->bandwidth = (struct dev_pm_opp_icc_bw *)(opp->supplies +
>> supply_count);
>> INIT_LIST_HEAD(&opp->node);
>
> Added this delta here.
>
> diff --git a/drivers/opp/core.c b/drivers/opp/core.c
> index 7302f2631f8d..dfbd3d10410c 100644
> --- a/drivers/opp/core.c
> +++ b/drivers/opp/core.c
> @@ -1330,7 +1330,8 @@ struct dev_pm_opp *_opp_allocate(struct opp_table
> *table)
>
> /* Put the supplies at the end of the OPP structure as an empty
> array */
> opp->supplies = (struct dev_pm_opp_supply *)(opp + 1);
> - opp->bandwidth = (struct dev_pm_opp_icc_bw *)(opp->supplies +
> supply_count);
> + if (icc_size)
> + opp->bandwidth = (struct dev_pm_opp_icc_bw
> *)(opp->supplies + supply_count);
nice catch!
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
> INIT_LIST_HEAD(&opp->node);
>
> return opp;
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply
* Re: [PATCH 04/12] dt-bindings: irqchip: ti,sci-intr: Update bindings to drop the usage of gic as parent
From: Lokesh Vutla @ 2020-05-29 11:13 UTC (permalink / raw)
To: Rob Herring
Cc: Marc Zyngier, Thomas Gleixner, Nishanth Menon, Tero Kristo,
Santosh Shilimkar, Linux ARM Mailing List, Sekhar Nori,
Grygorii Strashko, Peter Ujfalusi, Device Tree Mailing List
In-Reply-To: <20200528221406.GA769073@bogus>
Hi Rob,
[..snip..]
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
>> index 1a8718f8855d..8b56b2de1c73 100644
>> --- a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
>> @@ -44,15 +44,17 @@ Required Properties:
>> 4: If intr supports level triggered interrupts.
>> - interrupt-controller: Identifies the node as an interrupt controller
>> - #interrupt-cells: Specifies the number of cells needed to encode an
>> - interrupt source. The value should be 2.
>> - First cell should contain the TISCI device ID of source
>> - Second cell should contain the interrupt source offset
>> - within the device.
>> + interrupt source. The value should be 1.
>> + First cell should contain interrupt router input number
>> + as specified by hardware.
>> - ti,sci: Phandle to TI-SCI compatible System controller node.
>> -- ti,sci-dst-id: TISCI device ID of the destination IRQ controller.
>> -- ti,sci-rm-range-girq: Array of TISCI subtype ids representing the host irqs
>> - assigned to this interrupt router. Each subtype id
>> - corresponds to a range of host irqs.
>> +- ti,sci-dev-id: TISCI device id of interrupt controller.
>> +- ti,interrupt-ranges: Set of triplets containing ranges that convert
>> + the INTR output interrupt numbers to parent's
>> + interrupt number. Each triplet has following entries:
>> + - First entry specifies the base for intr output irq
>> + - Second entry specifies the base for parent irqs
>> + - Third entry specifies the limit
>
> Humm, sounds like what interrupt-map does.
IIUC, for every irq translation there should be an entry in interrupt-map
property. These Controllers has interrupts ranging from 32, 256 and more. It
might be odd to have 256 entries in the interrupt map no? Also there are
multiple interrupt controllers which need such translations.
Thanks and regards,
Lokesh
^ permalink raw reply
* Re: [PATCH v2 1/9] dt-bindings: mmc: Convert sdhci-pxa to json-schema
From: Ulf Hansson @ 2020-05-29 11:10 UTC (permalink / raw)
To: Rob Herring, Lubomir Rintel
Cc: Alessandro Zummo, Alexandre Belloni, Bartosz Golaszewski,
Daniel Lezcano, Jason Cooper, Linus Walleij, Marc Zyngier,
Thomas Gleixner, DTML, Linux Kernel Mailing List
In-Reply-To: <20200528225445.GB815881@bogus>
On Fri, 29 May 2020 at 00:54, Rob Herring <robh@kernel.org> wrote:
>
> On Wed, May 27, 2020 at 09:59:10AM +0200, Ulf Hansson wrote:
> > On Thu, 21 May 2020 at 11:14, Lubomir Rintel <lkundrak@v3.sk> wrote:
> > >
> > > Convert the sdhci-pxa binding to DT schema format using json-schema.
> > >
> > > At the same time, fix a couple of issues with the examples discovered by
> > > the validation tool -- a semicolon instead of a comma and wrong node names.
> > >
> > > Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> >
> > Rob, are you fine with this v2? I am intending to queue it up via my
> > mmc tree, unless you want to pick it?
>
> You can take it if you drop my name from 'maintainers'. Ideally, it
> shouldn't be your name either (should have called it 'owners'
> instead...).
Patch amended!
>
> Reviewed-by: Rob Herring <robh@kernel.org>
Thanks, applied to my next branch!
Kind regards
Uffe
^ permalink raw reply
* Re: [PATCH v3 1/5] regulator: Allow regulators to verify enabled during enable()
From: Mark Brown @ 2020-05-29 10:54 UTC (permalink / raw)
To: Sumit Semwal
Cc: agross, bjorn.andersson, lgirdwood, robh+dt, nishakumari,
linux-arm-msm, linux-kernel, devicetree, kgunda, rnayak
In-Reply-To: <20200528154625.17742-2-sumit.semwal@linaro.org>
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On Thu, May 28, 2020 at 09:16:21PM +0530, Sumit Semwal wrote:
> + while (time_remaining > 0) {
> + /* We've already waited for enable_time above;
> + * so we can start with immediate check of the
> + * status of the regulator.
> + */
> + if (rdev->desc->ops->is_enabled(rdev))
> + break;
I'd expect to prefer to get_status() if it's available.
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^ permalink raw reply
* Re: [PATCH] dt-bindings: sound: tlv320adcx140: Fix dt-binding-check issue
From: Mark Brown @ 2020-05-29 10:51 UTC (permalink / raw)
To: Dan Murphy
Cc: lgirdwood, perex, tiwai, robh, alsa-devel, linux-kernel,
devicetree
In-Reply-To: <20200528144711.18065-1-dmurphy@ti.com>
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On Thu, May 28, 2020 at 09:47:11AM -0500, Dan Murphy wrote:
> Fix dt-binding-check issue
Please submit patches using subject lines reflecting the style for the
subsystem, this makes it easier for people to identify relevant patches.
Look at what existing commits in the area you're changing are doing and
make sure your subject lines visually resemble what they're doing.
There's no need to resubmit to fix this alone.
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* Re: [PATCH v4 09/11] dmaengine: dw: Initialize min_burst capability
From: Serge Semin @ 2020-05-29 10:51 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Vinod Koul, Viresh Kumar, Dan Williams,
Alexey Malahov, Thomas Bogendoerfer, Arnd Bergmann, Rob Herring,
linux-mips, devicetree, dmaengine, linux-kernel
In-Reply-To: <20200529105009.GH1634618@smile.fi.intel.com>
On Fri, May 29, 2020 at 01:50:09PM +0300, Andy Shevchenko wrote:
> On Fri, May 29, 2020 at 01:41:19PM +0300, Serge Semin wrote:
> > On Fri, May 29, 2020 at 01:29:02PM +0300, Andy Shevchenko wrote:
> > > On Fri, May 29, 2020 at 01:25:15PM +0300, Andy Shevchenko wrote:
> > > > On Fri, May 29, 2020 at 01:23:59AM +0300, Serge Semin wrote:
>
> ...
>
> > > > > /* DMA capabilities */
> > > > > + dw->dma.min_burst = 1;
> > > >
> > > > Perhaps then relaxed maximum, like
> > > >
> > > > dw->dma.max_burst = 256;
> > > >
> > > > (channels will update this)
> > > >
> > > > ?
> >
> > > And forgot to mention that perhaps we need a definitions for both.
> >
> > By "definitions for both" do you mean a macro with corresponding parameter
> > definition like it's done for the max burst length in the next patch?
> > Something like this:
> > --- include/linux/platform_data/dma-dw.h
> > +++ include/linux/platform_data/dma-dw.h
> > +#define DW_DMA_MIN_BURST 1
> > +#define DW_DMA_MAX_BURST 256
> >
> > ?
>
> Yes!
Ok. Good idea. I'll do that. Thanks.
-Sergey
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply
* Re: [PATCH v3 1/5] regulator: Allow regulators to verify enabled during enable()
From: Mark Brown @ 2020-05-29 10:50 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Sumit Semwal, agross, lgirdwood, robh+dt, nishakumari,
linux-arm-msm, linux-kernel, devicetree, kgunda, rnayak
In-Reply-To: <20200529013743.GL279327@builder.lan>
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On Thu, May 28, 2020 at 06:37:43PM -0700, Bjorn Andersson wrote:
> On Thu 28 May 08:46 PDT 2020, Sumit Semwal wrote:
> > Some regulators might need to verify that they have indeed been enabled
> > after the enable() call is made and enable_time delay has passed.
> > _regulator_enable_delay(delay);
> My interpretation of "enable_time" (i.e. the value of delay) is that it
> denotes the maximum time it will take for the regulator to turn on, and
Right.
> the purpose of this patch is to be able to handle cases where we can
> poll the hardware to see if it completed earlier.
Is that it? From the changelog it sounded like this was a workaround
for broken hardware not an attempt at optimization.
> So I think you should flip the meaning of your two variables around,
> making "delay" the total time to sleep and the newly introduced
> "poll_enabled_time" the interval at which you check if the hardware
> finished early.
Yes.
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* Re: [PATCH v4 09/11] dmaengine: dw: Initialize min_burst capability
From: Andy Shevchenko @ 2020-05-29 10:50 UTC (permalink / raw)
To: Serge Semin
Cc: Serge Semin, Vinod Koul, Viresh Kumar, Dan Williams,
Alexey Malahov, Thomas Bogendoerfer, Arnd Bergmann, Rob Herring,
linux-mips, devicetree, dmaengine, linux-kernel
In-Reply-To: <20200529104119.qrqoptp5iz5hs56r@mobilestation>
On Fri, May 29, 2020 at 01:41:19PM +0300, Serge Semin wrote:
> On Fri, May 29, 2020 at 01:29:02PM +0300, Andy Shevchenko wrote:
> > On Fri, May 29, 2020 at 01:25:15PM +0300, Andy Shevchenko wrote:
> > > On Fri, May 29, 2020 at 01:23:59AM +0300, Serge Semin wrote:
...
> > > > /* DMA capabilities */
> > > > + dw->dma.min_burst = 1;
> > >
> > > Perhaps then relaxed maximum, like
> > >
> > > dw->dma.max_burst = 256;
> > >
> > > (channels will update this)
> > >
> > > ?
>
> > And forgot to mention that perhaps we need a definitions for both.
>
> By "definitions for both" do you mean a macro with corresponding parameter
> definition like it's done for the max burst length in the next patch?
> Something like this:
> --- include/linux/platform_data/dma-dw.h
> +++ include/linux/platform_data/dma-dw.h
> +#define DW_DMA_MIN_BURST 1
> +#define DW_DMA_MAX_BURST 256
>
> ?
Yes!
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v4 09/11] dmaengine: dw: Initialize min_burst capability
From: Serge Semin @ 2020-05-29 10:41 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Vinod Koul, Viresh Kumar, Dan Williams,
Alexey Malahov, Thomas Bogendoerfer, Arnd Bergmann, Rob Herring,
linux-mips, devicetree, dmaengine, linux-kernel
In-Reply-To: <20200529102902.GG1634618@smile.fi.intel.com>
On Fri, May 29, 2020 at 01:29:02PM +0300, Andy Shevchenko wrote:
> On Fri, May 29, 2020 at 01:25:15PM +0300, Andy Shevchenko wrote:
> > On Fri, May 29, 2020 at 01:23:59AM +0300, Serge Semin wrote:
> > > According to the DW APB DMAC data book the minimum burst transaction
> > > length is 1 and it's true for any version of the controller since
> > > isn't parametrised in the coreAssembler so can't be changed at the
> > > IP-core synthesis stage. Let's initialise the min_burst member of the
> > > DMA controller descriptor so the DMA clients could use it to properly
> > > optimize the DMA requests.
>
> ...
>
> > > /* DMA capabilities */
> >
> > > + dw->dma.min_burst = 1;
> >
> > Perhaps then relaxed maximum, like
> >
> > dw->dma.max_burst = 256;
> >
> > (channels will update this)
> >
> > ?
>
> And forgot to mention that perhaps we need a definitions for both.
By "definitions for both" do you mean a macro with corresponding parameter
definition like it's done for the max burst length in the next patch?
Something like this:
--- include/linux/platform_data/dma-dw.h
+++ include/linux/platform_data/dma-dw.h
+#define DW_DMA_MIN_BURST 1
+#define DW_DMA_MAX_BURST 256
?
-Sergey
>
> > > dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
> > > dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply
* Re: [PATCH v4 09/11] dmaengine: dw: Initialize min_burst capability
From: Andy Shevchenko @ 2020-05-29 10:29 UTC (permalink / raw)
To: Serge Semin
Cc: Vinod Koul, Viresh Kumar, Dan Williams, Serge Semin,
Alexey Malahov, Thomas Bogendoerfer, Arnd Bergmann, Rob Herring,
linux-mips, devicetree, dmaengine, linux-kernel
In-Reply-To: <20200529102515.GD1634618@smile.fi.intel.com>
On Fri, May 29, 2020 at 01:25:15PM +0300, Andy Shevchenko wrote:
> On Fri, May 29, 2020 at 01:23:59AM +0300, Serge Semin wrote:
> > According to the DW APB DMAC data book the minimum burst transaction
> > length is 1 and it's true for any version of the controller since
> > isn't parametrised in the coreAssembler so can't be changed at the
> > IP-core synthesis stage. Let's initialise the min_burst member of the
> > DMA controller descriptor so the DMA clients could use it to properly
> > optimize the DMA requests.
...
> > /* DMA capabilities */
>
> > + dw->dma.min_burst = 1;
>
> Perhaps then relaxed maximum, like
>
> dw->dma.max_burst = 256;
>
> (channels will update this)
>
> ?
And forgot to mention that perhaps we need a definitions for both.
> > dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
> > dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v4 11/11] dmaengine: dw: Initialize max_sg_nents capability
From: Andy Shevchenko @ 2020-05-29 10:27 UTC (permalink / raw)
To: Serge Semin
Cc: Vinod Koul, Viresh Kumar, Dan Williams, Serge Semin,
Alexey Malahov, Thomas Bogendoerfer, Arnd Bergmann, Rob Herring,
linux-mips, devicetree, dmaengine, linux-kernel
In-Reply-To: <20200528222401.26941-12-Sergey.Semin@baikalelectronics.ru>
On Fri, May 29, 2020 at 01:24:01AM +0300, Serge Semin wrote:
> Multi-block support provides a way to map the kernel-specific SG-table so
> the DW DMA device would handle it as a whole instead of handling the
> SG-list items or so called LLP block items one by one. So if true LLP
> list isn't supported by the DW DMA engine, then soft-LLP mode will be
> utilized to load and execute each LLP-block one by one. The soft-LLP mode
> of the DMA transactions execution might not work well for some DMA
> consumers like SPI due to its Tx and Rx buffers inter-dependency. Let's
> initialize the max_sg_nents DMA channels capability based on the nollp
> flag state. If it's true, no hardware accelerated LLP is available and
> max_sg_nents should be set with 1, which means that the DMA engine
> can handle only a single SG list entry at a time. If noLLP is set to
> false, then hardware accelerated LLP is supported and the DMA engine
> can handle infinite number of SG entries in a single DMA transaction.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
>
> ---
>
> Changelog v3:
> - This is a new patch created as a result of the discussion with Vinud and
> Andy in the framework of DW DMA burst and LLP capabilities.
>
> Changelog v4:
> - Use explicit if-else statement when assigning the max_sg_nents field.
> ---
> drivers/dma/dw/core.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
> index 60ef779fc5e0..b76eee75fde8 100644
> --- a/drivers/dma/dw/core.c
> +++ b/drivers/dma/dw/core.c
> @@ -1059,6 +1059,18 @@ static void dwc_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
> struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
>
> caps->max_burst = dwc->max_burst;
> +
> + /*
> + * It might be crucial for some devices to have the hardware
> + * accelerated multi-block transfers supported, aka LLPs in DW DMAC
> + * notation. So if LLPs are supported then max_sg_nents is set to
> + * zero which means unlimited number of SG entries can be handled in a
> + * single DMA transaction, otherwise it's just one SG entry.
> + */
> + if (dwc->nollp)
> + caps->max_sg_nents = 1;
> + else
> + caps->max_sg_nents = 0;
> }
>
> int do_dma_probe(struct dw_dma_chip *chip)
> --
> 2.26.2
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v4 10/11] dmaengine: dw: Introduce max burst length hw config
From: Andy Shevchenko @ 2020-05-29 10:27 UTC (permalink / raw)
To: Serge Semin
Cc: Vinod Koul, Viresh Kumar, Dan Williams, Serge Semin,
Alexey Malahov, Thomas Bogendoerfer, Arnd Bergmann, Rob Herring,
linux-mips, devicetree, dmaengine, linux-kernel
In-Reply-To: <20200528222401.26941-11-Sergey.Semin@baikalelectronics.ru>
On Fri, May 29, 2020 at 01:24:00AM +0300, Serge Semin wrote:
> IP core of the DW DMA controller may be synthesized with different
> max burst length of the transfers per each channel. According to Synopsis
> having the fixed maximum burst transactions length may provide some
> performance gain. At the same time setting up the source and destination
> multi size exceeding the max burst length limitation may cause a serious
> problems. In our case the DMA transaction just hangs up. In order to fix
> this lets introduce the max burst length platform config of the DW DMA
> controller device and don't let the DMA channels configuration code
> exceed the burst length hardware limitation.
>
> Note the maximum burst length parameter can be detected either in runtime
> from the DWC parameter registers or from the dedicated DT property.
> Depending on the IP core configuration the maximum value can vary from
> channel to channel so by overriding the channel slave max_burst capability
> we make sure a DMA consumer will get the channel-specific max burst
> length.
LGTM, but consider comment to previous patch (in that case perhaps definition
of min and max should be moved there).
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
>
> ---
>
> Changelog v2:
> - Rearrange SoBs.
> - Discard dwc_get_maxburst() accessor. It's enough to have a clamping
> guard against exceeding the hardware max burst limitation.
>
> Changelog v3:
> - Override the slave channel max_burst capability instead of calculating
> the minimum value of max burst lengths and setting the DMA-device
> generic capability.
>
> Changelog v4:
> - Clamp the dst and src burst lengths in the generic dwc_config() method
> instead of doing that in the encode_maxburst() callback.
> - Define max_burst with u32 type in struct dw_dma_platform_data.
> - Perform of_property_read_u32_array() directly into the platform data
> max_burst member.
> ---
> drivers/dma/dw/core.c | 10 ++++++++++
> drivers/dma/dw/of.c | 5 +++++
> drivers/dma/dw/regs.h | 2 ++
> include/linux/platform_data/dma-dw.h | 4 ++++
> 4 files changed, 21 insertions(+)
>
> diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
> index a8cebb1dbb68..60ef779fc5e0 100644
> --- a/drivers/dma/dw/core.c
> +++ b/drivers/dma/dw/core.c
> @@ -791,6 +791,11 @@ static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
>
> memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
>
> + dwc->dma_sconfig.src_maxburst =
> + clamp(dwc->dma_sconfig.src_maxburst, 0U, dwc->max_burst);
> + dwc->dma_sconfig.dst_maxburst =
> + clamp(dwc->dma_sconfig.dst_maxburst, 0U, dwc->max_burst);
> +
> dw->encode_maxburst(dwc, &dwc->dma_sconfig.src_maxburst);
> dw->encode_maxburst(dwc, &dwc->dma_sconfig.dst_maxburst);
>
> @@ -1051,7 +1056,9 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
>
> static void dwc_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
> {
> + struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
>
> + caps->max_burst = dwc->max_burst;
> }
>
> int do_dma_probe(struct dw_dma_chip *chip)
> @@ -1194,9 +1201,12 @@ int do_dma_probe(struct dw_dma_chip *chip)
> dwc->nollp =
> (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0 ||
> (dwc_params >> DWC_PARAMS_HC_LLP & 0x1) == 1;
> + dwc->max_burst =
> + (0x4 << (dwc_params >> DWC_PARAMS_MSIZE & 0x7));
> } else {
> dwc->block_size = pdata->block_size;
> dwc->nollp = !pdata->multi_block[i];
> + dwc->max_burst = pdata->max_burst[i] ?: DW_DMA_MAX_BURST;
> }
> }
>
> diff --git a/drivers/dma/dw/of.c b/drivers/dma/dw/of.c
> index 9e27831dee32..1474b3817ef4 100644
> --- a/drivers/dma/dw/of.c
> +++ b/drivers/dma/dw/of.c
> @@ -98,6 +98,11 @@ struct dw_dma_platform_data *dw_dma_parse_dt(struct platform_device *pdev)
> pdata->multi_block[tmp] = 1;
> }
>
> + if (of_property_read_u32_array(np, "snps,max-burst-len", pdata->max_burst,
> + nr_channels)) {
> + memset32(pdata->max_burst, DW_DMA_MAX_BURST, nr_channels);
> + }
> +
> if (!of_property_read_u32(np, "snps,dma-protection-control", &tmp)) {
> if (tmp > CHAN_PROTCTL_MASK)
> return NULL;
> diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
> index 1ab840b06e79..76654bd13c1a 100644
> --- a/drivers/dma/dw/regs.h
> +++ b/drivers/dma/dw/regs.h
> @@ -126,6 +126,7 @@ struct dw_dma_regs {
> /* Bitfields in DWC_PARAMS */
> #define DWC_PARAMS_MBLK_EN 11 /* multi block transfer */
> #define DWC_PARAMS_HC_LLP 13 /* set LLP register to zero */
> +#define DWC_PARAMS_MSIZE 16 /* max group transaction size */
>
> /* bursts size */
> enum dw_dma_msize {
> @@ -284,6 +285,7 @@ struct dw_dma_chan {
> /* hardware configuration */
> unsigned int block_size;
> bool nollp;
> + u32 max_burst;
>
> /* custom slave configuration */
> struct dw_dma_slave dws;
> diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h
> index f3eaf9ec00a1..29c484da2979 100644
> --- a/include/linux/platform_data/dma-dw.h
> +++ b/include/linux/platform_data/dma-dw.h
> @@ -12,6 +12,7 @@
>
> #define DW_DMA_MAX_NR_MASTERS 4
> #define DW_DMA_MAX_NR_CHANNELS 8
> +#define DW_DMA_MAX_BURST 256
>
> /**
> * struct dw_dma_slave - Controller-specific information about a slave
> @@ -42,6 +43,8 @@ struct dw_dma_slave {
> * @data_width: Maximum data width supported by hardware per AHB master
> * (in bytes, power of 2)
> * @multi_block: Multi block transfers supported by hardware per channel.
> + * @max_burst: Maximum value of burst transaction size supported by hardware
> + * per channel (in units of CTL.SRC_TR_WIDTH/CTL.DST_TR_WIDTH).
> * @protctl: Protection control signals setting per channel.
> */
> struct dw_dma_platform_data {
> @@ -56,6 +59,7 @@ struct dw_dma_platform_data {
> unsigned char nr_masters;
> unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
> unsigned char multi_block[DW_DMA_MAX_NR_CHANNELS];
> + u32 max_burst[DW_DMA_MAX_NR_CHANNELS];
> #define CHAN_PROTCTL_PRIVILEGED BIT(0)
> #define CHAN_PROTCTL_BUFFERABLE BIT(1)
> #define CHAN_PROTCTL_CACHEABLE BIT(2)
> --
> 2.26.2
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v4 09/11] dmaengine: dw: Initialize min_burst capability
From: Andy Shevchenko @ 2020-05-29 10:25 UTC (permalink / raw)
To: Serge Semin
Cc: Vinod Koul, Viresh Kumar, Dan Williams, Serge Semin,
Alexey Malahov, Thomas Bogendoerfer, Arnd Bergmann, Rob Herring,
linux-mips, devicetree, dmaengine, linux-kernel
In-Reply-To: <20200528222401.26941-10-Sergey.Semin@baikalelectronics.ru>
On Fri, May 29, 2020 at 01:23:59AM +0300, Serge Semin wrote:
> According to the DW APB DMAC data book the minimum burst transaction
> length is 1 and it's true for any version of the controller since
> isn't parametrised in the coreAssembler so can't be changed at the
> IP-core synthesis stage. Let's initialise the min_burst member of the
> DMA controller descriptor so the DMA clients could use it to properly
> optimize the DMA requests.
> @@ -1229,6 +1229,7 @@ int do_dma_probe(struct dw_dma_chip *chip)
> dw->dma.device_issue_pending = dwc_issue_pending;
>
> /* DMA capabilities */
> + dw->dma.min_burst = 1;
Perhaps then relaxed maximum, like
dw->dma.max_burst = 256;
(channels will update this)
?
> dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
> dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
> dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
> --
> 2.26.2
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v5 05/16] spi: dw: Add SPI Rx-done wait method to DMA-based transfer
From: Andy Shevchenko @ 2020-05-29 10:20 UTC (permalink / raw)
To: Serge Semin
Cc: Serge Semin, Mark Brown, Grant Likely, Linus Walleij, Feng Tang,
Alan Cox, Vinod Koul, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Arnd Bergmann, Rob Herring,
linux-mips, devicetree, linux-spi, linux-kernel
In-Reply-To: <20200529101328.bfoyyvmwm5gfflxv@mobilestation>
On Fri, May 29, 2020 at 01:13:28PM +0300, Serge Semin wrote:
> On Fri, May 29, 2020 at 12:46:48PM +0300, Andy Shevchenko wrote:
> > On Fri, May 29, 2020 at 06:59:03AM +0300, Serge Semin wrote:
> > > Having any data left in the Rx FIFO after the DMA engine claimed it has
> > > finished all DMA transactions is an abnormal situation, since the DW SPI
> > > controller driver expects to have all the data being fetched and placed
> > > into the SPI Rx buffer at that moment. In case if this has happened we
> > > assume that DMA engine still may be doing the data fetching, thus we give
> > > it sometime to finish. If after a short period of time the data is still
> > > left in the Rx FIFO, the driver will give up waiting and return an error
> > > indicating that the SPI controller/DMA engine must have hung up or failed
> > > at some point of doing their duties.
> >
> > ...
> >
> > > +static int dw_spi_dma_wait_rx_done(struct dw_spi *dws)
> > > +{
> > > + int retry = WAIT_RETRIES;
> > > + struct spi_delay delay;
> > > + unsigned long ns, us;
> > > + u32 nents;
> > > +
> > > + /*
> > > + * It's unlikely that DMA engine is still doing the data fetching, but
> > > + * if it's let's give it some reasonable time. The timeout calculation
> > > + * is based on the synchronous APB/SSI reference clock rate, on a
> > > + * number of data entries left in the Rx FIFO, times a number of clock
> > > + * periods normally needed for a single APB read/write transaction
> > > + * without PREADY signal utilized (which is true for the DW APB SSI
> > > + * controller).
> > > + */
> > > + nents = dw_readl(dws, DW_SPI_RXFLR);
> >
>
> > > + ns = NSEC_PER_SEC / dws->max_freq * 4 * nents;
> >
> > I think we may slightly increase precision by writing this like
> >
> > ns = 4 * NSEC_PER_SEC / dws->max_freq * nents;
>
> Good point. Although both 4 and NSEC_PER_SEC are signed. The later is
> 1000000000L. Formally speaking on x32 systems (4 * 1000 000 000L) equals
> to a negative value. Though overflow still won't happen so the result will
> be correct. Anyway to be on a safe side it would be better to use an explicit
> unsigned literal:
>
> + ns = 4U * NSEC_PER_SEC / dws->max_freq * nents;
Yes, right.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH 04/12] dt-bindings: irqchip: ti,sci-intr: Update bindings to drop the usage of gic as parent
From: Marc Zyngier @ 2020-05-29 10:18 UTC (permalink / raw)
To: Lokesh Vutla
Cc: Rob Herring, Thomas Gleixner, Nishanth Menon, Tero Kristo,
Santosh Shilimkar, Linux ARM Mailing List, Sekhar Nori,
Grygorii Strashko, Peter Ujfalusi, Device Tree Mailing List
In-Reply-To: <f803f646-2a55-4f15-9682-1dc616d7c714@ti.com>
On 2020-05-29 11:14, Lokesh Vutla wrote:
> Hi Rob,
>
> On 29/05/20 3:44 am, Rob Herring wrote:
>> On Wed, May 20, 2020 at 06:14:46PM +0530, Lokesh Vutla wrote:
>>> Drop the firmware related dt-bindings and use the hardware specified
>>> interrupt numbers within Interrupt Router. This ensures interrupt
>>> router
>>> DT node need not assume any interrupt parent type.
>>
>> I didn't like this binding to begin with, but now you're breaking
>> compatibility.
>
> Yes, I do agree that this change is breaking backward compatibility.
> But IMHO,
> this does cleanup of firmware specific properties from DT. Since this
> is not
> deployed out yet in the wild market, I took the leverage of breaking
> backward
> compatibility. Before accepting these changes from firmware team, I did
> discuss[0] with Marc on this topic.
And I assume that should anyone complain about the kernel being broken
because they have an old firmware, you'll be OK with the patches being
reverted, right?
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* Re: [PATCH 04/12] dt-bindings: irqchip: ti,sci-intr: Update bindings to drop the usage of gic as parent
From: Lokesh Vutla @ 2020-05-29 10:14 UTC (permalink / raw)
To: Rob Herring
Cc: Marc Zyngier, Thomas Gleixner, Nishanth Menon, Tero Kristo,
Santosh Shilimkar, Linux ARM Mailing List, Sekhar Nori,
Grygorii Strashko, Peter Ujfalusi, Device Tree Mailing List
In-Reply-To: <20200528221406.GA769073@bogus>
Hi Rob,
On 29/05/20 3:44 am, Rob Herring wrote:
> On Wed, May 20, 2020 at 06:14:46PM +0530, Lokesh Vutla wrote:
>> Drop the firmware related dt-bindings and use the hardware specified
>> interrupt numbers within Interrupt Router. This ensures interrupt router
>> DT node need not assume any interrupt parent type.
>
> I didn't like this binding to begin with, but now you're breaking
> compatibility.
Yes, I do agree that this change is breaking backward compatibility. But IMHO,
this does cleanup of firmware specific properties from DT. Since this is not
deployed out yet in the wild market, I took the leverage of breaking backward
compatibility. Before accepting these changes from firmware team, I did
discuss[0] with Marc on this topic.
>
>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>> ---
>> .../interrupt-controller/ti,sci-intr.txt | 31 ++++++++++---------
>> 1 file changed, 16 insertions(+), 15 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
>> index 1a8718f8855d..8b56b2de1c73 100644
>> --- a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
>> @@ -44,15 +44,17 @@ Required Properties:
>> 4: If intr supports level triggered interrupts.
>> - interrupt-controller: Identifies the node as an interrupt controller
>> - #interrupt-cells: Specifies the number of cells needed to encode an
>> - interrupt source. The value should be 2.
>> - First cell should contain the TISCI device ID of source
>> - Second cell should contain the interrupt source offset
>> - within the device.
>> + interrupt source. The value should be 1.
>> + First cell should contain interrupt router input number
>> + as specified by hardware.
>> - ti,sci: Phandle to TI-SCI compatible System controller node.
>> -- ti,sci-dst-id: TISCI device ID of the destination IRQ controller.
>> -- ti,sci-rm-range-girq: Array of TISCI subtype ids representing the host irqs
>> - assigned to this interrupt router. Each subtype id
>> - corresponds to a range of host irqs.
>> +- ti,sci-dev-id: TISCI device id of interrupt controller.
>> +- ti,interrupt-ranges: Set of triplets containing ranges that convert
>> + the INTR output interrupt numbers to parent's
>> + interrupt number. Each triplet has following entries:
>> + - First entry specifies the base for intr output irq
>> + - Second entry specifies the base for parent irqs
>> + - Third entry specifies the limit
>
> Humm, sounds like what interrupt-map does.
Okay, Ill look at it.
[0]
https://lore.kernel.org/linux-arm-kernel/2331f04eacee3b06cc152fc609225233@www.loen.fr/
Thanks and regards,
Lokesh
^ permalink raw reply
* Re: [PATCH v5 05/16] spi: dw: Add SPI Rx-done wait method to DMA-based transfer
From: Serge Semin @ 2020-05-29 10:13 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Mark Brown, Grant Likely, Linus Walleij, Feng Tang,
Alan Cox, Vinod Koul, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Arnd Bergmann, Rob Herring,
linux-mips, devicetree, linux-spi, linux-kernel
In-Reply-To: <20200529094648.GY1634618@smile.fi.intel.com>
On Fri, May 29, 2020 at 12:46:48PM +0300, Andy Shevchenko wrote:
> On Fri, May 29, 2020 at 06:59:03AM +0300, Serge Semin wrote:
> > Having any data left in the Rx FIFO after the DMA engine claimed it has
> > finished all DMA transactions is an abnormal situation, since the DW SPI
> > controller driver expects to have all the data being fetched and placed
> > into the SPI Rx buffer at that moment. In case if this has happened we
> > assume that DMA engine still may be doing the data fetching, thus we give
> > it sometime to finish. If after a short period of time the data is still
> > left in the Rx FIFO, the driver will give up waiting and return an error
> > indicating that the SPI controller/DMA engine must have hung up or failed
> > at some point of doing their duties.
>
> ...
>
> > +static int dw_spi_dma_wait_rx_done(struct dw_spi *dws)
> > +{
> > + int retry = WAIT_RETRIES;
> > + struct spi_delay delay;
> > + unsigned long ns, us;
> > + u32 nents;
> > +
> > + /*
> > + * It's unlikely that DMA engine is still doing the data fetching, but
> > + * if it's let's give it some reasonable time. The timeout calculation
> > + * is based on the synchronous APB/SSI reference clock rate, on a
> > + * number of data entries left in the Rx FIFO, times a number of clock
> > + * periods normally needed for a single APB read/write transaction
> > + * without PREADY signal utilized (which is true for the DW APB SSI
> > + * controller).
> > + */
> > + nents = dw_readl(dws, DW_SPI_RXFLR);
>
> > + ns = NSEC_PER_SEC / dws->max_freq * 4 * nents;
>
> I think we may slightly increase precision by writing this like
>
> ns = 4 * NSEC_PER_SEC / dws->max_freq * nents;
Good point. Although both 4 and NSEC_PER_SEC are signed. The later is
1000000000L. Formally speaking on x32 systems (4 * 1000 000 000L) equals
to a negative value. Though overflow still won't happen so the result will
be correct. Anyway to be on a safe side it would be better to use an explicit
unsigned literal:
+ ns = 4U * NSEC_PER_SEC / dws->max_freq * nents;
-Sergey
>
>
> > + if (ns <= NSEC_PER_USEC) {
> > + delay.unit = SPI_DELAY_UNIT_NSECS;
> > + delay.value = ns;
> > + } else {
> > + us = DIV_ROUND_UP(ns, NSEC_PER_USEC);
> > + delay.unit = SPI_DELAY_UNIT_USECS;
> > + delay.value = clamp_val(us, 0, USHRT_MAX);
> > + }
> > +
> > + while (dw_spi_dma_rx_busy(dws) && retry--)
> > + spi_delay_exec(&delay, NULL);
> > +
> > + if (retry < 0) {
> > + dev_err(&dws->master->dev, "Rx hanged up\n");
> > + return -EIO;
> > + }
> > +
> > + return 0;
> > +}
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply
* Re: [PATCH v3 1/9] dt-bindings: atmel-tcb: convert bindings to json-schema
From: Sebastian Andrzej Siewior @ 2020-05-29 10:13 UTC (permalink / raw)
To: Rob Herring, devicetree
Cc: Daniel Lezcano, Thomas Gleixner, Nicolas Ferre, kamel.bouhara,
linux-arm-kernel, linux-kernel, Alexandre Belloni
In-Reply-To: <20200506080554.283177-2-alexandre.belloni@bootlin.com>
Rob, could you please bless the DT parts of this series? Daniel Lezcano
asked for the blessing in:
https://lkml.kernel.org/r/f0feb409-11fb-08de-cc06-216a16de994a@linaro.org
On 2020-05-06 10:05:46 [+0200], Alexandre Belloni wrote:
> Convert Atmel Timer Counter Blocks bindings to DT schema format using
> json-schema.
>
> Also move it out of mfd as it is not and has never been related to mfd.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
> Cc: Rob Herring <robh+dt@kernel.org>
>
> Changes in v3:
> - Moved the child node documentation to the parent documentation
>
> Changes in v2:
> - Rebased on v5.7-rc1
> - Moved the binding documentation to its proper place
> - Added back the atmel,tcb-timer child node documentation
>
>
> .../devicetree/bindings/mfd/atmel-tcb.txt | 56 --------
> .../soc/microchip/atmel,at91rm9200-tcb.yaml | 126 ++++++++++++++++++
Sebastian
^ permalink raw reply
* Re: [RFC v3 0/3] Re-introduce TX FIFO resize for larger EP bursting
From: Greg KH @ 2020-05-29 10:12 UTC (permalink / raw)
To: Wesley Cheng
Cc: robh+dt, bjorn.andersson, balbi, agross, linux-kernel,
linux-arm-msm, devicetree, linux-usb
In-Reply-To: <1590630363-3934-1-git-send-email-wcheng@codeaurora.org>
On Wed, May 27, 2020 at 06:46:00PM -0700, Wesley Cheng wrote:
> Changes in V3:
> - Removed "Reviewed-by" tags
> - Renamed series back to RFC
> - Modified logic to ensure that fifo_size is reset if we pass the minimum
> threshold. Tested with binding multiple FDs requesting 6 FIFOs.
>
> Changes in V2:
> - Modified TXFIFO resizing logic to ensure that each EP is reserved a
> FIFO.
> - Removed dev_dbg() prints and fixed typos from patches
> - Added some more description on the dt-bindings commit message
>
> Currently, there is no functionality to allow for resizing the TXFIFOs, and
> relying on the HW default setting for the TXFIFO depth. In most cases, the
> HW default is probably sufficient, but for USB compositions that contain
> multiple functions that require EP bursting, the default settings
> might not be enough. Also to note, the current SW will assign an EP to a
> function driver w/o checking to see if the TXFIFO size for that particular
> EP is large enough. (this is a problem if there are multiple HW defined
> values for the TXFIFO size)
>
> It is mentioned in the SNPS databook that a minimum of TX FIFO depth = 3
> is required for an EP that supports bursting. Otherwise, there may be
> frequent occurences of bursts ending. For high bandwidth functions,
> such as data tethering (protocols that support data aggregation), mass
> storage, and media transfer protocol (over FFS), the bMaxBurst value can be
> large, and a bigger TXFIFO depth may prove to be beneficial in terms of USB
> throughput. (which can be associated to system access latency, etc...) It
> allows for a more consistent burst of traffic, w/o any interruptions, as
> data is readily available in the FIFO.
>
> With testing done using the mass storage function driver, the results show
> that with a larger TXFIFO depth, the bandwidth increased significantly.
Why is this still a "RFC" series? That implies you don't want this
applied...
^ permalink raw reply
* Re: [PATCH v5 03/16] spi: dw: Locally wait for the DMA transactions completion
From: Serge Semin @ 2020-05-29 9:56 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Mark Brown, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Arnd Bergmann, Feng Tang,
Rob Herring, linux-mips, devicetree, linux-spi,
Linux Kernel Mailing List
In-Reply-To: <20200529092610.GX1634618@smile.fi.intel.com>
On Fri, May 29, 2020 at 12:26:10PM +0300, Andy Shevchenko wrote:
> On Fri, May 29, 2020 at 11:12:04AM +0300, Serge Semin wrote:
> > On Fri, May 29, 2020 at 10:55:32AM +0300, Andy Shevchenko wrote:
> > > On Fri, May 29, 2020 at 7:02 AM Serge Semin
> > > <Sergey.Semin@baikalelectronics.ru> wrote:
> > > >
> > > > Even if DMA transactions are finished it doesn't mean that the SPI
> > > > transfers are also completed. It's specifically concerns the Tx-only
> > > > SPI transfers, since there might be data left in the SPI Tx FIFO after
> > > > the DMA engine notifies that the Tx DMA procedure is done. In order to
> > > > completely fix the problem first the driver has to wait for the DMA
> > > > transaction completion, then for the corresponding SPI operations to be
> > > > finished. In this commit we implement the former part of the solution.
> > > >
> > > > Note we can't just move the SPI operations wait procedure to the DMA
> > > > completion callbacks, since these callbacks might be executed in the
> > > > tasklet context (and they will be in case of the DW DMA). In case of
> > > > slow SPI bus it can cause significant system performance drop.
> > >
> >
> > > I read commit message, I read the code. What's going on here since you
> > > repeated xfer_completion (and its wait routine) from SPI core and I'm
> > > wondering what happened to it? Why we are not calling
> > > spi_finalize_current_transfer()?
> >
> > We discussed that in v4. You complained about using ndelay() for slow SPI bus,
> > which may cause too long atomic context execution. We agreed. Since we can't wait
> > in the tasklet context and using a dedicated kernel thread for waiting would be too
> > much, Me and Mark agreed, that
>
> > even if it causes us of the local wait-function
> > re-implementation the best approach would be not to use the generic
> > spi_transfer_wait() method, but instead wait for the DMA transactions locally
> > in the DMA driver and just return 0 from the transfer_one callback indicating
> > that the SPI transfer is finished and there is no need for SPI core to wait. As
> > a lot of DMA-based SPI drivers do.
>
> The above is missed in the commit message.
>
> > If you don't understand what the commit message says, just say so. I'll
> > reformulate it.
>
> See above. A bit of elaboration would be good. Thank you!
Agreed. I'll create a more detailed commit description, which will have the
info you cited.
-Sergey
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply
* Re: [PATCH v5 01/16] spi: dw: Set xfer effective_speed_hz
From: Serge Semin @ 2020-05-29 9:49 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Serge Semin, Mark Brown, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Arnd Bergmann, Feng Tang,
Andy Shevchenko, Rob Herring, linux-mips, devicetree, linux-spi,
linux-kernel
In-Reply-To: <afdf414a-df95-b130-85e8-cda5bf4e9405@cogentembedded.com>
On Fri, May 29, 2020 at 11:49:12AM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 29.05.2020 6:58, Serge Semin wrote:
>
> > Seeing DW APB SSI controller doesn't support setting the exactly
> > requested SPI bus frequency, but only a rounded frequency determined
> > by means of the odd-numbered half-worded reference clock divider,
> > it would be good tune the SPI core up and initialize the current
> ^ to?
Thanks! I'll fix it in the next patchset version.
-Sergey
>
> > transfer effective_speed_hz. By doing so the core will be able to
> > execute the xfer-related delays with better accuracy.
> >
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> > Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Feng Tang <feng.tang@intel.com>
> > Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: linux-mips@vger.kernel.org
> > Cc: devicetree@vger.kernel.org
> [...]
>
> MBR, Sergei
^ permalink raw reply
* Re: [PATCH 0/3] MIPS: Loongson64: Initial LS7A PCH support
From: Huacai Chen @ 2020-05-29 9:47 UTC (permalink / raw)
To: Jiaxun Yang
Cc: Marc Zyngier, Thomas Bogendoerfer, Rob Herring, open list:MIPS,
devicetree, LKML
In-Reply-To: <82608FDB-FEF8-45FA-85D7-236B46F906B7@flygoat.com>
Hi, Jiaxun,
On Fri, May 29, 2020 at 12:37 PM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
>
>
> 于 2020年5月29日 GMT+08:00 下午12:13:36, Huacai Chen <chenhc@lemote.com> 写到:
> >Hi, Jiaxun,
> >
> >On Fri, May 29, 2020 at 11:45 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> >>
> >> With this series, LS7A and Loongson-3A4000 is finally supported
> >> note that this series should depend on irqchip support[1], which
> >> is likely to get merged soon.
> >>
> >> Thanks.
> >>
> >> [1]: https://lkml.org/lkml/2020/5/16/72
> >>
> >> Jiaxun Yang (3):
> >> dt-bindings: mips: Document two Loongson generic boards
> >> MIPS: Loongson64: DeviceTree for LS7A PCH
> >> MIPS: Loongson64:Load LS7A dtbs
> >>
> >> .../bindings/mips/loongson/devices.yaml | 8 +
> >> arch/mips/boot/dts/loongson/Makefile | 5 +-
> >> .../dts/loongson/loongson3-r4-package.dtsi | 74 +++++++
> >> .../dts/loongson/loongson3_4core_ls7a.dts | 25 +++
> >> .../boot/dts/loongson/loongson3_r4_ls7a.dts | 10 +
> >> arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 185 ++++++++++++++++++
> >> .../asm/mach-loongson64/builtin_dtbs.h | 2 +
> >> arch/mips/loongson64/env.c | 56 +++---
> >> 8 files changed, 342 insertions(+), 23 deletions(-)
> >> create mode 100644 arch/mips/boot/dts/loongson/loongson3-r4-package.dtsi
> >> create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_ls7a.dts
> >> create mode 100644 arch/mips/boot/dts/loongson/loongson3_r4_ls7a.dts
> >> create mode 100644 arch/mips/boot/dts/loongson/ls7a-pch.dtsi
> >I think the naming can be like this: Old processor (Loongson 3A R1~R3)
> >use loongson64c_ prefix instead of loongson3, new processor (Loongson
> >3A R4) use loongson64g_ prefix instead of loongson3_r4, and
> >Loongson-2K use loongson64r_ prefix, this makes them consistent with
> >their PRID definitions.
>
>
> DeviceTree bindings have stable ABI. Although they're currently
> only used internally in Kernel. I don't think it's a good idea
> to rename existing bindings.
I think consistency is important, and this renaming doesn't break anything.
>
> Also, Loongson64C/64G/64R never came to a part of Loongson's
> official naming. I doubt if end users will recognize these names.
>
> I'd prefer keep naming as is. It's really not a big deal.
>
> Thanks.
>
>
> >
> >>
> >> --
> >> 2.27.0.rc0
> >>
>
> --
> Jiaxun Yang
^ permalink raw reply
* Re: [PATCH v5 05/16] spi: dw: Add SPI Rx-done wait method to DMA-based transfer
From: Andy Shevchenko @ 2020-05-29 9:46 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Grant Likely, Linus Walleij, Feng Tang, Alan Cox,
Vinod Koul, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Arnd Bergmann, Rob Herring,
linux-mips, devicetree, linux-spi, linux-kernel
In-Reply-To: <20200529035915.20790-6-Sergey.Semin@baikalelectronics.ru>
On Fri, May 29, 2020 at 06:59:03AM +0300, Serge Semin wrote:
> Having any data left in the Rx FIFO after the DMA engine claimed it has
> finished all DMA transactions is an abnormal situation, since the DW SPI
> controller driver expects to have all the data being fetched and placed
> into the SPI Rx buffer at that moment. In case if this has happened we
> assume that DMA engine still may be doing the data fetching, thus we give
> it sometime to finish. If after a short period of time the data is still
> left in the Rx FIFO, the driver will give up waiting and return an error
> indicating that the SPI controller/DMA engine must have hung up or failed
> at some point of doing their duties.
...
> +static int dw_spi_dma_wait_rx_done(struct dw_spi *dws)
> +{
> + int retry = WAIT_RETRIES;
> + struct spi_delay delay;
> + unsigned long ns, us;
> + u32 nents;
> +
> + /*
> + * It's unlikely that DMA engine is still doing the data fetching, but
> + * if it's let's give it some reasonable time. The timeout calculation
> + * is based on the synchronous APB/SSI reference clock rate, on a
> + * number of data entries left in the Rx FIFO, times a number of clock
> + * periods normally needed for a single APB read/write transaction
> + * without PREADY signal utilized (which is true for the DW APB SSI
> + * controller).
> + */
> + nents = dw_readl(dws, DW_SPI_RXFLR);
> + ns = NSEC_PER_SEC / dws->max_freq * 4 * nents;
I think we may slightly increase precision by writing this like
ns = 4 * NSEC_PER_SEC / dws->max_freq * nents;
> + if (ns <= NSEC_PER_USEC) {
> + delay.unit = SPI_DELAY_UNIT_NSECS;
> + delay.value = ns;
> + } else {
> + us = DIV_ROUND_UP(ns, NSEC_PER_USEC);
> + delay.unit = SPI_DELAY_UNIT_USECS;
> + delay.value = clamp_val(us, 0, USHRT_MAX);
> + }
> +
> + while (dw_spi_dma_rx_busy(dws) && retry--)
> + spi_delay_exec(&delay, NULL);
> +
> + if (retry < 0) {
> + dev_err(&dws->master->dev, "Rx hanged up\n");
> + return -EIO;
> + }
> +
> + return 0;
> +}
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
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