* [PATCH v6 5/6] dt-bindings: power: Extend RPMh power controller binding to describe thermal warming device
From: Thara Gopinath @ 2020-06-04 1:53 UTC (permalink / raw)
To: rui.zhang, ulf.hansson, daniel.lezcano, bjorn.andersson, agross,
robh
Cc: amit.kucheria, mark.rutland, rjw, linux-pm, devicetree,
linux-arm-msm, linux-kernel
In-Reply-To: <20200604015317.31389-1-thara.gopinath@linaro.org>
RPMh power controller hosts mx domain that can be used as thermal warming
device. Add #cooling-cells property to the power domain provider node to
indicate this.
Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
---
v3->v4:
- Removed subnode to indicate that mx power domain is a warming
device. Instead #cooling-cells is used as a power domain
provider property to indicate if the provider hosts a power
domain that can be used as a warming device.
v4->v5:
Moved the property from .txt format to .yaml format.
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
index 8058955fb3b9..a4fbbd88ce18 100644
--- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
+++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
@@ -28,6 +28,9 @@ properties:
'#power-domain-cells':
const: 1
+ '#cooling-cells':
+ const: 2
+
operating-points-v2: true
opp-table:
--
2.20.1
^ permalink raw reply related
* [PATCH v6 3/6] thermal: Add generic power domain warming device driver.
From: Thara Gopinath @ 2020-06-04 1:53 UTC (permalink / raw)
To: rui.zhang, ulf.hansson, daniel.lezcano, bjorn.andersson, agross,
robh
Cc: amit.kucheria, mark.rutland, rjw, linux-pm, devicetree,
linux-arm-msm, linux-kernel
In-Reply-To: <20200604015317.31389-1-thara.gopinath@linaro.org>
Resources modeled as power domains in linux kernel can be used to warm the
SoC(eg. mx power domain on sdm845). To support this feature, introduce a
generic power domain warming device driver that can be plugged into the
thermal framework (The thermal framework itself requires further
modifiction to support a warming device in place of a cooling device.
Those extensions are not introduced in this patch series).
Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
---
v3->v4:
- Removed late_init hook pd_warming_device_ops.
- Use of_genpd_add_device instead of pm_genpd_add_device to attach
device to the generic power domain.
- Use thermal_of_cooling_device_parent_register to register the
cooling device so that the device with genpd attached can be
made parent of the cooling device.
- With above changes, remove reference to generic_pm_domain in
pd_warming_device.
v4->v5:
- All the below changes are as per Ulf's review comments.
- Renamed pwr_domain_warming.c and pwr_domain_warming.h to
pd_warming.c and pd_warming.h.
- Renamed pwr_domain_warming_register API to
of_pd_warming_register.
- Dropped in-param pd_name to of_pd_warming_register.
- Introduced ID allocator to uniquely identify each power domain
warming device.
- Introduced pd_warming_release to handle device kfree for
pd_warming_device.
- Introduced pm_genpd_remove_device in the error exit path
of of_pd_warming_register.
v5->v6:
- Fixed issues with ->release() and kfree(dev) as pointed
out by Ulf.
drivers/thermal/Kconfig | 10 +++
drivers/thermal/Makefile | 4 +
drivers/thermal/pd_warming.c | 169 +++++++++++++++++++++++++++++++++++
include/linux/pd_warming.h | 29 ++++++
4 files changed, 212 insertions(+)
create mode 100644 drivers/thermal/pd_warming.c
create mode 100644 include/linux/pd_warming.h
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index e53314ea9e25..3a0bcf3e8bd9 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -206,6 +206,16 @@ config DEVFREQ_THERMAL
If you want this support, you should say Y here.
+config PWR_DOMAIN_WARMING_THERMAL
+ bool "Power Domain based warming device"
+ depends on PM_GENERIC_DOMAINS_OF
+ help
+ This implements the generic power domain based warming
+ mechanism through increasing the performance state of
+ a power domain.
+
+ If you want this support, you should say Y here.
+
config THERMAL_EMULATION
bool "Thermal emulation mode support"
help
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 86c506410cc0..14fa696a08bd 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -28,7 +28,11 @@ thermal_sys-$(CONFIG_CLOCK_THERMAL) += clock_cooling.o
# devfreq cooling
thermal_sys-$(CONFIG_DEVFREQ_THERMAL) += devfreq_cooling.o
+#pwr domain warming
+thermal_sys-$(CONFIG_PWR_DOMAIN_WARMING_THERMAL) += pd_warming.o
+
obj-$(CONFIG_K3_THERMAL) += k3_bandgap.o
+
# platform thermal drivers
obj-y += broadcom/
obj-$(CONFIG_THERMAL_MMIO) += thermal_mmio.o
diff --git a/drivers/thermal/pd_warming.c b/drivers/thermal/pd_warming.c
new file mode 100644
index 000000000000..1ea93481c79b
--- /dev/null
+++ b/drivers/thermal/pd_warming.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019, Linaro Ltd
+ */
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+#include <linux/pd_warming.h>
+
+struct pd_warming_device {
+ struct thermal_cooling_device *cdev;
+ struct device dev;
+ int id;
+ int max_state;
+ int cur_state;
+ bool runtime_resumed;
+};
+
+static DEFINE_IDA(pd_ida);
+
+static int pd_wdev_get_max_state(struct thermal_cooling_device *cdev,
+ unsigned long *state)
+{
+ struct pd_warming_device *pd_wdev = cdev->devdata;
+
+ *state = pd_wdev->max_state;
+ return 0;
+}
+
+static int pd_wdev_get_cur_state(struct thermal_cooling_device *cdev,
+ unsigned long *state)
+{
+ struct pd_warming_device *pd_wdev = cdev->devdata;
+
+ *state = dev_pm_genpd_get_performance_state(&pd_wdev->dev);
+
+ return 0;
+}
+
+static int pd_wdev_set_cur_state(struct thermal_cooling_device *cdev,
+ unsigned long state)
+{
+ struct pd_warming_device *pd_wdev = cdev->devdata;
+ struct device *dev = &pd_wdev->dev;
+ int ret;
+
+ ret = dev_pm_genpd_set_performance_state(dev, state);
+
+ if (ret)
+ return ret;
+
+ if (state && !pd_wdev->runtime_resumed) {
+ ret = pm_runtime_get_sync(dev);
+ pd_wdev->runtime_resumed = true;
+ } else if (!state && pd_wdev->runtime_resumed) {
+ ret = pm_runtime_put(dev);
+ pd_wdev->runtime_resumed = false;
+ }
+
+ return ret;
+}
+
+static struct thermal_cooling_device_ops pd_warming_device_ops = {
+ .get_max_state = pd_wdev_get_max_state,
+ .get_cur_state = pd_wdev_get_cur_state,
+ .set_cur_state = pd_wdev_set_cur_state,
+};
+
+static void pd_warming_release(struct device *dev)
+{
+ struct pd_warming_device *pd_wdev;
+
+ pd_wdev = container_of(dev, struct pd_warming_device, dev);
+ kfree(pd_wdev);
+}
+
+struct thermal_cooling_device *
+of_pd_warming_register(struct device *parent, int pd_id)
+{
+ struct pd_warming_device *pd_wdev;
+ struct of_phandle_args pd_args;
+ char cdev_name[THERMAL_NAME_LENGTH];
+ int ret;
+
+ pd_wdev = kzalloc(sizeof(*pd_wdev), GFP_KERNEL);
+ if (!pd_wdev)
+ return ERR_PTR(-ENOMEM);
+
+ dev_set_name(&pd_wdev->dev, "%s_%d_warming_dev",
+ dev_name(parent), pd_id);
+ pd_wdev->dev.parent = parent;
+ pd_wdev->dev.release = pd_warming_release;
+
+ ret = device_register(&pd_wdev->dev);
+ if (ret) {
+ put_device(&pd_wdev->dev);
+ goto out;
+ }
+
+ ret = ida_simple_get(&pd_ida, 0, 0, GFP_KERNEL);
+ if (ret < 0)
+ goto unregister_device;
+
+ pd_wdev->id = ret;
+
+ pd_args.np = parent->of_node;
+ pd_args.args[0] = pd_id;
+ pd_args.args_count = 1;
+
+ ret = of_genpd_add_device(&pd_args, &pd_wdev->dev);
+
+ if (ret)
+ goto remove_ida;
+
+ ret = dev_pm_genpd_performance_state_count(&pd_wdev->dev);
+ if (ret < 0)
+ goto out_genpd;
+
+ pd_wdev->max_state = ret - 1;
+ pm_runtime_enable(&pd_wdev->dev);
+ pd_wdev->runtime_resumed = false;
+
+ snprintf(cdev_name, sizeof(cdev_name), "thermal-pd-%d", pd_wdev->id);
+ pd_wdev->cdev = thermal_of_cooling_device_register
+ (NULL, cdev_name, pd_wdev,
+ &pd_warming_device_ops);
+ if (IS_ERR(pd_wdev->cdev)) {
+ pr_err("unable to register %s cooling device\n", cdev_name);
+ ret = PTR_ERR(pd_wdev->cdev);
+ goto out_runtime_disable;
+ }
+
+ return pd_wdev->cdev;
+
+out_runtime_disable:
+ pm_runtime_disable(&pd_wdev->dev);
+out_genpd:
+ pm_genpd_remove_device(&pd_wdev->dev);
+remove_ida:
+ ida_simple_remove(&pd_ida, pd_wdev->id);
+unregister_device:
+ device_unregister(&pd_wdev->dev);
+out:
+ return ERR_PTR(ret);
+}
+EXPORT_SYMBOL_GPL(of_pd_warming_register);
+
+void pd_warming_unregister(struct thermal_cooling_device *cdev)
+{
+ struct pd_warming_device *pd_wdev = cdev->devdata;
+ struct device *dev = &pd_wdev->dev;
+
+ if (pd_wdev->runtime_resumed) {
+ dev_pm_genpd_set_performance_state(dev, 0);
+ pm_runtime_put(dev);
+ pd_wdev->runtime_resumed = false;
+ }
+ pm_runtime_disable(dev);
+ pm_genpd_remove_device(dev);
+ ida_simple_remove(&pd_ida, pd_wdev->id);
+ thermal_cooling_device_unregister(cdev);
+ device_unregister(dev);
+}
+EXPORT_SYMBOL_GPL(pd_warming_unregister);
diff --git a/include/linux/pd_warming.h b/include/linux/pd_warming.h
new file mode 100644
index 000000000000..550a5683b56d
--- /dev/null
+++ b/include/linux/pd_warming.h
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019, Linaro Ltd.
+ */
+#ifndef __PWR_DOMAIN_WARMING_H__
+#define __PWR_DOMAIN_WARMING_H__
+
+#include <linux/pm_domain.h>
+#include <linux/thermal.h>
+
+#ifdef CONFIG_PWR_DOMAIN_WARMING_THERMAL
+struct thermal_cooling_device *
+of_pd_warming_register(struct device *parent, int pd_id);
+
+void pd_warming_unregister(struct thermal_cooling_device *cdev);
+
+#else
+static inline struct thermal_cooling_device *
+of_pd_warming_register(struct device *parent, int pd_id)
+{
+ return ERR_PTR(-ENOSYS);
+}
+
+static inline void
+pd_warming_unregister(struct thermal_cooling_device *cdev)
+{
+}
+#endif /* CONFIG_PWR_DOMAIN_WARMING_THERMAL */
+#endif /* __PWR_DOMAIN_WARMING_H__ */
--
2.20.1
^ permalink raw reply related
* [PATCH V2 1/3] dt-bindings: mmc: Convert imx esdhc to json-schema
From: Anson Huang @ 2020-06-04 1:41 UTC (permalink / raw)
To: ulf.hansson, robh+dt, shawnguo, s.hauer, kernel, festevam, mpa,
linux-mmc, devicetree, linux-arm-kernel, linux-kernel
Cc: Linux-imx
In-Reply-To: <1591234886-15351-1-git-send-email-Anson.Huang@nxp.com>
Convert the i.MX ESDHC binding to DT schema format using json-schema
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Changes since V1:
- add "unevaluatedProperties: false".
---
.../devicetree/bindings/mmc/fsl-imx-esdhc.txt | 67 -----------
.../devicetree/bindings/mmc/fsl-imx-esdhc.yaml | 124 +++++++++++++++++++++
2 files changed, 124 insertions(+), 67 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
create mode 100644 Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
deleted file mode 100644
index de1b8bd..0000000
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-* Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
-
-The Enhanced Secure Digital Host Controller on Freescale i.MX family
-provides an interface for MMC, SD, and SDIO types of memory cards.
-
-This file documents differences between the core properties described
-by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
-
-Required properties:
-- compatible : Should be "fsl,<chip>-esdhc", the supported chips include
- "fsl,imx25-esdhc"
- "fsl,imx35-esdhc"
- "fsl,imx51-esdhc"
- "fsl,imx53-esdhc"
- "fsl,imx6q-usdhc"
- "fsl,imx6sl-usdhc"
- "fsl,imx6sx-usdhc"
- "fsl,imx6ull-usdhc"
- "fsl,imx7d-usdhc"
- "fsl,imx7ulp-usdhc"
- "fsl,imx8mq-usdhc"
- "fsl,imx8mm-usdhc"
- "fsl,imx8mn-usdhc"
- "fsl,imx8mp-usdhc"
- "fsl,imx8qm-usdhc"
- "fsl,imx8qxp-usdhc"
-
-Optional properties:
-- fsl,wp-controller : Indicate to use controller internal write protection
-- fsl,delay-line : Specify the number of delay cells for override mode.
- This is used to set the clock delay for DLL(Delay Line) on override mode
- to select a proper data sampling window in case the clock quality is not good
- due to signal path is too long on the board. Please refer to eSDHC/uSDHC
- chapter, DLL (Delay Line) section in RM for details.
-- voltage-ranges : Specify the voltage range in case there are software
- transparent level shifters on the outputs of the controller. Two cells are
- required, first cell specifies minimum slot voltage (mV), second cell
- specifies maximum slot voltage (mV). Several ranges could be specified.
-- fsl,tuning-start-tap: Specify the start dealy cell point when send first CMD19
- in tuning procedure.
-- fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure.
- The uSDHC use one delay cell as default increasing step to do tuning process.
- This property allows user to change the tuning step to more than one delay
- cells which is useful for some special boards or cards when the default
- tuning step can't find the proper delay window within limited tuning retries.
-- fsl,strobe-dll-delay-target: Specify the strobe dll control slave delay target.
- This delay target programming host controller loopback read clock, and this
- property allows user to change the delay target for the strobe input read clock.
- If not use this property, driver default set the delay target to value 7.
- Only eMMC HS400 mode need to take care of this property.
-
-Examples:
-
-esdhc@70004000 {
- compatible = "fsl,imx51-esdhc";
- reg = <0x70004000 0x4000>;
- interrupts = <1>;
- fsl,wp-controller;
-};
-
-esdhc@70008000 {
- compatible = "fsl,imx51-esdhc";
- reg = <0x70008000 0x4000>;
- interrupts = <2>;
- cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
- wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
-};
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
new file mode 100644
index 0000000..74db24aa
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
+
+maintainers:
+ - Shawn Guo <shawn.guo@linaro.org>
+
+allOf:
+ - $ref: "mmc-controller.yaml"
+
+description: |
+ The Enhanced Secure Digital Host Controller on Freescale i.MX family
+ provides an interface for MMC, SD, and SDIO types of memory cards.
+
+ This file documents differences between the core properties described
+ by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx25-esdhc
+ - fsl,imx35-esdhc
+ - fsl,imx51-esdhc
+ - fsl,imx53-esdhc
+ - fsl,imx6q-usdhc
+ - fsl,imx6sl-usdhc
+ - fsl,imx6sx-usdhc
+ - fsl,imx6ull-usdhc
+ - fsl,imx7d-usdhc
+ - fsl,imx7ulp-usdhc
+ - fsl,imx8mq-usdhc
+ - fsl,imx8mm-usdhc
+ - fsl,imx8mn-usdhc
+ - fsl,imx8mp-usdhc
+ - fsl,imx8qm-usdhc
+ - fsl,imx8qxp-usdhc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ fsl,wp-controller:
+ description: |
+ boolean, if present, indicate to use controller internal write protection.
+ type: boolean
+
+ fsl,delay-line:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Specify the number of delay cells for override mode.
+ This is used to set the clock delay for DLL(Delay Line) on override mode
+ to select a proper data sampling window in case the clock quality is not good
+ due to signal path is too long on the board. Please refer to eSDHC/uSDHC
+ chapter, DLL (Delay Line) section in RM for details.
+ default: 0
+
+ voltage-ranges:
+ $ref: '/schemas/types.yaml#/definitions/uint32-matrix'
+ description: |
+ Specify the voltage range in case there are software
+ transparent level shifters on the outputs of the controller. Two cells are
+ required, first cell specifies minimum slot voltage (mV), second cell
+ specifies maximum slot voltage (mV). Several ranges could be specified.
+ items:
+ items:
+ - description: value for minimum slot voltage
+ - description: value for maximum slot voltage
+ maxItems: 1
+
+ fsl,tuning-start-tap:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Specify the start dealy cell point when send first CMD19 in tuning procedure.
+ default: 0
+
+ fsl,tuning-step:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Specify the increasing delay cell steps in tuning procedure.
+ The uSDHC use one delay cell as default increasing step to do tuning process.
+ This property allows user to change the tuning step to more than one delay
+ cells which is useful for some special boards or cards when the default
+ tuning step can't find the proper delay window within limited tuning retries.
+ default: 0
+
+ fsl,strobe-dll-delay-target:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Specify the strobe dll control slave delay target.
+ This delay target programming host controller loopback read clock, and this
+ property allows user to change the delay target for the strobe input read clock.
+ If not use this property, driver default set the delay target to value 7.
+ Only eMMC HS400 mode need to take care of this property.
+ default: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mmc@70004000 {
+ compatible = "fsl,imx51-esdhc";
+ reg = <0x70004000 0x4000>;
+ interrupts = <1>;
+ fsl,wp-controller;
+ };
+
+ mmc@70008000 {
+ compatible = "fsl,imx51-esdhc";
+ reg = <0x70008000 0x4000>;
+ interrupts = <2>;
+ cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
+ wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH V2 3/3] dt-bindings: mmc: Convert mxs mmc to json-schema
From: Anson Huang @ 2020-06-04 1:41 UTC (permalink / raw)
To: ulf.hansson, robh+dt, shawnguo, s.hauer, kernel, festevam, mpa,
linux-mmc, devicetree, linux-arm-kernel, linux-kernel
Cc: Linux-imx
In-Reply-To: <1591234886-15351-1-git-send-email-Anson.Huang@nxp.com>
Convert the MXS MMC binding to DT schema format using json-schema
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Changes since V1:
- add "unevaluatedProperties: false".
---
Documentation/devicetree/bindings/mmc/mxs-mmc.txt | 27 ----------
Documentation/devicetree/bindings/mmc/mxs-mmc.yaml | 58 ++++++++++++++++++++++
2 files changed, 58 insertions(+), 27 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/mxs-mmc.txt
create mode 100644 Documentation/devicetree/bindings/mmc/mxs-mmc.yaml
diff --git a/Documentation/devicetree/bindings/mmc/mxs-mmc.txt b/Documentation/devicetree/bindings/mmc/mxs-mmc.txt
deleted file mode 100644
index 515addc..0000000
--- a/Documentation/devicetree/bindings/mmc/mxs-mmc.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* Freescale MXS MMC controller
-
-The Freescale MXS Synchronous Serial Ports (SSP) can act as a MMC controller
-to support MMC, SD, and SDIO types of memory cards.
-
-This file documents differences between the core properties in mmc.txt
-and the properties used by the mxsmmc driver.
-
-Required properties:
-- compatible: Should be "fsl,<chip>-mmc". The supported chips include
- imx23 and imx28.
-- interrupts: Should contain ERROR interrupt number
-- dmas: DMA specifier, consisting of a phandle to DMA controller node
- and SSP DMA channel ID.
- Refer to dma.txt and fsl-mxs-dma.txt for details.
-- dma-names: Must be "rx-tx".
-
-Examples:
-
-ssp0: ssp@80010000 {
- compatible = "fsl,imx28-mmc";
- reg = <0x80010000 2000>;
- interrupts = <96>;
- dmas = <&dma_apbh 0>;
- dma-names = "rx-tx";
- bus-width = <8>;
-};
diff --git a/Documentation/devicetree/bindings/mmc/mxs-mmc.yaml b/Documentation/devicetree/bindings/mmc/mxs-mmc.yaml
new file mode 100644
index 0000000..1cccc04
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/mxs-mmc.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/mxs-mmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale MXS MMC controller
+
+maintainers:
+ - Shawn Guo <shawn.guo@linaro.org>
+
+description: |
+ The Freescale MXS Synchronous Serial Ports (SSP) can act as a MMC controller
+ to support MMC, SD, and SDIO types of memory cards.
+
+ This file documents differences between the core properties in mmc.txt
+ and the properties used by the mxsmmc driver.
+
+allOf:
+ - $ref: "mmc-controller.yaml"
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx23-mmc
+ - fsl,imx28-mmc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ dmas:
+ maxItems: 1
+
+ dma-names:
+ const: rx-tx
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - dmas
+ - dma-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mmc@80010000 {
+ compatible = "fsl,imx28-mmc";
+ reg = <0x80010000 2000>;
+ interrupts = <96>;
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+ bus-width = <8>;
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH V2 2/3] dt-bindings: mmc: Convert imx mmc to json-schema
From: Anson Huang @ 2020-06-04 1:41 UTC (permalink / raw)
To: ulf.hansson, robh+dt, shawnguo, s.hauer, kernel, festevam, mpa,
linux-mmc, devicetree, linux-arm-kernel, linux-kernel
Cc: Linux-imx
In-Reply-To: <1591234886-15351-1-git-send-email-Anson.Huang@nxp.com>
Convert the i.MX MMC binding to DT schema format using json-schema
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Changes since V1:
- add "unevaluatedProperties: false".
---
.../devicetree/bindings/mmc/fsl-imx-mmc.txt | 23 ----------
.../devicetree/bindings/mmc/fsl-imx-mmc.yaml | 53 ++++++++++++++++++++++
2 files changed, 53 insertions(+), 23 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/fsl-imx-mmc.txt
create mode 100644 Documentation/devicetree/bindings/mmc/fsl-imx-mmc.yaml
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-mmc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-mmc.txt
deleted file mode 100644
index 184ccff..0000000
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-mmc.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* Freescale Secure Digital Host Controller for i.MX2/3 series
-
-This file documents differences to the properties defined in mmc.txt.
-
-Required properties:
-- compatible : Should be "fsl,<chip>-mmc", chip can be imx21 or imx31
-
-Optional properties:
-- dmas: One DMA phandle with arguments as defined by the devicetree bindings
- of the used DMA controller.
-- dma-names: Has to be "rx-tx".
-
-Example:
-
-sdhci1: sdhci@10014000 {
- compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
- reg = <0x10014000 0x1000>;
- interrupts = <11>;
- dmas = <&dma 7>;
- dma-names = "rx-tx";
- bus-width = <4>;
- cd-gpios = <&gpio3 29>;
-};
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-mmc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-mmc.yaml
new file mode 100644
index 0000000..ffa1627
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-mmc.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/fsl-imx-mmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Secure Digital Host Controller for i.MX2/3 series
+
+maintainers:
+ - Markus Pargmann <mpa@pengutronix.de>
+
+allOf:
+ - $ref: "mmc-controller.yaml"
+
+properties:
+ compatible:
+ oneOf:
+ - const: fsl,imx21-mmc
+ - const: fsl,imx31-mmc
+ - items:
+ - const: fsl,imx27-mmc
+ - const: fsl,imx21-mmc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ dmas:
+ maxItems: 1
+
+ dma-names:
+ const: rx-tx
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mmc@10014000 {
+ compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
+ reg = <0x10014000 0x1000>;
+ interrupts = <11>;
+ dmas = <&dma 7>;
+ dma-names = "rx-tx";
+ bus-width = <4>;
+ cd-gpios = <&gpio3 29>;
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH V2 0/3] Convert i.MX/MXS mmc binding to json-schema
From: Anson Huang @ 2020-06-04 1:41 UTC (permalink / raw)
To: ulf.hansson, robh+dt, shawnguo, s.hauer, kernel, festevam, mpa,
linux-mmc, devicetree, linux-arm-kernel, linux-kernel
Cc: Linux-imx
This patch series converts i.MX and MXS mmc binding to json-schema,
fix some minor issues in original binding doc, such as node name should be 'mmc',
compatible name for i.MX27, reg/interrupts should be required properties etc..
Compared to V1, this patch series adds "unevaluatedProperties: false" for
each binding doc.
Anson Huang (3):
dt-bindings: mmc: Convert imx esdhc to json-schema
dt-bindings: mmc: Convert imx mmc to json-schema
dt-bindings: mmc: Convert mxs mmc to json-schema
.../devicetree/bindings/mmc/fsl-imx-esdhc.txt | 67 -----------
.../devicetree/bindings/mmc/fsl-imx-esdhc.yaml | 124 +++++++++++++++++++++
.../devicetree/bindings/mmc/fsl-imx-mmc.txt | 23 ----
.../devicetree/bindings/mmc/fsl-imx-mmc.yaml | 53 +++++++++
Documentation/devicetree/bindings/mmc/mxs-mmc.txt | 27 -----
Documentation/devicetree/bindings/mmc/mxs-mmc.yaml | 58 ++++++++++
6 files changed, 235 insertions(+), 117 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
create mode 100644 Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
delete mode 100644 Documentation/devicetree/bindings/mmc/fsl-imx-mmc.txt
create mode 100644 Documentation/devicetree/bindings/mmc/fsl-imx-mmc.yaml
delete mode 100644 Documentation/devicetree/bindings/mmc/mxs-mmc.txt
create mode 100644 Documentation/devicetree/bindings/mmc/mxs-mmc.yaml
--
2.7.4
^ permalink raw reply
* [PATCH V2] dt-bindings: rtc: Convert imxdi rtc to json-schema
From: Anson Huang @ 2020-06-04 1:35 UTC (permalink / raw)
To: a.zummo, alexandre.belloni, robh+dt, shawnguo, s.hauer, kernel,
festevam, stigge, linux-rtc, devicetree, linux-arm-kernel,
linux-kernel
Cc: Linux-imx
Convert the i.MXDI RTC binding to DT schema format using json-schema
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Changes since V1:
- add "additionalProperties: false".
---
.../devicetree/bindings/rtc/imxdi-rtc.txt | 20 ----------
.../devicetree/bindings/rtc/imxdi-rtc.yaml | 44 ++++++++++++++++++++++
2 files changed, 44 insertions(+), 20 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/rtc/imxdi-rtc.txt
create mode 100644 Documentation/devicetree/bindings/rtc/imxdi-rtc.yaml
diff --git a/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt b/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt
deleted file mode 100644
index c797bc9..0000000
--- a/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-* i.MX25 Real Time Clock controller
-
-Required properties:
-- compatible: should be: "fsl,imx25-rtc"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- clocks: should contain the phandle for the rtc clock
-- interrupts: rtc alarm interrupt
-
-Optional properties:
-- interrupts: dryice security violation interrupt (second entry)
-
-Example:
-
-rtc@53ffc000 {
- compatible = "fsl,imx25-rtc";
- reg = <0x53ffc000 0x4000>;
- clocks = <&clks 81>;
- interrupts = <25 56>;
-};
diff --git a/Documentation/devicetree/bindings/rtc/imxdi-rtc.yaml b/Documentation/devicetree/bindings/rtc/imxdi-rtc.yaml
new file mode 100644
index 0000000..06bd737
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/imxdi-rtc.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/imxdi-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX25 Real Time Clock controller
+
+maintainers:
+ - Roland Stigge <stigge@antcom.de>
+
+properties:
+ compatible:
+ const: fsl,imx25-rtc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: rtc alarm interrupt
+ - description: dryice security violation interrupt
+ minItems: 1
+ maxItems: 2
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ rtc@53ffc000 {
+ compatible = "fsl,imx25-rtc";
+ reg = <0x53ffc000 0x4000>;
+ clocks = <&clks 81>;
+ interrupts = <25>, <56>;
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH V2] dt-bindings: clock: Convert imx7ulp clock to json-schema
From: Anson Huang @ 2020-06-04 1:33 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, shawnguo, s.hauer, kernel, festevam,
aisheng.dong, linux-clk, devicetree, linux-arm-kernel,
linux-kernel
Cc: Linux-imx
Convert the i.MX7ULP clock binding to DT schema format using json-schema,
the original binding doc is actually for two clock modules(SCG and PCC),
so split it to two binding docs, and the MPLL(mipi PLL) is NOT supposed
to be in clock module, so remove it from binding doc as well.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Changes since V1:
- add "additionalProperties: false".
---
.../devicetree/bindings/clock/imx7ulp-clock.txt | 103 ------------------
.../bindings/clock/imx7ulp-pcc-clock.yaml | 121 +++++++++++++++++++++
.../bindings/clock/imx7ulp-scg-clock.yaml | 99 +++++++++++++++++
3 files changed, 220 insertions(+), 103 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-pcc-clock.yaml
create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-scg-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
deleted file mode 100644
index 93d89ad..0000000
--- a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
+++ /dev/null
@@ -1,103 +0,0 @@
-* Clock bindings for Freescale i.MX7ULP
-
-i.MX7ULP Clock functions are under joint control of the System
-Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
-modules, and Core Mode Controller (CMC)1 blocks
-
-The clocking scheme provides clear separation between M4 domain
-and A7 domain. Except for a few clock sources shared between two
-domains, such as the System Oscillator clock, the Slow IRC (SIRC),
-and and the Fast IRC clock (FIRCLK), clock sources and clock
-management are separated and contained within each domain.
-
-M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
-A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
-
-Note: this binding doc is only for A7 clock domain.
-
-System Clock Generation (SCG) modules:
----------------------------------------------------------------------
-The System Clock Generation (SCG) is responsible for clock generation
-and distribution across this device. Functions performed by the SCG
-include: clock reference selection, generation of clock used to derive
-processor, system, peripheral bus and external memory interface clocks,
-source selection for peripheral clocks and control of power saving
-clock gating mode.
-
-Required properties:
-
-- compatible: Should be "fsl,imx7ulp-scg1".
-- reg : Should contain registers location and length.
-- #clock-cells: Should be <1>.
-- clocks: Should contain the fixed input clocks.
-- clock-names: Should contain the following clock names:
- "rosc", "sosc", "sirc", "firc", "upll", "mpll".
-
-Peripheral Clock Control (PCC) modules:
----------------------------------------------------------------------
-The Peripheral Clock Control (PCC) is responsible for clock selection,
-optional division and clock gating mode for peripherals in their
-respected power domain
-
-Required properties:
-- compatible: Should be one of:
- "fsl,imx7ulp-pcc2",
- "fsl,imx7ulp-pcc3".
-- reg : Should contain registers location and length.
-- #clock-cells: Should be <1>.
-- clocks: Should contain the fixed input clocks.
-- clock-names: Should contain the following clock names:
- "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2",
- "apll_pfd1", "apll_pfd0", "upll", "sosc_bus_clk",
- "mpll", "firc_bus_clk", "rosc", "spll_bus_clk";
-
-The clock consumer should specify the desired clock by having the clock
-ID in its "clocks" phandle cell.
-See include/dt-bindings/clock/imx7ulp-clock.h
-for the full list of i.MX7ULP clock IDs of each module.
-
-Examples:
-
-#include <dt-bindings/clock/imx7ulp-clock.h>
-
-scg1: scg1@403e0000 {
- compatible = "fsl,imx7ulp-scg1;
- reg = <0x403e0000 0x10000>;
- clocks = <&rosc>, <&sosc>, <&sirc>,
- <&firc>, <&upll>, <&mpll>;
- clock-names = "rosc", "sosc", "sirc",
- "firc", "upll", "mpll";
- #clock-cells = <1>;
-};
-
-pcc2: pcc2@403f0000 {
- compatible = "fsl,imx7ulp-pcc2";
- reg = <0x403f0000 0x10000>;
- #clock-cells = <1>;
- clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
- <&scg1 IMX7ULP_CLK_NIC1_DIV>,
- <&scg1 IMX7ULP_CLK_DDR_DIV>,
- <&scg1 IMX7ULP_CLK_APLL_PFD2>,
- <&scg1 IMX7ULP_CLK_APLL_PFD1>,
- <&scg1 IMX7ULP_CLK_APLL_PFD0>,
- <&scg1 IMX7ULP_CLK_UPLL>,
- <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
- <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
- <&scg1 IMX7ULP_CLK_ROSC>,
- <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
- clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
- "apll_pfd2", "apll_pfd1", "apll_pfd0",
- "upll", "sosc_bus_clk", "mpll",
- "firc_bus_clk", "rosc", "spll_bus_clk";
-};
-
-usdhc1: usdhc@40380000 {
- compatible = "fsl,imx7ulp-usdhc";
- reg = <0x40380000 0x10000>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
- <&scg1 IMX7ULP_CLK_NIC1_DIV>,
- <&pcc2 IMX7ULP_CLK_USDHC1>;
- clock-names ="ipg", "ahb", "per";
- bus-width = <4>;
-};
diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-pcc-clock.yaml b/Documentation/devicetree/bindings/clock/imx7ulp-pcc-clock.yaml
new file mode 100644
index 0000000..7caf5ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx7ulp-pcc-clock.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Clock bindings for Freescale i.MX7ULP Peripheral Clock Control (PCC) modules
+
+maintainers:
+ - A.s. Dong <aisheng.dong@nxp.com>
+
+description: |
+ i.MX7ULP Clock functions are under joint control of the System
+ Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
+ modules, and Core Mode Controller (CMC)1 blocks
+
+ The clocking scheme provides clear separation between M4 domain
+ and A7 domain. Except for a few clock sources shared between two
+ domains, such as the System Oscillator clock, the Slow IRC (SIRC),
+ and and the Fast IRC clock (FIRCLK), clock sources and clock
+ management are separated and contained within each domain.
+
+ M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
+ A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
+
+ Note: this binding doc is only for A7 clock domain.
+
+ The Peripheral Clock Control (PCC) is responsible for clock selection,
+ optional division and clock gating mode for peripherals in their
+ respected power domain.
+
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell.
+ See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
+ i.MX7ULP clock IDs of each module.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx7ulp-pcc2
+ - fsl,imx7ulp-pcc3
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ items:
+ - description: nic1 bus clock
+ - description: nic1 clock
+ - description: ddr clock
+ - description: apll pfd2
+ - description: apll pfd1
+ - description: apll pfd0
+ - description: usb pll
+ - description: system osc bus clock
+ - description: fast internal reference clock bus
+ - description: rtc osc
+ - description: system pll bus clock
+
+ clock-names:
+ items:
+ - const: nic1_bus_clk
+ - const: nic1_clk
+ - const: ddr_clk
+ - const: apll_pfd2
+ - const: apll_pfd1
+ - const: apll_pfd0
+ - const: upll
+ - const: sosc_bus_clk
+ - const: firc_bus_clk
+ - const: rosc
+ - const: spll_bus_clk
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx7ulp-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ clock-controller@403f0000 {
+ compatible = "fsl,imx7ulp-pcc2";
+ reg = <0x403f0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+ <&scg1 IMX7ULP_CLK_DDR_DIV>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD2>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD1>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD0>,
+ <&scg1 IMX7ULP_CLK_UPLL>,
+ <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
+ <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
+ <&scg1 IMX7ULP_CLK_ROSC>,
+ <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
+ clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
+ "apll_pfd2", "apll_pfd1", "apll_pfd0",
+ "upll", "sosc_bus_clk", "firc_bus_clk",
+ "rosc", "spll_bus_clk";
+ };
+
+ mmc@40380000 {
+ compatible = "fsl,imx7ulp-usdhc";
+ reg = <0x40380000 0x10000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+ <&pcc2 IMX7ULP_CLK_USDHC1>;
+ clock-names ="ipg", "ahb", "per";
+ bus-width = <4>;
+ };
diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-scg-clock.yaml b/Documentation/devicetree/bindings/clock/imx7ulp-scg-clock.yaml
new file mode 100644
index 0000000..ee8efb4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx7ulp-scg-clock.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Clock bindings for Freescale i.MX7ULP System Clock Generation (SCG) modules
+
+maintainers:
+ - A.s. Dong <aisheng.dong@nxp.com>
+
+description: |
+ i.MX7ULP Clock functions are under joint control of the System
+ Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
+ modules, and Core Mode Controller (CMC)1 blocks
+
+ The clocking scheme provides clear separation between M4 domain
+ and A7 domain. Except for a few clock sources shared between two
+ domains, such as the System Oscillator clock, the Slow IRC (SIRC),
+ and and the Fast IRC clock (FIRCLK), clock sources and clock
+ management are separated and contained within each domain.
+
+ M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
+ A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
+
+ Note: this binding doc is only for A7 clock domain.
+
+ The System Clock Generation (SCG) is responsible for clock generation
+ and distribution across this device. Functions performed by the SCG
+ include: clock reference selection, generation of clock used to derive
+ processor, system, peripheral bus and external memory interface clocks,
+ source selection for peripheral clocks and control of power saving
+ clock gating mode.
+
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell.
+ See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
+ i.MX7ULP clock IDs of each module.
+
+properties:
+ compatible:
+ const: fsl,imx7ulp-scg1
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ items:
+ - description: rtc osc
+ - description: system osc
+ - description: slow internal reference clock
+ - description: fast internal reference clock
+ - description: usb PLL
+
+ clock-names:
+ items:
+ - const: rosc
+ - const: sosc
+ - const: sirc
+ - const: firc
+ - const: upll
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx7ulp-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ clock-controller@403e0000 {
+ compatible = "fsl,imx7ulp-scg1";
+ reg = <0x403e0000 0x10000>;
+ clocks = <&rosc>, <&sosc>, <&sirc>,
+ <&firc>, <&upll>;
+ clock-names = "rosc", "sosc", "sirc",
+ "firc", "upll";
+ #clock-cells = <1>;
+ };
+
+ mmc@40380000 {
+ compatible = "fsl,imx7ulp-usdhc";
+ reg = <0x40380000 0x10000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+ <&pcc2 IMX7ULP_CLK_USDHC1>;
+ clock-names ="ipg", "ahb", "per";
+ bus-width = <4>;
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH V5] dt-bindings: thermal: Convert qoriq to json-schema
From: Anson Huang @ 2020-06-04 1:30 UTC (permalink / raw)
To: rui.zhang, daniel.lezcano, amit.kucheria, robh+dt, linux-pm,
devicetree, linux-kernel
Cc: Linux-imx
Convert the qoriq thermal binding to DT schema format using json-schema
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Changes since V4:
- add "additionalProperties: false"
---
.../devicetree/bindings/thermal/qoriq-thermal.txt | 71 -------------
.../devicetree/bindings/thermal/qoriq-thermal.yaml | 114 +++++++++++++++++++++
2 files changed, 114 insertions(+), 71 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
create mode 100644 Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml
diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
deleted file mode 100644
index 28f2cba..0000000
--- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
+++ /dev/null
@@ -1,71 +0,0 @@
-* Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
-
-Required properties:
-- compatible : Must include "fsl,qoriq-tmu" or "fsl,imx8mq-tmu". The
- version of the device is determined by the TMU IP Block Revision
- Register (IPBRR0) at offset 0x0BF8.
- Table of correspondences between IPBRR0 values and example chips:
- Value Device
- ---------- -----
- 0x01900102 T1040
-- reg : Address range of TMU registers.
-- interrupts : Contains the interrupt for TMU.
-- fsl,tmu-range : The values to be programmed into TTRnCR, as specified by
- the SoC reference manual. The first cell is TTR0CR, the second is
- TTR1CR, etc.
-- fsl,tmu-calibration : A list of cell pairs containing temperature
- calibration data, as specified by the SoC reference manual.
- The first cell of each pair is the value to be written to TTCFGR,
- and the second is the value to be written to TSCFGR.
-- #thermal-sensor-cells : Must be 1. The sensor specifier is the monitoring
- site ID, and represents the "n" in TRITSRn and TRATSRn.
-
-Optional property:
-- little-endian : If present, the TMU registers are little endian. If absent,
- the default is big endian.
-- clocks : the clock for clocking the TMU silicon.
-
-Example:
-
-tmu@f0000 {
- compatible = "fsl,qoriq-tmu";
- reg = <0xf0000 0x1000>;
- interrupts = <18 2 0 0>;
- fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
- fsl,tmu-calibration = <0x00000000 0x00000025
- 0x00000001 0x00000028
- 0x00000002 0x0000002d
- 0x00000003 0x00000031
- 0x00000004 0x00000036
- 0x00000005 0x0000003a
- 0x00000006 0x00000040
- 0x00000007 0x00000044
- 0x00000008 0x0000004a
- 0x00000009 0x0000004f
- 0x0000000a 0x00000054
-
- 0x00010000 0x0000000d
- 0x00010001 0x00000013
- 0x00010002 0x00000019
- 0x00010003 0x0000001f
- 0x00010004 0x00000025
- 0x00010005 0x0000002d
- 0x00010006 0x00000033
- 0x00010007 0x00000043
- 0x00010008 0x0000004b
- 0x00010009 0x00000053
-
- 0x00020000 0x00000010
- 0x00020001 0x00000017
- 0x00020002 0x0000001f
- 0x00020003 0x00000029
- 0x00020004 0x00000031
- 0x00020005 0x0000003c
- 0x00020006 0x00000042
- 0x00020007 0x0000004d
- 0x00020008 0x00000056
-
- 0x00030000 0x00000012
- 0x00030001 0x0000001d>;
- #thermal-sensor-cells = <1>;
-};
diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml b/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml
new file mode 100644
index 0000000..f09e872
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/qoriq-thermal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
+
+maintainers:
+ - Anson Huang <Anson.Huang@nxp.com>
+
+properties:
+ compatible:
+ description: |
+ The version of the device is determined by the TMU IP Block Revision
+ Register (IPBRR0) at offset 0x0BF8.
+ Table of correspondences between IPBRR0 values and example chips:
+ Value Device
+ ---------- -----
+ 0x01900102 T1040
+ enum:
+ - fsl,qoriq-tmu
+ - fsl,imx8mq-tmu
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ fsl,tmu-range:
+ $ref: '/schemas/types.yaml#/definitions/uint32-array'
+ description: |
+ The values to be programmed into TTRnCR, as specified by the SoC
+ reference manual. The first cell is TTR0CR, the second is TTR1CR, etc.
+ maxItems: 4
+
+ fsl,tmu-calibration:
+ $ref: '/schemas/types.yaml#/definitions/uint32-matrix'
+ description: |
+ A list of cell pairs containing temperature calibration data, as
+ specified by the SoC reference manual. The first cell of each pair
+ is the value to be written to TTCFGR, and the second is the value
+ to be written to TSCFGR.
+ items:
+ items:
+ - description: value for TTCFGR
+ - description: value for TSCFGR
+ minItems: 1
+ maxItems: 64
+
+ little-endian:
+ description: |
+ boolean, if present, the TMU registers are little endian. If absent,
+ the default is big endian.
+ type: boolean
+
+ clocks:
+ maxItems: 1
+
+ "#thermal-sensor-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - fsl,tmu-range
+ - fsl,tmu-calibration
+ - '#thermal-sensor-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ tmu@f0000 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0xf0000 0x1000>;
+ interrupts = <18 2 0 0>;
+ fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
+ fsl,tmu-calibration = <0x00000000 0x00000025>,
+ <0x00000001 0x00000028>,
+ <0x00000002 0x0000002d>,
+ <0x00000003 0x00000031>,
+ <0x00000004 0x00000036>,
+ <0x00000005 0x0000003a>,
+ <0x00000006 0x00000040>,
+ <0x00000007 0x00000044>,
+ <0x00000008 0x0000004a>,
+ <0x00000009 0x0000004f>,
+ <0x0000000a 0x00000054>,
+ <0x00010000 0x0000000d>,
+ <0x00010001 0x00000013>,
+ <0x00010002 0x00000019>,
+ <0x00010003 0x0000001f>,
+ <0x00010004 0x00000025>,
+ <0x00010005 0x0000002d>,
+ <0x00010006 0x00000033>,
+ <0x00010007 0x00000043>,
+ <0x00010008 0x0000004b>,
+ <0x00010009 0x00000053>,
+ <0x00020000 0x00000010>,
+ <0x00020001 0x00000017>,
+ <0x00020002 0x0000001f>,
+ <0x00020003 0x00000029>,
+ <0x00020004 0x00000031>,
+ <0x00020005 0x0000003c>,
+ <0x00020006 0x00000042>,
+ <0x00020007 0x0000004d>,
+ <0x00020008 0x00000056>,
+ <0x00030000 0x00000012>,
+ <0x00030001 0x0000001d>;
+ #thermal-sensor-cells = <1>;
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH 7/7] arm64: dts: qcom: sm8250: add watchdog device
From: Dmitry Baryshkov @ 2020-06-04 0:43 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, devicetree, patches, linaro-kernel
In-Reply-To: <20200604004331.669936-1-dmitry.baryshkov@linaro.org>
Add on-SoC watchdog device node.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 972d8e04c8a2..f1641c6fe203 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -1662,6 +1662,12 @@ config {
};
};
+ watchdog@17c10000 {
+ compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
+ reg = <0 0x17c10000 0 0x1000>;
+ clocks = <&sleep_clk>;
+ };
+
timer@17c20000 {
#address-cells = <2>;
#size-cells = <2>;
--
2.26.2
^ permalink raw reply related
* [PATCH 5/7] arm64: dts: qcom: pm8150x: add thermal alarms and thermal zones
From: Dmitry Baryshkov @ 2020-06-04 0:43 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, devicetree, patches, linaro-kernel
In-Reply-To: <20200604004331.669936-1-dmitry.baryshkov@linaro.org>
Add temperature alarm and thermal zone configuration to all three
pm8150 instances. Configuration is largely based on the msm-4.19 tree.
These alarms use main adc of the pmic. Separate temperature adc is not
supported yet.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/pm8150.dtsi | 41 +++++++++++++++++++++++--
arch/arm64/boot/dts/qcom/pm8150b.dtsi | 43 +++++++++++++++++++++++++--
arch/arm64/boot/dts/qcom/pm8150l.dtsi | 43 +++++++++++++++++++++++++--
3 files changed, 119 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi
index c0b197458665..fee2db42f4cb 100644
--- a/arch/arm64/boot/dts/qcom/pm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi
@@ -30,6 +30,15 @@ pwrkey {
};
};
+ pm8150_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pm8150_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
pm8150_adc: adc@3100 {
compatible = "qcom,spmi-adc5";
reg = <0x3100>;
@@ -38,8 +47,6 @@ pm8150_adc: adc@3100 {
#io-channel-cells = <1>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
-
ref-gnd@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
@@ -85,3 +92,33 @@ pmic@1 {
#size-cells = <0>;
};
};
+
+&thermal_zones {
+ pm8150_temp {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm8150_temp>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi
index 40b5d75a4a1d..e93d16f2d1e0 100644
--- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi
@@ -22,7 +22,16 @@ power-on@800 {
status = "disabled";
};
- adc@3100 {
+ pm8150b_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pm8150b_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8150b_adc: adc@3100 {
compatible = "qcom,spmi-adc5";
reg = <0x3100>;
#address-cells = <1>;
@@ -30,8 +39,6 @@ adc@3100 {
#io-channel-cells = <1>;
interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
-
ref-gnd@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
@@ -74,3 +81,33 @@ pmic@3 {
#size-cells = <0>;
};
};
+
+&thermal_zones {
+ pm8150b_temp {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm8150b_temp>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi
index cf05e0685d10..1edf87c95a27 100644
--- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi
@@ -22,7 +22,16 @@ power-on@800 {
status = "disabled";
};
- adc@3100 {
+ pm8150l_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pm8150l_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8150l_adc: adc@3100 {
compatible = "qcom,spmi-adc5";
reg = <0x3100>;
#address-cells = <1>;
@@ -30,8 +39,6 @@ adc@3100 {
#io-channel-cells = <1>;
interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
-
ref-gnd@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
@@ -68,3 +75,33 @@ pmic@5 {
#size-cells = <0>;
};
};
+
+&thermal_zones {
+ pm8150l_temp {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm8150l_temp>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ };
+};
--
2.26.2
^ permalink raw reply related
* [PATCH 6/7] arm64: dts: qcom: pm8150: enable rtc device
From: Dmitry Baryshkov @ 2020-06-04 0:43 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, devicetree, patches, linaro-kernel
In-Reply-To: <20200604004331.669936-1-dmitry.baryshkov@linaro.org>
Enable rtc device provided by the pmic.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/pm8150.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi
index fee2db42f4cb..762fb902db81 100644
--- a/arch/arm64/boot/dts/qcom/pm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi
@@ -71,8 +71,6 @@ rtc@6000 {
reg = <0x6000>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
-
- status = "disabled";
};
pm8150_gpios: gpio@c000 {
--
2.26.2
^ permalink raw reply related
* [PATCH 4/7] arm64: dts: qcom: sm8x50: add empty thermal zone nodes
From: Dmitry Baryshkov @ 2020-06-04 0:43 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, devicetree, patches, linaro-kernel
In-Reply-To: <20200604004331.669936-1-dmitry.baryshkov@linaro.org>
Add empty thermal_zone nodes. They will be populated by PMIC dtsi files,
describing thermal sensors and trip points for zones handled by PMICs.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 3 +++
arch/arm64/boot/dts/qcom/sm8250.dtsi | 3 +++
2 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 141c21dfa68c..869a54352d77 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -857,6 +857,9 @@ cpufreq_hw: cpufreq@18323000 {
};
};
+ thermal_zones: thermal-zones {
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 9dd27aecdfda..972d8e04c8a2 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -1736,6 +1736,9 @@ cpufreq_hw: cpufreq@18591000 {
};
};
+ thermal_zones: thermal-zones {
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
--
2.26.2
^ permalink raw reply related
* [PATCH 3/7] arm64: dts: qcom: sm8250-mtp: include pmic files
From: Dmitry Baryshkov @ 2020-06-04 0:43 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, devicetree, patches, linaro-kernel
In-Reply-To: <20200604004331.669936-1-dmitry.baryshkov@linaro.org>
Include files describing used PMIC chips, GPIOs, power on, etc nodes.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
index 0bc4b1e037c4..c20ae91d3026 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
@@ -7,6 +7,10 @@
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8250.dtsi"
+#include "pm8150.dtsi"
+#include "pm8150b.dtsi"
+#include "pm8150l.dtsi"
+#include "pm8009.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SM8250 MTP";
--
2.26.2
^ permalink raw reply related
* [PATCH 2/7] arm64: dts: qcom: sm8250: change spmi node label
From: Dmitry Baryshkov @ 2020-06-04 0:43 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, devicetree, patches, linaro-kernel
In-Reply-To: <20200604004331.669936-1-dmitry.baryshkov@linaro.org>
PMIC dtsi files (pm8150*.dtsi) expect to have spmi_bus label, rather
than just spmi. Rename spmi label accordingly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 1e2862bbfb11..9dd27aecdfda 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -991,7 +991,7 @@ pdc: interrupt-controller@b220000 {
interrupt-controller;
};
- spmi: qcom,spmi@c440000 {
+ spmi_bus: qcom,spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x0c440000 0x0 0x0001100>,
<0x0 0x0c600000 0x0 0x2000000>,
--
2.26.2
^ permalink raw reply related
* [PATCH 1/7] arm64: dts: qcom: pm8009: Add base dts file
From: Dmitry Baryshkov @ 2020-06-04 0:43 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, devicetree, patches, linaro-kernel
Add base DTS file for pm8009 along with GPIOs and power-on nodes.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/pm8009.dtsi | 40 ++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pm8009.dtsi
diff --git a/arch/arm64/boot/dts/qcom/pm8009.dtsi b/arch/arm64/boot/dts/qcom/pm8009.dtsi
new file mode 100644
index 000000000000..9f3e19b5bd00
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm8009.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&spmi_bus {
+ pmic@a {
+ compatible = "qcom,pm8009", "qcom,spmi-pmic";
+ reg = <0xa SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-on@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x0800>;
+ };
+
+ pm8009_gpios: gpio@c000 {
+ compatible = "qcom,pm8005-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmic@b {
+ compatible = "qcom,pm8009", "qcom,spmi-pmic";
+ reg = <0xb SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
--
2.26.2
^ permalink raw reply related
* Re: [PATCH 4/4] arm64: dts: ipq6018: Add support for apcs clk
From: kernel test robot @ 2020-06-04 0:19 UTC (permalink / raw)
To: Sivaprakash Murugesan, agross, bjorn.andersson, robh+dt,
jassisinghbrar, linux-arm-msm, devicetree, linux-kernel
Cc: kbuild-all, clang-built-linux, Sivaprakash Murugesan
In-Reply-To: <1590583092-24290-5-git-send-email-sivaprak@codeaurora.org>
[-- Attachment #1: Type: text/plain, Size: 1543 bytes --]
Hi Sivaprakash,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v5.7]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Sivaprakash-Murugesan/Add-ipq6018-apcs-mailbox-driver/20200527-204025
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r016-20200603 (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 16437992cac249f6fe1efd392d20e3469b47e39e)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>, old ones prefixed by <<):
>> ERROR: Input tree has errors, aborting (use -f to force output)
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 35982 bytes --]
^ permalink raw reply
* Re: [v4] dt-bindings: msm: disp: add yaml schemas for DPU and DSI bindings
From: Rob Herring @ 2020-06-03 22:45 UTC (permalink / raw)
To: Krishna Manikandan
Cc: dri-devel, linux-arm-msm, freedreno, devicetree, linux-kernel,
robdclark, seanpaul, hoegsberg, kalyan_t, nganji, mka
In-Reply-To: <1589868421-30062-1-git-send-email-mkrishn@codeaurora.org>
On Tue, May 19, 2020 at 11:37:01AM +0530, Krishna Manikandan wrote:
> MSM Mobile Display Subsytem (MDSS) encapsulates sub-blocks
> like DPU display controller, DSI etc. Add YAML schema
> for the device tree bindings for the same.
>
> Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
>
> Changes in v2:
> - Changed dpu to DPU (Sam Ravnborg)
> - Fixed indentation issues (Sam Ravnborg)
> - Added empty line between different properties (Sam Ravnborg)
> - Replaced reference txt files with their corresponding
> yaml files (Sam Ravnborg)
> - Modified the file to use "|" only when it is
> necessary (Sam Ravnborg)
>
> Changes in v3:
> - Corrected the license used (Rob Herring)
> - Added maxItems for properties (Rob Herring)
> - Dropped generic descriptions (Rob Herring)
> - Added ranges property (Rob Herring)
> - Corrected the indendation (Rob Herring)
> - Added additionalProperties (Rob Herring)
> - Split dsi file into two, one for dsi controller
> and another one for dsi phy per target (Rob Herring)
> - Corrected description for pinctrl-names (Rob Herring)
> - Corrected the examples used in yaml file (Rob Herring)
> - Delete dsi.txt and dpu.txt (Rob Herring)
>
> Changes in v4:
> - Move schema up by one level (Rob Herring)
> - Add patternProperties for mdp node (Rob Herring)
> - Corrected description of some properties (Rob Herring)
> ---
> .../bindings/display/msm/dpu-sc7180.yaml | 243 ++++++++++++++++++++
> .../bindings/display/msm/dpu-sdm845.yaml | 220 ++++++++++++++++++
> .../devicetree/bindings/display/msm/dpu.txt | 141 ------------
> .../display/msm/dsi-controller-sc7180.yaml | 123 +++++++++++
> .../display/msm/dsi-controller-sdm845.yaml | 120 ++++++++++
> .../bindings/display/msm/dsi-controller.yaml | 151 +++++++++++++
> .../bindings/display/msm/dsi-phy-sc7180.yaml | 75 +++++++
> .../bindings/display/msm/dsi-phy-sdm845.yaml | 76 +++++++
> .../devicetree/bindings/display/msm/dsi-phy.yaml | 82 +++++++
> .../devicetree/bindings/display/msm/dsi.txt | 246 ---------------------
> 10 files changed, 1090 insertions(+), 387 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
> create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
> delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu.txt
> create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-controller-sc7180.yaml
> create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-controller-sdm845.yaml
> create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-controller.yaml
> create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-sc7180.yaml
> create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-sdm845.yaml
> create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy.yaml
> delete mode 100644 Documentation/devicetree/bindings/display/msm/dsi.txt
>
> diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
> new file mode 100644
> index 0000000..b5607f9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
> @@ -0,0 +1,243 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Description of Qualcomm Display DPU dt properties.
> +
> +maintainers:
> + - Krishna Manikandan <mkrishn@codeaurora.org>
> +
> +description: |
> + Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
> + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
> + bindings of MDSS and DPU are mentioned for SC7180 target.
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,sc7180-mdss
blank line between properties.
> + reg:
> + maxItems: 1
> +
> + reg-names:
> + const: mdss
> +
> + power-domains:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 3
> +
> + clock-names:
> + description: |
> + Device clock names in the same order as mentioned in clocks property.
> + The required clocks are mentioned below.
Not a useful description. Unless you have something specific about
*this* device, drop it.
> + items:
> + - const: iface
> + - const: ahb
> + - const: core
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupt-controller: true
> +
> + "#interrupt-cells":
> + const: 1
> +
> + iommus:
> + maxItems: 1
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
> +
> + ranges: true
> +
> + interconnects:
> + description: |
> + Interconnect path specifier for MDSS according to
> + Documentation/devicetree/bindings/interconnect/interconnect.txt.
> + An entry should contain 2 paths corresponding to 2 AXI ports representing
> + source and destination ports.
2 entries or...
> + maxItems: 1
1?
> +
> + interconnect-names:
> + description: |
> + MDSS will have 2 port names to differentiate between the
> + 2 interconnect paths defined with interconnect specifier.
> + maxItems: 1
Need to define the names.
> +
> + assigned-clocks:
> + description: |
> + Clock specifiers for clocks needing rate assignment (optional).
That's every 'assigned-clocks'. Think about that for all of your
'description' entries and drop them if nothing device specific.
> + maxItems: 1
> +
> + assigned-clock-rates:
> + description: |
> + Clock frequencies sorted in the same order as the
> + assigned-clocks property (optional).
> + maxItems: 1
> +
> +patternProperties:
> + "^mdp@[0-9a-f]+$":
> + type: object
> + description: Node containing the properties of DPU.
> +
> + properties:
> + compatible:
> + items:
> + - const: qcom,sc7180-dpu
> +
> + reg:
> + maxItems: 2
> +
> + reg-names:
> + items:
> + - const: mdp
> + - const: vbif
> +
> + clocks:
> + maxItems: 6
> +
> + clock-names:
> + description: |
> + Device clock names, must be in same order as clocks property.
> + The following clocks are required. "bus" is an optional property
> + in sc7180 due to architecture change. "rot" and "lut" are optional
> + device clocks, needed for accessing LUT blocks.
The schema doesn't match this description. The schema only allows
the exact list below. You'll need an if/then schema to define the
different combinations. Or a 'oneOf' schema if there's different
possibilities for just the sc7180. There shouldn't be though. A given
chip either has a clock or it doesn't.
> + items:
> + - const: bus
> + - const: iface
> + - const: rot
> + - const: lut
> + - const: core
> + - const: vsync
> +
> + interrupts:
> + maxItems: 1
> +
> + ports:
> + type: object
> + description: |
> + Contains the list of output ports from DPU device. These ports
> + connect to interfaces that are external to the DPU hardware,
> + such as DSI, DP etc. Each output port contains an endpoint that
> + describes how it is connected to an external interface. These
> + are described by the standard properties documented in files
> + mentioned below.
> +
> + Documentation/devicetree/bindings/graph.txt
> + Documentation/devicetree/bindings/media/video-interfaces.txt
> +
> + properties:
> + port@0:
Wrong indentation.
> + type: object
> + description: DPU_INTF1 (DSI1)
> + port@1:
> + type: object
> + description: DPU_INTF2 (DSI2)
> +
> + assigned-clocks:
> + description: |
> + Clock specifiers for clocks needing rate assignment (optional).
> + maxItems: 4
> +
> + assigned-clock-rates:
> + description: |
> + Clock frequencies sorted in the same order as the
> + assigned-clocks property (optional).
> + maxItems: 4
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - power-domains
> + - clocks
> + - clock-names
> + - interrupts
> + - interrupt-controller
> + - iommus
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
> + #include <dt-bindings/clock/qcom,gcc-sc7180.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interconnect/qcom,sdm845.h>
> + mdss: mdss@ae00000 {
> + compatible = "qcom,sc7180-mdss";
> + reg = <0 0xae00000 0 0x1000>;
> + reg-names = "mdss";
> + power-domains = <&dispcc MDSS_GDSC>;
> +
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> +
> + clock-names = "iface", "ahb", "core";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
> + assigned-clock-rates = <300000000>;
> +
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
interconnects = <&mmss_noc MASTER_MDP0>, <&mc_virt SLAVE_EBI1>;
Which will fail with the above schema.
> +
> + interconnect-names = "mdp0-mem";
> +
> + iommus = <&apps_smmu 0x800 0x2>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + mdp: mdp@ae01000 {
> + compatible = "qcom,sc7180-dpu";
> + reg = <0 0x0ae01000 0 0x8f000>,
> + <0 0x0aeb0000 0 0x2008>;
> +
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_ROT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus", "iface", "rot", "lut", "core",
> + "vsync";
> + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
> + <&dispcc DISP_CC_MDSS_ROT_CLK>,
> + <&dispcc DISP_CC_MDSS_ROT_CLK>;
> + assigned-clock-rates = <300000000>,
> + <19200000>,
> + <19200000>,
> + <19200000>;
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> + };
> + };
> + };
> +...
> diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
> new file mode 100644
> index 0000000..ed036fd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
> @@ -0,0 +1,220 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Description of Qualcomm Display DPU dt properties.
> +
> +maintainers:
> + - Krishna Manikandan <mkrishn@codeaurora.org>
> +
> +description: |
> + Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
> + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
> + bindings of MDSS and DPU are mentioned for SDM845 target.
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,sdm845-mdss
> + reg:
> + maxItems: 1
> +
> + reg-names:
> + const: mdss
> +
> + power-domains:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 3
> +
> + clock-names:
> + description: |
> + Device clock names in the same order as mentioned in clocks property.
> + The required clocks are mentioned below.
> + items:
> + - const: iface
> + - const: bus
> + - const: core
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupt-controller: true
> +
> + "#interrupt-cells":
> + const: 1
> +
> + iommus:
> + maxItems: 2
Need to define what each one is:
items:
- description: ...
- description: ...
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
> +
> + ranges: true
> +
> + assigned-clocks:
> + description: |
> + Clock specifiers for clocks needing rate assignment (optional).
> + maxItems: 1
> +
> + assigned-clock-rates:
> + description: |
> + Clock frequencies sorted in the same order as the
> + assigned-clocks property (optional).
> + maxItems: 1
> +
> +patternProperties:
> + "^mdp@[0-9a-f]+$":
> + type: object
> + description: Node containing the properties of DPU.
> +
> + properties:
> + compatible:
> + items:
> + - const: qcom,sdm845-dpu
> + reg:
> + maxItems: 2
> +
> + reg-names:
> + items:
> + - const: mdp
> + - const: vbif
> +
> + clocks:
> + maxItems: 4
> +
> + clock-names:
> + description: |
> + Device clock names, must be in same order as clocks property.
> + The following clocks are required.
> + items:
> + - const: iface
> + - const: bus
> + - const: core
> + - const: vsync
> +
> + interrupts:
> + maxItems: 1
> +
> + ports:
> + type: object
> + description: |
> + Contains the list of output ports from DPU device. These ports
> + connect to interfaces that are external to the DPU hardware,
> + such as DSI, DP etc. Each output port contains an endpoint that
> + describes how it is connected to an external interface. These
> + are described by the standard properties documented in files
> + mentioned below.
> +
> + Documentation/devicetree/bindings/graph.txt
> + Documentation/devicetree/bindings/media/video-interfaces.txt
> +
> + properties:
> + port@0:
> + type: object
> + description: DPU_INTF1 (DSI1)
> + port@1:
> + type: object
> + description: DPU_INTF2 (DSI2)
> +
> + assigned-clocks:
> + description: |
> + Clock specifiers for clocks needing rate assignment (optional).
> + maxItems: 2
> +
> + assigned-clock-rates:
> + description: |
> + Clock frequencies sorted in the same order as the
> + assigned-clocks property (optional).
> + maxItems: 2
> +
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - power-domains
> + - clocks
> + - clock-names
> + - interrupts
> + - interrupt-controller
> + - iommus
> +
> +additionalProperties: false
> +
> +examples:
> +- |
> + #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + mdss: mdss@ae00000 {
> + compatible = "qcom,sdm845-mdss";
> + reg = <0 0x0ae00000 0 0x1000>;
> + reg-names = "mdss";
> + power-domains = <&dispcc MDSS_GDSC>;
> +
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> + <&gcc GCC_DISP_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface", "bus", "core";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
> + assigned-clock-rates = <300000000>;
> +
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + iommus = <&apps_smmu 0x880 0x8>,
> + <&apps_smmu 0xc80 0x8>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + mdss_mdp: mdp@ae01000 {
> + compatible = "qcom,sdm845-dpu";
> + reg = <0 0x0ae01000 0 0x8f000>,
> + <0 0x0aeb0000 0 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "iface", "bus", "core", "vsync";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <300000000>,
> + <19200000>;
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dpu_intf2_out: endpoint {
> + remote-endpoint = <&dsi1_in>;
> + };
> + };
> + };
> + };
> + };
> +...
> diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt
> deleted file mode 100644
> index 551ae26..0000000
> --- a/Documentation/devicetree/bindings/display/msm/dpu.txt
> +++ /dev/null
> @@ -1,141 +0,0 @@
> -Qualcomm Technologies, Inc. DPU KMS
> -
> -Description:
> -
> -Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
> -sub-blocks like DPU display controller, DSI and DP interfaces etc.
> -The DPU display controller is found in SDM845 SoC.
> -
> -MDSS:
> -Required properties:
> -- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
> -- reg: physical base address and length of contoller's registers.
> -- reg-names: register region names. The following region is required:
> - * "mdss"
> -- power-domains: a power domain consumer specifier according to
> - Documentation/devicetree/bindings/power/power_domain.txt
> -- clocks: list of clock specifiers for clocks needed by the device.
> -- clock-names: device clock names, must be in same order as clocks property.
> - The following clocks are required:
> - * "iface"
> - * "bus"
> - * "core"
> -- interrupts: interrupt signal from MDSS.
> -- interrupt-controller: identifies the node as an interrupt controller.
> -- #interrupt-cells: specifies the number of cells needed to encode an interrupt
> - source, should be 1.
> -- iommus: phandle of iommu device node.
> -- #address-cells: number of address cells for the MDSS children. Should be 1.
> -- #size-cells: Should be 1.
> -- ranges: parent bus address space is the same as the child bus address space.
> -- interconnects : interconnect path specifier for MDSS according to
> - Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
> - 2 paths corresponding to 2 AXI ports.
> -- interconnect-names : MDSS will have 2 port names to differentiate between the
> - 2 interconnect paths defined with interconnect specifier.
> -
> -Optional properties:
> -- assigned-clocks: list of clock specifiers for clocks needing rate assignment
> -- assigned-clock-rates: list of clock frequencies sorted in the same order as
> - the assigned-clocks property.
> -
> -MDP:
> -Required properties:
> -- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
> -- reg: physical base address and length of controller's registers.
> -- reg-names : register region names. The following region is required:
> - * "mdp"
> - * "vbif"
> -- clocks: list of clock specifiers for clocks needed by the device.
> -- clock-names: device clock names, must be in same order as clocks property.
> - The following clocks are required.
> - * "bus"
> - * "iface"
> - * "core"
> - * "vsync"
> -- interrupts: interrupt line from DPU to MDSS.
> -- ports: contains the list of output ports from DPU device. These ports connect
> - to interfaces that are external to the DPU hardware, such as DSI, DP etc.
> -
> - Each output port contains an endpoint that describes how it is connected to an
> - external interface. These are described by the standard properties documented
> - here:
> - Documentation/devicetree/bindings/graph.txt
> - Documentation/devicetree/bindings/media/video-interfaces.txt
> -
> - Port 0 -> DPU_INTF1 (DSI1)
> - Port 1 -> DPU_INTF2 (DSI2)
> -
> -Optional properties:
> -- assigned-clocks: list of clock specifiers for clocks needing rate assignment
> -- assigned-clock-rates: list of clock frequencies sorted in the same order as
> - the assigned-clocks property.
> -
> -Example:
> -
> - mdss: mdss@ae00000 {
> - compatible = "qcom,sdm845-mdss";
> - reg = <0xae00000 0x1000>;
> - reg-names = "mdss";
> -
> - power-domains = <&clock_dispcc 0>;
> -
> - clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
> - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
> - clock-names = "iface", "bus", "core";
> -
> - assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
> - assigned-clock-rates = <300000000>;
> -
> - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-controller;
> - #interrupt-cells = <1>;
> -
> - interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>,
> - <&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>;
> -
> - interconnect-names = "mdp0-mem", "mdp1-mem";
> -
> - iommus = <&apps_iommu 0>;
> -
> - #address-cells = <2>;
> - #size-cells = <1>;
> - ranges = <0 0 0xae00000 0xb2008>;
> -
> - mdss_mdp: mdp@ae01000 {
> - compatible = "qcom,sdm845-dpu";
> - reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>;
> - reg-names = "mdp", "vbif";
> -
> - clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
> - <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
> - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
> - <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
> - clock-names = "iface", "bus", "core", "vsync";
> -
> - assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
> - <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
> - assigned-clock-rates = <0 0 300000000 19200000>;
> -
> - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
> -
> - ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - port@0 {
> - reg = <0>;
> - dpu_intf1_out: endpoint {
> - remote-endpoint = <&dsi0_in>;
> - };
> - };
> -
> - port@1 {
> - reg = <1>;
> - dpu_intf2_out: endpoint {
> - remote-endpoint = <&dsi1_in>;
> - };
> - };
> - };
> - };
> - };
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-sc7180.yaml
> new file mode 100644
> index 0000000..deb8272
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-sc7180.yaml
> @@ -0,0 +1,123 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dsi-controller-sc7180.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Description of Qualcomm Display DSI controller dt properties.
> +
> +maintainers:
> + - Krishna Manikandan <mkrishn@codeaurora.org>
> +
> +description: |
> + Device tree bindings for DSI controller for SC7180 target.
> +
> +allOf:
> + - $ref: dsi-controller.yaml#
> +
> +properties:
> + compatible:
> + const: qcom,mdss-dsi-ctrl
> +
> + reg:
> + maxItems: 1
> +
> + reg-names:
> + const: dsi_ctrl
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 6
> +
> + clock-names:
> + items:
> + - const: byte
> + - const: byte_intf
> + - const: pixel
> + - const: core
> + - const: iface
> + - const: bus
> +
> + phys:
> + maxItems: 1
> +
> + phy-names:
> + const: dsi
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
These 2 properties aren't needed here.
> +
> + ports: true
Need to define what 'port@0' and 'port@1' are.
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - interrupt-parent
> + - interrupts
> + - clocks
> + - clock-names
> + - phys
> + - phy-names
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
> + #include <dt-bindings/clock/qcom,gcc-sc7180.h>
> +
> + dsi0: dsi@ae94000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0 0x0ae94000 0 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>;
> +
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> +
> + phys = <&dsi_phy>;
> + phy-names = "dsi";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> + };
> +...
> +
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-sdm845.yaml
> new file mode 100644
> index 0000000..264d7c9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-sdm845.yaml
> @@ -0,0 +1,120 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dsi-controller-sdm845.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Description of Qualcomm Display DSI controller dt properties.
> +
> +maintainers:
> + - Krishna Manikandan <mkrishn@codeaurora.org>
> +
> +description: |
> + Device tree bindings for DSI controller for SDM845 target.
> +
> +allOf:
> + - $ref: dsi-controller.yaml#
> +
> +properties:
> + compatible:
> + const: qcom,mdss-dsi-ctrl
> +
> + reg:
> + maxItems: 1
> +
> + reg-names:
> + const: dsi_ctrl
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 6
> +
> + clock-names:
> + items:
> + - const: byte
> + - const: byte_intf
> + - const: pixel
> + - const: core
> + - const: iface
> + - const: bus
> +
> + phys:
> + maxItems: 1
> +
> + phy-names:
> + const: dsi
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> + ports: true
Need to define each port.
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - interrupt-parent
> + - interrupts
> + - clocks
> + - clock-names
> + - phys
> + - phy-names
> + - ports
> +
> +additionalProperties: false
unevaluatedProperties: false
Because DSI bus child nodes defined in dsi-controller.yaml should be
valid too.
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> +
> + dsi0: dsi@ae94000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0 0x0ae94000 0 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> +
> + phys = <&dsi0_phy>;
> + phy-names = "dsi";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> + };
> +...
> +
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller.yaml
> new file mode 100644
> index 0000000..dbec55e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller.yaml
> @@ -0,0 +1,151 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dsi-controller.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Description of Qualcomm Display DSI controller dt properties.
> +
> +maintainers:
> + - Krishna Manikandan <mkrishn@codeaurora.org>
> +
> +description: |
> + Common Device tree bindings for DSI controller.
Not a correct description. We already have a common binding for DSI
controllers and should reference it (dsi-controller.yaml).
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,mdss-dsi-ctrl
> +
> + clocks:
> + maxItems: 6
> +
> + clock-names:
> + description: |
> + Device clock names in the same order as mentioned in clocks property.
> + For DSIv2, we need an additional clock "src" and for DSI6G v2.0
> + onwards we need "byte_intf" clock.
Need a schema list.
> +
> + assigned-clocks:
> + description: Parents of "byte" and "pixel" for the given platform.
How many?
> +
> + assigned-clock-parents:
> + description: |
> + The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
> + Details on clock bindings are mentioned in
> + Documentation/devicetree/bindings/clock/clock-bindings.txt.
> +
> + vdd-supply:
> + description: Phandle to vdd regulator device node.
> +
> + vddio-supply:
> + description: Phandle to vdd-io regulator device node.
> +
> + vdda-supply:
> + description: Phandle to vdda regulator device node.
> +
> + phys:
> + description: Phandle to DSI PHY device node.
> +
> + phy-names:
> + description: Name of the corresponding PHY device.
> +
> + syscon-sfpb:
> + description: A phandle to mmss_sfpb syscon node (only for DSIv2).
Needs a type $ref.
> +
> + # Optional Properties for dsi controller
> + panel@0:
> + description: |
> + Node of panel connected to this DSI controller.
> + See files in Documentation/devicetree/bindings/display/panel/
> + for each supported panel.
Covered by the common binding. Could be a bridge instead BTW.
> +
> + qcom,mdss-mdp-transfer-time-us:
> + description: |
> + Specifies the DSI transfer time for command mode
> + panels in microseconds. Driver uses this number to adjust
> + the clock rate according to the expected transfer time.
> + Increasing this value would slow down the mdp processing
> + and can result in slower performance.
> + Decreasing this value can speed up the mdp processing,
> + but this can also impact power consumption.
> + As a rule this time should not be higher than the time
> + that would be expected with the processing at the
> + DSI link rate since anyways this would be the maximum
> + transfer time that could be achieved.
> + If ping pong split is enabled, this time should not be higher
> + than two times the DSI link rate time.
> + If the property is not specified, then the default value is
> + 14000 us. This is an optional property.
> +
> + qcom,dual-dsi-mode:
> + type: boolean
> + description: |
> + Boolean value indicating if the DSI controller is
> + driving a panel which needs 2 DSI links.
> +
> + qcom,master-dsi:
> + type: boolean
> + description: |
> + Boolean value indicating if the DSI controller is driving
> + the master link of the 2-DSI panel.
> +
> + qcom,sync-dual-dsi:
> + type: boolean
> + description: |
> + Boolean value indicating if the DSI controller is driving a
> + 2-DSI panel whose 2 links need receive command simultaneously.
Dependencies between these 3 properties? If so, use dependencies.
> +
> + pinctrl-names:
> + description: The pin control state names; may be "default" or "sleep".
Sounds like constraints.
> +
> + pinctrl-0:
> + description: The default pinctrl state (active)
> +
> + pinctrl-1:
> + description: The sleep pinctrl state (suspend)
No need to document these 2.
> +
> + ports:
> + type: object
> + description: |
> + Contains DSI controller input and output ports as children, each
> + containing one endpoint subnode as defined in
> + Documentation/devicetree/bindings/graph.txt and
> + Documentation/devicetree/bindings/media/video-interfaces.txt.
> +
> + properties:
> + remote-endpoint:
Not a property in 'ports'
> + description: |
> + For port@0, set to phandle of the connected panel/bridge's
> + input endpoint. For port@1, set to the MDP interface output.
> + See Documentation/devicetree/bindings/graph.txt for
> + device graph info.
> +
> + data-lanes:
> + description: |
> + This describes how the physical DSI data lanes are mapped
> + to the logical lanes on the given platform. The value contained in
> + index n describes what physical lane is mapped to the logical lane n
> + (DATAn, where n lies between 0 and 3). The clock lane position is fixed
> + and can't be changed. Hence, they aren't a part of the DT bindings. See
> + Documentation/devicetree/bindings/media/video-interfaces.txt for
> + more info on the data-lanes property.
> +
> + For example:
> + data-lanes = <3 0 1 2>;
> +
> + The above mapping describes that the logical data lane DATA0 is mapped
> + to the physical data lane DATA3, logical DATA1 to physical DATA0,
> + logic DATA2 to phys DATA1 and logic DATA3 to phys DATA2. There are
> + only a limited number of physical to logical mappings possible.
> + oneOf:
> + - const: <0 1 2 3>
> + - const: <1 2 3 0>
> + - const: <2 3 0 1>
> + - const: <3 0 1 2>
> + - const: <0 3 2 1>
> + - const: <1 0 3 2>
> + - const: <2 1 0 3>
> + - const: <3 2 1 0>
> +
> +...
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-sc7180.yaml
> new file mode 100644
> index 0000000..316b3b7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-sc7180.yaml
> @@ -0,0 +1,75 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dsi-phy-sc7180.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Description of Qualcomm Display DSI PHY dt properties.
> +
> +maintainers:
> + - Krishna Manikandan <mkrishn@codeaurora.org>
> +
> +description: |
> + Device tree bindings for DSI PHY for SC7180 target.
> +
> +allOf:
> + - $ref: dsi-phy.yaml#
> +
> +properties:
> + compatible:
> + const: qcom,dsi-phy-10nm
> +
> + reg:
> + maxItems: 3
> +
> + reg-names:
> + maxItems: 3
> +
> + clocks:
> + maxItems: 2
> +
> + clock-names:
> + items:
> + - const: iface
> + - const: ref
> +
> + "#clock-cells":
> + const: 1
> +
> + "#phy-cells":
> + const: 0
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
> + #include <dt-bindings/clock/qcom,gcc-sc7180.h>
> + #include <dt-bindings/clock/qcom,rpmh.h>
> +
> + dsi_phy: dsi-phy@ae94400 {
> + compatible = "qcom,dsi-phy-10nm";
> + reg = <0 0x0ae94400 0 0x200>,
> + <0 0x0ae94600 0 0x280>,
> + <0 0x0ae94a00 0 0x1e0>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> + };
> +...
> +
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-sdm845.yaml
> new file mode 100644
> index 0000000..0c9d19a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-sdm845.yaml
> @@ -0,0 +1,76 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dsi-phy-sdm845.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Description of Qualcomm Display DSI PHY dt properties.
> +
> +maintainers:
> + - Krishna Manikandan <mkrishn@codeaurora.org>
> +
> +description: |
> + Device tree bindings for DSI PHY for SDM845 target.
> +
> +allOf:
> + - $ref: dsi-phy.yaml#
> +
> +properties:
> + compatible:
> + const: qcom,dsi-phy-10nm
> +
> + reg:
> + maxItems: 3
> +
> + reg-names:
> + maxItems: 3
> +
> + clocks:
> + maxItems: 2
> +
> + clock-names:
> + items:
> + - const: iface
> + - const: ref
> +
> + "#clock-cells":
> + const: 1
> +
> + "#phy-cells":
> + const: 0
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> + #include <dt-bindings/clock/qcom,rpmh.h>
> +
> + dsi0_phy: dsi-phy@ae94400 {
> + compatible = "qcom,dsi-phy-10nm";
> + reg = <0 0x0ae94400 0 0x200>,
> + <0 0x0ae94600 0 0x280>,
> + <0 0x0ae94a00 0 0x1e0>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
Where's vdds-supply you say is required?
> +
> + };
> +...
> +
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy.yaml
> new file mode 100644
> index 0000000..46ac96f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy.yaml
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dsi-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Description of Qualcomm Display DSI PHY dt properties.
> +
> +maintainers:
> + - Krishna Manikandan <mkrishn@codeaurora.org>
> +
> +description: |
> + Common Device tree bindings for DSI PHY.
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: qcom,dsi-phy-28nm-hpm
> + - const: qcom,dsi-phy-28nm-lp
> + - const: qcom,dsi-phy-20nm
> + - const: qcom,dsi-phy-28nm-8960
> + - const: qcom,dsi-phy-14nm
> + - const: qcom,dsi-phy-10nm
> + - const: qcom,dsi-phy-10nm-8998
> +
> + reg-names:
> + description: Name of register regions.
> + oneOf:
> + - description: |
> + Following regions are required for DSI 28nm HPM/LP/8960 PHYs and
> + 20nm PHY.
> + items:
> + - const: dsi_pll
> + - const: dsi_phy
> + - const: dsi_phy_regulator
> +
> + - description: |
> + Following regions are required for DSI 14nm and 10nm PHYs:
> + items:
> + - const: dsi_phy
> + - const: dsi_phy_lane
> + - const: dsi_pll
> +
> + clock-cells:
> + description: |
> + The DSI PHY block acts as a clock provider, creating
> + 2 clocks: A byte clock (index 0), and a pixel clock (index 1).
> + const: 1
> +
> + power-domains:
> + description: Should be <&mmcc MDSS_GDSC>.
How many?
> +
> + clocks:
> + maxItems: 2
> +
> + clock-names:
> + description: |
> + The following clocks are required.
> + "iface"
> + "ref" (only required for new DTS files/entries)
Sounds like constraints.
> +
> + vddio-supply:
> + description: |
> + Phandle to vdd-io regulator device node. Required for 28nm HPM/LP,
> + 28nm 8960 PHYs and 20nm PHY.
I'm not sure a common file helps here with all these free form text
constraints. We can't validate whether having 'vddio-supply' is correct
or not.
> +
> + vcca-supply:
> + description: |
> + Phandle to vcca regulator device node. Required for 20nm PHY and
> + 10nm PHY.
> +
> + vdds-supply:
> + description: |
> + Phandle to vdds regulator device node. Required for 10nm PHY.
> +
> + qcom,dsi-phy-regulator-ldo-mode:
> + type: boolean
> + description: |
> + Boolean value indicating if the LDO mode PHY regulator is wanted (optional).
> +
> +...
> +
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt
> deleted file mode 100644
> index af95586..0000000
> --- a/Documentation/devicetree/bindings/display/msm/dsi.txt
> +++ /dev/null
> @@ -1,246 +0,0 @@
> -Qualcomm Technologies Inc. adreno/snapdragon DSI output
> -
> -DSI Controller:
> -Required properties:
> -- compatible:
> - * "qcom,mdss-dsi-ctrl"
> -- reg: Physical base address and length of the registers of controller
> -- reg-names: The names of register regions. The following regions are required:
> - * "dsi_ctrl"
> -- interrupts: The interrupt signal from the DSI block.
> -- power-domains: Should be <&mmcc MDSS_GDSC>.
> -- clocks: Phandles to device clocks.
> -- clock-names: the following clocks are required:
> - * "mdp_core"
> - * "iface"
> - * "bus"
> - * "core_mmss"
> - * "byte"
> - * "pixel"
> - * "core"
> - For DSIv2, we need an additional clock:
> - * "src"
> - For DSI6G v2.0 onwards, we need also need the clock:
> - * "byte_intf"
> -- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
> -- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
> - by a DSI PHY block. See [1] for details on clock bindings.
> -- vdd-supply: phandle to vdd regulator device node
> -- vddio-supply: phandle to vdd-io regulator device node
> -- vdda-supply: phandle to vdda regulator device node
> -- phys: phandle to DSI PHY device node
> -- phy-names: the name of the corresponding PHY device
> -- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
> -- ports: Contains 2 DSI controller ports as child nodes. Each port contains
> - an endpoint subnode as defined in [2] and [3].
> -
> -Optional properties:
> -- panel@0: Node of panel connected to this DSI controller.
> - See files in [4] for each supported panel.
> -- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
> - driving a panel which needs 2 DSI links.
> -- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
> - the master link of the 2-DSI panel.
> -- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
> - driving a 2-DSI panel whose 2 links need receive command simultaneously.
> -- pinctrl-names: the pin control state names; should contain "default"
> -- pinctrl-0: the default pinctrl state (active)
> -- pinctrl-n: the "sleep" pinctrl state
> -- ports: contains DSI controller input and output ports as children, each
> - containing one endpoint subnode.
> -
> - DSI Endpoint properties:
> - - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
> - input endpoint. For port@1, set to the MDP interface output. See [2] for
> - device graph info.
> -
> - - data-lanes: this describes how the physical DSI data lanes are mapped
> - to the logical lanes on the given platform. The value contained in
> - index n describes what physical lane is mapped to the logical lane n
> - (DATAn, where n lies between 0 and 3). The clock lane position is fixed
> - and can't be changed. Hence, they aren't a part of the DT bindings. See
> - [3] for more info on the data-lanes property.
> -
> - For example:
> -
> - data-lanes = <3 0 1 2>;
> -
> - The above mapping describes that the logical data lane DATA0 is mapped to
> - the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
> - to phys DATA1 and logic DATA3 to phys DATA2.
> -
> - There are only a limited number of physical to logical mappings possible:
> - <0 1 2 3>
> - <1 2 3 0>
> - <2 3 0 1>
> - <3 0 1 2>
> - <0 3 2 1>
> - <1 0 3 2>
> - <2 1 0 3>
> - <3 2 1 0>
> -
> -DSI PHY:
> -Required properties:
> -- compatible: Could be the following
> - * "qcom,dsi-phy-28nm-hpm"
> - * "qcom,dsi-phy-28nm-lp"
> - * "qcom,dsi-phy-20nm"
> - * "qcom,dsi-phy-28nm-8960"
> - * "qcom,dsi-phy-14nm"
> - * "qcom,dsi-phy-10nm"
> - * "qcom,dsi-phy-10nm-8998"
> -- reg: Physical base address and length of the registers of PLL, PHY. Some
> - revisions require the PHY regulator base address, whereas others require the
> - PHY lane base address. See below for each PHY revision.
> -- reg-names: The names of register regions. The following regions are required:
> - For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
> - * "dsi_pll"
> - * "dsi_phy"
> - * "dsi_phy_regulator"
> - For DSI 14nm and 10nm PHYs:
> - * "dsi_pll"
> - * "dsi_phy"
> - * "dsi_phy_lane"
> -- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
> - 2 clocks: A byte clock (index 0), and a pixel clock (index 1).
> -- power-domains: Should be <&mmcc MDSS_GDSC>.
> -- clocks: Phandles to device clocks. See [1] for details on clock bindings.
> -- clock-names: the following clocks are required:
> - * "iface"
> - * "ref" (only required for new DTS files/entries)
> - For 28nm HPM/LP, 28nm 8960 PHYs:
> -- vddio-supply: phandle to vdd-io regulator device node
> - For 20nm PHY:
> -- vddio-supply: phandle to vdd-io regulator device node
> -- vcca-supply: phandle to vcca regulator device node
> - For 14nm PHY:
> -- vcca-supply: phandle to vcca regulator device node
> - For 10nm PHY:
> -- vdds-supply: phandle to vdds regulator device node
> -
> -Optional properties:
> -- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
> - regulator is wanted.
> -- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
> - panels in microseconds. Driver uses this number to adjust
> - the clock rate according to the expected transfer time.
> - Increasing this value would slow down the mdp processing
> - and can result in slower performance.
> - Decreasing this value can speed up the mdp processing,
> - but this can also impact power consumption.
> - As a rule this time should not be higher than the time
> - that would be expected with the processing at the
> - dsi link rate since anyways this would be the maximum
> - transfer time that could be achieved.
> - If ping pong split is enabled, this time should not be higher
> - than two times the dsi link rate time.
> - If the property is not specified, then the default value is 14000 us.
> -
> -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> -[2] Documentation/devicetree/bindings/graph.txt
> -[3] Documentation/devicetree/bindings/media/video-interfaces.txt
> -[4] Documentation/devicetree/bindings/display/panel/
> -
> -Example:
> - dsi0: dsi@fd922800 {
> - compatible = "qcom,mdss-dsi-ctrl";
> - qcom,dsi-host-index = <0>;
> - interrupt-parent = <&mdp>;
> - interrupts = <4 0>;
> - reg-names = "dsi_ctrl";
> - reg = <0xfd922800 0x200>;
> - power-domains = <&mmcc MDSS_GDSC>;
> - clock-names =
> - "bus",
> - "byte",
> - "core",
> - "core_mmss",
> - "iface",
> - "mdp_core",
> - "pixel";
> - clocks =
> - <&mmcc MDSS_AXI_CLK>,
> - <&mmcc MDSS_BYTE0_CLK>,
> - <&mmcc MDSS_ESC0_CLK>,
> - <&mmcc MMSS_MISC_AHB_CLK>,
> - <&mmcc MDSS_AHB_CLK>,
> - <&mmcc MDSS_MDP_CLK>,
> - <&mmcc MDSS_PCLK0_CLK>;
> -
> - assigned-clocks =
> - <&mmcc BYTE0_CLK_SRC>,
> - <&mmcc PCLK0_CLK_SRC>;
> - assigned-clock-parents =
> - <&dsi_phy0 0>,
> - <&dsi_phy0 1>;
> -
> - vdda-supply = <&pma8084_l2>;
> - vdd-supply = <&pma8084_l22>;
> - vddio-supply = <&pma8084_l12>;
> -
> - phys = <&dsi_phy0>;
> - phy-names ="dsi-phy";
> -
> - qcom,dual-dsi-mode;
> - qcom,master-dsi;
> - qcom,sync-dual-dsi;
> -
> - qcom,mdss-mdp-transfer-time-us = <12000>;
> -
> - pinctrl-names = "default", "sleep";
> - pinctrl-0 = <&dsi_active>;
> - pinctrl-1 = <&dsi_suspend>;
> -
> - ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - port@0 {
> - reg = <0>;
> - dsi0_in: endpoint {
> - remote-endpoint = <&mdp_intf1_out>;
> - };
> - };
> -
> - port@1 {
> - reg = <1>;
> - dsi0_out: endpoint {
> - remote-endpoint = <&panel_in>;
> - data-lanes = <0 1 2 3>;
> - };
> - };
> - };
> -
> - panel: panel@0 {
> - compatible = "sharp,lq101r1sx01";
> - reg = <0>;
> - link2 = <&secondary>;
> -
> - power-supply = <...>;
> - backlight = <...>;
> -
> - port {
> - panel_in: endpoint {
> - remote-endpoint = <&dsi0_out>;
> - };
> - };
> - };
> - };
> -
> - dsi_phy0: dsi-phy@fd922a00 {
> - compatible = "qcom,dsi-phy-28nm-hpm";
> - qcom,dsi-phy-index = <0>;
> - reg-names =
> - "dsi_pll",
> - "dsi_phy",
> - "dsi_phy_regulator";
> - reg = <0xfd922a00 0xd4>,
> - <0xfd922b00 0x2b0>,
> - <0xfd922d80 0x7b>;
> - clock-names = "iface";
> - clocks = <&mmcc MDSS_AHB_CLK>;
> - #clock-cells = <1>;
> - vddio-supply = <&pma8084_l12>;
> -
> - qcom,dsi-phy-regulator-ldo-mode;
> - };
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH v10 06/20] dt-bindings: mtd: Document nand-ecc-engine
From: Rob Herring @ 2020-06-03 22:16 UTC (permalink / raw)
To: Miquel Raynal
Cc: Boris Brezillon, Tudor Ambarus, Thomas Petazzoni, linux-mtd,
Vignesh Raghavendra, Mason Yang, linux-arm-kernel,
Richard Weinberger, Julien Su, Mark Rutland, devicetree,
Rob Herring
In-Reply-To: <20200603175759.19948-7-miquel.raynal@bootlin.com>
On Wed, 03 Jun 2020 19:57:45 +0200, Miquel Raynal wrote:
> This property is needed to precisely point to the hardware ECC engine
> to use when there are several of them available. Here, hardware also
> refers to the on-die possibility.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> .../devicetree/bindings/mtd/nand-controller.yaml | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
Documentation/devicetree/bindings/mtd/nand-controller.yaml: while scanning for the next token
found character that cannot start any token
in "<unicode string>", line 62, column 1
Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/mtd/nand-controller.example.dts' failed
make[1]: *** [Documentation/devicetree/bindings/mtd/nand-controller.example.dts] Error 1
make[1]: *** Waiting for unfinished jobs....
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/mtd/nand-controller.yaml: ignoring, error parsing file
warning: no schema found in file: ./Documentation/devicetree/bindings/mtd/nand-controller.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/mtd/nand-controller.yaml: ignoring, error parsing file
warning: no schema found in file: ./Documentation/devicetree/bindings/mtd/nand-controller.yaml
Makefile:1300: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1303116
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.
^ permalink raw reply
* Re: [PATCH v13 3/7] dt-bindings: clock: Add documentation for X1830 bindings.
From: Rob Herring @ 2020-06-03 21:58 UTC (permalink / raw)
To: Stephen Boyd
Cc: Zhou Yanjie, Michael Turquette, aric.pzqi, rick.tyliu, yanfei.li,
zhenwenjin, sernia.zhou, Paul Cercueil, dongsheng.qiu, devicetree,
linux-clk, linux-kernel@vger.kernel.org
In-Reply-To: <159078668338.69627.5841582436445900180@swboyd.mtv.corp.google.com>
On Fri, May 29, 2020 at 3:11 PM Stephen Boyd <sboyd@kernel.org> wrote:
>
> Quoting Rob Herring (2020-05-29 12:14:31)
> >
> > Acked-by: Rob Herring <robh@kernel.org>
>
> Please apply to bindings tree Rob. The yaml conversion is in your tree.
Done.
Rob
^ permalink raw reply
* Re: [PATCH 22/28] dt-bindings: i2c: Convert i2c-pxa to json-schema
From: Wolfram Sang @ 2020-06-03 20:41 UTC (permalink / raw)
To: Lubomir Rintel
Cc: Rob Herring, Linus Walleij, Bartosz Golaszewski, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Mauro Carvalho Chehab, Ulf Hansson,
Kishon Vijay Abraham I, Alessandro Zummo, Alexandre Belloni,
Greg Kroah-Hartman, Mark Brown, Daniel Lezcano, Andrew Lunn,
Gregory Clement, Daniel Mack, Haojian Zhuang, Robert Jarzmik,
devicetree, linux-kernel, linux-gpio, linux-i2c, linux-media,
linux-mmc, linux-rtc, linux-serial, linux-spi, linux-usb
In-Reply-To: <20200317093922.20785-23-lkundrak@v3.sk>
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On Tue, Mar 17, 2020 at 10:39:16AM +0100, Lubomir Rintel wrote:
> A conversion of the i2c-pxa binding to DT schema format using json-schema.
>
> This also cleans ups some errors in the binding: The compatible string
> description suggested that "mmp" in "mrvl,mmp-twsi" is to be substituted
> with a processor model, which wouldn't be a right thing to do and indeed
> nobody seems to have been doing that. There also was "Recommended
> properties" section that included optional as well as mandatory
> properties. Missing mandatory properties were added to the example.
>
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Waiting for an ack from someone with DT-YAML experience here.
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^ permalink raw reply
* Re: [PATCH v14 0/3] i2c: npcm7xx: add NPCM i2c controller driver
From: Wolfram Sang @ 2020-06-03 20:25 UTC (permalink / raw)
To: Tali Perry
Cc: ofery, brendanhiggins, avifishman70, tmaimon77, kfting, venture,
yuenn, benjaminfair, robh+dt, andriy.shevchenko, linux-arm-kernel,
linux-i2c, openbmc, devicetree, linux-kernel, kbuild test robot
In-Reply-To: <20200527200820.47359-1-tali.perry1@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 876 bytes --]
On Wed, May 27, 2020 at 11:08:17PM +0300, Tali Perry wrote:
> This patch set adds i2c controller support
> for the Nuvoton NPCM Baseboard Management Controller (BMC).
>
> NPCM7xx includes 16 I2C controllers. This driver operates the controller.
> This module also includes a slave mode.
>
> ---
> v14 -> v13:
> - Fix yaml example: add missing include.
> - Replace all udelay to usleep_range, except one which is called from
> irq.
> - Fix compilation error (module_platfrom_init conflict).
> - debugfs counters always updated. Counting till max value,
> then stop counting.
> - Rename bus-frequency to clock-frequency.
> - Remove unused variables.
I don't have time for a deeper review, but from what I can tell this
driver is good to go and we can fix things incrementally from now on.
Applied to for-next (will go into 5.8), thanks!
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^ permalink raw reply
* [RFC 4/4] regulator: lp87565: add LP87524-Q1 variant
From: Luca Ceresoli @ 2020-06-03 20:03 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown
Cc: Luca Ceresoli, devicetree, linux-kernel, Lee Jones, Rob Herring,
Keerthy, Axel Lin
In-Reply-To: <20200603200319.16184-1-luca@lucaceresoli.net>
Add support for the LP87524B/J/P-Q1 Four 4-MHz Buck Converter. This is a
variant of the LP87565 having 4 single-phase outputs and up to 10 A of
total output current.
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
---
drivers/mfd/lp87565.c | 4 ++++
include/linux/mfd/lp87565.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/mfd/lp87565.c b/drivers/mfd/lp87565.c
index 4a5c8ade4ae0..cc1072927f6d 100644
--- a/drivers/mfd/lp87565.c
+++ b/drivers/mfd/lp87565.c
@@ -26,6 +26,10 @@ static const struct mfd_cell lp87565_cells[] = {
static const struct of_device_id of_lp87565_match_table[] = {
{ .compatible = "ti,lp87565", },
+ {
+ .compatible = "ti,lp87524-q1",
+ .data = (void *)LP87565_DEVICE_TYPE_LP87524_Q1,
+ },
{
.compatible = "ti,lp87565-q1",
.data = (void *)LP87565_DEVICE_TYPE_LP87565_Q1,
diff --git a/include/linux/mfd/lp87565.h b/include/linux/mfd/lp87565.h
index ce965354bbad..ad240f2d0d3f 100644
--- a/include/linux/mfd/lp87565.h
+++ b/include/linux/mfd/lp87565.h
@@ -14,6 +14,7 @@
enum lp87565_device_type {
LP87565_DEVICE_TYPE_UNKNOWN = 0,
+ LP87565_DEVICE_TYPE_LP87524_Q1,
LP87565_DEVICE_TYPE_LP87561_Q1,
LP87565_DEVICE_TYPE_LP87565_Q1,
};
--
2.27.0
^ permalink raw reply related
* [RFC 0/4] regulator: lp87565: ignore ENx pins and add LP87524-Q1
From: Luca Ceresoli @ 2020-06-03 20:03 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown
Cc: Luca Ceresoli, devicetree, linux-kernel, Lee Jones, Rob Herring,
Keerthy, Axel Lin
Hi,
the first patch in this series is a small but significant variation in how
the lp87565 driver enables the output rails, allow the kernel to always
know when it is enabling an output. However it can change existing
behaviour (depending on the hardware setup) and thus it should be carefully
evaluated.
The following patches are a fairly straightforward addition of a new chip
variant along with some DT bindings cleanup.
Luca
Luca Ceresoli (4):
regulator: lp87565: enable voltage regardless of ENx pin
regulator: lp87565: dt: remove duplicated section
regulator: lp87565: dt: add LP87524-Q1 variant
regulator: lp87565: add LP87524-Q1 variant
.../devicetree/bindings/mfd/lp87565.txt | 66 ++++++++++++++-----
drivers/mfd/lp87565.c | 4 ++
drivers/regulator/lp87565-regulator.c | 21 +++++-
include/linux/mfd/lp87565.h | 1 +
4 files changed, 73 insertions(+), 19 deletions(-)
--
2.27.0
^ permalink raw reply
* [RFC 3/4] regulator: lp87565: dt: add LP87524-Q1 variant
From: Luca Ceresoli @ 2020-06-03 20:03 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown
Cc: Luca Ceresoli, devicetree, linux-kernel, Lee Jones, Rob Herring,
Keerthy, Axel Lin
In-Reply-To: <20200603200319.16184-1-luca@lucaceresoli.net>
Add the LP87524-Q1 to the lp87565 bindings document along with an example.
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
---
.../devicetree/bindings/mfd/lp87565.txt | 47 ++++++++++++++++++-
1 file changed, 46 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mfd/lp87565.txt b/Documentation/devicetree/bindings/mfd/lp87565.txt
index b75ae23a1ef3..839eac6b75c2 100644
--- a/Documentation/devicetree/bindings/mfd/lp87565.txt
+++ b/Documentation/devicetree/bindings/mfd/lp87565.txt
@@ -1,7 +1,8 @@
TI LP87565 PMIC MFD driver
Required properties:
- - compatible: one of "ti,lp87565", "ti,lp87565-q1", "ti,lp87561-q1"
+ - compatible: one of "ti,lp87565", "ti,lp87565-q1", "ti,lp87561-q1",
+ "ti,lp87524-q1"
- reg: I2C slave address.
- gpio-controller: Marks the device node as a GPIO Controller.
- #gpio-cells: Should be two. The first cell is the pin number and
@@ -64,3 +65,47 @@ lp87561_pmic: pmic@62 {
};
};
};
+
+Example for the TI LP87524-Q1 PMIC (four 1-phase output configuration):
+
+lp87524_pmic: pmic@60 {
+ compatible = "ti,lp87524-q1";
+ reg = <0x60>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ buck0-in-supply = <&vdd_5v0>;
+ buck1-in-supply = <&vdd_5v0>;
+ buck2-in-supply = <&vdd_5v0>;
+ buck3-in-supply = <&vdd_5v0>;
+
+ regulators {
+ buck0_reg: buck0 {
+ regulator-name = "buck0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ buck1_reg: buck1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ };
+
+ buck2_reg: buck2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <950000>;
+ regulator-always-on;
+ };
+
+ buck3_reg: buck3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ };
+};
--
2.27.0
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