* [PATCH v3 08/16] clk: samsung: fsd: Add cmu_imem block clock information
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar, linux-fsd,
Arjun K V, Tauseef Nomani
In-Reply-To: <20220121172840.12121-1-alim.akhtar@samsung.com>
Adds cmu_imem clock related code, imem block contains IPs
like WDT, DMA, TMU etc, these clocks are required for such
IP function.
Cc: linux-fsd@tesla.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Arjun K V <arjun.kv@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Tauseef Nomani <tauseef.n@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/clk/samsung/clk-fsd.c | 283 ++++++++++++++++++++++++++++++++++
1 file changed, 283 insertions(+)
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
index 95367d151ab6..d39ec207213e 100644
--- a/drivers/clk/samsung/clk-fsd.c
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -1144,6 +1144,289 @@ static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
.clk_name = "dout_cmu_fsys1_shared0div4",
};
+/* Register Offset definitions for CMU_IMEM (0x10010000) */
+#define PLL_CON0_CLK_IMEM_ACLK 0x100
+#define PLL_CON0_CLK_IMEM_INTMEMCLK 0x120
+#define PLL_CON0_CLK_IMEM_TCUCLK 0x140
+#define DIV_OSCCLK_IMEM_TMUTSCLK 0x1800
+#define GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK 0x2000
+#define GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO 0x2004
+#define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2008
+#define GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK 0x200c
+#define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK 0x2010
+#define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 0x2014
+#define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK 0x2018
+#define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 0x201c
+#define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK 0x2020
+#define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 0x2024
+#define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK 0x2028
+#define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 0x202c
+#define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK 0x2030
+#define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 0x2034
+#define GAT_IMEM_WDT0_IPCLKPORT_CLK 0x2038
+#define GAT_IMEM_WDT1_IPCLKPORT_CLK 0x203c
+#define GAT_IMEM_WDT2_IPCLKPORT_CLK 0x2040
+#define GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM 0x2044
+#define GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM 0x2048
+#define GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM 0x204c
+#define GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS 0x2050
+#define GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS 0x2054
+#define GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS 0x2058
+#define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM 0x205c
+#define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS 0x2060
+#define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM 0x2064
+#define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS 0x2068
+#define GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK 0x206c
+#define GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK 0x2070
+#define GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK 0x2074
+#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK 0x2078
+#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK 0x207c
+#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK 0x2080
+#define GAT_IMEM_DMA0_IPCLKPORT_ACLK 0x2084
+#define GAT_IMEM_DMA1_IPCLKPORT_ACLK 0x2088
+#define GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK 0x208c
+#define GAT_IMEM_GIC_IPCLKPORT_CLK 0x2090
+#define GAT_IMEM_INTMEM_IPCLKPORT_ACLK 0x2094
+#define GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK 0x2098
+#define GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK 0x209c
+#define GAT_IMEM_MCT_IPCLKPORT_PCLK 0x20a0
+#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D 0x20a4
+#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU 0x20a8
+#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P 0x20ac
+#define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK 0x20b0
+#define GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK 0x20b4
+#define GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK 0x20b8
+#define GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK 0x20bc
+#define GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK 0x20c0
+#define GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK 0x20c4
+#define GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK 0x20c8
+#define GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK 0x20cc
+#define GAT_IMEM_TCU_IPCLKPORT_ACLK 0x20d0
+#define GAT_IMEM_WDT0_IPCLKPORT_PCLK 0x20d4
+#define GAT_IMEM_WDT1_IPCLKPORT_PCLK 0x20d8
+#define GAT_IMEM_WDT2_IPCLKPORT_PCLK 0x20dc
+
+static const unsigned long imem_clk_regs[] __initconst = {
+ PLL_CON0_CLK_IMEM_ACLK,
+ PLL_CON0_CLK_IMEM_INTMEMCLK,
+ PLL_CON0_CLK_IMEM_TCUCLK,
+ DIV_OSCCLK_IMEM_TMUTSCLK,
+ GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK,
+ GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO,
+ GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
+ GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK,
+ GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK,
+ GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS,
+ GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK,
+ GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS,
+ GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK,
+ GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS,
+ GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK,
+ GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS,
+ GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK,
+ GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS,
+ GAT_IMEM_WDT0_IPCLKPORT_CLK,
+ GAT_IMEM_WDT1_IPCLKPORT_CLK,
+ GAT_IMEM_WDT2_IPCLKPORT_CLK,
+ GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM,
+ GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM,
+ GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM,
+ GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS,
+ GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS,
+ GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS,
+ GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM,
+ GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS,
+ GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM,
+ GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS,
+ GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK,
+ GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK,
+ GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK,
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK,
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK,
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK,
+ GAT_IMEM_DMA0_IPCLKPORT_ACLK,
+ GAT_IMEM_DMA1_IPCLKPORT_ACLK,
+ GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK,
+ GAT_IMEM_GIC_IPCLKPORT_CLK,
+ GAT_IMEM_INTMEM_IPCLKPORT_ACLK,
+ GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK,
+ GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK,
+ GAT_IMEM_MCT_IPCLKPORT_PCLK,
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D,
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU,
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P,
+ GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK,
+ GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK,
+ GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK,
+ GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK,
+ GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK,
+ GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK,
+ GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK,
+ GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK,
+ GAT_IMEM_TCU_IPCLKPORT_ACLK,
+ GAT_IMEM_WDT0_IPCLKPORT_PCLK,
+ GAT_IMEM_WDT1_IPCLKPORT_PCLK,
+ GAT_IMEM_WDT2_IPCLKPORT_PCLK,
+};
+
+PNAME(mout_imem_clk_imem_tcuclk_p) = { "fin_pll", "dout_cmu_imem_tcuclk" };
+PNAME(mout_imem_clk_imem_aclk_p) = { "fin_pll", "dout_cmu_imem_aclk" };
+PNAME(mout_imem_clk_imem_intmemclk_p) = { "fin_pll", "dout_cmu_imem_dmaclk" };
+
+static const struct samsung_mux_clock imem_mux_clks[] __initconst = {
+ MUX(0, "mout_imem_clk_imem_tcuclk", mout_imem_clk_imem_tcuclk_p,
+ PLL_CON0_CLK_IMEM_TCUCLK, 4, 1),
+ MUX(0, "mout_imem_clk_imem_aclk", mout_imem_clk_imem_aclk_p, PLL_CON0_CLK_IMEM_ACLK, 4, 1),
+ MUX(0, "mout_imem_clk_imem_intmemclk", mout_imem_clk_imem_intmemclk_p,
+ PLL_CON0_CLK_IMEM_INTMEMCLK, 4, 1),
+};
+
+static const struct samsung_div_clock imem_div_clks[] __initconst = {
+ DIV(0, "dout_imem_oscclk_imem_tmutsclk", "fin_pll", DIV_OSCCLK_IMEM_TMUTSCLK, 0, 4),
+};
+
+static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
+ GATE(0, "imem_imem_cmu_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_otp_con_top_ipclkport_i_oscclk", "fin_pll",
+ GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tmu_top_ipclkport_i_clk", "fin_pll",
+ GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tmu_gt_ipclkport_i_clk", "fin_pll",
+ GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tmu_cpu0_ipclkport_i_clk", "fin_pll",
+ GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tmu_gpu_ipclkport_i_clk", "fin_pll",
+ GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_mct_ipclkport_oscclk__alo", "fin_pll",
+ GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_wdt0_ipclkport_clk", "fin_pll",
+ GAT_IMEM_WDT0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_wdt1_ipclkport_clk", "fin_pll",
+ GAT_IMEM_WDT1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_wdt2_ipclkport_clk", "fin_pll",
+ GAT_IMEM_WDT2_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu0_ipclkport_i_clk_ts",
+ "dout_imem_oscclk_imem_tmutsclk",
+ GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu2_ipclkport_i_clk_ts",
+ "dout_imem_oscclk_imem_tmutsclk",
+ GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, "imem_tmu_gpu_ipclkport_i_clk_ts",
+ "dout_imem_oscclk_imem_tmutsclk",
+ GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, "imem_tmu_gt_ipclkport_i_clk_ts",
+ "dout_imem_oscclk_imem_tmutsclk",
+ GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, "imem_tmu_top_ipclkport_i_clk_ts",
+ "dout_imem_oscclk_imem_tmutsclk",
+ GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_adm_axi4st_i0_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_adm_axi4st_i1_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_adm_axi4st_i2_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ads_axi4st_i0_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ads_axi4st_i1_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ads_axi4st_i2_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_async_dma0_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_async_dma0_ipclkport_pclks", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_async_dma1_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_async_dma1_ipclkport_pclks", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_axi2apb_imemp0_ipclkport_aclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_axi2apb_imemp1_ipclkport_aclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_bus_d_imem_ipclkport_mainclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_bus_p_imem_ipclkport_mainclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_bus_p_imem_ipclkport_pericclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_bus_p_imem_ipclkport_tcuclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_DMA0_IPCLKPORT_ACLK, "imem_dma0_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0),
+ GATE(IMEM_DMA1_IPCLKPORT_ACLK, "imem_dma1_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0),
+ GATE(0, "imem_gic500_input_sync_ipclkport_clk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_gic_ipclkport_clk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_GIC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_intmem_ipclkport_aclk", "mout_imem_clk_imem_intmemclk",
+ GAT_IMEM_INTMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_mailbox_scs_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_mailbox_sms_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_MCT_PCLK, "imem_mct_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_MCT_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_d",
+ "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_tcu",
+ "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psoc_imem__clk_imem_p", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_otp_con_top_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_rstnsync_aclk_ipclkport_clk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_rstnsync_oscclk_ipclkport_clk", "fin_pll",
+ GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_rstnsync_intmemclk_ipclkport_clk", "mout_imem_clk_imem_intmemclk",
+ GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_rstnsync_tcuclk_ipclkport_clk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_sfrif_tmu0_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_sfrif_tmu1_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tmu_cpu2_ipclkport_i_clk", "fin_pll",
+ GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_sysreg_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tbu_imem_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tcu_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_TCU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_WDT0_IPCLKPORT_PCLK, "imem_wdt0_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_WDT0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_WDT1_IPCLKPORT_PCLK, "imem_wdt1_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_WDT1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_WDT2_IPCLKPORT_PCLK, "imem_wdt2_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_WDT2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info imem_cmu_info __initconst = {
+ .mux_clks = imem_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(imem_mux_clks),
+ .div_clks = imem_div_clks,
+ .nr_div_clks = ARRAY_SIZE(imem_div_clks),
+ .gate_clks = imem_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(imem_gate_clks),
+ .nr_clk_ids = IMEM_NR_CLK,
+ .clk_regs = imem_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(imem_clk_regs),
+};
+
+static void __init fsd_clk_imem_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &imem_cmu_info);
+}
+
+CLK_OF_DECLARE(fsd_clk_imem, "tesla,fsd-clock-imem", fsd_clk_imem_init);
+
/**
* fsd_cmu_probe - Probe function for FSD platform clocks
* @pdev: Pointer to platform device
--
2.25.1
^ permalink raw reply related
* [PATCH v3 07/16] clk: samsung: fsd: Add cmu_fsys1 clock information
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar, linux-fsd,
Ajay Kumar
In-Reply-To: <20220121172840.12121-1-alim.akhtar@samsung.com>
Adds cmu_fsys1 block clock information which are needed
for PCIe IPs in block FSYS1.
Cc: linux-fsd@tesla.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/clk/samsung/clk-fsd.c | 175 ++++++++++++++++++++++++++++++++++
1 file changed, 175 insertions(+)
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
index 8062afab75e3..95367d151ab6 100644
--- a/drivers/clk/samsung/clk-fsd.c
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -972,6 +972,178 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
.clk_name = "dout_cmu_fsys0_shared1div4",
};
+/* Register Offset definitions for CMU_FSYS1 (0x16810000) */
+#define PLL_CON0_ACLK_FSYS1_BUSP_MUX 0x100
+#define PLL_CON0_PCLKL_FSYS1_BUSP_MUX 0x180
+#define DIV_CLK_FSYS1_PHY0_OSCCLK 0x1800
+#define DIV_CLK_FSYS1_PHY1_OSCCLK 0x1804
+#define GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2000
+#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK 0x2004
+#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK 0x2008
+#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK 0x200c
+#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL 0x202c
+#define GAT_FSYS1_PHY0_OSCCLLK 0x2034
+#define GAT_FSYS1_PHY1_OSCCLK 0x2038
+#define GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK 0x203c
+#define GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK 0x2040
+#define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK 0x2048
+#define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK 0x204c
+#define GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK 0x2054
+#define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0 0x205c
+#define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0 0x2064
+#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK 0x206c
+#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK 0x2070
+#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK 0x2074
+#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK 0x2078
+#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK 0x207c
+#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK 0x2080
+#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK 0x2084
+#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK 0x2088
+#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK 0x208c
+#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK 0x20a4
+#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL 0x20a8
+#define GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK 0x20b4
+#define GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK 0x20b8
+
+static const unsigned long fsys1_clk_regs[] __initconst = {
+ PLL_CON0_ACLK_FSYS1_BUSP_MUX,
+ PLL_CON0_PCLKL_FSYS1_BUSP_MUX,
+ DIV_CLK_FSYS1_PHY0_OSCCLK,
+ DIV_CLK_FSYS1_PHY1_OSCCLK,
+ GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK,
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK,
+ GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK,
+ GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL,
+ GAT_FSYS1_PHY0_OSCCLLK,
+ GAT_FSYS1_PHY1_OSCCLK,
+ GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK,
+ GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK,
+ GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK,
+ GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK,
+ GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK,
+ GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0,
+ GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0,
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK,
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK,
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK,
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK,
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK,
+ GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK,
+ GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK,
+ GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK,
+ GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK,
+ GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK,
+ GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL,
+ GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK,
+ GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK,
+};
+
+static const struct samsung_fixed_rate_clock fsys1_fixed_clks[] __initconst = {
+ FRATE(0, "clk_fsys1_phy0_ref", NULL, 0, 100000000),
+ FRATE(0, "clk_fsys1_phy1_ref", NULL, 0, 100000000),
+};
+
+/* List of parent clocks for Muxes in CMU_FSYS1 */
+PNAME(mout_fsys1_pclkl_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div8" };
+PNAME(mout_fsys1_aclk_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div4" };
+
+static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
+ MUX(0, "mout_fsys1_pclkl_fsys1_busp_mux", mout_fsys1_pclkl_fsys1_busp_mux_p,
+ PLL_CON0_PCLKL_FSYS1_BUSP_MUX, 4, 1),
+ MUX(0, "mout_fsys1_aclk_fsys1_busp_mux", mout_fsys1_aclk_fsys1_busp_mux_p,
+ PLL_CON0_ACLK_FSYS1_BUSP_MUX, 4, 1),
+};
+
+static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
+ DIV(0, "dout_fsys1_clk_fsys1_phy0_oscclk", "fsys1_phy0_osccllk",
+ DIV_CLK_FSYS1_PHY0_OSCCLK, 0, 4),
+ DIV(0, "dout_fsys1_clk_fsys1_phy1_oscclk", "fsys1_phy1_oscclk",
+ DIV_CLK_FSYS1_PHY1_OSCCLK, 0, 4),
+};
+
+static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
+ GATE(0, "fsys1_cmu_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux",
+ GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_xtal", "clk_fsys1_phy0_ref",
+ GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_phy0_osccllk", "mout_fsys1_aclk_fsys1_busp_mux",
+ GAT_FSYS1_PHY0_OSCCLLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_phy1_oscclk", "mout_fsys1_aclk_fsys1_busp_mux",
+ GAT_FSYS1_PHY1_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_axi2apb_fsys1_ipclkport_aclk", "mout_fsys1_pclkl_fsys1_busp_mux",
+ GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_bus_d0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux",
+ GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_bus_s0_fsys1_ipclkport_m250clk", "mout_fsys1_pclkl_fsys1_busp_mux",
+ GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_bus_s0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux",
+ GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_cpe425_0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux",
+ GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_d0",
+ "mout_fsys1_aclk_fsys1_busp_mux",
+ GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_s0",
+ "mout_fsys1_aclk_fsys1_busp_mux",
+ GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_LINK0_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link0_ipclkport_dbi_aclk",
+ "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_pcie_link0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_pcie_link0_ipclkport_i_soc_ref_clk", "fin_pll",
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_pcie_link0_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_LINK0_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link0_ipclkport_mstr_aclk",
+ "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_LINK0_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link0_ipclkport_slv_aclk",
+ "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_LINK1_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link1_ipclkport_dbi_aclk",
+ "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_pcie_link1_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
+ GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_LINK1_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link1_ipclkport_mstr_aclk",
+ "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_LINK1_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link1_ipclkport_slv_aclk",
+ "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_pcie_phy0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
+ GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_LINK0_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link0_ipclkport_auxclk", "fin_pll",
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_LINK1_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link1_ipclkport_auxclk", "fin_pll",
+ GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_soc_pll", "dout_fsys1_clk_fsys1_phy0_oscclk",
+ GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_sysreg_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux",
+ GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_tbu0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux",
+ GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
+ .mux_clks = fsys1_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
+ .div_clks = fsys1_div_clks,
+ .nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
+ .gate_clks = fsys1_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
+ .fixed_clks = fsys1_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(fsys1_fixed_clks),
+ .nr_clk_ids = FSYS1_NR_CLK,
+ .clk_regs = fsys1_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
+ .clk_name = "dout_cmu_fsys1_shared0div4",
+};
+
/**
* fsd_cmu_probe - Probe function for FSD platform clocks
* @pdev: Pointer to platform device
@@ -997,6 +1169,9 @@ static const struct of_device_id fsd_cmu_of_match[] = {
}, {
.compatible = "tesla,fsd-clock-fsys0",
.data = &fsys0_cmu_info,
+ }, {
+ .compatible = "tesla,fsd-clock-fsys1",
+ .data = &fsys1_cmu_info,
}, {
},
};
--
2.25.1
^ permalink raw reply related
* [PATCH v3 06/16] clk: samsung: fsd: Add cmu_fsys0 clock information
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar, linux-fsd,
Shradha Todi, Jayati Sahu, Ajay Kumar
In-Reply-To: <20220121172840.12121-1-alim.akhtar@samsung.com>
CMU_FSYS0 block has IPs like UFS, EQOS, PCIe etc, lets add
the related clock information for the same.
Cc: linux-fsd@tesla.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Shradha Todi <shradha.t@samsung.com>
Signed-off-by: Jayati Sahu <jayati.sahu@samsung.com>
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/clk/samsung/clk-fsd.c | 302 ++++++++++++++++++++++++++++++++++
1 file changed, 302 insertions(+)
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
index d190ceb7c1ab..8062afab75e3 100644
--- a/drivers/clk/samsung/clk-fsd.c
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -673,6 +673,305 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = {
.clk_name = "dout_cmu_pll_shared0_div4",
};
+/* Register Offset definitions for CMU_FSYS0 (0x15010000) */
+#define PLL_CON0_CLKCMU_FSYS0_UNIPRO 0x100
+#define PLL_CON0_CLK_FSYS0_SLAVEBUSCLK 0x140
+#define PLL_CON0_EQOS_RGMII_125_MUX1 0x160
+#define DIV_CLK_UNIPRO 0x1800
+#define DIV_EQS_RGMII_CLK_125 0x1804
+#define DIV_PERIBUS_GRP 0x1808
+#define DIV_EQOS_RII_CLK2O5 0x180c
+#define DIV_EQOS_RMIICLK_25 0x1810
+#define DIV_PCIE_PHY_OSCCLK 0x1814
+#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 0x2004
+#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 0x2008
+#define GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x200c
+#define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK 0x2010
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO 0x2014
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK 0x2018
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC 0x201c
+#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2020
+#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x2024
+#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2028
+#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x202c
+#define GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK 0x2038
+#define GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK 0x203c
+#define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK 0x2040
+#define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK 0x2044
+#define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK 0x2048
+#define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK 0x204c
+#define GAT_FSYS0_CPE425_IPCLKPORT_ACLK 0x2050
+#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 0x2054
+#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 0x2058
+#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 0x205c
+#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I 0x2060
+#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I 0x2064
+#define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK 0x2068
+#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D 0x206c
+#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1 0x2070
+#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P 0x2074
+#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S 0x2078
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK 0x207c
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL 0x2080
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0 0x2084
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC 0x2088
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x208c
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC 0x2090
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC 0x2094
+#define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK 0x2098
+#define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK 0x209c
+#define GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK 0x20a0
+#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS 0x20a4
+#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK 0x20a8
+#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO 0x20ac
+#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK 0x20b0
+#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS 0x20b4
+#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK 0x20b8
+#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO 0x20bc
+#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK 0x20c0
+#define GAT_FSYS0_RII_CLK_DIVGATE 0x20d4
+
+static const unsigned long fsys0_clk_regs[] __initconst = {
+ PLL_CON0_CLKCMU_FSYS0_UNIPRO,
+ PLL_CON0_CLK_FSYS0_SLAVEBUSCLK,
+ PLL_CON0_EQOS_RGMII_125_MUX1,
+ DIV_CLK_UNIPRO,
+ DIV_EQS_RGMII_CLK_125,
+ DIV_PERIBUS_GRP,
+ DIV_EQOS_RII_CLK2O5,
+ DIV_EQOS_RMIICLK_25,
+ DIV_PCIE_PHY_OSCCLK,
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I,
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I,
+ GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
+ GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC,
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24,
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26,
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24,
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26,
+ GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK,
+ GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK,
+ GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK,
+ GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK,
+ GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK,
+ GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK,
+ GAT_FSYS0_CPE425_IPCLKPORT_ACLK,
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I,
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I,
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I,
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I,
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I,
+ GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK,
+ GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D,
+ GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1,
+ GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P,
+ GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC,
+ GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK,
+ GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK,
+ GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK,
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS,
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK,
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO,
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK,
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS,
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK,
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO,
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK,
+ GAT_FSYS0_RII_CLK_DIVGATE,
+};
+
+static const struct samsung_fixed_rate_clock fsys0_fixed_clks[] __initconst = {
+ FRATE(0, "pad_eqos0_phyrxclk", NULL, 0, 125000000),
+ FRATE(0, "i_mphy_refclk_ixtal26", NULL, 0, 26000000),
+ FRATE(0, "xtal_clk_pcie_phy", NULL, 0, 100000000),
+};
+
+/* List of parent clocks for Muxes in CMU_FSYS0 */
+PNAME(mout_fsys0_clkcmu_fsys0_unipro_p) = { "fin_pll", "dout_cmu_pll_shared0_div6" };
+PNAME(mout_fsys0_clk_fsys0_slavebusclk_p) = { "fin_pll", "dout_cmu_fsys0_shared1div4" };
+PNAME(mout_fsys0_eqos_rgmii_125_mux1_p) = { "fin_pll", "dout_cmu_fsys0_shared0div4" };
+
+static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
+ MUX(0, "mout_fsys0_clkcmu_fsys0_unipro", mout_fsys0_clkcmu_fsys0_unipro_p,
+ PLL_CON0_CLKCMU_FSYS0_UNIPRO, 4, 1),
+ MUX(0, "mout_fsys0_clk_fsys0_slavebusclk", mout_fsys0_clk_fsys0_slavebusclk_p,
+ PLL_CON0_CLK_FSYS0_SLAVEBUSCLK, 4, 1),
+ MUX(0, "mout_fsys0_eqos_rgmii_125_mux1", mout_fsys0_eqos_rgmii_125_mux1_p,
+ PLL_CON0_EQOS_RGMII_125_MUX1, 4, 1),
+};
+
+static const struct samsung_div_clock fsys0_div_clks[] __initconst = {
+ DIV(0, "dout_fsys0_clk_unipro", "mout_fsys0_clkcmu_fsys0_unipro", DIV_CLK_UNIPRO, 0, 4),
+ DIV(0, "dout_fsys0_eqs_rgmii_clk_125", "mout_fsys0_eqos_rgmii_125_mux1",
+ DIV_EQS_RGMII_CLK_125, 0, 4),
+ DIV(FSYS0_DOUT_FSYS0_PERIBUS_GRP, "dout_fsys0_peribus_grp",
+ "mout_fsys0_clk_fsys0_slavebusclk", DIV_PERIBUS_GRP, 0, 4),
+ DIV(0, "dout_fsys0_eqos_rii_clk2o5", "fsys0_rii_clk_divgate", DIV_EQOS_RII_CLK2O5, 0, 4),
+ DIV(0, "dout_fsys0_eqos_rmiiclk_25", "mout_fsys0_eqos_rgmii_125_mux1",
+ DIV_EQOS_RMIICLK_25, 0, 5),
+ DIV(0, "dout_fsys0_pcie_phy_oscclk", "mout_fsys0_eqos_rgmii_125_mux1",
+ DIV_PCIE_PHY_OSCCLK, 0, 4),
+};
+
+static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
+ GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, "fsys0_eqos_top0_ipclkport_clk_rx_i",
+ "pad_eqos0_phyrxclk", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_SUBCTRL_INST0_AUX_CLK_SOC,
+ "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_aux_clk_soc", "fin_pll",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_fsys0_cmu_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0,
+ "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_xo",
+ "xtal_clk_pcie_phy",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(UFS0_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal24",
+ "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(UFS0_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal26",
+ "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(UFS1_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal24",
+ "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(UFS1_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal26",
+ "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_ahbbr_fsys0_ipclkport_hclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_axi2apb_fsys0_ipclkport_aclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_bus_d_fsys0_ipclkport_mainclk", "mout_fsys0_clk_fsys0_slavebusclk",
+ GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_bus_d_fsys0_ipclkport_periclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_bus_p_fsys0_ipclkport_mainclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_bus_p_fsys0_ipclkport_tcuclk", "mout_fsys0_eqos_rgmii_125_mux1",
+ GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_cpe425_ipclkport_aclk", "mout_fsys0_clk_fsys0_slavebusclk",
+ GAT_FSYS0_CPE425_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, "fsys0_eqos_top0_ipclkport_aclk_i",
+ "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, "fsys0_eqos_top0_ipclkport_hclk_i",
+ "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, "fsys0_eqos_top0_ipclkport_rgmii_clk_i",
+ "dout_fsys0_eqs_rgmii_clk_125", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_eqos_top0_ipclkport_rii_clk_i", "dout_fsys0_eqos_rii_clk2o5",
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_eqos_top0_ipclkport_rmii_clk_i", "dout_fsys0_eqos_rmiiclk_25",
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_gpio_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_gpio_fsys0_ipclkport_oscclk", "fin_pll",
+ GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d",
+ "mout_fsys0_clk_fsys0_slavebusclk",
+ GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d1",
+ "mout_fsys0_eqos_rgmii_125_mux1",
+ GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_p",
+ "dout_fsys0_peribus_grp",
+ GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_s",
+ "mout_fsys0_clk_fsys0_slavebusclk",
+ GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_i_apb_pclk",
+ "dout_fsys0_peribus_grp",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0,
+ "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_syspll",
+ "dout_fsys0_pcie_phy_oscclk",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL,
+ 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_apb_pclk_0", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_immortal_clk", "fin_pll",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_SUBCTRL_INST0_DBI_ACLK_SOC,
+ "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_dbi_aclk_soc",
+ "dout_fsys0_peribus_grp",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_i_driver_apb_clk",
+ "dout_fsys0_peribus_grp",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC,
+ "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_mstr_aclk_soc",
+ "mout_fsys0_clk_fsys0_slavebusclk",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_SUBCTRL_INST0_SLV_ACLK_SOC,
+ "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_slv_aclk_soc",
+ "mout_fsys0_clk_fsys0_slavebusclk",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_smmu_fsys0_ipclkport_cclk", "mout_fsys0_eqos_rgmii_125_mux1",
+ GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_smmu_fsys0_ipclkport_fsys0_bclk", "mout_fsys0_clk_fsys0_slavebusclk",
+ GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_sysreg_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(UFS0_TOP0_HCLK_BUS, "fsys0_ufs_top0_ipclkport_hclk_bus", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(UFS0_TOP0_ACLK, "fsys0_ufs_top0_ipclkport_i_aclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(UFS0_TOP0_CLK_UNIPRO, "fsys0_ufs_top0_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro",
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(UFS0_TOP0_FMP_CLK, "fsys0_ufs_top0_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(UFS1_TOP1_HCLK_BUS, "fsys0_ufs_top1_ipclkport_hclk_bus", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(UFS1_TOP1_ACLK, "fsys0_ufs_top1_ipclkport_i_aclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(UFS1_TOP1_CLK_UNIPRO, "fsys0_ufs_top1_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro",
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(UFS1_TOP1_FMP_CLK, "fsys0_ufs_top1_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_rii_clk_divgate", "dout_fsys0_eqos_rmiiclk_25", GAT_FSYS0_RII_CLK_DIVGATE,
+ 21, CLK_IGNORE_UNUSED, 0),
+ GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, "fsys0_eqos_top0_ipclkport_clk_ptp_ref_i",
+ "fin_pll", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
+ .mux_clks = fsys0_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
+ .div_clks = fsys0_div_clks,
+ .nr_div_clks = ARRAY_SIZE(fsys0_div_clks),
+ .gate_clks = fsys0_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
+ .fixed_clks = fsys0_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(fsys0_fixed_clks),
+ .nr_clk_ids = FSYS0_NR_CLK,
+ .clk_regs = fsys0_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
+ .clk_name = "dout_cmu_fsys0_shared1div4",
+};
+
/**
* fsd_cmu_probe - Probe function for FSD platform clocks
* @pdev: Pointer to platform device
@@ -695,6 +994,9 @@ static const struct of_device_id fsd_cmu_of_match[] = {
{
.compatible = "tesla,fsd-clock-peric",
.data = &peric_cmu_info,
+ }, {
+ .compatible = "tesla,fsd-clock-fsys0",
+ .data = &fsys0_cmu_info,
}, {
},
};
--
2.25.1
^ permalink raw reply related
* [PATCH v3 05/16] clk: samsung: fsd: Add cmu_peric block clock information
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar, linux-fsd,
Aswani Reddy, Niyas Ahmed S T, Chandrasekar R, Jayati Sahu,
Sriranjani P, Ajay Kumar
In-Reply-To: <20220121172840.12121-1-alim.akhtar@samsung.com>
Add CMU_PERIC block clock information needed for various IPs
functions found in this block.
Cc: linux-fsd@tesla.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Aswani Reddy <aswani.reddy@samsung.com>
Signed-off-by: Niyas Ahmed S T <niyas.ahmed@samsung.com>
Signed-off-by: Chandrasekar R <rcsekar@samsung.com>
Signed-off-by: Jayati Sahu <jayati.sahu@samsung.com>
Signed-off-by: Sriranjani P <sriranjani.p@samsung.com>
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/clk/samsung/clk-fsd.c | 405 ++++++++++++++++++++++++++++++++++
1 file changed, 405 insertions(+)
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
index 1caa31d08fc0..d190ceb7c1ab 100644
--- a/drivers/clk/samsung/clk-fsd.c
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -8,14 +8,19 @@
* Common Clock Framework support for FSD SoC.
*/
+#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include <dt-bindings/clock/fsd-clk.h>
#include "clk.h"
+#include "clk-exynos-arm64.h"
/* Register Offset definitions for CMU_CMU (0x11c10000) */
#define PLL_LOCKTIME_PLL_SHARED0 0x0
@@ -308,3 +313,403 @@ static void __init fsd_clk_cmu_init(struct device_node *np)
}
CLK_OF_DECLARE(fsd_clk_cmu, "tesla,fsd-clock-cmu", fsd_clk_cmu_init);
+
+/* Register Offset definitions for CMU_PERIC (0x14010000) */
+#define PLL_CON0_PERIC_DMACLK_MUX 0x100
+#define PLL_CON0_PERIC_EQOS_BUSCLK_MUX 0x120
+#define PLL_CON0_PERIC_PCLK_MUX 0x140
+#define PLL_CON0_PERIC_TBUCLK_MUX 0x160
+#define PLL_CON0_SPI_CLK 0x180
+#define PLL_CON0_SPI_PCLK 0x1a0
+#define PLL_CON0_UART_CLK 0x1c0
+#define PLL_CON0_UART_PCLK 0x1e0
+#define MUX_PERIC_EQOS_PHYRXCLK 0x1000
+#define DIV_EQOS_BUSCLK 0x1800
+#define DIV_PERIC_MCAN_CLK 0x1804
+#define DIV_RGMII_CLK 0x1808
+#define DIV_RII_CLK 0x180c
+#define DIV_RMII_CLK 0x1810
+#define DIV_SPI_CLK 0x1814
+#define DIV_UART_CLK 0x1818
+#define GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 0x2000
+#define GAT_GPIO_PERIC_IPCLKPORT_OSCCLK 0x2004
+#define GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK 0x2008
+#define GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK 0x200c
+#define GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK 0x2010
+#define GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK 0x2014
+#define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM 0x2018
+#define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS 0x201c
+#define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM 0x2020
+#define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS 0x2024
+#define GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK 0x2028
+#define GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK 0x202c
+#define GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK 0x2030
+#define GAT_BUS_D_PERIC_IPCLKPORT_DMACLK 0x2034
+#define GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK 0x2038
+#define GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK 0x203c
+#define GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK 0x2040
+#define GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK 0x2044
+#define GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK 0x2048
+#define GAT_EQOS_TOP_IPCLKPORT_ACLK_I 0x204c
+#define GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I 0x2050
+#define GAT_EQOS_TOP_IPCLKPORT_HCLK_I 0x2054
+#define GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 0x2058
+#define GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I 0x205c
+#define GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I 0x2060
+#define GAT_GPIO_PERIC_IPCLKPORT_PCLK 0x2064
+#define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D 0x2068
+#define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P 0x206c
+#define GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0 0x2070
+#define GAT_PERIC_DMA0_IPCLKPORT_ACLK 0x2074
+#define GAT_PERIC_DMA1_IPCLKPORT_ACLK 0x2078
+#define GAT_PERIC_I2C0_IPCLKPORT_I_PCLK 0x207c
+#define GAT_PERIC_I2C1_IPCLKPORT_I_PCLK 0x2080
+#define GAT_PERIC_I2C2_IPCLKPORT_I_PCLK 0x2084
+#define GAT_PERIC_I2C3_IPCLKPORT_I_PCLK 0x2088
+#define GAT_PERIC_I2C4_IPCLKPORT_I_PCLK 0x208c
+#define GAT_PERIC_I2C5_IPCLKPORT_I_PCLK 0x2090
+#define GAT_PERIC_I2C6_IPCLKPORT_I_PCLK 0x2094
+#define GAT_PERIC_I2C7_IPCLKPORT_I_PCLK 0x2098
+#define GAT_PERIC_MCAN0_IPCLKPORT_CCLK 0x209c
+#define GAT_PERIC_MCAN0_IPCLKPORT_PCLK 0x20a0
+#define GAT_PERIC_MCAN1_IPCLKPORT_CCLK 0x20a4
+#define GAT_PERIC_MCAN1_IPCLKPORT_PCLK 0x20a8
+#define GAT_PERIC_MCAN2_IPCLKPORT_CCLK 0x20ac
+#define GAT_PERIC_MCAN2_IPCLKPORT_PCLK 0x20b0
+#define GAT_PERIC_MCAN3_IPCLKPORT_CCLK 0x20b4
+#define GAT_PERIC_MCAN3_IPCLKPORT_PCLK 0x20b8
+#define GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0 0x20bc
+#define GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0 0x20c0
+#define GAT_PERIC_SMMU_IPCLKPORT_CCLK 0x20c4
+#define GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK 0x20c8
+#define GAT_PERIC_SPI0_IPCLKPORT_I_PCLK 0x20cc
+#define GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI 0x20d0
+#define GAT_PERIC_SPI1_IPCLKPORT_I_PCLK 0x20d4
+#define GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI 0x20d8
+#define GAT_PERIC_SPI2_IPCLKPORT_I_PCLK 0x20dc
+#define GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI 0x20e0
+#define GAT_PERIC_TDM0_IPCLKPORT_HCLK_M 0x20e4
+#define GAT_PERIC_TDM0_IPCLKPORT_PCLK 0x20e8
+#define GAT_PERIC_TDM1_IPCLKPORT_HCLK_M 0x20ec
+#define GAT_PERIC_TDM1_IPCLKPORT_PCLK 0x20f0
+#define GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART 0x20f4
+#define GAT_PERIC_UART0_IPCLKPORT_PCLK 0x20f8
+#define GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART 0x20fc
+#define GAT_PERIC_UART1_IPCLKPORT_PCLK 0x2100
+#define GAT_SYSREG_PERI_IPCLKPORT_PCLK 0x2104
+
+static const unsigned long peric_clk_regs[] __initconst = {
+ PLL_CON0_PERIC_DMACLK_MUX,
+ PLL_CON0_PERIC_EQOS_BUSCLK_MUX,
+ PLL_CON0_PERIC_PCLK_MUX,
+ PLL_CON0_PERIC_TBUCLK_MUX,
+ PLL_CON0_SPI_CLK,
+ PLL_CON0_SPI_PCLK,
+ PLL_CON0_UART_CLK,
+ PLL_CON0_UART_PCLK,
+ MUX_PERIC_EQOS_PHYRXCLK,
+ DIV_EQOS_BUSCLK,
+ DIV_PERIC_MCAN_CLK,
+ DIV_RGMII_CLK,
+ DIV_RII_CLK,
+ DIV_RMII_CLK,
+ DIV_SPI_CLK,
+ DIV_UART_CLK,
+ GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I,
+ GAT_GPIO_PERIC_IPCLKPORT_OSCCLK,
+ GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK,
+ GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK,
+ GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK,
+ GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK,
+ GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM,
+ GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS,
+ GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM,
+ GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS,
+ GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK,
+ GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK,
+ GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK,
+ GAT_BUS_D_PERIC_IPCLKPORT_DMACLK,
+ GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK,
+ GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK,
+ GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK,
+ GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK,
+ GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK,
+ GAT_EQOS_TOP_IPCLKPORT_ACLK_I,
+ GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I,
+ GAT_EQOS_TOP_IPCLKPORT_HCLK_I,
+ GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I,
+ GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I,
+ GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I,
+ GAT_GPIO_PERIC_IPCLKPORT_PCLK,
+ GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D,
+ GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P,
+ GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0,
+ GAT_PERIC_DMA0_IPCLKPORT_ACLK,
+ GAT_PERIC_DMA1_IPCLKPORT_ACLK,
+ GAT_PERIC_I2C0_IPCLKPORT_I_PCLK,
+ GAT_PERIC_I2C1_IPCLKPORT_I_PCLK,
+ GAT_PERIC_I2C2_IPCLKPORT_I_PCLK,
+ GAT_PERIC_I2C3_IPCLKPORT_I_PCLK,
+ GAT_PERIC_I2C4_IPCLKPORT_I_PCLK,
+ GAT_PERIC_I2C5_IPCLKPORT_I_PCLK,
+ GAT_PERIC_I2C6_IPCLKPORT_I_PCLK,
+ GAT_PERIC_I2C7_IPCLKPORT_I_PCLK,
+ GAT_PERIC_MCAN0_IPCLKPORT_CCLK,
+ GAT_PERIC_MCAN0_IPCLKPORT_PCLK,
+ GAT_PERIC_MCAN1_IPCLKPORT_CCLK,
+ GAT_PERIC_MCAN1_IPCLKPORT_PCLK,
+ GAT_PERIC_MCAN2_IPCLKPORT_CCLK,
+ GAT_PERIC_MCAN2_IPCLKPORT_PCLK,
+ GAT_PERIC_MCAN3_IPCLKPORT_CCLK,
+ GAT_PERIC_MCAN3_IPCLKPORT_PCLK,
+ GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0,
+ GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0,
+ GAT_PERIC_SMMU_IPCLKPORT_CCLK,
+ GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK,
+ GAT_PERIC_SPI0_IPCLKPORT_I_PCLK,
+ GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI,
+ GAT_PERIC_SPI1_IPCLKPORT_I_PCLK,
+ GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI,
+ GAT_PERIC_SPI2_IPCLKPORT_I_PCLK,
+ GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI,
+ GAT_PERIC_TDM0_IPCLKPORT_HCLK_M,
+ GAT_PERIC_TDM0_IPCLKPORT_PCLK,
+ GAT_PERIC_TDM1_IPCLKPORT_HCLK_M,
+ GAT_PERIC_TDM1_IPCLKPORT_PCLK,
+ GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART,
+ GAT_PERIC_UART0_IPCLKPORT_PCLK,
+ GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART,
+ GAT_PERIC_UART1_IPCLKPORT_PCLK,
+ GAT_SYSREG_PERI_IPCLKPORT_PCLK,
+};
+
+static const struct samsung_fixed_rate_clock peric_fixed_clks[] __initconst = {
+ FRATE(PERIC_EQOS_PHYRXCLK, "eqos_phyrxclk", NULL, 0, 125000000),
+};
+
+/* List of parent clocks for Muxes in CMU_PERIC */
+PNAME(mout_peric_dmaclk_p) = { "fin_pll", "cmu_peric_shared1div4_dmaclk_gate" };
+PNAME(mout_peric_eqos_busclk_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
+PNAME(mout_peric_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
+PNAME(mout_peric_tbuclk_p) = { "fin_pll", "dout_cmu_peric_shared0div3_tbuclk" };
+PNAME(mout_peric_spi_clk_p) = { "fin_pll", "dout_cmu_peric_shared0div20" };
+PNAME(mout_peric_spi_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
+PNAME(mout_peric_uart_clk_p) = { "fin_pll", "dout_cmu_peric_shared1div4_dmaclk" };
+PNAME(mout_peric_uart_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
+PNAME(mout_peric_eqos_phyrxclk_p) = { "dout_peric_rgmii_clk", "eqos_phyrxclk" };
+
+static const struct samsung_mux_clock peric_mux_clks[] __initconst = {
+ MUX(0, "mout_peric_dmaclk", mout_peric_dmaclk_p, PLL_CON0_PERIC_DMACLK_MUX, 4, 1),
+ MUX(0, "mout_peric_eqos_busclk", mout_peric_eqos_busclk_p,
+ PLL_CON0_PERIC_EQOS_BUSCLK_MUX, 4, 1),
+ MUX(0, "mout_peric_pclk", mout_peric_pclk_p, PLL_CON0_PERIC_PCLK_MUX, 4, 1),
+ MUX(0, "mout_peric_tbuclk", mout_peric_tbuclk_p, PLL_CON0_PERIC_TBUCLK_MUX, 4, 1),
+ MUX(0, "mout_peric_spi_clk", mout_peric_spi_clk_p, PLL_CON0_SPI_CLK, 4, 1),
+ MUX(0, "mout_peric_spi_pclk", mout_peric_spi_pclk_p, PLL_CON0_SPI_PCLK, 4, 1),
+ MUX(0, "mout_peric_uart_clk", mout_peric_uart_clk_p, PLL_CON0_UART_CLK, 4, 1),
+ MUX(0, "mout_peric_uart_pclk", mout_peric_uart_pclk_p, PLL_CON0_UART_PCLK, 4, 1),
+ MUX(PERIC_EQOS_PHYRXCLK_MUX, "mout_peric_eqos_phyrxclk", mout_peric_eqos_phyrxclk_p,
+ MUX_PERIC_EQOS_PHYRXCLK, 0, 1),
+};
+
+static const struct samsung_div_clock peric_div_clks[] __initconst = {
+ DIV(0, "dout_peric_eqos_busclk", "mout_peric_eqos_busclk", DIV_EQOS_BUSCLK, 0, 4),
+ DIV(0, "dout_peric_mcan_clk", "mout_peric_dmaclk", DIV_PERIC_MCAN_CLK, 0, 4),
+ DIV(PERIC_DOUT_RGMII_CLK, "dout_peric_rgmii_clk", "mout_peric_eqos_busclk",
+ DIV_RGMII_CLK, 0, 4),
+ DIV(0, "dout_peric_rii_clk", "dout_peric_rmii_clk", DIV_RII_CLK, 0, 4),
+ DIV(0, "dout_peric_rmii_clk", "dout_peric_rgmii_clk", DIV_RMII_CLK, 0, 4),
+ DIV(0, "dout_peric_spi_clk", "mout_peric_spi_clk", DIV_SPI_CLK, 0, 6),
+ DIV(0, "dout_peric_uart_clk", "mout_peric_uart_clk", DIV_UART_CLK, 0, 6),
+};
+
+static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
+ GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, "peric_eqos_top_ipclkport_clk_ptp_ref_i",
+ "fin_pll", GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_gpio_peric_ipclkport_oscclk", "fin_pll", GAT_GPIO_PERIC_IPCLKPORT_OSCCLK,
+ 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_ADCIF, "peric_adc0_ipclkport_i_oscclk", "fin_pll",
+ GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_cmu_peric_ipclkport_pclk", "mout_peric_pclk",
+ GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_pwm0_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_pwm1_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_async_apb_dma0_ipclkport_pclkm", "mout_peric_dmaclk",
+ GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_async_apb_dma0_ipclkport_pclks", "mout_peric_pclk",
+ GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_async_apb_dma1_ipclkport_pclkm", "mout_peric_dmaclk",
+ GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_async_apb_dma1_ipclkport_pclks", "mout_peric_pclk",
+ GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_axi2apb_peric0_ipclkport_aclk", "mout_peric_pclk",
+ GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_axi2apb_peric1_ipclkport_aclk", "mout_peric_pclk",
+ GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_axi2apb_peric2_ipclkport_aclk", "mout_peric_pclk",
+ GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_bus_d_peric_ipclkport_dmaclk", "mout_peric_dmaclk",
+ GAT_BUS_D_PERIC_IPCLKPORT_DMACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_d_peric_ipclkport_eqosclk",
+ "dout_peric_eqos_busclk", GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_bus_d_peric_ipclkport_mainclk", "mout_peric_tbuclk",
+ GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_p_peric_ipclkport_eqosclk",
+ "dout_peric_eqos_busclk", GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_bus_p_peric_ipclkport_mainclk", "mout_peric_pclk",
+ GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_bus_p_peric_ipclkport_smmuclk", "mout_peric_tbuclk",
+ GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_EQOS_TOP_IPCLKPORT_ACLK_I, "peric_eqos_top_ipclkport_aclk_i",
+ "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_ACLK_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I, "peric_eqos_top_ipclkport_clk_rx_i",
+ "mout_peric_eqos_phyrxclk", GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_EQOS_TOP_IPCLKPORT_HCLK_I, "peric_eqos_top_ipclkport_hclk_i",
+ "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_HCLK_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, "peric_eqos_top_ipclkport_rgmii_clk_i",
+ "dout_peric_rgmii_clk", GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_eqos_top_ipclkport_rii_clk_i", "dout_peric_rii_clk",
+ GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_eqos_top_ipclkport_rmii_clk_i", "dout_peric_rmii_clk",
+ GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_gpio_peric_ipclkport_pclk", "mout_peric_pclk",
+ GAT_GPIO_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_d", "mout_peric_tbuclk",
+ GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_p", "mout_peric_pclk",
+ GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_adc0_ipclkport_pclk_s0", "mout_peric_pclk",
+ GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_DMA0_IPCLKPORT_ACLK, "peric_dma0_ipclkport_aclk", "mout_peric_dmaclk",
+ GAT_PERIC_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_DMA1_IPCLKPORT_ACLK, "peric_dma1_ipclkport_aclk", "mout_peric_dmaclk",
+ GAT_PERIC_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_HSI2C0, "peric_i2c0_ipclkport_i_pclk", "mout_peric_pclk",
+ GAT_PERIC_I2C0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_HSI2C1, "peric_i2c1_ipclkport_i_pclk", "mout_peric_pclk",
+ GAT_PERIC_I2C1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_HSI2C2, "peric_i2c2_ipclkport_i_pclk", "mout_peric_pclk",
+ GAT_PERIC_I2C2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_HSI2C3, "peric_i2c3_ipclkport_i_pclk", "mout_peric_pclk",
+ GAT_PERIC_I2C3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_HSI2C4, "peric_i2c4_ipclkport_i_pclk", "mout_peric_pclk",
+ GAT_PERIC_I2C4_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_HSI2C5, "peric_i2c5_ipclkport_i_pclk", "mout_peric_pclk",
+ GAT_PERIC_I2C5_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_HSI2C6, "peric_i2c6_ipclkport_i_pclk", "mout_peric_pclk",
+ GAT_PERIC_I2C6_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_HSI2C7, "peric_i2c7_ipclkport_i_pclk", "mout_peric_pclk",
+ GAT_PERIC_I2C7_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_MCAN0_IPCLKPORT_CCLK, "peric_mcan0_ipclkport_cclk", "dout_peric_mcan_clk",
+ GAT_PERIC_MCAN0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_MCAN0_IPCLKPORT_PCLK, "peric_mcan0_ipclkport_pclk", "mout_peric_pclk",
+ GAT_PERIC_MCAN0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_MCAN1_IPCLKPORT_CCLK, "peric_mcan1_ipclkport_cclk", "dout_peric_mcan_clk",
+ GAT_PERIC_MCAN1_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_MCAN1_IPCLKPORT_PCLK, "peric_mcan1_ipclkport_pclk", "mout_peric_pclk",
+ GAT_PERIC_MCAN1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_MCAN2_IPCLKPORT_CCLK, "peric_mcan2_ipclkport_cclk", "dout_peric_mcan_clk",
+ GAT_PERIC_MCAN2_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_MCAN2_IPCLKPORT_PCLK, "peric_mcan2_ipclkport_pclk", "mout_peric_pclk",
+ GAT_PERIC_MCAN2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_MCAN3_IPCLKPORT_CCLK, "peric_mcan3_ipclkport_cclk", "dout_peric_mcan_clk",
+ GAT_PERIC_MCAN3_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_MCAN3_IPCLKPORT_PCLK, "peric_mcan3_ipclkport_pclk", "mout_peric_pclk",
+ GAT_PERIC_MCAN3_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PWM0_IPCLKPORT_I_PCLK_S0, "peric_pwm0_ipclkport_i_pclk_s0", "mout_peric_pclk",
+ GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PWM1_IPCLKPORT_I_PCLK_S0, "peric_pwm1_ipclkport_i_pclk_s0", "mout_peric_pclk",
+ GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_smmu_ipclkport_cclk", "mout_peric_tbuclk",
+ GAT_PERIC_SMMU_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_smmu_ipclkport_peric_bclk", "mout_peric_tbuclk",
+ GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_SPI0, "peric_spi0_ipclkport_i_pclk", "mout_peric_spi_pclk",
+ GAT_PERIC_SPI0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_SCLK_SPI0, "peric_spi0_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
+ GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_SPI1, "peric_spi1_ipclkport_i_pclk", "mout_peric_spi_pclk",
+ GAT_PERIC_SPI1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_SCLK_SPI1, "peric_spi1_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
+ GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_SPI2, "peric_spi2_ipclkport_i_pclk", "mout_peric_spi_pclk",
+ GAT_PERIC_SPI2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_SCLK_SPI2, "peric_spi2_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
+ GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_HCLK_TDM0, "peric_tdm0_ipclkport_hclk_m", "mout_peric_pclk",
+ GAT_PERIC_TDM0_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_TDM0, "peric_tdm0_ipclkport_pclk", "mout_peric_pclk",
+ GAT_PERIC_TDM0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_HCLK_TDM1, "peric_tdm1_ipclkport_hclk_m", "mout_peric_pclk",
+ GAT_PERIC_TDM1_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_TDM1, "peric_tdm1_ipclkport_pclk", "mout_peric_pclk",
+ GAT_PERIC_TDM1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_SCLK_UART0, "peric_uart0_ipclkport_i_sclk_uart", "dout_peric_uart_clk",
+ GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_UART0, "peric_uart0_ipclkport_pclk", "mout_peric_uart_pclk",
+ GAT_PERIC_UART0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_SCLK_UART1, "peric_uart1_ipclkport_i_sclk_uart", "dout_peric_uart_clk",
+ GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_UART1, "peric_uart1_ipclkport_pclk", "mout_peric_uart_pclk",
+ GAT_PERIC_UART1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_sysreg_peri_ipclkport_pclk", "mout_peric_pclk",
+ GAT_SYSREG_PERI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info peric_cmu_info __initconst = {
+ .mux_clks = peric_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(peric_mux_clks),
+ .div_clks = peric_div_clks,
+ .nr_div_clks = ARRAY_SIZE(peric_div_clks),
+ .gate_clks = peric_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
+ .fixed_clks = peric_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(peric_fixed_clks),
+ .nr_clk_ids = PERIC_NR_CLK,
+ .clk_regs = peric_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
+ .clk_name = "dout_cmu_pll_shared0_div4",
+};
+
+/**
+ * fsd_cmu_probe - Probe function for FSD platform clocks
+ * @pdev: Pointer to platform device
+ *
+ * Configure clock hierarchy for clock domains of FSD platform
+ */
+static int __init fsd_cmu_probe(struct platform_device *pdev)
+{
+ const struct samsung_cmu_info *info;
+ struct device *dev = &pdev->dev;
+
+ info = of_device_get_match_data(dev);
+ exynos_arm64_register_cmu(dev, dev->of_node, info);
+
+ return 0;
+}
+
+/* CMUs which belong to Power Domains and need runtime PM to be implemented */
+static const struct of_device_id fsd_cmu_of_match[] = {
+ {
+ .compatible = "tesla,fsd-clock-peric",
+ .data = &peric_cmu_info,
+ }, {
+ },
+};
+
+static struct platform_driver fsd_cmu_driver __refdata = {
+ .driver = {
+ .name = "fsd-cmu",
+ .of_match_table = fsd_cmu_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = fsd_cmu_probe,
+};
+
+static int __init fsd_cmu_init(void)
+{
+ return platform_driver_register(&fsd_cmu_driver);
+}
+core_initcall(fsd_cmu_init);
--
2.25.1
^ permalink raw reply related
* [PATCH v3 04/16] clk: samsung: fsd: Add initial clock support
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar, linux-fsd,
Jayati Sahu, Ajay Kumar
In-Reply-To: <20220121172840.12121-1-alim.akhtar@samsung.com>
Add initial clock support for FSD (Full Self-Driving) SoC
which is required to bring-up platforms based on this SoC.
Cc: linux-fsd@tesla.com
Signed-off-by: Jayati Sahu <jayati.sahu@samsung.com>
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/clk/samsung/Kconfig | 8 +
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-fsd.c | 310 ++++++++++++++++++++++++++++++++++
drivers/clk/samsung/clk-pll.c | 1 +
drivers/clk/samsung/clk-pll.h | 1 +
5 files changed, 321 insertions(+)
create mode 100644 drivers/clk/samsung/clk-fsd.c
diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
index 0e18d6ff2916..5f64c58f120f 100644
--- a/drivers/clk/samsung/Kconfig
+++ b/drivers/clk/samsung/Kconfig
@@ -11,6 +11,7 @@ config COMMON_CLK_SAMSUNG
select EXYNOS_5410_COMMON_CLK if ARM && SOC_EXYNOS5410
select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
+ select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
config S3C64XX_COMMON_CLK
bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
@@ -124,3 +125,10 @@ config S3C2443_COMMON_CLK
help
Support for the clock controller present on the Samsung
S3C2416/S3C2443 SoCs. Choose Y here only if you build for this SoC.
+
+config TESLA_FSD_COMMON_CLK
+ bool "Tesla FSD clock controller support" if COMPILE_TEST
+ depends on COMMON_CLK_SAMSUNG
+ help
+ Support for the clock controller present on the Tesla FSD SoC.
+ Choose Y here only if you build for this SoC.
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 0df74916a895..17e5d1cb9da2 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o
obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o
obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o
+obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
new file mode 100644
index 000000000000..1caa31d08fc0
--- /dev/null
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -0,0 +1,310 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
+ * https://www.samsung.com
+ * Copyright (c) 2017-2022 Tesla, Inc.
+ * https://www.tesla.com
+ *
+ * Common Clock Framework support for FSD SoC.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+
+#include <dt-bindings/clock/fsd-clk.h>
+
+#include "clk.h"
+
+/* Register Offset definitions for CMU_CMU (0x11c10000) */
+#define PLL_LOCKTIME_PLL_SHARED0 0x0
+#define PLL_LOCKTIME_PLL_SHARED1 0x4
+#define PLL_LOCKTIME_PLL_SHARED2 0x8
+#define PLL_LOCKTIME_PLL_SHARED3 0xc
+#define PLL_CON0_PLL_SHARED0 0x100
+#define PLL_CON0_PLL_SHARED1 0x120
+#define PLL_CON0_PLL_SHARED2 0x140
+#define PLL_CON0_PLL_SHARED3 0x160
+#define MUX_CMU_CIS0_CLKMUX 0x1000
+#define MUX_CMU_CIS1_CLKMUX 0x1004
+#define MUX_CMU_CIS2_CLKMUX 0x1008
+#define MUX_CMU_CPUCL_SWITCHMUX 0x100c
+#define MUX_CMU_FSYS1_ACLK_MUX 0x1014
+#define MUX_PLL_SHARED0_MUX 0x1020
+#define MUX_PLL_SHARED1_MUX 0x1024
+#define DIV_CMU_CIS0_CLK 0x1800
+#define DIV_CMU_CIS1_CLK 0x1804
+#define DIV_CMU_CIS2_CLK 0x1808
+#define DIV_CMU_CMU_ACLK 0x180c
+#define DIV_CMU_CPUCL_SWITCH 0x1810
+#define DIV_CMU_FSYS0_SHARED0DIV4 0x181c
+#define DIV_CMU_FSYS0_SHARED1DIV3 0x1820
+#define DIV_CMU_FSYS0_SHARED1DIV4 0x1824
+#define DIV_CMU_FSYS1_SHARED0DIV4 0x1828
+#define DIV_CMU_FSYS1_SHARED0DIV8 0x182c
+#define DIV_CMU_IMEM_ACLK 0x1834
+#define DIV_CMU_IMEM_DMACLK 0x1838
+#define DIV_CMU_IMEM_TCUCLK 0x183c
+#define DIV_CMU_PERIC_SHARED0DIV20 0x1844
+#define DIV_CMU_PERIC_SHARED0DIV3_TBUCLK 0x1848
+#define DIV_CMU_PERIC_SHARED1DIV36 0x184c
+#define DIV_CMU_PERIC_SHARED1DIV4_DMACLK 0x1850
+#define DIV_PLL_SHARED0_DIV2 0x1858
+#define DIV_PLL_SHARED0_DIV3 0x185c
+#define DIV_PLL_SHARED0_DIV4 0x1860
+#define DIV_PLL_SHARED0_DIV6 0x1864
+#define DIV_PLL_SHARED1_DIV3 0x1868
+#define DIV_PLL_SHARED1_DIV36 0x186c
+#define DIV_PLL_SHARED1_DIV4 0x1870
+#define DIV_PLL_SHARED1_DIV9 0x1874
+#define GAT_CMU_CIS0_CLKGATE 0x2000
+#define GAT_CMU_CIS1_CLKGATE 0x2004
+#define GAT_CMU_CIS2_CLKGATE 0x2008
+#define GAT_CMU_CPUCL_SWITCH_GATE 0x200c
+#define GAT_CMU_FSYS0_SHARED0DIV4_GATE 0x2018
+#define GAT_CMU_FSYS0_SHARED1DIV4_CLK 0x201c
+#define GAT_CMU_FSYS0_SHARED1DIV4_GATE 0x2020
+#define GAT_CMU_FSYS1_SHARED0DIV4_GATE 0x2024
+#define GAT_CMU_FSYS1_SHARED1DIV4_GATE 0x2028
+#define GAT_CMU_IMEM_ACLK_GATE 0x2030
+#define GAT_CMU_IMEM_DMACLK_GATE 0x2034
+#define GAT_CMU_IMEM_TCUCLK_GATE 0x2038
+#define GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE 0x2040
+#define GAT_CMU_PERIC_SHARED0DIVE4_GATE 0x2044
+#define GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE 0x2048
+#define GAT_CMU_PERIC_SHARED1DIVE4_GATE 0x204c
+#define GAT_CMU_CMU_CMU_IPCLKPORT_PCLK 0x2054
+#define GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK 0x2058
+#define GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU 0x205c
+#define GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK 0x2060
+
+static const unsigned long cmu_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_SHARED0,
+ PLL_LOCKTIME_PLL_SHARED1,
+ PLL_LOCKTIME_PLL_SHARED2,
+ PLL_LOCKTIME_PLL_SHARED3,
+ PLL_CON0_PLL_SHARED0,
+ PLL_CON0_PLL_SHARED1,
+ PLL_CON0_PLL_SHARED2,
+ PLL_CON0_PLL_SHARED3,
+ MUX_CMU_CIS0_CLKMUX,
+ MUX_CMU_CIS1_CLKMUX,
+ MUX_CMU_CIS2_CLKMUX,
+ MUX_CMU_CPUCL_SWITCHMUX,
+ MUX_CMU_FSYS1_ACLK_MUX,
+ MUX_PLL_SHARED0_MUX,
+ MUX_PLL_SHARED1_MUX,
+ DIV_CMU_CIS0_CLK,
+ DIV_CMU_CIS1_CLK,
+ DIV_CMU_CIS2_CLK,
+ DIV_CMU_CMU_ACLK,
+ DIV_CMU_CPUCL_SWITCH,
+ DIV_CMU_FSYS0_SHARED0DIV4,
+ DIV_CMU_FSYS0_SHARED1DIV3,
+ DIV_CMU_FSYS0_SHARED1DIV4,
+ DIV_CMU_FSYS1_SHARED0DIV4,
+ DIV_CMU_FSYS1_SHARED0DIV8,
+ DIV_CMU_IMEM_ACLK,
+ DIV_CMU_IMEM_DMACLK,
+ DIV_CMU_IMEM_TCUCLK,
+ DIV_CMU_PERIC_SHARED0DIV20,
+ DIV_CMU_PERIC_SHARED0DIV3_TBUCLK,
+ DIV_CMU_PERIC_SHARED1DIV36,
+ DIV_CMU_PERIC_SHARED1DIV4_DMACLK,
+ DIV_PLL_SHARED0_DIV2,
+ DIV_PLL_SHARED0_DIV3,
+ DIV_PLL_SHARED0_DIV4,
+ DIV_PLL_SHARED0_DIV6,
+ DIV_PLL_SHARED1_DIV3,
+ DIV_PLL_SHARED1_DIV36,
+ DIV_PLL_SHARED1_DIV4,
+ DIV_PLL_SHARED1_DIV9,
+ GAT_CMU_CIS0_CLKGATE,
+ GAT_CMU_CIS1_CLKGATE,
+ GAT_CMU_CIS2_CLKGATE,
+ GAT_CMU_CPUCL_SWITCH_GATE,
+ GAT_CMU_FSYS0_SHARED0DIV4_GATE,
+ GAT_CMU_FSYS0_SHARED1DIV4_CLK,
+ GAT_CMU_FSYS0_SHARED1DIV4_GATE,
+ GAT_CMU_FSYS1_SHARED0DIV4_GATE,
+ GAT_CMU_FSYS1_SHARED1DIV4_GATE,
+ GAT_CMU_IMEM_ACLK_GATE,
+ GAT_CMU_IMEM_DMACLK_GATE,
+ GAT_CMU_IMEM_TCUCLK_GATE,
+ GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE,
+ GAT_CMU_PERIC_SHARED0DIVE4_GATE,
+ GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE,
+ GAT_CMU_PERIC_SHARED1DIVE4_GATE,
+ GAT_CMU_CMU_CMU_IPCLKPORT_PCLK,
+ GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK,
+ GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU,
+ GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK,
+};
+
+static const struct samsung_pll_rate_table pll_shared0_rate_table[] __initconst = {
+ PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
+};
+
+static const struct samsung_pll_rate_table pll_shared1_rate_table[] __initconst = {
+ PLL_35XX_RATE(24 * MHZ, 2400000000, 200, 2, 0),
+};
+
+static const struct samsung_pll_rate_table pll_shared2_rate_table[] __initconst = {
+ PLL_35XX_RATE(24 * MHZ, 2400000000, 200, 2, 0),
+};
+
+static const struct samsung_pll_rate_table pll_shared3_rate_table[] __initconst = {
+ PLL_35XX_RATE(24 * MHZ, 1800000000, 150, 2, 0),
+};
+
+static const struct samsung_pll_clock cmu_pll_clks[] __initconst = {
+ PLL(pll_142xx, 0, "fout_pll_shared0", "fin_pll", PLL_LOCKTIME_PLL_SHARED0,
+ PLL_CON0_PLL_SHARED0, pll_shared0_rate_table),
+ PLL(pll_142xx, 0, "fout_pll_shared1", "fin_pll", PLL_LOCKTIME_PLL_SHARED1,
+ PLL_CON0_PLL_SHARED1, pll_shared1_rate_table),
+ PLL(pll_142xx, 0, "fout_pll_shared2", "fin_pll", PLL_LOCKTIME_PLL_SHARED2,
+ PLL_CON0_PLL_SHARED2, pll_shared2_rate_table),
+ PLL(pll_142xx, 0, "fout_pll_shared3", "fin_pll", PLL_LOCKTIME_PLL_SHARED3,
+ PLL_CON0_PLL_SHARED3, pll_shared3_rate_table),
+};
+
+/* List of parent clocks for Muxes in CMU_CMU */
+PNAME(mout_cmu_shared0_pll_p) = { "fin_pll", "fout_pll_shared0" };
+PNAME(mout_cmu_shared1_pll_p) = { "fin_pll", "fout_pll_shared1" };
+PNAME(mout_cmu_shared2_pll_p) = { "fin_pll", "fout_pll_shared2" };
+PNAME(mout_cmu_shared3_pll_p) = { "fin_pll", "fout_pll_shared3" };
+PNAME(mout_cmu_cis0_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
+PNAME(mout_cmu_cis1_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
+PNAME(mout_cmu_cis2_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
+PNAME(mout_cmu_cpucl_switchmux_p) = { "mout_cmu_pll_shared2", "mout_cmu_pll_shared0_mux" };
+PNAME(mout_cmu_fsys1_aclk_mux_p) = { "dout_cmu_pll_shared0_div4", "fin_pll" };
+PNAME(mout_cmu_pll_shared0_mux_p) = { "fin_pll", "mout_cmu_pll_shared0" };
+PNAME(mout_cmu_pll_shared1_mux_p) = { "fin_pll", "mout_cmu_pll_shared1" };
+
+static const struct samsung_mux_clock cmu_mux_clks[] __initconst = {
+ MUX(0, "mout_cmu_pll_shared0", mout_cmu_shared0_pll_p, PLL_CON0_PLL_SHARED0, 4, 1),
+ MUX(0, "mout_cmu_pll_shared1", mout_cmu_shared1_pll_p, PLL_CON0_PLL_SHARED1, 4, 1),
+ MUX(0, "mout_cmu_pll_shared2", mout_cmu_shared2_pll_p, PLL_CON0_PLL_SHARED2, 4, 1),
+ MUX(0, "mout_cmu_pll_shared3", mout_cmu_shared3_pll_p, PLL_CON0_PLL_SHARED3, 4, 1),
+ MUX(0, "mout_cmu_cis0_clkmux", mout_cmu_cis0_clkmux_p, MUX_CMU_CIS0_CLKMUX, 0, 1),
+ MUX(0, "mout_cmu_cis1_clkmux", mout_cmu_cis1_clkmux_p, MUX_CMU_CIS1_CLKMUX, 0, 1),
+ MUX(0, "mout_cmu_cis2_clkmux", mout_cmu_cis2_clkmux_p, MUX_CMU_CIS2_CLKMUX, 0, 1),
+ MUX(0, "mout_cmu_cpucl_switchmux", mout_cmu_cpucl_switchmux_p,
+ MUX_CMU_CPUCL_SWITCHMUX, 0, 1),
+ MUX(0, "mout_cmu_fsys1_aclk_mux", mout_cmu_fsys1_aclk_mux_p, MUX_CMU_FSYS1_ACLK_MUX, 0, 1),
+ MUX(0, "mout_cmu_pll_shared0_mux", mout_cmu_pll_shared0_mux_p, MUX_PLL_SHARED0_MUX, 0, 1),
+ MUX(0, "mout_cmu_pll_shared1_mux", mout_cmu_pll_shared1_mux_p, MUX_PLL_SHARED1_MUX, 0, 1),
+};
+
+static const struct samsung_div_clock cmu_div_clks[] __initconst = {
+ DIV(0, "dout_cmu_cis0_clk", "cmu_cis0_clkgate", DIV_CMU_CIS0_CLK, 0, 4),
+ DIV(0, "dout_cmu_cis1_clk", "cmu_cis1_clkgate", DIV_CMU_CIS1_CLK, 0, 4),
+ DIV(0, "dout_cmu_cis2_clk", "cmu_cis2_clkgate", DIV_CMU_CIS2_CLK, 0, 4),
+ DIV(0, "dout_cmu_cmu_aclk", "dout_cmu_pll_shared1_div9", DIV_CMU_CMU_ACLK, 0, 4),
+ DIV(0, "dout_cmu_cpucl_switch", "cmu_cpucl_switch_gate", DIV_CMU_CPUCL_SWITCH, 0, 4),
+ DIV(DOUT_CMU_FSYS0_SHARED0DIV4, "dout_cmu_fsys0_shared0div4", "cmu_fsys0_shared0div4_gate",
+ DIV_CMU_FSYS0_SHARED0DIV4, 0, 4),
+ DIV(0, "dout_cmu_fsys0_shared1div3", "cmu_fsys0_shared1div4_clk",
+ DIV_CMU_FSYS0_SHARED1DIV3, 0, 4),
+ DIV(DOUT_CMU_FSYS0_SHARED1DIV4, "dout_cmu_fsys0_shared1div4", "cmu_fsys0_shared1div4_gate",
+ DIV_CMU_FSYS0_SHARED1DIV4, 0, 4),
+ DIV(DOUT_CMU_FSYS1_SHARED0DIV4, "dout_cmu_fsys1_shared0div4", "cmu_fsys1_shared0div4_gate",
+ DIV_CMU_FSYS1_SHARED0DIV4, 0, 4),
+ DIV(DOUT_CMU_FSYS1_SHARED0DIV8, "dout_cmu_fsys1_shared0div8", "cmu_fsys1_shared1div4_gate",
+ DIV_CMU_FSYS1_SHARED0DIV8, 0, 4),
+ DIV(DOUT_CMU_IMEM_ACLK, "dout_cmu_imem_aclk", "cmu_imem_aclk_gate",
+ DIV_CMU_IMEM_ACLK, 0, 4),
+ DIV(DOUT_CMU_IMEM_DMACLK, "dout_cmu_imem_dmaclk", "cmu_imem_dmaclk_gate",
+ DIV_CMU_IMEM_DMACLK, 0, 4),
+ DIV(DOUT_CMU_IMEM_TCUCLK, "dout_cmu_imem_tcuclk", "cmu_imem_tcuclk_gate",
+ DIV_CMU_IMEM_TCUCLK, 0, 4),
+ DIV(DOUT_CMU_PERIC_SHARED0DIV20, "dout_cmu_peric_shared0div20",
+ "cmu_peric_shared0dive4_gate", DIV_CMU_PERIC_SHARED0DIV20, 0, 4),
+ DIV(DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK, "dout_cmu_peric_shared0div3_tbuclk",
+ "cmu_peric_shared0dive3_tbuclk_gate", DIV_CMU_PERIC_SHARED0DIV3_TBUCLK, 0, 4),
+ DIV(DOUT_CMU_PERIC_SHARED1DIV36, "dout_cmu_peric_shared1div36",
+ "cmu_peric_shared1dive4_gate", DIV_CMU_PERIC_SHARED1DIV36, 0, 4),
+ DIV(DOUT_CMU_PERIC_SHARED1DIV4_DMACLK, "dout_cmu_peric_shared1div4_dmaclk",
+ "cmu_peric_shared1div4_dmaclk_gate", DIV_CMU_PERIC_SHARED1DIV4_DMACLK, 0, 4),
+ DIV(0, "dout_cmu_pll_shared0_div2", "mout_cmu_pll_shared0_mux",
+ DIV_PLL_SHARED0_DIV2, 0, 4),
+ DIV(0, "dout_cmu_pll_shared0_div3", "mout_cmu_pll_shared0_mux",
+ DIV_PLL_SHARED0_DIV3, 0, 4),
+ DIV(DOUT_CMU_PLL_SHARED0_DIV4, "dout_cmu_pll_shared0_div4", "dout_cmu_pll_shared0_div2",
+ DIV_PLL_SHARED0_DIV4, 0, 4),
+ DIV(DOUT_CMU_PLL_SHARED0_DIV6, "dout_cmu_pll_shared0_div6", "dout_cmu_pll_shared0_div3",
+ DIV_PLL_SHARED0_DIV6, 0, 4),
+ DIV(0, "dout_cmu_pll_shared1_div3", "mout_cmu_pll_shared1_mux",
+ DIV_PLL_SHARED1_DIV3, 0, 4),
+ DIV(0, "dout_cmu_pll_shared1_div36", "dout_cmu_pll_shared1_div9",
+ DIV_PLL_SHARED1_DIV36, 0, 4),
+ DIV(0, "dout_cmu_pll_shared1_div4", "mout_cmu_pll_shared1_mux",
+ DIV_PLL_SHARED1_DIV4, 0, 4),
+ DIV(0, "dout_cmu_pll_shared1_div9", "dout_cmu_pll_shared1_div3",
+ DIV_PLL_SHARED1_DIV9, 0, 4),
+};
+
+static const struct samsung_gate_clock cmu_gate_clks[] __initconst = {
+ GATE(0, "cmu_cis0_clkgate", "mout_cmu_cis0_clkmux", GAT_CMU_CIS0_CLKGATE, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_cis1_clkgate", "mout_cmu_cis1_clkmux", GAT_CMU_CIS1_CLKGATE, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_cis2_clkgate", "mout_cmu_cis2_clkmux", GAT_CMU_CIS2_CLKGATE, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CMU_CPUCL_SWITCH_GATE, "cmu_cpucl_switch_gate", "mout_cmu_cpucl_switchmux",
+ GAT_CMU_CPUCL_SWITCH_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(GAT_CMU_FSYS0_SHARED0DIV4, "cmu_fsys0_shared0div4_gate", "dout_cmu_pll_shared0_div4",
+ GAT_CMU_FSYS0_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_fsys0_shared1div4_clk", "dout_cmu_pll_shared1_div3",
+ GAT_CMU_FSYS0_SHARED1DIV4_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_fsys0_shared1div4_gate", "dout_cmu_pll_shared1_div4",
+ GAT_CMU_FSYS0_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_fsys1_shared0div4_gate", "mout_cmu_fsys1_aclk_mux",
+ GAT_CMU_FSYS1_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_fsys1_shared1div4_gate", "dout_cmu_fsys1_shared0div4",
+ GAT_CMU_FSYS1_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_imem_aclk_gate", "dout_cmu_pll_shared1_div9", GAT_CMU_IMEM_ACLK_GATE, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_imem_dmaclk_gate", "mout_cmu_pll_shared1_mux", GAT_CMU_IMEM_DMACLK_GATE, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_imem_tcuclk_gate", "dout_cmu_pll_shared0_div3", GAT_CMU_IMEM_TCUCLK_GATE, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_peric_shared0dive3_tbuclk_gate", "dout_cmu_pll_shared0_div3",
+ GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_peric_shared0dive4_gate", "dout_cmu_pll_shared0_div4",
+ GAT_CMU_PERIC_SHARED0DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_peric_shared1div4_dmaclk_gate", "dout_cmu_pll_shared1_div4",
+ GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_peric_shared1dive4_gate", "dout_cmu_pll_shared1_div36",
+ GAT_CMU_PERIC_SHARED1DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_uid_cmu_cmu_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk",
+ GAT_CMU_CMU_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_uid_axi2apb_cmu_ipclkport_aclk", "dout_cmu_cmu_aclk",
+ GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_uid_ns_brdg_cmu_ipclkport_clk__psoc_cmu__clk_cmu", "dout_cmu_cmu_aclk",
+ GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_uid_sysreg_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk",
+ GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info cmu_cmu_info __initconst = {
+ .pll_clks = cmu_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(cmu_pll_clks),
+ .mux_clks = cmu_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cmu_mux_clks),
+ .div_clks = cmu_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cmu_div_clks),
+ .gate_clks = cmu_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cmu_gate_clks),
+ .nr_clk_ids = CMU_NR_CLK,
+ .clk_regs = cmu_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cmu_clk_regs),
+};
+
+static void __init fsd_clk_cmu_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &cmu_cmu_info);
+}
+
+CLK_OF_DECLARE(fsd_clk_cmu, "tesla,fsd-clock-cmu", fsd_clk_cmu_init);
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 70cdc87f714e..fe383471c5f0 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -1469,6 +1469,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
case pll_1450x:
case pll_1451x:
case pll_1452x:
+ case pll_142xx:
pll->enable_offs = PLL35XX_ENABLE_SHIFT;
pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
if (!pll->rate_table)
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index c83a20195f6d..a9892c2d1f57 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -39,6 +39,7 @@ enum samsung_pll_type {
pll_1460x,
pll_0822x,
pll_0831x,
+ pll_142xx,
};
#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
--
2.25.1
^ permalink raw reply related
* [PATCH v3 03/16] dt-bindings: clock: Document FSD CMU bindings
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar, linux-fsd
In-Reply-To: <20220121172840.12121-1-alim.akhtar@samsung.com>
Add dt-schema documentation for Tesla FSD SoC clock controller.
Cc: linux-fsd@tesla.com
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
.../bindings/clock/tesla,fsd-clock.yaml | 198 ++++++++++++++++++
1 file changed, 198 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
new file mode 100644
index 000000000000..dc808e2f8327
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
@@ -0,0 +1,198 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tesla FSD (Full Self-Driving) SoC clock controller
+
+maintainers:
+ - Alim Akhtar <alim.akhtar@samsung.com>
+ - linux-fsd@tesla.com
+
+description: |
+ FSD clock controller consist of several clock management unit
+ (CMU), which generates clocks for various inteernal SoC blocks.
+ The root clock comes from external OSC clock (24 MHz).
+
+ All available clocks are defined as preprocessor macros in
+ 'dt-bindings/clock/fsd-clk.h' header.
+
+properties:
+ compatible:
+ enum:
+ - tesla,fsd-clock-cmu
+ - tesla,fsd-clock-imem
+ - tesla,fsd-clock-peric
+ - tesla,fsd-clock-fsys0
+ - tesla,fsd-clock-fsys1
+ - tesla,fsd-clock-mfc
+ - tesla,fsd-clock-cam_csi
+
+ clocks:
+ minItems: 1
+ maxItems: 6
+
+ clock-names:
+ minItems: 1
+ maxItems: 6
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-cmu
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ clock-names:
+ items:
+ - const: fin_pll
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-imem
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ - description: IMEM TCU clock (from CMU_CMU)
+ - description: IMEM bus clock (from CMU_CMU)
+ - description: IMEM DMA clock (from CMU_CMU)
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_cmu_imem_tcuclk
+ - const: dout_cmu_imem_aclk
+ - const: dout_cmu_imem_dmaclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-peric
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ - description: Shared0 PLL div4 clock (from CMU_CMU)
+ - description: PERIC shared1 div36 clock (from CMU_CMU)
+ - description: PERIC shared0 div3 TBU clock (from CMU_CMU)
+ - description: PERIC shared0 div20 clock (from CMU_CMU)
+ - description: PERIC shared1 div4 DMAclock (from CMU_CMU)
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_cmu_pll_shared0_div4
+ - const: dout_cmu_peric_shared1div36
+ - const: dout_cmu_peric_shared0div3_tbuclk
+ - const: dout_cmu_peric_shared0div20
+ - const: dout_cmu_peric_shared1div4_dmaclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-fsys0
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ - description: Shared0 PLL div6 clock (from CMU_CMU)
+ - description: FSYS0 shared1 div4 clock (from CMU_CMU)
+ - description: FSYS0 shared0 div4 clock (from CMU_CMU)
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_cmu_pll_shared0_div6
+ - const: dout_cmu_fsys0_shared1div4
+ - const: dout_cmu_fsys0_shared0div4
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-fsys1
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ - description: FSYS1 shared0 div8 clock (from CMU_CMU)
+ - description: FSYS1 shared0 div4 clock (from CMU_CMU)
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_cmu_fsys1_shared0div8
+ - const: dout_cmu_fsys1_shared0div4
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-mfc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ clock-names:
+ items:
+ - const: fin_pll
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-cam_csi
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ clock-names:
+ items:
+ - const: fin_pll
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ - reg
+
+additionalProperties: false
+
+examples:
+ # Clock controller node for CMU_FSYS1
+ - |
+ #include <dt-bindings/clock/fsd-clk.h>
+
+ clock_fsys1: clock-controller@16810000 {
+ compatible = "tesla,fsd-clock-fsys1";
+ reg = <0x16810000 0x3000>;
+ #clock-cells = <1>;
+
+ clocks = <&fin_pll>,
+ <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,
+ <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>;
+ clock-names = "fin_pll",
+ "dout_cmu_fsys1_shared0div8",
+ "dout_cmu_fsys1_shared0div4";
+ };
+
+...
--
2.25.1
^ permalink raw reply related
* [PATCH v3 02/16] dt-bindings: clock: Add bindings definitions for FSD CMU blocks
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar, linux-fsd
In-Reply-To: <20220121172840.12121-1-alim.akhtar@samsung.com>
Clock controller driver of FSD platform is designed to have separate
instances for each particular CMU. So clock IDs in this bindings header
also start from 1 for each CMU block.
Cc: linux-fsd@tesla.com
Reported-by: kernel test robot <lkp@intel.com>
[robot: reported missing #endif]
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
include/dt-bindings/clock/fsd-clk.h | 150 ++++++++++++++++++++++++++++
1 file changed, 150 insertions(+)
create mode 100644 include/dt-bindings/clock/fsd-clk.h
diff --git a/include/dt-bindings/clock/fsd-clk.h b/include/dt-bindings/clock/fsd-clk.h
new file mode 100644
index 000000000000..c8a2af1dd1ad
--- /dev/null
+++ b/include/dt-bindings/clock/fsd-clk.h
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd.
+ * https://www.samsung.com
+ * Copyright (c) 2017-2022 Tesla, Inc.
+ * https://www.tesla.com
+ *
+ * The constants defined in this header are being used in dts
+ * and fsd platform driver.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_FSD_H
+#define _DT_BINDINGS_CLOCK_FSD_H
+
+/* CMU */
+#define DOUT_CMU_PLL_SHARED0_DIV4 1
+#define DOUT_CMU_PERIC_SHARED1DIV36 2
+#define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK 3
+#define DOUT_CMU_PERIC_SHARED0DIV20 4
+#define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK 5
+#define DOUT_CMU_PLL_SHARED0_DIV6 6
+#define DOUT_CMU_FSYS0_SHARED1DIV4 7
+#define DOUT_CMU_FSYS0_SHARED0DIV4 8
+#define DOUT_CMU_FSYS1_SHARED0DIV8 9
+#define DOUT_CMU_FSYS1_SHARED0DIV4 10
+#define CMU_CPUCL_SWITCH_GATE 11
+#define DOUT_CMU_IMEM_TCUCLK 12
+#define DOUT_CMU_IMEM_ACLK 13
+#define DOUT_CMU_IMEM_DMACLK 14
+#define GAT_CMU_FSYS0_SHARED0DIV4 15
+#define CMU_NR_CLK 16
+
+/* PERIC */
+#define PERIC_SCLK_UART0 1
+#define PERIC_PCLK_UART0 2
+#define PERIC_SCLK_UART1 3
+#define PERIC_PCLK_UART1 4
+#define PERIC_DMA0_IPCLKPORT_ACLK 5
+#define PERIC_DMA1_IPCLKPORT_ACLK 6
+#define PERIC_PWM0_IPCLKPORT_I_PCLK_S0 7
+#define PERIC_PWM1_IPCLKPORT_I_PCLK_S0 8
+#define PERIC_PCLK_SPI0 9
+#define PERIC_SCLK_SPI0 10
+#define PERIC_PCLK_SPI1 11
+#define PERIC_SCLK_SPI1 12
+#define PERIC_PCLK_SPI2 13
+#define PERIC_SCLK_SPI2 14
+#define PERIC_PCLK_TDM0 15
+#define PERIC_PCLK_HSI2C0 16
+#define PERIC_PCLK_HSI2C1 17
+#define PERIC_PCLK_HSI2C2 18
+#define PERIC_PCLK_HSI2C3 19
+#define PERIC_PCLK_HSI2C4 20
+#define PERIC_PCLK_HSI2C5 21
+#define PERIC_PCLK_HSI2C6 22
+#define PERIC_PCLK_HSI2C7 23
+#define PERIC_MCAN0_IPCLKPORT_CCLK 24
+#define PERIC_MCAN0_IPCLKPORT_PCLK 25
+#define PERIC_MCAN1_IPCLKPORT_CCLK 26
+#define PERIC_MCAN1_IPCLKPORT_PCLK 27
+#define PERIC_MCAN2_IPCLKPORT_CCLK 28
+#define PERIC_MCAN2_IPCLKPORT_PCLK 29
+#define PERIC_MCAN3_IPCLKPORT_CCLK 30
+#define PERIC_MCAN3_IPCLKPORT_PCLK 31
+#define PERIC_PCLK_ADCIF 32
+#define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 33
+#define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I 34
+#define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I 35
+#define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 36
+#define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I 37
+#define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK 38
+#define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK 39
+#define PERIC_HCLK_TDM0 40
+#define PERIC_PCLK_TDM1 41
+#define PERIC_HCLK_TDM1 42
+#define PERIC_EQOS_PHYRXCLK_MUX 43
+#define PERIC_EQOS_PHYRXCLK 44
+#define PERIC_DOUT_RGMII_CLK 45
+#define PERIC_NR_CLK 46
+
+/* FSYS0 */
+#define UFS0_MPHY_REFCLK_IXTAL24 1
+#define UFS0_MPHY_REFCLK_IXTAL26 2
+#define UFS1_MPHY_REFCLK_IXTAL24 3
+#define UFS1_MPHY_REFCLK_IXTAL26 4
+#define UFS0_TOP0_HCLK_BUS 5
+#define UFS0_TOP0_ACLK 6
+#define UFS0_TOP0_CLK_UNIPRO 7
+#define UFS0_TOP0_FMP_CLK 8
+#define UFS1_TOP1_HCLK_BUS 9
+#define UFS1_TOP1_ACLK 10
+#define UFS1_TOP1_CLK_UNIPRO 11
+#define UFS1_TOP1_FMP_CLK 12
+#define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC 13
+#define PCIE_SUBCTRL_INST0_AUX_CLK_SOC 14
+#define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC 15
+#define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC 16
+#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 17
+#define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 18
+#define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 19
+#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20
+#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21
+#define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22
+#define FSYS0_NR_CLK 23
+
+/* FSYS1 */
+#define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1
+#define PCIE_LINK0_IPCLKPORT_AUX_ACLK 2
+#define PCIE_LINK0_IPCLKPORT_MSTR_ACLK 3
+#define PCIE_LINK0_IPCLKPORT_SLV_ACLK 4
+#define PCIE_LINK1_IPCLKPORT_DBI_ACLK 5
+#define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6
+#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7
+#define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8
+#define FSYS1_NR_CLK 9
+
+/* IMEM */
+#define IMEM_DMA0_IPCLKPORT_ACLK 1
+#define IMEM_DMA1_IPCLKPORT_ACLK 2
+#define IMEM_WDT0_IPCLKPORT_PCLK 3
+#define IMEM_WDT1_IPCLKPORT_PCLK 4
+#define IMEM_WDT2_IPCLKPORT_PCLK 5
+#define IMEM_MCT_PCLK 6
+#define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 7
+#define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 8
+#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9
+#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10
+#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11
+#define IMEM_NR_CLK 12
+
+/* MFC */
+#define MFC_MFC_IPCLKPORT_ACLK 1
+#define MFC_NR_CLK 2
+
+/* CAM_CSI */
+#define CAM_CSI0_0_IPCLKPORT_I_ACLK 1
+#define CAM_CSI0_1_IPCLKPORT_I_ACLK 2
+#define CAM_CSI0_2_IPCLKPORT_I_ACLK 3
+#define CAM_CSI0_3_IPCLKPORT_I_ACLK 4
+#define CAM_CSI1_0_IPCLKPORT_I_ACLK 5
+#define CAM_CSI1_1_IPCLKPORT_I_ACLK 6
+#define CAM_CSI1_2_IPCLKPORT_I_ACLK 7
+#define CAM_CSI1_3_IPCLKPORT_I_ACLK 8
+#define CAM_CSI2_0_IPCLKPORT_I_ACLK 9
+#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10
+#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11
+#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12
+#define CAM_CSI_NR_CLK 13
+
+#endif /*_DT_BINDINGS_CLOCK_FSD_H */
--
2.25.1
^ permalink raw reply related
* [PATCH v3 01/16] dt-bindings: add vendor prefix for Tesla
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar, linux-fsd
In-Reply-To: <20220121172840.12121-1-alim.akhtar@samsung.com>
Add vendor prefix for the Tesla (https://www.tesla.com)
Cc: linux-fsd@tesla.com
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 64c604752052..09fbef521394 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1209,6 +1209,8 @@ patternProperties:
description: Shenzhen Techstar Electronics Co., Ltd.
"^terasic,.*":
description: Terasic Inc.
+ "^tesla,.*":
+ description: Tesla, Inc.
"^tfc,.*":
description: Three Five Corp
"^thead,.*":
--
2.25.1
^ permalink raw reply related
* [PATCH v3 00/16] Add support for Tesla Full Self-Driving (FSD) SoC
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar
In-Reply-To: <CGME20220121174016epcas5p347510c17404c703f6b857bc43413ed2a@epcas5p3.samsung.com>
Adds basic support for the Tesla Full Self-Driving (FSD)
SoC. This SoC contains three clusters of four Cortex-A72 CPUs,
as well as several IPs.
Patches 1 to 9 provide support for the clock controller
(which is designed similarly to Exynos SoCs).
The remaining changes provide pinmux support, initial device tree support.
- Changes since v2
* Addressed Krzysztof's and Stephen's review comments
* Added Reviewed-by and Acked-by tags
* Rebased on next-20220120
- Changes since v1
* fixed make dt_binding_check error as pointed by Rob
* Addressed Krzysztof's and Rob's review comments
* Added Reviewed-by and Acked-by tags
* Dropped SPI, MCT and ADC from this series (to be posted in small sets)
NOTE: These patches are based on next-20220120
Alim Akhtar (16):
dt-bindings: add vendor prefix for Tesla
dt-bindings: clock: Add bindings definitions for FSD CMU blocks
dt-bindings: clock: Document FSD CMU bindings
clk: samsung: fsd: Add initial clock support
clk: samsung: fsd: Add cmu_peric block clock information
clk: samsung: fsd: Add cmu_fsys0 clock information
clk: samsung: fsd: Add cmu_fsys1 clock information
clk: samsung: fsd: Add cmu_imem block clock information
clk: samsung: fsd: Add cmu_mfc block clock information
clk: samsung: fsd: Add cam_csi block clock information
dt-bindings: pinctrl: samsung: Add compatible for Tesla FSD SoC
pinctrl: samsung: add FSD SoC specific data
dt-bindings: arm: add Tesla FSD ARM SoC
arm64: dts: fsd: Add initial device tree support
arm64: dts: fsd: Add initial pinctrl support
arm64: defconfig: Enable Tesla FSD SoC
.../devicetree/bindings/arm/tesla.yaml | 27 +
.../bindings/clock/tesla,fsd-clock.yaml | 198 ++
.../bindings/pinctrl/samsung-pinctrl.txt | 1 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 8 +
arch/arm64/Kconfig.platforms | 6 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/tesla/Makefile | 3 +
arch/arm64/boot/dts/tesla/fsd-evb.dts | 39 +
arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 335 +++
arch/arm64/boot/dts/tesla/fsd.dtsi | 673 ++++++
arch/arm64/configs/defconfig | 1 +
drivers/clk/samsung/Kconfig | 8 +
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-fsd.c | 1803 +++++++++++++++++
drivers/clk/samsung/clk-pll.c | 1 +
drivers/clk/samsung/clk-pll.h | 1 +
.../pinctrl/samsung/pinctrl-exynos-arm64.c | 71 +
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
include/dt-bindings/clock/fsd-clk.h | 150 ++
21 files changed, 3332 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/tesla.yaml
create mode 100644 Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
create mode 100644 arch/arm64/boot/dts/tesla/Makefile
create mode 100644 arch/arm64/boot/dts/tesla/fsd-evb.dts
create mode 100644 arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/tesla/fsd.dtsi
create mode 100644 drivers/clk/samsung/clk-fsd.c
create mode 100644 include/dt-bindings/clock/fsd-clk.h
base-commit: 7fc5253f5a13271e9df35d6b936ff97b74540a59
--
2.25.1
^ permalink raw reply
* Re: [PATCH v3 2/6] ASoC: xilinx: xlnx_i2s: create drvdata structure
From: Robert Hancock @ 2022-01-21 17:26 UTC (permalink / raw)
To: amadeuszx.slawinski@linux.intel.com, alsa-devel@alsa-project.org
Cc: maruthi.srinivas.bayyavarapu@xilinx.com, robh+dt@kernel.org,
devicetree@vger.kernel.org, michal.simek@xilinx.com,
broonie@kernel.org, kuninori.morimoto.gx@renesas.com,
tiwai@suse.com, lgirdwood@gmail.com
In-Reply-To: <aa839d9e-76b8-1ee2-048b-1982ff9bdb31@linux.intel.com>
On Fri, 2022-01-21 at 10:06 +0100, Amadeusz Sławiński wrote:
> On 1/20/2022 8:58 PM, Robert Hancock wrote:
> > An upcoming change will require storing additional driver data other
> > than the memory base address. Create a drvdata structure and use that
> > rather than storing the raw base address pointer.
> >
> > Signed-off-by: Robert Hancock <robert.hancock@calian.com>
> > ---
> > sound/soc/xilinx/xlnx_i2s.c | 66 ++++++++++++++++++++-----------------
> > 1 file changed, 35 insertions(+), 31 deletions(-)
> >
> > diff --git a/sound/soc/xilinx/xlnx_i2s.c b/sound/soc/xilinx/xlnx_i2s.c
> > index cc641e582c82..3bafa34b789a 100644
> > --- a/sound/soc/xilinx/xlnx_i2s.c
> > +++ b/sound/soc/xilinx/xlnx_i2s.c
> > @@ -22,15 +22,20 @@
> > #define I2S_CH0_OFFSET 0x30
> > #define I2S_I2STIM_VALID_MASK GENMASK(7, 0)
> >
> > +struct xlnx_i2s_drv_data {
> > + struct snd_soc_dai_driver dai_drv;
> > + void __iomem *base;
> > +};
> > +
> > static int xlnx_i2s_set_sclkout_div(struct snd_soc_dai *cpu_dai,
> > int div_id, int div)
> > {
> > - void __iomem *base = snd_soc_dai_get_drvdata(cpu_dai);
> > + struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(cpu_dai);
> >
> > if (!div || (div & ~I2S_I2STIM_VALID_MASK))
> > return -EINVAL;
> >
> > - writel(div, base + I2S_I2STIM_OFFSET);
> > + writel(div, drv_data->base + I2S_I2STIM_OFFSET);
> >
> > return 0;
> > }
> > @@ -40,13 +45,13 @@ static int xlnx_i2s_hw_params(struct snd_pcm_substream
> > *substream,
> > struct snd_soc_dai *i2s_dai)
> > {
> > u32 reg_off, chan_id;
> > - void __iomem *base = snd_soc_dai_get_drvdata(i2s_dai);
> > + struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(i2s_dai);
> >
> > chan_id = params_channels(params) / 2;
> >
> > while (chan_id > 0) {
> > reg_off = I2S_CH0_OFFSET + ((chan_id - 1) * 4);
> > - writel(chan_id, base + reg_off);
> > + writel(chan_id, drv_data->base + reg_off);
> > chan_id--;
> > }
> >
> > @@ -56,18 +61,18 @@ static int xlnx_i2s_hw_params(struct snd_pcm_substream
> > *substream,
> > static int xlnx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
> > struct snd_soc_dai *i2s_dai)
> > {
> > - void __iomem *base = snd_soc_dai_get_drvdata(i2s_dai);
> > + struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(i2s_dai);
> >
> > switch (cmd) {
> > case SNDRV_PCM_TRIGGER_START:
> > case SNDRV_PCM_TRIGGER_RESUME:
> > case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
> > - writel(1, base + I2S_CORE_CTRL_OFFSET);
> > + writel(1, drv_data->base + I2S_CORE_CTRL_OFFSET);
> > break;
> > case SNDRV_PCM_TRIGGER_STOP:
> > case SNDRV_PCM_TRIGGER_SUSPEND:
> > case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
> > - writel(0, base + I2S_CORE_CTRL_OFFSET);
> > + writel(0, drv_data->base + I2S_CORE_CTRL_OFFSET);
> > break;
> > default:
> > return -EINVAL;
> > @@ -95,20 +100,19 @@ MODULE_DEVICE_TABLE(of, xlnx_i2s_of_match);
> >
> > static int xlnx_i2s_probe(struct platform_device *pdev)
> > {
> > - void __iomem *base;
> > - struct snd_soc_dai_driver *dai_drv;
> > + struct xlnx_i2s_drv_data *drv_data;
> > int ret;
> > u32 ch, format, data_width;
> > struct device *dev = &pdev->dev;
> > struct device_node *node = dev->of_node;
> >
> > - dai_drv = devm_kzalloc(&pdev->dev, sizeof(*dai_drv), GFP_KERNEL);
> > - if (!dai_drv)
> > + drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL);
> > + if (!drv_data)
> > return -ENOMEM;
> >
> > - base = devm_platform_ioremap_resource(pdev, 0);
> > - if (IS_ERR(base))
> > - return PTR_ERR(base);
> > + drv_data->base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(drv_data->base))
> > + return PTR_ERR(drv_data->base);
> >
> > ret = of_property_read_u32(node, "xlnx,num-channels", &ch);
> > if (ret < 0) {
> > @@ -134,35 +138,35 @@ static int xlnx_i2s_probe(struct platform_device
> > *pdev)
> > }
> >
> > if (of_device_is_compatible(node, "xlnx,i2s-transmitter-1.0")) {
> > - dai_drv->name = "xlnx_i2s_playback";
> > - dai_drv->playback.stream_name = "Playback";
> > - dai_drv->playback.formats = format;
> > - dai_drv->playback.channels_min = ch;
> > - dai_drv->playback.channels_max = ch;
> > - dai_drv->playback.rates = SNDRV_PCM_RATE_8000_192000;
> > - dai_drv->ops = &xlnx_i2s_dai_ops;
> > + drv_data->dai_drv.name = "xlnx_i2s_playback";
> > + drv_data->dai_drv.playback.stream_name = "Playback";
> > + drv_data->dai_drv.playback.formats = format;
> > + drv_data->dai_drv.playback.channels_min = ch;
> > + drv_data->dai_drv.playback.channels_max = ch;
> > + drv_data->dai_drv.playback.rates =
> > SNDRV_PCM_RATE_8000_192000;
> > + drv_data->dai_drv.ops = &xlnx_i2s_dai_ops;
> > } else if (of_device_is_compatible(node, "xlnx,i2s-receiver-1.0")) {
> > - dai_drv->name = "xlnx_i2s_capture";
> > - dai_drv->capture.stream_name = "Capture";
> > - dai_drv->capture.formats = format;
> > - dai_drv->capture.channels_min = ch;
> > - dai_drv->capture.channels_max = ch;
> > - dai_drv->capture.rates = SNDRV_PCM_RATE_8000_192000;
> > - dai_drv->ops = &xlnx_i2s_dai_ops;
> > + drv_data->dai_drv.name = "xlnx_i2s_capture";
> > + drv_data->dai_drv.capture.stream_name = "Capture";
> > + drv_data->dai_drv.capture.formats = format;
> > + drv_data->dai_drv.capture.channels_min = ch;
> > + drv_data->dai_drv.capture.channels_max = ch;
> > + drv_data->dai_drv.capture.rates = SNDRV_PCM_RATE_8000_192000;
> > + drv_data->dai_drv.ops = &xlnx_i2s_dai_ops;
> > } else {
> > return -ENODEV;
> > }
> >
> > - dev_set_drvdata(&pdev->dev, base);
> > + dev_set_drvdata(&pdev->dev, drv_data);
> >
> > ret = devm_snd_soc_register_component(&pdev->dev, &xlnx_i2s_component,
> > - dai_drv, 1);
> > + &drv_data->dai_drv, 1);
> > if (ret) {
> > dev_err(&pdev->dev, "i2s component registration failed\n");
> > return ret;
> > }
> >
> > - dev_info(&pdev->dev, "%s DAI registered\n", dai_drv->name);
> > + dev_info(&pdev->dev, "%s DAI registered\n", drv_data->dai_drv.name);
> >
> > return ret;
> > }
>
> I don't think this patch is needed, snd_soc_dai, already has pointer to
> its snd_soc_dai_driver, so there is no need to keep it additionally in
> drvdata?
>
> https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/sound/soc-dai.h?h=v5.16*n431__;Iw!!IOGos0k!wK-VYGvndh29eBo3CZIPn7xG_X7ib4R8-hEVEyJc8aXkGoYORJ8cLH25u-K31eZAYe4$
>
>
It's not a pointer to the struct snd_soc_dai_driver that's in the drvdata
structure, snd_soc_dai_driver is actually part of the drvdata structure.
Previously it was allocating snd_soc_dai_driver by itself, and stuffing the
base address into the drvdata pointer. Now it's allocating one
xlnx_i2s_drv_data structure which contains both (and more attributes to come).
--
Robert Hancock
Senior Hardware Designer, Calian Advanced Technologies
www.calian.com
^ permalink raw reply
* [RFD]: Solving qcom unique unit address warnings
From: Vinod Koul @ 2022-01-21 17:08 UTC (permalink / raw)
To: Rob Herring, devicetree; +Cc: Bjorn Andersson, linux-arm-msm
Hi Rob,
On all Qualcomm SoCs there exists QUP serial engine. These engines are
loaded with a firmware by bootloader and can support a specific protocol
like I2C/SPI/uart etc.
Since the serial engine can support different protocols we end up
describing all the supported ones for this, as illustrated below from
sdm845 dts upstream:
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x008c0000 0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
iommus = <&apps_smmu 0x3 0x0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
interconnect-names = "qup-core";
status = "disabled";
i2c0: i2c@880000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
spi0: spi@880000 {
compatible = "qcom,geni-spi";
reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
uart0: serial@880000 {
compatible = "qcom,geni-uart";
reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
The problem comes with all these nodes having same unit addresses. This
is adding to ~2K warning for unique_unit_address upstream.
So to solve this we thought of creating a qup se node and then query the
protocol supported from the firmware on boot and create a child
auxillary_device. The problem with that approach is another warning
"node name for SPI buses should be 'spi'"! So that would not help
Now, I cant think of any better idea here, except maybe move these to
respective board dts and perhaps keep them commented here for
documentation.
Do we have any better idea to solve this problem?
Thanks
--
~Vinod
^ permalink raw reply
* Re: [PATCH V4 XRT Alveo Infrastructure 3/5] of: create empty of root
From: Lizhi Hou @ 2022-01-21 16:54 UTC (permalink / raw)
To: Xu Yilun, Lizhi Hou
Cc: robh, linux-kernel, linux-fpga, maxz, sonal.santan, yliu,
michal.simek, stefanos, devicetree, trix, mdf, dwmw2, Max Zhen
In-Reply-To: <20220121014213.GA1102476@yilunxu-OptiPlex-7050>
Hi Yilun,
Thanks for your comments. To make the change simple and clear, I will
create a patch just for creating empty of_root and submit it to device
tree subsystem. I will CC you.
Lizhi
On 1/20/22 5:42 PM, Xu Yilun wrote:
>
> On Wed, Jan 19, 2022 at 10:59:48AM -0800, Lizhi Hou wrote:
>> Hi Yilun,
>>
>> Thanks for your comments. Overall, we made the code change based on Rob's
>> comments on previous patch set. Please see my inline comments for detail.
>>
>> Rob, please provide your guidance here.
>>
>> On 1/10/22 8:29 PM, Xu Yilun wrote:
>>> On Wed, Jan 05, 2022 at 02:50:11PM -0800, Lizhi Hou wrote:
>>>> When OF_FLATTREE is selected and there is not a device tree, create an
>>>> empty device tree root node. of/unittest.c code is referenced.
>>>>
>>>> Signed-off-by: Sonal Santan <sonal.santan@xilinx.com>
>>>> Signed-off-by: Max Zhen <max.zhen@xilinx.com>
>>>> Signed-off-by: Lizhi Hou <lizhi.hou@xilinx.com>
>>>> ---
>>>> drivers/of/Makefile | 5 +++
>>>> drivers/of/fdt.c | 90 ++++++++++++++++++++++++++++++++++++++
>>>> drivers/of/fdt_default.dts | 5 +++
>>>> drivers/of/of_private.h | 17 +++++++
>>>> drivers/of/unittest.c | 72 ++----------------------------
>>>> 5 files changed, 120 insertions(+), 69 deletions(-)
>>>> create mode 100644 drivers/of/fdt_default.dts
>>>>
>>>> diff --git a/drivers/of/Makefile b/drivers/of/Makefile
>>>> index c13b982084a3..a2989055c578 100644
>>>> --- a/drivers/of/Makefile
>>>> +++ b/drivers/of/Makefile
>>>> @@ -1,5 +1,6 @@
>>>> # SPDX-License-Identifier: GPL-2.0
>>>> obj-y = base.o device.o platform.o property.o
>>>> +
>>> remove the blank line.
>> Will remove.
>>>> obj-$(CONFIG_OF_KOBJ) += kobj.o
>>>> obj-$(CONFIG_OF_DYNAMIC) += dynamic.o
>>>> obj-$(CONFIG_OF_FLATTREE) += fdt.o
>>>> @@ -20,4 +21,8 @@ obj-y += kexec.o
>>>> endif
>>>> endif
>>>>
>>>> +ifndef CONFIG_OF_UNITTEST
>>>> +obj-$(CONFIG_OF_FLATTREE) += fdt_default.dtb.o
>>>> +endif
>>>> +
>>> Same question as Tom, the unittest should work well with or without
>>> of_root, is it? So creating an empty root will not affect unittest, so
>>> why so many ifdefs for CONFIG_OF_UNITTEST?
>> Based on Rob's comment in
>> https://lore.kernel.org/lkml/YaWFksVvfQQWqKcG@robh.at.kernel.org/, it needs
>> to have a unified code to set of_root with or without CONFIG_OF_UNITTEST
>> defined. So the unified code works as this during boot
>>
>> 1. With CONFIG_OF_UNITEST define, of_root is set to base tree
>> defined/compiled in testcases.dtb.o
>>
>> 2. Without CONFIG_OF_UNITEST, of_root is set to base tree defined/compiled
>> in fdt_default.dtb.o
>>
>>>> obj-$(CONFIG_OF_UNITTEST) += unittest-data/
>>>> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
>>>> index 4546572af24b..66ef9ac97829 100644
>>>> --- a/drivers/of/fdt.c
>>>> +++ b/drivers/of/fdt.c
>>>> @@ -466,6 +466,96 @@ void *of_fdt_unflatten_tree(const unsigned long *blob,
>>>> }
>>>> EXPORT_SYMBOL_GPL(of_fdt_unflatten_tree);
>>>>
>>>> +static int __init of_fdt_root_init(void)
>>>> +{
>>>> + struct device_node *dt = NULL, *np;
>>>> + void *fdt = NULL, *fdt_aligned;
>>>> + struct property *prop = NULL;
>>>> + __be32 *val = NULL;
>>>> + int size, rc = 0;
>>>> +
>>>> +#if !defined(CONFIG_OF_UNITTEST)
>>>> + if (of_root)
>>>> + return 0;
>>>> +#endif
>>>> + size = __dtb_fdt_default_end - __dtb_fdt_default_begin;
>>>> +
>>>> + fdt = kmalloc(size + FDT_ALIGN_SIZE, GFP_KERNEL);
>>>> + if (!fdt)
>>>> + return -ENOMEM;
>>>> +
>>>> + fdt_aligned = PTR_ALIGN(fdt, FDT_ALIGN_SIZE);
>>>> + memcpy(fdt_aligned, __dtb_fdt_default_begin, size);
>>>> +
>>>> + if (!of_fdt_unflatten_tree((const unsigned long *)fdt_aligned,
>>>> + NULL, &dt)) {
>>>> + pr_warn("%s: unflatten default tree failed\n", __func__);
>>>> + kfree(fdt);
>>>> + return -ENODATA;
>>>> + }
>>>> + if (!dt) {
>>>> + pr_warn("%s: empty default tree\n", __func__);
>>>> + kfree(fdt);
>>>> + return -ENODATA;
>>>> + }
>>>> +
>>>> + /*
>>>> + * This lock normally encloses of_resolve_phandles()
>>>> + */
>>>> + of_overlay_mutex_lock();
>>>> +
>>>> + rc = of_resolve_phandles(dt);
>>>> + if (rc) {
>>>> + pr_err("%s: Failed to resolve phandles (rc=%i)\n", __func__, rc);
>>>> + goto failed;
>>>> + }
>>>> +
>>>> + if (!of_root) {
>>>> + prop = kcalloc(2, sizeof(*prop), GFP_KERNEL);
>>>> + if (!prop) {
>>>> + rc = -ENOMEM;
>>>> + goto failed;
>>>> + }
>>>> + val = kzalloc(sizeof(*val), GFP_KERNEL);
>>>> + if (!val) {
>>>> + rc = -ENOMEM;
>>>> + goto failed;
>>>> + }
>>>> + *val = cpu_to_be32(sizeof(void *) / sizeof(u32));
>>>> +
>>>> + prop->name = "#address-cells";
>>>> + prop->value = val;
>>>> + prop->length = sizeof(u32);
>>>> + of_add_property(dt, prop);
>>>> + prop++;
>>>> + prop->name = "#size-cells";
>>>> + prop->value = val;
>>>> + prop->length = sizeof(u32);
>>>> + of_add_property(dt, prop);
>>>> + of_root = dt;
>>>> + for_each_of_allnodes(np)
>>>> + __of_attach_node_sysfs(np);
>>>> + of_aliases = of_find_node_by_path("/aliases");
>>>> + of_chosen = of_find_node_by_path("/chosen");
>>>> + of_overlay_mutex_unlock();
>>>> +pr_info("OF ROOT FLAG %lx\n", of_root->_flags);
>>>> + return 0;
>>>> + }
>>>> +
>>>> + unittest_data_add(dt);
>>> It's confusing to me. If we need to share some functions with unittest,
>>> make a new clearly defined (and named) function.
>> unittest_data_add() is not shared function. If CONFIG_OF_UNITTEST is not
>> defined, this is a null function (please see of_private.h). I just followed
>> the existing code style. e.g. of_property_notify() in of_private.h.
>>
>> Would adding some comments to describe this be good enough?
>>
>>>> +
>>>> + of_overlay_mutex_unlock();
>>>> +
>>>> + return 0;
>>>> +
>>>> +failed:
>>>> + of_overlay_mutex_unlock();
>>>> + kfree(val);
>>>> + kfree(prop);
>>>> + return rc;
>>>> +}
>>>> +pure_initcall(of_fdt_root_init);
>>> Is it better we have a new Kconfig option for the empty tree creation.
>> Sure, if needed.
>>>> +
>>>> /* Everything below here references initial_boot_params directly. */
>>>> int __initdata dt_root_addr_cells;
>>>> int __initdata dt_root_size_cells;
>>>> diff --git a/drivers/of/fdt_default.dts b/drivers/of/fdt_default.dts
>>>> new file mode 100644
>>>> index 000000000000..d1f12a76dfc6
>>>> --- /dev/null
>>>> +++ b/drivers/of/fdt_default.dts
>>>> @@ -0,0 +1,5 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>>> +/dts-v1/;
>>>> +
>>>> +/ {
>>>> +};
>>>> diff --git a/drivers/of/of_private.h b/drivers/of/of_private.h
>>>> index 631489f7f8c0..1ef93bccfdba 100644
>>>> --- a/drivers/of/of_private.h
>>>> +++ b/drivers/of/of_private.h
>>>> @@ -41,6 +41,18 @@ extern struct mutex of_mutex;
>>>> extern struct list_head aliases_lookup;
>>>> extern struct kset *of_kset;
>>>>
>>>> +#if defined(CONFIG_OF_UNITTEST)
>>>> +extern u8 __dtb_testcases_begin[];
>>>> +extern u8 __dtb_testcases_end[];
>>>> +#define __dtb_fdt_default_begin __dtb_testcases_begin
>>>> +#define __dtb_fdt_default_end __dtb_testcases_end
>>> Maybe we don't have to use the test dt data, stick to the default empty
>>> fdt is fine?
>> I am not sure I understand the point. test dt data contains a lot test nodes
>> and we should not create those nodes if CONFIG_OF_UNITTEST is not defined.
>>
>> Are you asking that we create empty of_root here and test nodes are created
>> in unittest.c? I believe that was we tried to do with previous patch. Is
>> this the same ask within your second comment?
> Yes, generally this is what I mean. I think you may have some
> misunderstanding for Rob's comments. My understanding is, to move the code
> from unittest to the of core, refactor them and make clearly defined
> functions, and let unittest call these functions.
>
> It is generally not reasonable the core uses help functions or test data
> from unittest.
>
>> We are open to change it back as previous patch does if needed.
>>
>> Rob, do you have any comment here?
>>
>>>> +void __init unittest_data_add(struct device_node *dt);
>>>> +#else
>>>> +extern u8 __dtb_fdt_default_begin[];
>>>> +extern u8 __dtb_fdt_default_end[];
>>>> +static inline void unittest_data_add(struct device_node *dt) {}
>>>> +#endif
>>>> +
>>>> #if defined(CONFIG_OF_DYNAMIC)
>>>> extern int of_property_notify(int action, struct device_node *np,
>>>> struct property *prop, struct property *old_prop);
>>>> @@ -84,6 +96,11 @@ static inline void __of_detach_node_sysfs(struct device_node *np) {}
>>>>
>>>> #if defined(CONFIG_OF_RESOLVE)
>>>> int of_resolve_phandles(struct device_node *tree);
>>>> +#else
>>>> +static inline int of_resolve_phandles(struct device_node *tree)
>>>> +{
>>>> + return 0;
>>>> +}
>>> If we have an empty of_resolve_phandles, does the empty tree creation
>>> still works? Or if we don't need this func, just delete in the code.
>> test nodes creation requires of_resolve_phandles() and creating empty
>> of_root does not. This define is added for unifying the code.
> If you don't need the of_resolve_phandles in core code, don't call it.
>
> Thanks,
> Yilun
>
>>
>> Thanks,
>>
>> Lizhi
>>
>>> Thanks,
>>> Yilun
>>>
>>>> #endif
>>>>
>>>> void __of_phandle_cache_inv_entry(phandle handle);
>>>> diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c
>>>> index 8c056972a6dd..745f455235cc 100644
>>>> --- a/drivers/of/unittest.c
>>>> +++ b/drivers/of/unittest.c
>>>> @@ -1402,73 +1402,15 @@ static void attach_node_and_children(struct device_node *np)
>>>> * unittest_data_add - Reads, copies data from
>>>> * linked tree and attaches it to the live tree
>>>> */
>>>> -static int __init unittest_data_add(void)
>>>> +void __init unittest_data_add(struct device_node *dt)
>>>> {
>>>> - void *unittest_data;
>>>> - void *unittest_data_align;
>>>> - struct device_node *unittest_data_node = NULL, *np;
>>>> - /*
>>>> - * __dtb_testcases_begin[] and __dtb_testcases_end[] are magically
>>>> - * created by cmd_dt_S_dtb in scripts/Makefile.lib
>>>> - */
>>>> - extern uint8_t __dtb_testcases_begin[];
>>>> - extern uint8_t __dtb_testcases_end[];
>>>> - const int size = __dtb_testcases_end - __dtb_testcases_begin;
>>>> - int rc;
>>>> - void *ret;
>>>> -
>>>> - if (!size) {
>>>> - pr_warn("%s: testcases is empty\n", __func__);
>>>> - return -ENODATA;
>>>> - }
>>>> -
>>>> - /* creating copy */
>>>> - unittest_data = kmalloc(size + FDT_ALIGN_SIZE, GFP_KERNEL);
>>>> - if (!unittest_data)
>>>> - return -ENOMEM;
>>>> -
>>>> - unittest_data_align = PTR_ALIGN(unittest_data, FDT_ALIGN_SIZE);
>>>> - memcpy(unittest_data_align, __dtb_testcases_begin, size);
>>>> -
>>>> - ret = of_fdt_unflatten_tree(unittest_data_align, NULL, &unittest_data_node);
>>>> - if (!ret) {
>>>> - pr_warn("%s: unflatten testcases tree failed\n", __func__);
>>>> - kfree(unittest_data);
>>>> - return -ENODATA;
>>>> - }
>>>> - if (!unittest_data_node) {
>>>> - pr_warn("%s: testcases tree is empty\n", __func__);
>>>> - kfree(unittest_data);
>>>> - return -ENODATA;
>>>> - }
>>>> -
>>>> - /*
>>>> - * This lock normally encloses of_resolve_phandles()
>>>> - */
>>>> - of_overlay_mutex_lock();
>>>> -
>>>> - rc = of_resolve_phandles(unittest_data_node);
>>>> - if (rc) {
>>>> - pr_err("%s: Failed to resolve phandles (rc=%i)\n", __func__, rc);
>>>> - of_overlay_mutex_unlock();
>>>> - return -EINVAL;
>>>> - }
>>>> -
>>>> - if (!of_root) {
>>>> - of_root = unittest_data_node;
>>>> - for_each_of_allnodes(np)
>>>> - __of_attach_node_sysfs(np);
>>>> - of_aliases = of_find_node_by_path("/aliases");
>>>> - of_chosen = of_find_node_by_path("/chosen");
>>>> - of_overlay_mutex_unlock();
>>>> - return 0;
>>>> - }
>>>> + struct device_node *np;
>>>>
>>>> EXPECT_BEGIN(KERN_INFO,
>>>> "Duplicate name in testcase-data, renamed to \"duplicate-name#1\"");
>>>>
>>>> /* attach the sub-tree to live tree */
>>>> - np = unittest_data_node->child;
>>>> + np = dt->child;
>>>> while (np) {
>>>> struct device_node *next = np->sibling;
>>>>
>>>> @@ -1479,10 +1421,6 @@ static int __init unittest_data_add(void)
>>>>
>>>> EXPECT_END(KERN_INFO,
>>>> "Duplicate name in testcase-data, renamed to \"duplicate-name#1\"");
>>>> -
>>>> - of_overlay_mutex_unlock();
>>>> -
>>>> - return 0;
>>>> }
>>>>
>>>> #ifdef CONFIG_OF_OVERLAY
>>>> @@ -3258,7 +3196,6 @@ static inline __init void of_unittest_overlay_high_level(void) {}
>>>> static int __init of_unittest(void)
>>>> {
>>>> struct device_node *np;
>>>> - int res;
>>>>
>>>> pr_info("start of unittest - you will see error messages\n");
>>>>
>>>> @@ -3267,9 +3204,6 @@ static int __init of_unittest(void)
>>>> if (IS_ENABLED(CONFIG_UML))
>>>> unittest_unflatten_overlay_base();
>>>>
>>>> - res = unittest_data_add();
>>>> - if (res)
>>>> - return res;
>>>> if (!of_aliases)
>>>> of_aliases = of_find_node_by_path("/aliases");
>>>>
>>>> --
>>>> 2.27.0
^ permalink raw reply
* Re: [PATCH v12, 2/2] net: Add dm9051 driver
From: Andrew Lunn @ 2022-01-21 16:43 UTC (permalink / raw)
To: Joseph CHAMG
Cc: David S . Miller, Jakub Kicinski, Rob Herring, joseph_chang,
netdev, devicetree, linux-kernel, andy.shevchenko,
Leon Romanovsky
In-Reply-To: <20220121041428.6437-3-josright123@gmail.com>
> +static int ctrl_dm9051_phywrite(void *context, unsigned int reg, unsigned int val)
> +{
> + /* chip internal operation need wait 1 ms for if power-up phy
> + */
> + if (reg == MII_BMCR && !(val & BMCR_PDOWN))
> + mdelay(1);
What PHY driver are you using? It would be much better to have this in
the PHY driver. The MAC driver should not be touching the PHY.
> +static int dm9051_phy_connect(struct board_info *db)
> +{
> + char phy_id[MII_BUS_ID_SIZE + 3];
> +
> + snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
> + db->mdiobus->id, DM9051_PHY_ID);
> +
> + db->phydev = phy_connect(db->ndev, phy_id, dm9051_handle_link_change,
> + PHY_INTERFACE_MODE_MII);
> + if (IS_ERR(db->phydev))
> + return PTR_ERR_OR_ZERO(db->phydev);
Why PTR_ERR_OR_ZERO()
> +static int dm9051_direct_fifo_reset(struct board_info *db)
> +{
> + struct net_device *ndev = db->ndev;
> + int rxlen = le16_to_cpu(db->eth_rxhdr.rxlen);
reverse christmas tree. There are a few more cases. Please review the
whole driver.
> +/* transmit a packet,
> + * return value,
> + * 0 - succeed
> + * -ETIMEDOUT - timeout error
> + */
> +static int dm9051_single_tx(struct board_info *db, u8 *buff, unsigned int len)
> +{
> + int ret;
> +
> + ret = dm9051_map_xmitpoll(db);
> + if (ret)
> + return -ETIMEDOUT;
> +
If dm9051_map_xmitpoll() returns an error code, use it. There needs to
be a good reason to change the error code, and if you have such a good
reason, please add a comment about it.
> +static irqreturn_t dm9051_rx_threaded_irq(int irq, void *pw)
> +{
> + struct board_info *db = pw;
> + int result, resul_tx;
> +
> + mutex_lock(&db->spi_lockm); /* mutex essential */
When are mutex's not essential? This commit seems to be
meaningless. It gives the impression you don't understand mutex's and
locking in general. You have just added mutex until it seems to work,
not that you have a locking design.
> + if (netif_carrier_ok(db->ndev)) {
> + result = regmap_write(db->regmap_dm, DM9051_IMR, IMR_PAR); /* disable imr */
> + if (unlikely(result))
> + goto spi_err;
> +
> + do {
> + result = dm9051_loop_rx(db); /* threaded irq rx */
> + if (result < 0)
> + goto spi_err;
> + resul_tx = dm9051_loop_tx(db); /* more tx better performance */
> + if (resul_tx < 0)
result_tx
^
> + goto spi_err;
> + } while (result > 0);
> +
> + result = regmap_write(db->regmap_dm, DM9051_IMR, db->imr_all); /* enable imr */
> + if (unlikely(result))
> + goto spi_err;
> + }
> +spi_err:
> + mutex_unlock(&db->spi_lockm); /* mutex essential */
> + return IRQ_HANDLED;
> +}
> +static int dm9051_map_phyup(struct board_info *db)
> +{
> + int ret;
> +
> + /* ~BMCR_PDOWN to power-up phyxcer
> + */
> + ret = mdiobus_modify(db->mdiobus, DM9051_PHY_ID, MII_BMCR, BMCR_PDOWN, 0);
> + if (ret < 0)
> + return ret;
> +
> + /* chip internal operation need wait 1 ms for if GPR power-up phy
> + */
> + ret = regmap_write(db->regmap_dm, DM9051_GPR, 0);
> + if (unlikely(ret))
> + return ret;
> + mdelay(1);
The phy driver should do this. Again, what PHY driver are you using?
> +static int dm9051_map_phydown(struct board_info *db)
> +{
> + int ret;
> +
> + ret = regmap_write(db->regmap_dm, DM9051_GPR, GPR_PHY_ON); /* Power-Down PHY */
> + if (unlikely(ret))
> + return ret;
> + return ret;
> +}
Cam you still access the PHY after this? Does it loose its
configuration?
> + /* We may have start with auto negotiation */
> + db->phydev->autoneg = AUTONEG_ENABLE;
> + db->phydev->speed = 0;
> + db->phydev->duplex = 0;
If you have to touch these, something is wrong. Please explain.
Andrew
^ permalink raw reply
* [PATCH v5 10/14] riscv: add cpufeature handling via alternatives
From: Heiko Stuebner @ 2022-01-21 16:36 UTC (permalink / raw)
To: palmer, paul.walmsley, aou
Cc: linux-riscv, devicetree, linux-kernel, robh+dt, wefu, liush,
guoren, atishp, anup, drew, hch, arnd, wens, maxime, dlustig,
gfavor, andrea.mondelli, behrensj, xinhaoqu, huffman, mick,
allen.baum, jscheid, rtrauben, samuel, cmuellner, philipp.tomsich,
Heiko Stuebner
In-Reply-To: <20220121163618.351934-1-heiko@sntech.de>
Some cpufeatures should be handled via the alternatives mechanism
to not incur penalties on unsupporting variants.
So add a mechanism to handle these similar to cpu erratas.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/riscv/include/asm/alternative.h | 3 ++
arch/riscv/include/asm/errata_list.h | 2 +
arch/riscv/kernel/alternative.c | 2 +
arch/riscv/kernel/cpufeature.c | 55 +++++++++++++++++++++++++++-
4 files changed, 61 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
index f0657b1b3174..cf3b22173834 100644
--- a/arch/riscv/include/asm/alternative.h
+++ b/arch/riscv/include/asm/alternative.h
@@ -39,5 +39,8 @@ struct errata_checkfunc_id {
void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
unsigned long archid, unsigned long impid,
unsigned int stage);
+
+void riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry *end,
+ unsigned int stage);
#endif
#endif
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 5f1046e82d9f..6b95bd9aee82 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -14,6 +14,8 @@
#define ERRATA_SIFIVE_NUMBER 2
#endif
+#define CPUFEATURE_NUMBER 0
+
#ifdef __ASSEMBLY__
#define ALT_INSN_FAULT(x) \
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index e1849faa2fa1..54913857b682 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -63,6 +63,8 @@ static void __init_or_module _apply_alternatives(struct alt_entry *begin,
struct alt_entry *end,
unsigned int stage)
{
+ riscv_cpufeature_patch_func(begin, end, stage);
+
if (!vendor_patch_func)
return;
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index d959d207a40d..fef804346d75 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -8,8 +8,12 @@
#include <linux/bitmap.h>
#include <linux/of.h>
-#include <asm/processor.h>
+#include <asm/alternative.h>
+#include <asm/errata_list.h>
#include <asm/hwcap.h>
+#include <asm/patch.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
#include <asm/smp.h>
#include <asm/switch_to.h>
@@ -149,3 +153,52 @@ void __init riscv_fill_hwcap(void)
static_branch_enable(&cpu_hwcap_fpu);
#endif
}
+
+struct cpufeature_info {
+ char name[ERRATA_STRING_LENGTH_MAX];
+ bool (*check_func)(unsigned int stage);
+};
+
+static const struct cpufeature_info cpufeature_list[CPUFEATURE_NUMBER] = {
+};
+
+static u32 __init cpufeature_probe(unsigned int stage)
+{
+ const struct cpufeature_info *info;
+ u32 cpu_req_feature = 0;
+ int idx;
+
+ for (idx = 0; idx < CPUFEATURE_NUMBER; idx++) {
+ info = &cpufeature_list[idx];
+
+ if (info->check_func(stage))
+ cpu_req_feature |= (1U << idx);
+ }
+
+ return cpu_req_feature;
+}
+
+void riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry *end,
+ unsigned int stage)
+{
+ u32 cpu_req_feature = cpufeature_probe(stage);
+ u32 cpu_apply_feature = 0;
+ struct alt_entry *alt;
+ u32 tmp;
+
+ for (alt = begin; alt < end; alt++) {
+ if (alt->vendor_id != 0)
+ continue;
+ if (alt->errata_id >= CPUFEATURE_NUMBER) {
+ WARN(1, "This feature id:%d is not in kernel cpufeature list",
+ alt->errata_id);
+ continue;
+ }
+
+ tmp = (1U << alt->errata_id);
+ if (cpu_req_feature & tmp) {
+ patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len);
+ cpu_apply_feature |= tmp;
+ }
+ }
+}
--
2.30.2
^ permalink raw reply related
* [PATCH v5 12/14] riscv: add RISC-V Svpbmt extension supports
From: Heiko Stuebner @ 2022-01-21 16:36 UTC (permalink / raw)
To: palmer, paul.walmsley, aou
Cc: linux-riscv, devicetree, linux-kernel, robh+dt, wefu, liush,
guoren, atishp, anup, drew, hch, arnd, wens, maxime, dlustig,
gfavor, andrea.mondelli, behrensj, xinhaoqu, huffman, mick,
allen.baum, jscheid, rtrauben, samuel, cmuellner, philipp.tomsich,
Heiko Stuebner, Palmer Dabbelt, Anup Patel, Atish Patra, Wei Wu
In-Reply-To: <20220121163618.351934-1-heiko@sntech.de>
From: Wei Fu <wefu@redhat.com>
This patch follows the standard pure RISC-V Svpbmt extension in
privilege spec to solve the non-coherent SOC dma synchronization
issues.
Here is the svpbmt PTE format:
| 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
N MT RSW D A G U X W R V
^
Of the Reserved bits [63:54] in a leaf PTE, the high bit is already
allocated (as the N bit), so bits [62:61] are used as the MT (aka
MemType) field. This field specifies one of three memory types that
are close equivalents (or equivalent in effect) to the three main x86
and ARMv8 memory types - as shown in the following table.
RISC-V
Encoding &
MemType RISC-V Description
---------- ------------------------------------------------
00 - PMA Normal Cacheable, No change to implied PMA memory type
01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory
10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory
11 - Rsvd Reserved for future standard use
The standard protection_map[] needn't be modified because the "PMA"
type keeps the highest bits zero. The implementation is limited to
arch/riscv/* as it uses an inline function and the alternatives
mechanism to generate the _PAGE_MTMASK/IO/NOCACHE values for
pgprot_noncached (& writecombine) in pgtable.h on both svpbmt and
non-svpbmt-capable chips.
Signed-off-by: Wei Fu <wefu@redhat.com>
Co-developed-by: Liu Shaohua <liush@allwinnertech.com>
Signed-off-by: Liu Shaohua <liush@allwinnertech.com>
Co-developed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Guo Ren <guoren@kernel.org>
[moved to use the alternatives mechanism]
Co-developed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Anup Patel <anup.patel@wdc.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Atish Patra <atish.patra@wdc.com>
Cc: Drew Fustini <drew@beagleboard.org>
Cc: Wei Fu <wefu@redhat.com>
Cc: Wei Wu <lazyparser@gmail.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime@cerno.tech>
Cc: Daniel Lustig <dlustig@nvidia.com>
Cc: Greg Favor <gfavor@ventanamicro.com>
Cc: Andrea Mondelli <andrea.mondelli@huawei.com>
Cc: Jonathan Behrens <behrensj@mit.edu>
Cc: Xinhaoqu (Freddie) <xinhaoqu@huawei.com>
Cc: Bill Huffman <huffman@cadence.com>
Cc: Nick Kossifidis <mick@ics.forth.gr>
Cc: Allen Baum <allen.baum@esperantotech.com>
Cc: Josh Scheid <jscheid@ventanamicro.com>
Cc: Richard Trauben <rtrauben@gmail.com>
---
arch/riscv/include/asm/errata_list.h | 13 ++++-
arch/riscv/include/asm/pgtable-32.h | 9 +++
arch/riscv/include/asm/pgtable-64.h | 47 ++++++++++++++++
arch/riscv/include/asm/pgtable-bits.h | 4 --
arch/riscv/include/asm/pgtable.h | 29 ++++++++--
arch/riscv/kernel/cpufeature.c | 79 +++++++++++++++++++++++++++
6 files changed, 171 insertions(+), 10 deletions(-)
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 6b95bd9aee82..a4a9b0842922 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -14,7 +14,8 @@
#define ERRATA_SIFIVE_NUMBER 2
#endif
-#define CPUFEATURE_NUMBER 0
+#define CPUFEATURE_SVPBMT 0
+#define CPUFEATURE_NUMBER 1
#ifdef __ASSEMBLY__
@@ -36,6 +37,16 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \
ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \
: : "r" (addr) : "memory")
+/*
+ * _val is marked as "will be overwritten", so need to set it to 0
+ * in the default case.
+ */
+#define ALT_SVPBMT_SHIFT 61
+#define ALT_SVPBMT(_val, prot) \
+asm(ALTERNATIVE("li %0, 0\t\nnop", "li %0, %1\t\nslli %0,%0,%2", 0, \
+ CPUFEATURE_SVPBMT, CONFIG_64BIT) \
+ : "=r"(_val) : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), "I"(ALT_SVPBMT_SHIFT))
+
#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
index e266a4fe7f43..59ba1fbaf784 100644
--- a/arch/riscv/include/asm/pgtable-32.h
+++ b/arch/riscv/include/asm/pgtable-32.h
@@ -24,4 +24,13 @@
*/
#define _PAGE_PFN_MASK GENMASK(31, 10)
+#define _PAGE_NOCACHE 0
+#define _PAGE_IO 0
+#define _PAGE_MTMASK 0
+
+/* Set of bits to preserve across pte_modify() */
+#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
+ _PAGE_WRITE | _PAGE_EXEC | \
+ _PAGE_USER | _PAGE_GLOBAL))
+
#endif /* _ASM_RISCV_PGTABLE_32_H */
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index 706f0897437d..58b34ef74acb 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -8,6 +8,7 @@
#include <linux/bits.h>
#include <linux/const.h>
+#include <asm/errata_list.h>
#define PGDIR_SHIFT 30
/* Size of region mapped by a page global directory */
@@ -36,6 +37,52 @@ typedef struct {
*/
#define _PAGE_PFN_MASK GENMASK(53, 10)
+/*
+ * [62:61] Svpbmt Memory Type definitions:
+ *
+ * 00 - PMA Normal Cacheable, No change to implied PMA memory type
+ * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory
+ * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory
+ * 11 - Rsvd Reserved for future standard use
+ */
+#define _PAGE_NOCACHE_SVPBMT (1UL << 61)
+#define _PAGE_IO_SVPBMT (1UL << 62)
+#define _PAGE_MTMASK_SVPBMT (_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT)
+
+static inline u64 riscv_page_mtmask(void)
+{
+ u64 val;
+
+ ALT_SVPBMT(val, _PAGE_MTMASK);
+ return val;
+}
+
+static inline u64 riscv_page_nocache(void)
+{
+ u64 val;
+
+ ALT_SVPBMT(val, _PAGE_NOCACHE);
+ return val;
+}
+
+static inline u64 riscv_page_io(void)
+{
+ u64 val;
+
+ ALT_SVPBMT(val, _PAGE_IO);
+ return val;
+}
+
+#define _PAGE_NOCACHE riscv_page_nocache()
+#define _PAGE_IO riscv_page_io()
+#define _PAGE_MTMASK riscv_page_mtmask()
+
+/* Set of bits to preserve across pte_modify() */
+#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
+ _PAGE_WRITE | _PAGE_EXEC | \
+ _PAGE_USER | _PAGE_GLOBAL | \
+ _PAGE_MTMASK))
+
static inline int pud_present(pud_t pud)
{
return (pud_val(pud) & _PAGE_PRESENT);
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index 4831122d559d..ee908a142f3c 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -29,10 +29,6 @@
#define _PAGE_PFN_SHIFT 10
-/* Set of bits to preserve across pte_modify() */
-#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
- _PAGE_WRITE | _PAGE_EXEC | \
- _PAGE_USER | _PAGE_GLOBAL))
/*
* when all of R/W/X are zero, the PTE is a pointer to the next level
* of the page table; otherwise, it is a leaf PTE.
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 5cf7465a96c5..a189a21a7c8a 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -148,11 +148,8 @@
#define PAGE_TABLE __pgprot(_PAGE_TABLE)
-/*
- * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't
- * change the properties of memory regions.
- */
-#define _PAGE_IOREMAP _PAGE_KERNEL
+#define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO)
+#define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP)
extern pgd_t swapper_pg_dir[];
@@ -492,6 +489,28 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
return ptep_test_and_clear_young(vma, address, ptep);
}
+#define pgprot_noncached pgprot_noncached
+static inline pgprot_t pgprot_noncached(pgprot_t _prot)
+{
+ unsigned long prot = pgprot_val(_prot);
+
+ prot &= ~_PAGE_MTMASK;
+ prot |= _PAGE_IO;
+
+ return __pgprot(prot);
+}
+
+#define pgprot_writecombine pgprot_writecombine
+static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
+{
+ unsigned long prot = pgprot_val(_prot);
+
+ prot &= ~_PAGE_MTMASK;
+ prot |= _PAGE_NOCACHE;
+
+ return __pgprot(prot);
+}
+
/*
* THP functions
*/
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index fef804346d75..d14289fba055 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -7,6 +7,7 @@
*/
#include <linux/bitmap.h>
+#include <linux/libfdt.h>
#include <linux/of.h>
#include <asm/alternative.h>
#include <asm/errata_list.h>
@@ -159,7 +160,85 @@ struct cpufeature_info {
bool (*check_func)(unsigned int stage);
};
+#if defined(CONFIG_MMU) && defined(CONFIG_64BIT)
+static bool cpufeature_svpbmt_check_fdt(void)
+{
+ const void *fdt = dtb_early_va;
+ const char *str;
+ int offset;
+
+ offset = fdt_path_offset(fdt, "/cpus");
+ if (offset < 0)
+ return false;
+
+ for (offset = fdt_next_node(fdt, offset, NULL); offset >= 0;
+ offset = fdt_next_node(fdt, offset, NULL)) {
+ str = fdt_getprop(fdt, offset, "device_type", NULL);
+ if (!str || strcmp(str, "cpu"))
+ break;
+
+ str = fdt_getprop(fdt, offset, "mmu-type", NULL);
+ if (!str)
+ continue;
+
+ if (!strncmp(str + 6, "none", 4))
+ continue;
+
+ str = fdt_getprop(fdt, offset, "mmu", NULL);
+ if (!str)
+ continue;
+
+ if (!strncmp(str + 6, "svpbmt", 6))
+ return true;
+ }
+
+ return false;
+}
+
+static bool cpufeature_svpbmt_check_of(void)
+{
+ struct device_node *node;
+ const char *str;
+
+ for_each_of_cpu_node(node) {
+ if (of_property_read_string(node, "mmu-type", &str))
+ continue;
+
+ if (!strncmp(str + 6, "none", 4))
+ continue;
+
+ if (of_property_read_string(node, "mmu", &str))
+ continue;
+
+ if (!strncmp(str + 6, "svpbmt", 6))
+ return true;
+ }
+
+ return false;
+}
+#endif
+
+static bool cpufeature_svpbmt_check_func(unsigned int stage)
+{
+ bool ret = false;
+
+#if defined(CONFIG_MMU) && defined(CONFIG_64BIT)
+ switch (stage) {
+ case RISCV_ALTERNATIVES_BOOT:
+ return cpufeature_svpbmt_check_fdt();
+ default:
+ return cpufeature_svpbmt_check_of();
+ }
+#endif
+
+ return ret;
+}
+
static const struct cpufeature_info cpufeature_list[CPUFEATURE_NUMBER] = {
+ {
+ .name = "svpbmt",
+ .check_func = cpufeature_svpbmt_check_func
+ },
};
static u32 __init cpufeature_probe(unsigned int stage)
--
2.30.2
^ permalink raw reply related
* [PATCH v5 11/14] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt
From: Heiko Stuebner @ 2022-01-21 16:36 UTC (permalink / raw)
To: palmer, paul.walmsley, aou
Cc: linux-riscv, devicetree, linux-kernel, robh+dt, wefu, liush,
guoren, atishp, anup, drew, hch, arnd, wens, maxime, dlustig,
gfavor, andrea.mondelli, behrensj, xinhaoqu, huffman, mick,
allen.baum, jscheid, rtrauben, samuel, cmuellner, philipp.tomsich,
Heiko Stuebner
In-Reply-To: <20220121163618.351934-1-heiko@sntech.de>
From: Wei Fu <wefu@redhat.com>
Previous patch has added svpbmt in arch/riscv and add "riscv,svpmbt"
in the DT mmu node. Update dt-bindings related property here.
Signed-off-by: Wei Fu <wefu@redhat.com>
Co-developed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Cc: Anup Patel <anup@brainfault.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Rob Herring <robh+dt@kernel.org>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index aa5fb64d57eb..3ad2593f1400 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -63,6 +63,16 @@ properties:
- riscv,sv48
- riscv,none
+ mmu:
+ description:
+ Describes the CPU's MMU Standard Extensions support.
+ These values originate from the RISC-V Privileged
+ Specification document, available from
+ https://riscv.org/specifications/
+ $ref: '/schemas/types.yaml#/definitions/string'
+ enum:
+ - riscv,svpbmt
+
riscv,isa:
description:
Identifies the specific RISC-V instruction set architecture
--
2.30.2
^ permalink raw reply related
* Re: [PATCH v8 1/4] phy: cadence: Add Cadence D-PHY Rx driver
From: kernel test robot @ 2022-01-21 16:38 UTC (permalink / raw)
To: Pratyush Yadav, Vinod Koul
Cc: llvm, kbuild-all, Pratyush Yadav, Laurent Pinchart,
Paul Kocialkowski, Tomi Valkeinen, Vignesh Raghavendra,
Kishon Vijay Abraham I, Rob Herring, Swapnil Jakhade, devicetree
In-Reply-To: <20220121093849.3218092-2-p.yadav@ti.com>
Hi Pratyush,
I love your patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master v5.16 next-20220121]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Pratyush-Yadav/Rx-mode-support-for-Cadence-DPHY/20220121-174104
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-allmodconfig (https://download.01.org/0day-ci/archive/20220122/202201220002.AYMD2qX0-lkp@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 7b3d30728816403d1fd73cc5082e9fb761262bce)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/0day-ci/linux/commit/a27020695f773ffff7f462e53f7ff7ca39109cd0
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Pratyush-Yadav/Rx-mode-support-for-Cadence-DPHY/20220121-174104
git checkout a27020695f773ffff7f462e53f7ff7ca39109cd0
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/meson/ drivers/phy/cadence/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/phy/cadence/cdns-dphy-rx.c:223:46: warning: format specifies type 'int' but the argument has type 'long' [-Wformat]
dev_err(dev, "Failed to create PHY: %d\n", PTR_ERR(dphy->phy));
~~ ^~~~~~~~~~~~~~~~~~
%ld
include/linux/dev_printk.h:144:65: note: expanded from macro 'dev_err'
dev_printk_index_wrap(_dev_err, KERN_ERR, dev, dev_fmt(fmt), ##__VA_ARGS__)
~~~ ^~~~~~~~~~~
include/linux/dev_printk.h:110:23: note: expanded from macro 'dev_printk_index_wrap'
_p_func(dev, fmt, ##__VA_ARGS__); \
~~~ ^~~~~~~~~~~
drivers/phy/cadence/cdns-dphy-rx.c:231:4: warning: format specifies type 'int' but the argument has type 'long' [-Wformat]
PTR_ERR(provider));
^~~~~~~~~~~~~~~~~
include/linux/dev_printk.h:144:65: note: expanded from macro 'dev_err'
dev_printk_index_wrap(_dev_err, KERN_ERR, dev, dev_fmt(fmt), ##__VA_ARGS__)
~~~ ^~~~~~~~~~~
include/linux/dev_printk.h:110:23: note: expanded from macro 'dev_printk_index_wrap'
_p_func(dev, fmt, ##__VA_ARGS__); \
~~~ ^~~~~~~~~~~
2 warnings generated.
vim +223 drivers/phy/cadence/cdns-dphy-rx.c
203
204 static int cdns_dphy_rx_probe(struct platform_device *pdev)
205 {
206 struct device *dev = &pdev->dev;
207 struct phy_provider *provider;
208 struct cdns_dphy_rx *dphy;
209
210 dphy = devm_kzalloc(dev, sizeof(*dphy), GFP_KERNEL);
211 if (!dphy)
212 return -ENOMEM;
213
214 dev_set_drvdata(dev, dphy);
215 dphy->dev = dev;
216
217 dphy->regs = devm_platform_ioremap_resource(pdev, 0);
218 if (IS_ERR(dphy->regs))
219 return PTR_ERR(dphy->regs);
220
221 dphy->phy = devm_phy_create(dev, NULL, &cdns_dphy_rx_ops);
222 if (IS_ERR(dphy->phy)) {
> 223 dev_err(dev, "Failed to create PHY: %d\n", PTR_ERR(dphy->phy));
224 return PTR_ERR(dphy->phy);
225 }
226
227 phy_set_drvdata(dphy->phy, dphy);
228 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
229 if (IS_ERR(provider)) {
230 dev_err(dev, "Failed to register PHY provider: %d\n",
231 PTR_ERR(provider));
232 return PTR_ERR(provider);
233 }
234
235 return 0;
236 }
237
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply
* Re: [PATCH v2 12/12] arm64: dts: renesas: Add support for r9a07g044c1/r9a07g054l1-smarc.dts
From: Lad, Prabhakar @ 2022-01-21 16:38 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Lad Prabhakar, Linux-Renesas, Magnus Damm, Rob Herring, Biju Das,
Linux Kernel Mailing List,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
In-Reply-To: <CAMuHMdUopcuP6XAd_Fw___04=-CyqJPEfNcwkrYgtdQz11yYvg@mail.gmail.com>
Hi Geert,
Ouch please ignore this patch.
Now I know where I missed the v2 combining "[PATCH 01/16] dt-bindings:
arm: renesas: Document Renesas RZ/V2L SoC" and "[PATCH 02/16]
dt-bindings: arm: renesas: Document SMARC EVK". I picked a wrong
commit-id vehicle sending a v2!
This patch is intended for internal build testing atm. We are yet to
test r9a07g044c1/r9a07g054l1 on actual HW.
Sorry about the inconvenience.
Cheers,
Prabhakar
On Fri, Jan 21, 2022 at 2:47 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar, Biju,
>
> On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/Makefile
> > +++ b/arch/arm64/boot/dts/renesas/Makefile
> > @@ -77,4 +77,6 @@ dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
> >
> > dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
> > dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
> > +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c1-smarc.dtb
>
> Please preserve sort order, and add a blank line to separate
> different SoCs.
>
> > dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb
> > +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l1-smarc.dtb
>
> Sort order.
>
> Given this patch adds boards with two different SoCs, and the two
> DTS files are quite dissimilar, I think this patch should be split in
> two parts.
>
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044c1-smarc.dts
> > @@ -0,0 +1,99 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/G2LC SMARC EVK board
> > + *
> > + * Copyright (C) 2021 Renesas Electronics Corp.
> > + */
> > +
> > +/dts-v1/;
> > +#include "r9a07g044c1.dtsi"
> > +#include "rzg2lc-smarc-som.dtsi"
> > +#include "rzg2lc-smarc-pinfunction.dtsi"
> > +#include "rzg2l-smarc.dtsi"
> > +
> > +/ {
> > + model = "Renesas SMARC EVK based on r9a07g044c2";
> > + compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
>
> "renesas,r9a07g044c1"
>
> > +
> > +};
> > +
> > +&canfd {
> > + /delete-property/ pinctrl-0;
> > + status = "disabled";
> > +};
>
> Looks like the corresponding pinctrl-names properties should be
> removed, too. Else "make dtbs_check" complains.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply
* [PATCH v5 14/14] riscv: add memory-type errata for T-Head
From: Heiko Stuebner @ 2022-01-21 16:36 UTC (permalink / raw)
To: palmer, paul.walmsley, aou
Cc: linux-riscv, devicetree, linux-kernel, robh+dt, wefu, liush,
guoren, atishp, anup, drew, hch, arnd, wens, maxime, dlustig,
gfavor, andrea.mondelli, behrensj, xinhaoqu, huffman, mick,
allen.baum, jscheid, rtrauben, samuel, cmuellner, philipp.tomsich,
Heiko Stuebner
In-Reply-To: <20220121163618.351934-1-heiko@sntech.de>
Some current cpus based on T-Head cores implement memory-types
way different than described in the svpbmt spec even going
so far as using PTE bits marked as reserved.
Add the T-Head vendor-id and necessary errata code to
replace the affected instructions.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/riscv/Kconfig.erratas | 19 ++++++
arch/riscv/errata/Makefile | 1 +
arch/riscv/errata/sifive/errata.c | 7 ++-
arch/riscv/errata/thead/Makefile | 1 +
arch/riscv/errata/thead/errata.c | 85 ++++++++++++++++++++++++++
arch/riscv/include/asm/alternative.h | 5 ++
arch/riscv/include/asm/errata_list.h | 47 ++++++++++++--
arch/riscv/include/asm/pgtable-64.h | 18 +++++-
arch/riscv/include/asm/pgtable.h | 18 +++++-
arch/riscv/include/asm/vendorid_list.h | 1 +
arch/riscv/kernel/alternative.c | 14 +++++
arch/riscv/kernel/cpufeature.c | 2 +
arch/riscv/mm/init.c | 2 +
13 files changed, 211 insertions(+), 9 deletions(-)
create mode 100644 arch/riscv/errata/thead/Makefile
create mode 100644 arch/riscv/errata/thead/errata.c
diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas
index d18be8ff0245..380ec039c3dc 100644
--- a/arch/riscv/Kconfig.erratas
+++ b/arch/riscv/Kconfig.erratas
@@ -31,4 +31,23 @@ config ERRATA_SIFIVE_CIP_1200
If you don't know what to do here, say "Y".
+config ERRATA_THEAD
+ bool "T-HEAD errata"
+ help
+ All T-HEAD errata Kconfig depend on this Kconfig. Disabling
+ this Kconfig will disable all T-HEAD errata. Please say "Y"
+ here if your platform uses T-HEAD CPU cores.
+
+ If you don't know what to do here, say "Y".
+
+config ERRATA_THEAD_PBMT
+ bool "Apply T-Head memory type errata"
+ depends on ERRATA_THEAD && 64BIT
+ default y
+ help
+ This will apply the memory type errata to handle the non-standard
+ memory type bits in page-table-entries on T-Head SoCs.
+
+ If you don't know what to do here, say "Y".
+
endmenu
diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile
index 0ca1c5281a2d..a1055965fbee 100644
--- a/arch/riscv/errata/Makefile
+++ b/arch/riscv/errata/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_ERRATA_SIFIVE) += sifive/
+obj-$(CONFIG_ERRATA_THEAD) += thead/
diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c
index 4fe03ac41fd7..f933d6cdf304 100644
--- a/arch/riscv/errata/sifive/errata.c
+++ b/arch/riscv/errata/sifive/errata.c
@@ -84,10 +84,15 @@ void __init sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *
unsigned int stage)
{
struct alt_entry *alt;
- u32 cpu_req_errata = sifive_errata_probe(archid, impid);
+ u32 cpu_req_errata;
u32 cpu_apply_errata = 0;
u32 tmp;
+ if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+ return;
+
+ cpu_req_errata = sifive_errata_probe(archid, impid);
+
for (alt = begin; alt < end; alt++) {
if (alt->vendor_id != SIFIVE_VENDOR_ID)
continue;
diff --git a/arch/riscv/errata/thead/Makefile b/arch/riscv/errata/thead/Makefile
new file mode 100644
index 000000000000..2d644e19caef
--- /dev/null
+++ b/arch/riscv/errata/thead/Makefile
@@ -0,0 +1 @@
+obj-y += errata.o
diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
new file mode 100644
index 000000000000..fd8e0538a3f0
--- /dev/null
+++ b/arch/riscv/errata/thead/errata.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2021 Heiko Stuebner <heiko@sntech.de>
+ */
+
+#include <linux/bug.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/uaccess.h>
+#include <asm/alternative.h>
+#include <asm/cacheflush.h>
+#include <asm/errata_list.h>
+#include <asm/patch.h>
+#include <asm/vendorid_list.h>
+
+struct errata_info {
+ char name[ERRATA_STRING_LENGTH_MAX];
+ bool (*check_func)(unsigned long arch_id, unsigned long impid);
+ unsigned int stage;
+};
+
+static bool errata_mt_check_func(unsigned long arch_id, unsigned long impid)
+{
+ if (arch_id != 0 || impid != 0)
+ return false;
+ return true;
+}
+
+static const struct errata_info errata_list[ERRATA_THEAD_NUMBER] = {
+ {
+ .name = "memory-types",
+ .stage = RISCV_ALTERNATIVES_EARLY_BOOT,
+ .check_func = errata_mt_check_func
+ },
+};
+
+static u32 thead_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid)
+{
+ const struct errata_info *info;
+ u32 cpu_req_errata = 0;
+ int idx;
+
+ for (idx = 0; idx < ERRATA_THEAD_NUMBER; idx++) {
+ info = &errata_list[idx];
+
+ if ((stage == RISCV_ALTERNATIVES_MODULE ||
+ info->stage == stage) && info->check_func(archid, impid))
+ cpu_req_errata |= (1U << idx);
+ }
+
+ return cpu_req_errata;
+}
+
+void __init_or_module thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
+ unsigned long archid, unsigned long impid,
+ unsigned int stage)
+{
+ struct alt_entry *alt;
+ u32 cpu_req_errata = thead_errata_probe(stage, archid, impid);
+ u32 cpu_apply_errata = 0;
+ u32 tmp;
+
+ for (alt = begin; alt < end; alt++) {
+ if (alt->vendor_id != THEAD_VENDOR_ID)
+ continue;
+ if (alt->errata_id >= ERRATA_THEAD_NUMBER)
+ continue;
+
+ tmp = (1U << alt->errata_id);
+ if (cpu_req_errata & tmp) {
+ /* On vm-alternatives, the mmu isn't running yet */
+ if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+ memcpy((void *)__pa_symbol(alt->old_ptr),
+ (void *)__pa_symbol(alt->alt_ptr), alt->alt_len);
+ else
+ patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len);
+
+ cpu_apply_errata |= tmp;
+ }
+ }
+
+ if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+ local_flush_icache_all();
+}
diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
index cf3b22173834..d1154c91ab03 100644
--- a/arch/riscv/include/asm/alternative.h
+++ b/arch/riscv/include/asm/alternative.h
@@ -19,8 +19,10 @@
#define RISCV_ALTERNATIVES_BOOT 0 /* alternatives applied during regular boot */
#define RISCV_ALTERNATIVES_MODULE 1 /* alternatives applied during module-init */
+#define RISCV_ALTERNATIVES_EARLY_BOOT 2 /* alternatives applied before mmu start */
void __init apply_boot_alternatives(void);
+void __init apply_early_boot_alternatives(void);
void apply_module_alternatives(void *start, size_t length);
struct alt_entry {
@@ -39,6 +41,9 @@ struct errata_checkfunc_id {
void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
unsigned long archid, unsigned long impid,
unsigned int stage);
+void thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
+ unsigned long archid, unsigned long impid,
+ unsigned int stage);
void riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry *end,
unsigned int stage);
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index a4a9b0842922..4fac46b82c16 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -14,6 +14,11 @@
#define ERRATA_SIFIVE_NUMBER 2
#endif
+#ifdef CONFIG_ERRATA_THEAD
+#define ERRATA_THEAD_PBMT 0
+#define ERRATA_THEAD_NUMBER 1
+#endif
+
#define CPUFEATURE_SVPBMT 0
#define CPUFEATURE_NUMBER 1
@@ -42,10 +47,44 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \
* in the default case.
*/
#define ALT_SVPBMT_SHIFT 61
-#define ALT_SVPBMT(_val, prot) \
-asm(ALTERNATIVE("li %0, 0\t\nnop", "li %0, %1\t\nslli %0,%0,%2", 0, \
- CPUFEATURE_SVPBMT, CONFIG_64BIT) \
- : "=r"(_val) : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), "I"(ALT_SVPBMT_SHIFT))
+#define ALT_THEAD_PBMT_SHIFT 59
+#define ALT_SVPBMT(_val, prot) \
+asm(ALTERNATIVE_2("li %0, 0\t\nnop", \
+ "li %0, %1\t\nslli %0,%0,%3", 0, CPUFEATURE_SVPBMT, CONFIG_64BIT, \
+ "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, ERRATA_THEAD_PBMT, \
+ CONFIG_ERRATA_THEAD_PBMT) \
+ : "=r"(_val) : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \
+ "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \
+ "I"(ALT_SVPBMT_SHIFT), "I"(ALT_THEAD_PBMT_SHIFT))
+
+#ifdef CONFIG_ERRATA_THEAD_PBMT
+/*
+ * IO/NOCACHE memory types are handled together with svpbmt,
+ * so on T-Head chips, check if no other memory type is set,
+ * and set the non-0 PMA type if applicable.
+ */
+#define ALT_THEAD_PMA(_val) \
+asm volatile(ALTERNATIVE( \
+ "nop\n\t" \
+ "nop\n\t" \
+ "nop\n\t" \
+ "nop\n\t" \
+ "nop\n\t" \
+ "nop\n\t" \
+ "nop", \
+ "li t3, %2\n\t" \
+ "slli t3, t3, %4\n\t" \
+ "and t3, %0, t3\n\t" \
+ "bne t3, zero, 2f\n\t" \
+ "li t3, %3\n\t" \
+ "slli t3, t3, %4\n\t" \
+ "or %0, %0, t3\n\t" \
+ "2:", THEAD_VENDOR_ID, ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \
+ : "+r"(_val) : "0"(_val), "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT), \
+ "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT), "I"(ALT_THEAD_PBMT_SHIFT))
+#else
+#define ALT_THEAD_PMA(_val)
+#endif
#endif /* __ASSEMBLY__ */
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index 58b34ef74acb..e7ce01cdc235 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -49,6 +49,18 @@ typedef struct {
#define _PAGE_IO_SVPBMT (1UL << 62)
#define _PAGE_MTMASK_SVPBMT (_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT)
+/*
+ * [63:59] T-Head Memory Type definitions:
+ *
+ * 00000 - NC Weakly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable
+ * 01110 - PMA Weakly-ordered, Cacheable, Bufferable, Shareable, Non-trustable
+ * 10000 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable
+ */
+#define _PAGE_PMA_THEAD ((1UL << 62) | (1UL << 61) | (1UL << 60))
+#define _PAGE_NOCACHE_THEAD 0UL
+#define _PAGE_IO_THEAD (1UL << 63)
+#define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
+
static inline u64 riscv_page_mtmask(void)
{
u64 val;
@@ -126,7 +138,11 @@ static inline struct page *pud_page(pud_t pud)
static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t prot)
{
- return __pmd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
+ unsigned long prot_val = pgprot_val(prot);
+
+ ALT_THEAD_PMA(prot_val);
+
+ return __pmd((pfn << _PAGE_PFN_SHIFT) | prot_val);
}
static inline unsigned long _pmd_pfn(pmd_t pmd)
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index a189a21a7c8a..c3b9220b2523 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -219,7 +219,11 @@ static inline void pmd_clear(pmd_t *pmdp)
static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot)
{
- return __pgd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
+ unsigned long prot_val = pgprot_val(prot);
+
+ ALT_THEAD_PMA(prot_val);
+
+ return __pgd((pfn << _PAGE_PFN_SHIFT) | prot_val);
}
static inline unsigned long _pgd_pfn(pgd_t pgd)
@@ -258,7 +262,11 @@ static inline unsigned long pte_pfn(pte_t pte)
/* Constructs a page table entry */
static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
{
- return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
+ unsigned long prot_val = pgprot_val(prot);
+
+ ALT_THEAD_PMA(prot_val);
+
+ return __pte((pfn << _PAGE_PFN_SHIFT) | prot_val);
}
#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
@@ -367,7 +375,11 @@ static inline int pmd_protnone(pmd_t pmd)
/* Modify page protection bits */
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
- return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
+ unsigned long newprot_val = pgprot_val(newprot);
+
+ ALT_THEAD_PMA(newprot_val);
+
+ return __pte((pte_val(pte) & _PAGE_CHG_MASK) | newprot_val);
}
#define pgd_ERROR(e) \
diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
index 9d934215b3c8..cb89af3f0704 100644
--- a/arch/riscv/include/asm/vendorid_list.h
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -6,5 +6,6 @@
#define ASM_VENDOR_LIST_H
#define SIFIVE_VENDOR_ID 0x489
+#define THEAD_VENDOR_ID 0x5b7
#endif
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index 54913857b682..e272599f96ef 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -48,6 +48,11 @@ static void __init init_alternative(void)
case SIFIVE_VENDOR_ID:
vendor_patch_func = sifive_errata_patch_func;
break;
+#endif
+#ifdef CONFIG_ERRATA_THEAD
+ case THEAD_VENDOR_ID:
+ vendor_patch_func = thead_errata_patch_func;
+ break;
#endif
default:
vendor_patch_func = NULL;
@@ -85,6 +90,15 @@ void __init apply_boot_alternatives(void)
RISCV_ALTERNATIVES_BOOT);
}
+void __init apply_early_boot_alternatives(void)
+{
+ init_alternative();
+
+ _apply_alternatives((struct alt_entry *)__alt_start,
+ (struct alt_entry *)__alt_end,
+ RISCV_ALTERNATIVES_EARLY_BOOT);
+}
+
#ifdef CONFIG_MODULES
void apply_module_alternatives(void *start, size_t length)
{
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index d14289fba055..4ed18981d94d 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -224,6 +224,8 @@ static bool cpufeature_svpbmt_check_func(unsigned int stage)
#if defined(CONFIG_MMU) && defined(CONFIG_64BIT)
switch (stage) {
+ case RISCV_ALTERNATIVES_EARLY_BOOT:
+ return false;
case RISCV_ALTERNATIVES_BOOT:
return cpufeature_svpbmt_check_fdt();
default:
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 24b2b8044602..063d5f022a05 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -624,6 +624,8 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa)
BUG_ON((kernel_map.virt_addr + kernel_map.size) > ADDRESS_SPACE_END - SZ_4K);
#endif
+ apply_early_boot_alternatives();
+
pt_ops.alloc_pte = alloc_pte_early;
pt_ops.get_pte_virt = get_pte_virt_early;
#ifndef __PAGETABLE_PMD_FOLDED
--
2.30.2
^ permalink raw reply related
* [PATCH v5 13/14] riscv: remove FIXMAP_PAGE_IO and fall back to its default value
From: Heiko Stuebner @ 2022-01-21 16:36 UTC (permalink / raw)
To: palmer, paul.walmsley, aou
Cc: linux-riscv, devicetree, linux-kernel, robh+dt, wefu, liush,
guoren, atishp, anup, drew, hch, arnd, wens, maxime, dlustig,
gfavor, andrea.mondelli, behrensj, xinhaoqu, huffman, mick,
allen.baum, jscheid, rtrauben, samuel, cmuellner, philipp.tomsich,
Heiko Stuebner
In-Reply-To: <20220121163618.351934-1-heiko@sntech.de>
If not defined in the arch, FIXMAP_PAGE_IO defaults to PAGE_KERNEL_IO,
which we defined when adding the svpbmt implementation.
So drop the FIXMAP_PAGE_IO riscv define.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/riscv/include/asm/fixmap.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixmap.h
index 54cbf07fb4e9..899b59bdb9eb 100644
--- a/arch/riscv/include/asm/fixmap.h
+++ b/arch/riscv/include/asm/fixmap.h
@@ -43,8 +43,6 @@ enum fixed_addresses {
__end_of_fixed_addresses
};
-#define FIXMAP_PAGE_IO PAGE_KERNEL
-
#define __early_set_fixmap __set_fixmap
#define __late_set_fixmap __set_fixmap
--
2.30.2
^ permalink raw reply related
* [PATCH v5 09/14] riscv: Fix accessing pfn bits in PTEs for non-32bit variants
From: Heiko Stuebner @ 2022-01-21 16:36 UTC (permalink / raw)
To: palmer, paul.walmsley, aou
Cc: linux-riscv, devicetree, linux-kernel, robh+dt, wefu, liush,
guoren, atishp, anup, drew, hch, arnd, wens, maxime, dlustig,
gfavor, andrea.mondelli, behrensj, xinhaoqu, huffman, mick,
allen.baum, jscheid, rtrauben, samuel, cmuellner, philipp.tomsich,
Heiko Stuebner
In-Reply-To: <20220121163618.351934-1-heiko@sntech.de>
On rv32 the PFN part of PTEs is defined to use bits [xlen-1:10]
while on rv64 it is defined to use bits [53:10], leaving [63:54]
as reserved.
With upcoming optional extensions like svpbmt these previously
reserved bits will get used so simply right-shifting the PTE
to get the PFN won't be enough.
So introduce a _PAGE_PFN_MASK constant to mask the correct bits
for both rv32 and rv64 before shifting.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/riscv/include/asm/pgtable-32.h | 8 ++++++++
arch/riscv/include/asm/pgtable-64.h | 14 +++++++++++---
arch/riscv/include/asm/pgtable-bits.h | 6 ------
arch/riscv/include/asm/pgtable.h | 6 +++---
4 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
index 5b2e79e5bfa5..e266a4fe7f43 100644
--- a/arch/riscv/include/asm/pgtable-32.h
+++ b/arch/riscv/include/asm/pgtable-32.h
@@ -7,6 +7,7 @@
#define _ASM_RISCV_PGTABLE_32_H
#include <asm-generic/pgtable-nopmd.h>
+#include <linux/bits.h>
#include <linux/const.h>
/* Size of region mapped by a page global directory */
@@ -16,4 +17,11 @@
#define MAX_POSSIBLE_PHYSMEM_BITS 34
+/*
+ * rv32 PTE format:
+ * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
+ * PFN reserved for SW D A G U X W R V
+ */
+#define _PAGE_PFN_MASK GENMASK(31, 10)
+
#endif /* _ASM_RISCV_PGTABLE_32_H */
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index 228261aa9628..706f0897437d 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -6,6 +6,7 @@
#ifndef _ASM_RISCV_PGTABLE_64_H
#define _ASM_RISCV_PGTABLE_64_H
+#include <linux/bits.h>
#include <linux/const.h>
#define PGDIR_SHIFT 30
@@ -28,6 +29,13 @@ typedef struct {
#define PTRS_PER_PMD (PAGE_SIZE / sizeof(pmd_t))
+/*
+ * rv64 PTE format:
+ * | 63 | 62 61 | 60 54 | 53 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
+ * N MT RSV PFN reserved for SW D A G U X W R V
+ */
+#define _PAGE_PFN_MASK GENMASK(53, 10)
+
static inline int pud_present(pud_t pud)
{
return (pud_val(pud) & _PAGE_PRESENT);
@@ -61,12 +69,12 @@ static inline void pud_clear(pud_t *pudp)
static inline pmd_t *pud_pgtable(pud_t pud)
{
- return (pmd_t *)pfn_to_virt(pud_val(pud) >> _PAGE_PFN_SHIFT);
+ return (pmd_t *)pfn_to_virt((pud_val(pud) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
}
static inline struct page *pud_page(pud_t pud)
{
- return pfn_to_page(pud_val(pud) >> _PAGE_PFN_SHIFT);
+ return pfn_to_page((pud_val(pud) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
}
static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t prot)
@@ -76,7 +84,7 @@ static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t prot)
static inline unsigned long _pmd_pfn(pmd_t pmd)
{
- return pmd_val(pmd) >> _PAGE_PFN_SHIFT;
+ return (pmd_val(pmd) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT;
}
#define mk_pmd(page, prot) pfn_pmd(page_to_pfn(page), prot)
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index 2ee413912926..4831122d559d 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -6,12 +6,6 @@
#ifndef _ASM_RISCV_PGTABLE_BITS_H
#define _ASM_RISCV_PGTABLE_BITS_H
-/*
- * PTE format:
- * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- * PFN reserved for SW D A G U X W R V
- */
-
#define _PAGE_ACCESSED_OFFSET 6
#define _PAGE_PRESENT (1 << 0)
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index bf204e7c1f74..5cf7465a96c5 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -232,12 +232,12 @@ static inline unsigned long _pgd_pfn(pgd_t pgd)
static inline struct page *pmd_page(pmd_t pmd)
{
- return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT);
+ return pfn_to_page((pmd_val(pmd) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
}
static inline unsigned long pmd_page_vaddr(pmd_t pmd)
{
- return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT);
+ return (unsigned long)pfn_to_virt((pmd_val(pmd) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
}
static inline pte_t pmd_pte(pmd_t pmd)
@@ -253,7 +253,7 @@ static inline pte_t pud_pte(pud_t pud)
/* Yields the page frame number (PFN) of a page table entry */
static inline unsigned long pte_pfn(pte_t pte)
{
- return (pte_val(pte) >> _PAGE_PFN_SHIFT);
+ return ((pte_val(pte) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
}
#define pte_page(x) pfn_to_page(pte_pfn(x))
--
2.30.2
^ permalink raw reply related
* [PATCH v5 07/14] riscv: prevent compressed instructions in alternatives
From: Heiko Stuebner @ 2022-01-21 16:36 UTC (permalink / raw)
To: palmer, paul.walmsley, aou
Cc: linux-riscv, devicetree, linux-kernel, robh+dt, wefu, liush,
guoren, atishp, anup, drew, hch, arnd, wens, maxime, dlustig,
gfavor, andrea.mondelli, behrensj, xinhaoqu, huffman, mick,
allen.baum, jscheid, rtrauben, samuel, cmuellner, philipp.tomsich,
Heiko Stuebner
In-Reply-To: <20220121163618.351934-1-heiko@sntech.de>
Instructions are opportunistically compressed by the RISC-V assembler
when possible, but in alternatives-blocks both the old and new content
need to be the same size, so having the toolchain do somewhat random
optimizations will cause strange side-effects like
"attempt to move .org backwards" compile-time errors.
Already a simple "and" used in alternatives assembly will cause these
mismatched code sizes.
So prevent compressed instructions to be generated in alternatives-
code and use option-push and -pop to limit this to the relevant
code blocks
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/riscv/include/asm/alternative-macros.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
index c0fb11fad631..3a52884bf23d 100644
--- a/arch/riscv/include/asm/alternative-macros.h
+++ b/arch/riscv/include/asm/alternative-macros.h
@@ -19,7 +19,10 @@
.popsection
.subsection 1
888 :
+ .option push
+ .option norvc
\new_c
+ .option pop
889 :
.previous
.org . - (889b - 888b) + (887b - 886b)
@@ -29,7 +32,10 @@
.macro __ALTERNATIVE_CFG old_c, new_c, vendor_id, errata_id, enable
886 :
+ .option push
+ .option norvc
\old_c
+ .option pop
887 :
ALT_NEW_CONTENT \vendor_id, \errata_id, \enable, \new_c
.endm
@@ -40,7 +46,10 @@
.macro __ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
new_c_2, vendor_id_2, errata_id_2, enable_2
886 :
+ .option push
+ .option norvc
\old_c
+ .option pop
887 :
ALT_NEW_CONTENT \vendor_id_1, \errata_id_1, \enable_1, \new_c_1
ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
@@ -70,7 +79,10 @@
".popsection\n" \
".subsection 1\n" \
"888 :\n" \
+ ".option push\n" \
+ ".option norvc\n" \
new_c "\n" \
+ ".option pop\n" \
"889 :\n" \
".previous\n" \
".org . - (887b - 886b) + (889b - 888b)\n" \
@@ -79,7 +91,10 @@
#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \
"886 :\n" \
+ ".option push\n" \
+ ".option norvc\n" \
old_c "\n" \
+ ".option pop\n" \
"887 :\n" \
ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c)
@@ -89,7 +104,10 @@
#define __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
new_c_2, vendor_id_2, errata_id_2, enable_2) \
"886 :\n" \
+ ".option push\n" \
+ ".option norvc\n" \
old_c "\n" \
+ ".option pop\n" \
"887 :\n" \
ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1) \
ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)
--
2.30.2
^ permalink raw reply related
* [PATCH v5 03/14] riscv: allow different stages with alternatives
From: Heiko Stuebner @ 2022-01-21 16:36 UTC (permalink / raw)
To: palmer, paul.walmsley, aou
Cc: linux-riscv, devicetree, linux-kernel, robh+dt, wefu, liush,
guoren, atishp, anup, drew, hch, arnd, wens, maxime, dlustig,
gfavor, andrea.mondelli, behrensj, xinhaoqu, huffman, mick,
allen.baum, jscheid, rtrauben, samuel, cmuellner, philipp.tomsich,
Heiko Stuebner
In-Reply-To: <20220121163618.351934-1-heiko@sntech.de>
Future features may need to be applied at a different
time during boot, so allow defining stages for alternatives
and handling them differently depending on the stage.
Also make the alternatives-location more flexible so that
future stages may provide their own location.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/riscv/errata/sifive/errata.c | 3 ++-
arch/riscv/include/asm/alternative.h | 5 ++++-
arch/riscv/kernel/alternative.c | 25 +++++++++++++++++--------
3 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c
index f5e5ae70e829..4fe03ac41fd7 100644
--- a/arch/riscv/errata/sifive/errata.c
+++ b/arch/riscv/errata/sifive/errata.c
@@ -80,7 +80,8 @@ static void __init warn_miss_errata(u32 miss_errata)
}
void __init sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
- unsigned long archid, unsigned long impid)
+ unsigned long archid, unsigned long impid,
+ unsigned int stage)
{
struct alt_entry *alt;
u32 cpu_req_errata = sifive_errata_probe(archid, impid);
diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
index e625d3cafbed..811bdd8027db 100644
--- a/arch/riscv/include/asm/alternative.h
+++ b/arch/riscv/include/asm/alternative.h
@@ -17,6 +17,8 @@
#include <linux/stddef.h>
#include <asm/hwcap.h>
+#define RISCV_ALTERNATIVES_BOOT 0 /* alternatives applied during regular boot */
+
void __init apply_boot_alternatives(void);
struct alt_entry {
@@ -33,7 +35,8 @@ struct errata_checkfunc_id {
};
void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
- unsigned long archid, unsigned long impid);
+ unsigned long archid, unsigned long impid,
+ unsigned int stage);
#endif
#endif
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index 3b15885db70b..ead00c508266 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -22,7 +22,8 @@ static struct cpu_manufacturer_info_t {
} cpu_mfr_info;
static void (*vendor_patch_func)(struct alt_entry *begin, struct alt_entry *end,
- unsigned long archid, unsigned long impid);
+ unsigned long archid, unsigned long impid,
+ unsigned int stage);
static inline void __init riscv_fill_cpu_mfr_info(void)
{
@@ -57,6 +58,18 @@ static void __init init_alternative(void)
* a feature detect on the boot CPU). No need to worry about other CPUs
* here.
*/
+static void __init _apply_alternatives(struct alt_entry *begin,
+ struct alt_entry *end,
+ unsigned int stage)
+{
+ if (!vendor_patch_func)
+ return;
+
+ vendor_patch_func(begin, end,
+ cpu_mfr_info.arch_id, cpu_mfr_info.imp_id,
+ stage);
+}
+
void __init apply_boot_alternatives(void)
{
/* If called on non-boot cpu things could go wrong */
@@ -64,11 +77,7 @@ void __init apply_boot_alternatives(void)
init_alternative();
- if (!vendor_patch_func)
- return;
-
- vendor_patch_func((struct alt_entry *)__alt_start,
- (struct alt_entry *)__alt_end,
- cpu_mfr_info.arch_id, cpu_mfr_info.imp_id);
+ _apply_alternatives((struct alt_entry *)__alt_start,
+ (struct alt_entry *)__alt_end,
+ RISCV_ALTERNATIVES_BOOT);
}
-
--
2.30.2
^ permalink raw reply related
* [PATCH v5 06/14] riscv: extend concatenated alternatives-lines to the same length
From: Heiko Stuebner @ 2022-01-21 16:36 UTC (permalink / raw)
To: palmer, paul.walmsley, aou
Cc: linux-riscv, devicetree, linux-kernel, robh+dt, wefu, liush,
guoren, atishp, anup, drew, hch, arnd, wens, maxime, dlustig,
gfavor, andrea.mondelli, behrensj, xinhaoqu, huffman, mick,
allen.baum, jscheid, rtrauben, samuel, cmuellner, philipp.tomsich,
Heiko Stuebner
In-Reply-To: <20220121163618.351934-1-heiko@sntech.de>
ALT_NEW_CONTENT already uses same-length assembler lines, so
extend this to the other elements as well.
This makes it more readable when these elements need to be extended
in the future.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/riscv/include/asm/alternative-macros.h | 30 ++++++++++-----------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
index baf649293288..c0fb11fad631 100644
--- a/arch/riscv/include/asm/alternative-macros.h
+++ b/arch/riscv/include/asm/alternative-macros.h
@@ -56,14 +56,14 @@
#include <asm/asm.h>
#include <linux/stringify.h>
-#define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \
- RISCV_PTR " " oldptr "\n" \
- RISCV_PTR " " newptr "\n" \
- REG_ASM " " vendor_id "\n" \
- REG_ASM " " newlen "\n" \
+#define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \
+ RISCV_PTR " " oldptr "\n" \
+ RISCV_PTR " " newptr "\n" \
+ REG_ASM " " vendor_id "\n" \
+ REG_ASM " " newlen "\n" \
".word " errata_id "\n"
-#define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) \
+#define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) \
".if " __stringify(enable) " == 1\n" \
".pushsection .alternative, \"a\"\n" \
ALT_ENTRY("886b", "888f", __stringify(vendor_id), __stringify(errata_id), "889f - 888f") \
@@ -77,21 +77,21 @@
".org . - (889b - 888b) + (887b - 886b)\n" \
".endif\n"
-#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \
- "886 :\n" \
- old_c "\n" \
- "887 :\n" \
+#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \
+ "886 :\n" \
+ old_c "\n" \
+ "887 :\n" \
ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c)
-#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
+#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
__ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, IS_ENABLED(CONFIG_k))
#define __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
new_c_2, vendor_id_2, errata_id_2, enable_2) \
- "886 :\n" \
- old_c "\n" \
- "887 :\n" \
- ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1) \
+ "886 :\n" \
+ old_c "\n" \
+ "887 :\n" \
+ ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1) \
ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)
#define _ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, CONFIG_k_1, \
--
2.30.2
^ permalink raw reply related
* [PATCH v5 00/14] riscv: support for svpbmt and D1 memory types
From: Heiko Stuebner @ 2022-01-21 16:36 UTC (permalink / raw)
To: palmer, paul.walmsley, aou
Cc: linux-riscv, devicetree, linux-kernel, robh+dt, wefu, liush,
guoren, atishp, anup, drew, hch, arnd, wens, maxime, dlustig,
gfavor, andrea.mondelli, behrensj, xinhaoqu, huffman, mick,
allen.baum, jscheid, rtrauben, samuel, cmuellner, philipp.tomsich,
Heiko Stuebner
So this is my try at implementing svpbmt (and the diverging D1 memory
types using the alternatives framework).
This includes a number of changes to the alternatives mechanism itself.
The biggest one being the move to a more central location, as I expect
in the future, nearly every chip needing some sort of patching, be it
either for erratas or for optional features (svpbmt or others).
The dt-binding for svpbmt itself is of course not finished and is still
using the binding introduced in previous versions, as where to put
a svpbmt-property in the devicetree is still under dicussion.
Atish seems to be working on a framework for extensions [0],
The series also introduces support for the memory types of the D1
which are implemented differently to svpbmt. But when patching anyway
it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
location.
The only slightly bigger difference is that the "normal" type is not 0
as with svpbmt, so kernel patches for this PMA type need to be applied
even before the MMU is brought up, so the series introduces a separate
stage for that.
In theory this series is 3 parts:
- sbi cache-flush / null-ptr
- alternatives improvements
- svpbmt+d1
So expecially patches from the first 2 areas could be applied when
deemed ready, I just thought to keep it together to show-case where
the end-goal is and not requiring jumping between different series.
The sbi cache-flush patch is based on Atish's sparse-hartid patch [1],
as it touches a similar area in mm/cacheflush.c
I picked the recipient list from the previous version, hopefully
I didn't forget anybody.
[0] https://lore.kernel.org/r/20211224211632.1698523-1-atishp@rivosinc.com
[1] https://lore.kernel.org/r/20220120090918.2646626-1-atishp@rivosinc.com
Heiko Stuebner (12):
riscv: only use IPIs to handle cache-flushes on remote cpus
riscv: integrate alternatives better into the main architecture
riscv: allow different stages with alternatives
riscv: implement module alternatives
riscv: implement ALTERNATIVE_2 macro
riscv: extend concatenated alternatives-lines to the same length
riscv: prevent compressed instructions in alternatives
riscv: move boot alternatives to a slightly earlier position
riscv: Fix accessing pfn bits in PTEs for non-32bit variants
riscv: add cpufeature handling via alternatives
riscv: remove FIXMAP_PAGE_IO and fall back to its default value
riscv: add memory-type errata for T-Head
Wei Fu (2):
dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt
riscv: add RISC-V Svpbmt extension supports
.../devicetree/bindings/riscv/cpus.yaml | 10 ++
arch/riscv/Kconfig.erratas | 29 ++--
arch/riscv/Kconfig.socs | 1 -
arch/riscv/Makefile | 2 +-
arch/riscv/errata/Makefile | 2 +-
arch/riscv/errata/sifive/errata.c | 10 +-
arch/riscv/errata/thead/Makefile | 1 +
arch/riscv/errata/thead/errata.c | 85 +++++++++++
arch/riscv/include/asm/alternative-macros.h | 114 ++++++++-------
arch/riscv/include/asm/alternative.h | 16 ++-
arch/riscv/include/asm/errata_list.h | 52 +++++++
arch/riscv/include/asm/fixmap.h | 2 -
arch/riscv/include/asm/pgtable-32.h | 17 +++
arch/riscv/include/asm/pgtable-64.h | 79 +++++++++-
arch/riscv/include/asm/pgtable-bits.h | 10 --
arch/riscv/include/asm/pgtable.h | 53 +++++--
arch/riscv/include/asm/vendorid_list.h | 1 +
arch/riscv/kernel/Makefile | 1 +
arch/riscv/{errata => kernel}/alternative.c | 47 +++++-
arch/riscv/kernel/cpufeature.c | 136 +++++++++++++++++-
arch/riscv/kernel/head.S | 2 +
arch/riscv/kernel/module.c | 29 ++++
arch/riscv/kernel/smpboot.c | 4 -
arch/riscv/kernel/traps.c | 2 +-
arch/riscv/mm/cacheflush.c | 8 +-
arch/riscv/mm/init.c | 2 +
26 files changed, 599 insertions(+), 116 deletions(-)
create mode 100644 arch/riscv/errata/thead/Makefile
create mode 100644 arch/riscv/errata/thead/errata.c
rename arch/riscv/{errata => kernel}/alternative.c (60%)
--
2.30.2
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