* [PATCH v3 08/16] clk: samsung: fsd: Add cmu_imem block clock information
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar, linux-fsd,
Arjun K V, Tauseef Nomani
In-Reply-To: <20220121172840.12121-1-alim.akhtar@samsung.com>
Adds cmu_imem clock related code, imem block contains IPs
like WDT, DMA, TMU etc, these clocks are required for such
IP function.
Cc: linux-fsd@tesla.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Arjun K V <arjun.kv@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Tauseef Nomani <tauseef.n@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/clk/samsung/clk-fsd.c | 283 ++++++++++++++++++++++++++++++++++
1 file changed, 283 insertions(+)
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
index 95367d151ab6..d39ec207213e 100644
--- a/drivers/clk/samsung/clk-fsd.c
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -1144,6 +1144,289 @@ static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
.clk_name = "dout_cmu_fsys1_shared0div4",
};
+/* Register Offset definitions for CMU_IMEM (0x10010000) */
+#define PLL_CON0_CLK_IMEM_ACLK 0x100
+#define PLL_CON0_CLK_IMEM_INTMEMCLK 0x120
+#define PLL_CON0_CLK_IMEM_TCUCLK 0x140
+#define DIV_OSCCLK_IMEM_TMUTSCLK 0x1800
+#define GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK 0x2000
+#define GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO 0x2004
+#define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2008
+#define GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK 0x200c
+#define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK 0x2010
+#define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 0x2014
+#define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK 0x2018
+#define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 0x201c
+#define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK 0x2020
+#define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 0x2024
+#define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK 0x2028
+#define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 0x202c
+#define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK 0x2030
+#define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 0x2034
+#define GAT_IMEM_WDT0_IPCLKPORT_CLK 0x2038
+#define GAT_IMEM_WDT1_IPCLKPORT_CLK 0x203c
+#define GAT_IMEM_WDT2_IPCLKPORT_CLK 0x2040
+#define GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM 0x2044
+#define GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM 0x2048
+#define GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM 0x204c
+#define GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS 0x2050
+#define GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS 0x2054
+#define GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS 0x2058
+#define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM 0x205c
+#define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS 0x2060
+#define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM 0x2064
+#define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS 0x2068
+#define GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK 0x206c
+#define GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK 0x2070
+#define GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK 0x2074
+#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK 0x2078
+#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK 0x207c
+#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK 0x2080
+#define GAT_IMEM_DMA0_IPCLKPORT_ACLK 0x2084
+#define GAT_IMEM_DMA1_IPCLKPORT_ACLK 0x2088
+#define GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK 0x208c
+#define GAT_IMEM_GIC_IPCLKPORT_CLK 0x2090
+#define GAT_IMEM_INTMEM_IPCLKPORT_ACLK 0x2094
+#define GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK 0x2098
+#define GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK 0x209c
+#define GAT_IMEM_MCT_IPCLKPORT_PCLK 0x20a0
+#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D 0x20a4
+#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU 0x20a8
+#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P 0x20ac
+#define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK 0x20b0
+#define GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK 0x20b4
+#define GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK 0x20b8
+#define GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK 0x20bc
+#define GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK 0x20c0
+#define GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK 0x20c4
+#define GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK 0x20c8
+#define GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK 0x20cc
+#define GAT_IMEM_TCU_IPCLKPORT_ACLK 0x20d0
+#define GAT_IMEM_WDT0_IPCLKPORT_PCLK 0x20d4
+#define GAT_IMEM_WDT1_IPCLKPORT_PCLK 0x20d8
+#define GAT_IMEM_WDT2_IPCLKPORT_PCLK 0x20dc
+
+static const unsigned long imem_clk_regs[] __initconst = {
+ PLL_CON0_CLK_IMEM_ACLK,
+ PLL_CON0_CLK_IMEM_INTMEMCLK,
+ PLL_CON0_CLK_IMEM_TCUCLK,
+ DIV_OSCCLK_IMEM_TMUTSCLK,
+ GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK,
+ GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO,
+ GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
+ GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK,
+ GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK,
+ GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS,
+ GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK,
+ GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS,
+ GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK,
+ GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS,
+ GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK,
+ GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS,
+ GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK,
+ GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS,
+ GAT_IMEM_WDT0_IPCLKPORT_CLK,
+ GAT_IMEM_WDT1_IPCLKPORT_CLK,
+ GAT_IMEM_WDT2_IPCLKPORT_CLK,
+ GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM,
+ GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM,
+ GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM,
+ GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS,
+ GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS,
+ GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS,
+ GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM,
+ GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS,
+ GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM,
+ GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS,
+ GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK,
+ GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK,
+ GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK,
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK,
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK,
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK,
+ GAT_IMEM_DMA0_IPCLKPORT_ACLK,
+ GAT_IMEM_DMA1_IPCLKPORT_ACLK,
+ GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK,
+ GAT_IMEM_GIC_IPCLKPORT_CLK,
+ GAT_IMEM_INTMEM_IPCLKPORT_ACLK,
+ GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK,
+ GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK,
+ GAT_IMEM_MCT_IPCLKPORT_PCLK,
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D,
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU,
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P,
+ GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK,
+ GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK,
+ GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK,
+ GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK,
+ GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK,
+ GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK,
+ GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK,
+ GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK,
+ GAT_IMEM_TCU_IPCLKPORT_ACLK,
+ GAT_IMEM_WDT0_IPCLKPORT_PCLK,
+ GAT_IMEM_WDT1_IPCLKPORT_PCLK,
+ GAT_IMEM_WDT2_IPCLKPORT_PCLK,
+};
+
+PNAME(mout_imem_clk_imem_tcuclk_p) = { "fin_pll", "dout_cmu_imem_tcuclk" };
+PNAME(mout_imem_clk_imem_aclk_p) = { "fin_pll", "dout_cmu_imem_aclk" };
+PNAME(mout_imem_clk_imem_intmemclk_p) = { "fin_pll", "dout_cmu_imem_dmaclk" };
+
+static const struct samsung_mux_clock imem_mux_clks[] __initconst = {
+ MUX(0, "mout_imem_clk_imem_tcuclk", mout_imem_clk_imem_tcuclk_p,
+ PLL_CON0_CLK_IMEM_TCUCLK, 4, 1),
+ MUX(0, "mout_imem_clk_imem_aclk", mout_imem_clk_imem_aclk_p, PLL_CON0_CLK_IMEM_ACLK, 4, 1),
+ MUX(0, "mout_imem_clk_imem_intmemclk", mout_imem_clk_imem_intmemclk_p,
+ PLL_CON0_CLK_IMEM_INTMEMCLK, 4, 1),
+};
+
+static const struct samsung_div_clock imem_div_clks[] __initconst = {
+ DIV(0, "dout_imem_oscclk_imem_tmutsclk", "fin_pll", DIV_OSCCLK_IMEM_TMUTSCLK, 0, 4),
+};
+
+static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
+ GATE(0, "imem_imem_cmu_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_otp_con_top_ipclkport_i_oscclk", "fin_pll",
+ GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tmu_top_ipclkport_i_clk", "fin_pll",
+ GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tmu_gt_ipclkport_i_clk", "fin_pll",
+ GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tmu_cpu0_ipclkport_i_clk", "fin_pll",
+ GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tmu_gpu_ipclkport_i_clk", "fin_pll",
+ GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_mct_ipclkport_oscclk__alo", "fin_pll",
+ GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_wdt0_ipclkport_clk", "fin_pll",
+ GAT_IMEM_WDT0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_wdt1_ipclkport_clk", "fin_pll",
+ GAT_IMEM_WDT1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_wdt2_ipclkport_clk", "fin_pll",
+ GAT_IMEM_WDT2_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu0_ipclkport_i_clk_ts",
+ "dout_imem_oscclk_imem_tmutsclk",
+ GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu2_ipclkport_i_clk_ts",
+ "dout_imem_oscclk_imem_tmutsclk",
+ GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, "imem_tmu_gpu_ipclkport_i_clk_ts",
+ "dout_imem_oscclk_imem_tmutsclk",
+ GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, "imem_tmu_gt_ipclkport_i_clk_ts",
+ "dout_imem_oscclk_imem_tmutsclk",
+ GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, "imem_tmu_top_ipclkport_i_clk_ts",
+ "dout_imem_oscclk_imem_tmutsclk",
+ GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_adm_axi4st_i0_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_adm_axi4st_i1_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_adm_axi4st_i2_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ads_axi4st_i0_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ads_axi4st_i1_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ads_axi4st_i2_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_async_dma0_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_async_dma0_ipclkport_pclks", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_async_dma1_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_async_dma1_ipclkport_pclks", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_axi2apb_imemp0_ipclkport_aclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_axi2apb_imemp1_ipclkport_aclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_bus_d_imem_ipclkport_mainclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_bus_p_imem_ipclkport_mainclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_bus_p_imem_ipclkport_pericclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_bus_p_imem_ipclkport_tcuclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_DMA0_IPCLKPORT_ACLK, "imem_dma0_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0),
+ GATE(IMEM_DMA1_IPCLKPORT_ACLK, "imem_dma1_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0),
+ GATE(0, "imem_gic500_input_sync_ipclkport_clk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_gic_ipclkport_clk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_GIC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_intmem_ipclkport_aclk", "mout_imem_clk_imem_intmemclk",
+ GAT_IMEM_INTMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_mailbox_scs_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_mailbox_sms_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_MCT_PCLK, "imem_mct_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_MCT_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_d",
+ "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_tcu",
+ "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psoc_imem__clk_imem_p", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_otp_con_top_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_rstnsync_aclk_ipclkport_clk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_rstnsync_oscclk_ipclkport_clk", "fin_pll",
+ GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_rstnsync_intmemclk_ipclkport_clk", "mout_imem_clk_imem_intmemclk",
+ GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_rstnsync_tcuclk_ipclkport_clk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_sfrif_tmu0_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_sfrif_tmu1_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tmu_cpu2_ipclkport_i_clk", "fin_pll",
+ GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_sysreg_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tbu_imem_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tcu_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_TCU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_WDT0_IPCLKPORT_PCLK, "imem_wdt0_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_WDT0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_WDT1_IPCLKPORT_PCLK, "imem_wdt1_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_WDT1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_WDT2_IPCLKPORT_PCLK, "imem_wdt2_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_WDT2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info imem_cmu_info __initconst = {
+ .mux_clks = imem_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(imem_mux_clks),
+ .div_clks = imem_div_clks,
+ .nr_div_clks = ARRAY_SIZE(imem_div_clks),
+ .gate_clks = imem_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(imem_gate_clks),
+ .nr_clk_ids = IMEM_NR_CLK,
+ .clk_regs = imem_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(imem_clk_regs),
+};
+
+static void __init fsd_clk_imem_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &imem_cmu_info);
+}
+
+CLK_OF_DECLARE(fsd_clk_imem, "tesla,fsd-clock-imem", fsd_clk_imem_init);
+
/**
* fsd_cmu_probe - Probe function for FSD platform clocks
* @pdev: Pointer to platform device
--
2.25.1
^ permalink raw reply related
* [PATCH v3 09/16] clk: samsung: fsd: Add cmu_mfc block clock information
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar, linux-fsd,
Smitha T Murthy
In-Reply-To: <20220121172840.12121-1-alim.akhtar@samsung.com>
Adds cmu_mfc clock related code, these clocks are
required for MFC IP.
Cc: linux-fsd@tesla.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/clk/samsung/clk-fsd.c | 121 ++++++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
index d39ec207213e..a9c4424b29ff 100644
--- a/drivers/clk/samsung/clk-fsd.c
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -1427,6 +1427,124 @@ static void __init fsd_clk_imem_init(struct device_node *np)
CLK_OF_DECLARE(fsd_clk_imem, "tesla,fsd-clock-imem", fsd_clk_imem_init);
+/* Register Offset definitions for CMU_MFC (0x12810000) */
+#define PLL_LOCKTIME_PLL_MFC 0x0
+#define PLL_CON0_PLL_MFC 0x100
+#define MUX_MFC_BUSD 0x1000
+#define MUX_MFC_BUSP 0x1008
+#define DIV_MFC_BUSD_DIV4 0x1800
+#define GAT_MFC_CMU_MFC_IPCLKPORT_PCLK 0x2000
+#define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM 0x2004
+#define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS 0x2008
+#define GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK 0x200c
+#define GAT_MFC_MFC_IPCLKPORT_ACLK 0x2010
+#define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D 0x2018
+#define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P 0x201c
+#define GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK 0x2028
+#define GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK 0x202c
+#define GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK 0x2030
+#define GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK 0x2034
+#define GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK 0x2038
+#define GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK 0x203c
+#define GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK 0x2040
+#define GAT_MFC_BUSD_DIV4_GATE 0x2044
+#define GAT_MFC_BUSD_GATE 0x2048
+
+static const unsigned long mfc_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_MFC,
+ PLL_CON0_PLL_MFC,
+ MUX_MFC_BUSD,
+ MUX_MFC_BUSP,
+ DIV_MFC_BUSD_DIV4,
+ GAT_MFC_CMU_MFC_IPCLKPORT_PCLK,
+ GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM,
+ GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS,
+ GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK,
+ GAT_MFC_MFC_IPCLKPORT_ACLK,
+ GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D,
+ GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P,
+ GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK,
+ GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK,
+ GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK,
+ GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK,
+ GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK,
+ GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK,
+ GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK,
+ GAT_MFC_BUSD_DIV4_GATE,
+ GAT_MFC_BUSD_GATE,
+};
+
+static const struct samsung_pll_rate_table pll_mfc_rate_table[] __initconst = {
+ PLL_35XX_RATE(24 * MHZ, 666000000, 111, 4, 0),
+};
+
+static const struct samsung_pll_clock mfc_pll_clks[] __initconst = {
+ PLL(pll_142xx, 0, "fout_pll_mfc", "fin_pll",
+ PLL_LOCKTIME_PLL_MFC, PLL_CON0_PLL_MFC, pll_mfc_rate_table),
+};
+
+PNAME(mout_mfc_pll_p) = { "fin_pll", "fout_pll_mfc" };
+PNAME(mout_mfc_busp_p) = { "fin_pll", "dout_mfc_busd_div4" };
+PNAME(mout_mfc_busd_p) = { "fin_pll", "mfc_busd_gate" };
+
+static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
+ MUX(0, "mout_mfc_pll", mout_mfc_pll_p, PLL_CON0_PLL_MFC, 4, 1),
+ MUX(0, "mout_mfc_busp", mout_mfc_busp_p, MUX_MFC_BUSP, 0, 1),
+ MUX(0, "mout_mfc_busd", mout_mfc_busd_p, MUX_MFC_BUSD, 0, 1),
+};
+
+static const struct samsung_div_clock mfc_div_clks[] __initconst = {
+ DIV(0, "dout_mfc_busd_div4", "mfc_busd_div4_gate", DIV_MFC_BUSD_DIV4, 0, 4),
+};
+
+static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
+ GATE(0, "mfc_cmu_mfc_ipclkport_pclk", "mout_mfc_busp",
+ GAT_MFC_CMU_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_as_p_mfc_ipclkport_pclkm", "mout_mfc_busd",
+ GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_as_p_mfc_ipclkport_pclks", "mout_mfc_busp",
+ GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_axi2apb_mfc_ipclkport_aclk", "mout_mfc_busp",
+ GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(MFC_MFC_IPCLKPORT_ACLK, "mfc_mfc_ipclkport_aclk", "mout_mfc_busd",
+ GAT_MFC_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_d", "mout_mfc_busd",
+ GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_p", "mout_mfc_busp",
+ GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_ppmu_mfcd0_ipclkport_aclk", "mout_mfc_busd",
+ GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_ppmu_mfcd0_ipclkport_pclk", "mout_mfc_busp",
+ GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_ppmu_mfcd1_ipclkport_aclk", "mout_mfc_busd",
+ GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_ppmu_mfcd1_ipclkport_pclk", "mout_mfc_busp",
+ GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_sysreg_mfc_ipclkport_pclk", "mout_mfc_busp",
+ GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_tbu_mfcd0_ipclkport_clk", "mout_mfc_busd",
+ GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_tbu_mfcd1_ipclkport_clk", "mout_mfc_busd",
+ GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_busd_div4_gate", "mout_mfc_pll",
+ GAT_MFC_BUSD_DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_busd_gate", "mout_mfc_pll", GAT_MFC_BUSD_GATE, 21, CLK_IS_CRITICAL, 0),
+};
+
+static const struct samsung_cmu_info mfc_cmu_info __initconst = {
+ .pll_clks = mfc_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(mfc_pll_clks),
+ .mux_clks = mfc_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
+ .div_clks = mfc_div_clks,
+ .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
+ .gate_clks = mfc_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
+ .nr_clk_ids = MFC_NR_CLK,
+ .clk_regs = mfc_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
+};
+
/**
* fsd_cmu_probe - Probe function for FSD platform clocks
* @pdev: Pointer to platform device
@@ -1455,6 +1573,9 @@ static const struct of_device_id fsd_cmu_of_match[] = {
}, {
.compatible = "tesla,fsd-clock-fsys1",
.data = &fsys1_cmu_info,
+ }, {
+ .compatible = "tesla,fsd-clock-mfc",
+ .data = &mfc_cmu_info,
}, {
},
};
--
2.25.1
^ permalink raw reply related
* [PATCH v3 10/16] clk: samsung: fsd: Add cam_csi block clock information
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar, linux-fsd,
Sathyakam M
In-Reply-To: <20220121172840.12121-1-alim.akhtar@samsung.com>
Adds clocks for BLK_CAM_CSI block, this is needed for CSI to work.
Cc: linux-fsd@tesla.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Sathyakam M <sathya@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/clk/samsung/clk-fsd.c | 207 ++++++++++++++++++++++++++++++++++
1 file changed, 207 insertions(+)
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
index a9c4424b29ff..4f88d71cb52e 100644
--- a/drivers/clk/samsung/clk-fsd.c
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -1545,6 +1545,210 @@ static const struct samsung_cmu_info mfc_cmu_info __initconst = {
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
};
+/* Register Offset definitions for CMU_CAM_CSI (0x12610000) */
+#define PLL_LOCKTIME_PLL_CAM_CSI 0x0
+#define PLL_CON0_PLL_CAM_CSI 0x100
+#define DIV_CAM_CSI0_ACLK 0x1800
+#define DIV_CAM_CSI1_ACLK 0x1804
+#define DIV_CAM_CSI2_ACLK 0x1808
+#define DIV_CAM_CSI_BUSD 0x180c
+#define DIV_CAM_CSI_BUSP 0x1810
+#define GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK 0x2000
+#define GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK 0x2004
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0 0x2008
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1 0x200c
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2 0x2010
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC 0x2014
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC 0x2018
+#define GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK 0x201c
+#define GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK 0x2020
+#define GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK 0x2024
+#define GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK 0x2028
+#define GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK 0x202c
+#define GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK 0x2030
+#define GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK 0x2034
+#define GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK 0x2038
+#define GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK 0x203c
+#define GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK 0x2040
+#define GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK 0x2044
+#define GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK 0x2048
+#define GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK 0x204c
+#define GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK 0x2050
+#define GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK 0x2054
+#define GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK 0x2058
+#define GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK 0x205c
+#define GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK 0x2060
+#define GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK 0x2064
+#define GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK 0x2068
+#define GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK 0x206c
+#define GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK 0x2070
+#define GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK 0x2074
+#define GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK 0x2078
+#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D 0x207c
+#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P 0x2080
+#define GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK 0x2084
+#define GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK 0x2088
+
+static const unsigned long cam_csi_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_CAM_CSI,
+ PLL_CON0_PLL_CAM_CSI,
+ DIV_CAM_CSI0_ACLK,
+ DIV_CAM_CSI1_ACLK,
+ DIV_CAM_CSI2_ACLK,
+ DIV_CAM_CSI_BUSD,
+ DIV_CAM_CSI_BUSP,
+ GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK,
+ GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC,
+ GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK,
+ GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D,
+ GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P,
+ GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK,
+ GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK,
+};
+
+static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst = {
+ PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 12, 0),
+};
+
+static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = {
+ PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll",
+ PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table),
+};
+
+PNAME(mout_cam_csi_pll_p) = { "fin_pll", "fout_pll_cam_csi" };
+
+static const struct samsung_mux_clock cam_csi_mux_clks[] __initconst = {
+ MUX(0, "mout_cam_csi_pll", mout_cam_csi_pll_p, PLL_CON0_PLL_CAM_CSI, 4, 1),
+};
+
+static const struct samsung_div_clock cam_csi_div_clks[] __initconst = {
+ DIV(0, "dout_cam_csi0_aclk", "mout_cam_csi_pll", DIV_CAM_CSI0_ACLK, 0, 4),
+ DIV(0, "dout_cam_csi1_aclk", "mout_cam_csi_pll", DIV_CAM_CSI1_ACLK, 0, 4),
+ DIV(0, "dout_cam_csi2_aclk", "mout_cam_csi_pll", DIV_CAM_CSI2_ACLK, 0, 4),
+ DIV(0, "dout_cam_csi_busd", "mout_cam_csi_pll", DIV_CAM_CSI_BUSD, 0, 4),
+ DIV(0, "dout_cam_csi_busp", "mout_cam_csi_pll", DIV_CAM_CSI_BUSP, 0, 4),
+};
+
+static const struct samsung_gate_clock cam_csi_gate_clks[] __initconst = {
+ GATE(0, "cam_csi_cmu_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_axi2apb_cam_csi_ipclkport_aclk", "dout_cam_csi_busp",
+ GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi0", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi1", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi2", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_soc_noc", "dout_cam_csi_busd",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__noc", "dout_cam_csi_busd",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d",
+ "dout_cam_csi_busd",
+ GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_p",
+ "dout_cam_csi_busp",
+ GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_sysreg_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
+ GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_tbu_cam_csi_ipclkport_aclk", "dout_cam_csi_busd",
+ GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info cam_csi_cmu_info __initconst = {
+ .pll_clks = cam_csi_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(cam_csi_pll_clks),
+ .mux_clks = cam_csi_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cam_csi_mux_clks),
+ .div_clks = cam_csi_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cam_csi_div_clks),
+ .gate_clks = cam_csi_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cam_csi_gate_clks),
+ .nr_clk_ids = CAM_CSI_NR_CLK,
+ .clk_regs = cam_csi_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cam_csi_clk_regs),
+};
+
/**
* fsd_cmu_probe - Probe function for FSD platform clocks
* @pdev: Pointer to platform device
@@ -1576,6 +1780,9 @@ static const struct of_device_id fsd_cmu_of_match[] = {
}, {
.compatible = "tesla,fsd-clock-mfc",
.data = &mfc_cmu_info,
+ }, {
+ .compatible = "tesla,fsd-clock-cam_csi",
+ .data = &cam_csi_cmu_info,
}, {
},
};
--
2.25.1
^ permalink raw reply related
* [PATCH v3 11/16] dt-bindings: pinctrl: samsung: Add compatible for Tesla FSD SoC
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar, linux-fsd
In-Reply-To: <20220121172840.12121-1-alim.akhtar@samsung.com>
Add compatible for Tesla Full Self-Driving SoC. The
pinctrl hardware IP is similar to what found on most of the
Exynos series of SoC, so this new compatible is added in
Samsung pinctrl binding.
Cc: linux-fsd@tesla.com
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 9e70edceb21b..81747b88b718 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -25,6 +25,7 @@ Required Properties:
- "samsung,exynos7885-pinctrl": for Exynos7885 compatible pin-controller.
- "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller.
- "samsung,exynosautov9-pinctrl": for ExynosAutov9 compatible pin-controller.
+ - "tesla,fsd-pinctrl": for Tesla FSD SoC compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
--
2.25.1
^ permalink raw reply related
* [PATCH v3 12/16] pinctrl: samsung: add FSD SoC specific data
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar, linux-fsd,
Ajay Kumar
In-Reply-To: <20220121172840.12121-1-alim.akhtar@samsung.com>
Adds Tesla FSD SoC specific data to enable pinctrl.
FSD SoC has similar pinctrl controller as found in the most
Samsung/Exynos SoCs.
Cc: linux-fsd@tesla.com
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
.../pinctrl/samsung/pinctrl-exynos-arm64.c | 71 +++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
3 files changed, 74 insertions(+)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index 2e490e7696f4..6fd06a6ee131 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -727,3 +727,74 @@ const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = {
.ctrl = exynosautov9_pin_ctrl,
.num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl),
};
+
+/*
+ * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three
+ * gpio/pin-mux/pinconfig controllers.
+ */
+
+/* pin banks of FSD pin-controller 0 (FSYS) */
+static const struct samsung_pin_bank_data fsd_pin_banks0[] __initconst = {
+ EXYNOS850_PIN_BANK_EINTG(7, 0x00, "gpf0", 0x00),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpf1", 0x04),
+ EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gpf6", 0x08),
+ EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpf4", 0x0c),
+ EXYNOS850_PIN_BANK_EINTG(6, 0x80, "gpf5", 0x10),
+};
+
+/* pin banks of FSD pin-controller 1 (PERIC) */
+static const struct samsung_pin_bank_data fsd_pin_banks1[] __initconst = {
+ EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpc8", 0x00),
+ EXYNOS850_PIN_BANK_EINTG(7, 0x020, "gpf2", 0x04),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpf3", 0x08),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpd0", 0x0c),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpb0", 0x10),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpb1", 0x14),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x0c0, "gpb4", 0x18),
+ EXYNOS850_PIN_BANK_EINTG(4, 0x0e0, "gpb5", 0x1c),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb6", 0x20),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb7", 0x24),
+ EXYNOS850_PIN_BANK_EINTG(5, 0x140, "gpd1", 0x28),
+ EXYNOS850_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
+ EXYNOS850_PIN_BANK_EINTG(7, 0x180, "gpd3", 0x30),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x1a0, "gpg0", 0x34),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x1c0, "gpg1", 0x38),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpg2", 0x3c),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x220, "gpg4", 0x44),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x240, "gpg5", 0x48),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x260, "gpg6", 0x4c),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x280, "gpg7", 0x50),
+};
+
+/* pin banks of FSD pin-controller 2 (PMU) */
+static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = {
+ EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"),
+};
+
+const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = {
+ {
+ /* pin-controller instance 0 FSYS0 data */
+ .pin_banks = fsd_pin_banks0,
+ .nr_banks = ARRAY_SIZE(fsd_pin_banks0),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend = exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ }, {
+ /* pin-controller instance 1 PERIC data */
+ .pin_banks = fsd_pin_banks1,
+ .nr_banks = ARRAY_SIZE(fsd_pin_banks1),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend = exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ }, {
+ /* pin-controller instance 2 PMU data */
+ .pin_banks = fsd_pin_banks2,
+ .nr_banks = ARRAY_SIZE(fsd_pin_banks2),
+ },
+};
+
+const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
+ .ctrl = fsd_pin_ctrl,
+ .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl),
+};
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 0f6e9305fec5..c542c8ed8fe7 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1271,6 +1271,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
.data = &exynos850_of_data },
{ .compatible = "samsung,exynosautov9-pinctrl",
.data = &exynosautov9_of_data },
+ { .compatible = "tesla,fsd-pinctrl",
+ .data = &fsd_of_data },
#endif
#ifdef CONFIG_PINCTRL_S3C64XX
{ .compatible = "samsung,s3c64xx-pinctrl",
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 1f8d30ba05af..5b32d3f30fcd 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -342,6 +342,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
+extern const struct samsung_pinctrl_of_match_data fsd_of_data;
extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
--
2.25.1
^ permalink raw reply related
* [PATCH v3 14/16] arm64: dts: fsd: Add initial device tree support
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar, linux-fsd,
Arjun K V, Aswani Reddy, Ajay Kumar, Sriranjani P, Chandrasekar R,
Shashank Prashar
In-Reply-To: <20220121172840.12121-1-alim.akhtar@samsung.com>
Add initial device tree support for "Full Self-Driving" (FSD) SoC
This SoC contain three clusters of four cortex-a72 CPUs and various
peripheral IPs.
Cc: linux-fsd@tesla.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Arjun K V <arjun.kv@samsung.com>
Signed-off-by: Aswani Reddy <aswani.reddy@samsung.com>
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Sriranjani P <sriranjani.p@samsung.com>
Signed-off-by: Chandrasekar R <rcsekar@samsung.com>
Signed-off-by: Shashank Prashar <s.prashar@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
MAINTAINERS | 8 +
arch/arm64/Kconfig.platforms | 6 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/tesla/Makefile | 3 +
arch/arm64/boot/dts/tesla/fsd-evb.dts | 39 ++
arch/arm64/boot/dts/tesla/fsd.dtsi | 651 ++++++++++++++++++++++++++
6 files changed, 708 insertions(+)
create mode 100644 arch/arm64/boot/dts/tesla/Makefile
create mode 100644 arch/arm64/boot/dts/tesla/fsd-evb.dts
create mode 100644 arch/arm64/boot/dts/tesla/fsd.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index 27730a5a6345..ed1c10c26e5b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2754,6 +2754,14 @@ S: Maintained
F: Documentation/devicetree/bindings/media/tegra-cec.txt
F: drivers/media/cec/platform/tegra/
+ARM/TESLA FSD SoC SUPPORT
+M: Alim Akhtar <alim.akhtar@samsung.com>
+M: linux-fsd@tesla.com
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L: linux-samsung-soc@vger.kernel.org
+S: Maintained
+F: arch/arm64/boot/dts/tesla*
+
ARM/TETON BGA MACHINE SUPPORT
M: "Mark F. Brown" <mark.brown314@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 7d5d58800170..739254493d6a 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -268,6 +268,12 @@ config ARCH_TEGRA
help
This enables support for the NVIDIA Tegra SoC family.
+config ARCH_TESLA_FSD
+ bool "ARMv8 based Tesla platform"
+ depends on ARCH_EXYNOS
+ help
+ Support for ARMv8 based Tesla platforms.
+
config ARCH_SPRD
bool "Spreadtrum SoC platform"
help
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 639e01a4d855..1ba04e31a438 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -27,6 +27,7 @@ subdir-y += rockchip
subdir-y += socionext
subdir-y += sprd
subdir-y += synaptics
+subdir-y += tesla
subdir-y += ti
subdir-y += toshiba
subdir-y += xilinx
diff --git a/arch/arm64/boot/dts/tesla/Makefile b/arch/arm64/boot/dts/tesla/Makefile
new file mode 100644
index 000000000000..a1ee50e2fd06
--- /dev/null
+++ b/arch/arm64/boot/dts/tesla/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_TESLA_FSD) += \
+ fsd-evb.dtb
diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
new file mode 100644
index 000000000000..5af560c1b5e6
--- /dev/null
+++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Tesla FSD board device tree source
+ *
+ * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
+ * https://www.samsung.com
+ * Copyright (c) 2017-2021 Tesla, Inc.
+ * https://www.tesla.com
+ */
+
+/dts-v1/;
+#include "fsd.dtsi"
+
+/ {
+ model = "Tesla Full Self-Driving (FSD) Evaluation board";
+ compatible = "tesla,fsd-evb", "tesla,fsd";
+
+ aliases {
+ serial0 = &serial_0;
+ serial1 = &serial_1;
+ };
+
+ chosen {
+ stdout-path = &serial_0;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x2 0x00000000>;
+ };
+};
+
+&fin_pll {
+ clock-frequency = <24000000>;
+};
+
+&serial_0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
new file mode 100644
index 000000000000..9a2b88f58c13
--- /dev/null
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -0,0 +1,651 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Tesla Full Self-Driving SoC device tree source
+ *
+ * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
+ * https://www.samsung.com
+ * Copyright (c) 2017-2022 Tesla, Inc.
+ * https://www.tesla.com
+ */
+
+#include <dt-bindings/clock/fsd-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "tesla,fsd";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c0 = &hsi2c_0;
+ i2c1 = &hsi2c_1;
+ i2c2 = &hsi2c_2;
+ i2c3 = &hsi2c_3;
+ i2c4 = &hsi2c_4;
+ i2c5 = &hsi2c_5;
+ i2c6 = &hsi2c_6;
+ i2c7 = &hsi2c_7;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpucl0_0>;
+ };
+ core1 {
+ cpu = <&cpucl0_1>;
+ };
+ core2 {
+ cpu = <&cpucl0_2>;
+ };
+ core3 {
+ cpu = <&cpucl0_3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpucl1_0>;
+ };
+ core1 {
+ cpu = <&cpucl1_1>;
+ };
+ core2 {
+ cpu = <&cpucl1_2>;
+ };
+ core3 {
+ cpu = <&cpucl1_3>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&cpucl2_0>;
+ };
+ core1 {
+ cpu = <&cpucl2_1>;
+ };
+ core2 {
+ cpu = <&cpucl2_2>;
+ };
+ core3 {
+ cpu = <&cpucl2_3>;
+ };
+ };
+ };
+
+ /* Cluster 0 */
+ cpucl0_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x000>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ cpucl0_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x001>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ cpucl0_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x002>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ cpucl0_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x003>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ /* Cluster 1 */
+ cpucl1_0: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ cpucl1_1: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ cpucl1_2: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ cpucl1_3: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ /* Cluster 2 */
+ cpucl2_0: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ cpucl2_1: cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x201>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ cpucl2_2: cpu@202 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x202>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ cpucl2_3: cpu@203 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x203>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ idle-states {
+ entry-method = "arm,psci";
+
+ CPU_SLEEP: cpu-sleep {
+ idle-state-name = "c2";
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <30>;
+ exit-latency-us = <75>;
+ min-residency-us = <300>;
+ };
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>,
+ <&cpucl0_3>, <&cpucl1_0>, <&cpucl1_1>,
+ <&cpucl1_2>, <&cpucl1_3>, <&cpucl2_0>,
+ <&cpucl2_1>, <&cpucl2_2>, <&cpucl2_3>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ fin_pll: clock {
+ compatible = "fixed-clock";
+ clock-output-names = "fin_pll";
+ #clock-cells = <0>;
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+
+ gic: interrupt-controller@10400000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */
+ <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */
+ };
+
+ smmu_imem: iommu@10200000 {
+ compatible = "arm,mmu-500";
+ reg = <0x0 0x10200000 0x0 0x10000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <7>;
+ interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
+ <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
+ <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
+ <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
+ /* Performance counter interrupts */
+ <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_0 */
+ <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_1 */
+ <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, /* for IMEM_0 */
+ /* Per context non-secure context interrupts, 0-3 interrupts */
+ <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
+ <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */
+ <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */
+ <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_3 */
+ };
+
+ smmu_isp: iommu@12100000 {
+ compatible = "arm,mmu-500";
+ reg = <0x0 0x12100000 0x0 0x10000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <11>;
+ interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
+ <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
+ /* Performance counter interrupts */
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_CSI */
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_0 */
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_1 */
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_0 */
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_1 */
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_0 */
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_1 */
+ /* Per context non-secure context interrupts, 0-7 interrupts */
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_3 */
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_4 */
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_5 */
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_6 */
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_7 */
+ };
+
+ smmu_peric: iommu@14900000 {
+ compatible = "arm,mmu-500";
+ reg = <0x0 0x14900000 0x0 0x10000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <5>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
+ <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
+ <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
+ /* Performance counter interrupts */
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, /* for PERIC */
+ /* Per context non-secure context interrupts, 0-1 interrupts */
+ <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
+ <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */
+ };
+
+ smmu_fsys0: iommu@15450000 {
+ compatible = "arm,mmu-500";
+ reg = <0x0 0x15450000 0x0 0x10000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <5>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
+ /* Performance counter interrupts */
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS0 */
+ /* Per context non-secure context interrupts, 0-1 interrupts */
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */
+ };
+
+ clock_imem: clock-controller@10010000 {
+ compatible = "tesla,fsd-clock-imem";
+ reg = <0x0 0x10010000 0x0 0x3000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_cmu DOUT_CMU_IMEM_TCUCLK>,
+ <&clock_cmu DOUT_CMU_IMEM_ACLK>,
+ <&clock_cmu DOUT_CMU_IMEM_DMACLK>;
+ clock-names = "fin_pll",
+ "dout_cmu_imem_tcuclk",
+ "dout_cmu_imem_aclk",
+ "dout_cmu_imem_dmaclk";
+ };
+
+ clock_cmu: clock-controller@11c10000 {
+ compatible = "tesla,fsd-clock-cmu";
+ reg = <0x0 0x11c10000 0x0 0x3000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>;
+ clock-names = "fin_pll";
+ };
+
+ clock_csi: clock-controller@12610000 {
+ compatible = "tesla,fsd-clock-cam_csi";
+ reg = <0x0 0x12610000 0x0 0x3000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>;
+ clock-names = "fin_pll";
+ };
+
+ clock_mfc: clock-controller@12810000 {
+ compatible = "tesla,fsd-clock-mfc";
+ reg = <0x0 0x12810000 0x0 0x3000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>;
+ clock-names = "fin_pll";
+ };
+
+ clock_peric: clock-controller@14010000 {
+ compatible = "tesla,fsd-clock-peric";
+ reg = <0x0 0x14010000 0x0 0x3000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>,
+ <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>,
+ <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>,
+ <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>,
+ <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>;
+ clock-names = "fin_pll",
+ "dout_cmu_pll_shared0_div4",
+ "dout_cmu_peric_shared1div36",
+ "dout_cmu_peric_shared0div3_tbuclk",
+ "dout_cmu_peric_shared0div20",
+ "dout_cmu_peric_shared1div4_dmaclk";
+ };
+
+ clock_fsys0: clock-controller@15010000 {
+ compatible = "tesla,fsd-clock-fsys0";
+ reg = <0x0 0x15010000 0x0 0x3000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>,
+ <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>,
+ <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>;
+ clock-names = "fin_pll",
+ "dout_cmu_pll_shared0_div6",
+ "dout_cmu_fsys0_shared1div4",
+ "dout_cmu_fsys0_shared0div4";
+ };
+
+ clock_fsys1: clock-controller@16810000 {
+ compatible = "tesla,fsd-clock-fsys1";
+ reg = <0x0 0x16810000 0x0 0x3000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,
+ <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>;
+ clock-names = "fin_pll",
+ "dout_cmu_fsys1_shared0div8",
+ "dout_cmu_fsys1_shared0div4";
+ };
+
+ mdma0: mdma@10100000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0x10100000 0x0 0x1000>;
+ interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>;
+ clock-names = "apb_pclk";
+ iommus = <&smmu_imem 0x800 0x0>;
+ };
+
+ mdma1: mdma@10110000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0x10110000 0x0 0x1000>;
+ interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>;
+ clock-names = "apb_pclk";
+ iommus = <&smmu_imem 0x801 0x0>;
+ };
+
+ pdma0: pdma@14280000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0x14280000 0x0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>;
+ clock-names = "apb_pclk";
+ iommus = <&smmu_peric 0x2 0x0>;
+ };
+
+ pdma1: pdma@14290000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0x14290000 0x0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>;
+ clock-names = "apb_pclk";
+ iommus = <&smmu_peric 0x1 0x0>;
+ };
+
+ serial_0: serial@14180000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x0 0x14180000 0x0 0x100>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&pdma1 0>, <&pdma1 1>;
+ dma-names = "tx", "rx";
+ clocks = <&clock_peric PERIC_PCLK_UART0>,
+ <&clock_peric PERIC_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+
+ serial_1: serial@14190000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x0 0x14190000 0x0 0x100>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&pdma1 2>, <&pdma1 3>;
+ dma-names = "tx", "rx";
+ clocks = <&clock_peric PERIC_PCLK_UART1>,
+ <&clock_peric PERIC_SCLK_UART1>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+
+ pmu_system_controller: system-controller@11400000 {
+ compatible = "samsung,exynos7-pmu", "syscon";
+ reg = <0x0 0x11400000 0x0 0x5000>;
+ };
+
+ watchdog_0: watchdog@100a0000 {
+ compatible = "samsung,exynos7-wdt";
+ reg = <0x0 0x100a0000 0x0 0x100>;
+ interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ clocks = <&fin_pll>;
+ clock-names = "watchdog";
+ };
+
+ watchdog_1: watchdog@100b0000 {
+ compatible = "samsung,exynos7-wdt";
+ reg = <0x0 0x100b0000 0x0 0x100>;
+ interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ clocks = <&fin_pll>;
+ clock-names = "watchdog";
+ };
+
+ watchdog_2: watchdog@100c0000 {
+ compatible = "samsung,exynos7-wdt";
+ reg = <0x0 0x100c0000 0x0 0x100>;
+ interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ clocks = <&fin_pll>;
+ clock-names = "watchdog";
+ };
+
+ pwm_0: pwm@14100000 {
+ compatible = "samsung,exynos4210-pwm";
+ reg = <0x0 0x14100000 0x0 0x100>;
+ samsung,pwm-outputs = <0>, <1>, <2>, <3>;
+ #pwm-cells = <3>;
+ clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>;
+ clock-names = "timers";
+ status = "disabled";
+ };
+
+ pwm_1: pwm@14110000 {
+ compatible = "samsung,exynos4210-pwm";
+ reg = <0x0 0x14110000 0x0 0x100>;
+ samsung,pwm-outputs = <0>, <1>, <2>, <3>;
+ #pwm-cells = <3>;
+ clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>;
+ clock-names = "timers";
+ status = "disabled";
+ };
+
+ hsi2c_0: hsi2c@14200000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x0 0x14200000 0x0 0x1000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c0_bus>;
+ clocks = <&clock_peric PERIC_PCLK_HSI2C0>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_1: hsi2c@14210000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x0 0x14210000 0x0 0x1000>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c1_bus>;
+ clocks = <&clock_peric PERIC_PCLK_HSI2C1>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_2: hsi2c@14220000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x0 0x14220000 0x0 0x1000>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c2_bus>;
+ clocks = <&clock_peric PERIC_PCLK_HSI2C2>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_3: hsi2c@14230000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x0 0x14230000 0x0 0x1000>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c3_bus>;
+ clocks = <&clock_peric PERIC_PCLK_HSI2C3>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_4: hsi2c@14240000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x0 0x14240000 0x0 0x1000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c4_bus>;
+ clocks = <&clock_peric PERIC_PCLK_HSI2C4>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_5: hsi2c@14250000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x0 0x14250000 0x0 0x1000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c5_bus>;
+ clocks = <&clock_peric PERIC_PCLK_HSI2C5>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_6: hsi2c@14260000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x0 0x14260000 0x0 0x1000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c6_bus>;
+ clocks = <&clock_peric PERIC_PCLK_HSI2C6>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_7: hsi2c@14270000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x0 0x14270000 0x0 0x1000>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c7_bus>;
+ clocks = <&clock_peric PERIC_PCLK_HSI2C7>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related
* [PATCH v3 16/16] arm64: defconfig: Enable Tesla FSD SoC
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar, linux-fsd
In-Reply-To: <20220121172840.12121-1-alim.akhtar@samsung.com>
This patch enables the Tesla FSD SoC in arm64 defconfig.
Cc: linux-fsd@tesla.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index ee4bd7710a0d..7dd0693a233e 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -54,6 +54,7 @@ CONFIG_ARCH_SEATTLE=y
CONFIG_ARCH_INTEL_SOCFPGA=y
CONFIG_ARCH_SYNQUACER=y
CONFIG_ARCH_TEGRA=y
+CONFIG_ARCH_TESLA_FSD=y
CONFIG_ARCH_SPRD=y
CONFIG_ARCH_THUNDER=y
CONFIG_ARCH_THUNDER2=y
--
2.25.1
^ permalink raw reply related
* [PATCH v3 13/16] dt-bindings: arm: add Tesla FSD ARM SoC
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar, linux-fsd
In-Reply-To: <20220121172840.12121-1-alim.akhtar@samsung.com>
Add device tree bindings for the Tesla FSD ARM SoC.
Cc: linux-fsd@tesla.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
.../devicetree/bindings/arm/tesla.yaml | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/tesla.yaml
diff --git a/Documentation/devicetree/bindings/arm/tesla.yaml b/Documentation/devicetree/bindings/arm/tesla.yaml
new file mode 100644
index 000000000000..09856da657dc
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tesla.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/tesla.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tesla Full Self Driving(FSD) platforms device tree bindings
+
+maintainers:
+ - Alim Akhtar <alim.akhtar@samsung.com>
+ - linux-fsd@tesla.com
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+
+ - description: FSD SoC board
+ items:
+ - enum:
+ - tesla,fsd-evb # Tesla FSD Evaluation
+ - const: tesla,fsd
+
+additionalProperties: true
+
+...
--
2.25.1
^ permalink raw reply related
* [PATCH v3 15/16] arm64: dts: fsd: Add initial pinctrl support
From: Alim Akhtar @ 2022-01-21 17:28 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, Alim Akhtar, linux-fsd,
Shashank Prashar, Aswani Reddy
In-Reply-To: <20220121172840.12121-1-alim.akhtar@samsung.com>
Add initial pin configuration nodes for FSD SoC.
Cc: linux-fsd@tesla.com
Signed-off-by: Shashank Prashar <s.prashar@samsung.com>
Signed-off-by: Aswani Reddy <aswani.reddy@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 335 +++++++++++++++++++++
arch/arm64/boot/dts/tesla/fsd.dtsi | 22 ++
2 files changed, 357 insertions(+)
create mode 100644 arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
new file mode 100644
index 000000000000..8f2c61eacf61
--- /dev/null
+++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
@@ -0,0 +1,335 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Tesla Full Self-Driving SoC device tree source
+ *
+ * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
+ * https://www.samsung.com
+ * Copyright (c) 2017-2021 Tesla, Inc.
+ * https://www.tesla.com
+ */
+
+#include <dt-bindings/pinctrl/samsung.h>
+
+&pinctrl_fsys0 {
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf6: gpf6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf4: gpf4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf5: gpf5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_peric {
+ gpc8: gpc8 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf2: gpf2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf3: gpf3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb1: gpb1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb4: gpb4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb5: gpb5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb6: gpb6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb7: gpb7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd3: gpd3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg0: gpg0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg1: gpg1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg2: gpg2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg3: gpg3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg4: gpg4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg5: gpg5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg6: gpg6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg7: gpg7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pwm0_out: pwm0-out-pins {
+ samsung,pins = "gpb6-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+ };
+
+ pwm1_out: pwm1-out-pins {
+ samsung,pins = "gpb6-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+ };
+
+ hs_i2c0_bus: hs-i2c0-bus-pins {
+ samsung,pins = "gpb0-0", "gpb0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ hs_i2c1_bus: hs-i2c1-bus-pins {
+ samsung,pins = "gpb0-2", "gpb0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ hs_i2c2_bus: hs-i2c2-bus-pins {
+ samsung,pins = "gpb0-4", "gpb0-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ hs_i2c3_bus: hs-i2c3-bus-pins {
+ samsung,pins = "gpb0-6", "gpb0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ hs_i2c4_bus: hs-i2c4-bus-pins {
+ samsung,pins = "gpb1-0", "gpb1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ hs_i2c5_bus: hs-i2c5-bus-pins {
+ samsung,pins = "gpb1-2", "gpb1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ hs_i2c6_bus: hs-i2c6-bus-pins {
+ samsung,pins = "gpb1-4", "gpb1-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ hs_i2c7_bus: hs-i2c7-bus-pins {
+ samsung,pins = "gpb1-6", "gpb1-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart0_data: uart0-data-pins {
+ samsung,pins = "gpb7-0", "gpb7-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart1_data: uart1-data-pins {
+ samsung,pins = "gpb7-4", "gpb7-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ spi0_bus: spi0-bus-pins {
+ samsung,pins = "gpb4-0", "gpb4-2", "gpb4-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ spi1_bus: spi1-bus-pins {
+ samsung,pins = "gpb4-4", "gpb4-6", "gpb4-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ spi2_bus: spi2-bus-pins {
+ samsung,pins = "gpb5-0", "gpb5-2", "gpb5-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+};
+
+&pinctrl_pmu {
+ gpq0: gpq0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index 9a2b88f58c13..bab63c9f79dc 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -26,6 +26,9 @@ aliases {
i2c5 = &hsi2c_5;
i2c6 = &hsi2c_6;
i2c7 = &hsi2c_7;
+ pinctrl0 = &pinctrl_fsys0;
+ pinctrl1 = &pinctrl_peric;
+ pinctrl2 = &pinctrl_pmu;
};
cpus {
@@ -647,5 +650,24 @@ hsi2c_7: hsi2c@14270000 {
clock-names = "hsi2c";
status = "disabled";
};
+
+ pinctrl_pmu: pinctrl@114f0000 {
+ compatible = "tesla,fsd-pinctrl";
+ reg = <0x0 0x114f0000 0x0 0x1000>;
+ };
+
+ pinctrl_peric: pinctrl@141f0000 {
+ compatible = "tesla,fsd-pinctrl";
+ reg = <0x0 0x141f0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_fsys0: pinctrl@15020000 {
+ compatible = "tesla,fsd-pinctrl";
+ reg = <0x0 0x15020000 0x0 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
};
+
+#include "fsd-pinctrl.dtsi"
--
2.25.1
^ permalink raw reply related
* [PATCH v3 0/3] Support for Apple SoCs' NCO blocks
From: Martin Povišer @ 2022-01-21 17:55 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt
Cc: marcan, sven, alyssa, linux-clk, devicetree, linux-kernel,
kettenis, Martin Povišer
Hi,
I am sending v3 of common clock driver for NCO blocks on recent Apple SoCs.
Changes since v2:
- move all under applnco_ prefix
- move away from signed types in register value calculations
- other minor things from Stephen's review
Changes since v1:
- drop apple,nchannels property from the binding, rely on size of the register
range instead to gauge the number of channels
- add a lock to guard set_rate from racing with clock disable/enable
- add short "theory of operation" comment
- incorporate minor changes from Rob's, Sven's and Stephen's review (thanks!)
Martin
v1: https://lore.kernel.org/linux-clk/20211214120213.15649-1-povik@protonmail.com/
v2: https://lore.kernel.org/linux-clk/20220118191839.64086-1-povik+lin@protonmail.com/
Martin Povišer (3):
dt-bindings: clock: Add Apple NCO
clk: clk-apple-nco: Add driver for Apple NCO
MAINTAINERS: Add clk-apple-nco under ARM/APPLE MACHINE
.../devicetree/bindings/clock/apple,nco.yaml | 62 ++++
MAINTAINERS | 2 +
drivers/clk/Kconfig | 9 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-apple-nco.c | 333 ++++++++++++++++++
5 files changed, 407 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/apple,nco.yaml
create mode 100644 drivers/clk/clk-apple-nco.c
--
2.33.0
^ permalink raw reply
* [PATCH v3 1/3] dt-bindings: clock: Add Apple NCO
From: Martin Povišer @ 2022-01-21 17:55 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt
Cc: marcan, sven, alyssa, linux-clk, devicetree, linux-kernel,
kettenis, Martin Povišer, Rob Herring
In-Reply-To: <20220121175441.9944-1-povik+lin@protonmail.com>
The NCO block found on Apple SoCs is a programmable clock generator
performing fractional division of a high frequency input clock.
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Martin Povišer <povik+lin@protonmail.com>
---
.../devicetree/bindings/clock/apple,nco.yaml | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/apple,nco.yaml
diff --git a/Documentation/devicetree/bindings/clock/apple,nco.yaml b/Documentation/devicetree/bindings/clock/apple,nco.yaml
new file mode 100644
index 000000000000..23ee3964fbde
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/apple,nco.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/apple,nco.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Apple SoCs' NCO block
+
+maintainers:
+ - Martin Povišer <povik+lin@protonmail.com>
+
+description: |
+ The NCO (Numerically Controlled Oscillator) block found on Apple SoCs
+ such as the t8103 (M1) is a programmable clock generator performing
+ fractional division of a high frequency input clock.
+
+ It carries a number of independent channels and is typically used for
+ generation of audio bitclocks.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - apple,t6000-nco
+ - apple,t8103-nco
+ - const: apple,nco
+
+ clocks:
+ description:
+ Specifies the reference clock from which the output clocks
+ are derived through fractional division.
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - '#clock-cells'
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ nco_clkref: clock-ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <900000000>;
+ clock-output-names = "nco-ref";
+ };
+
+ nco: clock-controller@23b044000 {
+ compatible = "apple,t8103-nco", "apple,nco";
+ reg = <0x3b044000 0x14000>;
+ #clock-cells = <1>;
+ clocks = <&nco_clkref>;
+ };
--
2.33.0
^ permalink raw reply related
* [PATCH v3 2/3] clk: clk-apple-nco: Add driver for Apple NCO
From: Martin Povišer @ 2022-01-21 17:56 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt
Cc: marcan, sven, alyssa, linux-clk, devicetree, linux-kernel,
kettenis, Martin Povišer
In-Reply-To: <20220121175441.9944-1-povik+lin@protonmail.com>
Add a common clock driver for NCO blocks found on Apple SoCs where they
are typically the generators of audio clocks.
Signed-off-by: Martin Povišer <povik+lin@protonmail.com>
---
drivers/clk/Kconfig | 9 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-apple-nco.c | 333 ++++++++++++++++++++++++++++++++++++
3 files changed, 343 insertions(+)
create mode 100644 drivers/clk/clk-apple-nco.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index ad4256d54361..af4d037e18e3 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -59,6 +59,15 @@ config LMK04832
Say yes here to build support for Texas Instruments' LMK04832 Ultra
Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
+config COMMON_CLK_APPLE_NCO
+ bool "Clock driver for Apple SoC NCOs"
+ depends on ARCH_APPLE || COMPILE_TEST
+ default ARCH_APPLE
+ help
+ This driver supports NCO (Numerically Controlled Oscillator) blocks
+ found on Apple SoCs such as t8103 (M1). The blocks are typically
+ generators of audio clocks.
+
config COMMON_CLK_MAX77686
tristate "Clock driver for Maxim 77620/77686/77802 MFD"
depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 16e588630472..e95e702bdaeb 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -17,6 +17,7 @@ endif
# hardware specific clock types
# please keep this section sorted lexicographically by file path name
+obj-$(CONFIG_COMMON_CLK_APPLE_NCO) += clk-apple-nco.o
obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o
obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o
diff --git a/drivers/clk/clk-apple-nco.c b/drivers/clk/clk-apple-nco.c
new file mode 100644
index 000000000000..a7ef1db9c82b
--- /dev/null
+++ b/drivers/clk/clk-apple-nco.c
@@ -0,0 +1,333 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Driver for an SoC block (Numerically Controlled Oscillator)
+ * found on t8103 (M1) and other Apple chips
+ *
+ * Copyright (C) The Asahi Linux Contributors
+ */
+
+#include <linux/bits.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+
+#define NCO_CHANNEL_STRIDE 0x4000
+#define NCO_CHANNEL_REGSIZE 20
+
+#define REG_CTRL 0
+#define CTRL_ENABLE BIT(31)
+#define REG_DIV 4
+#define DIV_FINE GENMASK(1, 0)
+#define DIV_COARSE GENMASK(12, 2)
+#define REG_INC1 8
+#define REG_INC2 12
+#define REG_ACCINIT 16
+
+/*
+ * Theory of operation (postulated)
+ *
+ * The REG_DIV register indirectly expresses a base integer divisor, roughly
+ * corresponding to twice the desired ratio of input to output clock. This
+ * base divisor is adjusted on a cycle-by-cycle basis based on the state of a
+ * 32-bit phase accumulator to achieve a desired precise clock ratio over the
+ * long term.
+ *
+ * Specifically an output clock cycle is produced after (REG_DIV divisor)/2
+ * or (REG_DIV divisor + 1)/2 input cycles, the latter taking effect when top
+ * bit of the 32-bit accumulator is set. The accumulator is incremented each
+ * produced output cycle, by the value from either REG_INC1 or REG_INC2, which
+ * of the two is selected depending again on the accumulator's current top bit.
+ *
+ * Because the NCO hardware implements counting of input clock cycles in part
+ * in a Galois linear-feedback shift register, the higher bits of divisor
+ * are programmed into REG_DIV by picking an appropriate LFSR state. See
+ * applnco_compute_tables/applnco_div_translate for details on this.
+ */
+
+#define LFSR_POLY 0xa01
+#define LFSR_INIT 0x7ff
+#define LFSR_LEN 11
+#define LFSR_PERIOD ((1 << LFSR_LEN) - 1)
+#define LFSR_TBLSIZE (1 << LFSR_LEN)
+
+/* The minimal attainable coarse divisor (first value in table) */
+#define COARSE_DIV_OFFSET 2
+
+struct applnco_tables {
+ u16 fwd[LFSR_TBLSIZE];
+ u16 inv[LFSR_TBLSIZE];
+};
+
+struct applnco_channel {
+ void __iomem *base;
+ struct applnco_tables *tbl;
+ struct clk_hw hw;
+
+ spinlock_t lock;
+};
+
+#define to_applnco_channel(_hw) container_of(_hw, struct applnco_channel, hw)
+
+static void applnco_enable_nolock(struct clk_hw *hw)
+{
+ struct applnco_channel *chan = to_applnco_channel(hw);
+ u32 val;
+
+ val = readl_relaxed(chan->base + REG_CTRL);
+ writel_relaxed(val | CTRL_ENABLE, chan->base + REG_CTRL);
+}
+
+static void applnco_disable_nolock(struct clk_hw *hw)
+{
+ struct applnco_channel *chan = to_applnco_channel(hw);
+ u32 val;
+
+ val = readl_relaxed(chan->base + REG_CTRL);
+ writel_relaxed(val & ~CTRL_ENABLE, chan->base + REG_CTRL);
+}
+
+static int applnco_is_enabled(struct clk_hw *hw)
+{
+ struct applnco_channel *chan = to_applnco_channel(hw);
+
+ return (readl_relaxed(chan->base + REG_CTRL) & CTRL_ENABLE) != 0;
+}
+
+static void applnco_compute_tables(struct applnco_tables *tbl)
+{
+ int i;
+ u32 state = LFSR_INIT;
+
+ /*
+ * Go through the states of a Galois LFSR and build
+ * a coarse divisor translation table.
+ */
+ for (i = LFSR_PERIOD; i > 0; i--) {
+ if (state & 1)
+ state = (state >> 1) ^ (LFSR_POLY >> 1);
+ else
+ state = (state >> 1);
+ tbl->fwd[i] = state;
+ tbl->inv[state] = i;
+ }
+
+ /* Zero value is special-cased */
+ tbl->fwd[0] = 0;
+ tbl->inv[0] = 0;
+}
+
+static bool applnco_div_out_of_range(unsigned int div)
+{
+ unsigned int coarse = div / 4;
+
+ return coarse < COARSE_DIV_OFFSET ||
+ coarse >= COARSE_DIV_OFFSET + LFSR_TBLSIZE;
+}
+
+static u32 applnco_div_translate(struct applnco_tables *tbl, unsigned int div)
+{
+ unsigned int coarse = div / 4;
+
+ if (WARN_ON(applnco_div_out_of_range(div)))
+ return 0;
+
+ return FIELD_PREP(DIV_COARSE, tbl->fwd[coarse - COARSE_DIV_OFFSET]) |
+ FIELD_PREP(DIV_FINE, div % 4);
+}
+
+static unsigned int applnco_div_translate_inv(struct applnco_tables *tbl, u32 regval)
+{
+ unsigned int coarse, fine;
+
+ coarse = tbl->inv[FIELD_GET(DIV_COARSE, regval)] + COARSE_DIV_OFFSET;
+ fine = FIELD_GET(DIV_FINE, regval);
+
+ return coarse * 4 + fine;
+}
+
+static int applnco_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct applnco_channel *chan = to_applnco_channel(hw);
+ unsigned long flags;
+ u32 div, inc1, inc2;
+ bool was_enabled;
+
+ div = 2 * parent_rate / rate;
+ inc1 = 2 * parent_rate - div * rate;
+ inc2 = inc1 - rate;
+
+ if (applnco_div_out_of_range(div))
+ return -EINVAL;
+
+ div = applnco_div_translate(chan->tbl, div);
+
+ spin_lock_irqsave(&chan->lock, flags);
+ was_enabled = applnco_is_enabled(hw);
+ applnco_disable_nolock(hw);
+
+ writel_relaxed(div, chan->base + REG_DIV);
+ writel_relaxed(inc1, chan->base + REG_INC1);
+ writel_relaxed(inc2, chan->base + REG_INC2);
+
+ /* Presumably a neutral initial value for accumulator */
+ writel_relaxed(1 << 31, chan->base + REG_ACCINIT);
+
+ if (was_enabled)
+ applnco_enable_nolock(hw);
+ spin_unlock_irqrestore(&chan->lock, flags);
+
+ return 0;
+}
+
+static unsigned long applnco_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct applnco_channel *chan = to_applnco_channel(hw);
+ u32 div, inc1, inc2, incbase;
+
+ div = applnco_div_translate_inv(chan->tbl,
+ readl_relaxed(chan->base + REG_DIV));
+
+ inc1 = readl_relaxed(chan->base + REG_INC1);
+ inc2 = readl_relaxed(chan->base + REG_INC2);
+
+ /*
+ * We don't support wraparound of accumulator
+ * nor the edge case of both increments being zero
+ */
+ if (inc1 >= (1 << 31) || inc2 < (1 << 31) || (inc1 == 0 && inc2 == 0))
+ return 0;
+
+ /* Scale both sides of division by incbase to maintain precision */
+ incbase = inc1 - inc2;
+
+ return div64_u64(((u64) parent_rate) * 2 * incbase,
+ ((u64) div) * incbase + inc1);
+}
+
+static long applnco_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long lo = *parent_rate / (COARSE_DIV_OFFSET + LFSR_TBLSIZE) + 1;
+ unsigned long hi = *parent_rate / COARSE_DIV_OFFSET;
+
+ return clamp(rate, lo, hi);
+}
+
+static int applnco_enable(struct clk_hw *hw)
+{
+ struct applnco_channel *chan = to_applnco_channel(hw);
+ unsigned long flags;
+
+ spin_lock_irqsave(&chan->lock, flags);
+ applnco_enable_nolock(hw);
+ spin_unlock_irqrestore(&chan->lock, flags);
+
+ return 0;
+}
+
+static void applnco_disable(struct clk_hw *hw)
+{
+ struct applnco_channel *chan = to_applnco_channel(hw);
+ unsigned long flags;
+
+ spin_lock_irqsave(&chan->lock, flags);
+ applnco_disable_nolock(hw);
+ spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+static const struct clk_ops applnco_ops = {
+ .set_rate = applnco_set_rate,
+ .recalc_rate = applnco_recalc_rate,
+ .round_rate = applnco_round_rate,
+ .enable = applnco_enable,
+ .disable = applnco_disable,
+ .is_enabled = applnco_is_enabled,
+};
+
+static int applnco_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct clk_parent_data pdata = { .index = 0 };
+ struct clk_init_data init;
+ struct clk_hw_onecell_data *onecell_data;
+ void __iomem *base;
+ struct resource *res;
+ struct applnco_tables *tbl;
+ unsigned int nchannels;
+ int ret, i;
+
+ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ if (resource_size(res) < NCO_CHANNEL_REGSIZE)
+ return -EINVAL;
+ nchannels = (resource_size(res) - NCO_CHANNEL_REGSIZE)
+ / NCO_CHANNEL_STRIDE + 1;
+
+ onecell_data = devm_kzalloc(&pdev->dev, struct_size(onecell_data, hws,
+ nchannels), GFP_KERNEL);
+ if (!onecell_data)
+ return -ENOMEM;
+ onecell_data->num = nchannels;
+
+ tbl = devm_kzalloc(&pdev->dev, sizeof(*tbl), GFP_KERNEL);
+ if (!tbl)
+ return -ENOMEM;
+ applnco_compute_tables(tbl);
+
+ for (i = 0; i < nchannels; i++) {
+ struct applnco_channel *chan;
+
+ chan = devm_kzalloc(&pdev->dev, sizeof(*chan), GFP_KERNEL);
+ if (!chan)
+ return -ENOMEM;
+ chan->base = base + NCO_CHANNEL_STRIDE * i;
+ chan->tbl = tbl;
+ spin_lock_init(&chan->lock);
+
+ memset(&init, 0, sizeof(init));
+ init.name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+ "%s-%d", np->name, i);
+ init.ops = &applnco_ops;
+ init.parent_data = &pdata;
+ init.num_parents = 1;
+ init.flags = 0;
+
+ chan->hw.init = &init;
+ ret = devm_clk_hw_register(&pdev->dev, &chan->hw);
+ if (ret)
+ return ret;
+
+ onecell_data->hws[i] = &chan->hw;
+ }
+
+ return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
+ onecell_data);
+}
+
+static const struct of_device_id applnco_ids[] = {
+ { .compatible = "apple,nco" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, applnco_ids)
+
+static struct platform_driver applnco_driver = {
+ .driver = {
+ .name = "apple-nco",
+ .of_match_table = applnco_ids,
+ },
+ .probe = applnco_probe,
+};
+module_platform_driver(applnco_driver);
+
+MODULE_AUTHOR("Martin Povišer <povik+lin@protonmail.com>");
+MODULE_DESCRIPTION("Clock driver for NCO blocks on Apple SoCs");
+MODULE_LICENSE("GPL v2");
--
2.33.0
^ permalink raw reply related
* [PATCH v3 3/3] MAINTAINERS: Add clk-apple-nco under ARM/APPLE MACHINE
From: Martin Povišer @ 2022-01-21 17:56 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt
Cc: marcan, sven, alyssa, linux-clk, devicetree, linux-kernel,
kettenis, Martin Povišer
In-Reply-To: <20220121175441.9944-1-povik+lin@protonmail.com>
Acked-by: Sven Peter <sven@svenpeter.dev>
Acked-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Martin Povišer <povik+lin@protonmail.com>
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 086f37a4763f..d6323083b695 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1765,6 +1765,7 @@ C: irc://irc.oftc.net/asahi-dev
T: git https://github.com/AsahiLinux/linux.git
F: Documentation/devicetree/bindings/arm/apple.yaml
F: Documentation/devicetree/bindings/arm/apple/*
+F: Documentation/devicetree/bindings/clock/apple,nco.yaml
F: Documentation/devicetree/bindings/i2c/apple,i2c.yaml
F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
F: Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml
@@ -1776,6 +1777,7 @@ F: Documentation/devicetree/bindings/spi/apple,spi.yaml
F: Documentation/devicetree/bindings/usb/apple,dwc3.yaml
F: Documentation/devicetree/bindings/watchdog/apple,wdt.yaml
F: arch/arm64/boot/dts/apple/
+F: drivers/clk/clk-apple-nco.c
F: drivers/i2c/busses/i2c-pasemi-core.c
F: drivers/i2c/busses/i2c-pasemi-platform.c
F: drivers/irqchip/irq-apple-aic.c
--
2.33.0
^ permalink raw reply related
* Re: [PATCH 4/4] arm64: dts: qcom: sc7280: Add herobrine-r1
From: Konrad Dybcio @ 2022-01-21 18:00 UTC (permalink / raw)
To: Douglas Anderson, Bjorn Andersson
Cc: quic_rjendra, sibis, kgodara1, mka, swboyd, pmaliset, Andy Gross,
Rob Herring, devicetree, linux-arm-msm, linux-kernel
In-Reply-To: <20220113164233.4.I5604b7af908e8bbe709ac037a6a8a6ba8a2bfa94@changeid>
Hi!
Your DTs look good, but incorporate some weird style decisions..
On 14.01.2022 01:43, Douglas Anderson wrote:
> Add the new herobrine-r1. Note that this is pretty much a re-design
> compared to herobrine-r0 so we don't attempt any dtsi to share stuff
> between them.
>
> This patch attempts to define things at 3 levels:
>
> 1. The Qcard level. Herobrine includes a Qcard PCB and the Qcard PCB
> is supposed to be the same (modulo stuffing options) across
> multiple boards, so trying to define what's there hopefully makes
> sense. NOTE that newer "CRD" boards from Qualcomm also use
> Qcard. When support for CRD3 is added hopefully it can use the
> Qcard include (and perhaps we should even evaluate it using
> herobrine.dtsi?)
> 2. The herobrine "baseboard" level. Right now most stuff is here with
> the exception of things that we _know_ will be different per
> board. We know that not all boards will have the same set of eMMC,
> nvme, and SD. We also know that the exact pin names are likely to
> be different.
> 3. The actual "board" level, AKA herobrine-rev1.
>
> NOTES:
> - This boots to command prompt, but no eDP yet since eDP hasn't
> been added to sc7280.dtsi yet.
> - This assumes LTE for now. Once it's clear how WiFi-only SKUs will
> work we expect some small changes.
>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
> ---
>
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> .../qcom/sc7280-herobrine-herobrine-r0.dts | 2 +-
> .../qcom/sc7280-herobrine-herobrine-r1.dts | 314 +++++++
> .../arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 781 ++++++++++++++++++
> arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 557 +++++++++++++
> 5 files changed, 1654 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts
> create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 9db743826391..54998e108092 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -83,6 +83,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r0.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts
> index 67680a13c234..dcd10d0ead1e 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts
> @@ -26,7 +26,7 @@
>
> / {
> model = "Google Herobrine (rev0)";
> - compatible = "google,herobrine",
> + compatible = "google,herobrine-rev0",
> "qcom,sc7280";
Why break the line here?
> };
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts
> new file mode 100644
> index 000000000000..c57bd689df23
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts
> @@ -0,0 +1,314 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Google Herobrine board device tree source
> + *
> + * Copyright 2022 Google LLC.
> + */
> +
> +/dts-v1/;
> +
> +#include "sc7280-herobrine.dtsi"
> +
> +/ {
> + model = "Google Herobrine (rev1+)";
Are you sure there won't be any changes significant enough in the future
that will make rev2 or rev7 or rev8192 incompatible with the rev1+ DT?
> + compatible = "google,herobrine",
> + "qcom,sc7280";
Why break the line here?
> +};
> +
> +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
This is superfluous at best.
> +
> +&ap_spi_fp {
> + status = "okay";
> +};
> +
> +/*
> + * Although the trackpad is really part of the herobrine baseboard, we'll
> + * put the actual definition in the board device tree since different boards
> + * might hook up different trackpads (or no i2c trackpad at all in the case
> + * of tablets / detachables).
> + */
> +ap_tp_i2c: &i2c0 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + trackpad: trackpad@15 {
> + compatible = "elan,ekth3000";
> + reg = <0x15>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&tp_int_odl>;
> +
> + interrupt-parent = <&tlmm>;
> + interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
> +
> + vcc-supply = <&pp3300_z1>;
> +
> + wakeup-source;
> + };
> +};
> +
> +/*
> + * The touchscreen connector might come off the Qcard, at least in the case of
> + * eDP. Like the trackpad, we'll put it in the board device tree file since
> + * different boards have different touchscreens.
> + */
> +ts_i2c: &i2c13 {
Either sort these by their i2c aliases, or by their new ones.. currently it is
not alphabetically sorted at all..
Looks like some nodes below are just thrown at random places too..
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + ap_ts: touchscreen@5c {
> + compatible = "hid-over-i2c";
> + reg = <0x5c>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>;
> +
> + interrupt-parent = <&tlmm>;
> + interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
> +
> + post-power-on-delay-ms = <500>;
> + hid-descr-addr = <0x0000>;
> +
> + vdd-supply = <&ts_avdd>;
> + };
> +};
> +
> +/* For nvme */
> +&pcie1 {
> + status = "okay";
> +};
> +
> +/* For nvme */
I think this is kind of obvious and there is no need for this to be said twice
within 10 lines..
> +&pcie1_phy {
> + status = "okay";
> +};
> +
> +/* For eMMC */
> +&sdhc_1 {
> + status = "okay";
> +};
> +
> +/* For SD Card */
> +&sdhc_2 {
> + status = "okay";
> +};
> +
> +/* PINCTRL - BOARD-SPECIFIC */
This is also kind of obvious, if it wasn't board-specific, it wouldn't be in the
board DT..
> +
> +/*
> + * Methodology for gpio-line-names:
> + * - If a pin goes to herobrine board and is named it gets that name.
> + * - If a pin goes to herobrine board and is not named, it gets no name.
> + * - If a pin is totally internal to Qcard then it gets Qcard name.
> + * - If a pin is not hooked up on Qcard, it gets no name.
> + */
> +
> +&pm8350c_gpios {
> + gpio-line-names = "FLASH_STROBE_1", /* 1 */
> + "AP_SUSPEND",
> + "PM8008_1_RST_N",
> + "",
> + "",
> + "",
> + "PMIC_EDP_BL_EN",
> + "PMIC_EDP_BL_PWM",
> + "";
> +};
> +
> +&tlmm {
> + gpio-line-names = "AP_TP_I2C_SDA", /* 0 */
> + "AP_TP_I2C_SCL",
> + "SSD_RST_L",
> + "PE_WAKE_ODL",
> + "AP_SAR_SDA",
> + "AP_SAR_SCL",
> + "PRB_SC_GPIO_6",
> + "TP_INT_ODL",
> + "HP_I2C_SDA",
> + "HP_I2C_SCL",
> +
> + "GNSS_L1_EN", /* 10 */
> + "GNSS_L5_EN",
> + "SPI_AP_MOSI",
> + "SPI_AP_MISO",
> + "SPI_AP_CLK",
> + "SPI_AP_CS0_L",
> + /*
> + * AP_FLASH_WP is crossystem ABI. Schematics
> + * call it BIOS_FLASH_WP_OD.
> + */
Is there a need to put this comment on 4 lines instead of a single one?
> + "AP_FLASH_WP",
> + "",
> + "AP_EC_INT_L",
> + "",
> +
> + "UF_CAM_RST_L", /* 20 */
> + "WF_CAM_RST_L",
> + "UART_AP_TX_DBG_RX",
> + "UART_DBG_TX_AP_RX",
> + "",
> + "PM8008_IRQ_1",
> + "HOST2WLAN_SOL",
> + "WLAN2HOST_SOL",
> + "MOS_BT_UART_CTS",
> + "MOS_BT_UART_RFR",
> +
> + "MOS_BT_UART_TX", /* 30 */
> + "MOS_BT_UART_RX",
> + "PRB_SC_GPIO_32",
> + "HUB_RST_L",
> + "",
> + "",
> + "AP_SPI_FP_MISO",
> + "AP_SPI_FP_MOSI",
> + "AP_SPI_FP_CLK",
> + "AP_SPI_FP_CS_L",
> +
> + "AP_EC_SPI_MISO", /* 40 */
> + "AP_EC_SPI_MOSI",
> + "AP_EC_SPI_CLK",
> + "AP_EC_SPI_CS_L",
> + "LCM_RST_L",
> + "EARLY_EUD_N",
> + "",
> + "DP_HOT_PLUG_DET",
> + "IO_BRD_MLB_ID0",
> + "IO_BRD_MLB_ID1",
> +
> + "IO_BRD_MLB_ID2", /* 50 */
> + "SSD_EN",
> + "TS_I2C_SDA_CONN",
> + "TS_I2C_CLK_CONN",
> + "TS_RST_CONN",
> + "TS_INT_CONN",
> + "AP_I2C_TPM_SDA",
> + "AP_I2C_TPM_SCL",
> + "PRB_SC_GPIO_58",
> + "PRB_SC_GPIO_59",
> +
> + "EDP_HOT_PLUG_DET_N", /* 60 */
> + "FP_TO_AP_IRQ_L",
> + "",
> + "AMP_EN",
> + "CAM0_MCLK_GPIO_64",
> + "CAM1_MCLK_GPIO_65",
> + "WF_CAM_MCLK",
> + "PRB_SC_GPIO_67",
> + "FPMCU_BOOT0",
> + "UF_CAM_SDA",
> +
> + "UF_CAM_SCL", /* 70 */
> + "",
> + "",
> + "WF_CAM_SDA",
> + "WF_CAM_SCL",
> + "",
> + "",
> + "EN_FP_RAILS",
> + "FP_RST_L",
> + "PCIE1_CLKREQ_ODL",
> +
> + "EN_PP3300_DX_EDP", /* 80 */
> + "SC_GPIO_81",
> + "FORCED_USB_BOOT",
> + "WCD_RESET_N",
> + "MOS_WLAN_EN",
> + "MOS_BT_EN",
> + "MOS_SW_CTRL",
> + "MOS_PCIE0_RST",
> + "MOS_PCIE0_CLKREQ_N",
> + "MOS_PCIE0_WAKE_N",
> +
> + "MOS_LAA_AS_EN", /* 90 */
> + "SD_CD_ODL",
> + "",
> + "",
> + "MOS_BT_WLAN_SLIMBUS_CLK",
> + "MOS_BT_WLAN_SLIMBUS_DAT0",
> + "HP_MCLK",
> + "HP_BCLK",
> + "HP_DOUT",
> + "HP_DIN",
> +
> + "HP_LRCLK", /* 100 */
> + "HP_IRQ",
> + "",
> + "",
> + "GSC_AP_INT_ODL",
> + "EN_PP3300_CODEC",
> + "AMP_BCLK",
> + "AMP_DIN",
> + "AMP_LRCLK",
> + "UIM1_DATA_GPIO_109",
> +
> + "UIM1_CLK_GPIO_110", /* 110 */
> + "UIM1_RESET_GPIO_111",
> + "PRB_SC_GPIO_112",
> + "UIM0_DATA",
> + "UIM0_CLK",
> + "UIM0_RST",
> + "UIM0_PRESENT_ODL",
> + "SDM_RFFE0_CLK",
> + "SDM_RFFE0_DATA",
> + "WF_CAM_EN",
> +
> + "FASTBOOT_SEL_0", /* 120 */
> + "SC_GPIO_121",
> + "FASTBOOT_SEL_1",
> + "SC_GPIO_123",
> + "FASTBOOT_SEL_2",
> + "SM_RFFE4_CLK_GRFC_8",
> + "SM_RFFE4_DATA_GRFC_9",
> + "WLAN_COEX_UART1_RX",
> + "WLAN_COEX_UART1_TX",
> + "PRB_SC_GPIO_129",
> +
> + "LCM_ID0", /* 130 */
> + "LCM_ID1",
> + "",
> + "SDR_QLINK_REQ",
> + "SDR_QLINK_EN",
> + "QLINK0_WMSS_RESET_N",
> + "SMR526_QLINK1_REQ",
> + "SMR526_QLINK1_EN",
> + "SMR526_QLINK1_WMSS_RESET_N",
> + "PRB_SC_GPIO_139",
> +
> + "SAR1_IRQ_ODL", /* 140 */
> + "SAR0_IRQ_ODL",
> + "PRB_SC_GPIO_142",
> + "",
> + "WCD_SWR_TX_CLK",
> + "WCD_SWR_TX_DATA0",
> + "WCD_SWR_TX_DATA1",
> + "WCD_SWR_RX_CLK",
> + "WCD_SWR_RX_DATA0",
> + "WCD_SWR_RX_DATA1",
> +
> + "DMIC01_CLK", /* 150 */
> + "DMIC01_DATA",
> + "DMIC23_CLK",
> + "DMIC23_DATA",
> + "",
> + "",
> + "EC_IN_RW_ODL",
> + "HUB_EN",
> + "WCD_SWR_TX_DATA2",
> + "",
> +
> + "", /* 160 */
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> +
> + "", /* 170 */
> + "MOS_BLE_UART_TX",
> + "MOS_BLE_UART_RX",
> + "",
> + "",
> + "";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
> new file mode 100644
> index 000000000000..157da25cc5a8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
> @@ -0,0 +1,781 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Google Herobrine baseboard device tree source
> + *
> + * The set of things in this file is a bit loosely defined. It's roughly
> + * defined as the set of things that the child boards happen to have in
> + * common. Since all of the child boards started from the same original
> + * design this is hopefully a large set of things but as more derivatives
> + * appear things may "bubble down" out of this file. For things that are
> + * part of the reference design but might not exist on child nodes we will
> + * follow the lead of the SoC dtsi files and leave their status as "disabled".
> + *
> + * Copyright 2022 Google LLC.
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
Factoring gpio.h out into the SoC DT is a good idea.
> +#include <dt-bindings/input/gpio-keys.h>
> +#include <dt-bindings/input/input.h>
> +
> +#include "sc7280-qcard.dtsi"
> +#include "sc7280-chrome-common.dtsi"
> +
> +/ {
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + /*
> + * FIXED REGULATORS
> + *
> + * Sort order:
> + * 1. parents above children.
> + * 2. higher voltage above lower voltage.
> + * 3. alphabetically by node name.
Why not just alphabetically? These regulator-fixed nodes shouldn't
have issues with probe order and their parent-child relations are
specified in their properties.
> + */
> +
> + /* This is the top level supply and variable voltage */
Is there a way to read out the voltage somehow, perhaps as a TODO for the future
if a driver is needed? I think the regulator framework used not to be very happy
about not specifying a (fixed) voltage range on a fixed regulator, but I may be
wrong..
> + ppvar_sys: ppvar-sys-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "ppvar_sys";
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + /* This divides ppvar_sys by 2, so voltage is variable */
> + src_vph_pwr: src-vph-pwr-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "src_vph_pwr";
> +
> + /* EC turns on with switchcap_on; always on for AP */
> + regulator-always-on;
> + regulator-boot-on;
> +
> + vin-supply = <&ppvar_sys>;
> + };
> +
> + pp5000_s5: pp5000-s5-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "pp5000_s5";
> +
> + /* EC turns on with en_pp5000_s5; always on for AP */
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> +
> + vin-supply = <&ppvar_sys>;
> + };
> +
> + pp3300_z1: pp3300-z1-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "pp3300_z1";
> +
> + /* EC turns on with en_pp3300_z1; always on for AP */
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + vin-supply = <&ppvar_sys>;
> + };
> +
> + pp3300_codec: pp3300-codec-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "pp3300_codec";
> +
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + gpio = <&tlmm 105 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + pinctrl-names = "default";
> + pinctrl-0 = <&en_pp3300_codec>;
> +
> + vin-supply = <&pp3300_z1>;
> + };
> +
> + pp3300_left_in_mlb: pp3300-left-in-mlb {
> + compatible = "regulator-fixed";
> + regulator-name = "pp3300_left_in_mlb";
> +
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + pinctrl-names = "default";
> + pinctrl-0 = <&en_pp3300_dx_edp>;
> +
> + vin-supply = <&pp3300_z1>;
> + };
> +
> + pp3300_mcu_fp:
> + pp3300_fp_ls:
> + pp3300_fp_mcu: pp3300-fp-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "pp3300_fp";
> +
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + regulator-boot-on;
> + regulator-always-on;
> +
> + /*
> + * WARNING: it is intentional that GPIO 77 isn't listed here.
> + * The userspace script for updating the fingerprint firmware
> + * needs to control the FP regulators during a FW update,
> + * hence the signal can't be owned by the kernel regulator.
> + */
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&en_fp_rails>;
> +
> + vin-supply = <&pp3300_z1>;
> + };
> +
> + pp3300_hub: pp3300-hub-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "pp3300_hub";
> +
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + regulator-boot-on;
> + regulator-always-on;
> +
> + gpio = <&tlmm 157 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hub_en>;
> +
> + vin-supply = <&pp3300_z1>;
> + };
> +
> + pp3300_tp: pp3300-tp-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "pp3300_tp";
> +
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + /* AP turns on with PP1800_L18B_S0; always on for AP */
> + regulator-always-on;
> + regulator-boot-on;
> +
> + vin-supply = <&pp3300_z1>;
> + };
> +
> + pp3300_ssd: pp3300-ssd {
> + compatible = "regulator-fixed";
> + regulator-name = "pp3300_ssd";
> +
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + pinctrl-names = "default";
> + pinctrl-0 = <&ssd_en>;
> +
> + vin-supply = <&pp3300_z1>;
> + };
> +
> + pp2850_vcm_wf_cam: pp2850-vcm-wf-cam {
> + compatible = "regulator-fixed";
> + regulator-name = "pp2850_vcm_wf_cam";
> +
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <2850000>;
> +
> + gpio = <&tlmm 119 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + pinctrl-names = "default";
> + pinctrl-0 = <&wf_cam_en>;
> +
> + vin-supply = <&pp3300_z1>;
> + };
> +
> + pp2850_wf_cam: pp2850-wf-cam {
> + compatible = "regulator-fixed";
> + regulator-name = "pp2850_wf_cam";
> +
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <2850000>;
> +
> + gpio = <&tlmm 119 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + /*
> + * The pinconf can only be referenced once so we put it on the
> + * first regulator and comment it out here.
> + *
> + * pinctrl-names = "default";
> + * pinctrl-0 = <&wf_cam_en>;
> + */
> +
> + vin-supply = <&pp3300_z1>;
> + };
> +
> + pp1800_fp: pp1800-fp-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "pp1800_fp";
> +
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + regulator-boot-on;
> + regulator-always-on;
> +
> + /*
> + * WARNING: it is intentional that GPIO 77 isn't listed here.
> + * The userspace script for updating the fingerprint firmware
> + * needs to control the FP regulators during a FW update,
> + * hence the signal can't be owned by the kernel regulator.
> + */
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&en_fp_rails>;
> +
> + vin-supply = <&pp1800_l18b_s0>;
> + status = "disabled";
> + };
> +
> + pp1800_wf_cam: pp1800-wf-cam {
> + compatible = "regulator-fixed";
> + regulator-name = "pp1800_wf_cam";
> +
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + gpio = <&tlmm 119 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + /*
> + * The pinconf can only be referenced once so we put it on the
> + * first regulator and comment it out here.
> + *
> + * pinctrl-names = "default";
> + * pinctrl-0 = <&wf_cam_en>;
> + */
> +
> + vin-supply = <&vreg_l19b_s0>;
> + };
> +
> + pp1200_wf_cam: pp1200-wf-cam {
> + compatible = "regulator-fixed";
> + regulator-name = "pp1200_wf_cam";
> +
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> +
> + gpio = <&tlmm 119 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + /*
> + * The pinconf can only be referenced once so we put it on the
> + * first regulator and comment it out here.
> + *
> + * pinctrl-names = "default";
> + * pinctrl-0 = <&wf_cam_en>;
> + */
> +
> + vin-supply = <&pp3300_z1>;
> + };
> +
> + /* BOARD-SPECIFIC TOP LEVEL NODES */
Again, seems superfluous.
> +
> + pwmleds {
> + compatible = "pwm-leds";
> + status = "disabled";
If it's disabled and it's not enabled anywhere else, why is it here?
Is it going to have users in a very near future?
> + keyboard_backlight: keyboard-backlight {
> + status = "disabled";
> + label = "cros_ec::kbd_backlight";
> + pwms = <&cros_ec_pwm 0>;
> + max-brightness = <1023>;
> + };
> + };
> +};
> +
> +/*
> + * BOARD-LOCAL NAMES FOR REGULATORS THAT CONNECT TO QCARD
> + *
> + * Names are only listed here if regulators go somewhere other than a
> + * testpoint.
> + */
> +
> +/* From Qcard to our board; ordered by PMIC-ID / rail number */
> +
> +pp1256_s8b: &vreg_s8b_1p256 {};
> +
> +pp1800_l18b_s0: &vreg_l18b_1p8 {};
> +pp1800_l18b: &vreg_l18b_1p8 {};
> +
> +vreg_l19b_s0: &vreg_l19b_1p8 {};
> +
> +pp1800_alc5682: &vreg_l2c_1p8 {};
> +pp1800_l2c: &vreg_l2c_1p8 {};
> +
> +vreg_l4c: &vreg_l4c_1p8_3p0 {};
> +
> +ppvar_l6c: &vreg_l6c_2p96 {};
> +
> +pp3000_l7c: &vreg_l7c_3p0 {};
> +
> +pp1800_prox: &vreg_l8c_1p8 {};
> +pp1800_l8c: &vreg_l8c_1p8 {};
> +
> +pp2950_l9c: &vreg_l9c_2p96 {};
> +
> +pp1800_lcm: &vreg_l12c_1p8 {};
> +pp1800_mipi: &vreg_l12c_1p8 {};
> +pp1800_l12c: &vreg_l12c_1p8 {};
> +
> +pp3300_lcm: &vreg_l13c_3p0 {};
> +pp3300_mipi: &vreg_l13c_3p0 {};
> +pp3300_l13c: &vreg_l13c_3p0 {};
> +
> +/* From our board to Qcard; ordered same as node definition above */
> +
> +vreg_edp_bl: &ppvar_sys {};
> +
> +ts_avdd: &pp3300_left_in_mlb {};
> +vreg_edp_3p3: &pp3300_left_in_mlb {};
> +
> +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
Again.
> +
> +ap_i2c_tpm: &i2c14 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + tpm@50 {
> + compatible = "google,cr50";
> + reg = <0x50>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&gsc_ap_int_odl>;
> +
> + interrupt-parent = <&tlmm>;
> + interrupts = <104 IRQ_TYPE_EDGE_RISING>;
> + };
> +};
> +
> +/* For nvme; not all herobrine boards have; boards set status = "okay" */
"NVMe drive, enabled on a per-board basis"?
> +&pcie1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>;
> +
> + perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>;
> + vddpe-3v3-supply = <&pp3300_ssd>;
> +};
> +
> +&pmk8350_rtc {
> + status = "disabled";
> +};
> +
> +&qupv3_id_0 {
> + status = "okay";
> +};
> +
> +&qupv3_id_1 {
> + status = "okay";
> +};
> +
> +/* For SD Card; not all herobrine boards have; boards set status = "okay" */
Ditto
> +&sdhc_2 {
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&sdc2_on>;
> + pinctrl-1 = <&sdc2_off>;
> +
> + vmmc-supply = <&pp2950_l9c>;
> + vqmmc-supply = <&ppvar_l6c>;
> +
> + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
> +};
> +
> +/* Not all herobrine boards have fingerprint; boards set status = "okay" */
Ditto
> +ap_spi_fp: &spi9 {
> + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs_gpio_init_high>, <&qup_spi9_cs_gpio>;
> +
> + cs-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
> +
> + cros_ec_fp: ec@0 {
> + compatible = "google,cros-ec-spi";
> + reg = <0>;
> + interrupt-parent = <&tlmm>;
> + interrupts = <61 IRQ_TYPE_LEVEL_LOW>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&fp_to_ap_irq_l>, <&fp_rst_l>, <&fpmcu_boot0>;
> + spi-max-frequency = <3000000>;
> + };
> +};
> +
> +ap_ec_spi: &spi10 {
> + status = "okay";
> + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>;
> +
> + cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
> +
> + cros_ec: ec@0 {
> + compatible = "google,cros-ec-spi";
> + reg = <0>;
> + interrupt-parent = <&tlmm>;
> + interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&ap_ec_int_l>;
> + spi-max-frequency = <3000000>;
> +
> + cros_ec_pwm: ec-pwm {
> + compatible = "google,cros-ec-pwm";
> + #pwm-cells = <1>;
> + };
> +
> + i2c_tunnel: i2c-tunnel {
> + compatible = "google,cros-ec-i2c-tunnel";
> + google,remote-bus = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + typec {
> + compatible = "google,cros-ec-typec";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + usb_c0: connector@0 {
> + compatible = "usb-c-connector";
> + reg = <0>;
> + label = "left";
> + power-role = "dual";
> + data-role = "host";
> + try-power-role = "source";
> + };
> +
> + usb_c1: connector@1 {
> + compatible = "usb-c-connector";
> + reg = <1>;
> + label = "right";
> + power-role = "dual";
> + data-role = "host";
> + try-power-role = "source";
> + };
> + };
> + };
> +};
> +
> +#include <arm/cros-ec-keyboard.dtsi>
> +#include <arm/cros-ec-sbs.dtsi>
> +
> +&keyboard_controller {
> + function-row-physmap = <
> + MATRIX_KEY(0x00, 0x02, 0) /* T1 */
> + MATRIX_KEY(0x03, 0x02, 0) /* T2 */
> + MATRIX_KEY(0x02, 0x02, 0) /* T3 */
> + MATRIX_KEY(0x01, 0x02, 0) /* T4 */
> + MATRIX_KEY(0x03, 0x04, 0) /* T5 */
> + MATRIX_KEY(0x02, 0x04, 0) /* T6 */
> + MATRIX_KEY(0x01, 0x04, 0) /* T7 */
> + MATRIX_KEY(0x02, 0x09, 0) /* T8 */
> + MATRIX_KEY(0x01, 0x09, 0) /* T9 */
> + MATRIX_KEY(0x00, 0x04, 0) /* T10 */
> + >;
> + linux,keymap = <
> + MATRIX_KEY(0x00, 0x02, KEY_BACK)
> + MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
> + MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
> + MATRIX_KEY(0x01, 0x02, KEY_SCALE)
> + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
> + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
> + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
> + MATRIX_KEY(0x02, 0x09, KEY_MUTE)
> + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
> + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
> +
> + CROS_STD_MAIN_KEYMAP
> + >;
> +};
> +
> +&usb_1 {
> + status = "okay";
> +};
> +
> +&usb_1_dwc3 {
> + dr_mode = "host";
> +};
> +
> +&usb_1_hsphy {
> + status = "okay";
> +};
> +
> +&usb_1_qmpphy {
> + status = "okay";
> +};
> +
> +&usb_2 {
> + status = "okay";
> +};
> +
> +&usb_2_dwc3 {
> + dr_mode = "host";
> +};
> +
> +&usb_2_hsphy {
> + status = "okay";
> +};
> +
> +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
Again, seemingly not very useful.
> +
> +&qspi_cs0 {
> + drive-strength = <8>;
> + bias-disable;
> +};
> +
> +&qspi_clk {
> + drive-strength = <8>;
> + bias-disable;
> +};
> +
> +&qspi_data01 {
> + drive-strength = <8>;
> + /* High-Z when no transfers; nice to park the lines */
> + bias-pull-up;
> +};
> +
> +/* For ap_tp_i2c */
> +&qup_i2c0_data_clk {
> + drive-strength = <2>;
> + /* Has external pull */
> + bias-disable;
> +};
> +
> +/* For ap_i2c_tpm */
> +&qup_i2c14_data_clk {
> + drive-strength = <2>;
> + /* Has external pull */
> + bias-disable;
> +};
> +
> +/* For ap_spi_fp */
> +&qup_spi9_data_clk {
> + drive-strength = <2>;
> + bias-disable;
> +};
> +
> +/* For ap_spi_fp */
> +&qup_spi9_cs_gpio {
> + drive-strength = <2>;
> + bias-disable;
> +};
> +
> +/* For ap_ec_spi */
> +&qup_spi10_data_clk {
> + drive-strength = <2>;
> + bias-disable;
> +};
> +
> +/* For ap_ec_spi */
> +&qup_spi10_cs_gpio {
> + drive-strength = <2>;
> + bias-disable;
> +};
> +
> +/* For uart_dbg */
> +&qup_uart5_rx {
> + bias-pull-up;
> +};
> +
> +/* For uart_dbg */
> +&qup_uart5_tx {
> + drive-strength = <2>;
> + bias-disable;
> +};
> +
> +&sdc2_on {
> + clk {
> + bias-disable;
> + drive-strength = <16>;
> + };
> +
> + cmd {
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> +
> + data {
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> +
> + sd-cd {
> + pins = "gpio91";
> + bias-pull-up;
> + };
> +};
> +
> +/* PINCTRL - board-specific pinctrl */
And again
> +
> +&pm7325_gpios {
> + /*
> + * On a quick glance it might look like KYPD_VOL_UP_N is used, but
> + * that only passes through to a debug connector and not to the actual
> + * volume up key.
> + */
> + status = "disabled"; /* No GPIOs are connected */
> +};
> +
> +&pmk8350_gpios {
> + status = "disabled"; /* No GPIOs are connected */
> +};
> +
> +&tlmm {
> + /*
> + * pinctrl settings for pins that have no real owners.
> + */
You can make it /* one line */
Also, the following pins seem to be in random order, not sorted by either their
name nor by their gpio number..
> + pinctrl-names = "default";
> + pinctrl-0 = <&bios_flash_wp_od>;
> +
> + amp_en: amp-en {
> + pins = "gpio63";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + ap_ec_int_l: ap-ec-int-l {
> + pins = "gpio18";
> + function = "gpio";
> + bias-pull-up;
> + };
> +
> + bios_flash_wp_od: bios-flash-wp-od {
> + pins = "gpio16";
> + function = "gpio";
> + /* Has external pull */
> + bias-disable;
> + };
> +
> + en_fp_rails: en-fp-rails {
> + pins = "gpio77";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + output-high;
> + };
> +
> + en_pp3300_codec: en-pp3300-codec {
> + pins = "gpio105";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + en_pp3300_dx_edp: en-pp3300-dx-edp {
> + pins = "gpio80";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + hub_en: hub-en {
> + pins = "gpio157";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + fp_rst_l: fp-rst-l {
> + pins = "gpio78";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + output-high;
> + };
> +
> + fp_to_ap_irq_l: fp-to-ap-irq-l {
> + pins = "gpio61";
> + function = "gpio";
> + /* Has external pullup */
> + bias-disable;
> + };
> +
> + fpmcu_boot0: fpmcu-boot0 {
> + pins = "gpio68";
> + function = "gpio";
> + bias-disable;
> + output-low;
> + };
> +
> + gsc_ap_int_odl: gsc-ap-int-odl {
> + pins = "gpio104";
> + function = "gpio";
> + bias-pull-up;
> + };
> +
> + hp_irq: hp-irq {
> + pins = "gpio101";
> + function = "gpio";
> + bias-pull-up;
> + };
> +
> + pe_wake_odl: pe-wake-odl {
> + pins = "gpio3";
> + function = "gpio";
> + drive-strength = <2>;
> + /* Has external pull */
> + bias-disable;
> + };
> +
> + /* For ap_spi_fp */
> + qup_spi9_cs_gpio_init_high: qup-spi9-cs-gpio-init-high {
> + pins = "gpio39";
> + function = "gpio";
> + output-high;
> + };
> +
> + /* For ap_ec_spi */
> + qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high {
> + pins = "gpio43";
> + function = "gpio";
> + output-high;
> + };
> +
> + sar0_irq_odl: sar0-irq-odl {
> + pins = "gpio141";
> + function = "gpio";
> + bias-pull-up;
> + };
> +
> + sar1_irq_odl: sar0-irq-odl {
> + pins = "gpio140";
> + function = "gpio";
> + bias-pull-up;
> + };
> +
> + ssd_en: ssd-en {
> + pins = "gpio51";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + ssd_rst_l: ssd-rst-l {
> + pins = "gpio2";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + output-low;
> + };
> +
> + tp_int_odl: tp-int-odl {
> + pins = "gpio7";
> + function = "gpio";
> + /* Has external pullup */
> + bias-disable;
> + };
> +
> + wf_cam_en: wf-cam-en {
> + pins = "gpio119";
> + function = "gpio";
> + drive-strength = <2>;
> + /* Has external pulldown */
> + bias-disable;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
> new file mode 100644
> index 000000000000..caff21d1e588
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
> @@ -0,0 +1,557 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * sc7280 Qcard device tree source
> + *
> + * Qcard PCB has the processor, RAM, eMMC (if stuffed), and eDP connector (if
> + * stuffed) on it. This device tree tries to encapsulate all the things that
> + * all boards using Qcard will have in common. Given that there are stuffing
> + * options, some things may be left with status "disabled" and enabled in
> + * the actual board device tree files.
> + *
> + * Copyright 2022 Google LLC.
> + */
> +
> +#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
> +#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +
> +#include "sc7280.dtsi"
> +
> +/* PMICs depend on spmi_bus label and so must come after SoC */
> +#include "pm7325.dtsi"
> +#include "pm8350c.dtsi"
> +#include "pmk8350.dtsi"
> +
> +/ {
> + aliases {
> + bluetooth0 = &bluetooth;
> + serial0 = &uart5;
> + serial1 = &uart7;
> + };
> +};
> +
> +&apps_rsc {
> + /*
> + * Regulators are given labels corresponding to the various names
> + * they are referred to on schematics. They are also given labels
> + * corresponding to named voltage inputs on the SoC or components
> + * bundled with the SoC (like radio companion chips). We totally
> + * ignore it when one regulator is the input to another regulator.
> + * That's handled automatically by the initial config given to
> + * RPMH by the firmware.
> + *
> + * Regulators that the HLOS (High Level OS) doesn't touch at all
> + * are left out of here since they are managed elsewhere.
> + */
> +
> + pm7325-regulators {
> + compatible = "qcom,pm7325-rpmh-regulators";
> + qcom,pmic-id = "b";
> +
> + vdd19_pmu_pcie_i:
> + vdd19_pmu_rfa_i:
> + vreg_s1b_1p856: smps1 {
> + regulator-min-microvolt = <1856000>;
> + regulator-max-microvolt = <2040000>;
> + };
> +
> + vdd_pmu_aon_i:
> + vdd09_pmu_rfa_i:
> + vdd095_mx_pmu:
> + vdd095_pmu:
> + vreg_s7b_0p952: smps7 {
> + regulator-min-microvolt = <535000>;
> + regulator-max-microvolt = <1120000>;
> + };
> +
> + vdd13_pmu_rfa_i:
> + vdd13_pmu_pcie_i:
> + vreg_s8b_1p256: smps8 {
> + regulator-min-microvolt = <1256000>;
> + regulator-max-microvolt = <1500000>;
> + };
> +
> + vdd_a_usbssdp_0_core:
> + vreg_l1b_0p912: ldo1 {
> + regulator-min-microvolt = <825000>;
> + regulator-max-microvolt = <925000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vdd_a_usbhs_3p1:
> + vreg_l2b_3p072: ldo2 {
> + regulator-min-microvolt = <2700000>;
> + regulator-max-microvolt = <3544000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vdd_a_csi_0_1_1p2:
> + vdd_a_csi_2_3_1p2:
> + vdd_a_csi_4_1p2:
> + vdd_a_dsi_0_1p2:
> + vdd_a_edp_0_1p2:
> + vdd_a_qlink_0_1p2:
> + vdd_a_qlink_1_1p2:
> + vdd_a_pcie_0_1p2:
> + vdd_a_pcie_1_1p2:
> + vdd_a_ufs_0_1p2:
> + vdd_a_usbssdp_0_1p2:
> + vreg_l6b_1p2: ldo6 {
> + regulator-min-microvolt = <1140000>;
> + regulator-max-microvolt = <1260000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + /*
> + * Despite the fact that this is named to be 2.5V on the
> + * schematic, it powers eMMC which doesn't accept 2.5V
> + */
> + vreg_l7b_2p5: ldo7 {
> + regulator-min-microvolt = <2960000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vdd_px_wcd9385:
> + vdd_txrx:
> + vddpx_0:
> + vddpx_3:
> + vddpx_7:
> + vreg_l18b_1p8: ldo18 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vdd_1p8:
> + vdd_px_sdr735:
> + vdd_pxm:
> + vdd18_io:
> + vddio_px_1:
> + vddio_px_2:
> + vddio_px_3:
> + vddpx_ts:
> + vddpx_wl4otp:
> + vreg_l19b_1p8: ldo19 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> + };
> +
> + pm8350c-regulators {
> + compatible = "qcom,pm8350c-rpmh-regulators";
> + qcom,pmic-id = "c";
> +
> + vdd22_wlbtpa_ch0:
> + vdd22_wlbtpa_ch1:
> + vdd22_wlbtppa_ch0:
> + vdd22_wlbtppa_ch1:
> + vdd22_wlpa5g_ch0:
> + vdd22_wlpa5g_ch1:
> + vdd22_wlppa5g_ch0:
> + vdd22_wlppa5g_ch1:
> + vreg_s1c_2p2: smps1 {
> + regulator-min-microvolt = <2190000>;
> + regulator-max-microvolt = <2210000>;
> + };
> +
> + lp4_vdd2_1p052:
> + vreg_s9c_0p676: smps9 {
> + regulator-min-microvolt = <1010000>;
> + regulator-max-microvolt = <1170000>;
> + };
> +
> + vdda_apc_cs_1p8:
> + vdda_gfx_cs_1p8:
> + vdda_turing_q6_cs_1p8:
> + vdd_a_cxo_1p8:
> + vdd_a_qrefs_1p8:
> + vdd_a_usbhs_1p8:
> + vdd_qfprom:
> + vreg_l1c_1p8: ldo1 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1980000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l2c_1p8: ldo2 {
> + regulator-min-microvolt = <1620000>;
> + regulator-max-microvolt = <1980000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l3c_3p0: ldo3 {
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <3540000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vddpx_5:
> + vreg_l4c_1p8_3p0: ldo4 {
> + regulator-min-microvolt = <1620000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vddpx_6:
> + vreg_l5c_1p8_3p0: ldo5 {
> + regulator-min-microvolt = <1620000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vddpx_2:
> + vreg_l6c_2p96: ldo6 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2950000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l7c_3p0: ldo7 {
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3544000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l8c_1p8: ldo8 {
> + regulator-min-microvolt = <1620000>;
> + regulator-max-microvolt = <2000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l9c_2p96: ldo9 {
> + regulator-min-microvolt = <2960000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vdd_a_csi_0_1_0p9:
> + vdd_a_csi_2_3_0p9:
> + vdd_a_csi_4_0p9:
> + vdd_a_dsi_0_0p9:
> + vdd_a_dsi_0_pll_0p9:
> + vdd_a_edp_0_0p9:
> + vdd_a_gnss_0p9:
> + vdd_a_pcie_0_core:
> + vdd_a_pcie_1_core:
> + vdd_a_qlink_0_0p9:
> + vdd_a_qlink_0_0p9_ck:
> + vdd_a_qlink_1_0p9:
> + vdd_a_qlink_1_0p9_ck:
> + vdd_a_qrefs_0p875_0:
> + vdd_a_qrefs_0p875_1:
> + vdd_a_qrefs_0p875_2:
> + vdd_a_qrefs_0p875_3:
> + vdd_a_qrefs_0p875_4_5:
> + vdd_a_qrefs_0p875_6:
> + vdd_a_qrefs_0p875_7:
> + vdd_a_qrefs_0p875_8:
> + vdd_a_qrefs_0p875_9:
> + vdd_a_ufs_0_core:
> + vdd_a_usbhs_core:
> + vreg_l10c_0p88: ldo10 {
> + regulator-min-microvolt = <720000>;
> + regulator-max-microvolt = <1050000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l11c_2p8: ldo11 {
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <3544000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l12c_1p8: ldo12 {
> + regulator-min-microvolt = <1650000>;
> + regulator-max-microvolt = <2000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l13c_3p0: ldo13 {
> + regulator-min-microvolt = <2700000>;
> + regulator-max-microvolt = <3544000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vdd_flash:
> + vdd_iris_rgb:
> + vdd_mic_bias:
> + vreg_bob: bob {
> + regulator-min-microvolt = <3008000>;
> + regulator-max-microvolt = <3960000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + };
> + };
> +};
> +
> +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
Ditto.
> +
> +&ipa {
> + status = "okay";
> + modem-init;
> +};
> +
> +/* For nvme; boards set status = "okay" */
This is kind of obvious, no?
> +&pcie1_phy {
> + vdda-phy-supply = <&vreg_l10c_0p88>;
> + vdda-pll-supply = <&vreg_l6b_1p2>;
> +};
> +
> +&pmk8350_vadc {
> + pmk8350-die-temp@3 {
> + reg = <PMK8350_ADC7_DIE_TEMP>;
> + label = "pmk8350_die_temp";
> + qcom,pre-scaling = <1 1>;
> + };
> +
> + pmr735a-die-temp@403 {
> + reg = <PMR735A_ADC7_DIE_TEMP>;
> + label = "pmr735a_die_temp";
> + qcom,pre-scaling = <1 1>;
> + };
> +};
> +
> +&qfprom {
> + vcc-supply = <&vdd_qfprom>;
> +};
> +
> +/* For eMMC; not all Qcards have eMMC stuffed; boards set status = "okay" */
Same here.
> +&sdhc_1 {
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&sdc1_on>;
> + pinctrl-1 = <&sdc1_off>;
> +
> + vmmc-supply = <&vreg_l7b_2p5>;
> + vqmmc-supply = <&vreg_l19b_1p8>;
> +
> + non-removable;
> + no-sd;
> + no-sdio;
> +};
> +
> +uart_dbg: &uart5 {
> + compatible = "qcom,geni-debug-uart";
> + status = "okay";
> +};
> +
> +mos_bt_uart: &uart7 {
> + status = "okay";
> +
> + /delete-property/interrupts;
I think generally one should put a space after '/'.
> + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
> + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
> +
> + bluetooth: bluetooth {
> + compatible = "qcom,wcn6750-bt";
> + pinctrl-names = "default";
> + pinctrl-0 = <&mos_bt_en>;
> + enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>;
> + swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>;
> + vddaon-supply = <&vreg_s7b_0p952>;
> + vddbtcxmx-supply = <&vreg_s7b_0p952>;
> + vddrfacmn-supply = <&vreg_s7b_0p952>;
> + vddrfa0p8-supply = <&vreg_s7b_0p952>;
> + vddrfa1p7-supply = <&vdd19_pmu_rfa_i>;
> + vddrfa1p2-supply = <&vdd13_pmu_rfa_i>;
> + vddrfa2p2-supply = <&vreg_s1c_2p2>;
> + vddasd-supply = <&vreg_l11c_2p8>;
> + vddio-supply = <&vreg_l18b_1p8>;
> + max-speed = <3200000>;
> + };
> +};
> +
> +&usb_1_hsphy {
> + vdda-pll-supply = <&vdd_a_usbhs_core>;
> + vdda33-supply = <&vdd_a_usbhs_3p1>;
> + vdda18-supply = <&vdd_a_usbhs_1p8>;
> +};
> +
> +&usb_1_qmpphy {
> + vdda-phy-supply = <&vdd_a_usbssdp_0_1p2>;
> + vdda-pll-supply = <&vdd_a_usbssdp_0_core>;
> +};
> +
> +&usb_2_hsphy {
> + vdda-pll-supply = <&vdd_a_usbhs_core>;
> + vdda33-supply = <&vdd_a_usbhs_3p1>;
> + vdda18-supply = <&vdd_a_usbhs_1p8>;
> +};
> +
> +/*
> + * PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES
Again.
> + *
> + * NOTE: In general if pins leave the Qcard then the pinctrl goes in the
> + * baseboard or board device tree, not here.
> + */
> +
> +/*
> + * For ts_i2c
> + *
> + * Technically this i2c bus actually leaves the Qcard, but it leaves directly
> + * via the eDP connector (it doesn't hit the baseboard). The external pulls
> + * are on Qcard.
> + */
> +&qup_i2c13_data_clk {
> + drive-strength = <2>;
> + /* Has external pull */
> + bias-disable;
> +};
> +
> +/* For mos_bt_uart */
> +&qup_uart7_cts {
> + /*
> + * Configure a pull-down on CTS to match the pull of
> + * the Bluetooth module.
My email client doesn't show me the column count, but I think this would
fit in a single 100 char line..
> + */
> + bias-pull-down;
> +};
> +
> +/* For mos_bt_uart */
> +&qup_uart7_rts {
> + /* We'll drive RTS, so no pull */
> + drive-strength = <2>;
> + bias-disable;
> +};
> +
> +/* For mos_bt_uart */
> +&qup_uart7_tx {
> + /* We'll drive TX, so no pull */
> + drive-strength = <2>;
> + bias-disable;
> +};
> +
> +/* For mos_bt_uart */
> +&qup_uart7_rx {
> + /*
> + * Configure a pull-up on RX. This is needed to avoid
> + * garbage data when the TX pin of the Bluetooth module is
> + * in tri-state (module powered off or not driving the
> + * signal yet).
> + */
> + bias-pull-up;
> +};
> +
> +/* eMMC, if stuffed, is straight on the Qcard */
> +&sdc1_on {
> + clk {
> + bias-disable;
> + drive-strength = <16>;
> + };
> +
> + cmd {
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> +
> + data {
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> +
> + rclk {
> + bias-pull-down;
> + };
> +};
> +
> +/*
> + * PINCTRL - QCARD
> + *
> + * This has entries that are defined by Qcard even if they go to the main
> + * board. In cases where the pulls may be board dependent we defer those
> + * settings to the board device tree. Drive strengths tend to be assinged here
> + * but could conceivably be overwridden by board device trees.
> + */
> +
> +&pm8350c_gpios {
> + pmic_edp_bl_en: pmic-edp-bl-en {
> + pins = "gpio7";
> + function = "normal";
> + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
> + bias-disable;
> +
> + /* Force backlight to be disabled to match state at boot. */
> + output-low;
> + };
> +
> + pmic_edp_bl_pwm: pmic-edp-bl-pwm {
> + pins = "gpio8";
> + function = "func1";
> + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
> + bias-disable;
> + output-low;
> + power-source = <0>;
> + };
> +};
> +
> +&tlmm {
> + mos_bt_en: mos-bt-en {
> + pins = "gpio85";
> + function = "gpio";
> + drive-strength = <2>;
> + output-low;
> + };
> +
> + /* For mos_bt_uart */
> + qup_uart7_sleep_cts: qup-uart7-sleep-cts {
> + pins = "gpio28";
> + function = "gpio";
> + /*
> + * Configure a pull-down on CTS to match the pull of
> + * the Bluetooth module.
> + */
> + bias-pull-down;
> + };
> +
> + /* For mos_bt_uart */
> + qup_uart7_sleep_rts: qup-uart7-sleep-rts {
> + pins = "gpio29";
> + function = "gpio";
> + /*
> + * Configure pull-down on RTS. As RTS is active low
> + * signal, pull it low to indicate the BT SoC that it
> + * can wakeup the system anytime from suspend state by
> + * pulling RX low (by sending wakeup bytes).
> + */
> + bias-pull-down;
> + };
> +
> + /* For mos_bt_uart */
> + qup_uart7_sleep_rx: qup-uart7-sleep-rx {
> + pins = "gpio31";
> + function = "gpio";
> + /*
> + * Configure a pull-up on RX. This is needed to avoid
> + * garbage data when the TX pin of the Bluetooth module
> + * is floating which may cause spurious wakeups.
> + */
> + bias-pull-up;
> + };
> +
> + /* For mos_bt_uart */
> + qup_uart7_sleep_tx: qup-uart7-sleep-tx {
> + pins = "gpio30";
> + function = "gpio";
> + /*
> + * Configure pull-up on TX when it isn't actively driven
> + * to prevent BT SoC from receiving garbage during sleep.
> + */
> + bias-pull-up;
> + };
> +
> + ts_int_conn: ts-int-conn {
> + pins = "gpio55";
> + function = "gpio";
> + bias-pull-up;
> + };
> +
> + ts_rst_conn: ts-rst-conn {
> + pins = "gpio54";
> + function = "gpio";
> + bias-pull-up;
> + drive-strength = <2>;
Please be consistent in the order in which you add the same properties throughout
GPIO nodes.
> + };
> +};
>
Konrad
^ permalink raw reply
* Re: [PATCH v2 1/3] spi: dt-bindings: samsung: Add fsd spi compatible
From: Krzysztof Kozlowski @ 2022-01-21 18:33 UTC (permalink / raw)
To: Alim Akhtar, linux-arm-kernel, linux-kernel
Cc: devicetree, linus.walleij, robh+dt, linux-samsung-soc,
pankaj.dubey, broonie, andi, linux-spi, linux-fsd, Adithya K V
In-Reply-To: <20220120192438.25555-2-alim.akhtar@samsung.com>
On 20/01/2022 20:24, Alim Akhtar wrote:
> Adds spi controller dt-binding compatible information for
> Tesla Full Self-Driving (FSD) SoC.
>
> Cc: linux-fsd@tesla.com
> Signed-off-by: Adithya K V <adithya.kv@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
> Documentation/devicetree/bindings/spi/samsung,spi.yaml | 1 +
> 1 file changed, 1 insertion(+)
I think you forgot to mention - in cover letter - that this depends on
my Samsung SPI bindings conversion to dtschema.
I'll be sending v6 of it after merge window, with minor changes.
>
> diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Documentation/devicetree/bindings/spi/samsung,spi.yaml
> index 61c77088e8ee..bf9a76d931d2 100644
> --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml
> +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml
> @@ -21,6 +21,7 @@ properties:
> - samsung,s3c6410-spi
> - samsung,s5pv210-spi # for S5PV210 and S5PC110
> - samsung,exynos5433-spi
> + - tesla,fsd-spi
> - const: samsung,exynos7-spi
> deprecated: true
>
>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 2/3] spi: s3c64xx: Add spi port configuration for Tesla FSD SoC
From: Krzysztof Kozlowski @ 2022-01-21 18:33 UTC (permalink / raw)
To: Alim Akhtar, linux-arm-kernel, linux-kernel
Cc: devicetree, linus.walleij, robh+dt, linux-samsung-soc,
pankaj.dubey, broonie, andi, linux-spi, linux-fsd, Aswani Reddy
In-Reply-To: <20220120192438.25555-3-alim.akhtar@samsung.com>
On 20/01/2022 20:24, Alim Akhtar wrote:
> Adds compatible and port configuration for spi controller
> for Tesla Full Self-Driving SoC.
>
> Cc: linux-fsd@tesla.com
> Signed-off-by: Aswani Reddy <aswani.reddy@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
> drivers/spi/spi-s3c64xx.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 1/3] spi: dt-bindings: samsung: Add fsd spi compatible
From: Krzysztof Kozlowski @ 2022-01-21 18:34 UTC (permalink / raw)
To: Alim Akhtar, linux-arm-kernel, linux-kernel
Cc: devicetree, linus.walleij, robh+dt, linux-samsung-soc,
pankaj.dubey, broonie, andi, linux-spi, linux-fsd, Adithya K V
In-Reply-To: <20220120192438.25555-2-alim.akhtar@samsung.com>
On 20/01/2022 20:24, Alim Akhtar wrote:
> Adds spi controller dt-binding compatible information for
> Tesla Full Self-Driving (FSD) SoC.
>
> Cc: linux-fsd@tesla.com
> Signed-off-by: Adithya K V <adithya.kv@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
> Documentation/devicetree/bindings/spi/samsung,spi.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH] arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlay for imx219 rpi v2 camera
From: Tim Harvey @ 2022-01-21 18:18 UTC (permalink / raw)
To: Rob Herring, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, devicetree, linux-kernel,
linux-arm-kernel
Cc: Tim Harvey
Add support for the RaspberryPi Camera v2 which is an IMX219 8MP module:
- https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf
- has its own on-board 24MHz osc so no clock required from baseboard
- pin 11 enables 1.8V and 2.8V LDO which is connected to
GW73xx MIPI_GPIO4 (IMX8MM GPIO1_IO1) so we use this as a gpio
controlled regulator enable.
Support is added via a device-tree overlay.
The IMX219 supports RAW8/RAW10 image formats.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../imx8mm-venice-gw73xx-0x-imx219.dts | 84 +++++++++++++++++++
2 files changed, 85 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 2d3489eb073d..324c1b01989a 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs232-rts.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs422.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs485.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-imx219.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs232-rts.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtbo
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts
new file mode 100644
index 000000000000..33aa9eb477a5
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";
+
+ reg_cam: regulator-cam {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_cam>;
+ compatible = "regulator-fixed";
+ regulator-name = "reg_cam";
+ gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ cam24m: cam24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "cam24m";
+ };
+};
+
+&csi {
+ status = "okay";
+};
+
+&i2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imx219: sensor@10 {
+ compatible = "sony,imx219";
+ reg = <0x10>;
+ clocks = <&cam24m>;
+ VDIG-supply = <®_cam>;
+
+ port {
+ /* MIPI CSI-2 bus endpoint */
+ imx219_to_mipi_csi2: endpoint {
+ remote-endpoint = <&imx8mm_mipi_csi_in>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ link-frequencies = /bits/ 64 <456000000>;
+ };
+ };
+ };
+};
+
+&mipi_csi {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ imx8mm_mipi_csi_in: endpoint {
+ remote-endpoint = <&imx219_to_mipi_csi2>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_reg_cam: regcamgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41
+ >;
+ };
+};
--
2.17.1
^ permalink raw reply related
* [PATCH] arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlay for imx219 rpi v2 camera
From: Tim Harvey @ 2022-01-21 18:19 UTC (permalink / raw)
To: Rob Herring, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, devicetree, linux-kernel,
linux-arm-kernel
Cc: Tim Harvey
Add support for the RaspberryPi Camera v2 which is an IMX219 8MP module:
- https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf
- has its own on-board 24MHz osc so no clock required from baseboard
- pin 11 enables 1.8V and 2.8V LDO which is connected to
GW73xx MIPI_GPIO4 (IMX8MM GPIO1_IO1) so we use this as a gpio
Support is added via a device-tree overlay.
The IMX219 supports RAW8/RAW10 image formats.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../imx8mm-venice-gw72xx-0x-imx219.dts | 84 +++++++++++++++++++
2 files changed, 85 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 324c1b01989a..08d1f28a5165 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -43,6 +43,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-imx219.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs232-rts.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs422.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs485.dtbo
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts
new file mode 100644
index 000000000000..6fbae90735d4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm";
+
+ reg_cam: regulator-cam {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_cam>;
+ compatible = "regulator-fixed";
+ regulator-name = "reg_cam";
+ gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ cam24m: cam24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "cam24m";
+ };
+};
+
+&csi {
+ status = "okay";
+};
+
+&i2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imx219: sensor@10 {
+ compatible = "sony,imx219";
+ reg = <0x10>;
+ clocks = <&cam24m>;
+ VDIG-supply = <®_cam>;
+
+ port {
+ /* MIPI CSI-2 bus endpoint */
+ imx219_to_mipi_csi2: endpoint {
+ remote-endpoint = <&imx8mm_mipi_csi_in>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ link-frequencies = /bits/ 64 <456000000>;
+ };
+ };
+ };
+};
+
+&mipi_csi {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ imx8mm_mipi_csi_in: endpoint {
+ remote-endpoint = <&imx219_to_mipi_csi2>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_reg_cam: regcamgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41
+ >;
+ };
+};
--
2.17.1
^ permalink raw reply related
* [PATCH] arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlays for serial modes
From: Tim Harvey @ 2022-01-21 18:17 UTC (permalink / raw)
To: Rob Herring, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, devicetree, linux-kernel,
linux-arm-kernel
Cc: Tim Harvey
The imx8mm-venice-gw72xx-0x som+baseboard combination has a multi-protocol
RS-232/RS-485/RS-422 transceiver to an off-board connector which
can be configured in a number of ways via UART and GPIO configuration.
The default configuration per the imx8mm-venice-gw72xx-0x dts is for
UART2 TX/RX and UART4 TX/RX to be available as RS-232:
J15.1 UART2 TX out
J15.2 UART2 RX in
J15.3 UART4 TX out
J15.4 UART4 RX in
J15.5 GND
Add dt overlays to allow additional the modes of operation:
rs232-rts (UART2 RS-232 with RTS/CTS hardware flow control)
J15.1 TX out
J15.2 RX in
J15.3 RTS out
J15.4 CTS in
J15.5 GND
rs485 (UART2 RS-485 half duplex)
J15.1 TXRX-
J15.2 N/C
J15.3 TXRX+
J15.4 N/C
J15.5 GND
rs422 (UART2 RS-422 full duplex)
J15.1 TX-
J15.2 RX+
J15.3 TX+
J15.4 RX-
J15.5 GND
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
arch/arm64/boot/dts/freescale/Makefile | 3 +
.../imx8mm-venice-gw72xx-0x-rs232-rts.dts | 53 ++++++++++++++++
.../imx8mm-venice-gw72xx-0x-rs422.dts | 61 +++++++++++++++++++
.../imx8mm-venice-gw72xx-0x-rs485.dts | 61 +++++++++++++++++++
4 files changed, 178 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 5ec8d59347b6..2d3489eb073d 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -43,6 +43,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs232-rts.dtbo
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs422.dtbo
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs485.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs232-rts.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtbo
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts
new file mode 100644
index 000000000000..3ea73a6886ff
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Gateworks Corporation
+ *
+ * GW72xx RS232 with RTS/CTS hardware flow control:
+ * - GPIO4_0 rs485_en needs to be driven low (in-active)
+ * - UART4_TX becomes RTS
+ * - UART4_RX becomes CTS
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "gw,imx8mm-gw72xx-0x";
+};
+
+&gpio4 {
+ rs485_en {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "rs485_en";
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
+ cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
+ MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x140
+ >;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts
new file mode 100644
index 000000000000..c3cd9f2b0db3
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Gateworks Corporation
+ *
+ * GW72xx RS422 (RS485 full duplex):
+ * - GPIO1_0 rs485_term selects on-chip termination
+ * - GPIO4_0 rs485_en needs to be driven high (active)
+ * - GPIO4_2 rs485_hd needs to be driven low (in-active)
+ * - UART4_TX is DE for RS485 transmitter
+ * - RS485_EN needs to be pulled high
+ * - RS485_HALF needs to be low
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "gw,imx8mm-gw72xx-0x";
+};
+
+&gpio4 {
+ rs485_en {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "rs485_en";
+ };
+
+ rs485_hd {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "rs485_hd";
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
+ linux,rs485-enabled-at-boot-time;
+ status = "okay";
+};
+
+&uart4 {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
+ >;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts
new file mode 100644
index 000000000000..cc0a287226ab
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Gateworks Corporation
+ *
+ * GW72xx RS485 HD:
+ * - GPIO1_0 rs485_term selects on-chip termination
+ * - GPIO4_0 rs485_en needs to be driven high (active)
+ * - GPIO4_2 rs485_hd needs to be driven high (active)
+ * - UART4_TX is DE for RS485 transmitter
+ * - RS485_EN needs to be pulled high
+ * - RS485_HALF needs to be pulled high
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "gw,imx8mm-gw72xx-0x";
+};
+
+&gpio4 {
+ rs485_en {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "rs485_en";
+ };
+
+ rs485_hd {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "rs485_hd";
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
+ linux,rs485-enabled-at-boot-time;
+ status = "okay";
+};
+
+&uart4 {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
+ >;
+ };
+};
--
2.17.1
^ permalink raw reply related
* [PATCH v2] arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlays for serial modes
From: Tim Harvey @ 2022-01-21 18:17 UTC (permalink / raw)
To: Rob Herring, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, devicetree, linux-kernel,
linux-arm-kernel
Cc: Tim Harvey
The imx8mm-venice-gw73xx-0x som+baseboard combination has a multi-protocol
RS-232/RS-485/RS-422 transceiver to an off-board connector which
can be configured in a number of ways via UART and GPIO configuration.
The default configuration per the imx8mm-venice-gw73xx-0x dts is for
UART2 TX/RX and UART4 TX/RX to be available as RS-232:
J15.1 UART2 TX out
J15.2 UART2 RX in
J15.3 UART4 TX out
J15.4 UART4 RX in
J15.5 GND
Add dt overlays to allow additional the modes of operation:
rs232-rts (UART2 RS-232 with RTS/CTS hardware flow control)
J15.1 TX out
J15.2 RX in
J15.3 RTS out
J15.4 CTS in
J15.5 GND
rs485 (UART2 RS-485 half duplex)
J15.1 TXRX-
J15.2 N/C
J15.3 TXRX+
J15.4 N/C
J15.5 GND
rs422 (UART2 RS-422 full duplex)
J15.1 TX-
J15.2 RX+
J15.3 TX+
J15.4 RX-
J15.5 GND
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
v2: fixed typo: s/uast/uart/
---
arch/arm64/boot/dts/freescale/Makefile | 3 +
.../imx8mm-venice-gw73xx-0x-rs232-rts.dts | 53 ++++++++++++++++
.../imx8mm-venice-gw73xx-0x-rs422.dts | 61 +++++++++++++++++++
.../imx8mm-venice-gw73xx-0x-rs485.dts | 61 +++++++++++++++++++
4 files changed, 178 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index a14a6173b765..5ec8d59347b6 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -44,6 +44,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs232-rts.dtbo
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtbo
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts
new file mode 100644
index 000000000000..2fa635e1c1a8
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Gateworks Corporation
+ *
+ * GW73xx RS232 with RTS/CTS hardware flow control:
+ * - GPIO4_0 rs485_en needs to be driven low (in-active)
+ * - UART4_TX becomes RTS
+ * - UART4_RX becomes CTS
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "gw,imx8mm-gw73xx-0x";
+};
+
+&gpio4 {
+ rs485_en {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "rs485_en";
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
+ cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
+ MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x140
+ >;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts
new file mode 100644
index 000000000000..3e6404340d52
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Gateworks Corporation
+ *
+ * GW73xx RS422 (RS485 full duplex):
+ * - GPIO1_0 rs485_term selects on-chip termination
+ * - GPIO4_0 rs485_en needs to be driven high (active)
+ * - GPIO4_2 rs485_hd needs to be driven low (in-active)
+ * - UART4_TX is DE for RS485 transmitter
+ * - RS485_EN needs to be pulled high
+ * - RS485_HALF needs to be low
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "gw,imx8mm-gw73xx-0x";
+};
+
+&gpio4 {
+ rs485_en {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "rs485_en";
+ };
+
+ rs485_hd {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "rs485_hd";
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
+ linux,rs485-enabled-at-boot-time;
+ status = "okay";
+};
+
+&uart4 {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
+ >;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts
new file mode 100644
index 000000000000..2c71ab9854cb
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Gateworks Corporation
+ *
+ * GW73xx RS485 HD:
+ * - GPIO1_0 rs485_term selects on-chip termination
+ * - GPIO4_0 rs485_en needs to be driven high (active)
+ * - GPIO4_2 rs485_hd needs to be driven high (active)
+ * - UART4_TX is DE for RS485 transmitter
+ * - RS485_EN needs to be pulled high
+ * - RS485_HALF needs to be pulled high
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "gw,imx8mm-gw73xx-0x";
+};
+
+&gpio4 {
+ rs485_en {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "rs485_en";
+ };
+
+ rs485_hd {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "rs485_hd";
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
+ linux,rs485-enabled-at-boot-time;
+ status = "okay";
+};
+
+&uart4 {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
+ >;
+ };
+};
--
2.17.1
^ permalink raw reply related
* Re: [PATCH v2 03/15] dt-bindings: clock: Document qcom,gcc-ipq8064 binding
From: Ansuel Smith @ 2022-01-21 19:07 UTC (permalink / raw)
To: Rob Herring
Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Philipp Zabel, Taniya Das, linux-arm-msm, linux-clk, devicetree,
linux-kernel
In-Reply-To: <YeoUk3t2iVbQwj5s@robh.at.kernel.org>
On Thu, Jan 20, 2022 at 08:04:03PM -0600, Rob Herring wrote:
> On Fri, Jan 21, 2022 at 12:20:16AM +0100, Ansuel Smith wrote:
> > Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source
> > clocks. The gcc node is also used by the tsens driver, already documented,
> > to get the calib nvmem cells and the base reg from gcc.
> >
> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > ---
> > .../bindings/clock/qcom,gcc-ipq8064.yaml | 70 +++++++++++++++++++
> > 1 file changed, 70 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> > new file mode 100644
> > index 000000000000..abc76a46b2ca
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> > @@ -0,0 +1,70 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
> > +
> > +allOf:
> > + - $ref: qcom,gcc.yaml#
> > +
> > +maintainers:
> > + - Ansuel Smith <ansuelsmth@gmail.com>
> > +
> > +description: |
> > + Qualcomm global clock control module which supports the clocks, resets and
> > + power domains on IPQ8064.
> > +
> > + See also:
> > + - dt-bindings/clock/qcom,gcc-ipq806x.h
> > + - dt-bindings/reset/qcom,gcc-ipq806x.h
> > +
> > +properties:
>
> This schema will never be applied because there is not a compatible
> property to use for matching. The base/common schema is the one that
> shouldn't have a compatible and then the specific schemas like this
> one do.
>
Just to make things clear. To fix things up, what changes should I do?
- I should remove the compatible from the base schema qcom,gcc.yaml
- Add the compatible to this schema
- Create another schema that includes all the others compatible?
Can I instead:
- Create a qcom,gcc-common.yaml schema
- Modify the qcom,gcc.yaml schema to ref the common one and drop the
other binding.
- Fix this schema with the missing compatible?
Tell me how I should proceed since it looks to me that all the
Documentation for the gcc driver looks a bit mess and full of
duplicated stuff.
> > + clocks:
> > + items:
> > + - description: PXO source
> > + - description: CXO source
> > +
> > + clock-names:
> > + items:
> > + - const: pxo
> > + - const: cxo
> > +
> > + thermal-sensor:
> > + type: object
> > +
> > + allOf:
> > + - $ref: /schemas/thermal/qcom-tsens.yaml#
> > +
> > +required:
> > + - clocks
> > + - clock-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + gcc: clock-controller@900000 {
> > + compatible = "qcom,gcc-ipq8064", "syscon";
> > + reg = <0x00900000 0x4000>;
> > + clocks = <&pxo_board>, <&cxo_board>;
> > + clock-names = "pxo", "cxo";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + #power-domain-cells = <1>;
> > +
> > + tsens: thermal-sensor {
> > + compatible = "qcom,ipq8064-tsens";
> > +
> > + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
> > + nvmem-cell-names = "calib", "calib_backup";
> > + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "uplow";
> > +
> > + #qcom,sensors = <11>;
> > + #thermal-sensor-cells = <1>;
> > + };
> > + };
> > --
> > 2.33.1
> >
> >
--
Ansuel
^ permalink raw reply
* Re: [PATCH devicetree v3] dt-bindings: phy: Add `tx-p2p-microvolt` property binding
From: Florian Fainelli @ 2022-01-21 19:18 UTC (permalink / raw)
To: Marek Behún, Rob Herring, devicetree
Cc: Vladimir Oltean, Holger Brunck, Andrew Lunn,
netdev@vger.kernel.org, Russell King, linux-phy, Vinod Koul,
Kishon Vijay Abraham I
In-Reply-To: <20220119131117.30245-1-kabel@kernel.org>
On 1/19/22 5:11 AM, Marek Behún wrote:
> Common PHYs and network PCSes often have the possibility to specify
> peak-to-peak voltage on the differential pair - the default voltage
> sometimes needs to be changed for a particular board.
>
> Add properties `tx-p2p-microvolt` and `tx-p2p-microvolt-names` for this
> purpose. The second property is needed to specify the mode for the
> corresponding voltage in the `tx-p2p-microvolt` property, if the voltage
> is to be used only for speficic mode. More voltage-mode pairs can be
> specified.
>
> Example usage with only one voltage (it will be used for all supported
> PHY modes, the `tx-p2p-microvolt-names` property is not needed in this
> case):
>
> tx-p2p-microvolt = <915000>;
>
> Example usage with voltages for multiple modes:
>
> tx-p2p-microvolt = <915000>, <1100000>, <1200000>;
> tx-p2p-microvolt-names = "2500base-x", "usb", "pcie";
>
> Add these properties into a separate file phy/transmit-amplitude.yaml,
> which should be referenced by any binding that uses it.
p2p commonly means peer to peer which incidentally could be confusing,
can you spell out the property entire:
tx-peaktopeak-microvolt or:
tx-pk2pk-microvolt for a more compact name maybe?
--
Florian
^ permalink raw reply
* Re: [PATCH v2 03/15] dt-bindings: clock: Document qcom,gcc-ipq8064 binding
From: Rob Herring @ 2022-01-21 19:22 UTC (permalink / raw)
To: Ansuel Smith
Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Philipp Zabel, Taniya Das, linux-arm-msm, linux-clk, devicetree,
linux-kernel
In-Reply-To: <61eb0488.1c69fb81.d267e.3b1f@mx.google.com>
On Fri, Jan 21, 2022 at 1:07 PM Ansuel Smith <ansuelsmth@gmail.com> wrote:
>
> On Thu, Jan 20, 2022 at 08:04:03PM -0600, Rob Herring wrote:
> > On Fri, Jan 21, 2022 at 12:20:16AM +0100, Ansuel Smith wrote:
> > > Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source
> > > clocks. The gcc node is also used by the tsens driver, already documented,
> > > to get the calib nvmem cells and the base reg from gcc.
> > >
> > > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > > ---
> > > .../bindings/clock/qcom,gcc-ipq8064.yaml | 70 +++++++++++++++++++
> > > 1 file changed, 70 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> > > new file mode 100644
> > > index 000000000000..abc76a46b2ca
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> > > @@ -0,0 +1,70 @@
> > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
> > > +
> > > +allOf:
> > > + - $ref: qcom,gcc.yaml#
> > > +
> > > +maintainers:
> > > + - Ansuel Smith <ansuelsmth@gmail.com>
> > > +
> > > +description: |
> > > + Qualcomm global clock control module which supports the clocks, resets and
> > > + power domains on IPQ8064.
> > > +
> > > + See also:
> > > + - dt-bindings/clock/qcom,gcc-ipq806x.h
> > > + - dt-bindings/reset/qcom,gcc-ipq806x.h
> > > +
> > > +properties:
> >
> > This schema will never be applied because there is not a compatible
> > property to use for matching. The base/common schema is the one that
> > shouldn't have a compatible and then the specific schemas like this
> > one do.
> >
>
> Just to make things clear. To fix things up, what changes should I do?
> - I should remove the compatible from the base schema qcom,gcc.yaml
> - Add the compatible to this schema
> - Create another schema that includes all the others compatible?
Yes.
>
> Can I instead:
> - Create a qcom,gcc-common.yaml schema
> - Modify the qcom,gcc.yaml schema to ref the common one and drop the
> other binding.
> - Fix this schema with the missing compatible?
That's fine. That's just a difference in filenames, right?
> Tell me how I should proceed since it looks to me that all the
> Documentation for the gcc driver looks a bit mess and full of
> duplicated stuff.
I think it was originally one document, but had too many if/then
schemas. Or maybe that was another QCom schema. There's no hard rule
on whether to split or not. It's a judgment call.
Rob
^ permalink raw reply
* [PATCH v3 0/9] ARM: mstar: cpupll
From: Romain Perier @ 2022-01-21 19:35 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, linux-clk, Arnd Bergmann,
Daniel Palmer, Romain Perier, Rob Herring
Cc: devicetree, linux-arm-kernel, linux-kernel
This series adds a basic driver for the PLL that generates
the cpu clock on MStar/SigmaStar ARMv7 SoCs.
Unfortunately there isn't much documentation for this thing
so there are few magic values and guesses.
This needs to come after the MPLL DT changes.
Changes since v2:
- Re-ordered Kconfig by name
- Re-ordered includes alphabetically and removed useless ones
- Used timeout for cpu_relax
- Returned DIV_ROUND_DOWN_ULL() directly in
msc313_cpupll_frequencyforreg()
- Returned DIV_ROUND_DOWN_ULL() directly in
msc313_cpupll_regforfrequecy()
- Reduced the number of lines for msc313_cpupll_of_match
- Removed CLK_IS_CRITICAL
Changes since v1:
- Re-worked the series and ensure that 'make dt_binding_check' passes.
The required commit is merged now, so it is okay.
- Fixed coding style issues in the driver and makes check_patch.pl happy
- Added one more commit for extending the opp_table for infinity2m.
Daniel Palmer (8):
dt-bindings: clk: mstar msc313 cpupll binding description
clk: mstar: msc313 cpupll clk driver
ARM: mstar: Add cpupll to base dtsi
ARM: mstar: Link cpupll to cpu
ARM: mstar: Link cpupll to second core
ARM: mstar: Add OPP table for infinity
ARM: mstar: Add OPP table for infinity3
ARM: mstar: Add OPP table for mercury5
Romain Perier (1):
ARM: mstar: Extend opp_table for infinity2m
.../bindings/clock/mstar,msc313-cpupll.yaml | 45 ++++
arch/arm/boot/dts/mstar-infinity.dtsi | 34 +++
arch/arm/boot/dts/mstar-infinity2m.dtsi | 17 ++
arch/arm/boot/dts/mstar-infinity3.dtsi | 58 +++++
arch/arm/boot/dts/mstar-mercury5.dtsi | 36 +++
arch/arm/boot/dts/mstar-v7.dtsi | 9 +
drivers/clk/mstar/Kconfig | 8 +
drivers/clk/mstar/Makefile | 2 +-
drivers/clk/mstar/clk-msc313-cpupll.c | 221 ++++++++++++++++++
9 files changed, 429 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml
create mode 100644 drivers/clk/mstar/clk-msc313-cpupll.c
--
2.34.1
^ permalink raw reply
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