* Re: [PATCH v3 3/9] ARM: mstar: Add cpupll to base dtsi
From: Daniel Palmer @ 2022-01-23 5:10 UTC (permalink / raw)
To: Romain Perier
Cc: Michael Turquette, Stephen Boyd, linux-clk, Arnd Bergmann,
Rob Herring, DTML, linux-arm-kernel, Linux Kernel Mailing List
In-Reply-To: <20220121193544.23231-4-romain.perier@gmail.com>
Hi Romain,
On Sat, 22 Jan 2022 at 04:35, Romain Perier <romain.perier@gmail.com> wrote:
>
> From: Daniel Palmer <daniel@0x0f.com>
>
> All MStar/SigmaStar ARMv7 SoCs have the CPU PLL at the same
> place so add it to the base dtsi.
>
> Signed-off-by: Daniel Palmer <daniel@0x0f.com>
> ---
> arch/arm/boot/dts/mstar-v7.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
> index 89ebfe4f29da..2249faaa3aa7 100644
> --- a/arch/arm/boot/dts/mstar-v7.dtsi
> +++ b/arch/arm/boot/dts/mstar-v7.dtsi
> @@ -155,6 +155,13 @@ mpll: mpll@206000 {
> clocks = <&xtal>;
> };
>
> + cpupll: cpupll@206400 {
> + compatible = "mstar,msc313-cpupll";
> + reg = <0x206400 0x200>;
> + #clock-cells = <0>;
> + clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
> + };
> +
> gpio: gpio@207800 {
> #gpio-cells = <2>;
> reg = <0x207800 0x200>;
> --
> 2.34.1
>
I guess I can't add a reviewed by for my own commit but this looks good to me.
The same CPUPLL is present on all of the chips seen so far so this is
the right place for this.
Cheers,
Daniel
^ permalink raw reply
* Re: [PATCH 3/4] dt-bindings: bus: add device tree bindings for qcom,ssc-block-bus
From: Rob Herring @ 2022-01-23 3:01 UTC (permalink / raw)
To: michael.srba
Cc: Bjorn Andersson, Greg Kroah-Hartman, Andy Gross, devicetree,
Rob Herring, Saravana Kannan, Florian Fainelli, Linus Walleij,
Philipp Zabel, Arnd Bergmann, Michael Srba, linux-arm-msm,
Stephen Boyd
In-Reply-To: <20220122180413.1480-3-michael.srba@seznam.cz>
On Sat, 22 Jan 2022 19:04:12 +0100, michael.srba@seznam.cz wrote:
> From: Michael Srba <Michael.Srba@seznam.cz>
>
> This patch adds bindings for the AHB bus which exposes the SCC block in
> the global address space. This bus (and the SSC block itself) is present
> on certain qcom SoCs.
>
> In typical configuration, this bus (as some of the clocks and registers
> that we need to manipulate) is not accessible to the OS, and the
> resources on this bus are indirectly accessed by communicating with a
> hexagon CPU core residing in the SSC block. In this configuration, the
> hypervisor is the one performing the bus initialization for the purposes
> of bringing the haxagon CPU core out of reset.
>
> However, it is possible to change the configuration, in which case this
> binding serves to allow the OS to initialize the bus.
>
> Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
> ---
> .../bindings/bus/qcom,ssc-block-bus.yaml | 156 ++++++++++++++++++
> 1 file changed, 156 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml:30:7: [warning] wrong indentation: expected 8 but found 6 (indentation)
./Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml:30:22: [warning] too few spaces after comma (commas)
./Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml:123:111: [warning] line too long (135 > 110 characters) (line-length)
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml: properties:reg-names: {'minItems': 2, 'maxItems': 2, 'items': [{'const': 'mpm_sscaon_config0'}, {'const': 'mpm_sscaon_config1'}]} should not be valid under {'required': ['maxItems']}
hint: "maxItems" is not needed with an "items" list
from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml: properties:reg-names: 'oneOf' conditional failed, one must be fixed:
[{'const': 'mpm_sscaon_config0'}, {'const': 'mpm_sscaon_config1'}] is too long
[{'const': 'mpm_sscaon_config0'}, {'const': 'mpm_sscaon_config1'}] is too short
False schema does not allow 2
1 was expected
hint: "minItems" is only needed if less than the "items" list length
from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml: ignoring, error in schema: properties: reg-names
Error: Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.example.dts:21.9-13 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:373: Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1413: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1583024
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply
* Re: [RFC 19/28] media: dt-bindings: media: renesas,vsp1: Document RZ/{G2L,V2L} VSPD bindings
From: Laurent Pinchart @ 2022-01-23 0:14 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mauro Carvalho Chehab, Kieran Bingham,
linux-media@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
devicetree@vger.kernel.org, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad
In-Reply-To: <OS0PR01MB5922E4E0E015D3EE42A97F36865C9@OS0PR01MB5922.jpnprd01.prod.outlook.com>
Hi Biju,
On Sat, Jan 22, 2022 at 11:23:32AM +0000, Biju Das wrote:
> > Subject: Re: [RFC 19/28] media: dt-bindings: media: renesas,vsp1: Document
> > RZ/{G2L,V2L} VSPD bindings
> >
> > On Wed, Jan 12, 2022 at 05:46:03PM +0000, Biju Das wrote:
> > > Document VSPD found in RZ/G2L and RZ/V2L family SoC's.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > ---
> > > Documentation/devicetree/bindings/media/renesas,vsp1.yaml | 4 +++-
> > > 1 file changed, 3 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> > > index 990e9c1dbc43..b27ee23d2b29 100644
> > > --- a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> > > +++ b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> > > @@ -19,6 +19,7 @@ properties:
> > > enum:
> > > - renesas,vsp1 # R-Car Gen2 and RZ/G1
> > > - renesas,vsp2 # R-Car Gen3 and RZ/G2
> > > + - renesas,vsp2-r9a07g044 # RZ/G2L and RZ/V2L
The commit message should explain why a new device-specific compatible
value is needed.
> > >
> > > reg:
> > > maxItems: 1
> > > @@ -27,7 +28,8 @@ properties:
> > > maxItems: 1
> > >
> > > clocks:
> > > - maxItems: 1
> > > + minItems: 1
> > > + maxItems: 3
> >
> > You have to define what each one is once you have more than 1.
>
> Agreed, Will define each clocks.
This should also be conditioned by the compatible string, to have
maxItems set to 1 for renesas,vsp1 and renesas,vsp2, and 3 for
renesas,vsp2-r9a07g044.
> > > power-domains:
> > > maxItems: 1
--
Regards,
Laurent Pinchart
^ permalink raw reply
* [PATCH AUTOSEL 5.15 04/16] riscv: dts: microchip: mpfs: Fix reference clock node
From: Sasha Levin @ 2022-01-23 0:12 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Geert Uytterhoeven, Krzysztof Kozlowski, Conor Dooley,
Palmer Dabbelt, Sasha Levin, robh+dt, paul.walmsley, palmer, aou,
bin.meng, atishp, devicetree, linux-riscv
In-Reply-To: <20220123001216.2460383-1-sashal@kernel.org>
From: Geert Uytterhoeven <geert@linux-m68k.org>
[ Upstream commit 9d7b3078628f591e4007210c0d5d3f94805cff55 ]
"make dtbs_check" reports:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[600000000]], 'clock-output-names': ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type': 'object'}
From schema: dtschema/schemas/simple-bus.yaml
Fix this by moving the node out of the "soc" subnode.
While at it, rename it to "msspllclk", and drop the now superfluous
"clock-output-names" property.
Move the actual clock-frequency value to the board DTS, since it is not
set until bitstream programming time.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
.../boot/dts/microchip/microchip-mpfs-icicle-kit.dts | 4 ++++
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 12 +++++-------
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index cce5eca31f257..4b69ab4ff30a2 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -40,6 +40,10 @@ soc {
};
};
+&refclk {
+ clock-frequency = <600000000>;
+};
+
&serial0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index b12fd594e7172..18ccbdbe86d99 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -142,6 +142,11 @@ cpu4_intc: interrupt-controller {
};
};
+ refclk: msspllclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
soc {
#address-cells = <2>;
#size-cells = <2>;
@@ -191,13 +196,6 @@ dma@3000000 {
#dma-cells = <1>;
};
- refclk: refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <600000000>;
- clock-output-names = "msspllclk";
- };
-
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply related
* [PATCH AUTOSEL 5.16 04/19] riscv: dts: microchip: mpfs: Fix reference clock node
From: Sasha Levin @ 2022-01-23 0:10 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Geert Uytterhoeven, Krzysztof Kozlowski, Conor Dooley,
Palmer Dabbelt, Sasha Levin, robh+dt, paul.walmsley, palmer, aou,
bin.meng, atishp, devicetree, linux-riscv
In-Reply-To: <20220123001113.2460140-1-sashal@kernel.org>
From: Geert Uytterhoeven <geert@linux-m68k.org>
[ Upstream commit 9d7b3078628f591e4007210c0d5d3f94805cff55 ]
"make dtbs_check" reports:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[600000000]], 'clock-output-names': ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type': 'object'}
From schema: dtschema/schemas/simple-bus.yaml
Fix this by moving the node out of the "soc" subnode.
While at it, rename it to "msspllclk", and drop the now superfluous
"clock-output-names" property.
Move the actual clock-frequency value to the board DTS, since it is not
set until bitstream programming time.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
.../boot/dts/microchip/microchip-mpfs-icicle-kit.dts | 4 ++++
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 12 +++++-------
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index fc1e5869df1b9..0c748ae1b0068 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -35,6 +35,10 @@ memory@80000000 {
};
};
+&refclk {
+ clock-frequency = <600000000>;
+};
+
&serial0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index c9f6d205d2ba1..393f18cdbb346 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -142,6 +142,11 @@ cpu4_intc: interrupt-controller {
};
};
+ refclk: msspllclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
soc {
#address-cells = <2>;
#size-cells = <2>;
@@ -191,13 +196,6 @@ dma@3000000 {
#dma-cells = <1>;
};
- refclk: refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <600000000>;
- clock-output-names = "msspllclk";
- };
-
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply related
* Re: [RFC PATCH v2 4/7] media: bcm2835-unicam: Add support for for CCP2/CSI2 camera interface
From: Laurent Pinchart @ 2022-01-22 23:26 UTC (permalink / raw)
To: Jean-Michel Hautbois
Cc: dave.stevenson, devicetree, kernel-list, linux-arm-kernel,
linux-kernel, linux-media, linux-rpi-kernel, lukasz, mchehab,
naush, robh, tomi.valkeinen
In-Reply-To: <20220121081810.155500-5-jeanmichel.hautbois@ideasonboard.com>
Hi Jean-Michel,
Thank you for the patch.
Dave, Naush, there are a few questions for you below.
On Fri, Jan 21, 2022 at 09:18:07AM +0100, Jean-Michel Hautbois wrote:
> Add driver for the Unicam camera receiver block on BCM283x processors.
> It is represented as two video device nodes: unicam-image and
> unicam-embedded which are connected to an internal subdev (named
> unicam-subdev) in order to manage streams routing.
>
> Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
> Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@ideasonboard.com>
>
> ---
> in v2: Remove the unicam_{info,debug,error} macros and use
> dev_dbg/dev_err instead.
> ---
> MAINTAINERS | 1 +
> drivers/media/platform/Kconfig | 1 +
> drivers/media/platform/Makefile | 2 +
> drivers/media/platform/bcm2835/Kconfig | 21 +
> drivers/media/platform/bcm2835/Makefile | 3 +
> .../media/platform/bcm2835/bcm2835-unicam.c | 2678 +++++++++++++++++
> .../media/platform/bcm2835/vc4-regs-unicam.h | 253 ++
> 7 files changed, 2959 insertions(+)
> create mode 100644 drivers/media/platform/bcm2835/Kconfig
> create mode 100644 drivers/media/platform/bcm2835/Makefile
> create mode 100644 drivers/media/platform/bcm2835/bcm2835-unicam.c
> create mode 100644 drivers/media/platform/bcm2835/vc4-regs-unicam.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 07f238fd5ff9..b17bb533e007 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3684,6 +3684,7 @@ M: Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
> L: linux-media@vger.kernel.org
> S: Maintained
> F: Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml
> +F: drivers/media/platform/bcm2835/
>
> BROADCOM BCM47XX MIPS ARCHITECTURE
> M: Hauke Mehrtens <hauke@hauke-m.de>
> diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
> index 9fbdba0fd1e7..033b0358fbb8 100644
> --- a/drivers/media/platform/Kconfig
> +++ b/drivers/media/platform/Kconfig
> @@ -170,6 +170,7 @@ source "drivers/media/platform/am437x/Kconfig"
> source "drivers/media/platform/xilinx/Kconfig"
> source "drivers/media/platform/rcar-vin/Kconfig"
> source "drivers/media/platform/atmel/Kconfig"
> +source "drivers/media/platform/bcm2835/Kconfig"
> source "drivers/media/platform/sunxi/Kconfig"
>
> config VIDEO_TI_CAL
> diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
> index 19bcbced7382..689e64857db1 100644
> --- a/drivers/media/platform/Makefile
> +++ b/drivers/media/platform/Makefile
> @@ -85,6 +85,8 @@ obj-$(CONFIG_VIDEO_QCOM_CAMSS) += qcom/camss/
>
> obj-$(CONFIG_VIDEO_QCOM_VENUS) += qcom/venus/
>
> +obj-y += bcm2835/
One day it would be nice to clean the media Kconfig and Makefile
infrastructure to use a consistent style for all drivers. One can always
dream :-)
> +
> obj-y += sunxi/
>
> obj-$(CONFIG_VIDEO_MESON_GE2D) += meson/ge2d/
> diff --git a/drivers/media/platform/bcm2835/Kconfig b/drivers/media/platform/bcm2835/Kconfig
> new file mode 100644
> index 000000000000..bd1370199650
> --- /dev/null
> +++ b/drivers/media/platform/bcm2835/Kconfig
> @@ -0,0 +1,21 @@
> +# Broadcom VideoCore4 V4L2 camera support
> +
> +config VIDEO_BCM2835_UNICAM
> + tristate "Broadcom BCM283x/BCM271x Unicam video capture driver"
> + depends on VIDEO_V4L2
> + depends on ARCH_BCM2835 || COMPILE_TEST
I would put the arch dependency first, but that may be just me.
> + select VIDEO_V4L2_SUBDEV_API
> + select MEDIA_CONTROLLER
> + select VIDEOBUF2_DMA_CONTIG
> + select V4L2_FWNODE
And sort there alphabetically.
> + help
> + Say Y here to enable support for the BCM283x/BCM271x CSI-2 receiver.
> + This is a V4L2 driver that controls the CSI-2 receiver directly,
> + independently from the VC4 firmware.
> + This driver is mutually exclusive with the use of bcm2835-camera. The
> + firmware will disable all access to the peripheral from within the
> + firmware if it finds a DT node using it, and bcm2835-camera will
> + therefore fail to probe.
Dave, Naush, what should we do with the bcm2835-camera driver in staging
? Do we need to keep it to support older Pi models ?
> +
> + To compile this driver as a module, choose M here. The module will be
> + called bcm2835-unicam.
> diff --git a/drivers/media/platform/bcm2835/Makefile b/drivers/media/platform/bcm2835/Makefile
> new file mode 100644
> index 000000000000..a98aba03598a
> --- /dev/null
> +++ b/drivers/media/platform/bcm2835/Makefile
> @@ -0,0 +1,3 @@
> +# Makefile for BCM2835 Unicam driver
> +
> +obj-$(CONFIG_VIDEO_BCM2835_UNICAM) += bcm2835-unicam.o
> diff --git a/drivers/media/platform/bcm2835/bcm2835-unicam.c b/drivers/media/platform/bcm2835/bcm2835-unicam.c
> new file mode 100644
> index 000000000000..7636496be00a
> --- /dev/null
> +++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c
> @@ -0,0 +1,2678 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * BCM283x / BCM271x Unicam Capture Driver
> + *
> + * Copyright (C) 2017-2020 - Raspberry Pi (Trading) Ltd.
> + *
> + * Dave Stevenson <dave.stevenson@raspberrypi.com>
> + *
> + * Based on TI am437x driver by
> + * Benoit Parrot <bparrot@ti.com>
> + * Lad, Prabhakar <prabhakar.csengg@gmail.com>
> + *
> + * and TI CAL camera interface driver by
> + * Benoit Parrot <bparrot@ti.com>
> + *
> + *
> + * There are two camera drivers in the kernel for BCM283x - this one
> + * and bcm2835-camera (currently in staging).
> + *
> + * This driver directly controls the Unicam peripheral - there is no
> + * involvement with the VideoCore firmware. Unicam receives CSI-2 or
> + * CCP2 data and writes it into SDRAM.
> + * The only potential processing options are to repack Bayer data into an
> + * alternate format, and applying windowing.
> + * The repacking does not shift the data, so can repack V4L2_PIX_FMT_Sxxxx10P
> + * to V4L2_PIX_FMT_Sxxxx10, or V4L2_PIX_FMT_Sxxxx12P to V4L2_PIX_FMT_Sxxxx12,
> + * but not generically up to V4L2_PIX_FMT_Sxxxx16. The driver will add both
> + * formats where the relevant formats are defined, and will automatically
> + * configure the repacking as required.
> + * Support for windowing may be added later.
> + *
> + * It should be possible to connect this driver to any sensor with a
> + * suitable output interface and V4L2 subdevice driver.
> + *
> + * bcm2835-camera uses the VideoCore firmware to control the sensor,
> + * Unicam, ISP, and all tuner control loops. Fully processed frames are
> + * delivered to the driver by the firmware. It only has sensor drivers
> + * for Omnivision OV5647, and Sony IMX219 sensors.
> + *
> + * The two drivers are mutually exclusive for the same Unicam instance.
> + * The VideoCore firmware checks the device tree configuration during boot.
> + * If it finds device tree nodes called csi0 or csi1 it will block the
> + * firmware from accessing the peripheral, and bcm2835-camera will
> + * not be able to stream data.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of_graph.h>
> +#include <linux/pinctrl/consumer.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/slab.h>
> +#include <linux/uaccess.h>
> +#include <linux/videodev2.h>
> +
> +#include <media/v4l2-common.h>
> +#include <media/v4l2-ctrls.h>
> +#include <media/v4l2-dev.h>
> +#include <media/v4l2-device.h>
> +#include <media/v4l2-dv-timings.h>
> +#include <media/v4l2-event.h>
> +#include <media/v4l2-ioctl.h>
> +#include <media/v4l2-fwnode.h>
> +#include <media/videobuf2-dma-contig.h>
> +
> +#include <media/v4l2-async.h>
> +#define v4l2_async_nf_add_subdev __v4l2_async_nf_add_subdev
Don't do that ! It's the kind of pattern that a malicious actor would
use to obfuscate code and get vulnerabilities merged.
> +
> +#include "vc4-regs-unicam.h"
> +
> +#define UNICAM_MODULE_NAME "unicam"
> +#define UNICAM_VERSION "0.1.0"
I doubt the version would ever be incremented, so let's just drop it.
> +
> +static int debug;
> +module_param(debug, int, 0644);
> +MODULE_PARM_DESC(debug, "Debug level 0-3");
Not used.
> +
> +/*
> + * Unicam must request a minimum of 250Mhz from the VPU clock.
> + * Otherwise the input FIFOs overrun and cause image corruption.
> + */
> +#define MIN_VPU_CLOCK_RATE (250 * 1000 * 1000)
> +/*
> + * To protect against a dodgy sensor driver never returning an error from
> + * enum_mbus_code, set a maximum index value to be used.
> + */
> +#define MAX_ENUM_MBUS_CODE 128
> +
> +/*
> + * Stride is a 16 bit register, but also has to be a multiple of 32.
> + */
> +#define BPL_ALIGNMENT 32
> +#define MAX_BYTESPERLINE ((1 << 16) - BPL_ALIGNMENT)
> +/*
> + * Max width is therefore determined by the max stride divided by
> + * the number of bits per pixel. Take 32bpp as a
> + * worst case.
> + * No imposed limit on the height, so adopt a square image for want
> + * of anything better.
> + */
> +#define MAX_WIDTH (MAX_BYTESPERLINE / 4)
> +#define MAX_HEIGHT MAX_WIDTH
> +/* Define a nominal minimum image size */
> +#define MIN_WIDTH 16
> +#define MIN_HEIGHT 16
> +/* Default size of the embedded buffer */
> +#define UNICAM_EMBEDDED_SIZE 16384
> +
> +/*
> + * Size of the dummy buffer. Can be any size really, but the DMA
> + * allocation works in units of page sizes.
> + */
> +#define DUMMY_BUF_SIZE (PAGE_SIZE)
No need for parentheses.
Some of those macros have toogeneric names and may result in namespace
clashes. Please prefix them all with UNICAM_.
> +
> +#define UNICAM_SD_PAD_SINK 0
> +#define UNICAM_SD_PAD_FIRST_SOURCE 1
I'd name the source pads explicitly.
#define UNICAM_SD_PAD_SOURCE_IMAGE 1
#define UNICAM_SD_PAD_SOURCE_METADATA 2
(or META instead of METADATA, up to you, as long as we use consistent
naming through the driver).
> +#define UNICAM_SD_NUM_SOURCE_PADS 2
> +#define UNICAM_SD_NUM_PADS (1 + UNICAM_SD_NUM_SOURCE_PADS)
> +
> +static inline bool unicam_sd_pad_is_sink(u32 pad)
> +{
> + /* Camera RX has 1 sink pad, and N source pads */
> + return pad == 0;
> +}
> +
> +static inline bool unicam_sd_pad_is_source(u32 pad)
> +{
> + /* Camera RX has 1 sink pad, and N source pads */
> + return pad >= UNICAM_SD_PAD_FIRST_SOURCE &&
> + pad <= UNICAM_SD_NUM_SOURCE_PADS;
return pad != UNICAM_SD_PAD_SINK;
and drop UNICAM_SD_PAD_FIRST_SOURCE and UNICAM_SD_NUM_SOURCE_PADS.
> +}
> +
> +enum node_types {
enum unicam_node_type {
> + IMAGE_NODE,
> + METADATA_NODE,
> + MAX_NODES
> +};
UNICAM_ prefixes please.
> +
> +#define MASK_CS_DEFAULT BIT(V4L2_COLORSPACE_DEFAULT)
This and several of the macros below are not used.
> +#define MASK_CS_SMPTE170M BIT(V4L2_COLORSPACE_SMPTE170M)
> +#define MASK_CS_SMPTE240M BIT(V4L2_COLORSPACE_SMPTE240M)
> +#define MASK_CS_REC709 BIT(V4L2_COLORSPACE_REC709)
> +#define MASK_CS_BT878 BIT(V4L2_COLORSPACE_BT878)
> +#define MASK_CS_470_M BIT(V4L2_COLORSPACE_470_SYSTEM_M)
> +#define MASK_CS_470_BG BIT(V4L2_COLORSPACE_470_SYSTEM_BG)
> +#define MASK_CS_JPEG BIT(V4L2_COLORSPACE_JPEG)
> +#define MASK_CS_SRGB BIT(V4L2_COLORSPACE_SRGB)
> +#define MASK_CS_OPRGB BIT(V4L2_COLORSPACE_OPRGB)
> +#define MASK_CS_BT2020 BIT(V4L2_COLORSPACE_BT2020)
> +#define MASK_CS_RAW BIT(V4L2_COLORSPACE_RAW)
> +#define MASK_CS_DCI_P3 BIT(V4L2_COLORSPACE_DCI_P3)
> +
> +#define MAX_COLORSPACE 32
> +
> +/*
> + * struct unicam_fmt - Unicam media bus format information
> + * @pixelformat: V4L2 pixel format FCC identifier. 0 if n/a.
> + * @repacked_fourcc: V4L2 pixel format FCC identifier if the data is expanded
> + * out to 16bpp. 0 if n/a.
> + * @code: V4L2 media bus format code.
> + * @depth: Bits per pixel as delivered from the source.
> + * @csi_dt: CSI data type.
> + * @valid_colorspaces: Bitmask of valid colorspaces so that the Media Controller
> + * centric try_fmt can validate the colorspace and pass
> + * v4l2-compliance.
I'd actually drop colorspace support completely. Unicam doesn't affect
the colorspace. It will output whatever it receives from the sensor. You
can accept any colorspace on the sink pad of the subdev, and just
propagate that to the source pad.
If that causes v4l2-compliance failures, then we have a problem either
in the sensor drivers, or in v4l2-compliance.
> + * @check_variants: Flag to denote that there are multiple mediabus formats
> + * still in the list that could match this V4L2 format.
> + * @mc_skip: Media Controller shouldn't list this format via ENUM_FMT as it is
> + * a duplicate of an earlier format.
> + * @metadata_fmt: This format only applies to the metadata pad.
> + */
> +struct unicam_fmt {
> + u32 fourcc;
> + u32 repacked_fourcc;
> + u32 code;
> + u8 depth;
> + u8 csi_dt;
> + u32 valid_colorspaces;
> + u8 check_variants:1;
> + u8 mc_skip:1;
> + u8 metadata_fmt:1;
> +};
> +
> +static const struct unicam_fmt formats[] = {
> + /* YUV Formats */
> + {
> + .fourcc = V4L2_PIX_FMT_YUYV,
> + .code = MEDIA_BUS_FMT_YUYV8_2X8,
The convention for CSI-2 buses is to used the _1X16 media bus codes for
YUV. You can drop the first four entries, and drop the check_variants
and mc_skip fields.
> + .depth = 16,
> + .csi_dt = 0x1e,
> + .check_variants = 1,
> + .valid_colorspaces = MASK_CS_SMPTE170M | MASK_CS_REC709 |
> + MASK_CS_JPEG,
> + }, {
> + .fourcc = V4L2_PIX_FMT_UYVY,
> + .code = MEDIA_BUS_FMT_UYVY8_2X8,
> + .depth = 16,
> + .csi_dt = 0x1e,
> + .check_variants = 1,
> + .valid_colorspaces = MASK_CS_SMPTE170M | MASK_CS_REC709 |
> + MASK_CS_JPEG,
> + }, {
> + .fourcc = V4L2_PIX_FMT_YVYU,
> + .code = MEDIA_BUS_FMT_YVYU8_2X8,
> + .depth = 16,
> + .csi_dt = 0x1e,
> + .check_variants = 1,
> + .valid_colorspaces = MASK_CS_SMPTE170M | MASK_CS_REC709 |
> + MASK_CS_JPEG,
> + }, {
> + .fourcc = V4L2_PIX_FMT_VYUY,
> + .code = MEDIA_BUS_FMT_VYUY8_2X8,
> + .depth = 16,
> + .csi_dt = 0x1e,
> + .check_variants = 1,
> + .valid_colorspaces = MASK_CS_SMPTE170M | MASK_CS_REC709 |
> + MASK_CS_JPEG,
> + }, {
> + .fourcc = V4L2_PIX_FMT_YUYV,
> + .code = MEDIA_BUS_FMT_YUYV8_1X16,
> + .depth = 16,
> + .csi_dt = 0x1e,
> + .mc_skip = 1,
> + .valid_colorspaces = MASK_CS_SMPTE170M | MASK_CS_REC709 |
> + MASK_CS_JPEG,
> + }, {
> + .fourcc = V4L2_PIX_FMT_UYVY,
> + .code = MEDIA_BUS_FMT_UYVY8_1X16,
> + .depth = 16,
> + .csi_dt = 0x1e,
> + .mc_skip = 1,
> + .valid_colorspaces = MASK_CS_SMPTE170M | MASK_CS_REC709 |
> + MASK_CS_JPEG,
> + }, {
> + .fourcc = V4L2_PIX_FMT_YVYU,
> + .code = MEDIA_BUS_FMT_YVYU8_1X16,
> + .depth = 16,
> + .csi_dt = 0x1e,
> + .mc_skip = 1,
> + .valid_colorspaces = MASK_CS_SMPTE170M | MASK_CS_REC709 |
> + MASK_CS_JPEG,
> + }, {
> + .fourcc = V4L2_PIX_FMT_VYUY,
> + .code = MEDIA_BUS_FMT_VYUY8_1X16,
> + .depth = 16,
> + .csi_dt = 0x1e,
> + .mc_skip = 1,
> + .valid_colorspaces = MASK_CS_SMPTE170M | MASK_CS_REC709 |
> + MASK_CS_JPEG,
> + }, {
> + /* RGB Formats */
> + .fourcc = V4L2_PIX_FMT_RGB565, /* gggbbbbb rrrrrggg */
> + .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
> + .depth = 16,
> + .csi_dt = 0x22,
> + .valid_colorspaces = MASK_CS_SRGB,
> + }, {
> + .fourcc = V4L2_PIX_FMT_RGB565X, /* rrrrrggg gggbbbbb */
> + .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
> + .depth = 16,
> + .csi_dt = 0x22,
> + .valid_colorspaces = MASK_CS_SRGB,
CSI-2 specifies the RGB565 format unambiguously, there are no little
endian of big endian variants. Let's drop one of the two entries, and
use MEDIA_BUS_FMT_RGB565_1X15. Dave, Naush, what is the correct pixel
format for this, is data layed out in big endian or little endian ?
> + }, {
> + .fourcc = V4L2_PIX_FMT_RGB555, /* gggbbbbb arrrrrgg */
> + .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
> + .depth = 16,
> + .csi_dt = 0x21,
> + .valid_colorspaces = MASK_CS_SRGB,
> + }, {
> + .fourcc = V4L2_PIX_FMT_RGB555X, /* arrrrrgg gggbbbbb */
> + .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
> + .depth = 16,
> + .csi_dt = 0x21,
> + .valid_colorspaces = MASK_CS_SRGB,
Same here, but we need to define a new MEDIA_BUS_FMT_RGB555_1X16 format.
The CSI-2 RGB555 data type has the padding bit between the green and
blue components, so I wonder if Unicam maps that to one of
V4L2_PIX_FMT_RGB555 or V4L2_PIX_FMT_RGB555X, or if a new pixel format is
needed too.
Another option would be to drop RGB555 support until someone needs it
(with a comment in the table to tell the entry is missing).
> + }, {
> + .fourcc = V4L2_PIX_FMT_RGB24, /* rgb */
> + .code = MEDIA_BUS_FMT_RGB888_1X24,
> + .depth = 24,
> + .csi_dt = 0x24,
> + .valid_colorspaces = MASK_CS_SRGB,
> + }, {
> + .fourcc = V4L2_PIX_FMT_BGR24, /* bgr */
> + .code = MEDIA_BUS_FMT_BGR888_1X24,
> + .depth = 24,
> + .csi_dt = 0x24,
> + .valid_colorspaces = MASK_CS_SRGB,
This is possibly more tricky, as CSI-2 defined RGB888 as being
transmitted in BGR order, but sensors could possibly also support RGB as
a non-standard extension (the same may CSI-2 standardizes on UYVY, but
many sensors can swap components). We can keep both entry I suppose.
> + }, {
> + .fourcc = V4L2_PIX_FMT_RGB32, /* argb */
> + .code = MEDIA_BUS_FMT_ARGB8888_1X32,
> + .depth = 32,
> + .csi_dt = 0x0,
> + .valid_colorspaces = MASK_CS_SRGB,
There's no 32-bit RGB in CSI-2, should this be dropped ?
> + }, {
> + /* Bayer Formats */
> + .fourcc = V4L2_PIX_FMT_SBGGR8,
> + .code = MEDIA_BUS_FMT_SBGGR8_1X8,
> + .depth = 8,
> + .csi_dt = 0x2a,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGBRG8,
> + .code = MEDIA_BUS_FMT_SGBRG8_1X8,
> + .depth = 8,
> + .csi_dt = 0x2a,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGRBG8,
> + .code = MEDIA_BUS_FMT_SGRBG8_1X8,
> + .depth = 8,
> + .csi_dt = 0x2a,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SRGGB8,
> + .code = MEDIA_BUS_FMT_SRGGB8_1X8,
> + .depth = 8,
> + .csi_dt = 0x2a,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SBGGR10P,
> + .repacked_fourcc = V4L2_PIX_FMT_SBGGR10,
> + .code = MEDIA_BUS_FMT_SBGGR10_1X10,
> + .depth = 10,
> + .csi_dt = 0x2b,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGBRG10P,
> + .repacked_fourcc = V4L2_PIX_FMT_SGBRG10,
> + .code = MEDIA_BUS_FMT_SGBRG10_1X10,
> + .depth = 10,
> + .csi_dt = 0x2b,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGRBG10P,
> + .repacked_fourcc = V4L2_PIX_FMT_SGRBG10,
> + .code = MEDIA_BUS_FMT_SGRBG10_1X10,
> + .depth = 10,
> + .csi_dt = 0x2b,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SRGGB10P,
> + .repacked_fourcc = V4L2_PIX_FMT_SRGGB10,
> + .code = MEDIA_BUS_FMT_SRGGB10_1X10,
> + .depth = 10,
> + .csi_dt = 0x2b,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SBGGR12P,
> + .repacked_fourcc = V4L2_PIX_FMT_SBGGR12,
> + .code = MEDIA_BUS_FMT_SBGGR12_1X12,
> + .depth = 12,
> + .csi_dt = 0x2c,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGBRG12P,
> + .repacked_fourcc = V4L2_PIX_FMT_SGBRG12,
> + .code = MEDIA_BUS_FMT_SGBRG12_1X12,
> + .depth = 12,
> + .csi_dt = 0x2c,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGRBG12P,
> + .repacked_fourcc = V4L2_PIX_FMT_SGRBG12,
> + .code = MEDIA_BUS_FMT_SGRBG12_1X12,
> + .depth = 12,
> + .csi_dt = 0x2c,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SRGGB12P,
> + .repacked_fourcc = V4L2_PIX_FMT_SRGGB12,
> + .code = MEDIA_BUS_FMT_SRGGB12_1X12,
> + .depth = 12,
> + .csi_dt = 0x2c,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SBGGR14P,
> + .repacked_fourcc = V4L2_PIX_FMT_SBGGR14,
> + .code = MEDIA_BUS_FMT_SBGGR14_1X14,
> + .depth = 14,
> + .csi_dt = 0x2d,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGBRG14P,
> + .repacked_fourcc = V4L2_PIX_FMT_SGBRG14,
> + .code = MEDIA_BUS_FMT_SGBRG14_1X14,
> + .depth = 14,
> + .csi_dt = 0x2d,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGRBG14P,
> + .repacked_fourcc = V4L2_PIX_FMT_SGRBG14,
> + .code = MEDIA_BUS_FMT_SGRBG14_1X14,
> + .depth = 14,
> + .csi_dt = 0x2d,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SRGGB14P,
> + .repacked_fourcc = V4L2_PIX_FMT_SRGGB14,
> + .code = MEDIA_BUS_FMT_SRGGB14_1X14,
> + .depth = 14,
> + .csi_dt = 0x2d,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + /*
> + * 16 bit Bayer formats could be supported, but there is no CSI2
> + * data_type defined for raw 16, and no sensors that produce it at
> + * present.
> + */
RAW16 is now defined in CSI-2, but that can be handled later.
> +
> + /* Greyscale formats */
> + .fourcc = V4L2_PIX_FMT_GREY,
> + .code = MEDIA_BUS_FMT_Y8_1X8,
> + .depth = 8,
> + .csi_dt = 0x2a,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_Y10P,
> + .repacked_fourcc = V4L2_PIX_FMT_Y10,
> + .code = MEDIA_BUS_FMT_Y10_1X10,
> + .depth = 10,
> + .csi_dt = 0x2b,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_Y12P,
> + .repacked_fourcc = V4L2_PIX_FMT_Y12,
> + .code = MEDIA_BUS_FMT_Y12_1X12,
> + .depth = 12,
> + .csi_dt = 0x2c,
> + .valid_colorspaces = MASK_CS_RAW,
> + }, {
> + .fourcc = V4L2_PIX_FMT_Y14P,
> + .repacked_fourcc = V4L2_PIX_FMT_Y14,
> + .code = MEDIA_BUS_FMT_Y14_1X14,
> + .depth = 14,
> + .csi_dt = 0x2d,
> + .valid_colorspaces = MASK_CS_RAW,
> + },
> + /* Embedded data format */
> + {
> + .fourcc = V4L2_META_FMT_8,
> + .code = MEDIA_BUS_FMT_METADATA_8,
> + .depth = 8,
> + .metadata_fmt = 1,
> + }
> +};
Let's reorder the code a bit to improve readability:
- Macro definitions
- Structure definitions (with the container_of wrappers following the
respective structure)
- Misc helper functions (from is_metadata_node() to reg_write_field())
- Format data table and helper functions (from find_format_by_code() to
unicam_calc_format_size_bpl())
- Hardware handling:
- From unicam_wr_dma_addr() to unicam_isr()
- From unicam_set_packing_config() to unicam_disable()
- V4L2 subdev (ops & initialization & registration)
- vb2 queue opq
- V4L2 video device (ops & initialization & registration)
- Probe
I recommend adding a comment header in front of each section after the
structure definitions with a distinctive visual appearance, to delimit
code blocks very clearly. I usually use the following style:
/* -----------------------------------------------------------------------------
* V4L2 Subdev Operations
*/
> +
> +struct unicam_buffer {
> + struct vb2_v4l2_buffer vb;
> + struct list_head list;
> +};
> +
> +static inline struct unicam_buffer *to_unicam_buffer(struct vb2_buffer *vb)
> +{
> + return container_of(vb, struct unicam_buffer, vb.vb2_buf);
> +}
> +
> +struct unicam_node {
> + bool registered;
> + int open;
Not used. Please go through all structure fields and delete the ones
that are not used.
> + bool streaming;
> + unsigned int node_id;
> + /* Source pad id on the sensor for this node */
> + unsigned int src_pad_id;
> + /* Pointer pointing to current v4l2_buffer */
> + struct unicam_buffer *cur_frm;
> + /* Pointer pointing to next v4l2_buffer */
> + struct unicam_buffer *next_frm;
> + /* video capture */
> + const struct unicam_fmt *fmt;
> + /* Used to store current pixel format */
> + struct v4l2_format v_fmt;
> + /* Used to store current mbus frame format */
> + struct v4l2_mbus_framefmt m_fmt;
> + /* Buffer queue used in video-buf */
> + struct vb2_queue buffer_queue;
> + /* Queue of filled frames */
> + struct list_head dma_queue;
> + /* IRQ lock for DMA queue */
> + spinlock_t dma_queue_lock;
> + /* lock used to access this structure */
> + struct mutex lock;
> + /* Identifies video device for this channel */
> + struct video_device video_dev;
> + /* Pointer to the parent handle */
> + struct unicam_device *dev;
> + struct media_pad pad;
> + unsigned int embedded_lines;
> + struct media_pipeline pipe;
> + /*
> + * Dummy buffer intended to be used by unicam
> + * if we have no other queued buffers to swap to.
> + */
> + void *dummy_buf_cpu_addr;
> + dma_addr_t dummy_buf_dma_addr;
> +};
> +
> +struct unicam_device {
> + struct kref kref;
> +
> + /* V4l2 specific parameters */
> + struct v4l2_async_subdev asd;
> +
> + /* peripheral base address */
> + void __iomem *base;
> + /* clock gating base address */
> + void __iomem *clk_gate_base;
> + /* lp clock handle */
> + struct clk *clock;
> + /* vpu clock handle */
> + struct clk *vpu_clock;
> + /* vpu clock request */
> + struct clk_request *vpu_req;
Not used (and that may be a problem).
> + /* clock status for error handling */
> + bool clocks_enabled;
> + /* V4l2 device */
> + struct v4l2_device v4l2_dev;
> + struct media_device mdev;
> +
> + /* parent device */
> + struct platform_device *pdev;
The pdev field is only used to access pdev.dev, so I'd replace it with
the struct device.
> + /* subdevice async Notifier */
> + struct v4l2_async_notifier notifier;
> + unsigned int sequence;
> +
> + /* ptr to sub device */
> + struct v4l2_subdev *sensor;
> + /* Pad config for the sensor */
> + struct v4l2_subdev_state *sensor_state;
> +
> + /* Internal subdev */
> + struct v4l2_subdev sd;
> + struct media_pad pads[UNICAM_SD_NUM_PADS];
> +
> + bool streaming;
"streaming" is ambiguous, it's not clear it relates to the subdev. I'd
group all the fields related to the subdev in a structure:
struct {
struct v4l2_subdev sd;
struct media_pad pads[UNICAM_SD_NUM_PADS];
bool streaming;
} subdev;
(there may be more, I haven't checked)
> +
> + enum v4l2_mbus_type bus_type;
> + /*
> + * Stores bus.mipi_csi2.flags for CSI2 sensors, or
> + * bus.mipi_csi1.strobe for CCP2.
> + */
> + unsigned int bus_flags;
> + unsigned int max_data_lanes;
> + unsigned int active_data_lanes;
> + bool sensor_embedded_data;
> +
> + struct unicam_node node[MAX_NODES];
> + struct v4l2_ctrl_handler ctrl_handler;
> +
> + bool mc_api;
> +};
> +
> +static inline struct unicam_device *
> +to_unicam_device(struct v4l2_device *v4l2_dev)
I'd rename this to v4l2_device_to_unicam_device(), as there's another
container_of wrapper.
> +{
> + return container_of(v4l2_dev, struct unicam_device, v4l2_dev);
> +}
> +
> +static inline struct unicam_device *
> +sd_to_unicam_device(struct v4l2_subdev *sd)
> +{
> + return container_of(sd, struct unicam_device, sd);
> +}
> +
> +static inline bool is_metadata_node(struct unicam_node *node)
> +{
> + return node->video_dev.device_caps & V4L2_CAP_META_CAPTURE;
> +}
> +
> +static inline bool is_image_node(struct unicam_node *node)
> +{
> + return node->video_dev.device_caps & V4L2_CAP_VIDEO_CAPTURE;
> +}
> +
> +/* Hardware access */
> +static inline void clk_write(struct unicam_device *dev, u32 val)
> +{
> + writel(val | 0x5a000000, dev->clk_gate_base);
> +}
The name of this function and the functions below are too generic. Add a
unicam_ prefix.
> +
> +static inline u32 reg_read(struct unicam_device *dev, u32 offset)
> +{
> + return readl(dev->base + offset);
> +}
> +
> +static inline void reg_write(struct unicam_device *dev, u32 offset, u32 val)
> +{
> + writel(val, dev->base + offset);
> +}
> +
> +static inline int get_field(u32 value, u32 mask)
> +{
> + return (value & mask) >> __ffs(mask);
> +}
> +
> +static inline void set_field(u32 *valp, u32 field, u32 mask)
> +{
> + u32 val = *valp;
> +
> + val &= ~mask;
> + val |= (field << __ffs(mask)) & mask;
> + *valp = val;
> +}
> +
> +static inline u32 reg_read_field(struct unicam_device *dev, u32 offset,
> + u32 mask)
Not used.
> +{
> + return get_field(reg_read(dev, offset), mask);
> +}
> +
> +static inline void reg_write_field(struct unicam_device *dev, u32 offset,
> + u32 field, u32 mask)
> +{
> + u32 val = reg_read(dev, offset);
> +
> + set_field(&val, field, mask);
> + reg_write(dev, offset, val);
> +}
I'm really not a bit fan of the read-modify-update patterns, more often
than not they can be replaced by direct writes. No need to fix this
though, it's ok.
> +
> +/* Power management functions */
> +static inline int unicam_runtime_get(struct unicam_device *dev)
> +{
> + return pm_runtime_get_sync(&dev->pdev->dev);
Use pm_runtime_resume_and_get() instead, as the error handling is broken
in the driver otherwise.
> +}
> +
> +static inline void unicam_runtime_put(struct unicam_device *dev)
> +{
> + pm_runtime_put_sync(&dev->pdev->dev);
> +}
Drop these wrappers and call the functions directly.
> +
> +/* Format setup functions */
> +static const struct unicam_fmt *find_format_by_code(u32 code)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < ARRAY_SIZE(formats); i++) {
> + if (formats[i].code == code)
> + return &formats[i];
> + }
> +
> + return NULL;
> +}
> +
> +static const struct unicam_fmt *find_format_by_fourcc(u32 fourcc)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < ARRAY_SIZE(formats); ++i) {
> + if (formats[i].fourcc == fourcc)
> + return &formats[i];
> + }
> +
> + return NULL;
> +}
> +
> +static unsigned int bytes_per_line(u32 width, const struct unicam_fmt *fmt,
> + u32 v4l2_fourcc)
> +{
> + if (v4l2_fourcc == fmt->repacked_fourcc)
> + /* Repacking always goes to 16bpp */
> + return ALIGN(width << 1, BPL_ALIGNMENT);
> + else
> + return ALIGN((width * fmt->depth) >> 3, BPL_ALIGNMENT);
> +}
> +
> +static int unicam_calc_format_size_bpl(struct unicam_device *dev,
> + const struct unicam_fmt *fmt,
> + struct v4l2_format *f)
> +{
> + unsigned int min_bytesperline;
> +
> + v4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 2,
> + &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 0,
> + 0);
> +
> + min_bytesperline = bytes_per_line(f->fmt.pix.width, fmt,
> + f->fmt.pix.pixelformat);
> +
> + if (f->fmt.pix.bytesperline > min_bytesperline &&
> + f->fmt.pix.bytesperline <= MAX_BYTESPERLINE)
> + f->fmt.pix.bytesperline = ALIGN(f->fmt.pix.bytesperline,
> + BPL_ALIGNMENT);
> + else
> + f->fmt.pix.bytesperline = min_bytesperline;
> +
> + f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
> +
> + dev_dbg(dev->v4l2_dev.dev, "%s: fourcc: %08X size: %dx%d bpl:%d img_size:%d\n",
> + __func__,
> + f->fmt.pix.pixelformat,
> + f->fmt.pix.width, f->fmt.pix.height,
> + f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
> +
> + return 0;
> +}
> +
> +static void unicam_wr_dma_addr(struct unicam_device *dev, dma_addr_t dmaaddr,
> + unsigned int buffer_size, int node_id)
> +{
> + dma_addr_t endaddr = dmaaddr + buffer_size;
> +
> + if (node_id == IMAGE_NODE) {
> + reg_write(dev, UNICAM_IBSA0, dmaaddr);
> + reg_write(dev, UNICAM_IBEA0, endaddr);
> + } else {
> + reg_write(dev, UNICAM_DBSA0, dmaaddr);
> + reg_write(dev, UNICAM_DBEA0, endaddr);
> + }
> +}
> +
> +static unsigned int unicam_get_lines_done(struct unicam_device *dev)
> +{
> + dma_addr_t start_addr, cur_addr;
> + unsigned int stride = dev->node[IMAGE_NODE].v_fmt.fmt.pix.bytesperline;
> + struct unicam_buffer *frm = dev->node[IMAGE_NODE].cur_frm;
> +
> + if (!frm)
> + return 0;
> +
> + start_addr = vb2_dma_contig_plane_dma_addr(&frm->vb.vb2_buf, 0);
> + cur_addr = reg_read(dev, UNICAM_IBWP);
> + return (unsigned int)(cur_addr - start_addr) / stride;
> +}
> +
> +static void unicam_schedule_next_buffer(struct unicam_node *node)
> +{
> + struct unicam_device *dev = node->dev;
> + struct unicam_buffer *buf;
> + unsigned int size;
> + dma_addr_t addr;
> +
> + buf = list_first_entry(&node->dma_queue, struct unicam_buffer, list);
> + node->next_frm = buf;
> + list_del(&buf->list);
> +
> + addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
> + if (is_image_node(node)) {
> + size = node->v_fmt.fmt.pix.sizeimage;
> + unicam_wr_dma_addr(dev, addr, size, IMAGE_NODE);
> + } else {
> + size = node->v_fmt.fmt.meta.buffersize;
> + unicam_wr_dma_addr(dev, addr, size, METADATA_NODE);
> + }
> +}
> +
> +static void unicam_schedule_dummy_buffer(struct unicam_node *node)
> +{
> + struct unicam_device *dev = node->dev;
> + int node_id = is_image_node(node) ? IMAGE_NODE : METADATA_NODE;
> +
> + dev_dbg(dev->v4l2_dev.dev, "Scheduling dummy buffer for node %d\n", node_id);
> +
> + unicam_wr_dma_addr(dev, node->dummy_buf_dma_addr, DUMMY_BUF_SIZE,
> + node_id);
> + node->next_frm = NULL;
> +}
> +
> +static void unicam_process_buffer_complete(struct unicam_node *node,
> + unsigned int sequence)
> +{
> + node->cur_frm->vb.field = node->m_fmt.field;
> + node->cur_frm->vb.sequence = sequence;
> +
> + vb2_buffer_done(&node->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);
> +}
> +
> +static void unicam_queue_event_sof(struct unicam_device *unicam)
> +{
> + struct v4l2_event event = {
> + .type = V4L2_EVENT_FRAME_SYNC,
> + .u.frame_sync.frame_sequence = unicam->sequence,
> + };
> +
> + v4l2_event_queue(&unicam->node[IMAGE_NODE].video_dev, &event);
> +}
> +
> +/*
> + * unicam_isr : ISR handler for unicam capture
> + * @irq: irq number
> + * @dev_id: dev_id ptr
> + *
> + * It changes status of the captured buffer, takes next buffer from the queue
> + * and sets its address in unicam registers
> + */
> +static irqreturn_t unicam_isr(int irq, void *dev)
> +{
> + struct unicam_device *unicam = dev;
> + unsigned int lines_done = unicam_get_lines_done(dev);
> + unsigned int sequence = unicam->sequence;
> + unsigned int i;
> + u32 ista, sta;
> + bool fe;
> + u64 ts;
> +
> + sta = reg_read(unicam, UNICAM_STA);
> + /* Write value back to clear the interrupts */
> + reg_write(unicam, UNICAM_STA, sta);
> +
> + ista = reg_read(unicam, UNICAM_ISTA);
> + /* Write value back to clear the interrupts */
> + reg_write(unicam, UNICAM_ISTA, ista);
> +
> + dev_dbg(unicam->v4l2_dev.dev, "ISR: ISTA: 0x%X, STA: 0x%X, sequence %d, lines done %d",
> + ista, sta, sequence, lines_done);
> +
> + if (!(sta & (UNICAM_IS | UNICAM_PI0)))
> + return IRQ_HANDLED;
> +
> + /*
> + * Look for either the Frame End interrupt or the Packet Capture status
> + * to signal a frame end.
> + */
> + fe = (ista & UNICAM_FEI || sta & UNICAM_PI0);
No need for the outer parentheses.
> +
> + /*
> + * We must run the frame end handler first. If we have a valid next_frm
> + * and we get a simultaneout FE + FS interrupt, running the FS handler
> + * first would null out the next_frm ptr and we would have lost the
> + * buffer forever.
> + */
> + if (fe) {
> + /*
> + * Ensure we have swapped buffers already as we can't
> + * stop the peripheral. If no buffer is available, use a
> + * dummy buffer to dump out frames until we get a new buffer
> + * to use.
> + */
> + for (i = 0; i < ARRAY_SIZE(unicam->node); i++) {
> + if (!unicam->node[i].streaming)
> + continue;
> +
> + /*
> + * If cur_frm == next_frm, it means we have not had
> + * a chance to swap buffers, likely due to having
> + * multiple interrupts occurring simultaneously (like FE
> + * + FS + LS). In this case, we cannot signal the buffer
> + * as complete, as the HW will reuse that buffer.
> + */
> + if (unicam->node[i].cur_frm &&
> + unicam->node[i].cur_frm != unicam->node[i].next_frm)
> + unicam_process_buffer_complete(&unicam->node[i],
> + sequence);
> + unicam->node[i].cur_frm = unicam->node[i].next_frm;
> + }
> + unicam->sequence++;
> + }
> +
> + if (ista & UNICAM_FSI) {
> + /*
> + * Timestamp is to be when the first data byte was captured,
> + * aka frame start.
> + */
> + ts = ktime_get_ns();
> + for (i = 0; i < ARRAY_SIZE(unicam->node); i++) {
> + if (!unicam->node[i].streaming)
> + continue;
> +
> + if (unicam->node[i].cur_frm)
> + unicam->node[i].cur_frm->vb.vb2_buf.timestamp =
> + ts;
> + else
> + dev_dbg(unicam->v4l2_dev.dev, "ISR: [%d] Dropping frame, buffer not available at FS\n",
> + i);
> + /*
> + * Set the next frame output to go to a dummy frame
> + * if we have not managed to obtain another frame
> + * from the queue.
> + */
> + unicam_schedule_dummy_buffer(&unicam->node[i]);
> + }
> +
> + unicam_queue_event_sof(unicam);
> + }
> +
> + /*
> + * Cannot swap buffer at frame end, there may be a race condition
> + * where the HW does not actually swap it if the new frame has
> + * already started.
> + */
> + if (ista & (UNICAM_FSI | UNICAM_LCI) && !fe) {
> + for (i = 0; i < ARRAY_SIZE(unicam->node); i++) {
> + if (!unicam->node[i].streaming)
> + continue;
> +
> + spin_lock(&unicam->node[i].dma_queue_lock);
> + if (!list_empty(&unicam->node[i].dma_queue) &&
> + !unicam->node[i].next_frm)
> + unicam_schedule_next_buffer(&unicam->node[i]);
> + spin_unlock(&unicam->node[i].dma_queue_lock);
> + }
> + }
> +
> + if (reg_read(unicam, UNICAM_ICTL) & UNICAM_FCM) {
> + /* Switch out of trigger mode if selected */
> + reg_write_field(unicam, UNICAM_ICTL, 1, UNICAM_TFC);
> + reg_write_field(unicam, UNICAM_ICTL, 0, UNICAM_FCM);
> + }
> + return IRQ_HANDLED;
> +}
> +
> +/* V4L2 Common IOCTLs */
> +static int unicam_querycap(struct file *file, void *priv,
> + struct v4l2_capability *cap)
> +{
> + struct unicam_node *node = video_drvdata(file);
> + struct unicam_device *dev = node->dev;
> +
> + strscpy(cap->driver, UNICAM_MODULE_NAME, sizeof(cap->driver));
> + strscpy(cap->card, UNICAM_MODULE_NAME, sizeof(cap->card));
> +
> + snprintf(cap->bus_info, sizeof(cap->bus_info),
> + "platform:%s", dev_name(&dev->pdev->dev));
> +
> + cap->capabilities |= V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_META_CAPTURE;
> +
> + return 0;
> +}
> +
> +static int unicam_log_status(struct file *file, void *fh)
> +{
> + struct unicam_node *node = video_drvdata(file);
> + struct unicam_device *dev = node->dev;
> + u32 reg;
> +
> + /* status for sub devices */
> + v4l2_device_call_all(&dev->v4l2_dev, 0, core, log_status);
I'm tempted to drop this, bit I won't insist.
> +
> + dev_info(dev->v4l2_dev.dev, "-----Receiver status-----\n");
> + dev_info(dev->v4l2_dev.dev, "V4L2 width/height: %ux%u\n",
> + node->v_fmt.fmt.pix.width, node->v_fmt.fmt.pix.height);
> + dev_info(dev->v4l2_dev.dev, "Mediabus format: %08x\n", node->fmt->code);
> + dev_info(dev->v4l2_dev.dev, "V4L2 format: %08x\n",
> + node->v_fmt.fmt.pix.pixelformat);
> + reg = reg_read(dev, UNICAM_IPIPE);
> + dev_info(dev->v4l2_dev.dev, "Unpacking/packing: %u / %u\n",
> + get_field(reg, UNICAM_PUM_MASK),
> + get_field(reg, UNICAM_PPM_MASK));
> + dev_info(dev->v4l2_dev.dev, "----Live data----\n");
> + dev_info(dev->v4l2_dev.dev, "Programmed stride: %4u\n",
> + reg_read(dev, UNICAM_IBLS));
> + dev_info(dev->v4l2_dev.dev, "Detected resolution: %ux%u\n",
> + reg_read(dev, UNICAM_IHSTA),
> + reg_read(dev, UNICAM_IVSTA));
> + dev_info(dev->v4l2_dev.dev, "Write pointer: %08x\n",
> + reg_read(dev, UNICAM_IBWP));
> +
> + return 0;
> +}
> +
> +static int unicam_subscribe_event(struct v4l2_fh *fh,
> + const struct v4l2_event_subscription *sub)
> +{
> + switch (sub->type) {
> + case V4L2_EVENT_FRAME_SYNC:
> + return v4l2_event_subscribe(fh, sub, 2, NULL);
> + case V4L2_EVENT_SOURCE_CHANGE:
> + return v4l2_event_subscribe(fh, sub, 4, NULL);
The drive doesn't generate V4L2_EVENT_SOURCE_CHANGE events, drop it.
> + }
> +
> + return v4l2_ctrl_subscribe_event(fh, sub);
> +}
> +
> +static void unicam_notify(struct v4l2_subdev *sd,
> + unsigned int notification, void *arg)
> +{
> + struct unicam_device *dev = to_unicam_device(sd->v4l2_dev);
Use sd_to_unicam_device().
> +
> + switch (notification) {
> + case V4L2_DEVICE_NOTIFY_EVENT:
> + v4l2_event_queue(&dev->node[IMAGE_NODE].video_dev, arg);
> + break;
> + default:
> + break;
> + }
> +}
Not needed, drop it.
> +
> +/* V4L2 Media Controller Centric IOCTLs */
> +
> +static int unicam_mc_enum_fmt_vid_cap(struct file *file, void *priv,
> + struct v4l2_fmtdesc *f)
Drop "mc" in all function names as that's the only option now.
> +{
> + int i, j;
Never negative, can be unsigned int.
j is not a loop counter but the format index, I'd rename it to index to
make it clearer.
> +
> + for (i = 0, j = 0; i < ARRAY_SIZE(formats); i++) {
> + if (f->mbus_code && formats[i].code != f->mbus_code)
> + continue;
> + if (formats[i].mc_skip || formats[i].metadata_fmt)
> + continue;
> +
> + if (formats[i].fourcc) {
All entries have a fourcc so you can drop this check.
> + if (j == f->index) {
> + f->pixelformat = formats[i].fourcc;
> + f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
Not needed, the type is an input parameter. Same below.
> + return 0;
> + }
> + j++;
> + }
> + if (formats[i].repacked_fourcc) {
> + if (j == f->index) {
> + f->pixelformat = formats[i].repacked_fourcc;
> + f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
> + return 0;
> + }
> + j++;
> + }
> + }
> +
> + return -EINVAL;
> +}
> +
> +static int unicam_mc_g_fmt_vid_cap(struct file *file, void *priv,
> + struct v4l2_format *f)
> +{
> + struct unicam_node *node = video_drvdata(file);
> +
> + if (!is_image_node(node))
> + return -EINVAL;
Can this happen ?
> +
> + *f = node->v_fmt;
> +
> + return 0;
> +}
> +
> +static void unicam_mc_try_fmt(struct unicam_node *node, struct v4l2_format *f,
> + const struct unicam_fmt **ret_fmt)
> +{
> + struct v4l2_pix_format *v4l2_format = &f->fmt.pix;
> + struct unicam_device *dev = node->dev;
> + const struct unicam_fmt *fmt;
> + int is_rgb;
bool.
> +
> + /*
> + * Default to the first format if the requested pixel format code isn't
> + * supported.
> + */
> + fmt = find_format_by_fourcc(v4l2_format->pixelformat);
> + if (!fmt) {
> + fmt = &formats[0];
> + v4l2_format->pixelformat = fmt->fourcc;
> + }
> +
> + unicam_calc_format_size_bpl(dev, fmt, f);
> +
> + if (v4l2_format->field == V4L2_FIELD_ANY)
> + v4l2_format->field = V4L2_FIELD_NONE;
> +
> + if (v4l2_format->colorspace >= MAX_COLORSPACE ||
> + !(fmt->valid_colorspaces & (1 << v4l2_format->colorspace))) {
> + v4l2_format->colorspace = __ffs(fmt->valid_colorspaces);
> +
> + v4l2_format->xfer_func =
> + V4L2_MAP_XFER_FUNC_DEFAULT(v4l2_format->colorspace);
> + v4l2_format->ycbcr_enc =
> + V4L2_MAP_YCBCR_ENC_DEFAULT(v4l2_format->colorspace);
> + is_rgb = v4l2_format->colorspace == V4L2_COLORSPACE_SRGB;
> + v4l2_format->quantization =
> + V4L2_MAP_QUANTIZATION_DEFAULT(is_rgb,
> + v4l2_format->colorspace,
> + v4l2_format->ycbcr_enc);
> + }
Drop this, we can accept any colorspace produced by the sensor.
> +
> + if (ret_fmt)
> + *ret_fmt = fmt;
How about returning the format from the function instead ?
> +
> + dev_dbg(dev->v4l2_dev.dev, "%s: %08x %ux%u (bytesperline %u sizeimage %u)\n",
> + __func__, v4l2_format->pixelformat,
> + v4l2_format->width, v4l2_format->height,
> + v4l2_format->bytesperline, v4l2_format->sizeimage);
> +}
> +
> +static int unicam_mc_try_fmt_vid_cap(struct file *file, void *priv,
> + struct v4l2_format *f)
> +{
> + struct unicam_node *node = video_drvdata(file);
> +
> + unicam_mc_try_fmt(node, f, NULL);
> + return 0;
> +}
> +
> +static int unicam_mc_s_fmt_vid_cap(struct file *file, void *priv,
> + struct v4l2_format *f)
> +{
> + struct unicam_node *node = video_drvdata(file);
> + struct unicam_device *dev = node->dev;
> + const struct unicam_fmt *fmt;
> +
> + if (vb2_is_busy(&node->buffer_queue)) {
> + dev_dbg(dev->v4l2_dev.dev, "%s device busy\n", __func__);
> + return -EBUSY;
> + }
> +
> + unicam_mc_try_fmt(node, f, &fmt);
> +
> + node->v_fmt = *f;
> + node->fmt = fmt;
> +
> + return 0;
> +}
> +
> +static int unicam_mc_enum_framesizes(struct file *file, void *fh,
> + struct v4l2_frmsizeenum *fsize)
> +{
> + struct unicam_node *node = video_drvdata(file);
> + struct unicam_device *dev = node->dev;
> +
> + if (fsize->index > 0)
> + return -EINVAL;
> +
> + if (!find_format_by_fourcc(fsize->pixel_format)) {
> + dev_dbg(dev->v4l2_dev.dev, "Invalid pixel format 0x%08x\n",
> + fsize->pixel_format);
I'd drop this message.
> + return -EINVAL;
> + }
> +
> + fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
> + fsize->stepwise.min_width = MIN_WIDTH;
> + fsize->stepwise.max_width = MAX_WIDTH;
> + fsize->stepwise.step_width = 1;
> + fsize->stepwise.min_height = MIN_HEIGHT;
> + fsize->stepwise.max_height = MAX_HEIGHT;
> + fsize->stepwise.step_height = 1;
Is this valid for the metadata node too ?
> +
> + return 0;
> +}
> +
> +static int unicam_mc_enum_fmt_meta_cap(struct file *file, void *priv,
> + struct v4l2_fmtdesc *f)
> +{
> + struct unicam_node *node = video_drvdata(file);
> + int i, j;
> +
> + if (!is_metadata_node(node))
> + return -EINVAL;
Same comments as for video format enumeration.
> +
> + for (i = 0, j = 0; i < ARRAY_SIZE(formats); i++) {
> + if (f->mbus_code && formats[i].code != f->mbus_code)
> + continue;
> + if (!formats[i].metadata_fmt)
> + continue;
> +
> + if (formats[i].fourcc) {
> + if (j == f->index) {
> + f->pixelformat = formats[i].fourcc;
> + f->type = V4L2_BUF_TYPE_META_CAPTURE;
> + return 0;
> + }
> + j++;
> + }
> + }
> +
> + return -EINVAL;
> +}
> +
> +static int unicam_mc_g_fmt_meta_cap(struct file *file, void *priv,
> + struct v4l2_format *f)
> +{
> + struct unicam_node *node = video_drvdata(file);
> +
> + if (!is_metadata_node(node))
> + return -EINVAL;
Can this happen ? Same below.
> +
> + *f = node->v_fmt;
> +
> + return 0;
> +}
> +
> +static int unicam_mc_try_fmt_meta_cap(struct file *file, void *priv,
> + struct v4l2_format *f)
> +{
> + struct unicam_node *node = video_drvdata(file);
> +
> + if (!is_metadata_node(node))
> + return -EINVAL;
> +
> + f->fmt.meta.dataformat = V4L2_META_FMT_8;
> +
> + return 0;
> +}
> +
> +static int unicam_mc_s_fmt_meta_cap(struct file *file, void *priv,
> + struct v4l2_format *f)
> +{
> + struct unicam_node *node = video_drvdata(file);
> +
> + if (!is_metadata_node(node))
> + return -EINVAL;
> +
> + unicam_mc_try_fmt_meta_cap(file, priv, f);
> +
> + node->v_fmt = *f;
> +
> + return 0;
> +}
> +
> +static const struct v4l2_ioctl_ops unicam_mc_ioctl_ops = {
> + .vidioc_querycap = unicam_querycap,
> + .vidioc_enum_fmt_vid_cap = unicam_mc_enum_fmt_vid_cap,
> + .vidioc_g_fmt_vid_cap = unicam_mc_g_fmt_vid_cap,
> + .vidioc_try_fmt_vid_cap = unicam_mc_try_fmt_vid_cap,
> + .vidioc_s_fmt_vid_cap = unicam_mc_s_fmt_vid_cap,
> +
> + .vidioc_enum_fmt_meta_cap = unicam_mc_enum_fmt_meta_cap,
> + .vidioc_g_fmt_meta_cap = unicam_mc_g_fmt_meta_cap,
> + .vidioc_try_fmt_meta_cap = unicam_mc_try_fmt_meta_cap,
> + .vidioc_s_fmt_meta_cap = unicam_mc_s_fmt_meta_cap,
> +
> + .vidioc_enum_framesizes = unicam_mc_enum_framesizes,
> + .vidioc_reqbufs = vb2_ioctl_reqbufs,
> + .vidioc_create_bufs = vb2_ioctl_create_bufs,
> + .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
> + .vidioc_querybuf = vb2_ioctl_querybuf,
> + .vidioc_qbuf = vb2_ioctl_qbuf,
> + .vidioc_dqbuf = vb2_ioctl_dqbuf,
> + .vidioc_expbuf = vb2_ioctl_expbuf,
> + .vidioc_streamon = vb2_ioctl_streamon,
> + .vidioc_streamoff = vb2_ioctl_streamoff,
> +
> + .vidioc_log_status = unicam_log_status,
> + .vidioc_subscribe_event = unicam_subscribe_event,
> + .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
> +};
> +
> +static const struct media_entity_operations unicam_mc_entity_ops = {
> + .link_validate = v4l2_subdev_link_validate,
> + .has_route = v4l2_subdev_has_route,
> +};
I don't think this is needed for the video nodes.
> +
> +/* videobuf2 Operations */
> +
> +static int unicam_queue_setup(struct vb2_queue *vq,
> + unsigned int *nbuffers,
> + unsigned int *nplanes,
> + unsigned int sizes[],
> + struct device *alloc_devs[])
> +{
> + struct unicam_node *node = vb2_get_drv_priv(vq);
> + struct unicam_device *dev = node->dev;
> + unsigned int size = is_image_node(node) ?
> + node->v_fmt.fmt.pix.sizeimage :
> + node->v_fmt.fmt.meta.buffersize;
> +
> + if (vq->num_buffers + *nbuffers < 3)
> + *nbuffers = 3 - vq->num_buffers;
> +
> + if (*nplanes) {
> + if (sizes[0] < size) {
> + dev_err(dev->v4l2_dev.dev, "sizes[0] %i < size %u\n", sizes[0],
> + size);
This can be a debug message, let's not give a way to unprivileged
userspace to flood the kernel log.
> + return -EINVAL;
> + }
> + size = sizes[0];
> + }
> +
> + *nplanes = 1;
> + sizes[0] = size;
> +
> + return 0;
> +}
> +
> +static int unicam_buffer_prepare(struct vb2_buffer *vb)
> +{
> + struct unicam_node *node = vb2_get_drv_priv(vb->vb2_queue);
> + struct unicam_device *dev = node->dev;
> + struct unicam_buffer *buf = to_unicam_buffer(vb);
> + unsigned long size;
> +
> + if (WARN_ON(!node->fmt))
> + return -EINVAL;
> +
> + size = is_image_node(node) ? node->v_fmt.fmt.pix.sizeimage :
> + node->v_fmt.fmt.meta.buffersize;
> + if (vb2_plane_size(vb, 0) < size) {
> + dev_err(dev->v4l2_dev.dev, "data will not fit into plane (%lu < %lu)\n",
> + vb2_plane_size(vb, 0), size);
Debug message here too.
> + return -EINVAL;
> + }
> +
> + vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
> + return 0;
> +}
> +
> +static void unicam_buffer_queue(struct vb2_buffer *vb)
> +{
> + struct unicam_node *node = vb2_get_drv_priv(vb->vb2_queue);
> + struct unicam_buffer *buf = to_unicam_buffer(vb);
> + unsigned long flags;
> +
> + spin_lock_irqsave(&node->dma_queue_lock, flags);
Small optimization, as this is guaranteed to be called with interrupts
enabled, you can use the spin_lock_irq() variant.
> + list_add_tail(&buf->list, &node->dma_queue);
> + spin_unlock_irqrestore(&node->dma_queue_lock, flags);
> +}
> +
> +static void unicam_set_packing_config(struct unicam_device *dev)
> +{
> + u32 pack, unpack;
> + u32 val;
> +
> + if (dev->node[IMAGE_NODE].v_fmt.fmt.pix.pixelformat ==
> + dev->node[IMAGE_NODE].fmt->fourcc) {
> + unpack = UNICAM_PUM_NONE;
> + pack = UNICAM_PPM_NONE;
> + } else {
> + switch (dev->node[IMAGE_NODE].fmt->depth) {
> + case 8:
> + unpack = UNICAM_PUM_UNPACK8;
> + break;
> + case 10:
> + unpack = UNICAM_PUM_UNPACK10;
> + break;
> + case 12:
> + unpack = UNICAM_PUM_UNPACK12;
> + break;
> + case 14:
> + unpack = UNICAM_PUM_UNPACK14;
> + break;
> + case 16:
> + unpack = UNICAM_PUM_UNPACK16;
> + break;
> + default:
> + unpack = UNICAM_PUM_NONE;
> + break;
> + }
> +
> + /* Repacking is always to 16bpp */
> + pack = UNICAM_PPM_PACK16;
> + }
> +
> + val = 0;
> + set_field(&val, unpack, UNICAM_PUM_MASK);
> + set_field(&val, pack, UNICAM_PPM_MASK);
> + reg_write(dev, UNICAM_IPIPE, val);
> +}
> +
> +static void unicam_cfg_image_id(struct unicam_device *dev)
> +{
> + if (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {
> + /* CSI2 mode, hardcode VC 0 for now. */
> + reg_write(dev, UNICAM_IDI0,
> + (0 << 6) | dev->node[IMAGE_NODE].fmt->csi_dt);
> + } else {
> + /* CCP2 mode */
> + reg_write(dev, UNICAM_IDI0,
> + 0x80 | dev->node[IMAGE_NODE].fmt->csi_dt);
> + }
> +}
> +
> +static void unicam_enable_ed(struct unicam_device *dev)
> +{
> + u32 val = reg_read(dev, UNICAM_DCS);
> +
> + set_field(&val, 2, UNICAM_EDL_MASK);
> + /* Do not wrap at the end of the embedded data buffer */
> + set_field(&val, 0, UNICAM_DBOB);
> +
> + reg_write(dev, UNICAM_DCS, val);
> +}
> +
> +static void unicam_start_rx(struct unicam_device *dev, dma_addr_t *addr)
> +{
> + int line_int_freq = dev->node[IMAGE_NODE].v_fmt.fmt.pix.height >> 2;
> + unsigned int size, i;
> + u32 val;
> +
> + if (line_int_freq < 128)
> + line_int_freq = 128;
> +
> + /* Enable lane clocks */
> + val = 1;
> + for (i = 0; i < dev->active_data_lanes; i++)
> + val = val << 2 | 1;
> + clk_write(dev, val);
> +
> + /* Basic init */
> + reg_write(dev, UNICAM_CTRL, UNICAM_MEM);
> +
> + /* Enable analogue control, and leave in reset. */
> + val = UNICAM_AR;
> + set_field(&val, 7, UNICAM_CTATADJ_MASK);
> + set_field(&val, 7, UNICAM_PTATADJ_MASK);
> + reg_write(dev, UNICAM_ANA, val);
> + usleep_range(1000, 2000);
> +
> + /* Come out of reset */
> + reg_write_field(dev, UNICAM_ANA, 0, UNICAM_AR);
> +
> + /* Peripheral reset */
> + reg_write_field(dev, UNICAM_CTRL, 1, UNICAM_CPR);
> + reg_write_field(dev, UNICAM_CTRL, 0, UNICAM_CPR);
> +
> + reg_write_field(dev, UNICAM_CTRL, 0, UNICAM_CPE);
> +
> + /* Enable Rx control. */
> + val = reg_read(dev, UNICAM_CTRL);
> + if (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {
> + set_field(&val, UNICAM_CPM_CSI2, UNICAM_CPM_MASK);
> + set_field(&val, UNICAM_DCM_STROBE, UNICAM_DCM_MASK);
> + } else {
> + set_field(&val, UNICAM_CPM_CCP2, UNICAM_CPM_MASK);
> + set_field(&val, dev->bus_flags, UNICAM_DCM_MASK);
> + }
> + /* Packet framer timeout */
> + set_field(&val, 0xf, UNICAM_PFT_MASK);
> + set_field(&val, 128, UNICAM_OET_MASK);
> + reg_write(dev, UNICAM_CTRL, val);
> +
> + reg_write(dev, UNICAM_IHWIN, 0);
> + reg_write(dev, UNICAM_IVWIN, 0);
> +
> + /* AXI bus access QoS setup */
> + val = reg_read(dev, UNICAM_PRI);
> + set_field(&val, 0, UNICAM_BL_MASK);
> + set_field(&val, 0, UNICAM_BS_MASK);
> + set_field(&val, 0xe, UNICAM_PP_MASK);
> + set_field(&val, 8, UNICAM_NP_MASK);
> + set_field(&val, 2, UNICAM_PT_MASK);
> + set_field(&val, 1, UNICAM_PE);
> + reg_write(dev, UNICAM_PRI, val);
> +
> + reg_write_field(dev, UNICAM_ANA, 0, UNICAM_DDL);
> +
> + /* Always start in trigger frame capture mode (UNICAM_FCM set) */
> + val = UNICAM_FSIE | UNICAM_FEIE | UNICAM_FCM | UNICAM_IBOB;
> + set_field(&val, line_int_freq, UNICAM_LCIE_MASK);
> + reg_write(dev, UNICAM_ICTL, val);
> + reg_write(dev, UNICAM_STA, UNICAM_STA_MASK_ALL);
> + reg_write(dev, UNICAM_ISTA, UNICAM_ISTA_MASK_ALL);
> +
> + /* tclk_term_en */
> + reg_write_field(dev, UNICAM_CLT, 2, UNICAM_CLT1_MASK);
> + /* tclk_settle */
> + reg_write_field(dev, UNICAM_CLT, 6, UNICAM_CLT2_MASK);
> + /* td_term_en */
> + reg_write_field(dev, UNICAM_DLT, 2, UNICAM_DLT1_MASK);
> + /* ths_settle */
> + reg_write_field(dev, UNICAM_DLT, 6, UNICAM_DLT2_MASK);
> + /* trx_enable */
> + reg_write_field(dev, UNICAM_DLT, 0, UNICAM_DLT3_MASK);
> +
> + reg_write_field(dev, UNICAM_CTRL, 0, UNICAM_SOE);
> +
> + /* Packet compare setup - required to avoid missing frame ends */
> + val = 0;
> + set_field(&val, 1, UNICAM_PCE);
> + set_field(&val, 1, UNICAM_GI);
> + set_field(&val, 1, UNICAM_CPH);
> + set_field(&val, 0, UNICAM_PCVC_MASK);
> + set_field(&val, 1, UNICAM_PCDT_MASK);
> + reg_write(dev, UNICAM_CMP0, val);
> +
> + /* Enable clock lane and set up terminations */
> + val = 0;
> + if (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {
> + /* CSI2 */
> + set_field(&val, 1, UNICAM_CLE);
> + set_field(&val, 1, UNICAM_CLLPE);
> + if (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {
> + set_field(&val, 1, UNICAM_CLTRE);
> + set_field(&val, 1, UNICAM_CLHSE);
> + }
> + } else {
> + /* CCP2 */
> + set_field(&val, 1, UNICAM_CLE);
> + set_field(&val, 1, UNICAM_CLHSE);
> + set_field(&val, 1, UNICAM_CLTRE);
> + }
> + reg_write(dev, UNICAM_CLK, val);
> +
> + /*
> + * Enable required data lanes with appropriate terminations.
> + * The same value needs to be written to UNICAM_DATn registers for
> + * the active lanes, and 0 for inactive ones.
> + */
> + val = 0;
> + if (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {
> + /* CSI2 */
> + set_field(&val, 1, UNICAM_DLE);
> + set_field(&val, 1, UNICAM_DLLPE);
> + if (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {
> + set_field(&val, 1, UNICAM_DLTRE);
> + set_field(&val, 1, UNICAM_DLHSE);
> + }
> + } else {
> + /* CCP2 */
> + set_field(&val, 1, UNICAM_DLE);
> + set_field(&val, 1, UNICAM_DLHSE);
> + set_field(&val, 1, UNICAM_DLTRE);
> + }
> + reg_write(dev, UNICAM_DAT0, val);
> +
> + if (dev->active_data_lanes == 1)
> + val = 0;
> + reg_write(dev, UNICAM_DAT1, val);
> +
> + if (dev->max_data_lanes > 2) {
> + /*
> + * Registers UNICAM_DAT2 and UNICAM_DAT3 only valid if the
> + * instance supports more than 2 data lanes.
> + */
> + if (dev->active_data_lanes == 2)
> + val = 0;
> + reg_write(dev, UNICAM_DAT2, val);
> +
> + if (dev->active_data_lanes == 3)
> + val = 0;
> + reg_write(dev, UNICAM_DAT3, val);
> + }
> +
> + reg_write(dev, UNICAM_IBLS,
> + dev->node[IMAGE_NODE].v_fmt.fmt.pix.bytesperline);
> + size = dev->node[IMAGE_NODE].v_fmt.fmt.pix.sizeimage;
> + unicam_wr_dma_addr(dev, addr[IMAGE_NODE], size, IMAGE_NODE);
> + unicam_set_packing_config(dev);
> + unicam_cfg_image_id(dev);
> +
> + val = reg_read(dev, UNICAM_MISC);
> + set_field(&val, 1, UNICAM_FL0);
> + set_field(&val, 1, UNICAM_FL1);
> + reg_write(dev, UNICAM_MISC, val);
> +
> + if (dev->node[METADATA_NODE].streaming && dev->sensor_embedded_data) {
> + dev_dbg(dev->v4l2_dev.dev, "enable metadata dma\n");
> + size = dev->node[METADATA_NODE].v_fmt.fmt.meta.buffersize;
> + unicam_enable_ed(dev);
> + unicam_wr_dma_addr(dev, addr[METADATA_NODE], size, METADATA_NODE);
> + }
> +
> + /* Enable peripheral */
> + reg_write_field(dev, UNICAM_CTRL, 1, UNICAM_CPE);
> +
> + /* Load image pointers */
> + reg_write_field(dev, UNICAM_ICTL, 1, UNICAM_LIP_MASK);
> +
> + /* Load embedded data buffer pointers if needed */
> + if (dev->node[METADATA_NODE].streaming && dev->sensor_embedded_data)
> + reg_write_field(dev, UNICAM_DCS, 1, UNICAM_LDP);
> +
> + /*
> + * Enable trigger only for the first frame to
> + * sync correctly to the FS from the source.
> + */
> + reg_write_field(dev, UNICAM_ICTL, 1, UNICAM_TFC);
> +}
> +
> +static void unicam_disable(struct unicam_device *dev)
> +{
> + /* Analogue lane control disable */
> + reg_write_field(dev, UNICAM_ANA, 1, UNICAM_DDL);
> +
> + /* Stop the output engine */
> + reg_write_field(dev, UNICAM_CTRL, 1, UNICAM_SOE);
> +
> + /* Disable the data lanes. */
> + reg_write(dev, UNICAM_DAT0, 0);
> + reg_write(dev, UNICAM_DAT1, 0);
> +
> + if (dev->max_data_lanes > 2) {
> + reg_write(dev, UNICAM_DAT2, 0);
> + reg_write(dev, UNICAM_DAT3, 0);
> + }
> +
> + /* Peripheral reset */
> + reg_write_field(dev, UNICAM_CTRL, 1, UNICAM_CPR);
> + usleep_range(50, 100);
> + reg_write_field(dev, UNICAM_CTRL, 0, UNICAM_CPR);
> +
> + /* Disable peripheral */
> + reg_write_field(dev, UNICAM_CTRL, 0, UNICAM_CPE);
> +
> + /* Clear ED setup */
> + reg_write(dev, UNICAM_DCS, 0);
> +
> + /* Disable all lane clocks */
> + clk_write(dev, 0);
> +}
> +
> +static void unicam_return_buffers(struct unicam_node *node,
> + enum vb2_buffer_state state)
> +{
> + struct unicam_buffer *buf, *tmp;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&node->dma_queue_lock, flags);
Same here, spin_lock_irq() would do. But isn't this function meant to be
called with the hardware stopped ? Shouldn't it then be safe to drop the
spinlock completely ?
> + list_for_each_entry_safe(buf, tmp, &node->dma_queue, list) {
> + list_del(&buf->list);
> + vb2_buffer_done(&buf->vb.vb2_buf, state);
> + }
> +
> + if (node->cur_frm)
> + vb2_buffer_done(&node->cur_frm->vb.vb2_buf,
> + state);
> + if (node->next_frm && node->cur_frm != node->next_frm)
> + vb2_buffer_done(&node->next_frm->vb.vb2_buf,
> + state);
> +
> + node->cur_frm = NULL;
> + node->next_frm = NULL;
> + spin_unlock_irqrestore(&node->dma_queue_lock, flags);
> +}
> +
> +static int unicam_video_check_format(struct unicam_node *node)
> +{
> + const struct v4l2_mbus_framefmt *format;
> + struct media_pad *remote_pad;
> + struct v4l2_subdev_state *state;
> + int ret = 0;
> +
> + remote_pad = media_entity_remote_pad(&node->pad);
> + if (!remote_pad)
> + return -ENODEV;
This could be done in unicam_async_complete() and cached in the
unicam_device structure, the same way we cache the sensor subdev
pointer.
> +
> + state = v4l2_subdev_lock_active_state(node->dev->sensor);
That's not correct, the video node is connected to the subdev, not to
the sensor.
> +
> + format = v4l2_state_get_stream_format(state,
> + remote_pad->index, 0);
This holds on a single line.
> + if (!format) {
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + if (node->fmt->code != format->code ||
> + node->v_fmt.fmt.pix.height != format->height ||
> + node->v_fmt.fmt.pix.width != format->width ||
> + node->v_fmt.fmt.pix.field != format->field) {
A debug message that prints the configuration on both sides could be
useful for debugging here.
> + ret = -EPIPE;
> + goto out;
> + }
> +
> +out:
> + v4l2_subdev_unlock_state(state);
> +
> + return ret;
> +}
> +
> +static int unicam_start_streaming(struct vb2_queue *vq, unsigned int count)
> +{
> + struct unicam_node *node = vb2_get_drv_priv(vq);
> + struct unicam_device *dev = node->dev;
> + dma_addr_t buffer_addr[MAX_NODES] = { 0 };
> + struct unicam_buffer *buf;
> + unsigned long flags;
> + unsigned int i;
> + int ret;
> +
> + node->streaming = true;
Locking seems to be completely missing from the driver. I'll comment
more on that on v3, it will be easier after all the other cleanups.
> +
> + dev->sequence = 0;
> + ret = unicam_runtime_get(dev);
> + if (ret < 0) {
> + dev_dbg(dev->v4l2_dev.dev, "unicam_runtime_get failed\n");
This is really not supposed to happen, dev_err() is appropriate.
> + goto err_streaming;
> + }
> +
> + ret = media_pipeline_start(node->video_dev.entity.pads, &node->pipe);
> + if (ret < 0) {
> + dev_err(dev->v4l2_dev.dev, "Failed to start media pipeline: %d\n", ret);
dev_dbg() here too.
> + goto err_pm_put;
> + }
> +
> + dev->active_data_lanes = dev->max_data_lanes;
You need to get the number of data lanes from the sensor subdev and
validate it to ensure it doesn't exceed the maximum.
> +
> + unicam_video_check_format(node);
Where's the return value check ?
> +
> + dev_dbg(dev->v4l2_dev.dev, "Running with %u data lanes\n",
> + dev->active_data_lanes);
> +
> + ret = clk_set_min_rate(dev->vpu_clock, MIN_VPU_CLOCK_RATE);
> + if (ret) {
> + dev_err(dev->v4l2_dev.dev, "failed to set up VPU clock\n");
> + goto error_pipeline;
> + }
> +
> + ret = clk_prepare_enable(dev->vpu_clock);
> + if (ret) {
> + dev_err(dev->v4l2_dev.dev, "Failed to enable VPU clock: %d\n", ret);
> + goto error_pipeline;
> + }
> +
> + ret = clk_set_rate(dev->clock, 100 * 1000 * 1000);
> + if (ret) {
> + dev_err(dev->v4l2_dev.dev, "failed to set up CSI clock\n");
> + goto err_vpu_clock;
> + }
> +
> + ret = clk_prepare_enable(dev->clock);
> + if (ret) {
> + dev_err(dev->v4l2_dev.dev, "Failed to enable CSI clock: %d\n", ret);
> + goto err_vpu_clock;
> + }
> +
> + dev_dbg(dev->v4l2_dev.dev, "node %s\n", node->video_dev.name);
> +
> + spin_lock_irqsave(&node->dma_queue_lock, flags);
> + buf = list_first_entry(&node->dma_queue,
> + struct unicam_buffer, list);
This holds on a single line.
> + node->cur_frm = buf;
> + node->next_frm = buf;
> + list_del(&buf->list);
> + spin_unlock_irqrestore(&node->dma_queue_lock, flags);
> +
> + buffer_addr[i] =
> + vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
This too.
> +
> + unicam_start_rx(dev, buffer_addr);
> +
> + ret = v4l2_subdev_call(&dev->sd, video, s_stream, 1);
> + if (ret < 0) {
> + dev_err(dev->v4l2_dev.dev, "stream on failed in subdev\n");
> + goto err_disable_unicam;
> + }
Do I understand correctly that all this will run twice, once when
VIDIOC_STREAMON is called on the image node, and once when it's called
on the metadata node ? That doesn't seem right. The stop_streaming
function is affected similarly.
> +
> + dev->clocks_enabled = true;
> + return 0;
> +
> +err_disable_unicam:
> + unicam_disable(dev);
> + clk_disable_unprepare(dev->clock);
> +err_vpu_clock:
> + if (clk_set_min_rate(dev->vpu_clock, 0))
> + dev_err(dev->v4l2_dev.dev, "failed to reset the VPU clock\n");
> + clk_disable_unprepare(dev->vpu_clock);
> +error_pipeline:
> + media_pipeline_stop(node->video_dev.entity.pads);
> +err_pm_put:
> + unicam_runtime_put(dev);
> +err_streaming:
> + unicam_return_buffers(node, VB2_BUF_STATE_QUEUED);
> + node->streaming = false;
> +
> + return ret;
> +}
> +
> +static void unicam_stop_streaming(struct vb2_queue *vq)
> +{
> + struct unicam_node *node = vb2_get_drv_priv(vq);
> + struct unicam_device *dev = node->dev;
> +
> + node->streaming = false;
> + /*
> + * Stop streaming the sensor and disable the peripheral.
> + * We cannot continue streaming embedded data with the
> + * image pad disabled.
> + */
> + if (v4l2_subdev_call(&dev->sd, video, s_stream, 0) < 0)
> + dev_err(dev->v4l2_dev.dev, "stream off failed in subdev\n");
> +
> + unicam_disable(dev);
> +
> + media_pipeline_stop(node->video_dev.entity.pads);
> +
> + if (dev->clocks_enabled) {
.stop_streaming() can only be called after a successful
.start_streaming() call, so you can drop the clocks_enabled field.
> + if (clk_set_min_rate(dev->vpu_clock, 0))
> + dev_err(dev->v4l2_dev.dev, "failed to reset the VPU clock\n");
> + clk_disable_unprepare(dev->vpu_clock);
> + clk_disable_unprepare(dev->clock);
> + dev->clocks_enabled = false;
> + }
> + unicam_runtime_put(dev);
> +
> + if (is_metadata_node(node)) {
> + /*
> + * Allow the hardware to spin in the dummy buffer.
> + * This is only really needed if the embedded data pad is
> + * disabled before the image pad.
> + */
> + unicam_wr_dma_addr(dev, node->dummy_buf_dma_addr,
> + DUMMY_BUF_SIZE, METADATA_NODE);
> + }
> +
> + /* Clear all queued buffers for the node */
> + unicam_return_buffers(node, VB2_BUF_STATE_ERROR);
> +}
> +
> +static const struct vb2_ops unicam_video_qops = {
> + .wait_prepare = vb2_ops_wait_prepare,
> + .wait_finish = vb2_ops_wait_finish,
> + .queue_setup = unicam_queue_setup,
> + .buf_prepare = unicam_buffer_prepare,
> + .buf_queue = unicam_buffer_queue,
> + .start_streaming = unicam_start_streaming,
> + .stop_streaming = unicam_stop_streaming,
> +};
> +
> +/* unicam capture driver file operations */
> +static const struct v4l2_file_operations unicam_fops = {
> + .owner = THIS_MODULE,
> + .open = v4l2_fh_open,
> + .release = vb2_fop_release,
> + .poll = vb2_fop_poll,
> + .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
Drop the comment.
> + .mmap = vb2_fop_mmap,
> +};
> +
> +static int
> +unicam_async_bound(struct v4l2_async_notifier *notifier,
> + struct v4l2_subdev *subdev,
> + struct v4l2_async_subdev *asd)
> +{
> + struct unicam_device *unicam = to_unicam_device(notifier->v4l2_dev);
> +
> + if (unicam->sensor) {
> + dev_info(unicam->v4l2_dev.dev, "subdev %s (Already set!!)",
> + subdev->name);
> + return 0;
> + }
This can't happen as we register a single asd only.
> +
> + unicam->sensor = subdev;
> + dev_dbg(unicam->v4l2_dev.dev, "Using sensor %s for capture\n", subdev->name);
Line wrap.
> +
> + return 0;
> +}
> +
> +static void unicam_release(struct kref *kref)
> +{
> + struct unicam_device *unicam =
> + container_of(kref, struct unicam_device, kref);
> +
> + v4l2_ctrl_handler_free(&unicam->ctrl_handler);
> + media_device_cleanup(&unicam->mdev);
> +
> + if (unicam->sensor_state)
> + __v4l2_subdev_state_free(unicam->sensor_state);
> +
> + kfree(unicam);
> +}
> +
> +static void unicam_put(struct unicam_device *unicam)
> +{
> + kref_put(&unicam->kref, unicam_release);
> +}
> +
> +static void unicam_get(struct unicam_device *unicam)
> +{
> + kref_get(&unicam->kref);
> +}
> +
> +static void unicam_node_release(struct video_device *vdev)
> +{
> + struct unicam_node *node = video_get_drvdata(vdev);
> +
> + unicam_put(node->dev);
> +}
> +
> +static void unicam_mc_set_default_format(struct unicam_node *node)
> +{
> + dev_dbg(node->dev->v4l2_dev.dev, "Set default format for %s node\n",
node->dev->dev should do, no need to go through v4l2_dev here. But I'd
drop the message, I don't think it brings much value.
> + node->node_id == IMAGE_NODE ? "image" : "metadata");
> +
> + if (is_image_node(node)) {
> + struct v4l2_pix_format *pix_fmt = &node->v_fmt.fmt.pix;
> +
> + pix_fmt->width = 640;
> + pix_fmt->height = 480;
> + pix_fmt->field = V4L2_FIELD_NONE;
> + pix_fmt->colorspace = V4L2_COLORSPACE_SRGB;
> + pix_fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
> + pix_fmt->quantization = V4L2_QUANTIZATION_LIM_RANGE;
> + pix_fmt->xfer_func = V4L2_XFER_FUNC_SRGB;
> + pix_fmt->pixelformat = formats[0].fourcc;
> + unicam_calc_format_size_bpl(node->dev, &formats[0],
> + &node->v_fmt);
> + node->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
> +
> + node->fmt = &formats[0];
> + } else {
> + const struct unicam_fmt *fmt;
> +
> + /* Fix this node format as embedded data. */
> + fmt = find_format_by_code(MEDIA_BUS_FMT_METADATA_8);
> + node->v_fmt.fmt.meta.dataformat = fmt->fourcc;
> + node->fmt = fmt;
Move this to the end to group all v_fmt initialization together.
> + node->v_fmt.fmt.meta.buffersize = UNICAM_EMBEDDED_SIZE;
> + node->embedded_lines = 1;
This belongs to the called.
> + node->v_fmt.type = V4L2_BUF_TYPE_META_CAPTURE;
> + }
> +}
> +
> +static int register_node(struct unicam_device *unicam, struct unicam_node *node,
> + enum v4l2_buf_type type)
Replace the type parameter with a enum unicam_node_type, that will look
cleaner in
> +{
> + struct video_device *vdev;
> + struct vb2_queue *q;
> + int ret;
> +
> + node->dev = unicam;
> + node->node_id = type == V4L2_BUF_TYPE_VIDEO_CAPTURE ?
> + IMAGE_NODE :
> + METADATA_NODE;
> +
> + spin_lock_init(&node->dma_queue_lock);
> + mutex_init(&node->lock);
> +
> + vdev = &node->video_dev;
> + /*
> + * If the sensor subdevice has any controls, associate the node
> + * with the ctrl handler to allow access from userland.
> + */
> + if (!list_empty(&unicam->ctrl_handler.ctrls))
> + vdev->ctrl_handler = &unicam->ctrl_handler;
Drop this, and move the vdev assignment below, just before it gets used.
/* Initialize the videobuf2 queue. */
> +
> + q = &node->buffer_queue;
> + q->type = type;
> + q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
Drop VB2_READ, that shouldn't be used.
> + q->drv_priv = node;
> + q->ops = &unicam_video_qops;
> + q->mem_ops = &vb2_dma_contig_memops;
> + q->buf_struct_size = sizeof(struct unicam_buffer);
> + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
> + q->lock = &node->lock;
> + q->min_buffers_needed = 1;
> + q->dev = &unicam->pdev->dev;
> +
> + ret = vb2_queue_init(q);
> + if (ret) {
> + dev_err(unicam->v4l2_dev.dev, "vb2_queue_init() failed\n");
> + return ret;
> + }
> +
> + INIT_LIST_HEAD(&node->dma_queue);
Move this to the beginning of the function with the rest of the node
initialization.
/* Initialize the video device. */
> +
> + vdev->release = unicam_node_release;
> + vdev->fops = &unicam_fops;
> + vdev->ioctl_ops = &unicam_mc_ioctl_ops;
> + vdev->v4l2_dev = &unicam->v4l2_dev;
> + vdev->vfl_dir = VFL_DIR_RX;
> + vdev->queue = q;
> + vdev->lock = &node->lock;
> + vdev->device_caps = (type == V4L2_BUF_TYPE_VIDEO_CAPTURE) ?
No need for parentheses.
> + V4L2_CAP_VIDEO_CAPTURE : V4L2_CAP_META_CAPTURE;
> + vdev->device_caps |= V4L2_CAP_READWRITE | V4L2_CAP_STREAMING | V4L2_CAP_IO_MC;
Drop V4L2_CAP_READWRITE.
> + vdev->entity.ops = &unicam_mc_entity_ops;
> +
> + /* Define the device names */
> + snprintf(vdev->name, sizeof(vdev->name), "%s-%s", UNICAM_MODULE_NAME,
> + type == V4L2_BUF_TYPE_VIDEO_CAPTURE ? "image" : "embedded");
> +
> + video_set_drvdata(vdev, node);
> + if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
> + vdev->entity.flags |= MEDIA_ENT_FL_DEFAULT;
> + node->pad.flags = MEDIA_PAD_FL_SINK;
> + media_entity_pads_init(&vdev->entity, 1, &node->pad);
Error check.
> +
> + node->dummy_buf_cpu_addr = dma_alloc_coherent(&unicam->pdev->dev,
> + DUMMY_BUF_SIZE,
> + &node->dummy_buf_dma_addr,
> + GFP_KERNEL);
> + if (!node->dummy_buf_cpu_addr) {
> + dev_err(unicam->v4l2_dev.dev, "Unable to allocate dummy buffer.\n");
> + return -ENOMEM;
> + }
> +
> + ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
> + if (ret) {
> + dev_err(unicam->v4l2_dev.dev, "Unable to register video device %s\n",
> + vdev->name);
> + return ret;
> + }
> +
> + /*
> + * Acquire a reference to unicam, which will be released when the video
> + * device will be unregistered and userspace will have closed all open
> + * file handles.
> + */
> + unicam_get(unicam);
This is error-prone. References should be acquired when stored, so this
should be moved to the beginning of the function, and written as
node->dev = unicam_get(unicam);
(you'll need to modify the function prototype to return the pointer).
You can then drop the comment. You will also to add error handling to
this function, as the reference will be released by
unicam_node_release(), which is called only after successful
registration of the video device. All error paths before registration
will thus need to release the reference (possibly with a goto
err_unicam_put)..
> + node->registered = true;
> +
> + ret = media_create_pad_link(&unicam->sd.entity,
> + node->src_pad_id,
unicam->sd is the unicam sd, node->src_pad_id is documented as being the
source pad of the sensor. This is wrong.
> + &node->video_dev.entity,
> + 0,
> + MEDIA_LNK_FL_ENABLED |
> + MEDIA_LNK_FL_IMMUTABLE);
> + if (ret)
> + dev_err(unicam->v4l2_dev.dev, "Unable to create pad link for %s",
> + unicam->sensor->name);
return ret;
}
> +
> + unicam_mc_set_default_format(node);
Call this before registering the video device, otherwise it can race
with userspace.
> +
> + return ret;
return 0;
> +}
> +
> +static void unregister_nodes(struct unicam_device *unicam)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < ARRAY_SIZE(unicam->node); i++) {
> + struct unicam_node *node = &unicam->node[i];
> +
> + if (node->dummy_buf_cpu_addr) {
> + dma_free_coherent(&unicam->pdev->dev, DUMMY_BUF_SIZE,
> + node->dummy_buf_cpu_addr,
> + node->dummy_buf_dma_addr);
> + }
No need for curly braces.
> +
> + if (node->registered) {
> + node->registered = false;
> + video_unregister_device(&node->video_dev);
Swap the two lines.
> + }
> + }
> +}
> +
> +static int unicam_async_complete(struct v4l2_async_notifier *notifier)
> +{
> + struct unicam_device *unicam = to_unicam_device(notifier->v4l2_dev);
> + unsigned int i, source_pads = 0;
> + int ret;
> + static struct lock_class_key key;
> +
> + unicam->v4l2_dev.notify = unicam_notify;
> +
> + unicam->sensor_state = __v4l2_subdev_state_alloc(unicam->sensor,
> + "unicam:state->lock",
> + &key);
You never use sensor_state.
> + if (!unicam->sensor_state)
> + return -ENOMEM;
> +
> + for (i = 0; i < unicam->sd.entity.num_pads; i++) {
> + if (unicam->sd.entity.pads[i].flags & MEDIA_PAD_FL_SOURCE) {
> + if (source_pads < MAX_NODES) {
> + unicam->node[source_pads].src_pad_id = i;
> + dev_dbg(unicam->v4l2_dev.dev, "source pad %u is index %u\n",
> + source_pads, i);
> + }
> + source_pads++;
> + }
> + }
> + if (!source_pads) {
> + dev_err(unicam->v4l2_dev.dev, "No source pads on sensor.\n");
> + goto unregister;
> + }
You're not looking at the sensor here, unicam->sd is the unicam subdev.
Furthermore, you're hardcoding the source pad of the sensor to 0 below
when creating the link. And in any case, that's not how it's supposed to
be done, a source subdev could have multiple source pads, you need to
identify the correct one from the device tree.
The right way to handle this is to replace the call to
media_create_pad_link() with v4l2_create_fwnode_links_to_pad(). This can
be done in the .bound() handler.
> +
> + ret = register_node(unicam, &unicam->node[IMAGE_NODE],
> + V4L2_BUF_TYPE_VIDEO_CAPTURE);
Replace the type parameter with a enum unicam_node_type, so this will
become
ret = register_node(unicam, &unicam->node[IMAGE_NODE], IMAGE_NODE);
which is less error-prone. You could even drop the second parameters:
ret = register_node(unicam, IMAGE_NODE);
> + if (ret) {
> + dev_err(unicam->v4l2_dev.dev, "Unable to register image video device.\n");
> + goto unregister;
> + }
> +
> + /* \todo: check before :-) */
> + unicam->sensor_embedded_data = true;
Check what ? In any case I don't think this belongs here.
> +
> + ret = register_node(unicam, &unicam->node[METADATA_NODE],
> + V4L2_BUF_TYPE_META_CAPTURE);
> + if (ret) {
> + dev_err(unicam->v4l2_dev.dev, "Unable to register metadata video device.\n");
> + goto unregister;
> + }
> +
> + ret = media_create_pad_link(&unicam->sensor->entity,
> + 0,
> + &unicam->sd.entity,
> + UNICAM_SD_PAD_SINK,
> + MEDIA_LNK_FL_ENABLED |
> + MEDIA_LNK_FL_IMMUTABLE);
> + if (ret)
> + dev_err(unicam->v4l2_dev.dev, "Unable to create pad link for %s",
> + unicam->sensor->name);
> +
> + ret = v4l2_device_register_subdev_nodes(&unicam->v4l2_dev);
> + if (ret) {
> + dev_err(unicam->v4l2_dev.dev, "Unable to register subdev nodes.\n");
> + goto unregister;
> + }
> +
> + /*
> + * Release the initial reference, all references are now owned by the
> + * video devices.
> + */
> + unicam_put(unicam);
> + return 0;
> +
> +unregister:
> + unregister_nodes(unicam);
> + unicam_put(unicam);
> +
> + return ret;
> +}
> +
> +static const struct v4l2_async_notifier_operations unicam_async_ops = {
> + .bound = unicam_async_bound,
> + .complete = unicam_async_complete,
> +};
> +
> +static int of_unicam_connect_subdevs(struct unicam_device *dev)
> +{
> + struct platform_device *pdev = dev->pdev;
> + struct v4l2_fwnode_endpoint ep = { };
> + struct device_node *ep_node;
> + struct device_node *sensor_node;
> + unsigned int lane;
> + int ret = -EINVAL;
> +
> + if (of_property_read_u32(pdev->dev.of_node, "num-data-lanes",
> + &dev->max_data_lanes) < 0) {
> + dev_err(dev->v4l2_dev.dev, "number of data lanes not set\n");
> + return -EINVAL;
> + }
> +
> + /* Get the local endpoint and remote device. */
> + ep_node = of_graph_get_next_endpoint(pdev->dev.of_node, NULL);
Use of_graph_get_endpoint_by_regs(node, 0, -1).
> + if (!ep_node) {
> + dev_dbg(dev->v4l2_dev.dev, "can't get next endpoint\n");
dev_dbg(dev->v4l2_dev.dev, "No endpoint\n");
> + return -EINVAL;
> + }
> +
> + dev_dbg(dev->v4l2_dev.dev, "ep_node is %pOF\n", ep_node);
You can drop this.
> +
> + sensor_node = of_graph_get_remote_port_parent(ep_node);
> + if (!sensor_node) {
> + dev_dbg(dev->v4l2_dev.dev, "can't get remote parent\n");
> + goto cleanup_exit;
> + }
> +
> + dev_dbg(dev->v4l2_dev.dev, "found subdevice %pOF\n", sensor_node);
There's no subdev yet, we're dealing with DT here.
dev_dbg(dev->v4l2_dev.dev, "found source device %pOF\n", sensor_node);
But I would actually drop all this. The sensor_node is only used in
debug or error messages, so you could remove it and use ep_node in those
messages instead. Or even better, drop the "subdevice %pOF: " prefix in
the messages, that will make the code simpler.
> +
> + /* Parse the local endpoint and validate its configuration. */
> + v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), &ep);
Use v4l2_fwnode_endpoint_alloc_parse() and check for errors (and update
the error cleanup path accordingly).
> +
> + dev_dbg(dev->v4l2_dev.dev, "parsed local endpoint, bus_type %u\n",
> + ep.bus_type);
> +
> + dev->bus_type = ep.bus_type;
> +
> + switch (ep.bus_type) {
> + case V4L2_MBUS_CSI2_DPHY:
> + switch (ep.bus.mipi_csi2.num_data_lanes) {
> + case 1:
> + case 2:
> + case 4:
> + break;
> +
> + default:
> + dev_err(dev->v4l2_dev.dev, "subdevice %pOF: %u data lanes not supported\n",
> + sensor_node,
> + ep.bus.mipi_csi2.num_data_lanes);
> + goto cleanup_exit;
> + }
> +
> + for (lane = 0; lane < ep.bus.mipi_csi2.num_data_lanes; lane++) {
> + if (ep.bus.mipi_csi2.data_lanes[lane] != lane + 1) {
> + dev_err(dev->v4l2_dev.dev, "subdevice %pOF: data lanes reordering not supported\n",
> + sensor_node);
> + goto cleanup_exit;
> + }
> + }
> +
> + if (ep.bus.mipi_csi2.num_data_lanes > dev->max_data_lanes) {
> + dev_err(dev->v4l2_dev.dev, "subdevice requires %u data lanes when %u are supported\n",
s/subdevice/endpoint/
> + ep.bus.mipi_csi2.num_data_lanes,
> + dev->max_data_lanes);
> + }
> +
> + dev->max_data_lanes = ep.bus.mipi_csi2.num_data_lanes;
> + dev->bus_flags = ep.bus.mipi_csi2.flags;
> +
> + break;
> +
> + case V4L2_MBUS_CCP2:
> + if (ep.bus.mipi_csi1.clock_lane != 0 ||
> + ep.bus.mipi_csi1.data_lane != 1) {
> + dev_err(dev->v4l2_dev.dev, "subdevice %pOF: unsupported lanes configuration\n",
> + sensor_node);
> + goto cleanup_exit;
> + }
> +
> + dev->max_data_lanes = 1;
> + dev->bus_flags = ep.bus.mipi_csi1.strobe;
> + break;
I wonder if this driver will ever be used with a CCP2 sensor.
> +
> + default:
> + /* Unsupported bus type */
> + dev_err(dev->v4l2_dev.dev, "subdevice %pOF: unsupported bus type %u\n",
> + sensor_node, ep.bus_type);
> + goto cleanup_exit;
> + }
> +
> + dev_dbg(dev->v4l2_dev.dev, "subdevice %pOF: %s bus, %u data lanes, flags=0x%08x\n",
> + sensor_node,
> + dev->bus_type == V4L2_MBUS_CSI2_DPHY ? "CSI-2" : "CCP2",
> + dev->max_data_lanes, dev->bus_flags);
> +
> + /* Initialize and register the async notifier. */
> + v4l2_async_nf_init(&dev->notifier);
> + dev->notifier.ops = &unicam_async_ops;
> +
> + dev->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
> + dev->asd.match.fwnode = fwnode_graph_get_remote_endpoint(of_fwnode_handle(ep_node));
> + ret = v4l2_async_nf_add_subdev(&dev->notifier, &dev->asd);
The asd must be dynamically allocated as stated by the documentation of
__v4l2_async_nf_add_subdev(). You can use
v4l2_async_nf_add_fwnode_remote() to simplify this.
> + if (ret) {
> + dev_err(dev->v4l2_dev.dev, "Error adding subdevice: %d\n", ret);
> + goto cleanup_exit;
> + }
> +
> + ret = v4l2_async_nf_register(&dev->v4l2_dev, &dev->notifier);
> + if (ret) {
> + dev_err(dev->v4l2_dev.dev, "Error registering async notifier: %d\n", ret);
> + ret = -EINVAL;
> + }
> +
> +cleanup_exit:
> + of_node_put(sensor_node);
> + of_node_put(ep_node);
> +
> + return ret;
> +}
> +
> +static int bcm2835_media_dev_init(struct unicam_device *unicam,
> + struct platform_device *pdev)
> +{
> + int ret = 0;
> +
> + unicam->mdev.dev = &pdev->dev;
> + strscpy(unicam->mdev.model, UNICAM_MODULE_NAME,
> + sizeof(unicam->mdev.model));
> + strscpy(unicam->mdev.serial, "", sizeof(unicam->mdev.serial));
> + snprintf(unicam->mdev.bus_info, sizeof(unicam->mdev.bus_info),
> + "platform:%s", dev_name(&pdev->dev));
> + unicam->mdev.hw_revision = 0;
> +
> + media_device_init(&unicam->mdev);
> +
> + unicam->v4l2_dev.mdev = &unicam->mdev;
> +
> + ret = v4l2_device_register(&pdev->dev, &unicam->v4l2_dev);
return v4l2_device_register(&pdev->dev, &unicam->v4l2_dev);
> +
> + return ret;
> +}
> +
> +/* Internal subdev */
> +
> +static int _unicam_subdev_set_routing(struct v4l2_subdev *sd,
__ is more conventional.
> + struct v4l2_subdev_state *state,
> + struct v4l2_subdev_krouting *routing)
> +{
> + static const struct v4l2_mbus_framefmt format = {
> + .width = 640,
> + .height = 480,
> + .code = MEDIA_BUS_FMT_UYVY8_2X8,
> + .field = V4L2_FIELD_NONE,
> + .colorspace = V4L2_COLORSPACE_SRGB,
> + .ycbcr_enc = V4L2_YCBCR_ENC_601,
> + .quantization = V4L2_QUANTIZATION_LIM_RANGE,
> + .xfer_func = V4L2_XFER_FUNC_SRGB,
> + .flags = 0,
> + };
As this should match the values in unicam_mc_set_default_format(), can
you move this structure out of the function, and use it to initialize
the pix_fmt fields in unicam_mc_set_default_format() ?
> + int ret;
> +
> + ret = v4l2_subdev_routing_validate_1_to_1(routing);
> + if (ret)
> + return ret;
> +
> + v4l2_subdev_lock_state(state);
> +
> + ret = v4l2_subdev_set_routing_with_fmt(sd, state, routing, &format);
> +
> + v4l2_subdev_unlock_state(state);
> +
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int unicam_subdev_set_routing(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state,
> + enum v4l2_subdev_format_whence which,
> + struct v4l2_subdev_krouting *routing)
> +{
> + struct unicam_device *unicam = sd_to_unicam_device(sd);
> +
> + if (which == V4L2_SUBDEV_FORMAT_ACTIVE && unicam->streaming)
> + return -EBUSY;
> +
> + return _unicam_subdev_set_routing(sd, state, routing);
> +}
> +
> +static int unicam_subdev_init_cfg(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state)
> +{
> + struct v4l2_subdev_route routes[] = {
> + {
> + .sink_pad = 0,
> + .sink_stream = 0,
> + .source_pad = 1,
You have macros you can use for the pad numbers.
> + .source_stream = 0,
> + .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE,
> + },
> + };
> +
> + struct v4l2_subdev_krouting routing = {
> + .num_routes = ARRAY_SIZE(routes),
> + .routes = routes,
> + };
> +
> + /* Initialize routing to single route to the fist source pad */
> + return _unicam_subdev_set_routing(sd, state, &routing);
> +}
> +
> +static int unicam_subdev_enum_mbus_code(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state,
> + struct v4l2_subdev_mbus_code_enum *code)
> +{
> + int ret = 0;
> +
> + v4l2_subdev_lock_state(state);
> +
> + /* No transcoding, source and sink codes must match. */
> + if (unicam_sd_pad_is_source(code->pad)) {
> + struct v4l2_mbus_framefmt *fmt;
> +
> + if (code->index > 0) {
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + fmt = v4l2_subdev_state_get_opposite_stream_format(state,
> + code->pad,
> + code->stream);
> + if (!fmt) {
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + code->code = fmt->code;
> + } else {
> + if (code->index >= ARRAY_SIZE(formats)) {
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + code->code = formats[code->index].code;
> + }
> +
> +out:
> + v4l2_subdev_unlock_state(state);
> +
> + return ret;
> +}
> +
> +static int unicam_subdev_start_streaming(struct unicam_device *unicam)
> +{
> + const struct v4l2_subdev_krouting *routing;
> + struct v4l2_subdev_state *state;
> + int ret = 0;
No need to initialize ret to 0.
> +
> + state = v4l2_subdev_lock_active_state(&unicam->sd);
> +
> + routing = &state->routing;
> +
> + v4l2_subdev_unlock_state(state);
As a piece of conceptual art, maybe, but as useful code, I have some
doubts.
> +
> + unicam->streaming = true;
> +
> + ret = v4l2_subdev_call(unicam->sensor, video, s_stream, 1);
> + if (ret) {
> + v4l2_subdev_call(unicam->sensor, video, s_stream, 0);
If .s_stream(1) fails, why do you need to call .s_stream(0) ?
> + unicam->streaming = false;
Drop this, and move the unicam->streaming = true line below.
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int unicam_subdev_stop_streaming(struct unicam_device *unicam)
> +{
> + v4l2_subdev_call(unicam->sensor, video, s_stream, 0);
> +
> + unicam->streaming = false;
> +
> + return 0;
> +}
> +
> +static int unicam_subdev_s_stream(struct v4l2_subdev *sd, int enable)
> +{
> + struct unicam_device *unicam = sd_to_unicam_device(sd);
> +
> + if (enable)
> + return unicam_subdev_start_streaming(unicam);
> + else
> + return unicam_subdev_stop_streaming(unicam);
> + return 0;
Drop the last line.
> +}
> +
> +static int unicam_subdev_set_pad_format(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state,
> + struct v4l2_subdev_format *format)
> +{
> + struct unicam_device *unicam = sd_to_unicam_device(sd);
> + struct v4l2_mbus_framefmt *fmt;
> + int ret = 0;
> +
> + if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE && unicam->streaming)
> + return -EBUSY;
> +
> + /* No transcoding, source and sink formats must match. */
> + if (unicam_sd_pad_is_source(format->pad))
> + return v4l2_subdev_get_fmt(sd, state, format);
> +
> + // TODO: implement fmt validation
That's a candidate for v3.
> +
> + v4l2_subdev_lock_state(state);
> +
> + fmt = v4l2_state_get_stream_format(state, format->pad, format->stream);
> + if (!fmt) {
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + *fmt = format->format;
> +
> + fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad,
> + format->stream);
> + if (!fmt) {
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + *fmt = format->format;
Let's avoid applying the format on one pad to then fail on the other
pad.
sink_format = v4l2_state_get_stream_format(state, format->pad,
format->stream);
source_format = v4l2_subdev_state_get_opposite_stream_format(state,
format->pad,
format->stream);
if (!sink_format || !source_format) {
ret = -EINVAL;
goto out;
}
*sink_format = format->format;
*source_format = format->format;
> +
> +out:
> + v4l2_subdev_unlock_state(state);
> +
> + return ret;
> +}
> +
> +static int unicam_subdev_enum_frame_size(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state,
> + struct v4l2_subdev_frame_size_enum *fse)
> +{
> + const struct unicam_fmt *fmtinfo;
> + int ret = 0;
> +
> + if (fse->index > 0)
> + return -EINVAL;
> +
> + v4l2_subdev_lock_state(state);
> +
> + /* No transcoding, source and sink formats must match. */
> + if (unicam_sd_pad_is_source(fse->pad)) {
> + struct v4l2_mbus_framefmt *fmt;
> +
> + fmt = v4l2_subdev_state_get_opposite_stream_format(state,
> + fse->pad,
> + fse->stream);
> +
You can drop this blank line.
> + if (!fmt) {
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + if (fse->code != fmt->code) {
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + fse->min_width = fmt->width;
> + fse->max_width = fmt->width;
> + fse->min_height = fmt->height;
> + fse->max_height = fmt->height;
> + } else {
> + fmtinfo = find_format_by_code(fse->code);
> + if (!fmtinfo) {
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + fse->min_width = MIN_WIDTH * 8 / ALIGN(fmtinfo->depth, 8);
> + fse->max_width = MAX_WIDTH * 8 / ALIGN(fmtinfo->depth, 8);
> + fse->min_height = MIN_HEIGHT;
> + fse->max_height = MAX_HEIGHT;
> + }
> +
> +out:
> + v4l2_subdev_unlock_state(state);
> +
> + return ret;
> +}
> +
> +static const struct v4l2_subdev_video_ops unicam_subdev_video_ops = {
> + .s_stream = unicam_subdev_s_stream,
> +};
> +
> +static const struct v4l2_subdev_pad_ops unicam_subdev_pad_ops = {
> + .init_cfg = unicam_subdev_init_cfg,
> + .enum_mbus_code = unicam_subdev_enum_mbus_code,
> + .get_fmt = v4l2_subdev_get_fmt,
> + .set_fmt = unicam_subdev_set_pad_format,
> + .set_routing = unicam_subdev_set_routing,
> + .enum_frame_size = unicam_subdev_enum_frame_size,
> +};
> +
> +static const struct v4l2_subdev_ops unicam_subdev_ops = {
> + .video = &unicam_subdev_video_ops,
> + .pad = &unicam_subdev_pad_ops,
> +};
> +
> +static struct media_entity_operations unicam_subdev_media_ops = {
static const
> + .link_validate = v4l2_subdev_link_validate,
> + .has_route = v4l2_subdev_has_route,
> +};
> +
> +static int unicam_probe(struct platform_device *pdev)
> +{
> + struct unicam_device *unicam;
> + int ret = 0;
> + int i;
> +
> + unicam = kzalloc(sizeof(*unicam), GFP_KERNEL);
> + if (!unicam)
> + return -ENOMEM;
> +
> + kref_init(&unicam->kref);
> + unicam->pdev = pdev;
> +
> + unicam->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(unicam->base)) {
> + dev_err(unicam->v4l2_dev.dev, "Failed to get main io block\n");
Let's use unicam->dev to access the struct device, especially given that
unicam->v4l2_dev is only initialized below when calling
bcm2835_media_dev_init().
This message can actually br dropped, devm_platform_ioremap_resource()
already prints an error.
> + ret = PTR_ERR(unicam->base);
> + goto err_unicam_put;
> + }
> +
> + unicam->clk_gate_base = devm_platform_ioremap_resource(pdev, 1);
> + if (IS_ERR(unicam->clk_gate_base)) {
> + dev_err(unicam->v4l2_dev.dev, "Failed to get 2nd io block\n");
Same here.
> + ret = PTR_ERR(unicam->clk_gate_base);
> + goto err_unicam_put;
> + }
> +
> + unicam->clock = devm_clk_get(&pdev->dev, "lp");
> + if (IS_ERR(unicam->clock)) {
> + dev_err(unicam->v4l2_dev.dev, "Failed to get lp clock\n");
> + ret = PTR_ERR(unicam->clock);
> + goto err_unicam_put;
> + }
> +
> + unicam->vpu_clock = devm_clk_get(&pdev->dev, "vpu");
> + if (IS_ERR(unicam->vpu_clock)) {
> + dev_err(unicam->v4l2_dev.dev, "Failed to get vpu clock\n");
> + ret = PTR_ERR(unicam->vpu_clock);
> + goto err_unicam_put;
> + }
Could the clock bulk API help here ?
> +
> + ret = platform_get_irq(pdev, 0);
> + if (ret <= 0) {
> + dev_err(&pdev->dev, "No IRQ resource\n");
> + ret = -EINVAL;
> + goto err_unicam_put;
> + }
> +
> + ret = devm_request_irq(&pdev->dev, ret, unicam_isr, 0,
> + "unicam_capture0", unicam);
> + if (ret) {
> + dev_err(&pdev->dev, "Unable to request interrupt\n");
> + ret = -EINVAL;
> + goto err_unicam_put;
> + }
> +
> + ret = bcm2835_media_dev_init(unicam, pdev);
> + if (ret) {
> + dev_err(unicam->v4l2_dev.dev,
> + "Unable to register v4l2 device.\n");
> + goto err_unicam_put;
> + }
> +
> + ret = media_device_register(&unicam->mdev);
> + if (ret < 0) {
> + dev_err(unicam->v4l2_dev.dev,
> + "Unable to register media-controller device.\n");
> + goto err_v4l2_unregister;
> + }
> +
> + /* Reserve space for the controls */
> + ret = v4l2_ctrl_handler_init(&unicam->ctrl_handler, 16);
> + if (ret < 0)
> + goto err_media_unregister;
The control handler is unused, drop it.
> +
> + /* set the driver data in platform device */
> + platform_set_drvdata(pdev, unicam);
> +
> + dev_dbg(unicam->v4l2_dev.dev, "Initialize internal subdev");
You can drop this.
> + v4l2_subdev_init(&unicam->sd, &unicam_subdev_ops);
> + v4l2_set_subdevdata(&unicam->sd, unicam);
> + unicam->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
> + unicam->sd.dev = &pdev->dev;
> + unicam->sd.owner = THIS_MODULE;
> + unicam->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_MULTIPLEXED;
> + snprintf(unicam->sd.name, sizeof(unicam->sd.name), "unicam-subdev");
> +
> + unicam->pads[UNICAM_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
> +
> + for (i = UNICAM_SD_PAD_FIRST_SOURCE; i < UNICAM_SD_NUM_PADS; ++i)
> + unicam->pads[i].flags = MEDIA_PAD_FL_SOURCE;
unicam->pads[UNICAM_SD_PAD_SOURCE_IMAGE].flags = MEDIA_PAD_FL_SOURCE;
unicam->pads[UNICAM_SD_PAD_SOURCE_META].flags = MEDIA_PAD_FL_SOURCE;
> + unicam->sd.entity.ops = &unicam_subdev_media_ops;
> + ret = media_entity_pads_init(&unicam->sd.entity,
> + ARRAY_SIZE(unicam->pads), unicam->pads);
> + if (ret) {
> + dev_err(unicam->v4l2_dev.dev, "Could not init media controller for subdev");
> + goto err_subdev_unregister;
> + }
> +
> + ret = v4l2_subdev_init_finalize(&unicam->sd);
> + if (ret) {
> + dev_err(unicam->v4l2_dev.dev, "Could not finalize init for subdev");
> + goto err_entity_cleanup;
> + }
> +
> + ret = v4l2_device_register_subdev(&unicam->v4l2_dev, &unicam->sd);
> + if (ret) {
> + dev_err(&pdev->dev, "Failed to register internal subdev\n");
> + goto err_subdev_unregister;
> + }
Let's split initialization and registration of the subdev to a separate
function, placed above with the subdev operations.
> +
> + ret = of_unicam_connect_subdevs(unicam);
> + if (ret) {
> + dev_err(&pdev->dev, "Failed to connect subdevs\n");
> + goto err_subdev_unregister;
> + }
> +
> + /* Enable the block power domain */
> + pm_runtime_enable(&pdev->dev);
> +
> + return 0;
> +
> +err_subdev_unregister:
> + v4l2_subdev_cleanup(&unicam->sd);
> +err_entity_cleanup:
> + media_entity_cleanup(&unicam->sd.entity);
> +err_media_unregister:
> + media_device_unregister(&unicam->mdev);
> +err_v4l2_unregister:
> + v4l2_device_unregister(&unicam->v4l2_dev);
> +err_unicam_put:
> + unicam_put(unicam);
> +
> + return ret;
> +}
> +
> +static int unicam_remove(struct platform_device *pdev)
> +{
> + struct unicam_device *unicam = platform_get_drvdata(pdev);
> +
> + v4l2_async_nf_unregister(&unicam->notifier);
> + v4l2_device_unregister(&unicam->v4l2_dev);
> + media_device_unregister(&unicam->mdev);
> + unregister_nodes(unicam);
I'm a bit worried there could be race conditions with userspace here.
For instance, calling v4l2_async_nf_unregister() will result in
v4l2_device_unregister_subdev() being called on the sensor subdev, which
may race with userspace starting capture on a video node. The following
order would, I think be safer:
unregister_nodes(unicam);
v4l2_device_unregister(&unicam->v4l2_dev);
media_device_unregister(&unicam->mdev);
v4l2_async_nf_unregister(&unicam->notifier);
But this will cause a problem, when unregistering device nodes, the last
reference to unicam would be dropped. I think you could drop the calls
to unicam_put() from unicam_async_complete(), and add a unicam_put()
call here. Dave, does that sound good to you ?
> +
> + pm_runtime_disable(&pdev->dev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id unicam_of_match[] = {
> + { .compatible = "brcm,bcm2835-unicam", },
> + { /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(of, unicam_of_match);
> +
> +static struct platform_driver unicam_driver = {
> + .probe = unicam_probe,
> + .remove = unicam_remove,
> + .driver = {
> + .name = UNICAM_MODULE_NAME,
> + .of_match_table = of_match_ptr(unicam_of_match),
> + },
> +};
> +
> +module_platform_driver(unicam_driver);
> +
> +MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com>");
> +MODULE_DESCRIPTION("BCM2835 Unicam driver");
> +MODULE_LICENSE("GPL");
> +MODULE_VERSION(UNICAM_VERSION);
> diff --git a/drivers/media/platform/bcm2835/vc4-regs-unicam.h b/drivers/media/platform/bcm2835/vc4-regs-unicam.h
> new file mode 100644
> index 000000000000..ae059a171d0f
> --- /dev/null
> +++ b/drivers/media/platform/bcm2835/vc4-regs-unicam.h
> @@ -0,0 +1,253 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +/*
> + * Copyright (C) 2017-2020 Raspberry Pi Trading.
> + * Dave Stevenson <dave.stevenson@raspberrypi.com>
> + */
> +
> +#ifndef VC4_REGS_UNICAM_H
> +#define VC4_REGS_UNICAM_H
> +
> +/*
> + * The following values are taken from files found within the code drop
> + * made by Broadcom for the BCM21553 Graphics Driver, predominantly in
> + * brcm_usrlib/dag/vmcsx/vcinclude/hardware_vc4.h.
> + * They have been modified to be only the register offset.
> + */
> +#define UNICAM_CTRL 0x000
> +#define UNICAM_STA 0x004
> +#define UNICAM_ANA 0x008
> +#define UNICAM_PRI 0x00c
> +#define UNICAM_CLK 0x010
> +#define UNICAM_CLT 0x014
> +#define UNICAM_DAT0 0x018
> +#define UNICAM_DAT1 0x01c
> +#define UNICAM_DAT2 0x020
> +#define UNICAM_DAT3 0x024
> +#define UNICAM_DLT 0x028
> +#define UNICAM_CMP0 0x02c
> +#define UNICAM_CMP1 0x030
> +#define UNICAM_CAP0 0x034
> +#define UNICAM_CAP1 0x038
> +#define UNICAM_ICTL 0x100
> +#define UNICAM_ISTA 0x104
> +#define UNICAM_IDI0 0x108
> +#define UNICAM_IPIPE 0x10c
> +#define UNICAM_IBSA0 0x110
> +#define UNICAM_IBEA0 0x114
> +#define UNICAM_IBLS 0x118
> +#define UNICAM_IBWP 0x11c
> +#define UNICAM_IHWIN 0x120
> +#define UNICAM_IHSTA 0x124
> +#define UNICAM_IVWIN 0x128
> +#define UNICAM_IVSTA 0x12c
> +#define UNICAM_ICC 0x130
> +#define UNICAM_ICS 0x134
> +#define UNICAM_IDC 0x138
> +#define UNICAM_IDPO 0x13c
> +#define UNICAM_IDCA 0x140
> +#define UNICAM_IDCD 0x144
> +#define UNICAM_IDS 0x148
> +#define UNICAM_DCS 0x200
> +#define UNICAM_DBSA0 0x204
> +#define UNICAM_DBEA0 0x208
> +#define UNICAM_DBWP 0x20c
> +#define UNICAM_DBCTL 0x300
> +#define UNICAM_IBSA1 0x304
> +#define UNICAM_IBEA1 0x308
> +#define UNICAM_IDI1 0x30c
> +#define UNICAM_DBSA1 0x310
> +#define UNICAM_DBEA1 0x314
> +#define UNICAM_MISC 0x400
Please add one tab before the value, to match the indentation of the
rest of the file.
> +
> +/*
> + * The following bitmasks are from the kernel released by Broadcom
> + * for Android - https://android.googlesource.com/kernel/bcm/
> + * The Rhea, Hawaii, and Java chips all contain the same VideoCore4
> + * Unicam block as BCM2835, as defined in eg
> + * arch/arm/mach-rhea/include/mach/rdb_A0/brcm_rdb_cam.h and similar.
> + * Values reworked to use the kernel BIT and GENMASK macros.
> + *
> + * Some of the bit mnenomics have been amended to match the datasheet.
> + */
> +/* UNICAM_CTRL Register */
> +#define UNICAM_CPE BIT(0)
> +#define UNICAM_MEM BIT(1)
> +#define UNICAM_CPR BIT(2)
> +#define UNICAM_CPM_MASK GENMASK(3, 3)
> +#define UNICAM_CPM_CSI2 0
> +#define UNICAM_CPM_CCP2 1
> +#define UNICAM_SOE BIT(4)
> +#define UNICAM_DCM_MASK GENMASK(5, 5)
> +#define UNICAM_DCM_STROBE 0
> +#define UNICAM_DCM_DATA 1
> +#define UNICAM_SLS BIT(6)
> +#define UNICAM_PFT_MASK GENMASK(11, 8)
> +#define UNICAM_OET_MASK GENMASK(20, 12)
> +
> +/* UNICAM_STA Register */
> +#define UNICAM_SYN BIT(0)
> +#define UNICAM_CS BIT(1)
> +#define UNICAM_SBE BIT(2)
> +#define UNICAM_PBE BIT(3)
> +#define UNICAM_HOE BIT(4)
> +#define UNICAM_PLE BIT(5)
> +#define UNICAM_SSC BIT(6)
> +#define UNICAM_CRCE BIT(7)
> +#define UNICAM_OES BIT(8)
> +#define UNICAM_IFO BIT(9)
> +#define UNICAM_OFO BIT(10)
> +#define UNICAM_BFO BIT(11)
> +#define UNICAM_DL BIT(12)
> +#define UNICAM_PS BIT(13)
> +#define UNICAM_IS BIT(14)
> +#define UNICAM_PI0 BIT(15)
> +#define UNICAM_PI1 BIT(16)
> +#define UNICAM_FSI_S BIT(17)
> +#define UNICAM_FEI_S BIT(18)
> +#define UNICAM_LCI_S BIT(19)
> +#define UNICAM_BUF0_RDY BIT(20)
> +#define UNICAM_BUF0_NO BIT(21)
> +#define UNICAM_BUF1_RDY BIT(22)
> +#define UNICAM_BUF1_NO BIT(23)
> +#define UNICAM_DI BIT(24)
> +
> +#define UNICAM_STA_MASK_ALL \
> + (UNICAM_DL + \
> + UNICAM_SBE + \
> + UNICAM_PBE + \
> + UNICAM_HOE + \
> + UNICAM_PLE + \
> + UNICAM_SSC + \
> + UNICAM_CRCE + \
> + UNICAM_IFO + \
> + UNICAM_OFO + \
> + UNICAM_PS + \
> + UNICAM_PI0 + \
> + UNICAM_PI1)
I'd use | instead of + to combine bits. Same below.
> +
> +/* UNICAM_ANA Register */
> +#define UNICAM_APD BIT(0)
> +#define UNICAM_BPD BIT(1)
> +#define UNICAM_AR BIT(2)
> +#define UNICAM_DDL BIT(3)
> +#define UNICAM_CTATADJ_MASK GENMASK(7, 4)
> +#define UNICAM_PTATADJ_MASK GENMASK(11, 8)
> +
> +/* UNICAM_PRI Register */
> +#define UNICAM_PE BIT(0)
> +#define UNICAM_PT_MASK GENMASK(2, 1)
> +#define UNICAM_NP_MASK GENMASK(7, 4)
> +#define UNICAM_PP_MASK GENMASK(11, 8)
> +#define UNICAM_BS_MASK GENMASK(15, 12)
> +#define UNICAM_BL_MASK GENMASK(17, 16)
> +
> +/* UNICAM_CLK Register */
> +#define UNICAM_CLE BIT(0)
> +#define UNICAM_CLPD BIT(1)
> +#define UNICAM_CLLPE BIT(2)
> +#define UNICAM_CLHSE BIT(3)
> +#define UNICAM_CLTRE BIT(4)
> +#define UNICAM_CLAC_MASK GENMASK(8, 5)
> +#define UNICAM_CLSTE BIT(29)
> +
> +/* UNICAM_CLT Register */
> +#define UNICAM_CLT1_MASK GENMASK(7, 0)
> +#define UNICAM_CLT2_MASK GENMASK(15, 8)
> +
> +/* UNICAM_DATn Registers */
> +#define UNICAM_DLE BIT(0)
> +#define UNICAM_DLPD BIT(1)
> +#define UNICAM_DLLPE BIT(2)
> +#define UNICAM_DLHSE BIT(3)
> +#define UNICAM_DLTRE BIT(4)
> +#define UNICAM_DLSM BIT(5)
> +#define UNICAM_DLFO BIT(28)
> +#define UNICAM_DLSTE BIT(29)
> +
> +#define UNICAM_DAT_MASK_ALL (UNICAM_DLSTE + UNICAM_DLFO)
This also needs an indentation fix, as well as UNICAM_ISTA_MASK_ALL.
> +
> +/* UNICAM_DLT Register */
> +#define UNICAM_DLT1_MASK GENMASK(7, 0)
> +#define UNICAM_DLT2_MASK GENMASK(15, 8)
> +#define UNICAM_DLT3_MASK GENMASK(23, 16)
> +
> +/* UNICAM_ICTL Register */
> +#define UNICAM_FSIE BIT(0)
> +#define UNICAM_FEIE BIT(1)
> +#define UNICAM_IBOB BIT(2)
> +#define UNICAM_FCM BIT(3)
> +#define UNICAM_TFC BIT(4)
> +#define UNICAM_LIP_MASK GENMASK(6, 5)
> +#define UNICAM_LCIE_MASK GENMASK(28, 16)
> +
> +/* UNICAM_IDI0/1 Register */
> +#define UNICAM_ID0_MASK GENMASK(7, 0)
> +#define UNICAM_ID1_MASK GENMASK(15, 8)
> +#define UNICAM_ID2_MASK GENMASK(23, 16)
> +#define UNICAM_ID3_MASK GENMASK(31, 24)
> +
> +/* UNICAM_ISTA Register */
> +#define UNICAM_FSI BIT(0)
> +#define UNICAM_FEI BIT(1)
> +#define UNICAM_LCI BIT(2)
> +
> +#define UNICAM_ISTA_MASK_ALL (UNICAM_FSI + UNICAM_FEI + UNICAM_LCI)
> +
> +/* UNICAM_IPIPE Register */
> +#define UNICAM_PUM_MASK GENMASK(2, 0)
> + /* Unpacking modes */
> + #define UNICAM_PUM_NONE 0
> + #define UNICAM_PUM_UNPACK6 1
> + #define UNICAM_PUM_UNPACK7 2
> + #define UNICAM_PUM_UNPACK8 3
> + #define UNICAM_PUM_UNPACK10 4
> + #define UNICAM_PUM_UNPACK12 5
> + #define UNICAM_PUM_UNPACK14 6
> + #define UNICAM_PUM_UNPACK16 7
> +#define UNICAM_DDM_MASK GENMASK(6, 3)
> +#define UNICAM_PPM_MASK GENMASK(9, 7)
> + /* Packing modes */
> + #define UNICAM_PPM_NONE 0
> + #define UNICAM_PPM_PACK8 1
> + #define UNICAM_PPM_PACK10 2
> + #define UNICAM_PPM_PACK12 3
> + #define UNICAM_PPM_PACK14 4
> + #define UNICAM_PPM_PACK16 5
I'd drop the leading tab.
> +#define UNICAM_DEM_MASK GENMASK(11, 10)
> +#define UNICAM_DEBL_MASK GENMASK(14, 12)
> +#define UNICAM_ICM_MASK GENMASK(16, 15)
> +#define UNICAM_IDM_MASK GENMASK(17, 17)
> +
> +/* UNICAM_ICC Register */
> +#define UNICAM_ICFL_MASK GENMASK(4, 0)
> +#define UNICAM_ICFH_MASK GENMASK(9, 5)
> +#define UNICAM_ICST_MASK GENMASK(12, 10)
> +#define UNICAM_ICLT_MASK GENMASK(15, 13)
> +#define UNICAM_ICLL_MASK GENMASK(31, 16)
> +
> +/* UNICAM_DCS Register */
> +#define UNICAM_DIE BIT(0)
> +#define UNICAM_DIM BIT(1)
> +#define UNICAM_DBOB BIT(3)
> +#define UNICAM_FDE BIT(4)
> +#define UNICAM_LDP BIT(5)
> +#define UNICAM_EDL_MASK GENMASK(15, 8)
> +
> +/* UNICAM_DBCTL Register */
> +#define UNICAM_DBEN BIT(0)
> +#define UNICAM_BUF0_IE BIT(1)
> +#define UNICAM_BUF1_IE BIT(2)
> +
> +/* UNICAM_CMP[0,1] register */
> +#define UNICAM_PCE BIT(31)
> +#define UNICAM_GI BIT(9)
> +#define UNICAM_CPH BIT(8)
> +#define UNICAM_PCVC_MASK GENMASK(7, 6)
> +#define UNICAM_PCDT_MASK GENMASK(5, 0)
> +
> +/* UNICAM_MISC register */
> +#define UNICAM_FL0 BIT(6)
> +#define UNICAM_FL1 BIT(9)
> +
> +#endif
--
Regards,
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH v2 1/4] dt-bindings: Add headers for Tegra234 I2C
From: Dmitry Osipenko @ 2022-01-22 18:35 UTC (permalink / raw)
To: Akhil R, devicetree, jonathanh, ldewangan, linux-i2c,
linux-kernel, linux-tegra, mperttunen, robh+dt, thierry.reding
In-Reply-To: <1642850607-20664-2-git-send-email-akhilrajeev@nvidia.com>
22.01.2022 14:23, Akhil R пишет:
> Add dt-bindings header files for I2C controllers for Tegra234
>
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> ---
> include/dt-bindings/clock/tegra234-clock.h | 19 +++++++++++++++++++
> include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++
> 2 files changed, 27 insertions(+)
>
> diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
> index 8d7e66e..5d05c19 100644
> --- a/include/dt-bindings/clock/tegra234-clock.h
> +++ b/include/dt-bindings/clock/tegra234-clock.h
> @@ -30,5 +30,24 @@
> #define TEGRA234_CLK_PLLC4 237U
> /** @brief 32K input clock provided by PMIC */
> #define TEGRA234_CLK_CLK_32K 289U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
> +#define TEGRA234_CLK_I2C1 48U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
> +#define TEGRA234_CLK_I2C2 49U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
> +#define TEGRA234_CLK_I2C3 50U
> +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
> +#define TEGRA234_CLK_I2C4 51U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
> +#define TEGRA234_CLK_I2C6 52U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
> +#define TEGRA234_CLK_I2C7 53U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
> +#define TEGRA234_CLK_I2C8 54U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
> +#define TEGRA234_CLK_I2C9 55U
> +
> +/** @brief PLLP clk output */
> +#define TEGRA234_CLK_PLLP_OUT0 102U
>
> #endif
> diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h
> index 50e13bc..e07e898 100644
> --- a/include/dt-bindings/reset/tegra234-reset.h
> +++ b/include/dt-bindings/reset/tegra234-reset.h
> @@ -12,6 +12,14 @@
> */
> #define TEGRA234_RESET_SDMMC4 85U
> #define TEGRA234_RESET_UARTA 100U
> +#define TEGRA234_RESET_I2C1 24U
> +#define TEGRA234_RESET_I2C2 29U
> +#define TEGRA234_RESET_I2C3 30U
> +#define TEGRA234_RESET_I2C4 31U
> +#define TEGRA234_RESET_I2C6 32U
> +#define TEGRA234_RESET_I2C7 33U
> +#define TEGRA234_RESET_I2C8 34U
> +#define TEGRA234_RESET_I2C9 35U
Why ID order isn't maintained?
^ permalink raw reply
* Re: [PATCH v16 2/4] dmaengine: tegra: Add tegra gpcdma driver
From: Dmitry Osipenko @ 2022-01-22 18:31 UTC (permalink / raw)
To: Akhil R, dan.j.williams@intel.com, devicetree@vger.kernel.org,
dmaengine@vger.kernel.org, Jonathan Hunter, Krishna Yarlagadda,
Laxman Dewangan, linux-kernel@vger.kernel.org,
linux-tegra@vger.kernel.org, p.zabel@pengutronix.de,
Rajesh Gumasta, robh+dt@kernel.org, thierry.reding@gmail.com,
vkoul@kernel.org
Cc: Pavan Kunapuli
In-Reply-To: <DM5PR12MB1850D67F9B5640943F1AEB2EC05B9@DM5PR12MB1850.namprd12.prod.outlook.com>
21.01.2022 19:24, Akhil R пишет:
>>>>>>> +static int tegra_dma_terminate_all(struct dma_chan *dc)
>>>>>>> +{
>>>>>>> + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
>>>>>>> + unsigned long flags;
>>>>>>> + LIST_HEAD(head);
>>>>>>> + int err;
>>>>>>> +
>>>>>>> + if (tdc->dma_desc) {
>>>>>>
>>>>>> Needs locking protection against racing with the interrupt handler.
>>>>> tegra_dma_stop_client() waits for the in-flight transfer
>>>>> to complete and prevents any additional transfer to start.
>>>>> Wouldn't it manage the race? Do you see any potential issue there?
>>>>
>>>> You should consider interrupt handler like a process running in a
>>>> parallel thread. The interrupt handler sets tdc->dma_desc to NULL, hence
>>>> you'll get NULL dereference in tegra_dma_stop_client().
>>>
>>> Is it better if I remove the below part from tegra_dma_stop_client() so
>>> that dma_desc is not accessed at all?
>>>
>>> + wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
>>> + tdc->dma_desc->bytes_transferred +=
>>> + tdc->dma_desc->bytes_requested - (wcount * 4);
>>>
>>> Because I don't see a point in updating the value there. dma_desc is set
>>> to NULL in the next step in terminate_all() anyway.
>>
>> That isn't going help you much because you also can't release DMA
>> descriptor while interrupt handler still may be running and using that
>> descriptor.
>
> Does the below functions look good to resolve the issue, provided
> tegra_dma_stop_client() doesn't access dma_desc?
Stop shall not race with the start.
> +static int tegra_dma_terminate_all(struct dma_chan *dc)
> +{
> + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
> + unsigned long flags;
> + LIST_HEAD(head);
> + int err;
> +
> + err = tegra_dma_stop_client(tdc);
> + if (err)
> + return err;
> +
> + tegra_dma_stop(tdc);
> +
> + spin_lock_irqsave(&tdc->vc.lock, flags);
> + tegra_dma_sid_free(tdc);
> + tdc->dma_desc = NULL;
> +
> + vchan_get_all_descriptors(&tdc->vc, &head);
> + spin_unlock_irqrestore(&tdc->vc.lock, flags);
> +
> + vchan_dma_desc_free_list(&tdc->vc, &head);
> +
> + return 0;
> +}
>
> +static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
> +{
> + struct tegra_dma_channel *tdc = dev_id;
> + struct tegra_dma_desc *dma_desc = tdc->dma_desc;
> + struct tegra_dma_sg_req *sg_req;
> + u32 status;
> +
> + /* Check channel error status register */
> + status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS);
> + if (status) {
> + tegra_dma_chan_decode_error(tdc, status);
> + tegra_dma_dump_chan_regs(tdc);
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF);
> + }
> +
> + status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
> + if (!(status & TEGRA_GPCDMA_STATUS_ISE_EOC))
> + return IRQ_HANDLED;
> +
> + tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS,
> + TEGRA_GPCDMA_STATUS_ISE_EOC);
> +
> + spin_lock(&tdc->vc.lock);
> + if (!dma_desc)
All checks and assignments must be done inside of critical section.
> + goto irq_done;
^ permalink raw reply
* [PATCH 2/4] clk: qcom: gcc-msm8998: add SSC-related clocks
From: michael.srba @ 2022-01-22 18:04 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Stephen Boyd,
Philipp Zabel
Cc: Linus Walleij, Florian Fainelli, Arnd Bergmann,
Greg Kroah-Hartman, Saravana Kannan, linux-arm-msm, devicetree,
Michael Srba
In-Reply-To: <20220122180413.1480-1-michael.srba@seznam.cz>
From: Michael Srba <Michael.Srba@seznam.cz>
This patch adds four clocks which need to be manipulated in order to
initialize the AHB bus which exposes the SCC block in the global address
space.
Care should be taken not to write to these registers unless the device is
known to be configured such that writing to these registers from Linux
is permitted.
Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
---
drivers/clk/qcom/gcc-msm8998.c | 56 ++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index 407e2c5caea4..2d14c3d672fc 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -2833,6 +2833,58 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = {
},
};
+static struct clk_branch gcc_im_sleep_clk = {
+ .halt_reg = 0x4300C,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4300C,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_im_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch aggre2_snoc_north_axi_clk = {
+ .halt_reg = 0x83010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x83010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "aggre2_snoc_north_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ssc_xo_clk = {
+ .halt_reg = 0x63018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x63018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "ssc_xo_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ssc_cnoc_ahbs_clk = {
+ .halt_reg = 0x6300C,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6300C,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "ssc_cnoc_ahbs_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.gds_hw_ctrl = 0x0,
@@ -3036,6 +3088,10 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
[GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
[HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
+ [GCC_IM_SLEEP] = &gcc_im_sleep_clk.clkr,
+ [AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr,
+ [SSC_XO] = &ssc_xo_clk.clkr,
+ [SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr,
};
static struct gdsc *gcc_msm8998_gdscs[] = {
--
2.34.1
^ permalink raw reply related
* [PATCH 3/4] dt-bindings: bus: add device tree bindings for qcom,ssc-block-bus
From: michael.srba @ 2022-01-22 18:04 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Stephen Boyd,
Philipp Zabel
Cc: Linus Walleij, Florian Fainelli, Arnd Bergmann,
Greg Kroah-Hartman, Saravana Kannan, linux-arm-msm, devicetree,
Michael Srba
In-Reply-To: <20220122180413.1480-1-michael.srba@seznam.cz>
From: Michael Srba <Michael.Srba@seznam.cz>
This patch adds bindings for the AHB bus which exposes the SCC block in
the global address space. This bus (and the SSC block itself) is present
on certain qcom SoCs.
In typical configuration, this bus (as some of the clocks and registers
that we need to manipulate) is not accessible to the OS, and the
resources on this bus are indirectly accessed by communicating with a
hexagon CPU core residing in the SSC block. In this configuration, the
hypervisor is the one performing the bus initialization for the purposes
of bringing the haxagon CPU core out of reset.
However, it is possible to change the configuration, in which case this
binding serves to allow the OS to initialize the bus.
Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
---
.../bindings/bus/qcom,ssc-block-bus.yaml | 156 ++++++++++++++++++
1 file changed, 156 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml
diff --git a/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml b/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml
new file mode 100644
index 000000000000..ff02b13618a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs
+
+maintainers:
+ - Michael Srba <Michael.Srba@seznam.cz>
+
+description: |
+ This binding describes the dependencies (clocks, resets, power domains) which
+ need to be turned on in a sequence before communication over the AHB bus
+ becomes possible.
+
+ Additionally, the reg property is used to pass to the driver the location of
+ two sadly undocumented registers which need to be poked as part of the sequence.
+
+ Currently, this binding is known to apply to msm8998. If the binding applies
+ in it's current form, the compatible should contain "qcom,ssc-block-bus-v1".
+ If the binding needs tweaking in order to apply to another SoC, this binding
+ shall be extended.
+
+
+properties:
+ compatible:
+ contains:
+ items:
+ - enum: [ qcom,ssc-block-bus-v1 ]
+ - const: qcom,ssc-block-bus
+ description:
+ Shall contain "qcom,ssc-block-bus"
+
+ reg:
+ description: |
+ Shall contain the addresses of the SSCAON_CONFIG0 and SSCAON_CONFIG1
+ registers
+ minItems: 2
+ maxItems: 2
+
+ reg-names:
+ minItems: 2
+ maxItems: 2
+ items:
+ - const: mpm_sscaon_config0
+ - const: mpm_sscaon_config1
+
+ '#address-cells':
+ enum: [ 1, 2 ]
+
+ '#size-cells':
+ enum: [ 1, 2 ]
+
+ ranges: true
+
+ clocks:
+ description: |
+ Clock phandles for the xo, aggre2, gcc_im_sleep, aggre2_north,
+ ssc_xo and ssc_ahbs clocks
+ minItems: 6
+ maxItems: 6
+
+ clock-names:
+ items:
+ - const: xo
+ - const: aggre2
+ - const: gcc_im_sleep
+ - const: aggre2_north
+ - const: ssc_xo
+ - const: ssc_ahbs
+
+ power-domains:
+ description: Power domain phandles for the ssc_cx and ssc_mx power domains
+ minItems: 2
+ maxItems: 2
+
+ power-domain-names:
+ items:
+ - const: ssc_cx
+ - const: ssc_mx
+
+ resets:
+ description: |
+ Reset phandles for the ssc_reset and ssc_bcr resets (note: ssc_bcr is the
+ branch control register associated with the ssc_xo and ssc_ahbs clocks)
+ minItems: 2
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: ssc_reset
+ - const: ssc_bcr
+
+ qcom,halt-regs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Phandle reference to a syscon representing TCSR followed by the
+ offset within syscon for the ssc AXI halt register.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - '#address-cells'
+ - '#size-cells'
+ - ranges
+ - clocks
+ - clock-names
+ - power-domains
+ - power-domain-names
+ - resets
+ - reset-names
+ - qcom,halt-regs
+
+additionalProperties: true
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8996.h>
+
+ &soc {
+ ssc_ahb_slave@0x10AC008 { // devices under this node are physically located in the SSC block, connected to an ssc-internal bus;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ compatible = "qcom,ssc-block-bus";
+ reg = <0x10AC008 0x4>, <0x10AC010 0x4>;
+ reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1";
+
+ clocks = <&xo>,
+ <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
+ <&gcc GCC_IM_SLEEP>,
+ <&gcc AGGRE2_SNOC_NORTH_AXI>,
+ <&gcc SSC_XO>,
+ <&gcc SSC_CNOC_AHBS_CLK>;
+ clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs";
+
+ resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>;
+ reset-names = "ssc_reset", "ssc_bcr";
+
+ power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>;
+ power-domain-names = "ssc_cx", "ssc_mx";
+
+ qcom,halt-regs = <&tcsr_mutex_regs 0x26000>;
+
+ ssc_tlmm: pinctrl@5e10000 {
+ compatible = "qcom,msm8998-ssc-tlmm-pinctrl";
+ reg = <0x5E10000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&ssc_tlmm 0 0 20>;
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related
* [PATCH 1/4] dt-bindings: clock: gcc-msm8998: Add definitions of SSC-related clocks
From: michael.srba @ 2022-01-22 18:04 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Stephen Boyd,
Philipp Zabel
Cc: Linus Walleij, Florian Fainelli, Arnd Bergmann,
Greg Kroah-Hartman, Saravana Kannan, linux-arm-msm, devicetree,
Michael Srba
From: Michael Srba <Michael.Srba@seznam.cz>
This patch adds definitions of four clocks which need to be manipulated
in order to initialize the AHB bus which exposes the SCC block in the
global address space.
Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
---
include/dt-bindings/clock/qcom,gcc-msm8998.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h
index 72c99e486d86..1badb4f9c58f 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8998.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h
@@ -186,6 +186,10 @@
#define UFS_UNIPRO_CORE_CLK_SRC 177
#define GCC_MMSS_GPLL0_CLK 178
#define HMSS_GPLL0_CLK_SRC 179
+#define GCC_IM_SLEEP 180
+#define AGGRE2_SNOC_NORTH_AXI 181
+#define SSC_XO 182
+#define SSC_CNOC_AHBS_CLK 183
#define PCIE_0_GDSC 0
#define UFS_GDSC 1
--
2.34.1
^ permalink raw reply related
* [PATCH 4/4] drivers: bus: add driver for initializing the SSC bus on (some) qcom SoCs
From: michael.srba @ 2022-01-22 18:04 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Stephen Boyd,
Philipp Zabel
Cc: Linus Walleij, Florian Fainelli, Arnd Bergmann,
Greg Kroah-Hartman, Saravana Kannan, linux-arm-msm, devicetree,
Michael Srba
In-Reply-To: <20220122180413.1480-1-michael.srba@seznam.cz>
From: Michael Srba <Michael.Srba@seznam.cz>
This patch adds bindings for the AHB bus which exposes the SCC block in
the global address space. This bus (and the SSC block itself) is present
on certain qcom SoCs.
In typical configuration, this bus (as some of the clocks and registers
that we need to manipulate) is not accessible to Linux, and the resources
on this bus are indirectly accessed by communicating with a hexagon CPU
core residing in the SSC block. In this configuration, the hypervisor is
the one performing the bus initialization for the purposes of bringing
the haxagon CPU core out of reset.
However, it is possible to change the configuration, in which case this
driver will initialize the bus.
In combination with drivers for resources on the SSC bus, this driver can
aid in debugging, and for example with a TLMM driver can be used to
directly access SSC-dedicated GPIO pins, removing the need to commit
to a particular usecase during hw design.
Finally, until open firmware for the hexagon core is available, this
approach allows for using sensors hooked up to SSC-dedicated GPIO pins
on mainline Linux simply by utilizing the existing in-tree drivers for
these sensors.
Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
---
drivers/bus/Kconfig | 6 +
drivers/bus/Makefile | 1 +
drivers/bus/qcom-ssc-block-bus.c | 365 +++++++++++++++++++++++++++++++
3 files changed, 372 insertions(+)
create mode 100644 drivers/bus/qcom-ssc-block-bus.c
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 3c68e174a113..f2b2e3098491 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -173,6 +173,12 @@ config SUNXI_RSB
with various RSB based devices, such as AXP223, AXP8XX PMICs,
and AC100/AC200 ICs.
+config QCOM_SSC_BLOCK_BUS
+ bool "Qualcomm SSC Block Bus Init Driver"
+ help
+ Say y here to enable support for initializing the bus that connects the SSC block's internal
+ bus to the cNoC on (some) qcom SoCs
+
config TEGRA_ACONNECT
tristate "Tegra ACONNECT Bus Driver"
depends on ARCH_TEGRA_210_SOC
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 52c2f35a26a9..e6756e83a9c4 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o
+obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o
obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o
obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o
obj-$(CONFIG_OF) += simple-pm-bus.o
diff --git a/drivers/bus/qcom-ssc-block-bus.c b/drivers/bus/qcom-ssc-block-bus.c
new file mode 100644
index 000000000000..a93c7350a231
--- /dev/null
+++ b/drivers/bus/qcom-ssc-block-bus.c
@@ -0,0 +1,365 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (c) 2021, Michael Srba
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+/* AXI Halt Register Offsets */
+#define AXI_HALTREQ_REG 0x0
+#define AXI_HALTACK_REG 0x4
+#define AXI_IDLE_REG 0x8
+
+static const char * const qcom_ssc_block_pd_names[] = {
+ "ssc_cx",
+ "ssc_mx"
+};
+
+struct qcom_ssc_block_bus_data {
+ int num_pds;
+ const char **pd_names;
+ struct device *pds[ARRAY_SIZE(qcom_ssc_block_pd_names)];
+ char __iomem *reg_mpm_sscaon_config0; // MPM - msm power manager; AON - always-on
+ char __iomem *reg_mpm_sscaon_config1; // that's as much as we know about these
+ struct regmap *halt_map;
+ u32 ssc_axi_halt;
+ struct clk *xo_clk;
+ struct clk *aggre2_clk;
+ struct clk *gcc_im_sleep_clk;
+ struct clk *aggre2_north_clk;
+ struct clk *ssc_xo_clk;
+ struct clk *ssc_ahbs_clk;
+ struct reset_control *ssc_bcr;
+ struct reset_control *ssc_reset;
+};
+
+static void reg32_set_bits(char __iomem *reg, u32 value)
+{
+ u32 tmp = ioread32(reg);
+
+ iowrite32(tmp | value, reg);
+}
+
+static void reg32_clear_bits(char __iomem *reg, u32 value)
+{
+ u32 tmp = ioread32(reg);
+
+ iowrite32(tmp & (~value), reg);
+}
+
+
+static int qcom_ssc_block_bus_init(struct device *dev)
+{
+ int ret;
+
+ struct qcom_ssc_block_bus_data *data = dev_get_drvdata(dev);
+
+ clk_prepare_enable(data->xo_clk);
+ clk_prepare_enable(data->aggre2_clk);
+
+ clk_prepare_enable(data->gcc_im_sleep_clk);
+
+ reg32_clear_bits(data->reg_mpm_sscaon_config0, BIT(4) | BIT(5));
+ reg32_clear_bits(data->reg_mpm_sscaon_config1, BIT(31));
+
+ clk_disable(data->aggre2_north_clk);
+
+ ret = reset_control_deassert(data->ssc_reset);
+ if (ret) {
+ dev_err(dev, "error deasserting ssc_reset: %d\n", ret);
+ return ret;
+ }
+
+ clk_prepare_enable(data->aggre2_north_clk);
+
+ ret = reset_control_deassert(data->ssc_bcr);
+ if (ret) {
+ dev_err(dev, "error deasserting ssc_bcr: %d\n", ret);
+ return ret;
+ }
+
+ regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 0);
+
+ clk_prepare_enable(data->ssc_xo_clk);
+
+ clk_prepare_enable(data->ssc_ahbs_clk);
+
+ return 0;
+}
+
+static int qcom_ssc_block_bus_deinit(struct device *dev)
+{
+ int ret;
+
+ struct qcom_ssc_block_bus_data *data = dev_get_drvdata(dev);
+
+ clk_disable(data->ssc_xo_clk);
+ clk_disable(data->ssc_ahbs_clk);
+
+ ret = reset_control_assert(data->ssc_bcr);
+ if (ret) {
+ dev_err(dev, "error asserting ssc_bcr: %d\n", ret);
+ return ret;
+ }
+
+ regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 1);
+
+ reg32_set_bits(data->reg_mpm_sscaon_config1, BIT(31));
+ reg32_set_bits(data->reg_mpm_sscaon_config0, BIT(4) | BIT(5));
+
+ ret = reset_control_assert(data->ssc_reset);
+ if (ret) {
+ dev_err(dev, "error asserting ssc_reset: %d\n", ret);
+ return ret;
+ }
+
+ clk_disable(data->gcc_im_sleep_clk);
+
+ clk_disable(data->aggre2_north_clk);
+
+ clk_disable(data->aggre2_clk);
+ clk_disable(data->xo_clk);
+
+ return 0;
+}
+
+
+static int qcom_ssc_block_bus_pds_attach(struct device *dev, struct device **pds,
+ const char **pd_names, size_t num_pds)
+{
+ int ret;
+ int i;
+
+ for (i = 0; i < num_pds; i++) {
+ pds[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
+ if (IS_ERR_OR_NULL(pds[i])) {
+ ret = PTR_ERR(pds[i]) ? : -ENODATA;
+ goto unroll_attach;
+ }
+ }
+
+ return num_pds;
+
+unroll_attach:
+ for (i--; i >= 0; i--)
+ dev_pm_domain_detach(pds[i], false);
+
+ return ret;
+};
+
+static void qcom_ssc_block_bus_pds_detach(struct device *dev, struct device **pds, size_t num_pds)
+{
+ int i;
+
+ for (i = 0; i < num_pds; i++)
+ dev_pm_domain_detach(pds[i], false);
+}
+
+static int qcom_ssc_block_bus_pds_enable(struct device **pds, size_t num_pds)
+{
+ int ret;
+ int i;
+
+ for (i = 0; i < num_pds; i++) {
+ dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
+ ret = pm_runtime_get_sync(pds[i]);
+ if (ret < 0)
+ goto unroll_pd_votes;
+ }
+
+ return 0;
+
+unroll_pd_votes:
+ for (i--; i >= 0; i--) {
+ dev_pm_genpd_set_performance_state(pds[i], 0);
+ pm_runtime_put(pds[i]);
+ }
+
+ return ret;
+};
+
+static void qcom_ssc_block_bus_pds_disable(struct device **pds, size_t num_pds)
+{
+ int i;
+
+ for (i = 0; i < num_pds; i++) {
+ dev_pm_genpd_set_performance_state(pds[i], 0);
+ pm_runtime_put(pds[i]);
+ }
+}
+
+static int qcom_ssc_block_bus_probe(struct platform_device *pdev)
+{
+ struct qcom_ssc_block_bus_data *data;
+ struct device_node *np = pdev->dev.of_node;
+ struct of_phandle_args halt_args;
+ struct resource *res;
+ int ret;
+
+ if (np)
+ of_platform_populate(np, NULL, NULL, &pdev->dev);
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, data);
+
+ data->pd_names = qcom_ssc_block_pd_names;
+ data->num_pds = ARRAY_SIZE(qcom_ssc_block_pd_names);
+
+ ret = qcom_ssc_block_bus_pds_attach(&pdev->dev, data->pds, data->pd_names, data->num_pds);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "error when attaching power domains: %d\n", ret);
+ return ret;
+ }
+
+ ret = qcom_ssc_block_bus_pds_enable(data->pds, data->num_pds);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "error when enabling power domains: %d\n", ret);
+ return ret;
+ }
+
+ // the meaning of the bits in these two registers is sadly not documented,
+ // the set/clear operations are just copying what qcom does
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpm_sscaon_config0");
+ data->reg_mpm_sscaon_config0 = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(data->reg_mpm_sscaon_config0)) {
+ ret = PTR_ERR(data->reg_mpm_sscaon_config0);
+ dev_err(&pdev->dev, "failed to ioremap mpm_sscaon_config0 (err: %d)\n", ret);
+ return ret;
+ }
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpm_sscaon_config0");
+ data->reg_mpm_sscaon_config1 = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(data->reg_mpm_sscaon_config1)) {
+ ret = PTR_ERR(data->reg_mpm_sscaon_config1);
+ dev_err(&pdev->dev, "failed to ioremap mpm_sscaon_config1 (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->ssc_bcr = devm_reset_control_get_exclusive(&pdev->dev, "ssc_bcr");
+ if (IS_ERR(data->ssc_bcr)) {
+ ret = PTR_ERR(data->ssc_bcr);
+ dev_err(&pdev->dev, "failed to acquire reset: scc_bcr (err: %d)\n", ret);
+ return ret;
+ }
+ data->ssc_reset = devm_reset_control_get_exclusive(&pdev->dev, "ssc_reset");
+ if (IS_ERR(data->ssc_reset)) {
+ ret = PTR_ERR(data->ssc_reset);
+ dev_err(&pdev->dev, "failed to acquire reset: ssc_reset: (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->xo_clk = devm_clk_get(&pdev->dev, "xo");
+ if (IS_ERR(data->xo_clk)) {
+ ret = PTR_ERR(data->xo_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: xo (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->aggre2_clk = devm_clk_get(&pdev->dev, "aggre2");
+ if (IS_ERR(data->aggre2_clk)) {
+ ret = PTR_ERR(data->aggre2_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: aggre2 (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->gcc_im_sleep_clk = devm_clk_get(&pdev->dev, "gcc_im_sleep");
+ if (IS_ERR(data->gcc_im_sleep_clk)) {
+ ret = PTR_ERR(data->gcc_im_sleep_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: gcc_im_sleep (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->aggre2_north_clk = devm_clk_get(&pdev->dev, "aggre2_north");
+ if (IS_ERR(data->aggre2_north_clk)) {
+ ret = PTR_ERR(data->aggre2_north_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: aggre2_north (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->ssc_xo_clk = devm_clk_get(&pdev->dev, "ssc_xo");
+ if (IS_ERR(data->ssc_xo_clk)) {
+ ret = PTR_ERR(data->ssc_xo_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: ssc_xo (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->ssc_ahbs_clk = devm_clk_get(&pdev->dev, "ssc_ahbs");
+ if (IS_ERR(data->ssc_ahbs_clk)) {
+ ret = PTR_ERR(data->ssc_ahbs_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: ssc_ahbs (err: %d)\n", ret);
+ return ret;
+ }
+
+ ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, "qcom,halt-regs", 1, 0,
+ &halt_args);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
+ return -EINVAL;
+ }
+
+ data->halt_map = syscon_node_to_regmap(halt_args.np);
+ of_node_put(halt_args.np);
+ if (IS_ERR(data->halt_map))
+ return PTR_ERR(data->halt_map);
+
+ data->ssc_axi_halt = halt_args.args[0];
+
+ qcom_ssc_block_bus_init(&pdev->dev);
+
+ return 0;
+}
+
+static int qcom_ssc_block_bus_remove(struct platform_device *pdev)
+{
+ struct qcom_ssc_block_bus_data *data = platform_get_drvdata(pdev);
+
+ qcom_ssc_block_bus_deinit(&pdev->dev);
+
+ iounmap(data->reg_mpm_sscaon_config0);
+ iounmap(data->reg_mpm_sscaon_config1);
+
+ qcom_ssc_block_bus_pds_disable(data->pds, data->num_pds);
+ qcom_ssc_block_bus_pds_detach(&pdev->dev, data->pds, data->num_pds);
+ pm_runtime_disable(&pdev->dev);
+ pm_clk_destroy(&pdev->dev);
+
+ return 0;
+}
+
+static const struct of_device_id qcom_ssc_block_bus_of_match[] = {
+ { .compatible = "qcom,ssc-block-bus", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, qcom_ssc_block_bus_of_match);
+
+static struct platform_driver qcom_ssc_block_bus_driver = {
+ .probe = qcom_ssc_block_bus_probe,
+ .remove = qcom_ssc_block_bus_remove,
+ .driver = {
+ .name = "qcom-ssc-block-bus",
+ .of_match_table = qcom_ssc_block_bus_of_match,
+ },
+};
+
+module_platform_driver(qcom_ssc_block_bus_driver);
+
+MODULE_DESCRIPTION("A driver for handling the init sequence needed for accessing the SSC block on (some) qcom SoCs over AHB");
+MODULE_AUTHOR("Michael Srba <Michael.Srba@seznam.cz>");
+MODULE_LICENSE("GPL v2");
--
2.34.1
^ permalink raw reply related
* Re: [v2 06/10] iio: document bno055 private sysfs attributes
From: Jonathan Cameron @ 2022-01-22 18:08 UTC (permalink / raw)
To: Andrea Merello
Cc: Mauro Carvalho Chehab, linux-iio, linux-kernel, devicetree,
Lars-Peter Clausen, Rob Herring, Andy Shevchenko, Matt Ranostay,
Alexandru Ardelean, Jacopo Mondi, Andrea Merello
In-Reply-To: <CAN8YU5OT44Wz813tKA62-Dvq3=VoTcoyVE__5UuRw+i7+B7i8w@mail.gmail.com>
On Mon, 17 Jan 2022 10:37:33 +0100
Andrea Merello <andrea.merello@gmail.com> wrote:
> Trivial inline comments below. Beside that, I've found another
> pleasing issue with this "range" thing on this device..
>
> One one hand, things seem to always work as we discussed for the
> accelerometer (i.e. range doesn't affect the scale; the HW always
> provides readings in the same scale, but with different range and
> precision) on the other hand, the gyroscope behavior depends by the
> internal IMU firmware version.. great..
*sigh* :)
>
> Stock firmware has a bug[0], so that the "range" gyroscope registers
> do change the scale indeed. AFAICT stock firmware is the one you find
> in most (all?) breakout boards, which are usually available (and which
> I'm using right now for this driver mainlining attempt). Upgrading
> firmware looks like a rather obscure process that AFAICT can be done
> only in some specific USB-stick demo-board ("shuttle board") or with
> maybe with FAE assistance on custom developed boards [1] (i.e. maybe
> can be done by some professional user; I would say not for most
> people).
>
> So, I'm now wondering how to handle this... I really want to support
> the stock FW, which seems the most widespread, and the one I have
> right now; I'd say this means: the accelerometer thing will still work
> as we discussed (i.e. the range attribute thing), while the gyro will
> have writeable scale, and a (ro) scale_available attrib. But what
> about the gyro range thing? Should I drop it, or keep it as
> informative read-only?
I'd be cynical and for initial version at least, just hide it as 'too
complex' with a comment in the driver code on why.
>
> Then I could also support the new firmware (which I cannot test right
> now with my actual breakout board, but I might see whether I could get
> a board with an updated IMU), keeping also the current driver behavior
> (i.e. range stuff).
>
> But the question is: in either cases (new vs old fw) should the
> non-necessary attributes disappear or they may just be RO or locked
> (i.e. scale_available for new FW and range stuff for the old one)?
If they don't have meaning then they should disappear, but it would
also be valid to have the 'broken' one be read only if there is
an appropriate value.
>
> Any thoughts and advice on this whole thing would be very welcome :)
> my current inclination anyway now tends to be: go on supporting only
> the stock FW (i.e. the board I have here now) and eventually add
> support for the new fw later on, after merge.
Sounds sensible - but.... Make sure you check the firmware version
number (I hope it has one) and print a warning at least if you get
one that you have strong reason to believe will handle this differently
from whatever the driver is supporting.
This is definitely going to be a case for detailed comments in
the driver code so that we can 'recall' what on earth was
going on here in N years time!
>
> [0] https://community.bosch-sensortec.com/t5/MEMS-sensors-forum/BNO055-Wrong-sensitivity-resolution-in-datasheet/td-p/10266
> [1] https://community.bosch-sensortec.com/t5/MEMS-sensors-forum/BNO055-Software-Version/td-p/14001
>
> > > I've looked at other iio sysfs attributes in the DOC. It seems that
> > > "thesh" and "roc" attributes allows for both preprocessed and raw
> > > data: I found e.g. "<type>[Y][_name]_<raw|input>_thresh_value", but
> > > the related "what" entries written above all seem to omit both "_raw"
> > > and "_input"; I don't understand why.
> >
> > Excellent point. That documentation is garbage. Events are meant
> > to pick it up implicitly from the related channel _raw or _input.
> > I don't remember them ever having raw or input in their naming but
> > it's possible they did right at the beginning before the ABI was anywhere
> > near stable. Gah. I dread to think how long that that has been wrong.
>
> Ok, great :)
>
> > So I think range_raw postfix is the best bet.
>
> Will go with this, thanks.
>
> > Jonathan
> >
> >
> >
> >
> >
> > >
> >
> > >
> > > Andrea
> >
^ permalink raw reply
* MT7621 SoC Traffic Won't Flow on RGMII2 Bus/2nd GMAC
From: Arınç ÜNAL @ 2022-01-22 18:01 UTC (permalink / raw)
To: Luiz Angelo Daros de Luca, DENG Qingfang, Matthias Brugger,
John Crispin, Siddhant Gupta, Ilya Lipnitskiy, Sergio Paracuellos,
Felix Fietkau, Sean Wang, Mark Lee, Russell King, Jakub Kicinski,
David Miller, René van Dorst
Cc: linux-mediatek, netdev, linux-mips, devicetree, openwrt-devel,
erkin.bozoglu
[-- Attachment #1: Type: text/plain, Size: 2200 bytes --]
Hi all,
The company I currently work for has got an Ralink mt7621a board with an
external phy connected. It's a Realtek rtl8367s switch.
I've been running gregkh/staging staging-next & netdev/net-next master
branches with Sergio's "clk: ralink: make system controller a reset
provider" v8 patch series.
We don't have traffic flow on the RGMII2 bus which is shared by the 2nd
GMAC of the SoC, MT7530's GMAC5 and an external phy (rtl switch in our
case).
According to Documentation/devicetree/bindings/net/dsa/mt7530.txt, I can
either configure the external phy to connect to the second GMAC of the
mt7621 SoC or to MT7530's GMAC5 to create a cascade.
None of the documented configurations work:
External phy <-> 2nd GMAC
External phy <-> MT7530's GMAC5
The external switch works with Mediatek SDK ethernet driver on External
phy <-> 2nd GMAC mode.
I suspect there is a problem with the mtk_eth_soc driver on upstream.
Same issue on 5.10 (OpenWrt Master) and 4.14 (OpenWrt 19.07)
The board's RTL8367S schematics is in the attachments.
Dumbed down wiring scheme:
CPU
┌───────────────┐
│ GMAC0 | GMAC1 │
└───┼───────┼───┘
│ │
┌────────────┼┐ │
MT7530 │0 1 2 3 4 5 6│ │
└─────────────┘ │
┌───────┘
┌────────────┼┐
RTL8367S │0 1 2 3 4 6 7│
└┼─┼─┼─┼─┼────┘
┌───────┘ │ │ │ └───────┐
│ ┌───┘ │ └───┐ │
│ │ │ │ │
│ │ │ │ │
┌───┼─────┼─────┼─────┼─────┼───┐
│ sw1p0 sw1p1 sw1p2 sw1p3 sw1p4 │
└───────────────────────────────┘
Cheers.
Arınç
[-- Attachment #2: Xeront_7531_8367.pdf --]
[-- Type: application/pdf, Size: 361521 bytes --]
^ permalink raw reply
* Re: [PATCH v3 1/4] iio:frequency:admv1014: add support for ADMV1014
From: Jonathan Cameron @ 2022-01-22 18:01 UTC (permalink / raw)
To: Antoniu Miclaus; +Cc: robh+dt, linux-iio, devicetree, linux-kernel
In-Reply-To: <20220119081838.70210-1-antoniu.miclaus@analog.com>
On Wed, 19 Jan 2022 10:18:35 +0200
Antoniu Miclaus <antoniu.miclaus@analog.com> wrote:
> The ADMV1014 is a silicon germanium (SiGe), wideband,
> microwave downconverter optimized for point to point microwave
> radio designs operating in the 24 GHz to 44 GHz frequency range.
>
> Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/ADMV1014.pdf
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
Hi Antoniu,
This looks mostly fine to me, but I think you haven't quite understood
the difference between a required regulator and an optional one.
It's about whether there is power needed on the pin. E.g. sometimes for things
like reference voltages we can use either an external voltage or an
internally generated reference, thus making vref-supply optional.
It's not about whether they 'need' to be specified in DT. The regulator
core has a concept of a dummy regulator which is provided in some
cases when we request a regulator and one is not specified. This
is a simplification to allow for always on supplies without fully describing
them. That fallback is what should be relied on, not optional regulators
unless they really are.
Once you've made most (maybe all?) of the regulators in here non optional
you can use the bulk get / enable regulator calls to cut down on repetition.
Thanks,
Jonathan
...
> +static int admv1014_init(struct admv1014_state *st)
> +{
> + int ret;
> + unsigned int chip_id, enable_reg, enable_reg_msk;
> + struct spi_device *spi = st->spi;
> +
> + ret = regulator_enable(st->vcm_reg);
> + if (ret) {
> + dev_err(&spi->dev, "Failed to enable Common-Mode Voltage!\n");
> + return ret;
> + }
> +
> + ret = devm_add_action_or_reset(&spi->dev, admv1014_reg_disable, st->vcm_reg);
> + if (ret)
> + return ret;
> +
> + if (st->vcc_if_bb_reg) {
> + ret = regulator_enable(st->vcc_if_bb_reg);
> + if (ret) {
> + dev_err(&spi->dev, "Failed to enable BB and IF Voltage!\n");
> + return ret;
> + }
> +
> + ret = devm_add_action_or_reset(&spi->dev, admv1014_reg_disable, st->vcc_if_bb_reg);
> + if (ret)
> + return ret;
> + }
> +
> + if (st->vcc_vga_reg) {
I'm fairly sure these should not be optional regs (they may be dummy ones provided by
the regulator subsystem) so we should always enable them.
As below, you should be able to use bulk regulator handling for all of these.
> + ret = regulator_enable(st->vcc_vga_reg);
> + if (ret) {
> + dev_err(&spi->dev, "Failed to enable RF Amplifier Voltage!\n");
> + return ret;
> + }
> +
> + ret = devm_add_action_or_reset(&spi->dev, admv1014_reg_disable, st->vcc_vga_reg);
> + if (ret)
> + return ret;
> + }
> +
> + if (st->vcc_vva_reg) {
> + ret = regulator_enable(st->vcc_vva_reg);
> + if (ret) {
> + dev_err(&spi->dev, "Failed to enable VVA Control Circuit Voltage!\n");
> + return ret;
> + }
> +
> + ret = devm_add_action_or_reset(&spi->dev, admv1014_reg_disable, st->vcc_vva_reg);
> + if (ret)
> + return ret;
> + }
> +
> + if (st->vcc_lna_3p3_reg) {
> + ret = regulator_enable(st->vcc_lna_3p3_reg);
> + if (ret) {
> + dev_err(&spi->dev, "Failed to enable Low Noise Amplifier 3.3V Voltage!\n");
> + return ret;
> + }
> +
> + ret = devm_add_action_or_reset(&spi->dev, admv1014_reg_disable, st->vcc_lna_3p3_reg);
> + if (ret)
> + return ret;
> + }
> +
> + if (st->vcc_lna_1p5_reg) {
> + ret = regulator_enable(st->vcc_lna_1p5_reg);
> + if (ret) {
> + dev_err(&spi->dev, "Failed to enable Low Noise Amplifier 1.5V Voltage!\n");
> + return ret;
> + }
> +
> + ret = devm_add_action_or_reset(&spi->dev, admv1014_reg_disable, st->vcc_lna_1p5_reg);
> + if (ret)
> + return ret;
> + }
> +
> + if (st->vcc_bg_reg) {
> + ret = regulator_enable(st->vcc_bg_reg);
> + if (ret) {
> + dev_err(&spi->dev, "Failed to enable Band Gap Circuit Voltage!\n");
> + return ret;
> + }
> +
> + ret = devm_add_action_or_reset(&spi->dev, admv1014_reg_disable, st->vcc_bg_reg);
> + if (ret)
> + return ret;
> + }
> +
> + if (st->vcc_quad_reg) {
> + ret = regulator_enable(st->vcc_quad_reg);
> + if (ret) {
> + dev_err(&spi->dev, "Failed to enable Quadruple Voltage!\n");
> + return ret;
> + }
> +
> + ret = devm_add_action_or_reset(&spi->dev, admv1014_reg_disable, st->vcc_quad_reg);
> + if (ret)
> + return ret;
> + }
> +
> + if (st->vcc_mixer_reg) {
> + ret = regulator_enable(st->vcc_mixer_reg);
> + if (ret) {
> + dev_err(&spi->dev, "Failed to enable Mixer Voltage!\n");
> + return ret;
> + }
> +
> + ret = devm_add_action_or_reset(&spi->dev, admv1014_reg_disable, st->vcc_mixer_reg);
> + if (ret)
> + return ret;
> + }
> +
> + ret = clk_prepare_enable(st->clkin);
> + if (ret)
> + return ret;
> +
> + ret = devm_add_action_or_reset(&spi->dev, admv1014_clk_disable, st->clkin);
> + if (ret)
> + return ret;
> +
> + st->nb.notifier_call = admv1014_freq_change;
> + ret = devm_clk_notifier_register(&spi->dev, st->clkin, &st->nb);
> + if (ret)
> + return ret;
> +
> + ret = devm_add_action_or_reset(&spi->dev, admv1014_powerdown, st);
> + if (ret)
> + return ret;
> +
> + /* Perform a software reset */
> + ret = __admv1014_spi_update_bits(st, ADMV1014_REG_SPI_CONTROL,
> + ADMV1014_SPI_SOFT_RESET_MSK,
> + FIELD_PREP(ADMV1014_SPI_SOFT_RESET_MSK, 1));
> + if (ret) {
> + dev_err(&spi->dev, "ADMV1014 SPI software reset failed.\n");
> + return ret;
> + }
> +
> + ret = __admv1014_spi_update_bits(st, ADMV1014_REG_SPI_CONTROL,
> + ADMV1014_SPI_SOFT_RESET_MSK,
> + FIELD_PREP(ADMV1014_SPI_SOFT_RESET_MSK, 0));
> + if (ret) {
> + dev_err(&spi->dev, "ADMV1014 SPI software reset disable failed.\n");
> + return ret;
> + }
> +
> + ret = __admv1014_spi_write(st, ADMV1014_REG_VVA_TEMP_COMP, 0x727C);
> + if (ret) {
> + dev_err(&spi->dev, "Writing default Temperature Compensation value failed.\n");
> + return ret;
> + }
> +
> + ret = __admv1014_spi_read(st, ADMV1014_REG_SPI_CONTROL, &chip_id);
> + if (ret)
> + return ret;
> +
> + chip_id = (chip_id & ADMV1014_CHIP_ID_MSK) >> 4;
> + if (chip_id != ADMV1014_CHIP_ID) {
> + dev_err(&spi->dev, "Invalid Chip ID.\n");
> + return -EINVAL;
> + }
> +
> + ret = __admv1014_spi_update_bits(st, ADMV1014_REG_QUAD,
> + ADMV1014_QUAD_SE_MODE_MSK,
> + FIELD_PREP(ADMV1014_QUAD_SE_MODE_MSK,
> + st->quad_se_mode));
> + if (ret) {
> + dev_err(&spi->dev, "Writing Quad SE Mode failed.\n");
> + return ret;
> + }
> +
> + ret = admv1014_update_quad_filters(st);
> + if (ret) {
> + dev_err(&spi->dev, "Update Quad Filters failed.\n");
> + return ret;
> + }
> +
> + ret = admv1014_update_vcm_settings(st);
> + if (ret) {
> + dev_err(&spi->dev, "Update VCM Settings failed.\n");
> + return ret;
> + }
> +
> + enable_reg_msk = ADMV1014_P1DB_COMPENSATION_MSK |
> + ADMV1014_IF_AMP_PD_MSK |
> + ADMV1014_BB_AMP_PD_MSK |
> + ADMV1014_DET_EN_MSK;
> +
> + enable_reg = FIELD_PREP(ADMV1014_P1DB_COMPENSATION_MSK, st->p1db_comp ? 3 : 0) |
> + FIELD_PREP(ADMV1014_IF_AMP_PD_MSK, !(st->input_mode)) |
> + FIELD_PREP(ADMV1014_BB_AMP_PD_MSK, st->input_mode) |
> + FIELD_PREP(ADMV1014_DET_EN_MSK, st->det_en);
> +
> + return __admv1014_spi_update_bits(st, ADMV1014_REG_ENABLE, enable_reg_msk, enable_reg);
> +}
> +
> +static int admv1014_properties_parse(struct admv1014_state *st)
> +{
> + const char *str;
> + struct spi_device *spi = st->spi;
> +
> + st->det_en = device_property_read_bool(&spi->dev, "adi,detector-enable");
> +
> + st->p1db_comp = device_property_read_bool(&spi->dev, "adi,p1db-compensation-enable");
> +
> + str = "iq";
> + device_property_read_string(&spi->dev, "adi,input-mode", &str);
> +
> + if (!strcmp(str, "iq"))
> + st->input_mode = ADMV1014_IQ_MODE;
> + else if (!strcmp(str, "if"))
> + st->input_mode = ADMV1014_IF_MODE;
> + else
> + return -EINVAL;
> +
> + str = "diff";
> + device_property_read_string(&spi->dev, "adi,quad-se-mode", &str);
> +
> + if (!strcmp(str, "diff"))
> + st->quad_se_mode = ADMV1014_SE_MODE_DIFF;
> + else if (!strcmp(str, "se-pos"))
> + st->quad_se_mode = ADMV1014_SE_MODE_POS;
> + else if (!strcmp(str, "se-neg"))
> + st->quad_se_mode = ADMV1014_SE_MODE_NEG;
> + else
> + return -EINVAL;
> +
> + st->vcm_reg = devm_regulator_get(&spi->dev, "vcm");
> + if (IS_ERR(st->vcm_reg))
> + return dev_err_probe(&spi->dev, PTR_ERR(st->vcm_reg),
> + "failed to get the common-mode voltage\n");
> +
> + st->vcc_if_bb_reg = devm_regulator_get_optional(&spi->dev, "vcc-if-bb");
Are these actually optional? That means we can operate the device in a mode where
it doesn't matter if there is power on this pin... It doesn't mean we have
to specify them in DT, because they may be always on supplies in which case
a dummy regulator is fine (which is what you get from devm_regulator_get()
under some circumstances when one isn't specified).
Having made those that aren't actually optional, non optional you can probably
use the bulk regulator controls to avoid lots of identical calls.
> + if (IS_ERR(st->vcc_if_bb_reg))
> + return dev_err_probe(&spi->dev, PTR_ERR(st->vcc_if_bb_reg),
> + "failed to get the BB and IF supply\n");
> +
> + st->vcc_vga_reg = devm_regulator_get_optional(&spi->dev, "vcc-vga");
> + if (IS_ERR(st->vcc_vga_reg))
> + return dev_err_probe(&spi->dev, PTR_ERR(st->vcc_vga_reg),
> + "failed to get the RF Amplifier supply\n");
> +
> + st->vcc_vva_reg = devm_regulator_get_optional(&spi->dev, "vcc-vva");
> + if (IS_ERR(st->vcc_vva_reg))
> + return dev_err_probe(&spi->dev, PTR_ERR(st->vcc_vva_reg),
> + "failed to get the VVA Control Circuit supply\n");
> +
> + st->vcc_lna_3p3_reg = devm_regulator_get_optional(&spi->dev, "vcc-lna-3p3");
> + if (IS_ERR(st->vcc_lna_3p3_reg))
> + return dev_err_probe(&spi->dev, PTR_ERR(st->vcc_lna_3p3_reg),
> + "failed to get the Low Noise Amplifier 3.3V supply\n");
> +
> + st->vcc_lna_1p5_reg = devm_regulator_get_optional(&spi->dev, "vcc-lna-1p5");
> + if (IS_ERR(st->vcc_lna_1p5_reg))
> + return dev_err_probe(&spi->dev, PTR_ERR(st->vcc_lna_1p5_reg),
> + "failed to get the Low Noise Amplifier 1.5V supply\n");
> +
> + st->vcc_bg_reg = devm_regulator_get_optional(&spi->dev, "vcc-bg");
> + if (IS_ERR(st->vcc_lna_1p5_reg))
> + return dev_err_probe(&spi->dev, PTR_ERR(st->vcc_bg_reg),
> + "failed to get the Band Gap Circuit supply\n");
> +
> + st->vcc_quad_reg = devm_regulator_get_optional(&spi->dev, "vcc-quad");
> + if (IS_ERR(st->vcc_quad_reg))
> + return dev_err_probe(&spi->dev, PTR_ERR(st->vcc_quad_reg),
> + "failed to get the Quadruple supply\n");
> +
> + st->vcc_mixer_reg = devm_regulator_get_optional(&spi->dev, "vcc-mixer");
> + if (IS_ERR(st->vcc_quad_reg))
> + return dev_err_probe(&spi->dev, PTR_ERR(st->vcc_mixer_reg),
> + "failed to get the Mixer supply\n");
> +
> + st->clkin = devm_clk_get(&spi->dev, "lo_in");
> + if (IS_ERR(st->clkin))
> + return dev_err_probe(&spi->dev, PTR_ERR(st->clkin),
> + "failed to get the LO input clock\n");
> +
> + return 0;
> +}
> +
^ permalink raw reply
* Re: [PATCH v3 2/4] dt-bindings:iio:frequency: add admv1014 binding
From: Jonathan Cameron @ 2022-01-22 17:43 UTC (permalink / raw)
To: Antoniu Miclaus; +Cc: robh+dt, linux-iio, devicetree, linux-kernel
In-Reply-To: <20220119081838.70210-2-antoniu.miclaus@analog.com>
On Wed, 19 Jan 2022 10:18:36 +0200
Antoniu Miclaus <antoniu.miclaus@analog.com> wrote:
> Add device tree bindings for the ADMV1014 Upconverter.
>
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> changes in v3:
> - change clock description as suggested
> ---
> .../bindings/iio/frequency/adi,admv1014.yaml | 129 ++++++++++++++++++
> 1 file changed, 129 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml
>
> diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml b/Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml
> new file mode 100644
> index 000000000000..864093f6a29a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml
> @@ -0,0 +1,129 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/frequency/adi,admv1014.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ADMV1014 Microwave Downconverter
> +
> +maintainers:
> + - Antoniu Miclaus <antoniu.miclaus@analog.com>
> +
> +description: |
> + Wideband, microwave downconverter optimized for point to point microwave
> + radio designs operating in the 24 GHz to 44 GHz frequency range.
> +
> + https://www.analog.com/en/products/admv1014.html
> +
> +properties:
> + compatible:
> + enum:
> + - adi,admv1014
> +
> + reg:
> + maxItems: 1
> +
> + spi-max-frequency:
> + maximum: 1000000
> +
> + clocks:
> + minItems: 1
> +
> + clock-names:
> + items:
> + - const: lo_in
> + description:
> + External clock that provides the Local Oscilator input.
> +
> + vcm-supply:
> + description:
> + Common-mode voltage regulator.
> +
> + vcc-if-bb-supply:
> + description:
> + BB and IF supply voltage regulator.
> +
> + vcc-vga-supply:
> + description:
> + RF Amplifier supply voltage regulator.
> +
> + vcc-vva-supply:
> + description:
> + VVA Control Circuit supply voltage regulator.
> +
> + vcc-lna-3p3-supply:
> + description:
> + Low Noise Amplifier 3.3V supply voltage regulator.
> +
> + vcc-lna-1p5-supply:
> + description:
> + Low Noise Amplifier 1.5V supply voltage regulator.
> +
> + vcc-bg-supply:
> + description:
> + Band Gap Circuit supply voltage regulator.
> +
> + vcc-quad-supply:
> + description:
> + Quadruple supply voltage regulator.
> +
> + vcc-mixer-supply:
> + description:
> + Mixer supply voltage regulator.
> +
> + adi,input-mode:
> + description:
> + Select the input mode.
> + iq - in-phase quadrature (I/Q) input
> + if - complex intermediate frequency (IF) input
> + enum: [iq, if]
> +
> + adi,detector-enable:
> + description:
> + Digital Rx Detector Enable. The Square Law Detector output is
> + available at output pin VDET.
> + type: boolean
> +
> + adi,p1db-compensation-enable:
> + description:
> + Turn on bits to optimize P1dB.
> + type: boolean
> +
> + adi,quad-se-mode:
> + description:
> + Switch the LO path from differential to single-ended operation.
> + se-neg - Single-Ended Mode, Negative Side Disabled.
> + se-pos - Single-Ended Mode, Positive Side Disabled.
> + diff - Differential Mode.
> + enum: [se-neg, se-pos, diff]
Hi Antoniu
These elements need to specify a default for when they are not provided
seeing as they are optional and the default is not obvious.
Thanks,
Jonathan
> +
> + '#clock-cells':
> + const: 0
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - vcm-supply
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + spi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + admv1014@0{
> + compatible = "adi,admv1014";
> + reg = <0>;
> + spi-max-frequency = <1000000>;
> + clocks = <&admv1014_lo>;
> + clock-names = "lo_in";
> + vcm-supply = <&vcm>;
> + adi,quad-se-mode = "diff";
> + adi,detector-enable;
> + adi,p1db-compensation-enable;
> + };
> + };
> +...
^ permalink raw reply
* Re: [PATCH v3 3/4] Documentation:ABI:testing:admv1014: add ABI docs
From: Jonathan Cameron @ 2022-01-22 17:38 UTC (permalink / raw)
To: Antoniu Miclaus; +Cc: robh+dt, linux-iio, devicetree, linux-kernel
In-Reply-To: <20220119081838.70210-3-antoniu.miclaus@analog.com>
On Wed, 19 Jan 2022 10:18:37 +0200
Antoniu Miclaus <antoniu.miclaus@analog.com> wrote:
> Add documentation for the use of the Digital Attenuator gain.
>
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
One entry that should be in the generic docs rather than here.
Given the documentation generation scripts don't support multiple
entries for a given attribute name an that one is 'standard'
we should just add it to the main file as otherwise the chances
are very high of accidentally getting duplication when it
turns up in another driver ABI doc.
We may need to move some of the others later if they turn out
to occur in multiple drivers but they are obscure enough to
be fine in this file for now.
Thanks,
Jonathan
> ---
> changes in v3:
> - add description for calibscale in I/Q mode
> .../testing/sysfs-bus-iio-frequency-admv1014 | 29 +++++++++++++++++++
> 1 file changed, 29 insertions(+)
> create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1014
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1014 b/Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1014
> new file mode 100644
> index 000000000000..77c1691e6910
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1014
> @@ -0,0 +1,29 @@
> +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_i_calibscale_coarse
> +KernelVersion:
> +Contact: linux-iio@vger.kernel.org
> +Description:
> + Read/write value for the digital attenuator gain (IF_I) with coarse steps.
> +
> +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_q_calibscale_coarse
> +KernelVersion:
> +Contact: linux-iio@vger.kernel.org
> +Description:
> + Read/write value for the digital attenuator gain (IF_Q) with coarse steps.
> +
> +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_i_calibscale_fine
> +KernelVersion:
> +Contact: linux-iio@vger.kernel.org
> +Description:
> + Read/write value for the digital attenuator gain (IF_I) with fine steps.
> +
> +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_q_calibscale_fine
> +KernelVersion:
> +Contact: linux-iio@vger.kernel.org
> +Description:
> + Read/write value for the digital attenuator gain (IF_Q) with fine steps.
> +
> +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage_calibscale
This particular one is normal ABI, so should just be added to the list
in sysfs-bus-iio alongside all the other calibscale entries.
> +KernelVersion:
> +Contact: linux-iio@vger.kernel.org
> +Description:
> + Read/write value for the digital attenuator gain (I/Q).
^ permalink raw reply
* Re: [PATCH v3 2/4] dt-bindings:iio:frequency: add admv1014 binding
From: Jonathan Cameron @ 2022-01-22 17:32 UTC (permalink / raw)
To: Antoniu Miclaus; +Cc: robh+dt, linux-iio, devicetree, linux-kernel
In-Reply-To: <20220119081838.70210-2-antoniu.miclaus@analog.com>
On Wed, 19 Jan 2022 10:18:36 +0200
Antoniu Miclaus <antoniu.miclaus@analog.com> wrote:
> Add device tree bindings for the ADMV1014 Upconverter.
>
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> changes in v3:
> - change clock description as suggested
> ---
Change log below the ---
We don't want it in the permanent git history. There will
be a link tag to this thread to allow anyone who happens to
want to known more to find the version change log.
Given you got it right in the other 3 patches, I'm guessing you
just missed here.
If that is all that turns up in review, I can fix it whilst applying.
Thanks,
Jonathan
> .../bindings/iio/frequency/adi,admv1014.yaml | 129 ++++++++++++++++++
> 1 file changed, 129 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml
>
> diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml b/Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml
> new file mode 100644
> index 000000000000..864093f6a29a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml
> @@ -0,0 +1,129 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/frequency/adi,admv1014.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ADMV1014 Microwave Downconverter
> +
> +maintainers:
> + - Antoniu Miclaus <antoniu.miclaus@analog.com>
> +
> +description: |
> + Wideband, microwave downconverter optimized for point to point microwave
> + radio designs operating in the 24 GHz to 44 GHz frequency range.
> +
> + https://www.analog.com/en/products/admv1014.html
> +
> +properties:
> + compatible:
> + enum:
> + - adi,admv1014
> +
> + reg:
> + maxItems: 1
> +
> + spi-max-frequency:
> + maximum: 1000000
> +
> + clocks:
> + minItems: 1
> +
> + clock-names:
> + items:
> + - const: lo_in
> + description:
> + External clock that provides the Local Oscilator input.
> +
> + vcm-supply:
> + description:
> + Common-mode voltage regulator.
> +
> + vcc-if-bb-supply:
> + description:
> + BB and IF supply voltage regulator.
> +
> + vcc-vga-supply:
> + description:
> + RF Amplifier supply voltage regulator.
> +
> + vcc-vva-supply:
> + description:
> + VVA Control Circuit supply voltage regulator.
> +
> + vcc-lna-3p3-supply:
> + description:
> + Low Noise Amplifier 3.3V supply voltage regulator.
> +
> + vcc-lna-1p5-supply:
> + description:
> + Low Noise Amplifier 1.5V supply voltage regulator.
> +
> + vcc-bg-supply:
> + description:
> + Band Gap Circuit supply voltage regulator.
> +
> + vcc-quad-supply:
> + description:
> + Quadruple supply voltage regulator.
> +
> + vcc-mixer-supply:
> + description:
> + Mixer supply voltage regulator.
> +
> + adi,input-mode:
> + description:
> + Select the input mode.
> + iq - in-phase quadrature (I/Q) input
> + if - complex intermediate frequency (IF) input
> + enum: [iq, if]
> +
> + adi,detector-enable:
> + description:
> + Digital Rx Detector Enable. The Square Law Detector output is
> + available at output pin VDET.
> + type: boolean
> +
> + adi,p1db-compensation-enable:
> + description:
> + Turn on bits to optimize P1dB.
> + type: boolean
> +
> + adi,quad-se-mode:
> + description:
> + Switch the LO path from differential to single-ended operation.
> + se-neg - Single-Ended Mode, Negative Side Disabled.
> + se-pos - Single-Ended Mode, Positive Side Disabled.
> + diff - Differential Mode.
> + enum: [se-neg, se-pos, diff]
> +
> + '#clock-cells':
> + const: 0
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - vcm-supply
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + spi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + admv1014@0{
> + compatible = "adi,admv1014";
> + reg = <0>;
> + spi-max-frequency = <1000000>;
> + clocks = <&admv1014_lo>;
> + clock-names = "lo_in";
> + vcm-supply = <&vcm>;
> + adi,quad-se-mode = "diff";
> + adi,detector-enable;
> + adi,p1db-compensation-enable;
> + };
> + };
> +...
^ permalink raw reply
* Re: [PATCH v3 0/3] Add support for LTC2688
From: Jonathan Cameron @ 2022-01-22 17:27 UTC (permalink / raw)
To: Nuno Sá
Cc: linux-iio, devicetree, Rob Herring, Lars-Peter Clausen,
Michael Hennerich
In-Reply-To: <20220121142501.151-1-nuno.sa@analog.com>
On Fri, 21 Jan 2022 15:24:58 +0100
Nuno Sá <nuno.sa@analog.com> wrote:
> The ABI defined for this driver has some subtleties that were previously
> discussed in this RFC [1]. This might not be the final state but,
> hopefully, we are close to it:
>
> toggle mode channels:
>
> * out_voltageY_toggle_en
> * out_voltageY_raw0
> * out_voltageY_raw1
> * out_voltageY_symbol
>
> dither mode channels:
>
> * out_voltageY_dither_en
> * out_voltageY_dither_raw
> * out_voltageY_dither_raw_available
> * out_voltageY_dither_offset
> * out_voltageY_dither_frequency
> * out_voltageY_dither_frequency_available
> * out_voltageY_dither_phase
> * out_voltageY_dither_phase_available
>
> Default channels won't have any of the above ABIs. A channel is toggle
> capable if the devicetree 'adi,toggle-mode' flag is set. For dither, the
> assumption is more silent. If 'adi,toggle-mode' is not given and a
> channel is associated with a TGPx pin through 'adi,toggle-dither-input',
> then the channel is assumed to be dither capable (there's no point in
> having a dither capable channel without an input clock).
>
> changes in v2:
>
> ltc2688:
> * Use local buffer for regmap read. Do not assume that reg is part of
> larger buffer;
> * Renamed GPIO to "clr" so that is consistent with the datasheet;
> * Renamed 'mask' and 'm' to info. 'mask' is a thing from the past;
> * Removed 'LTC2688_CHAN_TOGGLE()' and defined to static ext_info arrays;
> * Use 'regmap_set_bits' to set external ref;
> * Use FIELD_{PREP|GET} for dither amplitude and channel calibbias where
> only 13bits are used;
> * Use 'regmap_write()' instead of update_bits for channels settings;
> * Init 'val' at the beginning of the channel configuration loop
> (and drop mask);
> * Comment 'ltc2688_reg_writable()' to account for the special condition;
> * Kmemdup default channels so that it can be safely changed per probed
> device;
> * Replace extended info multiplexer functions by individual functions;
> * Use raw0 ABI for toggle channels;
> * Use dedicated offset ABI for dither channels;
> * Misc changes (spell fixes, blank lines...);
> * Have a clock property per channel. Note that we this I moved to OF
> since we now have to use 'devm_get_clk_from_child()' which is using
> device_node. Note that I could use 'to_of_node()' but mixing of.h and
> property.h does not feel like a good idea.
>
> ABI:
> * Added out_voltageY_raw0 ABI for toggle mode;
> * Added out_voltageY_dither_offset.
>
> Bindings:
> * Use standard microvolt unit;
> * Added constrains for adi,output-range-microvolt and removed negative
> values from the dts example;
> * Moved clocks to the channel object;
> * Dropped clock-names;
> * Add a dependency between 'adi,toggle-dither-input' and 'clocks'.
>
> Changes in v3:
>
> ltc2688:
> * Fix mismatch between functions and function pointers detected by kernel
> test bot;
> * Always use if (ret) when ret > 0 has no meaning;
> * Rename ltc2688_bulk_disable -> ltc2688_disable_regulators;
> * Report dither phase in radians rather than degrees.
>
> ABI:
> * Specify units for dither_phase and dither_freqency;
> * Say why its useful to have dither_en and toggle_en;
> * Combine out_voltageY_raw0 and out_voltageY_raw1;
> * Fix some description issues in out_voltageY_raw{0|1} and
> out_voltageY_symbol.
>
> Bindings:
> * Remove mentions to ABI (linux specifix);
> * Slightly rephrased VREF and adi,toggle-dither-input properties and
> suggested.
>
> [1]: https://marc.info/?l=linux-iio&m=163662843603265&w=2
Series looks good to me, but will have to wait a little longer for DT and
any other review before I apply it.
Thanks,
Jonathan
>
> Nuno Sá (3):
> iio: dac: add support for ltc2688
> iio: ABI: add ABI file for the LTC2688 DAC
> dt-bindings: iio: Add ltc2688 documentation
>
> .../ABI/testing/sysfs-bus-iio-dac-ltc2688 | 86 ++
> .../bindings/iio/dac/adi,ltc2688.yaml | 146 +++
> MAINTAINERS | 9 +
> drivers/iio/dac/Kconfig | 11 +
> drivers/iio/dac/Makefile | 1 +
> drivers/iio/dac/ltc2688.c | 1070 +++++++++++++++++
> 6 files changed, 1323 insertions(+)
> create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-dac-ltc2688
> create mode 100644 Documentation/devicetree/bindings/iio/dac/adi,ltc2688.yaml
> create mode 100644 drivers/iio/dac/ltc2688.c
>
^ permalink raw reply
* Re: [PATCH v3 1/2] iio: adc: tsc2046: add .read_raw support
From: Jonathan Cameron @ 2022-01-22 17:14 UTC (permalink / raw)
To: Oleksij Rempel
Cc: devicetree, linux-kernel, Pengutronix Kernel Team, David Jander,
Robin van der Gracht, linux-iio, Lars-Peter Clausen
In-Reply-To: <20220117082852.3370869-1-o.rempel@pengutronix.de>
On Mon, 17 Jan 2022 09:28:51 +0100
Oleksij Rempel <o.rempel@pengutronix.de> wrote:
> Add read_raw() support to make use of iio_hwmon and other iio clients.
>
> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
> ---
Change log? If it's just the check against PAGE_SIZE then I'm fine with it, but
maybe I missed something. Much better to have a short description of what
changed here.
Anyhow, I'll assume that's it. Applied to the togreg branch of iio.git and
pushed out as testing to let 0-day poke at it and see if it can find any
problems.
There was a little fuzz here for patch 2, presumably because the fix that is
in flight. Hopefully that won't cause us too many problems in linux-next or
at merge time.
Thanks,
Jonathan
> drivers/iio/adc/ti-tsc2046.c | 118 ++++++++++++++++++++++++++++-------
> 1 file changed, 97 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/iio/adc/ti-tsc2046.c b/drivers/iio/adc/ti-tsc2046.c
> index 7ac1fc4b04c2..95771ceba206 100644
> --- a/drivers/iio/adc/ti-tsc2046.c
> +++ b/drivers/iio/adc/ti-tsc2046.c
> @@ -86,6 +86,7 @@
> #define TI_TSC2046_EXT_POLL_CNT 3
> #define TI_TSC2046_POLL_CNT \
> (TI_TSC2046_MIN_POLL_CNT + TI_TSC2046_EXT_POLL_CNT)
> +#define TI_TSC2046_INT_VREF 2500
>
> /* Represents a HW sample */
> struct tsc2046_adc_atom {
> @@ -166,9 +167,6 @@ struct tsc2046_adc_priv {
> struct tsc2046_adc_atom *rx;
> struct tsc2046_adc_atom *tx;
>
> - struct tsc2046_adc_atom *rx_one;
> - struct tsc2046_adc_atom *tx_one;
> -
> unsigned int count;
> unsigned int groups;
> u32 effective_speed_hz;
> @@ -184,6 +182,8 @@ struct tsc2046_adc_priv {
> .type = IIO_VOLTAGE, \
> .indexed = 1, \
> .channel = index, \
> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
> .datasheet_name = "#name", \
> .scan_index = index, \
> .scan_type = { \
> @@ -247,6 +247,14 @@ static u8 tsc2046_adc_get_cmd(struct tsc2046_adc_priv *priv, int ch_idx,
> else
> pd = 0;
>
> + switch (ch_idx) {
> + case TI_TSC2046_ADDR_TEMP1:
> + case TI_TSC2046_ADDR_AUX:
> + case TI_TSC2046_ADDR_VBAT:
> + case TI_TSC2046_ADDR_TEMP0:
> + pd |= TI_TSC2046_SER | TI_TSC2046_PD1_VREF_ON;
> + }
> +
> return TI_TSC2046_START | FIELD_PREP(TI_TSC2046_ADDR, ch_idx) | pd;
> }
>
> @@ -258,16 +266,50 @@ static u16 tsc2046_adc_get_value(struct tsc2046_adc_atom *buf)
> static int tsc2046_adc_read_one(struct tsc2046_adc_priv *priv, int ch_idx,
> u32 *effective_speed_hz)
> {
> + struct tsc2046_adc_ch_cfg *ch = &priv->ch_cfg[ch_idx];
> + struct tsc2046_adc_atom *rx_buf, *tx_buf;
> + unsigned int val, val_normalized = 0;
> + int ret, i, count_skip = 0, max_count;
> struct spi_transfer xfer;
> struct spi_message msg;
> - int ret;
> + u8 cmd;
> +
> + if (!effective_speed_hz) {
> + count_skip = tsc2046_adc_time_to_count(priv, ch->settling_time_us);
> + max_count = count_skip + ch->oversampling_ratio;
> + } else {
> + max_count = 1;
> + }
> +
> + if (sizeof(*tx_buf) * max_count > PAGE_SIZE)
> + return -ENOSPC;
> +
> + tx_buf = kcalloc(max_count, sizeof(*tx_buf), GFP_KERNEL);
> + if (!tx_buf)
> + return -ENOMEM;
> +
> + rx_buf = kcalloc(max_count, sizeof(*rx_buf), GFP_KERNEL);
> + if (!rx_buf) {
> + ret = -ENOMEM;
> + goto free_tx;
> + }
> +
> + /*
> + * Do not enable automatic power down on working samples. Otherwise the
> + * plates will never be completely charged.
> + */
> + cmd = tsc2046_adc_get_cmd(priv, ch_idx, true);
> +
> + for (i = 0; i < max_count - 1; i++)
> + tx_buf[i].cmd = cmd;
> +
> + /* automatically power down on last sample */
> + tx_buf[i].cmd = tsc2046_adc_get_cmd(priv, ch_idx, false);
>
> memset(&xfer, 0, sizeof(xfer));
> - priv->tx_one->cmd = tsc2046_adc_get_cmd(priv, ch_idx, false);
> - priv->tx_one->data = 0;
> - xfer.tx_buf = priv->tx_one;
> - xfer.rx_buf = priv->rx_one;
> - xfer.len = sizeof(*priv->tx_one);
> + xfer.tx_buf = tx_buf;
> + xfer.rx_buf = rx_buf;
> + xfer.len = sizeof(*tx_buf) * max_count;
> spi_message_init_with_transfers(&msg, &xfer, 1);
>
> /*
> @@ -278,13 +320,25 @@ static int tsc2046_adc_read_one(struct tsc2046_adc_priv *priv, int ch_idx,
> if (ret) {
> dev_err_ratelimited(&priv->spi->dev, "SPI transfer failed %pe\n",
> ERR_PTR(ret));
> - return ret;
> + goto free_bufs;
> }
>
> if (effective_speed_hz)
> *effective_speed_hz = xfer.effective_speed_hz;
>
> - return tsc2046_adc_get_value(priv->rx_one);
> + for (i = 0; i < max_count - count_skip; i++) {
> + val = tsc2046_adc_get_value(&rx_buf[count_skip + i]);
> + val_normalized += val;
> + }
> +
> + ret = DIV_ROUND_UP(val_normalized, max_count - count_skip);
> +
> +free_bufs:
> + kfree(rx_buf);
> +free_tx:
> + kfree(tx_buf);
> +
> + return ret;
> }
>
> static size_t tsc2046_adc_group_set_layout(struct tsc2046_adc_priv *priv,
> @@ -391,6 +445,37 @@ static irqreturn_t tsc2046_adc_trigger_handler(int irq, void *p)
> return IRQ_HANDLED;
> }
>
> +static int tsc2046_adc_read_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + int *val, int *val2, long m)
> +{
> + struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
> + int ret;
> +
> + switch (m) {
> + case IIO_CHAN_INFO_RAW:
> + ret = tsc2046_adc_read_one(priv, chan->channel, NULL);
> + if (ret < 0)
> + return ret;
> +
> + *val = ret;
> +
> + return IIO_VAL_INT;
> + case IIO_CHAN_INFO_SCALE:
> + /*
> + * Note: the TSC2046 has internal voltage divider on the VBAT
> + * line. This divider can be influenced by external divider.
> + * So, it is better to use external voltage-divider driver
> + * instead, which is calculating complete chain.
> + */
> + *val = TI_TSC2046_INT_VREF;
> + *val2 = chan->scan_type.realbits;
> + return IIO_VAL_FRACTIONAL_LOG2;
> + }
> +
> + return -EINVAL;
> +}
> +
> static int tsc2046_adc_update_scan_mode(struct iio_dev *indio_dev,
> const unsigned long *active_scan_mask)
> {
> @@ -421,6 +506,7 @@ static int tsc2046_adc_update_scan_mode(struct iio_dev *indio_dev,
> }
>
> static const struct iio_info tsc2046_adc_info = {
> + .read_raw = tsc2046_adc_read_raw,
> .update_scan_mode = tsc2046_adc_update_scan_mode,
> };
>
> @@ -563,16 +649,6 @@ static int tsc2046_adc_setup_spi_msg(struct tsc2046_adc_priv *priv)
> size_t size;
> int ret;
>
> - priv->tx_one = devm_kzalloc(&priv->spi->dev, sizeof(*priv->tx_one),
> - GFP_KERNEL);
> - if (!priv->tx_one)
> - return -ENOMEM;
> -
> - priv->rx_one = devm_kzalloc(&priv->spi->dev, sizeof(*priv->rx_one),
> - GFP_KERNEL);
> - if (!priv->rx_one)
> - return -ENOMEM;
> -
> /*
> * Make dummy read to set initial power state and get real SPI clock
> * freq. It seems to be not important which channel is used for this
^ permalink raw reply
* [PATCH 2/2] arm64: dts: qcom: sm8450: fix apps_smmu interrupts
From: Jonathan Marek @ 2022-01-22 16:29 UTC (permalink / raw)
To: linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Konrad Dybcio,
Vinod Koul,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20220122162932.7686-1-jonathan@marek.ca>
Update interrupts in apps_smmu to match downstream. This is fixes apps_smmu
failing to probe when running at EL2 (expects 96 context interrupts)
Fixes: 892d5395396d ("arm64: dts: qcom: sm8450: add smmu nodes")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 5a98f2aad7099..aef8b6814cda0 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1076,7 +1076,7 @@ apps_smmu: iommu@15000000 {
compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
#iommu-cells = <2>;
- #global-interrupts = <2>;
+ #global-interrupts = <1>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
@@ -1163,6 +1163,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
--
2.26.1
^ permalink raw reply related
* [PATCH 1/2] arm64: dts: qcom: sm8450: enable GCC_USB3_0_CLKREF_EN for usb
From: Jonathan Marek @ 2022-01-22 16:29 UTC (permalink / raw)
To: linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Vinod Koul,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
USB doesn't work at all without this clock enabled. This fixes USB when not
using clk_ignore_unused.
Fixes: 19fd04fb9247 ("arm64: dts: qcom: sm8450: Add usb nodes")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 7611ceaa918af..5a98f2aad7099 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1442,9 +1442,10 @@ usb_1: usb@a6f8800 {
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
- <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB3_0_CLKREF_EN>;
clock-names = "cfg_noc", "core", "iface", "mock_utmi",
- "sleep";
+ "sleep", "xo";
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
--
2.26.1
^ permalink raw reply related
* Aw: Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0
From: Frank Wunderlich @ 2022-01-22 14:50 UTC (permalink / raw)
To: Heiko Stübner
Cc: Peter Geis, Johan Jonker, Frank Wunderlich,
open list:ARM/Rockchip SoC..., Rob Herring, devicetree,
arm-mail-list, Linux Kernel Mailing List
In-Reply-To: <236548630.RelmrRfzIS@diego>
Hi,
i plan to send a v2 of the series after 5.17-rc1 is out, because i have now verified
the functions from gpio header and found some pinctrl-changes. V1 had only prepared
the nodes to know which devices are present on this header.
should i include this patch again or do you pull it from v1 (maybe as fix)?
regards Frank
> Gesendet: Montag, 17. Januar 2022 um 22:05 Uhr
> Von: "Heiko Stübner" <heiko@sntech.de>
> From looking at the documentation I got the impression that the
> pclk_xpcs is related to the separate qsgmii_pcs in the memory map.
>
> So yes, I fully agree to dropping this clock from here and then adding
> them to whatever ip block really needs it.
^ permalink raw reply
* [PATCH 2/3] dt-bindings: thermal: samsung: convert to dtschema
From: Krzysztof Kozlowski @ 2022-01-22 13:25 UTC (permalink / raw)
To: Rafael J. Wysocki, Daniel Lezcano, Amit Kucheria, Zhang Rui,
Rob Herring, Krzysztof Kozlowski, Bartlomiej Zolnierkiewicz,
linux-pm, devicetree, linux-arm-kernel, linux-samsung-soc,
linux-kernel
In-Reply-To: <20220122132554.65192-1-krzysztof.kozlowski@canonical.com>
Convert the Samsung Exynos SoC Thermal Management Unit bindings to DT
schema format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/thermal/exynos-thermal.txt | 106 ----------
.../thermal/samsung,exynos-thermal.yaml | 184 ++++++++++++++++++
2 files changed, 184 insertions(+), 106 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/thermal/exynos-thermal.txt
create mode 100644 Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.yaml
diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
deleted file mode 100644
index 33004ce7e5df..000000000000
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ /dev/null
@@ -1,106 +0,0 @@
-* Exynos Thermal Management Unit (TMU)
-
-** Required properties:
-
-- compatible : One of the following:
- "samsung,exynos3250-tmu"
- "samsung,exynos4412-tmu"
- "samsung,exynos4210-tmu"
- "samsung,exynos5250-tmu"
- "samsung,exynos5260-tmu"
- "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
- "samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4
- Exynos5420 (Must pass triminfo base and triminfo clock)
- "samsung,exynos5433-tmu"
- "samsung,exynos7-tmu"
-- reg : Address range of the thermal registers. For soc's which has multiple
- instances of TMU and some registers are shared across all TMU's like
- interrupt related then 2 set of register has to supplied. First set
- belongs to register set of TMU instance and second set belongs to
- registers shared with the TMU instance.
-
- NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
- channels 2, 3 and 4
- Use "samsung,exynos5420-tmu-ext-triminfo" in cases, there is a misplaced
- register, also provide clock to access that base.
-
- TRIMINFO at 0x1006c000 contains data for TMU channel 3
- TRIMINFO at 0x100a0000 contains data for TMU channel 4
- TRIMINFO at 0x10068000 contains data for TMU channel 2
-
-- interrupts : Should contain interrupt for thermal system
-- clocks : The main clocks for TMU device
- -- 1. operational clock for TMU channel
- -- 2. optional clock to access the shared registers of TMU channel
- -- 3. optional special clock for functional operation
-- clock-names : Thermal system clock name
- -- "tmu_apbif" operational clock for current TMU channel
- -- "tmu_triminfo_apbif" clock to access the shared triminfo register
- for current TMU channel
- -- "tmu_sclk" clock for functional operation of the current TMU
- channel
-
-The Exynos TMU supports generating interrupts when reaching given
-temperature thresholds. Number of supported thermal trip points depends
-on the SoC (only first trip points defined in DT will be configured):
- - most of SoC: 4
- - samsung,exynos5433-tmu: 8
- - samsung,exynos7-tmu: 8
-
-** Optional properties:
-
-- vtmu-supply: This entry is optional and provides the regulator node supplying
- voltage to TMU. If needed this entry can be placed inside
- board/platform specific dts file.
-
-Example 1):
-
- tmu@100c0000 {
- compatible = "samsung,exynos4412-tmu";
- interrupt-parent = <&combiner>;
- reg = <0x100C0000 0x100>;
- interrupts = <2 4>;
- clocks = <&clock 383>;
- clock-names = "tmu_apbif";
- vtmu-supply = <&tmu_regulator_node>;
- #thermal-sensor-cells = <0>;
- };
-
-Example 2): (In case of Exynos5420 "with misplaced TRIMINFO register")
- tmu_cpu2: tmu@10068000 {
- compatible = "samsung,exynos5420-tmu-ext-triminfo";
- reg = <0x10068000 0x100>, <0x1006c000 0x4>;
- interrupts = <0 184 0>;
- clocks = <&clock 318>, <&clock 318>;
- clock-names = "tmu_apbif", "tmu_triminfo_apbif";
- #thermal-sensor-cells = <0>;
- };
-
- tmu_cpu3: tmu@1006c000 {
- compatible = "samsung,exynos5420-tmu-ext-triminfo";
- reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
- interrupts = <0 185 0>;
- clocks = <&clock 318>, <&clock 319>;
- clock-names = "tmu_apbif", "tmu_triminfo_apbif";
- #thermal-sensor-cells = <0>;
- };
-
- tmu_gpu: tmu@100a0000 {
- compatible = "samsung,exynos5420-tmu-ext-triminfo";
- reg = <0x100a0000 0x100>, <0x10068000 0x4>;
- interrupts = <0 215 0>;
- clocks = <&clock 319>, <&clock 318>;
- clock-names = "tmu_apbif", "tmu_triminfo_apbif";
- #thermal-sensor-cells = <0>;
- };
-
-Note: For multi-instance tmu each instance should have an alias correctly
-numbered in "aliases" node.
-
-Example:
-
-aliases {
- tmuctrl0 = &tmuctrl_0;
- tmuctrl1 = &tmuctrl_1;
- tmuctrl2 = &tmuctrl_2;
-};
diff --git a/Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.yaml b/Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.yaml
new file mode 100644
index 000000000000..17129f75d962
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.yaml
@@ -0,0 +1,184 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/samsung,exynos-thermal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC Thermal Management Unit (TMU)
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+description: |
+ For multi-instance tmu each instance should have an alias correctly numbered
+ in "aliases" node.
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos3250-tmu
+ - samsung,exynos4412-tmu
+ - samsung,exynos4210-tmu
+ - samsung,exynos5250-tmu
+ - samsung,exynos5260-tmu
+ # For TMU channel 0, 1 on Exynos5420:
+ - samsung,exynos5420-tmu
+ # For TMU channels 2, 3 and 4 of Exynos5420:
+ - samsung,exynos5420-tmu-ext-triminfo
+ - samsung,exynos5433-tmu
+ - samsung,exynos7-tmu
+
+ clocks:
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ minItems: 1
+ maxItems: 3
+
+ interrupts:
+ description: |
+ The Exynos TMU supports generating interrupts when reaching given
+ temperature thresholds. Number of supported thermal trip points depends
+ on the SoC (only first trip points defined in DT will be configured)::
+ - most of SoC: 4
+ - samsung,exynos5433-tmu: 8
+ - samsung,exynos7-tmu: 8
+ maxItems: 1
+
+ reg:
+ items:
+ - description: TMU instance registers.
+ - description: |
+ Shared TMU registers.
+
+ Note:: On Exynos5420, the TRIMINFO register is misplaced for TMU
+ channels 2, 3 and 4 Use "samsung,exynos5420-tmu-ext-triminfo" in
+ cases, there is a misplaced register, also provide clock to access
+ that base.
+ TRIMINFO at 0x1006c000 contains data for TMU channel 3
+ TRIMINFO at 0x100a0000 contains data for TMU channel 4
+ TRIMINFO at 0x10068000 contains data for TMU channel 2
+ minItems: 1
+
+ '#thermal-sensor-cells': true
+
+ vtmu-supply:
+ description: The regulator node supplying voltage to TMU.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - interrupts
+ - reg
+
+allOf:
+ - $ref: /schemas/thermal/thermal-sensor.yaml
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5420-tmu-ext-triminfo
+ then:
+ properties:
+ clocks:
+ items:
+ - description:
+ Operational clock for TMU channel.
+ - description:
+ Optional clock to access the shared registers (e.g. TRIMINFO) of TMU
+ channel.
+ clock-names:
+ items:
+ - const: tmu_apbif
+ - const: tmu_triminfo_apbif
+ reg:
+ minItems: 2
+ maxItems: 2
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos5433-tmu
+ - samsung,exynos7-tmu
+ then:
+ properties:
+ clocks:
+ items:
+ - description:
+ Operational clock for TMU channel.
+ - description:
+ Optional special clock for functional operation of TMU channel.
+ clock-names:
+ items:
+ - const: tmu_apbif
+ - const: tmu_sclk
+ reg:
+ minItems: 1
+ maxItems: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos3250-tmu
+ - samsung,exynos4412-tmu
+ - samsung,exynos4210-tmu
+ - samsung,exynos5250-tmu
+ - samsung,exynos5260-tmu
+ - samsung,exynos5420-tmu
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ reg:
+ minItems: 1
+ maxItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos4.h>
+
+ tmu@100c0000 {
+ compatible = "samsung,exynos4412-tmu";
+ reg = <0x100C0000 0x100>;
+ interrupt-parent = <&combiner>;
+ interrupts = <2 4>;
+ #thermal-sensor-cells = <0>;
+ clocks = <&clock CLK_TMU_APBIF>;
+ clock-names = "tmu_apbif";
+ vtmu-supply = <&ldo10_reg>;
+ };
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ tmu@10068000 {
+ compatible = "samsung,exynos5420-tmu-ext-triminfo";
+ reg = <0x10068000 0x100>, <0x1006c000 0x4>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ #thermal-sensor-cells = <0>;
+ clocks = <&clock 318>, <&clock 318>; /* CLK_TMU */
+ clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+ vtmu-supply = <&ldo7_reg>;
+ };
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ tmu@10060000 {
+ compatible = "samsung,exynos5433-tmu";
+ reg = <0x10060000 0x200>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ #thermal-sensor-cells = <0>;
+ clocks = <&cmu_peris 3>, /* CLK_PCLK_TMU0_APBIF */
+ <&cmu_peris 35>; /* CLK_SCLK_TMU0 */
+ clock-names = "tmu_apbif", "tmu_sclk";
+ vtmu-supply = <&ldo3_reg>;
+ };
--
2.32.0
^ permalink raw reply related
* [PATCH 3/3] MAINTAINERS: thermal: samsung: drop obsolete properties
From: Krzysztof Kozlowski @ 2022-01-22 13:25 UTC (permalink / raw)
To: Rafael J. Wysocki, Daniel Lezcano, Amit Kucheria, Zhang Rui,
Rob Herring, Krzysztof Kozlowski, Bartlomiej Zolnierkiewicz,
linux-pm, devicetree, linux-arm-kernel, linux-samsung-soc,
linux-kernel
In-Reply-To: <20220122132554.65192-1-krzysztof.kozlowski@canonical.com>
Update the Samsung Exynos SoC thermal driver entry to match reality and
add Krzysztof Kozlowski as co-maintainer (as he maintains entire Samsung
SoC). The rationale:
1. Bartlomiej's Samsung email bounces, since he is not working in
Samsung for some time.
2. The mentioned Lukasz Majewski's Git tree was not updated
since 2015.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
MAINTAINERS | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 27730a5a6345..928fb4cebe09 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17118,11 +17118,12 @@ S: Supported
F: drivers/net/ethernet/samsung/sxgbe/
SAMSUNG THERMAL DRIVER
-M: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
+M: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
+M: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
L: linux-pm@vger.kernel.org
L: linux-samsung-soc@vger.kernel.org
-S: Supported
-T: git https://github.com/lmajewski/linux-samsung-thermal.git
+S: Maintained
+F: Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.yaml
F: drivers/thermal/samsung/
SAMSUNG USB2 PHY DRIVER
--
2.32.0
^ permalink raw reply related
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