* Re: [PATCH v3 3/9] ARM: mstar: Add cpupll to base dtsi
From: Daniel Palmer @ 2022-01-23 5:10 UTC (permalink / raw)
To: Romain Perier
Cc: Michael Turquette, Stephen Boyd, linux-clk, Arnd Bergmann,
Rob Herring, DTML, linux-arm-kernel, Linux Kernel Mailing List
In-Reply-To: <20220121193544.23231-4-romain.perier@gmail.com>
Hi Romain,
On Sat, 22 Jan 2022 at 04:35, Romain Perier <romain.perier@gmail.com> wrote:
>
> From: Daniel Palmer <daniel@0x0f.com>
>
> All MStar/SigmaStar ARMv7 SoCs have the CPU PLL at the same
> place so add it to the base dtsi.
>
> Signed-off-by: Daniel Palmer <daniel@0x0f.com>
> ---
> arch/arm/boot/dts/mstar-v7.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
> index 89ebfe4f29da..2249faaa3aa7 100644
> --- a/arch/arm/boot/dts/mstar-v7.dtsi
> +++ b/arch/arm/boot/dts/mstar-v7.dtsi
> @@ -155,6 +155,13 @@ mpll: mpll@206000 {
> clocks = <&xtal>;
> };
>
> + cpupll: cpupll@206400 {
> + compatible = "mstar,msc313-cpupll";
> + reg = <0x206400 0x200>;
> + #clock-cells = <0>;
> + clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
> + };
> +
> gpio: gpio@207800 {
> #gpio-cells = <2>;
> reg = <0x207800 0x200>;
> --
> 2.34.1
>
I guess I can't add a reviewed by for my own commit but this looks good to me.
The same CPUPLL is present on all of the chips seen so far so this is
the right place for this.
Cheers,
Daniel
^ permalink raw reply
* Re: [PATCH v3 8/9] ARM: mstar: Add OPP table for mercury5
From: Daniel Palmer @ 2022-01-23 5:12 UTC (permalink / raw)
To: Romain Perier
Cc: Michael Turquette, Stephen Boyd, linux-clk, Arnd Bergmann,
Rob Herring, DTML, linux-arm-kernel, Linux Kernel Mailing List
In-Reply-To: <20220121193544.23231-9-romain.perier@gmail.com>
Hi Romain,
On Sat, 22 Jan 2022 at 04:35, Romain Perier <romain.perier@gmail.com> wrote:
>
> From: Daniel Palmer <daniel@0x0f.com>
>
> Add an OPP table for mercury5 so that cpu frequency scaling can
> happen.
>
> Signed-off-by: Daniel Palmer <daniel@0x0f.com>
> ---
> arch/arm/boot/dts/mstar-mercury5.dtsi | 36 +++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mstar-mercury5.dtsi b/arch/arm/boot/dts/mstar-mercury5.dtsi
> index a7d0dd9d6132..80a19bd23c9c 100644
> --- a/arch/arm/boot/dts/mstar-mercury5.dtsi
> +++ b/arch/arm/boot/dts/mstar-mercury5.dtsi
> @@ -6,6 +6,42 @@
>
> #include "mstar-v7.dtsi"
>
> +/ {
> + cpu0_opp_table: opp_table0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>;
> + opp-microvolt = <800000 800000 850000>;
> + clock-latency-ns = <300000>;
> + };
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + opp-microvolt = <850000 850000 880000>;
> + clock-latency-ns = <300000>;
> + };
> +
> + opp-400000000 {
> + opp-hz = /bits/ 64 <400000000>;
> + opp-microvolt = <880000 880000 890000>;
> + clock-latency-ns = <300000>;
> + };
> + opp-600000000 {
> + opp-hz = /bits/ 64 <600000000>;
> + opp-microvolt = <900000 900000 1000000>;
> + clock-latency-ns = <300000>;
> + };
> +
> + opp-800000000 {
> + opp-hz = /bits/ 64 <800000000>;
> + opp-microvolt = <900000 900000 1000000>;
> + clock-latency-ns = <300000>;
> + };
> + };
> +};
> +
> &imi {
> reg = <0xa0000000 0x20000>;
> };
> --
> 2.34.1
>
I think we should drop this one when applying as the frequencies need
to be checked on the hardware again.
I think they should probably match the msc313e settings that Willy verified.
Cheers,
Daniel
^ permalink raw reply
* Re: MT7621 SoC Traffic Won't Flow on RGMII2 Bus/2nd GMAC
From: DENG Qingfang @ 2022-01-23 6:51 UTC (permalink / raw)
To: Arınç ÜNAL
Cc: Luiz Angelo Daros de Luca, Matthias Brugger, John Crispin,
Siddhant Gupta, Ilya Lipnitskiy, Sergio Paracuellos,
Felix Fietkau, Sean Wang, Mark Lee, Russell King, Jakub Kicinski,
David Miller, René van Dorst,
moderated list:ARM/Mediatek SoC support, netdev, linux-mips,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
openwrt-devel, erkin.bozoglu
In-Reply-To: <83a35aa3-6cb8-2bc4-2ff4-64278bbcd8c8@arinc9.com>
Hi,
Do you set the ethernet pinmux correctly?
ðernet {
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
};
^ permalink raw reply
* Re: MT7621 SoC Traffic Won't Flow on RGMII2 Bus/2nd GMAC
From: Arınç ÜNAL @ 2022-01-23 8:33 UTC (permalink / raw)
To: DENG Qingfang
Cc: Luiz Angelo Daros de Luca, Matthias Brugger, John Crispin,
Siddhant Gupta, Ilya Lipnitskiy, Sergio Paracuellos,
Felix Fietkau, Sean Wang, Mark Lee, Russell King, Jakub Kicinski,
David Miller, René van Dorst,
moderated list:ARM/Mediatek SoC support, netdev, linux-mips,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
openwrt-devel, erkin.bozoglu
In-Reply-To: <CALW65jZ4N_YRJd8F-uaETWm1Hs3rNcy95csf++rz7vTk8G8oOg@mail.gmail.com>
Hey Deng,
On 23/01/2022 09:51, DENG Qingfang wrote:
> Hi,
>
> Do you set the ethernet pinmux correctly?
>
> ðernet {
> pinctrl-names = "default";
> pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
> };
This fixed it! We did have &rgmii2_pins on the gmac1 node (it was
originally on external_phy) so we never thought to investigate the
pinctrl configuration further! Turns out &rgmii2_pins needs to be
defined on the ethernet node instead.
I'll send a patch to address this on mt7621.dtsi.
You saved us a bunch of time, thank you very much!
Cheers.
Arınç
^ permalink raw reply
* [PATCH 0/4] crypto: Add Xilinx ZynqMP SHA3 driver support
From: Harsha @ 2022-01-23 9:47 UTC (permalink / raw)
To: herbert, davem, linux-crypto, linux-kernel, michals,
linux-arm-kernel, robh+dt, devicetree
Cc: saratcha, harshj, git, Harsha
This patch set does the following:
- Updates the Makefile for xilinx subdirectory
- Adds communication layer support for sha_hash in zynqmp.c
- Adds Xilinx ZynqMP driver for SHA3 Algorithm
- Updates the list of MAINTAINERS
Harsha (4):
drivers: crypto: Updated Makefile for xilinx subdirectory
firmware: xilinx: Add ZynqMP SHA API for SHA3 functionality
crypto: xilinx: Add Xilinx SHA3 driver
MAINTAINERS: Add maintainer for Xilinx ZynqMP SHA3 driver
MAINTAINERS | 5 +
drivers/crypto/Kconfig | 10 ++
drivers/crypto/Makefile | 2 +-
drivers/crypto/xilinx/Makefile | 1 +
drivers/crypto/xilinx/zynqmp-sha.c | 285 +++++++++++++++++++++++++++++++++++
drivers/firmware/xilinx/zynqmp.c | 26 ++++
include/linux/firmware/xlnx-zynqmp.h | 8 +
7 files changed, 336 insertions(+), 1 deletion(-)
create mode 100644 drivers/crypto/xilinx/zynqmp-sha.c
--
1.8.2.1
^ permalink raw reply
* [PATCH 1/4] drivers: crypto: Updated Makefile for xilinx subdirectory
From: Harsha @ 2022-01-23 9:47 UTC (permalink / raw)
To: herbert, davem, linux-crypto, linux-kernel, michals,
linux-arm-kernel, robh+dt, devicetree
Cc: saratcha, harshj, git, Harsha
In-Reply-To: <1642931227-20706-1-git-send-email-harsha.harsha@xilinx.com>
This patch updates the Makefile for xilinx subdirectory.
CONFIG_CRYPTO_DEV_ZYNQMP_AES protects zynqmp-aes-gcm.o and it is used
twice (in drivers/crypto/Makefile and drivers/crypto/xilinx/Makefile)
and it is enough to use it once.
Signed-off-by: Harsha <harsha.harsha@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/crypto/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 1fe5120..0a4fff2 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -47,7 +47,7 @@ obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/
obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/
-obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_AES) += xilinx/
+obj-y += xilinx/
obj-y += hisilicon/
obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/
obj-y += keembay/
--
1.8.2.1
^ permalink raw reply related
* [PATCH 2/4] firmware: xilinx: Add ZynqMP SHA API for SHA3 functionality
From: Harsha @ 2022-01-23 9:47 UTC (permalink / raw)
To: herbert, davem, linux-crypto, linux-kernel, michals,
linux-arm-kernel, robh+dt, devicetree
Cc: saratcha, harshj, git, Harsha
In-Reply-To: <1642931227-20706-1-git-send-email-harsha.harsha@xilinx.com>
This patch adds zynqmp_pm_sha_hash API in the ZynqMP firmware to compute
SHA3 hash of given data.
Signed-off-by: Harsha <harsha.harsha@xilinx.com>
---
drivers/firmware/xilinx/zynqmp.c | 26 ++++++++++++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 8 ++++++++
2 files changed, 34 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 3dd45a7..a84c5ea 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -1117,6 +1117,32 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out)
EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine);
/**
+ * zynqmp_pm_sha_hash - Access the SHA engine to calculate the hash
+ * @address: Address of the data/ Address of output buffer where
+ * hash should be stored.
+ * @size: Size of the data.
+ * @flags:
+ * BIT(0) - for initializing csudma driver and SHA3(Here address
+ * and size inputs can be NULL).
+ * BIT(1) - to call Sha3_Update API which can be called multiple
+ * times when data is not contiguous.
+ * BIT(2) - to get final hash of the whole updated data.
+ * Hash will be overwritten at provided address with
+ * 48 bytes.
+ *
+ * Return: Returns status, either success or error code.
+ */
+int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags)
+{
+ u32 lower_addr = lower_32_bits(address);
+ u32 upper_addr = upper_32_bits(address);
+
+ return zynqmp_pm_invoke_fn(PM_SECURE_SHA, upper_addr, lower_addr,
+ size, flags, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_sha_hash);
+
+/**
* zynqmp_pm_system_shutdown - PM call to request a system shutdown or restart
* @type: Shutdown or restart? 0 for shutdown, 1 for restart
* @subtype: Specifies which system should be restarted or shut down
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 47fd4e5..38ef708 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -78,6 +78,7 @@ enum pm_api_id {
PM_FPGA_LOAD = 22,
PM_FPGA_GET_STATUS = 23,
PM_GET_CHIPID = 24,
+ PM_SECURE_SHA = 26,
PM_PINCTRL_REQUEST = 28,
PM_PINCTRL_RELEASE = 29,
PM_PINCTRL_GET_FUNCTION = 30,
@@ -410,6 +411,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
const u32 qos,
const enum zynqmp_pm_request_ack ack);
int zynqmp_pm_aes_engine(const u64 address, u32 *out);
+int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
int zynqmp_pm_fpga_get_status(u32 *value);
int zynqmp_pm_write_ggs(u32 index, u32 value);
@@ -581,6 +583,12 @@ static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
return -ENODEV;
}
+static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
+ const u32 flags)
+{
+ return -ENODEV;
+}
+
static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
const u32 flags)
{
--
1.8.2.1
^ permalink raw reply related
* [PATCH 4/4] MAINTAINERS: Add maintainer for Xilinx ZynqMP SHA3 driver
From: Harsha @ 2022-01-23 9:47 UTC (permalink / raw)
To: herbert, davem, linux-crypto, linux-kernel, michals,
linux-arm-kernel, robh+dt, devicetree
Cc: saratcha, harshj, git, Harsha
In-Reply-To: <1642931227-20706-1-git-send-email-harsha.harsha@xilinx.com>
This patch adds an entry for ZynqMP SHA3 driver in the list of
Maintainers.
Signed-off-by: Harsha <harsha.harsha@xilinx.com>
---
MAINTAINERS | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4fb3a88..cf2da60 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20931,6 +20931,11 @@ T: git https://github.com/Xilinx/linux-xlnx.git
F: Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
F: drivers/phy/xilinx/phy-zynqmp.c
+XILINX ZYNQMP SHA3 DRIVER
+M: Harsha <harsha.harsha@xilinx.com>
+S: Maintained
+F: drivers/crypto/xilinx/zynqmp-sha.c
+
XILLYBUS DRIVER
M: Eli Billauer <eli.billauer@gmail.com>
L: linux-kernel@vger.kernel.org
--
1.8.2.1
^ permalink raw reply related
* [PATCH 3/4] crypto: xilinx: Add Xilinx SHA3 driver
From: Harsha @ 2022-01-23 9:47 UTC (permalink / raw)
To: herbert, davem, linux-crypto, linux-kernel, michals,
linux-arm-kernel, robh+dt, devicetree
Cc: saratcha, harshj, git, Harsha
In-Reply-To: <1642931227-20706-1-git-send-email-harsha.harsha@xilinx.com>
This patch adds SHA3 driver support for the Xilinx ZynqMP SoC.
Xilinx ZynqMP SoC has SHA3 engine used for secure hash calculation.
The flow is
SHA3 request from Userspace -> SHA3 driver-> ZynqMp driver-> Firmware ->
SHA3 HW Engine
SHA3 HW engine in Xilinx ZynqMP SoC, does not support parallel processing
of 2 hash requests.
Therefore, software fallback is being used for init, update, final,
export and import in the ZynqMP SHA driver
For digest, the calculation of SHA3 hash is done by the hardened
SHA3 accelerator in Xilinx ZynqMP SoC.
Signed-off-by: Harsha <harsha.harsha@xilinx.com>
---
drivers/crypto/Kconfig | 10 ++
drivers/crypto/xilinx/Makefile | 1 +
drivers/crypto/xilinx/zynqmp-sha.c | 285 +++++++++++++++++++++++++++++++++++++
3 files changed, 296 insertions(+)
create mode 100644 drivers/crypto/xilinx/zynqmp-sha.c
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 51690e7..2e43f11 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -796,6 +796,16 @@ config CRYPTO_DEV_ZYNQMP_AES
accelerator. Select this if you want to use the ZynqMP module
for AES algorithms.
+config CRYPTO_DEV_ZYNQMP_SHA3
+ bool "Support for Xilinx ZynqMP SHA3 hardware accelerator"
+ depends on ARCH_ZYNQMP || COMPILE_TEST
+ select CRYPTO_SHA3
+ help
+ Xilinx ZynqMP has SHA3 engine used for secure hash calculation.
+ This driver interfaces with SHA3 hardware engine.
+ Select this if you want to use the ZynqMP module
+ for SHA3 hash computation.
+
source "drivers/crypto/chelsio/Kconfig"
source "drivers/crypto/virtio/Kconfig"
diff --git a/drivers/crypto/xilinx/Makefile b/drivers/crypto/xilinx/Makefile
index 534e32d..730feff 100644
--- a/drivers/crypto/xilinx/Makefile
+++ b/drivers/crypto/xilinx/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_AES) += zynqmp-aes-gcm.o
+obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_SHA3) += zynqmp-sha.o
diff --git a/drivers/crypto/xilinx/zynqmp-sha.c b/drivers/crypto/xilinx/zynqmp-sha.c
new file mode 100644
index 0000000..11f103c
--- /dev/null
+++ b/drivers/crypto/xilinx/zynqmp-sha.c
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx ZynqMP SHA Driver.
+ * Copyright (c) 2022 Xilinx Inc.
+ */
+#include <asm/cacheflush.h>
+#include <crypto/hash.h>
+#include <crypto/internal/hash.h>
+#include <crypto/sha3.h>
+#include <linux/crypto.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#define ZYNQMP_DMA_BIT_MASK 32U
+#define ZYNQMP_DMA_ALLOC_FIXED_SIZE 0x1000U
+
+enum zynqmp_sha_op {
+ ZYNQMP_SHA3_INIT = 1,
+ ZYNQMP_SHA3_UPDATE = 2,
+ ZYNQMP_SHA3_FINAL = 4,
+};
+
+struct zynqmp_sha_drv_ctx {
+ struct shash_alg sha3_384;
+ struct device *dev;
+};
+
+struct zynqmp_sha_tfm_ctx {
+ struct device *dev;
+ struct crypto_shash *fbk_tfm;
+};
+
+struct zynqmp_sha_desc_ctx {
+ struct shash_desc fbk_req;
+};
+
+static dma_addr_t update_dma_addr, final_dma_addr;
+static char *ubuf, *fbuf;
+
+static int zynqmp_sha_init_tfm(struct crypto_shash *hash)
+{
+ const char *fallback_driver_name = crypto_shash_alg_name(hash);
+ struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash);
+ struct shash_alg *alg = crypto_shash_alg(hash);
+ struct crypto_shash *fallback_tfm;
+ struct zynqmp_sha_drv_ctx *drv_ctx;
+
+ drv_ctx = container_of(alg, struct zynqmp_sha_drv_ctx, sha3_384);
+ tfm_ctx->dev = drv_ctx->dev;
+
+ /* Allocate a fallback and abort if it failed. */
+ fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
+ CRYPTO_ALG_NEED_FALLBACK);
+ if (IS_ERR(fallback_tfm))
+ return PTR_ERR(fallback_tfm);
+
+ tfm_ctx->fbk_tfm = fallback_tfm;
+ hash->descsize += crypto_shash_descsize(tfm_ctx->fbk_tfm);
+
+ return 0;
+}
+
+static void zynqmp_sha_exit_tfm(struct crypto_shash *hash)
+{
+ struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash);
+
+ if (tfm_ctx->fbk_tfm) {
+ crypto_free_shash(tfm_ctx->fbk_tfm);
+ tfm_ctx->fbk_tfm = NULL;
+ }
+
+ memzero_explicit(tfm_ctx, sizeof(struct zynqmp_sha_tfm_ctx));
+}
+
+static int zynqmp_sha_init(struct shash_desc *desc)
+{
+ struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+ struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
+
+ dctx->fbk_req.tfm = tctx->fbk_tfm;
+ return crypto_shash_init(&dctx->fbk_req);
+}
+
+static int zynqmp_sha_update(struct shash_desc *desc, const u8 *data, unsigned int length)
+{
+ struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+
+ return crypto_shash_update(&dctx->fbk_req, data, length);
+}
+
+static int zynqmp_sha_final(struct shash_desc *desc, u8 *out)
+{
+ struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+
+ return crypto_shash_final(&dctx->fbk_req, out);
+}
+
+static int zynqmp_sha_finup(struct shash_desc *desc, const u8 *data, unsigned int length, u8 *out)
+{
+ struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+
+ return crypto_shash_finup(&dctx->fbk_req, data, length, out);
+}
+
+static int zynqmp_sha_import(struct shash_desc *desc, const void *in)
+{
+ struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+ struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
+
+ dctx->fbk_req.tfm = tctx->fbk_tfm;
+ return crypto_shash_import(&dctx->fbk_req, in);
+}
+
+static int zynqmp_sha_export(struct shash_desc *desc, void *out)
+{
+ struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+
+ return crypto_shash_export(&dctx->fbk_req, out);
+}
+
+static int zynqmp_sha_digest(struct shash_desc *desc, const u8 *data, unsigned int len, u8 *out)
+{
+ unsigned int remaining_len = len;
+ int update_size;
+ int ret;
+
+ ret = zynqmp_pm_sha_hash(0, 0, ZYNQMP_SHA3_INIT);
+ if (ret)
+ return ret;
+
+ while (remaining_len != 0) {
+ memset(ubuf, 0, ZYNQMP_DMA_ALLOC_FIXED_SIZE);
+ if (remaining_len >= ZYNQMP_DMA_ALLOC_FIXED_SIZE) {
+ update_size = ZYNQMP_DMA_ALLOC_FIXED_SIZE;
+ remaining_len -= ZYNQMP_DMA_ALLOC_FIXED_SIZE;
+ } else {
+ update_size = remaining_len;
+ remaining_len = 0;
+ }
+ memcpy(ubuf, data, update_size);
+ flush_icache_range((unsigned long)ubuf, (unsigned long)ubuf + update_size);
+ ret = zynqmp_pm_sha_hash(update_dma_addr, update_size, ZYNQMP_SHA3_UPDATE);
+ if (ret)
+ return ret;
+
+ data += update_size;
+ }
+
+ ret = zynqmp_pm_sha_hash(final_dma_addr, SHA3_384_DIGEST_SIZE, ZYNQMP_SHA3_FINAL);
+ memcpy(out, fbuf, SHA3_384_DIGEST_SIZE);
+ memset(fbuf, 0, SHA3_384_DIGEST_SIZE);
+
+ return ret;
+}
+
+static struct zynqmp_sha_drv_ctx sha3_drv_ctx = {
+ .sha3_384 = {
+ .init = zynqmp_sha_init,
+ .update = zynqmp_sha_update,
+ .final = zynqmp_sha_final,
+ .finup = zynqmp_sha_finup,
+ .digest = zynqmp_sha_digest,
+ .export = zynqmp_sha_export,
+ .import = zynqmp_sha_import,
+ .init_tfm = zynqmp_sha_init_tfm,
+ .exit_tfm = zynqmp_sha_exit_tfm,
+ .descsize = sizeof(struct zynqmp_sha_desc_ctx),
+ .statesize = sizeof(struct sha3_state),
+ .digestsize = SHA3_384_DIGEST_SIZE,
+ .base = {
+ .cra_name = "sha3-384",
+ .cra_driver_name = "zynqmp-sha3-384",
+ .cra_priority = 300,
+ .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_NEED_FALLBACK,
+ .cra_blocksize = SHA3_384_BLOCK_SIZE,
+ .cra_ctxsize = sizeof(struct zynqmp_sha_tfm_ctx),
+ .cra_alignmask = 3,
+ .cra_module = THIS_MODULE,
+ }
+ }
+};
+
+static int zynqmp_sha_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ int err;
+
+ err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(ZYNQMP_DMA_BIT_MASK));
+ if (err < 0) {
+ dev_err(dev, "No usable DMA configuration\n");
+ return err;
+ }
+
+ err = crypto_register_shash(&sha3_drv_ctx.sha3_384);
+ if (err < 0) {
+ dev_err(dev, "Failed to register shash alg.\n");
+ return err;
+ }
+
+ sha3_drv_ctx.dev = dev;
+ platform_set_drvdata(pdev, &sha3_drv_ctx);
+
+ ubuf = dma_alloc_coherent(dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, &update_dma_addr, GFP_KERNEL);
+ if (!ubuf) {
+ err = -ENOMEM;
+ goto err_shash;
+ }
+
+ fbuf = dma_alloc_coherent(dev, SHA3_384_DIGEST_SIZE, &final_dma_addr, GFP_KERNEL);
+ if (!fbuf) {
+ err = -ENOMEM;
+ goto err_mem;
+ }
+
+ return 0;
+
+err_mem:
+ dma_free_coherent(sha3_drv_ctx.dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, ubuf, update_dma_addr);
+
+err_shash:
+ crypto_unregister_shash(&sha3_drv_ctx.sha3_384);
+
+ return err;
+}
+
+static int zynqmp_sha_remove(struct platform_device *pdev)
+{
+ sha3_drv_ctx.dev = platform_get_drvdata(pdev);
+
+ dma_free_coherent(sha3_drv_ctx.dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, ubuf, update_dma_addr);
+ dma_free_coherent(sha3_drv_ctx.dev, SHA3_384_DIGEST_SIZE, fbuf, final_dma_addr);
+ crypto_unregister_shash(&sha3_drv_ctx.sha3_384);
+
+ return 0;
+}
+
+static struct platform_driver zynqmp_sha_driver = {
+ .probe = zynqmp_sha_probe,
+ .remove = zynqmp_sha_remove,
+ .driver = {
+ .name = "zynqmp-sha3-384",
+ },
+};
+
+static int __init sha_driver_init(void)
+{
+ struct platform_device *pdev;
+ int ret;
+
+ ret = platform_driver_register(&zynqmp_sha_driver);
+ if (ret)
+ return ret;
+
+ pdev = platform_device_register_simple(zynqmp_sha_driver.driver.name,
+ 0, NULL, 0);
+ if (IS_ERR(pdev)) {
+ ret = PTR_ERR(pdev);
+ platform_driver_unregister(&zynqmp_sha_driver);
+ pr_info("Failed to register ZynqMP SHA3 dvixe %d\n", ret);
+ }
+
+ return ret;
+}
+
+device_initcall(sha_driver_init);
+
+static void __exit sha_driver_exit(void)
+{
+ platform_driver_unregister(&zynqmp_sha_driver);
+}
+
+module_platform_driver(zynqmp_sha_driver);
+
+MODULE_DESCRIPTION("ZynqMP SHA3 hardware acceleration support.");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Harsha <harsha.harsha@xilinx.com>");
--
1.8.2.1
^ permalink raw reply related
* [PATCH 00/12] usb: dt-bindings: samsung: convert to dtschema
From: Krzysztof Kozlowski @ 2022-01-23 11:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, linux-usb,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel
Hi,
Dependencies
============
None.
The DTS patches are independent and I will take them via Samsung SoC tree.
I am including them here just so automatic robot checks won't complain about
DTS differences against newly dtschema.
Best regards,
Krzysztof
Krzysztof Kozlowski (12):
arm64: dts: exynos: add USB DWC3 supplies to Espresso board
ARM: dts: exynos: add USB DWC3 supplies to Arndale
ARM: dts: exynos: add USB DWC3 supplies to SMDK5250
ARM: dts: exynos: add USB DWC3 supplies to Chromebook Snow
ARM: dts: exynos: add USB DWC3 supplies to Chromebook Spring
ARM: dts: exynos: add USB DWC3 supplies to ArndaleOcta
ARM: dts: exynos: add USB DWC3 supplies to Chromebook Peach Pit
ARM: dts: exynos: add USB DWC3 supplies to Chromebook Peach Pi
ARM: dts: exynos: add USB DWC3 supplies to SMDK5420
ARM: dts: exynos: add fake USB DWC3 supplies to SMDK5410
dt-bindings: usb: samsung,exynos-dwc3: convert to dtschema
dt-bindings: usb: samsung,exynos-usb2: convert to dtschema
.../devicetree/bindings/usb/exynos-usb.txt | 115 ----------------
.../bindings/usb/samsung,exynos-dwc3.yaml | 129 ++++++++++++++++++
.../bindings/usb/samsung,exynos-usb2.yaml | 117 ++++++++++++++++
arch/arm/boot/dts/exynos5250-arndale.dts | 5 +
arch/arm/boot/dts/exynos5250-smdk5250.dts | 5 +
arch/arm/boot/dts/exynos5250-snow-common.dtsi | 5 +
arch/arm/boot/dts/exynos5250-spring.dts | 5 +
arch/arm/boot/dts/exynos5250.dtsi | 2 +-
arch/arm/boot/dts/exynos5410-smdk5410.dts | 23 ++++
arch/arm/boot/dts/exynos5420-arndale-octa.dts | 10 ++
arch/arm/boot/dts/exynos5420-peach-pit.dts | 10 ++
arch/arm/boot/dts/exynos5420-smdk5420.dts | 10 ++
arch/arm/boot/dts/exynos5800-peach-pi.dts | 10 ++
.../boot/dts/exynos/exynos7-espresso.dts | 5 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +-
15 files changed, 336 insertions(+), 117 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/usb/exynos-usb.txt
create mode 100644 Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml
create mode 100644 Documentation/devicetree/bindings/usb/samsung,exynos-usb2.yaml
--
2.32.0
^ permalink raw reply
* [PATCH 01/12] arm64: dts: exynos: add USB DWC3 supplies to Espresso board
From: Krzysztof Kozlowski @ 2022-01-23 11:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, linux-usb,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel
In-Reply-To: <20220123111644.25540-1-krzysztof.kozlowski@canonical.com>
Add required voltage regulators for USB DWC3 block on Exynos7 Espresso
board. Due to lack of schematics of Espresso board, the choice of
regulators is approximate. What bindings call VDD10, for Exynos7 should
be actually called VDD09 (0.9 V). Use regulators with a matching
voltage range based on vendor sources for Meizu Pro 5 M576 handset (also
with Exynos7420).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 5 +++++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 125c03f351d9..4c45e689d34a 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -412,6 +412,11 @@ &ufs {
status = "okay";
};
+&usbdrd {
+ vdd10-supply = <&ldo4_reg>;
+ vdd33-supply = <&ldo6_reg>;
+};
+
&usbdrd_phy {
vbus-supply = <&usb30_vbus_reg>;
vbus-boost-supply = <&usb3drd_boost_5v>;
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index c3efbc8add38..01b4210d8b62 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -672,7 +672,7 @@ usbdrd_phy: phy@15500000 {
#phy-cells = <1>;
};
- usbdrd3 {
+ usbdrd: usb {
compatible = "samsung,exynos7-dwusb3";
clocks = <&clock_fsys0 ACLK_USBDRD300>,
<&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
--
2.32.0
^ permalink raw reply related
* [PATCH 03/12] ARM: dts: exynos: add USB DWC3 supplies to SMDK5250
From: Krzysztof Kozlowski @ 2022-01-23 11:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, linux-usb,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel
In-Reply-To: <20220123111644.25540-1-krzysztof.kozlowski@canonical.com>
Add required voltage regulators for USB DWC3 block on Exynos5250
SMDK5250 board. Due to lack of board schematics, use same regulators as
on Arndale board.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 39bbe18145cf..53670383d607 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -417,3 +417,8 @@ max77686_irq: max77686-irq {
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
};
+
+&usbdrd {
+ vdd10-supply = <&ldo15_reg>;
+ vdd33-supply = <&ldo12_reg>;
+};
--
2.32.0
^ permalink raw reply related
* [PATCH 04/12] ARM: dts: exynos: add USB DWC3 supplies to Chromebook Snow
From: Krzysztof Kozlowski @ 2022-01-23 11:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, linux-usb,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel
In-Reply-To: <20220123111644.25540-1-krzysztof.kozlowski@canonical.com>
Add required voltage regulators for USB DWC3 block on Exynos5250
Chromebook Snow board. Due to lack of board schematics, use same
regulators as on Arndale board.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm/boot/dts/exynos5250-snow-common.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
index 2335c4687349..ccb32d53d598 100644
--- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
@@ -698,6 +698,11 @@ &spi_1 {
cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>;
};
+&usbdrd {
+ vdd10-supply = <&ldo15_reg>;
+ vdd33-supply = <&ldo12_reg>;
+};
+
&usbdrd_dwc3 {
dr_mode = "host";
};
--
2.32.0
^ permalink raw reply related
* [PATCH 02/12] ARM: dts: exynos: add USB DWC3 supplies to Arndale
From: Krzysztof Kozlowski @ 2022-01-23 11:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, linux-usb,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel
In-Reply-To: <20220123111644.25540-1-krzysztof.kozlowski@canonical.com>
Add required voltage regulators for USB DWC3 block on Exynos5250 Arndale
board.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm/boot/dts/exynos5250-arndale.dts | 5 +++++
arch/arm/boot/dts/exynos5250.dtsi | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 3583095fbb2a..e639cf6d9b64 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -632,3 +632,8 @@ i2c_ddc: i2c-10 {
#size-cells = <0>;
};
};
+
+&usbdrd {
+ vdd10-supply = <&ldo15_reg>;
+ vdd33-supply = <&ldo12_reg>;
+};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 139778928b93..a6f48f31f618 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -637,7 +637,7 @@ i2s2: i2s@12d70000 {
#sound-dai-cells = <1>;
};
- usb_dwc3 {
+ usbdrd: usb3 {
compatible = "samsung,exynos5250-dwusb3";
clocks = <&clock CLK_USB3>;
clock-names = "usbdrd30";
--
2.32.0
^ permalink raw reply related
* [PATCH 05/12] ARM: dts: exynos: add USB DWC3 supplies to Chromebook Spring
From: Krzysztof Kozlowski @ 2022-01-23 11:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, linux-usb,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel
In-Reply-To: <20220123111644.25540-1-krzysztof.kozlowski@canonical.com>
Add required voltage regulators for USB DWC3 block on Exynos5250
Chromebook Spring board. Due to lack of board schematics, use same
regulators as on Arndale board.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm/boot/dts/exynos5250-spring.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index e0feedcf54bb..138f51f974c7 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -553,4 +553,9 @@ &spi_1 {
num-cs = <1>;
};
+&usbdrd {
+ vdd10-supply = <&ldo15_reg>;
+ vdd33-supply = <&ldo12_reg>;
+};
+
#include "cros-ec-keyboard.dtsi"
--
2.32.0
^ permalink raw reply related
* [PATCH 06/12] ARM: dts: exynos: add USB DWC3 supplies to ArndaleOcta
From: Krzysztof Kozlowski @ 2022-01-23 11:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, linux-usb,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel
In-Reply-To: <20220123111644.25540-1-krzysztof.kozlowski@canonical.com>
Add required voltage regulators for USB DWC3 block on Exynos5420
ArndaleOcta board.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm/boot/dts/exynos5420-arndale-octa.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index dfc7f14f5772..ffdf0e247c15 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -825,3 +825,13 @@ &rtc {
&usbdrd_dwc3_1 {
dr_mode = "host";
};
+
+&usbdrd3_0 {
+ vdd10-supply = <&ldo11_reg>;
+ vdd33-supply = <&ldo9_reg>;
+};
+
+&usbdrd3_1 {
+ vdd10-supply = <&ldo11_reg>;
+ vdd33-supply = <&ldo9_reg>;
+};
--
2.32.0
^ permalink raw reply related
* [PATCH 09/12] ARM: dts: exynos: add USB DWC3 supplies to SMDK5420
From: Krzysztof Kozlowski @ 2022-01-23 11:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, linux-usb,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel
In-Reply-To: <20220123111644.25540-1-krzysztof.kozlowski@canonical.com>
Add required voltage regulators for USB DWC3 block on Exynos5420
SMDK5420 board. Due to lack of board schematics, use same
regulators as on ArndaleOcta board.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index a4f0e3ffedbd..69ce3e430863 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -407,6 +407,16 @@ &rtc {
clock-names = "rtc", "rtc_src";
};
+&usbdrd3_0 {
+ vdd10-supply = <&ldo11_reg>;
+ vdd33-supply = <&ldo9_reg>;
+};
+
+&usbdrd3_1 {
+ vdd10-supply = <&ldo11_reg>;
+ vdd33-supply = <&ldo9_reg>;
+};
+
&usbdrd_phy0 {
vbus-supply = <&usb300_vbus_reg>;
};
--
2.32.0
^ permalink raw reply related
* [PATCH 11/12] dt-bindings: usb: samsung,exynos-dwc3: convert to dtschema
From: Krzysztof Kozlowski @ 2022-01-23 11:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, linux-usb,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel
In-Reply-To: <20220123111644.25540-1-krzysztof.kozlowski@canonical.com>
Convert the Samsung Exynos SoC USB 3.0 DWC3 Controller bindings to DT
schema format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../devicetree/bindings/usb/exynos-usb.txt | 49 -------
.../bindings/usb/samsung,exynos-dwc3.yaml | 129 ++++++++++++++++++
2 files changed, 129 insertions(+), 49 deletions(-)
create mode 100644 Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index f7ae79825d7d..61c03c0ef19f 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -64,52 +64,3 @@ Example:
phys = <&usb2phy 1>;
phy-names = "host";
};
-
-DWC3
-Required properties:
- - compatible: should be one of the following -
- "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on
- Exynos5250/5420.
- "samsung,exynos5433-dwusb3": for USB 3.0 DWC3 controller on
- Exynos5433.
- "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7.
- - #address-cells, #size-cells : should be '1' if the device has sub-nodes
- with 'reg' property.
- - ranges: allows valid 1:1 translation between child's address space and
- parent's address space
- - clocks: Clock IDs array as required by the controller.
- - clock-names: Names of clocks corresponding to IDs in the clock property.
- Following clock names shall be provided for different
- compatibles:
- - samsung,exynos5250-dwusb3: "usbdrd30",
- - samsung,exynos5433-dwusb3: "aclk", "susp_clk", "pipe_pclk",
- "phyclk",
- - samsung,exynos7-dwusb3: "usbdrd30", "usbdrd30_susp_clk",
- "usbdrd30_axius_clk"
- - vdd10-supply: 1.0V powr supply
- - vdd33-supply: 3.0V/3.3V power supply
-
-Sub-nodes:
-The dwc3 core should be added as subnode to Exynos dwc3 glue.
-- dwc3 :
- The binding details of dwc3 can be found in:
- Documentation/devicetree/bindings/usb/snps,dwc3.yaml
-
-Example:
- usb@12000000 {
- compatible = "samsung,exynos5250-dwusb3";
- clocks = <&clock 286>;
- clock-names = "usbdrd30";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- vdd10-supply = <&ldo11_reg>;
- vdd33-supply = <&ldo9_reg>;
-
- dwc3 {
- compatible = "synopsys,dwc3";
- reg = <0x12000000 0x10000>;
- interrupts = <0 72 0>;
- usb-phy = <&usb2_phy &usb3_phy>;
- };
- };
diff --git a/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml b/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml
new file mode 100644
index 000000000000..22b91a27d776
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/samsung,exynos-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC USB 3.0 DWC3 Controller
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos5250-dwusb3
+ - samsung,exynos5433-dwusb3
+ - samsung,exynos7-dwusb3
+
+ '#address-cells':
+ const: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+
+ ranges: true
+
+ '#size-cells':
+ const: 1
+
+ vdd10-supply:
+ description: 1.0V power supply
+
+ vdd33-supply:
+ description: 3.0V/3.3V power supply
+
+patternProperties:
+ "^usb@[0-9a-f]+$":
+ $ref: snps,dwc3.yaml#
+ description: Required child node
+
+required:
+ - compatible
+ - '#address-cells'
+ - clocks
+ - clock-names
+ - ranges
+ - '#size-cells'
+ - vdd10-supply
+ - vdd33-supply
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5250-dwusb3
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ - const: usbdrd30
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos54333-dwusb3
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: aclk
+ - const: susp_clk
+ - const: pipe_pclk
+ - const: phyclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-dwusb3
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: usbdrd30
+ - const: usbdrd30_susp_clk
+ - const: usbdrd30_axius_clk
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5420.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ usb {
+ compatible = "samsung,exynos5250-dwusb3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&clock CLK_USBD300>;
+ clock-names = "usbdrd30";
+ vdd33-supply = <&ldo9_reg>;
+ vdd10-supply = <&ldo11_reg>;
+
+ usb@12000000 {
+ compatible = "snps,dwc3";
+ reg = <0x12000000 0x10000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ snps,dis_u3_susphy_quirk;
+ };
+ };
--
2.32.0
^ permalink raw reply related
* [PATCH 12/12] dt-bindings: usb: samsung,exynos-usb2: convert to dtschema
From: Krzysztof Kozlowski @ 2022-01-23 11:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, linux-usb,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel
In-Reply-To: <20220123111644.25540-1-krzysztof.kozlowski@canonical.com>
Convert the Samsung Exynos SoC USB 2.0 EHCI and OHCI Controller bindings
to DT schema format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../devicetree/bindings/usb/exynos-usb.txt | 66 ----------
.../bindings/usb/samsung,exynos-usb2.yaml | 117 ++++++++++++++++++
2 files changed, 117 insertions(+), 66 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/usb/exynos-usb.txt
create mode 100644 Documentation/devicetree/bindings/usb/samsung,exynos-usb2.yaml
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
deleted file mode 100644
index 61c03c0ef19f..000000000000
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ /dev/null
@@ -1,66 +0,0 @@
-Samsung Exynos SoC USB controller
-
-The USB devices interface with USB controllers on Exynos SOCs.
-The device node has following properties.
-
-EHCI
-Required properties:
- - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
- EHCI controller in host mode.
- - reg: physical base address of the controller and length of memory mapped
- region.
- - interrupts: interrupt number to the cpu.
- - clocks: from common clock binding: handle to usb clock.
- - clock-names: from common clock binding: Shall be "usbhost".
- - phys: from the *Generic PHY* bindings; array specifying phy(s) used
- by the root port.
- - phy-names: from the *Generic PHY* bindings; array of the names for
- each phy for the root ports, must be a subset of the following:
- "host", "hsic0", "hsic1".
-
-Optional properties:
- - samsung,vbus-gpio: if present, specifies the GPIO that
- needs to be pulled up for the bus to be powered.
-
-Example:
-
- usb@12110000 {
- compatible = "samsung,exynos4210-ehci";
- reg = <0x12110000 0x100>;
- interrupts = <0 71 0>;
- samsung,vbus-gpio = <&gpx2 6 1 3 3>;
-
- clocks = <&clock 285>;
- clock-names = "usbhost";
-
- phys = <&usb2phy 1>;
- phy-names = "host";
- };
-
-OHCI
-Required properties:
- - compatible: should be "samsung,exynos4210-ohci" for USB 2.0
- OHCI companion controller in host mode.
- - reg: physical base address of the controller and length of memory mapped
- region.
- - interrupts: interrupt number to the cpu.
- - clocks: from common clock binding: handle to usb clock.
- - clock-names: from common clock binding: Shall be "usbhost".
- - phys: from the *Generic PHY* bindings; array specifying phy(s) used
- by the root port.
- - phy-names: from the *Generic PHY* bindings; array of the names for
- each phy for the root ports, must be a subset of the following:
- "host", "hsic0", "hsic1".
-
-Example:
- usb@12120000 {
- compatible = "samsung,exynos4210-ohci";
- reg = <0x12120000 0x100>;
- interrupts = <0 71 0>;
-
- clocks = <&clock 285>;
- clock-names = "usbhost";
-
- phys = <&usb2phy 1>;
- phy-names = "host";
- };
diff --git a/Documentation/devicetree/bindings/usb/samsung,exynos-usb2.yaml b/Documentation/devicetree/bindings/usb/samsung,exynos-usb2.yaml
new file mode 100644
index 000000000000..fbf07d6e707a
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/samsung,exynos-usb2.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/samsung,exynos-usb2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC USB 2.0 EHCI/OHCI Controller
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos4210-ehci
+ - samsung,exynos4210-ohci
+
+ '#address-cells':
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: usbhost
+
+ interrupts:
+ maxItems: 1
+
+ phys:
+ minItems: 1
+ maxItems: 3
+
+ phy-names:
+ items:
+ enum: [host, hsic0, hsic1]
+ minItems: 1
+ maxItems: 3
+
+ reg:
+ maxItems: 1
+
+ samsung,vbus-gpio:
+ description:
+ Only for controller in EHCI mode, if present, specifies the GPIO that
+ needs to be pulled up for the bus to be powered.
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ "^.*@[0-9a-f]{1,2}$":
+ description: The hard wired USB devices
+ type: object
+ $ref: /usb/usb-device.yaml
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - interrupts
+ - phys
+ - phy-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos4210-ohci
+ then:
+ properties:
+ samsung,vbus-gpio: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5420.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ usb@12110000 {
+ compatible = "samsung,exynos4210-ehci";
+ reg = <0x12110000 0x100>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_USBH20>;
+ clock-names = "usbhost";
+ phys = <&usb2_phy 0>;
+ phy-names = "host";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hub@1 {
+ compatible = "usb0424,9514";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbether@1 {
+ compatible = "usb0424,ec00";
+ reg = <1>;
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ };
+ };
+
+ usb@12120000 {
+ compatible = "samsung,exynos4210-ohci";
+ reg = <0x12120000 0x100>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_USBH20>;
+ clock-names = "usbhost";
+ phys = <&usb2_phy 0>;
+ phy-names = "host";
+ };
--
2.32.0
^ permalink raw reply related
* [PATCH 10/12] ARM: dts: exynos: add fake USB DWC3 supplies to SMDK5410
From: Krzysztof Kozlowski @ 2022-01-23 11:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, linux-usb,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel
In-Reply-To: <20220123111644.25540-1-krzysztof.kozlowski@canonical.com>
Add dummy/fake voltage regulators for USB DWC3 block on Exynos5410
SMDK5410 board. These regulators are required by dtschema, however the
SMDK5410 board does not define the PMIC providing regulators. Use dummy
fixed-regulators just to satisfy the dtschema checks.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm/boot/dts/exynos5410-smdk5410.dts | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
index 2a3ade77a2de..eae69e857247 100644
--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -41,6 +41,19 @@ firmware@2037000 {
reg = <0x02037000 0x1000>;
};
+ vdd10_usb3: voltage-regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD10_USB3";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ vdd33_usb3: voltage-regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD33_USB3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
&mmc_0 {
@@ -121,3 +134,13 @@ &serial_1 {
&serial_2 {
status = "okay";
};
+
+&usbdrd3_0 {
+ vdd10-supply = <&vdd10_usb3>;
+ vdd33-supply = <&vdd33_usb3>;
+};
+
+&usbdrd3_1 {
+ vdd10-supply = <&vdd10_usb3>;
+ vdd33-supply = <&vdd33_usb3>;
+};
--
2.32.0
^ permalink raw reply related
* [PATCH 07/12] ARM: dts: exynos: add USB DWC3 supplies to Chromebook Peach Pit
From: Krzysztof Kozlowski @ 2022-01-23 11:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, linux-usb,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel
In-Reply-To: <20220123111644.25540-1-krzysztof.kozlowski@canonical.com>
Add required voltage regulators for USB DWC3 block on Exynos5420
Chromebook Peach Pit board. Due to lack of board schematics, use same
regulators as on Odroid XU board (using same MAX77802 PMIC).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm/boot/dts/exynos5420-peach-pit.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index e76fb104db19..6252089e4350 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -1090,6 +1090,16 @@ &tmu_gpu {
vtmu-supply = <&ldo10_reg>;
};
+&usbdrd3_0 {
+ vdd10-supply = <&ldo15_reg>;
+ vdd33-supply = <&ldo12_reg>;
+};
+
+&usbdrd3_1 {
+ vdd10-supply = <&ldo15_reg>;
+ vdd33-supply = <&ldo12_reg>;
+};
+
&usbdrd_dwc3_0 {
dr_mode = "host";
};
--
2.32.0
^ permalink raw reply related
* [PATCH 08/12] ARM: dts: exynos: add USB DWC3 supplies to Chromebook Peach Pi
From: Krzysztof Kozlowski @ 2022-01-23 11:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, linux-usb,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel
In-Reply-To: <20220123111644.25540-1-krzysztof.kozlowski@canonical.com>
Add required voltage regulators for USB DWC3 block on Exynos5800
Chromebook Peach Pi board. Due to lack of board schematics, use same
regulators as on Odroid XU board (using same MAX77802 PMIC).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm/boot/dts/exynos5800-peach-pi.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 77013ee586f8..fd6f80a9c64e 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -1072,6 +1072,16 @@ &tmu_gpu {
vtmu-supply = <&ldo10_reg>;
};
+&usbdrd3_0 {
+ vdd10-supply = <&ldo15_reg>;
+ vdd33-supply = <&ldo12_reg>;
+};
+
+&usbdrd3_1 {
+ vdd10-supply = <&ldo15_reg>;
+ vdd33-supply = <&ldo12_reg>;
+};
+
&usbdrd_dwc3_0 {
dr_mode = "host";
};
--
2.32.0
^ permalink raw reply related
* Re: [PATCH v2 00/28] pinctrl: dt-bindings: samsung: convert to dtschema
From: Krzysztof Kozlowski @ 2022-01-23 11:46 UTC (permalink / raw)
To: linux-kernel, Krzysztof Kozlowski, Rob Herring, linux-gpio,
Linus Walleij, Sylwester Nawrocki, Tomasz Figa, devicetree,
linux-arm-kernel, linux-samsung-soc
Cc: Marek Szyprowski, Chanho Park, Sam Protsenko, Alim Akhtar
In-Reply-To: <20220111201426.326777-1-krzysztof.kozlowski@canonical.com>
On Tue, 11 Jan 2022 21:13:58 +0100, Krzysztof Kozlowski wrote:
> Changes since v1
> ================
> 1. Patch #1: add missing pin assignment (Alim).
> 2. Patch #2: correct double sizeof() (Alim).
> 3. Patch #7, #8: put label-override in proper patch (Alim).
> 4. Patch #24: Extend doc, change the 'if' clause for wake-up interrupts.
> 5. New patches: #25 - #28.
> Exynos850 and ExynosAutov9 seems to be different in pin ctrl interrupt
> handling, so they need their own compatibles.
> Please kindly review and provide feedback on these as I do not have
> details.
> 6. Add review tags.
>
> [...]
Applied, thanks!
To Samsung pinctrl tree:
[01/28] pinctrl: samsung: drop pin banks references on error paths
commit: 50ebd19e3585b9792e994cfa8cbee8947fe06371
[02/28] pinctrl: samsung: accept GPIO bank nodes with a suffix
commit: a29681b0cc3778c9ff6abdbcad579cba776dbb81
[24/28] dt-bindings: pinctrl: samsung: convert to dtschema
commit: af030d83da1dc0d750d7bcc88d57dd1cae5f6b61
[25/28] dt-bindings: pinctrl: samsung: describe Exynos850 and ExynosAutov9 wake-ups
commit: 1755e227c21636ade047dc9b920f647c1d53b4e9
[26/28] pinctrl: samsung: add support for Exynos850 and ExynosAutov9 wake-ups
commit: 832ae134ccc1c78a2f5ec81b7010dd24c3c49535
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
^ permalink raw reply
* [PATCH v1] arm64: dts: rk356x: fix dma-controller warning
From: Frank Wunderlich @ 2022-01-23 13:36 UTC (permalink / raw)
To: linux-rockchip
Cc: Frank Wunderlich, Rob Herring, Heiko Stuebner, Michael Riesch,
devicetree, linux-arm-kernel, linux-kernel
From: Frank Wunderlich <frank-w@public-files.de>
DMA-Cotrollers defined in rk356x.dtsi do not match the pattern in bindings.
arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dt.yaml:
dmac@fe530000: $nodename:0: 'dmac@fe530000' does not match '^dma-controller(@.*)?$'
From schema: Documentation/devicetree/bindings/dma/arm,pl330.yaml
arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dt.yaml:
dmac@fe550000: $nodename:0: 'dmac@fe550000' does not match '^dma-controller(@.*)?$'
From schema: Documentation/devicetree/bindings/dma/arm,pl330.yaml
This Patch fixes it.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index a68033a23975..8ccce54ee8e7 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -651,7 +651,7 @@ &i2s1m0_sdo0 &i2s1m0_sdo1
status = "disabled";
};
- dmac0: dmac@fe530000 {
+ dmac0: dma-controller@fe530000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xfe530000 0x0 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
@@ -662,7 +662,7 @@ dmac0: dmac@fe530000 {
#dma-cells = <1>;
};
- dmac1: dmac@fe550000 {
+ dmac1: dma-controller@fe550000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xfe550000 0x0 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
--
2.25.1
^ permalink raw reply related
* Re: Aw: Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0
From: Heiko Stuebner @ 2022-01-23 13:38 UTC (permalink / raw)
To: Frank Wunderlich
Cc: Peter Geis, Johan Jonker, Frank Wunderlich,
open list:ARM/Rockchip SoC..., Rob Herring, devicetree,
arm-mail-list, Linux Kernel Mailing List
In-Reply-To: <trinity-d0efbf68-ed45-47d4-97b3-d3788c5a9de6-1642863025116@3c-app-gmx-bap44>
Hi Frank,
Am Samstag, 22. Januar 2022, 15:50:25 CET schrieb Frank Wunderlich:
> i plan to send a v2 of the series after 5.17-rc1 is out, because i have now verified
> the functions from gpio header and found some pinctrl-changes. V1 had only prepared
> the nodes to know which devices are present on this header.
>
> should i include this patch again or do you pull it from v1 (maybe as fix)?
I do plan to include this as fix after -rc1, but I just saw that you already sent
a separate patch of it, so I'll take that one instead :-)
Heiko
>
> regards Frank
>
>
> > Gesendet: Montag, 17. Januar 2022 um 22:05 Uhr
> > Von: "Heiko Stübner" <heiko@sntech.de>
>
> > From looking at the documentation I got the impression that the
> > pclk_xpcs is related to the separate qsgmii_pcs in the memory map.
> >
> > So yes, I fully agree to dropping this clock from here and then adding
> > them to whatever ip block really needs it.
>
^ permalink raw reply
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