* Re: [PATCH V2 1/3] dt-bindings: spi: Convert spi-slave-mt27xx to json-schema
From: Leilk Liu @ 2022-01-24 5:54 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Brown, Matthias Brugger, devicetree, linux-kernel,
linux-arm-kernel, linux-spi, linux-mediatek
In-Reply-To: <YetVd7IR7FDt+nz3@robh.at.kernel.org>
On Fri, 2022-01-21 at 18:53 -0600, Rob Herring wrote:
> On Wed, Jan 12, 2022 at 06:36:07PM +0800, Leilk Liu wrote:
> > Convert Mediatek ARM SOC's SPI Slave controller binding
> > to json-schema format.
> >
> > Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
> > ---
> > .../spi/mediatek,spi-slave-mt27xx.yaml | 73
> > +++++++++++++++++++
> > .../bindings/spi/spi-slave-mt27xx.txt | 33 ---------
> > 2 files changed, 73 insertions(+), 33 deletions(-)
> > create mode 100644
> > Documentation/devicetree/bindings/spi/mediatek,spi-slave-
> > mt27xx.yaml
> > delete mode 100644 Documentation/devicetree/bindings/spi/spi-
> > slave-mt27xx.txt
> >
> > diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-
> > slave-mt27xx.yaml
> > b/Documentation/devicetree/bindings/spi/mediatek,spi-slave-
> > mt27xx.yaml
> > new file mode 100644
> > index 000000000000..3364fff08cca
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-slave-
> > mt27xx.yaml
> > @@ -0,0 +1,73 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > http://devicetree.org/schemas/spi/mediatek,spi-slave-mt27xx.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: SPI Slave controller for MediaTek ARM SoCs
> > +
> > +maintainers:
> > + - Leilk Liu <leilk.liu@mediatek.com>
> > +
> > +allOf:
> > + - $ref: /spi/spi-controller.yaml#
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - enum:
> > + - mediatek,mt2712-spi-slave
> > + - items:
> > + - enum:
> > + - mediatek,mt8195-spi-slave
>
> Just:
>
> enum:
> - mediatek,mt2712-spi-slave
> - mediatek,mt8195-spi-slave
>
OK, I'll fix it.
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: clock used for the clock gate
>
> Just 'maxItems: 1'
>
OK, I'll fix it.
> > +
> > + clock-names:
> > + items:
> > + - const: spi
> > +
> > + assigned-clocks:
> > + maxItems: 1
> > + description: |
> > + The mux clock for the given platform.
> > +
> > + assigned-clock-parents:
> > + maxItems: 1
> > + description: |
> > + The parent of mux clock for the given platform.
>
> You can drop assigned-clocks. They are always allowed on nodes with
> 'clocks'.
>
OK, I'll fix it.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > + - clock-names
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt2712-clk.h>
> > + #include <dt-bindings/gpio/gpio.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > +
> > + spi@10013000 {
> > + compatible = "mediatek,mt2712-spi-slave";
> > + reg = <0x10013000 0x100>;
> > + interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&infracfg CLK_INFRA_AO_SPI1>;
> > + clock-names = "spi";
> > + assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
> > + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
> > + };
^ permalink raw reply
* Re: [PATCH V2 2/3] dt-bindings: spi: Convert spi-mt65xx to json-schema
From: Leilk Liu @ 2022-01-24 5:54 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Brown, Matthias Brugger, devicetree, linux-kernel,
linux-arm-kernel, linux-spi, linux-mediatek
In-Reply-To: <YetWXSzugRwKb+xA@robh.at.kernel.org>
On Fri, 2022-01-21 at 18:57 -0600, Rob Herring wrote:
> On Wed, Jan 12, 2022 at 06:36:08PM +0800, Leilk Liu wrote:
> > Convert Mediatek ARM SOC's SPI Master controller binding
> > to json-schema format.
> >
> > Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
> > ---
> > .../bindings/spi/mediatek,spi-mt65xx.yaml | 99
> > +++++++++++++++++++
> > .../devicetree/bindings/spi/spi-mt65xx.txt | 68 -------------
> > 2 files changed, 99 insertions(+), 68 deletions(-)
> > create mode 100644
> > Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
> > delete mode 100644 Documentation/devicetree/bindings/spi/spi-
> > mt65xx.txt
> >
> > diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-
> > mt65xx.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-
> > mt65xx.yaml
> > new file mode 100644
> > index 000000000000..71f0cf6e5d70
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-
> > mt65xx.yaml
> > @@ -0,0 +1,99 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: SPI Bus controller for MediaTek ARM SoCs
> > +
> > +maintainers:
> > + - Leilk Liu <leilk.liu@mediatek.com>
> > +
> > +allOf:
> > + - $ref: /spi/spi-controller.yaml#
>
> /schemas/spi/spi-controller.yaml#
>
OK, I'll fix it.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - enum:
> > + - mediatek,mt7629-spi
> > + - const: mediatek,mt7622-spi
> > + - items:
> > + - enum:
> > + - mediatek,mt8516-spi
> > + - const: mediatek,mt2712-spi
> > + - items:
> > + - enum:
> > + - mediatek,mt6779-spi
> > + - mediatek,mt8192-spi
> > + - mediatek,mt8195-spi
> > + - const: mediatek,mt6765-spi
> > + - const: mediatek,mt2701-spi
> > + - const: mediatek,mt2712-spi
> > + - const: mediatek,mt6589-spi
> > + - const: mediatek,mt6765-spi
> > + - const: mediatek,mt6893-spi
> > + - const: mediatek,mt7622-spi
> > + - const: mediatek,mt8135-spi
> > + - const: mediatek,mt8173-spi
> > + - const: mediatek,mt8183-spi
>
> All these can be 1 enum.
>
OK, I'll fix it.
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: clock used for the parent clock
> > + - description: clock used for the muxes clock
> > + - description: clock used for the clock gate
> > +
> > + clock-names:
> > + items:
> > + - const: parent-clk
> > + - const: sel-clk
> > + - const: spi-clk
> > +
> > + mediatek,pad-select:
> > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > + maxItems: 4
> > + items:
> > + enum: [0, 1, 2, 3]
> > + description:
> > + specify which pins group(ck/mi/mo/cs) spi controller used.
> > + This is an array.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > + - clock-names
> > + - '#address-cells'
> > + - '#size-cells'
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8173-clk.h>
> > + #include <dt-bindings/gpio/gpio.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > +
> > + spi@1100a000 {
> > + compatible = "mediatek,mt8173-spi";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x1100a000 0x1000>;
> > + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
> > + <&topckgen CLK_TOP_SPI_SEL>,
> > + <&pericfg CLK_PERI_SPI0>;
> > + clock-names = "parent-clk", "sel-clk", "spi-clk";
> > + cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72
> > GPIO_ACTIVE_LOW>;
> > + mediatek,pad-select = <1>, <0>;
> > + };
^ permalink raw reply
* [PATCH V3 0/3] Add compatible for Mediatek MT8186
From: Leilk Liu @ 2022-01-24 6:12 UTC (permalink / raw)
To: Mark Brown, Rob Herring
Cc: Matthias Brugger, devicetree, linux-kernel, linux-arm-kernel,
linux-spi, linux-mediatek
Subject: [PATCH V3 0/3] Add compatible for Mediatek MT8186
v3:
1. Fix Rob review comment in v2.
v2:
1. Fix Rob review comment.
2. split spi-mt65xx & spi-slave-mt27xx to 2 patches.
Leilk Liu (3):
dt-bindings: spi: Convert spi-slave-mt27xx to json-schema
dt-bindings: spi: Convert spi-mt65xx to json-schema
dt-bindings: spi: Add compatible for Mediatek MT8186
.../bindings/spi/mediatek,spi-mt65xx.yaml | 102 ++++++++++++++++++
.../spi/mediatek,spi-slave-mt27xx.yaml | 58 ++++++++++
.../devicetree/bindings/spi/spi-mt65xx.txt | 68 ------------
.../bindings/spi/spi-slave-mt27xx.txt | 33 ------
4 files changed, 160 insertions(+), 101 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
create mode 100644 Documentation/devicetree/bindings/spi/mediatek,spi-slave-mt27xx.yaml
delete mode 100644 Documentation/devicetree/bindings/spi/spi-mt65xx.txt
delete mode 100644 Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt
--
2.18.0
^ permalink raw reply
* [PATCH V3 2/2] dt-bindings: spi: Add compatible for Mediatek MT8186
From: Leilk Liu @ 2022-01-24 6:12 UTC (permalink / raw)
To: Mark Brown, Rob Herring
Cc: Matthias Brugger, devicetree, linux-kernel, linux-arm-kernel,
linux-spi, linux-mediatek, Leilk Liu, Rob Herring
In-Reply-To: <20220124061238.7854-1-leilk.liu@mediatek.com>
This commit adds dt-binding documentation of spi bus for Mediatek MT8186 SoC
Platform.
Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
index ea977fba49a7..bfa44acb1bdd 100644
--- a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
+++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
@@ -26,6 +26,7 @@ properties:
- items:
- enum:
- mediatek,mt6779-spi
+ - mediatek,mt8186-spi
- mediatek,mt8192-spi
- mediatek,mt8195-spi
- const: mediatek,mt6765-spi
--
2.25.1
^ permalink raw reply related
* [PATCH V3 1/2] dt-bindings: spi: Convert spi-mt65xx to json-schema
From: Leilk Liu @ 2022-01-24 6:12 UTC (permalink / raw)
To: Mark Brown, Rob Herring
Cc: Matthias Brugger, devicetree, linux-kernel, linux-arm-kernel,
linux-spi, linux-mediatek, Leilk Liu
In-Reply-To: <20220124061238.7854-1-leilk.liu@mediatek.com>
Convert Mediatek ARM SOC's SPI Master controller binding
to json-schema format.
Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
---
.../bindings/spi/mediatek,spi-mt65xx.yaml | 101 ++++++++++++++++++
.../devicetree/bindings/spi/spi-mt65xx.txt | 68 ------------
2 files changed, 101 insertions(+), 68 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
delete mode 100644 Documentation/devicetree/bindings/spi/spi-mt65xx.txt
diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
new file mode 100644
index 000000000000..ea977fba49a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SPI Bus controller for MediaTek ARM SoCs
+
+maintainers:
+ - Leilk Liu <leilk.liu@mediatek.com>
+
+allOf:
+ - $ref: "/schemas/spi/spi-controller.yaml#"
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - mediatek,mt7629-spi
+ - const: mediatek,mt7622-spi
+ - items:
+ - enum:
+ - mediatek,mt8516-spi
+ - const: mediatek,mt2712-spi
+ - items:
+ - enum:
+ - mediatek,mt6779-spi
+ - mediatek,mt8192-spi
+ - mediatek,mt8195-spi
+ - const: mediatek,mt6765-spi
+ - items:
+ - enum:
+ - mediatek,mt2701-spi
+ - mediatek,mt2712-spi
+ - mediatek,mt6589-spi
+ - mediatek,mt6765-spi
+ - mediatek,mt6893-spi
+ - mediatek,mt7622-spi
+ - mediatek,mt8135-spi
+ - mediatek,mt8173-spi
+ - mediatek,mt8183-spi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: clock used for the parent clock
+ - description: clock used for the muxes clock
+ - description: clock used for the clock gate
+
+ clock-names:
+ items:
+ - const: parent-clk
+ - const: sel-clk
+ - const: spi-clk
+
+ mediatek,pad-select:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ maxItems: 4
+ items:
+ enum: [0, 1, 2, 3]
+ description:
+ specify which pins group(ck/mi/mo/cs) spi controller used.
+ This is an array.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - '#address-cells'
+ - '#size-cells'
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ spi@1100a000 {
+ compatible = "mediatek,mt8173-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1100a000 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&pericfg CLK_PERI_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
+ mediatek,pad-select = <1>, <0>;
+ };
diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
deleted file mode 100644
index 2a24969159cc..000000000000
--- a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
+++ /dev/null
@@ -1,68 +0,0 @@
-Binding for MTK SPI controller
-
-Required properties:
-- compatible: should be one of the following.
- - mediatek,mt2701-spi: for mt2701 platforms
- - mediatek,mt2712-spi: for mt2712 platforms
- - mediatek,mt6589-spi: for mt6589 platforms
- - mediatek,mt6765-spi: for mt6765 platforms
- - mediatek,mt7622-spi: for mt7622 platforms
- - "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms
- - mediatek,mt8135-spi: for mt8135 platforms
- - mediatek,mt8173-spi: for mt8173 platforms
- - mediatek,mt8183-spi: for mt8183 platforms
- - mediatek,mt6893-spi: for mt6893 platforms
- - "mediatek,mt8192-spi", "mediatek,mt6765-spi": for mt8192 platforms
- - "mediatek,mt8195-spi", "mediatek,mt6765-spi": for mt8195 platforms
- - "mediatek,mt8516-spi", "mediatek,mt2712-spi": for mt8516 platforms
- - "mediatek,mt6779-spi", "mediatek,mt6765-spi": for mt6779 platforms
-
-- #address-cells: should be 1.
-
-- #size-cells: should be 0.
-
-- reg: Address and length of the register set for the device
-
-- interrupts: Should contain spi interrupt
-
-- clocks: phandles to input clocks.
- The first should be one of the following. It's PLL.
- - <&clk26m>: specify parent clock 26MHZ.
- - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
- It's the default one.
- - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
- - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
- - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
- The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux.
- The third is <&pericfg CLK_PERI_SPI0>. It's clock gate.
-
-- clock-names: shall be "parent-clk" for the parent clock, "sel-clk" for the
- muxes clock, and "spi-clk" for the clock gate.
-
-Optional properties:
--cs-gpios: see spi-bus.txt.
-
-- mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi
- controller used. This is an array, the element value should be 0~3,
- only required for MT8173.
- 0: specify GPIO69,70,71,72 for spi pins.
- 1: specify GPIO102,103,104,105 for spi pins.
- 2: specify GPIO128,129,130,131 for spi pins.
- 3: specify GPIO5,6,7,8 for spi pins.
-
-Example:
-
-- SoC Specific Portion:
-spi: spi@1100a000 {
- compatible = "mediatek,mt8173-spi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0 0x1100a000 0 0x1000>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
- <&topckgen CLK_TOP_SPI_SEL>,
- <&pericfg CLK_PERI_SPI0>;
- clock-names = "parent-clk", "sel-clk", "spi-clk";
- cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
- mediatek,pad-select = <1>, <0>;
-};
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v21 3/8] soc: mediatek: SVS: introduce MTK SVS engine
From: Roger Lu @ 2022-01-24 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger,
Enric Balletbo Serra, Kevin Hilman, Rob Herring, Nicolas Boichat,
Stephen Boyd, Philipp Zabel
Cc: Fan Chen, HenryC Chen, YT Lee, Xiaoqing Liu, Charles Yang,
Angus Lin, Mark Rutland, Nishanth Menon, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, linux-pm,
Project_Global_Chrome_Upstream_Group, Guenter Roeck
In-Reply-To: <63d8884d-d02d-53f9-8524-4a074ca5bfea@collabora.com>
Hi AngeloGioacchino,
Sorry for the late reply and thanks for the advice.
On Fri, 2022-01-07 at 15:33 +0100, AngeloGioacchino Del Regno wrote:
> Il 07/01/22 10:51, Roger Lu ha scritto:
> > The Smart Voltage Scaling(SVS) engine is a piece of hardware
> > which calculates suitable SVS bank voltages to OPP voltage table.
> > Then, DVFS driver could apply those SVS bank voltages to PMIC/Buck
> > when receiving OPP_EVENT_ADJUST_VOLTAGE.
> >
> > Signed-off-by: Roger Lu <roger.lu@mediatek.com>
> > ---
> > drivers/soc/mediatek/Kconfig | 10 +
> > drivers/soc/mediatek/Makefile | 1 +
> > drivers/soc/mediatek/mtk-svs.c | 1446 ++++++++++++++++++++++++++++++++
> > 3 files changed, 1457 insertions(+)
> > create mode 100644 drivers/soc/mediatek/mtk-svs.c
[snip]
> > +
> > +struct svs_platform_data {
> > + char *name;
> > + struct svs_bank *banks;
> > + bool (*efuse_parsing)(struct svs_platform *svsp);
> > + unsigned long irqflags;
> > + const u32 *regs;
> > + u32 bank_max;
> > + int (*probe)(struct svs_platform *svsp);
> > +};
> > +
>
> Please move the definition of struct svs_platform_data at the beginning of
> the file for increased readability.
Okay. I'll move them at the beginning of the file in the next patch.
>
> With that done,
>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
^ permalink raw reply
* Re: [PATCH v3 1/2] iio: adc: tsc2046: add .read_raw support
From: Oleksij Rempel @ 2022-01-24 7:08 UTC (permalink / raw)
To: Jonathan Cameron
Cc: devicetree, Lars-Peter Clausen, linux-iio, Robin van der Gracht,
linux-kernel, Pengutronix Kernel Team, David Jander
In-Reply-To: <20220122171420.7036e031@jic23-huawei>
Hi Jonathan,
On Sat, Jan 22, 2022 at 05:14:20PM +0000, Jonathan Cameron wrote:
> On Mon, 17 Jan 2022 09:28:51 +0100
> Oleksij Rempel <o.rempel@pengutronix.de> wrote:
>
> > Add read_raw() support to make use of iio_hwmon and other iio clients.
> >
> > Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
>
> > ---
>
> Change log? If it's just the check against PAGE_SIZE then I'm fine with it, but
> maybe I missed something.
yes, only PAGE_SIZE.
> Much better to have a short description of what
> changed here.
OK
> Anyhow, I'll assume that's it. Applied to the togreg branch of iio.git and
> pushed out as testing to let 0-day poke at it and see if it can find any
> problems.
>
> There was a little fuzz here for patch 2, presumably because the fix that is
> in flight. Hopefully that won't cause us too many problems in linux-next or
> at merge time.
Thank you!
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* Re: [PATCH v5 00/14] riscv: support for svpbmt and D1 memory types
From: Christoph Hellwig @ 2022-01-24 7:22 UTC (permalink / raw)
To: Heiko Stuebner
Cc: palmer, paul.walmsley, aou, linux-riscv, devicetree, linux-kernel,
robh+dt, wefu, liush, guoren, atishp, anup, drew, hch, arnd, wens,
maxime, dlustig, gfavor, andrea.mondelli, behrensj, xinhaoqu,
huffman, mick, allen.baum, jscheid, rtrauben, samuel, cmuellner,
philipp.tomsich
In-Reply-To: <20220121163618.351934-1-heiko@sntech.de>
On Fri, Jan 21, 2022 at 05:36:04PM +0100, Heiko Stuebner wrote:
> So this is my try at implementing svpbmt (and the diverging D1 memory
> types using the alternatives framework).
Please spell out what it does. While I can remember the original single
letter extensions very well, the new priviliged extension naming is
just letter salad.
You might also want to explain in more detail what it does and why you
want to support it.
^ permalink raw reply
* Re: [PATCH v21 4/8] soc: mediatek: SVS: add monitor mode
From: Roger Lu @ 2022-01-24 7:28 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger,
Enric Balletbo Serra, Kevin Hilman, Rob Herring, Nicolas Boichat,
Stephen Boyd, Philipp Zabel
Cc: Fan Chen, HenryC Chen, YT Lee, Xiaoqing Liu, Charles Yang,
Angus Lin, Mark Rutland, Nishanth Menon, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, linux-pm,
Project_Global_Chrome_Upstream_Group, Guenter Roeck
In-Reply-To: <e118df40-da6b-88f6-fbff-15befb3405d5@collabora.com>
Hi AngeloGioacchino,
Sorry for the late reply and thanks for the advice.
On Fri, 2022-01-07 at 15:34 +0100, AngeloGioacchino Del Regno wrote:
> Il 07/01/22 10:51, Roger Lu ha scritto:
> > SVS monitor mode is based on different thermal temperature
> > to provide suitable SVS bank voltages.
> >
> > Signed-off-by: Roger Lu <roger.lu@mediatek.com>
> > ---
> > drivers/soc/mediatek/mtk-svs.c | 253 ++++++++++++++++++++++++++++++++-
> > 1 file changed, 247 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c
> > index fc7e2ee44a92..042c6e8e9069 100644
> > --- a/drivers/soc/mediatek/mtk-svs.c
> > +++ b/drivers/soc/mediatek/mtk-svs.c
> > @@ -25,6 +25,7 @@
> > #include <linux/regulator/consumer.h>
> > #include <linux/slab.h>
> > #include <linux/spinlock.h>
> > +#include <linux/thermal.h>
> >
> > /* svs bank 1-line sw id */
> > #define SVSB_CPU_LITTLE BIT(0)
> > @@ -36,6 +37,7 @@
> > #define SVSB_MODE_ALL_DISABLE 0
> > #define SVSB_MODE_INIT01 BIT(1)
> > #define SVSB_MODE_INIT02 BIT(2)
> > +#define SVSB_MODE_MON BIT(3)
[snip]
> > /**
> > @@ -241,6 +254,7 @@ struct svs_platform {
> > * @get_volts: function pointer to get bank voltages
> > * @name: bank name
> > * @buck_name: regulator name
> > + * @tzone_name: thermal zone name
> > * @suspended: suspend flag of this bank
> > * @phase: bank current phase
> > * @volt_od: bank voltage overdrive
> > @@ -270,6 +284,13 @@ struct svs_platform {
> > * @sw_id: bank software identification
> > * @cpu_id: cpu core id for SVS CPU bank use only
> > * @ctl0: TS-x selection
> > + * @temp: bank temperature
> > + * @tzone_htemp: thermal zone high temperature threshold
> > + * @tzone_htemp_voffset: thermal zone high temperature voltage offset
> > + * @tzone_ltemp: thermal zone low temperature threshold
> > + * @tzone_ltemp_voffset: thermal zone low temperature voltage offset
> > + * @bts: svs efuse data
> > + * @mts: svs efuse data
> > * @bdes: svs efuse data
> > * @mdes: svs efuse data
> > * @mtdes: svs efuse data
> > @@ -292,6 +313,7 @@ struct svs_bank {
> > void (*get_volts)(struct svs_platform *svsp);
> > char *name;
> > char *buck_name;
> > + char *tzone_name;
> > bool suspended;
> > enum svsb_phase phase;
> > s32 volt_od;
> > @@ -321,6 +343,13 @@ struct svs_bank {
> > u32 sw_id;
> > u32 cpu_id;
> > u32 ctl0;
> > + u32 temp;
> > + u32 tzone_htemp;
> > + u32 tzone_htemp_voffset;
> > + u32 tzone_ltemp;
> > + u32 tzone_ltemp_voffset;
> > + u32 bts;
> > + u32 mts;
> > u32 bdes;
> > u32 mdes;
> > u32 mtdes;
> > @@ -361,10 +390,21 @@ static u32 svs_bank_volt_to_opp_volt(u32 svsb_volt,
> > u32 svsb_volt_step,
> > return (svsb_volt * svsb_volt_step) + svsb_volt_base;
> > }
> >
>
> I'm sorry for the double review, but this went unnoticed in the previous one.
>
> > +static int svs_get_zone_temperature(const char *tzone_name, int
> > *tzone_temp)
> > +{
> > + struct thermal_zone_device *tzd;
> > +
> > + tzd = thermal_zone_get_zone_by_name(tzone_name);
>
> This call is expensive, as it's iterating through the (possibly) entire
> thermal_tz_list (drivers/thermal/thermal_core.c) so, for performance purposes,
> noting that you're using this in svs_adjust_pm_opp_volts(), it's not a good
> idea
> to call it at every ISR.
>
> I would instead propose to get a pointer to the thermal_zone at driver probe
> time and cache that in struct svs_bank: this function would also be removed
> as the only thing that you'd need to do then would be just one call...
>
> [read forward...]
No problem. I'll cache thermal_zone at driver probe time and remove this API in
the next patch. Thanks.
>
> > + if (IS_ERR(tzd))
> > + return PTR_ERR(tzd);
> > +
> > + return thermal_zone_get_temp(tzd, tzone_temp);
> > +}
> > +
> > static int svs_adjust_pm_opp_volts(struct svs_bank *svsb, bool
> > force_update)
> > {
> > - int ret = -EPERM;
> > - u32 i, svsb_volt, opp_volt;
> > + int ret = -EPERM, tzone_temp = 0;
> > + u32 i, svsb_volt, opp_volt, temp_voffset = 0;
> >
> > mutex_lock(&svsb->lock);
> >
> > @@ -378,6 +418,22 @@ static int svs_adjust_pm_opp_volts(struct svs_bank
> > *svsb, bool force_update)
> > goto unlock_mutex;
> > }
> >
> > + /* Get thermal effect */
> > + if (svsb->phase == SVSB_PHASE_MON) {
> > + ret = svs_get_zone_temperature(svsb->tzone_name, &tzone_temp);
>
> ... so you can simply call ...
>
>
> ret = thermal_zone_get_temp(svsb->tzd, tzone_temp);
>
>
> ...without any need for any helper.
Sure, I'll call thermal_zone_get_temp() directly after applying this recommended
change in the next patch. Thanks.
>
> > + if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND &&
> > + svsb->temp < SVSB_TEMP_LOWER_BOUND)) {
> > + dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n",
> > + svsb->tzone_name, ret, svsb->temp);
> > + svsb->phase = SVSB_PHASE_ERROR;
> > + }
> > +
> > + if (tzone_temp >= svsb->tzone_htemp)
> > + temp_voffset += svsb->tzone_htemp_voffset;
> > + else if (tzone_temp <= svsb->tzone_ltemp)
> > + temp_voffset += svsb->tzone_ltemp_voffset;
> > + }
> > +
> > /* vmin <= svsb_volt (opp_volt) <= default opp voltage */
> > for (i = 0; i < svsb->opp_count; i++) {
> > switch (svsb->phase) {
>
> Apart from that, the commit looks good. Looking forward to review the new
> version!
>
> Regards,
> - Angelo
^ permalink raw reply
* Re: [PATCH v5 3/4] mfd: dt-bindings: google,cros-ec: reference Samsung SPI bindings
From: Krzysztof Kozlowski @ 2022-01-24 7:49 UTC (permalink / raw)
To: Rob Herring
Cc: Lee Jones, Benson Leung, Guenter Roeck, Andi Shyti, Mark Brown,
Sam Protsenko, Pratyush Yadav, devicetree, linux-kernel,
linux-arm-kernel, linux-samsung-soc, linux-spi, Alim Akhtar
In-Reply-To: <YenkV2rgEXQJ6Bc5@robh.at.kernel.org>
On 20/01/2022 23:38, Rob Herring wrote:
> On Thu, Jan 20, 2022 at 06:57:46PM +0100, Krzysztof Kozlowski wrote:
>> The ChromeOS Embedded Controller appears on boards with Samsung Exynos
>> SoC, where Exynos SPI bindings expect controller-data node. Reference
>> newly added dtschema for this property.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>> ---
>> .../bindings/mfd/google,cros-ec.yaml | 29 ++++++++++---------
>> 1 file changed, 16 insertions(+), 13 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
>> index 58a1a9405228..66a995bbbbe9 100644
>> --- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
>> +++ b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
>> @@ -31,7 +31,7 @@ properties:
>>
>> controller-data:
>> description:
>> - SPI controller data, see bindings/spi/spi-samsung.txt
>> + SPI controller data, see bindings/spi/samsung,spi-peripheral-props.yaml
>> type: object
>
> We should be able to drop all of this if unevaluatedProperties is used.
>
>>
>> google,cros-ec-spi-pre-delay:
>> @@ -148,18 +148,21 @@ patternProperties:
>> required:
>> - compatible
>>
>> -if:
>> - properties:
>> - compatible:
>> - contains:
>> - enum:
>> - - google,cros-ec-i2c
>> - - google,cros-ec-rpmsg
>> -then:
>> - properties:
>> - google,cros-ec-spi-pre-delay: false
>> - google,cros-ec-spi-msg-delay: false
>> - spi-max-frequency: false
>> +allOf:
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - google,cros-ec-i2c
>> + - google,cros-ec-rpmsg
>> + then:
>> + properties:
>> + google,cros-ec-spi-pre-delay: false
>> + google,cros-ec-spi-msg-delay: false
>> + spi-max-frequency: false
>> +
>> + - $ref: /schemas/spi/samsung,spi-peripheral-props.yaml
>
> SPI device schemas should reference spi-peripheral-props.yaml only.
> spi-peripheral-props.yaml in turn should reference all the vendor
> specific peripheral property schemas.
>
> You should be able to do just:
>
> else:
> $ref: /schemas/spi/spi-peripheral-props.yaml
I tried now with your changes (no controller-data and else-ref), but
dt_binding_check complains:
linux/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml:
'additionalProperties' is a required property
hint: A schema without a "$ref" to another schema must define all
properties and use "additionalProperties"
from schema $id: http://devicetree.org/meta-schemas/base.yaml#
Which makes sense because only one part - SPI devices - get the ref to
spi-perpheral-props.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 3/7] iio: adc: sc27xx: structure adjuststment and optimization
From: Cixi Geng @ 2022-01-24 8:06 UTC (permalink / raw)
To: Baolin Wang
Cc: Orson Zhai, Chunyan Zhang, jic23, Lars-Peter Clausen, Rob Herring,
lgirdwood, Mark Brown,
朱玉明 (Yuming Zhu/11457), linux-iio,
Devicetree List, LKML
In-Reply-To: <CADBw62rSdWN-L8HbnyMrUNp=x0pDdKR6MyKO4yfu00MnrN4L-g@mail.gmail.com>
Baolin Wang <baolin.wang7@gmail.com> 于2022年1月17日周一 14:15写道：
>
> On Thu, Jan 13, 2022 at 9:54 AM Cixi Geng <gengcixi@gmail.com> wrote:
> >
> > Baolin Wang <baolin.wang7@gmail.com> 于2022年1月7日周五 15:03写道：
> > >
> > > On Thu, Jan 6, 2022 at 9:00 PM Cixi Geng <gengcixi@gmail.com> wrote:
> > > >
> > > > From: Cixi Geng <cixi.geng1@unisoc.com>
> > > >
> > > > Introduce one variant device data structure to be compatible
> > > > with SC2731 PMIC since it has different scale and ratio calculation
> > > > and so on.
> > > >
> > > > Signed-off-by: Yuming Zhu <yuming.zhu1@unisoc.com>
> > > > Signed-off-by: Cixi Geng <cixi.geng1@unisoc.com>
> > > > ---
> > > > drivers/iio/adc/sc27xx_adc.c | 94 ++++++++++++++++++++++++++++++------
> > > > 1 file changed, 79 insertions(+), 15 deletions(-)
> > > >
> > > > diff --git a/drivers/iio/adc/sc27xx_adc.c b/drivers/iio/adc/sc27xx_adc.c
> > > > index aee076c8e2b1..d2712e54ee79 100644
> > > > --- a/drivers/iio/adc/sc27xx_adc.c
> > > > +++ b/drivers/iio/adc/sc27xx_adc.c
> > > > @@ -12,9 +12,9 @@
> > > > #include <linux/slab.h>
> > > >
> > > > /* PMIC global registers definition */
> > > > -#define SC27XX_MODULE_EN 0xc08
> > > > +#define SC2731_MODULE_EN 0xc08
> > > > #define SC27XX_MODULE_ADC_EN BIT(5)
> > > > -#define SC27XX_ARM_CLK_EN 0xc10
> > > > +#define SC2731_ARM_CLK_EN 0xc10
> > > > #define SC27XX_CLK_ADC_EN BIT(5)
> > > > #define SC27XX_CLK_ADC_CLK_EN BIT(6)
> > > >
> > > > @@ -78,6 +78,23 @@ struct sc27xx_adc_data {
> > > > int channel_scale[SC27XX_ADC_CHANNEL_MAX];
> > > > u32 base;
> > > > int irq;
> > > > + const struct sc27xx_adc_variant_data *var_data;
> > > > +};
> > > > +
> > > > +/*
> > > > + * Since different PMICs of SC27xx series can have different
> > > > + * address and ratio, we should save ratio config and base
> > > > + * in the device data structure.
> > > > + */
> > > > +struct sc27xx_adc_variant_data {
> > > > + u32 module_en;
> > > > + u32 clk_en;
> > > > + u32 scale_shift;
> > > > + u32 scale_mask;
> > > > + const struct sc27xx_adc_linear_graph *bscale_cal;
> > > > + const struct sc27xx_adc_linear_graph *sscale_cal;
> > > > + void (*init_scale)(struct sc27xx_adc_data *data);
> > > > + int (*get_ratio)(int channel, int scale);
> > > > };
> > > >
> > > > struct sc27xx_adc_linear_graph {
> > > > @@ -103,6 +120,16 @@ static struct sc27xx_adc_linear_graph small_scale_graph = {
> > > > 100, 341,
> > > > };
> > > >
> > > > +static const struct sc27xx_adc_linear_graph sc2731_big_scale_graph_calib = {
> > > > + 4200, 850,
> > > > + 3600, 728,
> > > > +};
> > > > +
> > > > +static const struct sc27xx_adc_linear_graph sc2731_small_scale_graph_calib = {
> > > > + 1000, 838,
> > > > + 100, 84,
> > > > +};
> > >
> > > The original big_scale_graph_calib and small_scale_graph_calib are for
> > > SC2731 PMIC, why add new structure definition for SC2731?
> > >
> > > > +
> > > > static const struct sc27xx_adc_linear_graph big_scale_graph_calib = {
> > > > 4200, 856,
> > > > 3600, 733,
> > > > @@ -130,11 +157,11 @@ static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data,
> > > > size_t len;
> > > >
> > > > if (big_scale) {
> > > > - calib_graph = &big_scale_graph_calib;
> > > > + calib_graph = data->var_data->bscale_cal;
> > > > graph = &big_scale_graph;
> > > > cell_name = "big_scale_calib";
> > > > } else {
> > > > - calib_graph = &small_scale_graph_calib;
> > > > + calib_graph = data->var_data->sscale_cal;
> > > > graph = &small_scale_graph;
> > > > cell_name = "small_scale_calib";
> > > > }
> > > > @@ -160,7 +187,7 @@ static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data,
> > > > return 0;
> > > > }
> > > >
> > > > -static int sc27xx_adc_get_ratio(int channel, int scale)
> > > > +static int sc2731_adc_get_ratio(int channel, int scale)
> > > > {
> > > > switch (channel) {
> > > > case 1:
> > > > @@ -185,6 +212,21 @@ static int sc27xx_adc_get_ratio(int channel, int scale)
> > > > return SC27XX_VOLT_RATIO(1, 1);
> > > > }
> > > >
> > > > +/*
> > > > + * According to the datasheet set specific value on some channel.
> > > > + */
> > > > +static void sc2731_adc_scale_init(struct sc27xx_adc_data *data)
> > > > +{
> > > > + int i;
> > > > +
> > > > + for (i = 0; i < SC27XX_ADC_CHANNEL_MAX; i++) {
> > > > + if (i == 5)
> > > > + data->channel_scale[i] = 1;
> > > > + else
> > > > + data->channel_scale[i] = 0;
> > > > + }
> > > > +}
> > >
> > > This is unnecessary I think, please see sc27xx_adc_write_raw() that
> > > can set the channel scale.
> > Did you mean that all the PMIC's scale_init function should put into
> > the sc27xx_adc_write_raw?
>
> No.
>
> > but the scale_init is all different by each PMIC, if implemented in
> > the write_raw, will add a lot of
> > if or switch_case branch
>
> What I mean is we should follow the original method to set the channel
> scale by iio_info. Please also refer to other drivers how ot handle
> the channel scale.
Hi Baolin, I understand the adc_write_raw() function is the method to set
channal scale for the userspace, we can change the channel scale by write
a value on a user code. did i understand right?
out scale_init is to set scale value when the driver probe stage, and I also
did not found other adc driver use the adc_write_raw() during the driver
initialization phase.
>
> --
> Baolin Wang
^ permalink raw reply
* [PATCH] ARM: dts: aspeed: Adding Wistron Lannister BMC
From: Bob King @ 2022-01-24 8:07 UTC (permalink / raw)
To: robh+dt, joel, andrew, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Cc: Bob King
Initial introduction of Wistron Lannister equipped with
Aspeed 2600 BMC SoC.
Signed-off-by: Bob King <Bob_King@wistron.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/aspeed-bmc-wistron-lannister.dts | 1007 ++++++++++++++++++++
2 files changed, 1009 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-wistron-lannister.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 235ad55..7d37aab 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1548,4 +1548,5 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-tyan-s8036.dtb \
aspeed-bmc-vegman-n110.dtb \
aspeed-bmc-vegman-rx20.dtb \
- aspeed-bmc-vegman-sx20.dtb
+ aspeed-bmc-vegman-sx20.dtb \
+ aspeed-bmc-wistron-lannister.dtb
diff --git a/arch/arm/boot/dts/aspeed-bmc-wistron-lannister.dts b/arch/arm/boot/dts/aspeed-bmc-wistron-lannister.dts
new file mode 100644
index 0000000..e8e4f9d
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-wistron-lannister.dts
@@ -0,0 +1,1007 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+
+/ {
+ model = "Lannister BMC";
+ compatible = "aspeed,ast2600";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200n8 root=/dev/ram rw init=/linuxrc";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+
+ video_engine_memory: jpegbuffer {
+ size = <0x02000000>; /* 32M */
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ video_memory: video {
+ size = <0x04000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ no-map;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ identify {
+ default-state = "off";
+ gpios = <&gpio0 ASPEED_GPIO(B, 7) GPIO_ACTIVE_LOW>;
+ };
+
+ status_amber {
+ default-state = "off";
+ gpios = <&gpio0 ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>;
+ };
+
+ status_green {
+ default-state = "keep";
+ gpios = <&gpio0 ASPEED_GPIO(G, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ bmc-heart-beat {
+ default-state = "off";
+ gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
+ };
+
+ power-ok {
+ default-state = "keep";
+ gpios = <&gpio0 ASPEED_GPIO(R, 6) GPIO_ACTIVE_LOW>;
+ };
+
+ global-error {
+ default-state = "off";
+ gpios = <&gpio0 ASPEED_GPIO(R, 7) GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err1 {
+ default-state = "off";
+ gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err2 {
+ default-state = "off";
+ gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err3 {
+ default-state = "off";
+ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err4 {
+ default-state = "off";
+ gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err5 {
+ default-state = "off";
+ gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err6 {
+ default-state = "off";
+ gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err7 {
+ default-state = "off";
+ gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err8 {
+ default-state = "off";
+ gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err9 {
+ default-state = "off";
+ gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err10 {
+ default-state = "off";
+ gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err11 {
+ default-state = "off";
+ gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err12 {
+ default-state = "off";
+ gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err13 {
+ default-state = "off";
+ gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err14 {
+ default-state = "off";
+ gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err15 {
+ default-state = "off";
+ gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err16 {
+ default-state = "off";
+ gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err17 {
+ default-state = "off";
+ gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err18 {
+ default-state = "off";
+ gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err19 {
+ default-state = "off";
+ gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err20 {
+ default-state = "off";
+ gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err21 {
+ default-state = "off";
+ gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err22 {
+ default-state = "off";
+ gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err23 {
+ default-state = "off";
+ gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err24 {
+ default-state = "off";
+ gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err25 {
+ default-state = "off";
+ gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err26 {
+ default-state = "off";
+ gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err27 {
+ default-state = "off";
+ gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err28 {
+ default-state = "off";
+ gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err29 {
+ default-state = "off";
+ gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err30 {
+ default-state = "off";
+ gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err31 {
+ default-state = "off";
+ gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
+ };
+
+ dimm-err32 {
+ default-state = "off";
+ gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
+ };
+
+ fan1-fault {
+ default-state = "off";
+ gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
+ };
+
+ fan2-fault {
+ default-state = "off";
+ gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ };
+
+ fan3-fault {
+ default-state = "off";
+ gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
+ };
+
+ fan4-fault {
+ default-state = "off";
+ gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
+ };
+
+ fan5-fault {
+ default-state = "off";
+ gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
+ };
+
+ fan6-fault {
+ default-state = "off";
+ gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
+ };
+
+ cpu1 {
+ default-state = "off";
+ gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ };
+
+ cpu2 {
+ default-state = "off";
+ gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ };
+
+ riser1-s1 {
+ default-state = "off";
+ gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ };
+
+ riser1-s2 {
+ default-state = "off";
+ gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+ };
+
+ riser1-s3 {
+ default-state = "off";
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ };
+
+ riser2-s1 {
+ default-state = "off";
+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+ };
+
+ riser2-s2 {
+ default-state = "off";
+ gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
+ };
+
+ riser2-s3 {
+ default-state = "off";
+ gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
+ };
+
+ riser3-s1 {
+ default-state = "off";
+ gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
+ };
+
+ riser3-s2 {
+ default-state = "off";
+ gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
+ };
+
+ m2-1 {
+ default-state = "off";
+ gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
+ };
+
+ m2-2 {
+ default-state = "off";
+ gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ };
+
+ bat {
+ default-state = "off";
+ gpios = <&gpio5 15 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ poll-interval = <1000>;
+
+ fan0-presence {
+ /* GPIO18C2 */
+ label = "fan0-presence";
+ gpios = <&gpio1 ASPEED_GPIO(C, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(C, 2)>;
+ };
+
+ fan1-presence {
+ /* GPIO18C3 */
+ label = "fan1-presence";
+ gpios = <&gpio1 ASPEED_GPIO(C, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(C, 3)>;
+ };
+
+ fan2-presence {
+ /* GPIO18C7 */
+ label = "fan2-presence";
+ gpios = <&gpio1 ASPEED_GPIO(C, 7) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(C, 7)>;
+ };
+
+ fan3-presence {
+ /* GPIO18C6 */
+ label = "fan3-presence";
+ gpios = <&gpio1 ASPEED_GPIO(C, 6) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(C, 6)>;
+ };
+
+ fan4-presence {
+ /* GPIO18C5 */
+ label = "fan4-presence";
+ gpios = <&gpio1 ASPEED_GPIO(C, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(C, 5)>;
+ };
+
+ fan5-presence {
+ /* GPIO18C4 */
+ label = "fan5-presence";
+ gpios = <&gpio1 ASPEED_GPIO(C, 4) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(C, 4)>;
+ };
+ };
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <4>;
+ m25p,fast-read;
+#include "openbmc-flash-layout-64.dtsi"
+ };
+};
+&syscon {
+ uart-clock-high-speed;
+ status = "okay";
+
+ misc_control {
+ compatible = "aspeed,bmc-misc";
+ chip_id {
+ offset = <0x5b0>;
+ bit-mask = <0xffffffff 0xffffffff>;
+ bit-shift = <0>;
+ read-only;
+ reg-width = <64>;
+ hash-data = "d44f9b804976fa23c2e25d62f16154d26520a7e24c5555095fd1b55c027804f1570dcd16189739c640cd7d9a6ce14944a2c4eaf1dc429eed6940e8a83498a474";
+ };
+ };
+};
+
+#if 0
+ GPIO Alias: (runtime alias -> schematic name)
+ ID_BUTTON -> FP_ID_BTN_N
+ CPU_CATERR -> FM_PLT_BMC_THERMTRIP_N
+ PCH_BMC_THERMTRIP -> FM_PLT_BMC_THERMTRIP_N
+ RESET_BUTTON -> FP_BMC_RST_BTN_N
+ RESET_OUT -> RST_BMC_RSTBTN_OUT_R_N
+ POWER_BUTTON -> FP_BMC_PWR_BTN_R_N
+ POWER_OUT -> FM_BMC_PWR_BTN_N
+ PREQ_N -> DBP_ASD_BMC_PREQ_R_N
+ POST_COMPLETE -> FM_BIOS_POST_CMPLT_BMC_N
+ CPU_ERR0 -> FM_CPU_ERR0_LVT3_N
+ CPU_ERR1 -> FM_CPU_ERR1_LVT3_N
+ CPU_ERR2 -> FM_CPU_ERR2_LVT3_N
+ DEBUG_EN_N -> FM_JTAG_TCK_MUX_SEL_R
+ NMI_OUT -> IRQ_BMC_CPU_NMI_R
+ PLTRST_N -> RST_PLTRST_BMC_N
+ PRDY_N -> DBP_ASD_BMC_PRDY_R_N
+ PWR_DEBUG_N ->
+ XDP_PRST_N ->
+ SYSPWROK ->
+ RSMRST_N ->
+ SIO_S3 -> FM_SLPS3_R_N
+ SIO_S5 -> FM_SLPS4_R_N
+ SIO_ONCONTROL -> FM_BMC_ONCTL_R_N
+ SIO_POWER_GOOD -> PWRGD_CPU0_LVC3_R
+ PS_PWROK -> PWRGD_BMC_PS_PWROK_R
+ P3VBAT_BRIDGE_EN ->
+ TCK_MUX_SEL ->
+ SMI -> IRQ_SMI_ACTIVE_BMC_N
+ NMI_BUTTON -> FP_NMI_BTN_N
+#endif
+
+&gpio0 {
+ status = "okay";
+ /* pinctrl-names = "pass-through";
+ pinctrl-0 = <&pinctrl_thru0_default
+ &pinctrl_thru1_default>; */
+ gpio-line-names =
+ /*A0-A7*/ "SMB_BMC0_MUX01_CLK_H","SMB_BMC0_MUX01_DAT_H","RST_BTN_IRMC_N","BTN_PWR_BMC_N","SMB_CPU_PIROM_SCL","SMB_CPU_PIROM_SDA","I2C_BMC_SCL14","I2C_BMC_SDA14",
+ /*B0-B7*/ "FM_SEL_BMC_USB_HOST_N","NMI_OUT","IRQ_SMB3_M2_ALERT_N","SMB_BMC_2_PMBUS_ALERT_N","RST_BMC_PCIE_MUX_N","FM_BMC_EUP_LOT6_N","FM_BMC_BMCINIT_R","FP_ID_LED_N",
+ /*C0-C7*/ "FM_FORCE_BMC_UPDATE_N","RST_RGMII_PHYRST_N","FM_TPM_EN_PULSE","FM_BMC_CRASHLOG_TRIG_N","IRQ_BMC_PCH_NMI_R","FM_CPU1_DISABLE_COD_N","SMB_BMCLC1_CLK_R_H","SMB_BMCLC1_DAT_R_H",
+ /*D0-D7*/ "CPU_ERR0","CPU_ERR1","CPU_ERR2","PRDY_N","FM_SPD_SWITCH_CTRL_N","FM_RISER3_BMC_ID_0","FAN_PRSNT_LC2","FAN_PRSNT_LC1",
+ /*E0-E7*/ "FM_RISER2_RBP_ID_R_0","LED_CSS_R_N","CLK_50M_CKMNG_BMCB","FM_BMC_BOARD_REV_ID2_N","FM_RISER2_ID_0","FM_RISER2_ID_1","SMB_BMCLC2_DAT_R_H","SMB_BMCLC2_CLK_R_H",
+ /*F0-F7*/ "FM_BMC_BOARD_SKU_ID0_N","FM_BMC_BOARD_SKU_ID1_N","FM_BMC_BOARD_SKU_ID2_N","FM_BMC_BOARD_SKU_ID3_N","FM_BMC_BOARD_SKU_ID4_N ","FM_BMC_BOARD_SKU_ID5_N","PRSNT_MONITOR_FP_L","PS_PWROK",
+ /*G0-G7*/ "FM_SMB_BMC_NVME_LVC3_ALERT_N","RST_BMC_I2C_M2_R_N","FP_LED_STATUS_GREEN_N","FP_LED_STATUS_AMBER_N","FM_BMC_BOARD_REV_ID0_N","FM_BMC_BOARD_REV_ID1_N","FM_BMC_CPU_FBRK_OUT_R_N","DBP_PRESENT_IN_R2_N",
+ /*H0-H7*/ "SGPIO_BMC_CLK_R","SGPIO_BMC_LD_R_N","SGPIO_BMC_DOUT_R","SGPIO_BMC_DIN","PLTRST_N","CPU_CATERR","SMB_TEMPSENSOR_STBY_LVC3_R_SCL","SMB_TEMPSENSOR_STBY_LVC3_R_SDA",
+ /*I0-I7*/ "JTAG_ASD_NTRST_R_N","JTAG_ASD_TDI_R","JTAG_ASD_TCK_R","JTAG_ASD_TMS_R","JTAG_ASD_TDO","FM_BMC_PWRBTN_OUT_R_N","","TP_FM_BMC_PCH_SCI_LPC_R_N",
+ /*J0-J7*/ "I2C_BMC_RISER1_SCL1","I2C_BMC_RISER1_SDA1","I2C_BMC_PSU_SCL2","I2C_BMC_PSU_SDA2","I2C_BMC_PWR_SCL3","I2C_BMC_PWR_SDA3","I2C_BMC_SCL4","I2C_BMC_SDA4",
+ /*K0-K7*/ "SMB_HSBP_STBY_LVC3_R_SCL","SMB_HSBP_STBY_LVC3_R_SDA","SMB_SMLINK0_STBY_LVC3_R2_SCL","SMB_SMLINK0_STBY_LVC3_R2_SDA","I2C_BMC_RISER2_SCL7","I2C_BMC_RISER2_SDA7","SMB_PMBUS_SML1_STBY_LVC3_R_SCL","SMB_PMBUS_SML1_STBY_LVC3_R_SDA",
+ /*L0-L7*/ "SMB_PCIE_STBY_LVC3_R_SCL","SMB_PCIE_STBY_LVC3_R_SDA","SMB_HOST_STBY_BMC_LVC3_R_SCL","SMB_HOST_STBY_BMC_LVC3_R_SDA","PREQ_N","TCK_MUX_SEL","V_BMC_GFX_HSYNC_R","V_BMC_GFX_VSYNC_R",
+ /*M0-M7*/ "SPA_CTS_N ","SPA_DCD_N","SPA_DSR_N","PU_SPA_RI_N","SPA_DTR_N","SPA_RTS_N","SPA_SOUT","SPA_SIN",
+ /*N0-N7*/ "SPB_CTS_N","SPB_DCD_N","SPB_DSR_N","PU_SPB_RI_N","SPB_DTR_N","SPB_RTS_N","SPB_SOUT","SPB_SIN",
+ /*O0-O7*/ "FAN_PWM_BMC_1_H","FAN_PWM_BMC_2_H","FAN_PWM_BMC_3_H","FAN_PWM_BMC_4_H","FAN_PWM_BMC_5_H","FAN_PWM_BMC_6_H","NMI_BUTTON","FM_RECOVER_BIOS_R_N",
+ /*P0-P7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","FM_RISER3_BMC_ID_1","FM_RISER2_BMC_ID_2","RST_BMC_I2C_R_8","LED_BMC_HEARTBEAT_R_N",
+ /*Q0-Q7*/ "FAN_TACH_BMC_0_N_BUF","FAN_TACH_BMC_1_N_BUF","FAN_TACH_BMC_2_N_BUF","FAN_TACH_BMC_3_N_BUF","FAN_TACH_BMC_4_N_BUF","FAN_TACH_BMC_5_N_BUF","FAN_TACH_BMC_6_N_BUF","FAN_TACH_BMC_7_N_BUF",
+ /*R0-R7*/ "FAN_TACH_BMC_8_N_BUF","FAN_TACH_BMC_9_N_BUF","FAN_TACH_BMC_10_N_BUF","FAN_TACH_BMC_11_N_BUF","FAN_TACH_BMC_LC1_N_BUF","FAN_TACH_BMC_LC2_N_BUF","LED_PWROK_BMC_N","LED_GERR_IRMC_N",
+ /*S0-S7*/ "RGMII_BMC_RMM4_LVC3_R_MDC","RGMII_BMC_RMM4_LVC3_R_MDIO","ID_BUTTON","PCH_BMC_THERMTRIP","TP_LED_BMC_HEARTBEAT_N","A_P3V_BAT_SCALED_EN","FM_ASD_EN_DET_R","FM_PCHHOT_N",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","",
+ /*V0-V7*/ "SIO_S3","SIO_S5","TP_BMC_SIO_PWREQ_N","SIO_ONCONTROL","SIO_POWER_GOOD","LED_BMC_HB_LED_N","FM_BMC_SUSACK_N","TP_IRQ_BMC_PCH_SMI_LPC_N_R",
+ /*W0-W7*/ "LPC_LAD0_ESPI_R_IO0","LPC_LAD1_ESPI_R_IO1","LPC_LAD2_ESPI_R_IO2","LPC_LAD3_ESPI_R_IO3","CLK_24M_66M_LPC0_ESPI_BMC","LFRAME_N_ESPI_CS0_BMC_N","IRQ_LPC_SERIRQ_ESPI_ALERT_N","RST_LPC_LRST_ESPI_RST_BMC_R_N",
+ /*X0-X7*/ "ERR_FAT_VRM_N","SMI","POST_COMPLETE","FM_CLR_LDL_H","PU_SPB_FORCEOFF_N","PU_SPA_FORCEOFF_N","FM_RISER1_RBP_ID_0","FM_OCP1_PRSNTB3_N",
+ /*Y0-Y7*/ "FM_M2_PRSTN_BMC_N","IRQ_SML0_ALERT_BMC_R2_N","I2C_BUS8_INT_N","IRQ_SML1_PMBUS_BMC_ALERT_N","SPI_BMC_BOOT_R_IO2","SPI_BMC_BOOT_R_IO3","PU_SPI_BMC_BOOT_ABR","PU_SPI_BMC_BOOT_WP_N",
+ /*Z0-Z7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PRSNT_USB3_FP_X_L","PU_GPIOZ3","PU_GPIOZ4","PU_GPIOZ5","PU_GPIOZ6","PU_GPIOZ7";
+};
+
+&gpio1 {
+ status = "disabled";
+ gpio-line-names = /* GPIO18 A-E */
+ /*A0-A7*/ "RGMII_BMC_RMM4_TX_R_CLK","RGMII_BMC_RMM4_TX_R_CTRL","RGMII_BMC_RMM4_R_TXD0","RGMII_BMC_RMM4_R_TXD1","RGMII_BMC_RMM4_R_TXD2","RGMII_BMC_RMM4_R_TXD3","RGMII_BMC_RMM4_RX_CLK","RGMII_BMC_RMM4_RX_CTRL",
+ /*B0-B7*/ "RGMII_BMC_RMM4_RXD0","RGMII_BMC_RMM4_RXD1","RGMII_BMC_RMM4_RXD2","RGMII_BMC_RMM4_RXD3","FAN_PWM_BMC_LC2_H","FAN_PWM_BMC_LC1_H ","RST_EMMC_BMC_R_N","FM_RISER1_BMC_ID_2",
+ /*C0-C7*/ "FM_RISER1_BMC_ID_1","FM_RISER1_BMC_ID_0","FAN_PRSNT1_N","FAN_PRSNT2_N","FAN_PRSNT6_N","FAN_PRSNT5_N","FAN_PRSNT4_N","FAN_PRSNT3_N",
+ /*D0-D7*/ "EMMC_BMC_R_CLK","EMMC_BMC_R_CMD","EMMC_BMC_R_DATA0","EMMC_BMC_R_DATA1","EMMC_BMC_R_DATA2","EMMC_BMC_R_DATA3","EMMC_BMC_CD_N","EMMC_BMC_WP_N",
+ /*E0-E3*/ "EMMC_BMC_R_DATA4","EMMC_BMC_R_DATA5","EMMC_BMC_R_DATA6","EMMC_BMC_R_DATA7";
+};
+
+&sgpiom0 {
+ status = "okay";
+};
+
+&kcs3 {
+ kcs_addr = <0xCA2>;
+ status = "okay";
+};
+
+&kcs4 {
+ kcs_addr = <0xCA4>;
+ status = "okay";
+};
+
+&lpc_snoop {
+ snoop-ports = <0x80>;
+ status = "okay";
+};
+
+&mdio0 {
+ status = "okay";
+
+ ethphy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
+&mac0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
+ phy-mode = "rgmii";
+ phy-handle = <ðphy1>;
+};
+
+&adc0 {
+ status = "okay";
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default
+ &pinctrl_nrts1_default
+ &pinctrl_ndtr1_default
+ &pinctrl_ndsr1_default
+ &pinctrl_ncts1_default
+ &pinctrl_ndcd1_default
+ &pinctrl_nri1_default>;
+};
+
+&uart2 {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_txd2_default
+ &pinctrl_rxd2_default
+ &pinctrl_nrts2_default
+ &pinctrl_ndtr2_default
+ &pinctrl_ndsr2_default
+ &pinctrl_ncts2_default
+ &pinctrl_ndcd2_default
+ &pinctrl_nri2_default>;
+};
+
+&uart3 {
+ status = "okay";
+ pinctrl-0 = <>;
+};
+
+&uart4 {
+ status = "okay";
+ pinctrl-0 = <>;
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&uart_routing {
+ status = "okay";
+};
+
+&i2c0 {
+ /* I2C_BMC_RISER1 */
+ multi-master;
+ status = "okay";
+
+ pca9545@70 {
+ compatible = "nxp,pca9545";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ };
+};
+
+&i2c1 {
+ /* I2C_BMC_PSU */
+ multi-master;
+ status = "okay";
+
+ psu1-eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+
+ psu2-eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+
+ pmbus@58 {
+ compatible = "pmbus,sgd009";
+ reg = <0x58>;
+ };
+
+ pmbus@59 {
+ compatible = "pmbus,sgd009";
+ reg = <0x59>;
+ };
+};
+
+&i2c2 {
+ /* I2C_BMC_PWR */
+ multi-master;
+ status = "okay";
+};
+
+&i2c3 {
+ multi-master;
+ status = "okay";
+
+ gpio2: pca9539@74{
+ compatible = "nxp,pca9539";
+ reg = <0x74>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ };
+ };
+
+ gpio3: pca9539@75{
+ compatible = "nxp,pca9539";
+ reg = <0x75>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ };
+ };
+
+ gpio4: pca9539@76{
+ compatible = "nxp,pca9539";
+ reg = <0x76>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ };
+ };
+
+ gpio5: pca9539@77{
+ compatible = "nxp,pca9539";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ };
+ };
+};
+
+&i2c4 {
+ /* SMB_HSBP_STBY_LVC3_R */
+ multi-master;
+ status = "okay";
+};
+
+&i2c5 {
+ /* SMB_SMLINK0_STBY_LVC3_R2 */
+ bus-frequency = <1000000>;
+ multi-master;
+ status = "okay";
+};
+
+&i2c6 {
+ /* I2C_BMC_RISER2 */
+ multi-master;
+ status = "okay";
+
+ pca9543@70 {
+ compatible = "nxp,pca9543";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ };
+
+ pca9545@72 {
+ compatible = "nxp,pca9545";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x72>;
+ };
+};
+
+&i2c7 {
+ /* SMB_PMBUS_SML1_STBY_LVC3_R */
+ multi-master;
+ status = "okay";
+};
+
+&i2c8 {
+ /* SMB_PCIE_STBY_LVC3_R */
+ multi-master;
+ status = "okay";
+};
+
+&i2c9 {
+ /* SMB_HOST_STBY_BMC_LVC3_R */
+ multi-master;
+ status = "okay";
+};
+
+&i2c10 {
+ /* SMB_BMC0_MUX01 */
+ multi-master;
+ status = "okay";
+};
+
+&i2c12 {
+ /* SMB_CPU_PIROM */
+ multi-master;
+ status = "okay";
+};
+
+&i2c13 {
+ multi-master;
+ status = "okay";
+};
+
+&i2c15 {
+ /* SMB_TEMPSENSOR_STBY_LVC3_R */
+ multi-master;
+ status = "okay";
+
+ tmp75@48 {
+ compatible = "ti,tmp75";
+ reg = <0x48>;
+ };
+};
+
+&vhub {
+ status = "okay";
+};
--
2.7.4
---------------------------------------------------------------------------------------------------------------------------------------------------------------
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^ permalink raw reply related
* [PATCH v6 0/4] spi: dt-bindings: samsung: convert to dtschema
From: Krzysztof Kozlowski @ 2022-01-24 8:23 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Benson Leung, Guenter Roeck,
Krzysztof Kozlowski, Alim Akhtar, Andi Shyti, Mark Brown,
Sam Protsenko, Pratyush Yadav, devicetree, linux-kernel,
linux-arm-kernel, linux-samsung-soc, linux-spi
Hi,
Changes since v5
================
1. Add new patch 3 (fix indentation in example).
2. Patch 2: reference spi-peripheral-props in else.
3. Add tags.
Changes since v4
================
1. Do not require samsung,spi-feedback-delay and fold patch 3 into patch 2.
2. Rework message in patch 4.
3. Add tags.
Changes since v3
================
1. Patch 2: correct path in exynos-usi.yaml.
2. Add patch 5.
3. Add tags.
Changes since v2
================
1. Patch 2: drop child device schema, as Rob suggested.
Changes since v1
================
1. Patch 2: describe devices matching compatible, correct issues pointed out by
Rob, add reviewed-by tag.
2. New patches 3 and 4.
Best regards,
Krzysztof
Krzysztof Kozlowski (4):
spi: dt-bindings: samsung: convert to dtschema
mfd: dt-bindings: google,cros-ec: reference Samsung SPI bindings
mfd: dt-bindings: google,cros-ec: fix indentation in example
spi: s3c64xx: allow controller-data to be optional
.../bindings/mfd/google,cros-ec.yaml | 31 +--
.../bindings/soc/samsung/exynos-usi.yaml | 2 +-
.../spi/samsung,spi-peripheral-props.yaml | 33 ++++
.../devicetree/bindings/spi/samsung,spi.yaml | 187 ++++++++++++++++++
.../bindings/spi/spi-peripheral-props.yaml | 1 +
.../devicetree/bindings/spi/spi-samsung.txt | 122 ------------
MAINTAINERS | 2 +-
drivers/spi/spi-s3c64xx.c | 14 +-
8 files changed, 246 insertions(+), 146 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/samsung,spi-peripheral-props.yaml
create mode 100644 Documentation/devicetree/bindings/spi/samsung,spi.yaml
delete mode 100644 Documentation/devicetree/bindings/spi/spi-samsung.txt
--
2.32.0
^ permalink raw reply
* [PATCH v6 2/4] mfd: dt-bindings: google,cros-ec: reference Samsung SPI bindings
From: Krzysztof Kozlowski @ 2022-01-24 8:23 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Benson Leung, Guenter Roeck,
Krzysztof Kozlowski, Alim Akhtar, Andi Shyti, Mark Brown,
Sam Protsenko, Pratyush Yadav, devicetree, linux-kernel,
linux-arm-kernel, linux-samsung-soc, linux-spi
In-Reply-To: <20220124082347.32747-1-krzysztof.kozlowski@canonical.com>
The ChromeOS Embedded Controller appears on boards with Samsung Exynos
SoC, where Exynos SPI bindings expect controller-data node. Reference
SPI peripheral bindings which include now Samsung SPI peripheral parts.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/mfd/google,cros-ec.yaml | 29 ++++++++++---------
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
index d1f53bd449f7..525ab18005b3 100644
--- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
+++ b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
@@ -31,7 +31,7 @@ properties:
controller-data:
description:
- SPI controller data, see bindings/spi/spi-samsung.txt
+ SPI controller data, see bindings/spi/samsung,spi-peripheral-props.yaml
type: object
google,cros-ec-spi-pre-delay:
@@ -148,18 +148,21 @@ patternProperties:
required:
- compatible
-if:
- properties:
- compatible:
- contains:
- enum:
- - google,cros-ec-i2c
- - google,cros-ec-rpmsg
-then:
- properties:
- google,cros-ec-spi-pre-delay: false
- google,cros-ec-spi-msg-delay: false
- spi-max-frequency: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - google,cros-ec-i2c
+ - google,cros-ec-rpmsg
+ then:
+ properties:
+ google,cros-ec-spi-pre-delay: false
+ google,cros-ec-spi-msg-delay: false
+ spi-max-frequency: false
+ else:
+ $ref: /schemas/spi/spi-peripheral-props.yaml
additionalProperties: false
--
2.32.0
^ permalink raw reply related
* [PATCH v6 1/4] spi: dt-bindings: samsung: convert to dtschema
From: Krzysztof Kozlowski @ 2022-01-24 8:23 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Benson Leung, Guenter Roeck,
Krzysztof Kozlowski, Alim Akhtar, Andi Shyti, Mark Brown,
Sam Protsenko, Pratyush Yadav, devicetree, linux-kernel,
linux-arm-kernel, linux-samsung-soc, linux-spi
In-Reply-To: <20220124082347.32747-1-krzysztof.kozlowski@canonical.com>
Convert the Samsung SoC (S3C24xx, S3C64xx, S5Pv210, Exynos) SPI
controller bindings to DT schema format.
The conversion also drops requirement from providing controller-data and
its data for each of SPI peripheral device nodes. The dtschema cannot
express this and the requirement is being relaxed in the driver now.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
---
.../bindings/soc/samsung/exynos-usi.yaml | 2 +-
.../spi/samsung,spi-peripheral-props.yaml | 33 ++++
.../devicetree/bindings/spi/samsung,spi.yaml | 187 ++++++++++++++++++
.../bindings/spi/spi-peripheral-props.yaml | 1 +
.../devicetree/bindings/spi/spi-samsung.txt | 122 ------------
MAINTAINERS | 2 +-
6 files changed, 223 insertions(+), 124 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/samsung,spi-peripheral-props.yaml
create mode 100644 Documentation/devicetree/bindings/spi/samsung,spi.yaml
delete mode 100644 Documentation/devicetree/bindings/spi/spi-samsung.txt
diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
index 58f2e9d8bb0e..d10ec742a6a5 100644
--- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
@@ -22,7 +22,7 @@ description: |
[1] Documentation/devicetree/bindings/serial/samsung_uart.yaml
[2] Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
- [3] Documentation/devicetree/bindings/spi/spi-samsung.txt
+ [3] Documentation/devicetree/bindings/spi/samsung,spi.yaml
properties:
$nodename:
diff --git a/Documentation/devicetree/bindings/spi/samsung,spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/samsung,spi-peripheral-props.yaml
new file mode 100644
index 000000000000..f0db3fb3d688
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/samsung,spi-peripheral-props.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/samsung,spi-peripheral-props.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Peripheral-specific properties for Samsung S3C/S5P/Exynos SoC SPI controller
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+description:
+ See spi-peripheral-props.yaml for more info.
+
+properties:
+ controller-data:
+ type: object
+ additionalProperties: false
+
+ properties:
+ samsung,spi-feedback-delay:
+ description: |
+ The sampling phase shift to be applied on the miso line (to account
+ for any lag in the miso line). Valid values:
+ - 0: No phase shift.
+ - 1: 90 degree phase shift sampling.
+ - 2: 180 degree phase shift sampling.
+ - 3: 270 degree phase shift sampling.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Documentation/devicetree/bindings/spi/samsung,spi.yaml
new file mode 100644
index 000000000000..61c77088e8ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml
@@ -0,0 +1,187 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/samsung,spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S3C/S5P/Exynos SoC SPI controller
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+description:
+ All the SPI controller nodes should be represented in the aliases node using
+ the following format 'spi{n}' where n is a unique number for the alias.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450
+ - samsung,s3c6410-spi
+ - samsung,s5pv210-spi # for S5PV210 and S5PC110
+ - samsung,exynos5433-spi
+ - const: samsung,exynos7-spi
+ deprecated: true
+
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+ clock-names:
+ minItems: 2
+ maxItems: 3
+
+ cs-gpios: true
+
+ dmas:
+ minItems: 2
+ maxItems: 2
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+ interrupts:
+ maxItems: 1
+
+ no-cs-readback:
+ description:
+ The CS line is disconnected, therefore the device should not operate
+ based on CS signalling.
+ type: boolean
+
+ num-cs:
+ minimum: 1
+ maximum: 4
+ default: 1
+
+ samsung,spi-src-clk:
+ description:
+ If the spi controller includes a internal clock mux to select the clock
+ source for the spi bus clock, this property can be used to indicate the
+ clock to be used for driving the spi bus clock. If not specified, the
+ clock number 0 is used as default.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - dmas
+ - dma-names
+ - interrupts
+ - reg
+
+allOf:
+ - $ref: spi-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-spi
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: spi
+ - enum:
+ - spi_busclk0
+ - spi_busclk1
+ - spi_busclk2
+ - spi_busclk3
+ - const: spi_ioclk
+ else:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: spi
+ - enum:
+ - spi_busclk0
+ - spi_busclk1
+ - spi_busclk2
+ - spi_busclk3
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5433.h>
+ #include <dt-bindings/clock/samsung,s2mps11.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi@14d30000 {
+ compatible = "samsung,exynos5433-spi";
+ reg = <0x14d30000 0x100>;
+ interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&pdma0 11>, <&pdma0 10>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_peric CLK_PCLK_SPI1>,
+ <&cmu_peric CLK_SCLK_SPI1>,
+ <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
+ clock-names = "spi",
+ "spi_busclk0",
+ "spi_ioclk";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_bus>;
+ num-cs = <1>;
+
+ cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
+
+ audio-codec@0 {
+ compatible = "wlf,wm5110";
+ reg = <0x0>;
+ spi-max-frequency = <20000000>;
+ interrupt-parent = <&gpa0>;
+ interrupts = <4 IRQ_TYPE_NONE>;
+ clocks = <&pmu_system_controller 0>,
+ <&s2mps13_osc S2MPS11_CLK_BT>;
+ clock-names = "mclk1", "mclk2";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ wlf,micd-detect-debounce = <300>;
+ wlf,micd-bias-start-time = <0x1>;
+ wlf,micd-rate = <0x7>;
+ wlf,micd-dbtime = <0x2>;
+ wlf,micd-force-micbias;
+ wlf,micd-configs = <0x0 1 0>;
+ wlf,hpdet-channel = <1>;
+ wlf,gpsw = <0x1>;
+ wlf,inmode = <2 0 2 0>;
+
+ wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
+ wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
+
+ /* core supplies */
+ AVDD-supply = <&ldo18_reg>;
+ DBVDD1-supply = <&ldo18_reg>;
+ CPVDD-supply = <&ldo18_reg>;
+ DBVDD2-supply = <&ldo18_reg>;
+ DBVDD3-supply = <&ldo18_reg>;
+ SPKVDDL-supply = <&ldo18_reg>;
+ SPKVDDR-supply = <&ldo18_reg>;
+
+ controller-data {
+ samsung,spi-feedback-delay = <0>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
index 5dd209206e88..df885eeb144f 100644
--- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
@@ -85,5 +85,6 @@ properties:
# The controller specific properties go here.
allOf:
- $ref: cdns,qspi-nor-peripheral-props.yaml#
+ - $ref: samsung,spi-peripheral-props.yaml#
additionalProperties: true
diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt
deleted file mode 100644
index 49028a4f5df1..000000000000
--- a/Documentation/devicetree/bindings/spi/spi-samsung.txt
+++ /dev/null
@@ -1,122 +0,0 @@
-* Samsung SPI Controller
-
-The Samsung SPI controller is used to interface with various devices such as flash
-and display controllers using the SPI communication interface.
-
-Required SoC Specific Properties:
-
-- compatible: should be one of the following.
- - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
- - samsung,s3c6410-spi: for s3c6410 platforms
- - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
- - samsung,exynos5433-spi: for exynos5433 compatible controllers
- - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- interrupts: The interrupt number to the cpu. The interrupt specifier format
- depends on the interrupt controller.
-
-- dmas : Two or more DMA channel specifiers following the convention outlined
- in bindings/dma/dma.txt
-
-- dma-names: Names for the dma channels. There must be at least one channel
- named "tx" for transmit and named "rx" for receive.
-
-- clocks: specifies the clock IDs provided to the SPI controller; they are
- required for interacting with the controller itself, for synchronizing the bus
- and as I/O clock (the latter is required by exynos5433 and exynos7).
-
-- clock-names: string names of the clocks in the 'clocks' property; for all the
- the devices the names must be "spi", "spi_busclkN" (where N is determined by
- "samsung,spi-src-clk"), while Exynos5433 should specify a third clock
- "spi_ioclk" for the I/O clock.
-
-Required Board Specific Properties:
-
-- #address-cells: should be 1.
-- #size-cells: should be 0.
-
-Optional Board Specific Properties:
-
-- samsung,spi-src-clk: If the spi controller includes a internal clock mux to
- select the clock source for the spi bus clock, this property can be used to
- indicate the clock to be used for driving the spi bus clock. If not specified,
- the clock number 0 is used as default.
-
-- num-cs: Specifies the number of chip select lines supported. If
- not specified, the default number of chip select lines is set to 1.
-
-- cs-gpios: should specify GPIOs used for chipselects (see spi-bus.txt)
-
-- no-cs-readback: the CS line is disconnected, therefore the device should not
- operate based on CS signalling.
-
-SPI Controller specific data in SPI slave nodes:
-
-- The spi slave nodes should provide the following information which is required
- by the spi controller.
-
- - samsung,spi-feedback-delay: The sampling phase shift to be applied on the
- miso line (to account for any lag in the miso line). The following are the
- valid values.
-
- - 0: No phase shift.
- - 1: 90 degree phase shift sampling.
- - 2: 180 degree phase shift sampling.
- - 3: 270 degree phase shift sampling.
-
-Aliases:
-
-- All the SPI controller nodes should be represented in the aliases node using
- the following format 'spi{n}' where n is a unique number for the alias.
-
-
-Example:
-
-- SoC Specific Portion:
-
- spi_0: spi@12d20000 {
- compatible = "samsung,exynos4210-spi";
- reg = <0x12d20000 0x100>;
- interrupts = <0 66 0>;
- dmas = <&pdma0 5
- &pdma0 4>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
-- Board Specific Portion:
-
- spi_0: spi@12d20000 {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_bus>;
- cs-gpios = <&gpa2 5 0>;
-
- w25q80bw@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "w25x80";
- reg = <0>;
- spi-max-frequency = <10000>;
-
- controller-data {
- samsung,spi-feedback-delay = <0>;
- };
-
- partition@0 {
- label = "U-Boot";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "Kernel";
- reg = <0x40000 0xc0000>;
- };
- };
- };
diff --git a/MAINTAINERS b/MAINTAINERS
index 77c01b55099c..f0b083b279de 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17114,7 +17114,7 @@ M: Andi Shyti <andi@etezian.org>
L: linux-spi@vger.kernel.org
L: linux-samsung-soc@vger.kernel.org
S: Maintained
-F: Documentation/devicetree/bindings/spi/spi-samsung.txt
+F: Documentation/devicetree/bindings/spi/samsung,spi*.yaml
F: drivers/spi/spi-s3c*
F: include/linux/platform_data/spi-s3c64xx.h
F: include/linux/spi/s3c24xx-fiq.h
--
2.32.0
^ permalink raw reply related
* [PATCH v6 4/4] spi: s3c64xx: allow controller-data to be optional
From: Krzysztof Kozlowski @ 2022-01-24 8:23 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Benson Leung, Guenter Roeck,
Krzysztof Kozlowski, Alim Akhtar, Andi Shyti, Mark Brown,
Sam Protsenko, Pratyush Yadav, devicetree, linux-kernel,
linux-arm-kernel, linux-samsung-soc, linux-spi
Cc: Rob Herring
In-Reply-To: <20220124082347.32747-1-krzysztof.kozlowski@canonical.com>
The Samsung SoC SPI driver requires to provide controller-data node
for each of SPI peripheral device nodes. Make this controller-data node
optional, so DTS could be simpler.
Suggested-by: Rob Herring <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Andi Shyti <andi@etezian.org>
---
drivers/spi/spi-s3c64xx.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 8755cd85e83c..386550fca81c 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -796,16 +796,14 @@ static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
return ERR_PTR(-EINVAL);
}
- data_np = of_get_child_by_name(slave_np, "controller-data");
- if (!data_np) {
- dev_err(&spi->dev, "child node 'controller-data' not found\n");
- return ERR_PTR(-EINVAL);
- }
-
cs = kzalloc(sizeof(*cs), GFP_KERNEL);
- if (!cs) {
- of_node_put(data_np);
+ if (!cs)
return ERR_PTR(-ENOMEM);
+
+ data_np = of_get_child_by_name(slave_np, "controller-data");
+ if (!data_np) {
+ dev_info(&spi->dev, "feedback delay set to default (0)\n");
+ return cs;
}
of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
--
2.32.0
^ permalink raw reply related
* [PATCH v6 3/4] mfd: dt-bindings: google,cros-ec: fix indentation in example
From: Krzysztof Kozlowski @ 2022-01-24 8:23 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Benson Leung, Guenter Roeck,
Krzysztof Kozlowski, Alim Akhtar, Andi Shyti, Mark Brown,
Sam Protsenko, Pratyush Yadav, devicetree, linux-kernel,
linux-arm-kernel, linux-samsung-soc, linux-spi
In-Reply-To: <20220124082347.32747-1-krzysztof.kozlowski@canonical.com>
Correct level of indentation in the example.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
Documentation/devicetree/bindings/mfd/google,cros-ec.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
index 525ab18005b3..4caadf73fc4a 100644
--- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
+++ b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
@@ -203,7 +203,7 @@ examples:
spi-max-frequency = <5000000>;
proximity {
- compatible = "google,cros-ec-mkbp-proximity";
+ compatible = "google,cros-ec-mkbp-proximity";
};
cbas {
--
2.32.0
^ permalink raw reply related
* [PATCH v2 0/2] Enable i.MX7 SOLO temperature sensor
From: Francesco Dolcini @ 2022-01-24 8:28 UTC (permalink / raw)
To: Rob Herring, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Rafael J. Wysocki, Viresh Kumar,
Matthias Brugger
Cc: Francesco Dolcini, devicetree, linux-arm-kernel, linux-pm,
linux-kernel, Marcel Ziswiler, Denys Drozdov, Stefan Agner
To be able to read the T junction on i.MX CPU the imx-cpufreq-dt needs to be
loaded, however this is currently not the case for i.MX7S given that it does
have only one operating frequency.
Add "fsl,imx7s" to cpufreq-dt-platdev blocklist and a single frequency
operating point to the CPU.
With that it is now possible to correctly read the CPU T junction.
Tested on Toradex Colibri iMX7S
[ 6.232577] imx-cpufreq-dt imx-cpufreq-dt: cpu speed grade 0 mkt segment 1 supported-hw 0x1 0x2
...
[ 6.880624] imx_thermal 30360000.anatop:tempmon: Extended Commercial CPU temperature grade - max:105C critical:100C passive:95C
root@colibri-imx7-02983025:~# cat /sys/class/thermal/thermal_zone0/temp
38000
v2:
- removed empty new line
- rebased and tested on v5.17-rc1
Denys Drozdov (1):
ARM: dts: imx7s: Define operating points table for cpufreq
Stefan Agner (1):
cpufreq: Add i.MX7S to cpufreq-dt-platdev blocklist
arch/arm/boot/dts/imx7s.dtsi | 16 ++++++++++++++++
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
2 files changed, 17 insertions(+)
--
2.25.1
^ permalink raw reply
* [PATCH v2 2/2] cpufreq: Add i.MX7S to cpufreq-dt-platdev blocklist
From: Francesco Dolcini @ 2022-01-24 8:28 UTC (permalink / raw)
To: Rob Herring, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Rafael J. Wysocki, Viresh Kumar,
Matthias Brugger
Cc: Stefan Agner, devicetree, linux-arm-kernel, linux-pm,
linux-kernel, Marcel Ziswiler, Denys Drozdov, Stefan Agner,
Francesco Dolcini
In-Reply-To: <20220124082803.94286-1-francesco.dolcini@toradex.com>
From: Stefan Agner <stefan.agner@toradex.com>
The i.MX 7Solo currently does not have multiple operating points,
however, in order for the i.MX Thermal driver to successfully probe
a cpufreq device is required. Add it to the cpufreq-dt-platdev
driver's blocklist to allow using imx-cpufreq-dt.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Cc: Stefan Agner <stefan@agner.ch>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
---
v2: removed empty line
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index ca1d103ec449..6b808f805eab 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -110,6 +110,7 @@ static const struct of_device_id blocklist[] __initconst = {
{ .compatible = "fsl,imx7ulp", },
{ .compatible = "fsl,imx7d", },
+ { .compatible = "fsl,imx7s", },
{ .compatible = "fsl,imx8mq", },
{ .compatible = "fsl,imx8mm", },
{ .compatible = "fsl,imx8mn", },
--
2.25.1
^ permalink raw reply related
* [PATCH v2 1/2] ARM: dts: imx7s: Define operating points table for cpufreq
From: Francesco Dolcini @ 2022-01-24 8:28 UTC (permalink / raw)
To: Rob Herring, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Rafael J. Wysocki, Viresh Kumar,
Matthias Brugger
Cc: Denys Drozdov, devicetree, linux-arm-kernel, linux-pm,
linux-kernel, Marcel Ziswiler, Francesco Dolcini
In-Reply-To: <20220124082803.94286-1-francesco.dolcini@toradex.com>
From: Denys Drozdov <denys.drozdov@toradex.com>
Processor operating points for imx7s.dtsi should be properly defined to
perform correct imx-cpufreq-dt probe and registration and provide an
access to the temperature sensors using the i.MX thermal driver.
Signed-off-by: Denys Drozdov <denys.drozdov@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
---
v2: no changes
---
arch/arm/boot/dts/imx7s.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 52a9aeecdbb2..5af6d58666f4 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -76,6 +76,22 @@ cpu0: cpu@0 {
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX7D_CLK_ARM>;
cpu-idle-states = <&cpu_sleep_wait>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ nvmem-cells = <&fuse_grade>;
+ nvmem-cell-names = "speed_grade";
+ };
+ };
+
+ cpu0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-792000000 {
+ opp-hz = /bits/ 64 <792000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <150000>;
+ opp-supported-hw = <0xf>, <0xf>;
};
};
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Bananapi R2 Pro
From: Sascha Hauer @ 2022-01-24 8:31 UTC (permalink / raw)
To: Frank Wunderlich
Cc: linux-rockchip, Frank Wunderlich, Rob Herring, Heiko Stuebner,
Peter Geis, Johan Jonker, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <20220123135116.136846-3-linux@fw-web.de>
On Sun, Jan 23, 2022 at 02:51:16PM +0100, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
>
> This patch adds Devicetree for Bananapi R2 Pro based on RK3568.
> Add uart/sd/emmc/i2c/rk809/tsadc nodes for basic function.
> Gmac0 is directly connected to wan-port so usable without additional
> driver.
> On gmac1 there is a switch (rtl8367rb) connected which have not yet a
> driver in mainline.
>
> Patch also prepares nodes for GPIO header.
>
> Co-developed-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
> +&gmac0 {
> + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
> + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
> + clock_in_out = "input";
> + phy-handle = <&rgmii_phy0>;
> + phy-mode = "rgmii";
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac0_miim
> + &gmac0_tx_bus2
> + &gmac0_rx_bus2
> + &gmac0_rgmii_clk
> + &gmac0_rgmii_bus>;
> +
> + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
> + snps,reset-active-low;
> + /* Reset time is 20ms, 100ms for rtl8211f */
Is this really a rtl8211f? I don't know and it could indeed be a
rtl8211f, I'm just asking because the comment is copy pasted from
the Quartz64 board.
> + snps,reset-delays-us = <0 20000 100000>;
> +
> +&mdio0 {
> + rgmii_phy0: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0x0>;
> + };
0 is the broadcast address. I'm not sure if it's a good idea to use it.
There should be another address the phy listens on.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH v20 0/5] support reserving crashkernel above 4G on arm64 kdump
From: Zhen Lei @ 2022-01-24 8:47 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Borislav Petkov, x86,
H . Peter Anvin, linux-kernel, Dave Young, Baoquan He,
Vivek Goyal, Eric Biederman, kexec, Catalin Marinas, Will Deacon,
linux-arm-kernel, Rob Herring, Frank Rowand, devicetree,
Jonathan Corbet, linux-doc
Cc: Zhen Lei, Randy Dunlap, Feng Zhou, Kefeng Wang, Chen Zhou,
John Donnelly, Dave Kleikamp
There are following issues in arm64 kdump:
1. We use crashkernel=X to reserve crashkernel below 4G, which
will fail when there is no enough low memory.
2. If reserving crashkernel above 4G, in this case, crash dump
kernel will boot failure because there is no low memory available
for allocation.
To solve these issues, change the behavior of crashkernel=X.
crashkernel=X tries low allocation in DMA zone and fall back to high
allocation if it fails.
We can also use "crashkernel=X,high" to select a high region above
DMA zone, which also tries to allocate at least 256M low memory in
DMA zone automatically and "crashkernel=Y,low" can be used to allocate
specified size low memory.
When reserving crashkernel in high memory, some low memory is reserved
for crash dump kernel devices. So there may be two regions reserved for
crash dump kernel.
In order to distinct from the high region and make no effect to the use
of existing kexec-tools, rename the low region as "Crash kernel (low)",
and pass the low region by reusing DT property
"linux,usable-memory-range". We made the low memory region as the last
range of "linux,usable-memory-range" to keep compatibility with existing
user-space and older kdump kernels.
Besides, we need to modify kexec-tools:
arm64: support more than one crash kernel regions(see [1])
Another update is document about DT property 'linux,usable-memory-range':
schemas: update 'linux,usable-memory-range' node schema(see [2])
Changes since [v19]:
1. Temporarily stop making reserve_crashkernel[_low]() generic. There are a
lot of details need to be considered, which can take a long time. Because
"make generic" does not add new functions and does not improve performance,
maybe I should say it's just a cleanup. So by stripping it out and leaving
it for other patches later, we can aggregate the changes to the main functions.
2. Use insert_resource() to replace request_resource(), this not only simplifies
the code, but also reduces the differences between arm64 and x86 implementations.
3. As commit 157752d84f5d ("kexec: use Crash kernel for Crash kernel low") do for
x86, we can also extend kexec-tools for arm64, and it's currently applied. See:
https://www.spinics.net/lists/kexec/msg28284.html
Thank you very much, Borislav Petkov, for so many valuable comments.
Changes since [v17]: v17 --> v19
1. Patch 0001-0004
Introduce generic parse_crashkernel_high_low() to bring the parsing of
"crashkernel=X,high" and the parsing of "crashkernel=X,low" together,
then use it instead of the call to parse_crashkernel_{high|low}(). Two
confusing parameters of parse_crashkernel_{high|low}() are deleted.
I previously sent these four patches separately:
[1] https://lkml.org/lkml/2021/12/25/40
2. Patch 0005-0009
Introduce generic reserve_crashkernel_mem[_low](), the implementation of
these two functions is based on function reserve_crashkernel[_low]() in
arch/x86/kernel/setup.c. There is no functional change for x86.
1) The check position of xen_pv_domain() does not change.
2) Still 1M alignment for crash kernel fixed region, when 'base' is specified.
To avoid compilation problems on other architectures: patch 0004 moves
the definition of global variable crashk[_low]_res from kexec_core.c to
crash_core.c, and provide default definitions for all macros involved, a
particular platform can redefine these macros to override the default
values.
3. 0010, only one line of comment was changed.
4. 0011
1) crashk_low_res may also a valid reserved memory, should be checked
in crash_is_nosave(), see arch/arm64/kernel/machine_kexec.
2) Drop memblock_mark_nomap() for crashk_low_res, because of:
2687275a5843 arm64: Force NO_BLOCK_MAPPINGS if crashkernel reservation is required
3) Also call kmemleak_ignore_phys() for crashk_low_res, because of:
85f58eb18898 arm64: kdump: Skip kmemleak scan reserved memory for kdump
5. 0012, slightly rebased, because the following patch is applied in advance.
https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git/commit/?h=dt/linus&id=8347b41748c3019157312fbe7f8a6792ae396eb7
6. 0013, no change.
Others:
1. Discard add ARCH_WANT_RESERVE_CRASH_KERNEL
2. When allocating crash low memory, the start address still starts from 0.
low_base = memblock_phys_alloc_range(low_size, CRASH_ALIGN, 0, CRASH_ADDR_LOW_MAX);
3. Discard change (1ULL << 32) to CRASH_ADDR_LOW_MAX.
4. Ensure the check position of xen_pv_domain() have no change.
5. Except patch 0010 and 0012, all "Tested-by", "Reviewed-by", "Acked-by" are removed.
6. Update description.
Changes since [v16]
- Because no functional changes in this version, so add
"Tested-by: Dave Kleikamp <dave.kleikamp@oracle.com>" for patch 1-9
- Add "Reviewed-by: Rob Herring <robh@kernel.org>" for patch 8
- Update patch 9 based on the review comments of Rob Herring
- As Catalin Marinas's suggestion, merge the implementation of
ARCH_WANT_RESERVE_CRASH_KERNEL into patch 5. Ensure that the
contents of X86 and ARM64 do not overlap, and reduce unnecessary
temporary differences.
Changes since [v15]
- Aggregate the processing of "linux,usable-memory-range" into one function.
Only patch 9-10 have been updated.
Changes since [v14]
- Recovering the requirement that the CrashKernel memory regions on X86
only requires 1 MiB alignment.
- Combine patches 5 and 6 in v14 into one. The compilation warning fixed
by patch 6 was introduced by patch 5 in v14.
- As with crashk_res, crashk_low_res is also processed by
crash_exclude_mem_range() in patch 7.
- Due to commit b261dba2fdb2 ("arm64: kdump: Remove custom linux,usable-memory-range handling")
has removed the architecture-specific code, extend the property "linux,usable-memory-range"
in the platform-agnostic FDT core code. See patch 9.
- Discard the x86 description update in the document, because the description
has been updated by commit b1f4c363666c ("Documentation: kdump: update kdump guide").
- Change "arm64" to "ARM64" in Doc.
Changes since [v13]
- Rebased on top of 5.11-rc5.
- Introduce config CONFIG_ARCH_WANT_RESERVE_CRASH_KERNEL.
Since reserve_crashkernel[_low]() implementations are quite similar on
other architectures, so have CONFIG_ARCH_WANT_RESERVE_CRASH_KERNEL in
arch/Kconfig and select this by X86 and ARM64.
- Some minor cleanup.
Changes since [v12]
- Rebased on top of 5.10-rc1.
- Keep CRASH_ALIGN as 16M suggested by Dave.
- Drop patch "kdump: add threshold for the required memory".
- Add Tested-by from John.
Changes since [v11]
- Rebased on top of 5.9-rc4.
- Make the function reserve_crashkernel() of x86 generic.
Suggested by Catalin, make the function reserve_crashkernel() of x86 generic
and arm64 use the generic version to reimplement crashkernel=X.
Changes since [v10]
- Reimplement crashkernel=X suggested by Catalin, Many thanks to Catalin.
Changes since [v9]
- Patch 1 add Acked-by from Dave.
- Update patch 5 according to Dave's comments.
- Update chosen schema.
Changes since [v8]
- Reuse DT property "linux,usable-memory-range".
Suggested by Rob, reuse DT property "linux,usable-memory-range" to pass the low
memory region.
- Fix kdump broken with ZONE_DMA reintroduced.
- Update chosen schema.
Changes since [v7]
- Move x86 CRASH_ALIGN to 2M
Suggested by Dave and do some test, move x86 CRASH_ALIGN to 2M.
- Update Documentation/devicetree/bindings/chosen.txt.
Add corresponding documentation to Documentation/devicetree/bindings/chosen.txt
suggested by Arnd.
- Add Tested-by from Jhon and pk.
Changes since [v6]
- Fix build errors reported by kbuild test robot.
Changes since [v5]
- Move reserve_crashkernel_low() into kernel/crash_core.c.
- Delete crashkernel=X,high.
- Modify crashkernel=X,low.
If crashkernel=X,low is specified simultaneously, reserve spcified size low
memory for crash kdump kernel devices firstly and then reserve memory above 4G.
In addition, rename crashk_low_res as "Crash kernel (low)" for arm64, and then
pass to crash dump kernel by DT property "linux,low-memory-range".
- Update Documentation/admin-guide/kdump/kdump.rst.
Changes since [v4]
- Reimplement memblock_cap_memory_ranges for multiple ranges by Mike.
Changes since [v3]
- Add memblock_cap_memory_ranges back for multiple ranges.
- Fix some compiling warnings.
Changes since [v2]
- Split patch "arm64: kdump: support reserving crashkernel above 4G" as
two. Put "move reserve_crashkernel_low() into kexec_core.c" in a separate
patch.
Changes since [v1]:
- Move common reserve_crashkernel_low() code into kernel/kexec_core.c.
- Remove memblock_cap_memory_ranges() i added in v1 and implement that
in fdt_enforce_memory_region().
There are at most two crash kernel regions, for two crash kernel regions
case, we cap the memory range [min(regs[*].start), max(regs[*].end)]
and then remove the memory range in the middle.
[1]: https://www.spinics.net/lists/kexec/msg28226.html
[2]: https://github.com/robherring/dt-schema/pull/19
[v1]: https://lkml.org/lkml/2019/4/2/1174
[v2]: https://lkml.org/lkml/2019/4/9/86
[v3]: https://lkml.org/lkml/2019/4/9/306
[v4]: https://lkml.org/lkml/2019/4/15/273
[v5]: https://lkml.org/lkml/2019/5/6/1360
[v6]: https://lkml.org/lkml/2019/8/30/142
[v7]: https://lkml.org/lkml/2019/12/23/411
[v8]: https://lkml.org/lkml/2020/5/21/213
[v9]: https://lkml.org/lkml/2020/6/28/73
[v10]: https://lkml.org/lkml/2020/7/2/1443
[v11]: https://lkml.org/lkml/2020/8/1/150
[v12]: https://lkml.org/lkml/2020/9/7/1037
[v13]: https://lkml.org/lkml/2020/10/31/34
[v14]: https://lkml.org/lkml/2021/1/30/53
[v15]: https://lkml.org/lkml/2021/10/19/1405
[v16]: https://lkml.org/lkml/2021/11/23/435
[v17]: https://lkml.org/lkml/2021/12/10/38
[v18]: https://lkml.org/lkml/2021/12/22/424
[v19]: https://lkml.org/lkml/2021/12/28/203
Chen Zhou (4):
arm64: kdump: introduce some macros for crash kernel reservation
arm64: kdump: reimplement crashkernel=X
of: fdt: Add memory for devices by DT property
"linux,usable-memory-range"
kdump: update Documentation about crashkernel
Zhen Lei (1):
arm64: Use insert_resource() to simplify code
Documentation/admin-guide/kdump/kdump.rst | 11 ++-
.../admin-guide/kernel-parameters.txt | 11 ++-
arch/arm64/kernel/machine_kexec.c | 9 ++-
arch/arm64/kernel/machine_kexec_file.c | 12 ++-
arch/arm64/kernel/setup.c | 17 +---
arch/arm64/mm/init.c | 80 +++++++++++++++++--
drivers/of/fdt.c | 33 +++++---
7 files changed, 134 insertions(+), 39 deletions(-)
--
2.25.1
^ permalink raw reply
* [PATCH v20 1/5] arm64: Use insert_resource() to simplify code
From: Zhen Lei @ 2022-01-24 8:47 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Borislav Petkov, x86,
H . Peter Anvin, linux-kernel, Dave Young, Baoquan He,
Vivek Goyal, Eric Biederman, kexec, Catalin Marinas, Will Deacon,
linux-arm-kernel, Rob Herring, Frank Rowand, devicetree,
Jonathan Corbet, linux-doc
Cc: Zhen Lei, Randy Dunlap, Feng Zhou, Kefeng Wang, Chen Zhou,
John Donnelly, Dave Kleikamp
In-Reply-To: <20220124084708.683-1-thunder.leizhen@huawei.com>
insert_resource() traverses the subtree layer by layer from the root node
until a proper location is found. Compared with request_resource(), the
parent node does not need to be determined in advance.
In addition, move the insertion of node 'crashk_res' into function
reserve_crashkernel() to make the associated code close together.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
arch/arm64/kernel/setup.c | 17 +++--------------
arch/arm64/mm/init.c | 1 +
2 files changed, 4 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index f70573928f1bff0..a81efcc359e4e78 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -225,6 +225,8 @@ static void __init request_standard_resources(void)
kernel_code.end = __pa_symbol(__init_begin - 1);
kernel_data.start = __pa_symbol(_sdata);
kernel_data.end = __pa_symbol(_end - 1);
+ insert_resource(&iomem_resource, &kernel_code);
+ insert_resource(&iomem_resource, &kernel_data);
num_standard_resources = memblock.memory.cnt;
res_size = num_standard_resources * sizeof(*standard_resources);
@@ -246,20 +248,7 @@ static void __init request_standard_resources(void)
res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
}
- request_resource(&iomem_resource, res);
-
- if (kernel_code.start >= res->start &&
- kernel_code.end <= res->end)
- request_resource(res, &kernel_code);
- if (kernel_data.start >= res->start &&
- kernel_data.end <= res->end)
- request_resource(res, &kernel_data);
-#ifdef CONFIG_KEXEC_CORE
- /* Userspace will find "Crash kernel" region in /proc/iomem. */
- if (crashk_res.end && crashk_res.start >= res->start &&
- crashk_res.end <= res->end)
- request_resource(res, &crashk_res);
-#endif
+ insert_resource(&iomem_resource, res);
}
}
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index db63cc885771a52..90f276d46b93bc6 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -109,6 +109,7 @@ static void __init reserve_crashkernel(void)
kmemleak_ignore_phys(crash_base);
crashk_res.start = crash_base;
crashk_res.end = crash_base + crash_size - 1;
+ insert_resource(&iomem_resource, &crashk_res);
}
#else
static void __init reserve_crashkernel(void)
--
2.25.1
^ permalink raw reply related
* [PATCH v20 2/5] arm64: kdump: introduce some macros for crash kernel reservation
From: Zhen Lei @ 2022-01-24 8:47 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Borislav Petkov, x86,
H . Peter Anvin, linux-kernel, Dave Young, Baoquan He,
Vivek Goyal, Eric Biederman, kexec, Catalin Marinas, Will Deacon,
linux-arm-kernel, Rob Herring, Frank Rowand, devicetree,
Jonathan Corbet, linux-doc
Cc: Zhen Lei, Randy Dunlap, Feng Zhou, Kefeng Wang, Chen Zhou,
John Donnelly, Dave Kleikamp
In-Reply-To: <20220124084708.683-1-thunder.leizhen@huawei.com>
From: Chen Zhou <chenzhou10@huawei.com>
Introduce macro CRASH_ALIGN for alignment, macro CRASH_ADDR_LOW_MAX
for upper bound of low crash memory, macro CRASH_ADDR_HIGH_MAX for
upper bound of high crash memory, use macros instead.
Signed-off-by: Chen Zhou <chenzhou10@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Tested-by: John Donnelly <John.p.donnelly@oracle.com>
Tested-by: Dave Kleikamp <dave.kleikamp@oracle.com>
---
arch/arm64/mm/init.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 90f276d46b93bc6..6c653a2c7cff052 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -65,6 +65,12 @@ EXPORT_SYMBOL(memstart_addr);
phys_addr_t arm64_dma_phys_limit __ro_after_init;
#ifdef CONFIG_KEXEC_CORE
+/* Current arm64 boot protocol requires 2MB alignment */
+#define CRASH_ALIGN SZ_2M
+
+#define CRASH_ADDR_LOW_MAX arm64_dma_phys_limit
+#define CRASH_ADDR_HIGH_MAX MEMBLOCK_ALLOC_ACCESSIBLE
+
/*
* reserve_crashkernel() - reserves memory for crash kernel
*
@@ -75,7 +81,7 @@ phys_addr_t arm64_dma_phys_limit __ro_after_init;
static void __init reserve_crashkernel(void)
{
unsigned long long crash_base, crash_size;
- unsigned long long crash_max = arm64_dma_phys_limit;
+ unsigned long long crash_max = CRASH_ADDR_LOW_MAX;
int ret;
ret = parse_crashkernel(boot_command_line, memblock_phys_mem_size(),
@@ -90,8 +96,7 @@ static void __init reserve_crashkernel(void)
if (crash_base)
crash_max = crash_base + crash_size;
- /* Current arm64 boot protocol requires 2MB alignment */
- crash_base = memblock_phys_alloc_range(crash_size, SZ_2M,
+ crash_base = memblock_phys_alloc_range(crash_size, CRASH_ALIGN,
crash_base, crash_max);
if (!crash_base) {
pr_warn("cannot allocate crashkernel (size:0x%llx)\n",
--
2.25.1
^ permalink raw reply related
* [PATCH v20 3/5] arm64: kdump: reimplement crashkernel=X
From: Zhen Lei @ 2022-01-24 8:47 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Borislav Petkov, x86,
H . Peter Anvin, linux-kernel, Dave Young, Baoquan He,
Vivek Goyal, Eric Biederman, kexec, Catalin Marinas, Will Deacon,
linux-arm-kernel, Rob Herring, Frank Rowand, devicetree,
Jonathan Corbet, linux-doc
Cc: Zhen Lei, Randy Dunlap, Feng Zhou, Kefeng Wang, Chen Zhou,
John Donnelly, Dave Kleikamp
In-Reply-To: <20220124084708.683-1-thunder.leizhen@huawei.com>
From: Chen Zhou <chenzhou10@huawei.com>
There are following issues in arm64 kdump:
1. We use crashkernel=X to reserve crashkernel below 4G, which
will fail when there is no enough low memory.
2. If reserving crashkernel above 4G, in this case, crash dump
kernel will boot failure because there is no low memory available
for allocation.
To solve these issues, change the behavior of crashkernel=X and
introduce crashkernel=X,[high,low]. crashkernel=X tries low allocation
in DMA zone, and fall back to high allocation if it fails.
We can also use "crashkernel=X,high" to select a region above DMA zone,
which also tries to allocate at least 256M in DMA zone automatically.
"crashkernel=Y,low" can be used to allocate specified size low memory.
Signed-off-by: Chen Zhou <chenzhou10@huawei.com>
Co-developed-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
arch/arm64/kernel/machine_kexec.c | 9 +++-
arch/arm64/kernel/machine_kexec_file.c | 12 ++++-
arch/arm64/mm/init.c | 68 ++++++++++++++++++++++++--
3 files changed, 81 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/kernel/machine_kexec.c b/arch/arm64/kernel/machine_kexec.c
index e16b248699d5c3c..19c2d487cb08feb 100644
--- a/arch/arm64/kernel/machine_kexec.c
+++ b/arch/arm64/kernel/machine_kexec.c
@@ -329,8 +329,13 @@ bool crash_is_nosave(unsigned long pfn)
/* in reserved memory? */
addr = __pfn_to_phys(pfn);
- if ((addr < crashk_res.start) || (crashk_res.end < addr))
- return false;
+ if ((addr < crashk_res.start) || (crashk_res.end < addr)) {
+ if (!crashk_low_res.end)
+ return false;
+
+ if ((addr < crashk_low_res.start) || (crashk_low_res.end < addr))
+ return false;
+ }
if (!kexec_crash_image)
return true;
diff --git a/arch/arm64/kernel/machine_kexec_file.c b/arch/arm64/kernel/machine_kexec_file.c
index 59c648d51848886..889951291cc0f9c 100644
--- a/arch/arm64/kernel/machine_kexec_file.c
+++ b/arch/arm64/kernel/machine_kexec_file.c
@@ -65,10 +65,18 @@ static int prepare_elf_headers(void **addr, unsigned long *sz)
/* Exclude crashkernel region */
ret = crash_exclude_mem_range(cmem, crashk_res.start, crashk_res.end);
+ if (ret)
+ goto out;
+
+ if (crashk_low_res.end) {
+ ret = crash_exclude_mem_range(cmem, crashk_low_res.start, crashk_low_res.end);
+ if (ret)
+ goto out;
+ }
- if (!ret)
- ret = crash_prepare_elf64_headers(cmem, true, addr, sz);
+ ret = crash_prepare_elf64_headers(cmem, true, addr, sz);
+out:
kfree(cmem);
return ret;
}
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 6c653a2c7cff052..a5d43feac0d7d96 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -71,6 +71,30 @@ phys_addr_t arm64_dma_phys_limit __ro_after_init;
#define CRASH_ADDR_LOW_MAX arm64_dma_phys_limit
#define CRASH_ADDR_HIGH_MAX MEMBLOCK_ALLOC_ACCESSIBLE
+static int __init reserve_crashkernel_low(unsigned long long low_size)
+{
+ unsigned long long low_base;
+
+ /* passed with crashkernel=0,low ? */
+ if (!low_size)
+ return 0;
+
+ low_base = memblock_phys_alloc_range(low_size, CRASH_ALIGN, 0, CRASH_ADDR_LOW_MAX);
+ if (!low_base) {
+ pr_err("cannot allocate crashkernel low memory (size:0x%llx).\n", low_size);
+ return -ENOMEM;
+ }
+
+ pr_info("crashkernel low memory reserved: 0x%llx - 0x%llx (%lld MB)\n",
+ low_base, low_base + low_size, low_size >> 20);
+
+ crashk_low_res.start = low_base;
+ crashk_low_res.end = low_base + low_size - 1;
+ insert_resource(&iomem_resource, &crashk_low_res);
+
+ return 0;
+}
+
/*
* reserve_crashkernel() - reserves memory for crash kernel
*
@@ -81,29 +105,62 @@ phys_addr_t arm64_dma_phys_limit __ro_after_init;
static void __init reserve_crashkernel(void)
{
unsigned long long crash_base, crash_size;
+ unsigned long long crash_low_size = SZ_256M;
unsigned long long crash_max = CRASH_ADDR_LOW_MAX;
int ret;
+ bool fixed_base;
+ char *cmdline = boot_command_line;
- ret = parse_crashkernel(boot_command_line, memblock_phys_mem_size(),
+ /* crashkernel=X[@offset] */
+ ret = parse_crashkernel(cmdline, memblock_phys_mem_size(),
&crash_size, &crash_base);
- /* no crashkernel= or invalid value specified */
- if (ret || !crash_size)
- return;
+ if (ret || !crash_size) {
+ unsigned long long low_size;
+ /* crashkernel=X,high */
+ ret = parse_crashkernel_high(cmdline, 0, &crash_size, &crash_base);
+ if (ret || !crash_size)
+ return;
+
+ /* crashkernel=X,low */
+ ret = parse_crashkernel_low(cmdline, 0, &low_size, &crash_base);
+ if (!ret)
+ crash_low_size = low_size;
+
+ crash_max = CRASH_ADDR_HIGH_MAX;
+ }
+
+ fixed_base = !!crash_base;
crash_size = PAGE_ALIGN(crash_size);
/* User specifies base address explicitly. */
if (crash_base)
crash_max = crash_base + crash_size;
+retry:
crash_base = memblock_phys_alloc_range(crash_size, CRASH_ALIGN,
crash_base, crash_max);
if (!crash_base) {
+ /*
+ * Attempt to fully allocate low memory failed, fall back
+ * to high memory, the minimum required low memory will be
+ * reserved later.
+ */
+ if (!fixed_base && (crash_max == CRASH_ADDR_LOW_MAX)) {
+ crash_max = CRASH_ADDR_HIGH_MAX;
+ goto retry;
+ }
+
pr_warn("cannot allocate crashkernel (size:0x%llx)\n",
crash_size);
return;
}
+ if (crash_base >= SZ_4G && reserve_crashkernel_low(crash_low_size)) {
+ memblock_phys_free(crash_base, crash_size);
+ return;
+ }
+
pr_info("crashkernel reserved: 0x%016llx - 0x%016llx (%lld MB)\n",
crash_base, crash_base + crash_size, crash_size >> 20);
@@ -112,6 +169,9 @@ static void __init reserve_crashkernel(void)
* map. Inform kmemleak so that it won't try to access it.
*/
kmemleak_ignore_phys(crash_base);
+ if (crashk_low_res.end)
+ kmemleak_ignore_phys(crashk_low_res.start);
+
crashk_res.start = crash_base;
crashk_res.end = crash_base + crash_size - 1;
insert_resource(&iomem_resource, &crashk_res);
--
2.25.1
^ permalink raw reply related
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