* [PATCH v20 3/5] arm64: kdump: reimplement crashkernel=X
From: Zhen Lei @ 2022-01-24 8:47 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Borislav Petkov, x86,
H . Peter Anvin, linux-kernel, Dave Young, Baoquan He,
Vivek Goyal, Eric Biederman, kexec, Catalin Marinas, Will Deacon,
linux-arm-kernel, Rob Herring, Frank Rowand, devicetree,
Jonathan Corbet, linux-doc
Cc: Zhen Lei, Randy Dunlap, Feng Zhou, Kefeng Wang, Chen Zhou,
John Donnelly, Dave Kleikamp
In-Reply-To: <20220124084708.683-1-thunder.leizhen@huawei.com>
From: Chen Zhou <chenzhou10@huawei.com>
There are following issues in arm64 kdump:
1. We use crashkernel=X to reserve crashkernel below 4G, which
will fail when there is no enough low memory.
2. If reserving crashkernel above 4G, in this case, crash dump
kernel will boot failure because there is no low memory available
for allocation.
To solve these issues, change the behavior of crashkernel=X and
introduce crashkernel=X,[high,low]. crashkernel=X tries low allocation
in DMA zone, and fall back to high allocation if it fails.
We can also use "crashkernel=X,high" to select a region above DMA zone,
which also tries to allocate at least 256M in DMA zone automatically.
"crashkernel=Y,low" can be used to allocate specified size low memory.
Signed-off-by: Chen Zhou <chenzhou10@huawei.com>
Co-developed-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
arch/arm64/kernel/machine_kexec.c | 9 +++-
arch/arm64/kernel/machine_kexec_file.c | 12 ++++-
arch/arm64/mm/init.c | 68 ++++++++++++++++++++++++--
3 files changed, 81 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/kernel/machine_kexec.c b/arch/arm64/kernel/machine_kexec.c
index e16b248699d5c3c..19c2d487cb08feb 100644
--- a/arch/arm64/kernel/machine_kexec.c
+++ b/arch/arm64/kernel/machine_kexec.c
@@ -329,8 +329,13 @@ bool crash_is_nosave(unsigned long pfn)
/* in reserved memory? */
addr = __pfn_to_phys(pfn);
- if ((addr < crashk_res.start) || (crashk_res.end < addr))
- return false;
+ if ((addr < crashk_res.start) || (crashk_res.end < addr)) {
+ if (!crashk_low_res.end)
+ return false;
+
+ if ((addr < crashk_low_res.start) || (crashk_low_res.end < addr))
+ return false;
+ }
if (!kexec_crash_image)
return true;
diff --git a/arch/arm64/kernel/machine_kexec_file.c b/arch/arm64/kernel/machine_kexec_file.c
index 59c648d51848886..889951291cc0f9c 100644
--- a/arch/arm64/kernel/machine_kexec_file.c
+++ b/arch/arm64/kernel/machine_kexec_file.c
@@ -65,10 +65,18 @@ static int prepare_elf_headers(void **addr, unsigned long *sz)
/* Exclude crashkernel region */
ret = crash_exclude_mem_range(cmem, crashk_res.start, crashk_res.end);
+ if (ret)
+ goto out;
+
+ if (crashk_low_res.end) {
+ ret = crash_exclude_mem_range(cmem, crashk_low_res.start, crashk_low_res.end);
+ if (ret)
+ goto out;
+ }
- if (!ret)
- ret = crash_prepare_elf64_headers(cmem, true, addr, sz);
+ ret = crash_prepare_elf64_headers(cmem, true, addr, sz);
+out:
kfree(cmem);
return ret;
}
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 6c653a2c7cff052..a5d43feac0d7d96 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -71,6 +71,30 @@ phys_addr_t arm64_dma_phys_limit __ro_after_init;
#define CRASH_ADDR_LOW_MAX arm64_dma_phys_limit
#define CRASH_ADDR_HIGH_MAX MEMBLOCK_ALLOC_ACCESSIBLE
+static int __init reserve_crashkernel_low(unsigned long long low_size)
+{
+ unsigned long long low_base;
+
+ /* passed with crashkernel=0,low ? */
+ if (!low_size)
+ return 0;
+
+ low_base = memblock_phys_alloc_range(low_size, CRASH_ALIGN, 0, CRASH_ADDR_LOW_MAX);
+ if (!low_base) {
+ pr_err("cannot allocate crashkernel low memory (size:0x%llx).\n", low_size);
+ return -ENOMEM;
+ }
+
+ pr_info("crashkernel low memory reserved: 0x%llx - 0x%llx (%lld MB)\n",
+ low_base, low_base + low_size, low_size >> 20);
+
+ crashk_low_res.start = low_base;
+ crashk_low_res.end = low_base + low_size - 1;
+ insert_resource(&iomem_resource, &crashk_low_res);
+
+ return 0;
+}
+
/*
* reserve_crashkernel() - reserves memory for crash kernel
*
@@ -81,29 +105,62 @@ phys_addr_t arm64_dma_phys_limit __ro_after_init;
static void __init reserve_crashkernel(void)
{
unsigned long long crash_base, crash_size;
+ unsigned long long crash_low_size = SZ_256M;
unsigned long long crash_max = CRASH_ADDR_LOW_MAX;
int ret;
+ bool fixed_base;
+ char *cmdline = boot_command_line;
- ret = parse_crashkernel(boot_command_line, memblock_phys_mem_size(),
+ /* crashkernel=X[@offset] */
+ ret = parse_crashkernel(cmdline, memblock_phys_mem_size(),
&crash_size, &crash_base);
- /* no crashkernel= or invalid value specified */
- if (ret || !crash_size)
- return;
+ if (ret || !crash_size) {
+ unsigned long long low_size;
+ /* crashkernel=X,high */
+ ret = parse_crashkernel_high(cmdline, 0, &crash_size, &crash_base);
+ if (ret || !crash_size)
+ return;
+
+ /* crashkernel=X,low */
+ ret = parse_crashkernel_low(cmdline, 0, &low_size, &crash_base);
+ if (!ret)
+ crash_low_size = low_size;
+
+ crash_max = CRASH_ADDR_HIGH_MAX;
+ }
+
+ fixed_base = !!crash_base;
crash_size = PAGE_ALIGN(crash_size);
/* User specifies base address explicitly. */
if (crash_base)
crash_max = crash_base + crash_size;
+retry:
crash_base = memblock_phys_alloc_range(crash_size, CRASH_ALIGN,
crash_base, crash_max);
if (!crash_base) {
+ /*
+ * Attempt to fully allocate low memory failed, fall back
+ * to high memory, the minimum required low memory will be
+ * reserved later.
+ */
+ if (!fixed_base && (crash_max == CRASH_ADDR_LOW_MAX)) {
+ crash_max = CRASH_ADDR_HIGH_MAX;
+ goto retry;
+ }
+
pr_warn("cannot allocate crashkernel (size:0x%llx)\n",
crash_size);
return;
}
+ if (crash_base >= SZ_4G && reserve_crashkernel_low(crash_low_size)) {
+ memblock_phys_free(crash_base, crash_size);
+ return;
+ }
+
pr_info("crashkernel reserved: 0x%016llx - 0x%016llx (%lld MB)\n",
crash_base, crash_base + crash_size, crash_size >> 20);
@@ -112,6 +169,9 @@ static void __init reserve_crashkernel(void)
* map. Inform kmemleak so that it won't try to access it.
*/
kmemleak_ignore_phys(crash_base);
+ if (crashk_low_res.end)
+ kmemleak_ignore_phys(crashk_low_res.start);
+
crashk_res.start = crash_base;
crashk_res.end = crash_base + crash_size - 1;
insert_resource(&iomem_resource, &crashk_res);
--
2.25.1
^ permalink raw reply related
* [PATCH v20 4/5] of: fdt: Add memory for devices by DT property "linux,usable-memory-range"
From: Zhen Lei @ 2022-01-24 8:47 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Borislav Petkov, x86,
H . Peter Anvin, linux-kernel, Dave Young, Baoquan He,
Vivek Goyal, Eric Biederman, kexec, Catalin Marinas, Will Deacon,
linux-arm-kernel, Rob Herring, Frank Rowand, devicetree,
Jonathan Corbet, linux-doc
Cc: Zhen Lei, Randy Dunlap, Feng Zhou, Kefeng Wang, Chen Zhou,
John Donnelly, Dave Kleikamp
In-Reply-To: <20220124084708.683-1-thunder.leizhen@huawei.com>
From: Chen Zhou <chenzhou10@huawei.com>
When reserving crashkernel in high memory, some low memory is reserved
for crash dump kernel devices and never mapped by the first kernel.
This memory range is advertised to crash dump kernel via DT property
under /chosen,
linux,usable-memory-range = <BASE1 SIZE1 [BASE2 SIZE2]>
We reused the DT property linux,usable-memory-range and made the low
memory region as the second range "BASE2 SIZE2", which keeps compatibility
with existing user-space and older kdump kernels.
Crash dump kernel reads this property at boot time and call memblock_add()
to add the low memory region after memblock_cap_memory_range() has been
called.
Signed-off-by: Chen Zhou <chenzhou10@huawei.com>
Co-developed-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Tested-by: Dave Kleikamp <dave.kleikamp@oracle.com>
---
drivers/of/fdt.c | 33 +++++++++++++++++++++++----------
1 file changed, 23 insertions(+), 10 deletions(-)
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index ad85ff6474ff139..df4b9d2418a13d4 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -973,16 +973,24 @@ static void __init early_init_dt_check_for_elfcorehdr(unsigned long node)
static unsigned long chosen_node_offset = -FDT_ERR_NOTFOUND;
+/*
+ * The main usage of linux,usable-memory-range is for crash dump kernel.
+ * Originally, the number of usable-memory regions is one. Now there may
+ * be two regions, low region and high region.
+ * To make compatibility with existing user-space and older kdump, the low
+ * region is always the last range of linux,usable-memory-range if exist.
+ */
+#define MAX_USABLE_RANGES 2
+
/**
* early_init_dt_check_for_usable_mem_range - Decode usable memory range
* location from flat tree
*/
void __init early_init_dt_check_for_usable_mem_range(void)
{
- const __be32 *prop;
- int len;
- phys_addr_t cap_mem_addr;
- phys_addr_t cap_mem_size;
+ struct memblock_region rgn[MAX_USABLE_RANGES] = {0};
+ const __be32 *prop, *endp;
+ int len, i;
unsigned long node = chosen_node_offset;
if ((long)node < 0)
@@ -991,16 +999,21 @@ void __init early_init_dt_check_for_usable_mem_range(void)
pr_debug("Looking for usable-memory-range property... ");
prop = of_get_flat_dt_prop(node, "linux,usable-memory-range", &len);
- if (!prop || (len < (dt_root_addr_cells + dt_root_size_cells)))
+ if (!prop || (len % (dt_root_addr_cells + dt_root_size_cells)))
return;
- cap_mem_addr = dt_mem_next_cell(dt_root_addr_cells, &prop);
- cap_mem_size = dt_mem_next_cell(dt_root_size_cells, &prop);
+ endp = prop + (len / sizeof(__be32));
+ for (i = 0; i < MAX_USABLE_RANGES && prop < endp; i++) {
+ rgn[i].base = dt_mem_next_cell(dt_root_addr_cells, &prop);
+ rgn[i].size = dt_mem_next_cell(dt_root_size_cells, &prop);
- pr_debug("cap_mem_start=%pa cap_mem_size=%pa\n", &cap_mem_addr,
- &cap_mem_size);
+ pr_debug("cap_mem_regions[%d]: base=%pa, size=%pa\n",
+ i, &rgn[i].base, &rgn[i].size);
+ }
- memblock_cap_memory_range(cap_mem_addr, cap_mem_size);
+ memblock_cap_memory_range(rgn[0].base, rgn[0].size);
+ for (i = 1; i < MAX_USABLE_RANGES && rgn[i].size; i++)
+ memblock_add(rgn[i].base, rgn[i].size);
}
#ifdef CONFIG_SERIAL_EARLYCON
--
2.25.1
^ permalink raw reply related
* [PATCH v20 5/5] kdump: update Documentation about crashkernel
From: Zhen Lei @ 2022-01-24 8:47 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Borislav Petkov, x86,
H . Peter Anvin, linux-kernel, Dave Young, Baoquan He,
Vivek Goyal, Eric Biederman, kexec, Catalin Marinas, Will Deacon,
linux-arm-kernel, Rob Herring, Frank Rowand, devicetree,
Jonathan Corbet, linux-doc
Cc: Zhen Lei, Randy Dunlap, Feng Zhou, Kefeng Wang, Chen Zhou,
John Donnelly, Dave Kleikamp
In-Reply-To: <20220124084708.683-1-thunder.leizhen@huawei.com>
From: Chen Zhou <chenzhou10@huawei.com>
For arm64, the behavior of crashkernel=X has been changed, which
tries low allocation in DMA zone and fall back to high allocation
if it fails.
We can also use "crashkernel=X,high" to select a high region above
DMA zone, which also tries to allocate at least 256M low memory in
DMA zone automatically and "crashkernel=Y,low" can be used to allocate
specified size low memory.
So update the Documentation.
Signed-off-by: Chen Zhou <chenzhou10@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
Documentation/admin-guide/kdump/kdump.rst | 11 +++++++++--
Documentation/admin-guide/kernel-parameters.txt | 11 +++++++++--
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/Documentation/admin-guide/kdump/kdump.rst b/Documentation/admin-guide/kdump/kdump.rst
index cb30ca3df27c9b2..d4c287044be0c70 100644
--- a/Documentation/admin-guide/kdump/kdump.rst
+++ b/Documentation/admin-guide/kdump/kdump.rst
@@ -361,8 +361,15 @@ Boot into System Kernel
kernel will automatically locate the crash kernel image within the
first 512MB of RAM if X is not given.
- On arm64, use "crashkernel=Y[@X]". Note that the start address of
- the kernel, X if explicitly specified, must be aligned to 2MiB (0x200000).
+ On arm64, use "crashkernel=X" to try low allocation in DMA zone and
+ fall back to high allocation if it fails.
+ We can also use "crashkernel=X,high" to select a high region above
+ DMA zone, which also tries to allocate at least 256M low memory in
+ DMA zone automatically.
+ "crashkernel=Y,low" can be used to allocate specified size low memory.
+ Use "crashkernel=Y@X" if you really have to reserve memory from
+ specified start address X. Note that the start address of the kernel,
+ X if explicitly specified, must be aligned to 2MiB (0x200000).
Load the Dump-capture Kernel
============================
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index f5a27f067db9ed9..65780c2ca830be0 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -792,6 +792,9 @@
[KNL, X86-64] Select a region under 4G first, and
fall back to reserve region above 4G when '@offset'
hasn't been specified.
+ [KNL, ARM64] Try low allocation in DMA zone and fall back
+ to high allocation if it fails when '@offset' hasn't been
+ specified.
See Documentation/admin-guide/kdump/kdump.rst for further details.
crashkernel=range1:size1[,range2:size2,...][@offset]
@@ -808,6 +811,8 @@
Otherwise memory region will be allocated below 4G, if
available.
It will be ignored if crashkernel=X is specified.
+ [KNL, ARM64] range in high memory.
+ Allow kernel to allocate physical memory region from top.
crashkernel=size[KMG],low
[KNL, X86-64] range under 4G. When crashkernel=X,high
is passed, kernel could allocate physical memory region
@@ -816,13 +821,15 @@
requires at least 64M+32K low memory, also enough extra
low memory is needed to make sure DMA buffers for 32-bit
devices won't run out. Kernel would try to allocate at
- at least 256M below 4G automatically.
+ least 256M below 4G automatically.
This one let user to specify own low range under 4G
for second kernel instead.
0: to disable low allocation.
It will be ignored when crashkernel=X,high is not used
or memory reserved is below 4G.
-
+ [KNL, ARM64] range in low memory.
+ This one let user to specify a low range in DMA zone for
+ crash dump kernel.
cryptomgr.notests
[KNL] Disable crypto self-tests
--
2.25.1
^ permalink raw reply related
* Aw: Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Bananapi R2 Pro
From: Frank Wunderlich @ 2022-01-24 8:55 UTC (permalink / raw)
To: Sascha Hauer
Cc: Frank Wunderlich, linux-rockchip, Rob Herring, Heiko Stuebner,
Peter Geis, Johan Jonker, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <20220124083102.GW23490@pengutronix.de>
Hi
> Gesendet: Montag, 24. Januar 2022 um 09:31 Uhr
> Von: "Sascha Hauer" <sha@pengutronix.de>
> An: "Frank Wunderlich" <linux@fw-web.de>
> Cc: linux-rockchip@lists.infradead.org, "Frank Wunderlich" <frank-w@public-files.de>, "Rob Herring" <robh+dt@kernel.org>, "Heiko Stuebner" <heiko@sntech.de>, "Peter Geis" <pgwipeout@gmail.com>, "Johan Jonker" <jbx6244@gmail.com>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
> Betreff: Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Bananapi R2 Pro
>
> On Sun, Jan 23, 2022 at 02:51:16PM +0100, Frank Wunderlich wrote:
> > From: Frank Wunderlich <frank-w@public-files.de>
> >
> > This patch adds Devicetree for Bananapi R2 Pro based on RK3568.
> > Add uart/sd/emmc/i2c/rk809/tsadc nodes for basic function.
> > Gmac0 is directly connected to wan-port so usable without additional
> > driver.
> > On gmac1 there is a switch (rtl8367rb) connected which have not yet a
> > driver in mainline.
> >
> > Patch also prepares nodes for GPIO header.
> >
> > Co-developed-by: Peter Geis <pgwipeout@gmail.com>
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> > ---
> > +&gmac0 {
> > + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
> > + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
> > + clock_in_out = "input";
> > + phy-handle = <&rgmii_phy0>;
> > + phy-mode = "rgmii";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&gmac0_miim
> > + &gmac0_tx_bus2
> > + &gmac0_rx_bus2
> > + &gmac0_rgmii_clk
> > + &gmac0_rgmii_bus>;
> > +
> > + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
> > + snps,reset-active-low;
> > + /* Reset time is 20ms, 100ms for rtl8211f */
>
> Is this really a rtl8211f? I don't know and it could indeed be a
> rtl8211f, I'm just asking because the comment is copy pasted from
> the Quartz64 board.
i know thats a RTL8211 phy, but i see no additional letter on the chip, based on shematics it's a RTL8211F-CG
> > + snps,reset-delays-us = <0 20000 100000>;
> > +
> > +&mdio0 {
> > + rgmii_phy0: ethernet-phy@0 {
> > + compatible = "ethernet-phy-ieee802.3-c22";
> > + reg = <0x0>;
> > + };
>
> 0 is the broadcast address. I'm not sure if it's a good idea to use it.
> There should be another address the phy listens on.
took this from the 3568-EVB (like the most parts, as the board is mostly the same), and in linux it's the same and working. The switch have also phy-id 0 on mdio bus #1, are you sure this is invalid?
regards Frank
^ permalink raw reply
* Re: [PATCH v6 11/14] media: ti: Add CSI2RX support for J721E
From: Sakari Ailus @ 2022-01-24 9:00 UTC (permalink / raw)
To: Pratyush Yadav
Cc: Mauro Carvalho Chehab, Laurent Pinchart, Nikhil Devshatwar,
Tomi Valkeinen, Benoit Parrot, Maxime Ripard, Rob Herring,
Niklas Söderlund, devicetree, linux-kernel, linux-media
In-Reply-To: <20220121142904.4091481-12-p.yadav@ti.com>
Hi Pratyush,
On Fri, Jan 21, 2022 at 07:59:01PM +0530, Pratyush Yadav wrote:
> TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate
> capture over a CSI-2 bus.
>
> The Cadence CSI2RX IP acts as a bridge between the TI specific parts and
> the CSI-2 protocol parts. TI then has a wrapper on top of this bridge
> called the SHIM layer. It takes in data from stream 0, repacks it, and
> sends it to memory over PSI-L DMA.
>
> This driver acts as the "front end" to V4L2 client applications. It
> implements the required ioctls and buffer operations, passes the
> necessary calls on to the bridge, programs the SHIM layer, and performs
> DMA via the dmaengine API to finally return the data to a buffer
> supplied by the application.
>
> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
>
> ---
>
> (no changes since v5)
>
> Changes in v5:
> - Add dependency on PHY_CADENCE_DPHY_RX instead of PHY_CADENCE_DPHY
> since the Rx mode DPHY now has a separate driver.
> - Drop ti_csi2rx_validate_pipeline(). Pipeline validation should be done
> at media_pipeline_start().
> - Do not assign flags.
> - Fix error handling in ti_csi2rx_start_streaming(). Free up vb2 buffers
> when media_pipeline_start() fails.
>
> Changes in v4:
> - Acquire the media device's graph_mutex before starting the graph walk.
> - Call media_graph_walk_init() and media_graph_walk_cleanup() when
> starting and ending the graph walk respectively.
> - Reduce max frame height and width in enum_framesizes. Currently they
> are set to UINT_MAX but they must be a multiple of step_width, so they
> need to be rounded down. Also, these values are absurdly large which
> causes some userspace applications like gstreamer to trip up. While it
> is not generally right to change the kernel for an application bug, it
> is not such a big deal here. This change is replacing one set of
> absurdly large arbitrary values with another set of smaller but still
> absurdly large arbitrary values. Both limits are unlikely to be hit in
> practice.
>
> Changes in v3:
> - Move DMA related fields in struct ti_csi2rx_dma.
> - Protect DMA buffer queue with a spinlock to make sure the queue buffer
> and DMA callback don't race on it.
> - Track the current DMA state. It might go idle because of a lack of
> buffers. This state can be used to restart it if needed.
> - Do not include the current buffer in the pending queue. It is slightly
> better modelling than leaving it at the head of the pending queue.
> - Use the buffer as the callback argument, and add a reference to csi in it.
> - If queueing a buffer to DMA fails, the buffer gets leaked and DMA gets
> stalled with. Instead, report the error to vb2 and queue the next
> buffer in the pending queue.
> - DMA gets stalled if we run out of buffers since the callback is the
> only one that fires subsequent transfers and it is no longer being
> called. Check for that when queueing buffers and restart DMA if
> needed.
> - Do not put of node until we are done using the fwnode.
> - Set inital format to UYVY 640x480.
>
> Changes in v2:
> - Use dmaengine_get_dma_device() instead of directly accessing
> dma->device->dev.
> - Do not set dst_addr_width when configuring slave DMA.
> - Move to a separate subdir and rename to j721e-csi2rx.c
> - Convert compatible to ti,j721e-csi2rx.
> - Move to use Media Controller centric APIs.
> - Improve cleanup in probe when one of the steps fails.
> - Add colorspace to formats database.
> - Set hw_revision on media_device.
> - Move video device initialization to probe time instead of register time.
>
> MAINTAINERS | 6 +
> drivers/media/platform/Kconfig | 12 +
> drivers/media/platform/ti/Makefile | 1 +
> .../media/platform/ti/j721e-csi2rx/Makefile | 2 +
> .../platform/ti/j721e-csi2rx/j721e-csi2rx.c | 913 ++++++++++++++++++
> 5 files changed, 934 insertions(+)
> create mode 100644 drivers/media/platform/ti/j721e-csi2rx/Makefile
> create mode 100644 drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 3b8fa4e5047f..2a8ebf17462e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -19181,6 +19181,12 @@ S: Odd Fixes
> F: drivers/clk/ti/
> F: include/linux/clk/ti.h
>
> +TI J721E CSI2RX DRIVER
> +M: Pratyush Yadav <p.yadav@ti.com>
> +L: linux-media@vger.kernel.org
> +S: Supported
> +F: drivers/media/platform/ti/j721e-csi2rx/
> +
> TI DAVINCI MACHINE SUPPORT
> M: Sekhar Nori <nsekhar@ti.com>
> R: Bartosz Golaszewski <brgl@bgdev.pl>
> diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
> index 9fbdba0fd1e7..0fa58563d93b 100644
> --- a/drivers/media/platform/Kconfig
> +++ b/drivers/media/platform/Kconfig
> @@ -216,6 +216,18 @@ config VIDEO_RCAR_ISP
> To compile this driver as a module, choose M here: the
> module will be called rcar-isp.
>
> +config VIDEO_TI_J721E_CSI2RX
> + tristate "TI J721E CSI2RX wrapper layer driver"
> + depends on VIDEO_DEV && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
> + depends on MEDIA_SUPPORT && MEDIA_CONTROLLER
> + depends on PHY_CADENCE_DPHY_RX && VIDEO_CADENCE_CSI2RX
> + depends on ARCH_K3 || COMPILE_TEST
> + select VIDEOBUF2_DMA_CONTIG
> + select V4L2_FWNODE
> + help
> + Support for TI CSI2RX wrapper layer. This just enables the wrapper driver.
> + The Cadence CSI2RX bridge driver needs to be enabled separately.
> +
> endif # V4L_PLATFORM_DRIVERS
>
> menuconfig V4L_MEM2MEM_DRIVERS
> diff --git a/drivers/media/platform/ti/Makefile b/drivers/media/platform/ti/Makefile
> index bbc737ccbbea..17c9cfb74f66 100644
> --- a/drivers/media/platform/ti/Makefile
> +++ b/drivers/media/platform/ti/Makefile
> @@ -1,3 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0
> obj-y += cal/
> obj-y += vpe/
> +obj-y += j721e-csi2rx/
> diff --git a/drivers/media/platform/ti/j721e-csi2rx/Makefile b/drivers/media/platform/ti/j721e-csi2rx/Makefile
> new file mode 100644
> index 000000000000..377afc1d6280
> --- /dev/null
> +++ b/drivers/media/platform/ti/j721e-csi2rx/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +obj-$(CONFIG_VIDEO_TI_J721E_CSI2RX) += j721e-csi2rx.o
> diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c
> new file mode 100644
> index 000000000000..43f31f161f43
> --- /dev/null
> +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c
> @@ -0,0 +1,913 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * TI CSI2 RX driver.
> + *
> + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
> + *
> + * Author: Pratyush Yadav <p.yadav@ti.com>
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/dmaengine.h>
> +#include <linux/of_platform.h>
> +
> +#include <media/v4l2-device.h>
> +#include <media/v4l2-ioctl.h>
> +#include <media/videobuf2-dma-contig.h>
> +
> +#define TI_CSI2RX_MODULE_NAME "j721e-csi2rx"
> +
> +#define SHIM_CNTL 0x10
> +#define SHIM_CNTL_PIX_RST BIT(0)
> +
> +#define SHIM_DMACNTX 0x20
> +#define SHIM_DMACNTX_EN BIT(31)
> +#define SHIM_DMACNTX_YUV422 GENMASK(27, 26)
> +#define SHIM_DMACNTX_FMT GENMASK(5, 0)
> +#define SHIM_DMACNTX_UYVY 0
> +#define SHIM_DMACNTX_VYUY 1
> +#define SHIM_DMACNTX_YUYV 2
> +#define SHIM_DMACNTX_YVYU 3
> +
> +#define SHIM_PSI_CFG0 0x24
> +#define SHIM_PSI_CFG0_SRC_TAG GENMASK(15, 0)
> +#define SHIM_PSI_CFG0_DST_TAG GENMASK(31, 15)
> +
> +#define CSI_DF_YUV420 0x18
> +#define CSI_DF_YUV422 0x1e
> +#define CSI_DF_RGB444 0x20
> +#define CSI_DF_RGB888 0x24
> +
> +#define PSIL_WORD_SIZE_BYTES 16
> +/*
> + * There are no hard limits on the width or height. The DMA engine can handle
> + * all sizes. The max width and height are arbitrary numbers for this driver.
> + * Use 16M * 16M as the arbitrary limit. It is large enough that it is unlikely
> + * the limit will be hit in practice.
> + */
> +#define MAX_WIDTH_BYTES SZ_16M
> +#define MAX_HEIGHT_BYTES SZ_16M
> +
> +struct ti_csi2rx_fmt {
> + u32 fourcc; /* Four character code. */
> + u32 code; /* Mbus code. */
> + enum v4l2_colorspace colorspace;
> + u32 csi_df; /* CSI Data format. */
> + u8 bpp; /* Bits per pixel. */
> +};
> +
> +struct ti_csi2rx_buffer {
> + /* Common v4l2 buffer. Must be first. */
> + struct vb2_v4l2_buffer vb;
> + struct list_head list;
> + struct ti_csi2rx_dev *csi;
> +};
> +
> +enum ti_csi2rx_dma_state {
> + TI_CSI2RX_DMA_STOPPED, /* Streaming not started yet. */
> + TI_CSI2RX_DMA_IDLE, /* Streaming but no pending DMA operation. */
> + TI_CSI2RX_DMA_ACTIVE, /* Streaming and pending DMA operation. */
> +};
> +
> +struct ti_csi2rx_dma {
> + /* Protects all fields in this struct. */
> + spinlock_t lock;
> + struct dma_chan *chan;
> + /* Buffers queued to the driver, waiting to be processed by DMA. */
> + struct list_head queue;
> + enum ti_csi2rx_dma_state state;
> + /*
> + * Current buffer being processed by DMA. NULL if no buffer is being
> + * processed.
> + */
> + struct ti_csi2rx_buffer *curr;
> +};
> +
> +struct ti_csi2rx_dev {
> + struct device *dev;
> + void __iomem *shim;
> + struct v4l2_device v4l2_dev;
> + struct video_device vdev;
> + struct media_device mdev;
> + struct media_pipeline pipe;
> + struct media_pad pad;
> + struct v4l2_async_notifier notifier;
> + struct v4l2_subdev *subdev;
> + struct vb2_queue vidq;
> + struct mutex mutex; /* To serialize ioctls. */
> + struct v4l2_format v_fmt;
> + struct ti_csi2rx_dma dma;
> + u32 sequence;
> +};
> +
> +static const struct ti_csi2rx_fmt formats[] = {
> + {
> + .fourcc = V4L2_PIX_FMT_YUYV,
> + .code = MEDIA_BUS_FMT_YUYV8_2X8,
> + .colorspace = V4L2_COLORSPACE_SRGB,
> + .csi_df = CSI_DF_YUV422,
> + .bpp = 16,
> + }, {
> + .fourcc = V4L2_PIX_FMT_UYVY,
> + .code = MEDIA_BUS_FMT_UYVY8_2X8,
> + .colorspace = V4L2_COLORSPACE_SRGB,
> + .csi_df = CSI_DF_YUV422,
> + .bpp = 16,
> + }, {
> + .fourcc = V4L2_PIX_FMT_YVYU,
> + .code = MEDIA_BUS_FMT_YVYU8_2X8,
> + .colorspace = V4L2_COLORSPACE_SRGB,
> + .csi_df = CSI_DF_YUV422,
> + .bpp = 16,
> + }, {
> + .fourcc = V4L2_PIX_FMT_VYUY,
> + .code = MEDIA_BUS_FMT_VYUY8_2X8,
> + .colorspace = V4L2_COLORSPACE_SRGB,
> + .csi_df = CSI_DF_YUV422,
> + .bpp = 16,
> + },
> +
> + /* More formats can be supported but they are not listed for now. */
> +};
> +
> +static const unsigned int num_formats = ARRAY_SIZE(formats);
> +
> +/* Forward declaration needed by ti_csi2rx_dma_callback. */
> +static int ti_csi2rx_start_dma(struct ti_csi2rx_dev *csi,
> + struct ti_csi2rx_buffer *buf);
> +
> +static const struct ti_csi2rx_fmt *find_format_by_pix(u32 pixelformat)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < num_formats; i++) {
> + if (formats[i].fourcc == pixelformat)
> + return &formats[i];
> + }
> +
> + return NULL;
> +}
> +
> +static void ti_csi2rx_fill_fmt(const struct ti_csi2rx_fmt *csi_fmt,
> + struct v4l2_format *v4l2_fmt)
> +{
> + struct v4l2_pix_format *pix = &v4l2_fmt->fmt.pix;
> + u32 bpl;
> +
> + v4l2_fmt->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
> + pix->pixelformat = csi_fmt->fourcc;
> + pix->colorspace = csi_fmt->colorspace;
> + pix->sizeimage = pix->height * pix->width * (csi_fmt->bpp / 8);
This can overflow.
Width and height also aren't checked for the same limits (including step)
you have in enum_framesizes.
> +
> + bpl = (pix->width * ALIGN(csi_fmt->bpp, 8)) >> 3;
> + pix->bytesperline = ALIGN(bpl, 16);
> +}
> +
> +static int ti_csi2rx_querycap(struct file *file, void *priv,
> + struct v4l2_capability *cap)
> +{
> + struct ti_csi2rx_dev *csi = video_drvdata(file);
> +
> + strscpy(cap->driver, TI_CSI2RX_MODULE_NAME, sizeof(cap->driver));
> + strscpy(cap->card, TI_CSI2RX_MODULE_NAME, sizeof(cap->card));
> +
> + snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
> + dev_name(csi->dev));
> +
> + return 0;
> +}
> +
> +static int ti_csi2rx_enum_fmt_vid_cap(struct file *file, void *priv,
> + struct v4l2_fmtdesc *f)
> +{
> + if (f->index >= num_formats)
> + return -EINVAL;
> +
> + memset(f->reserved, 0, sizeof(f->reserved));
> + f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
> + f->pixelformat = formats[f->index].fourcc;
> +
> + return 0;
> +}
> +
> +static int ti_csi2rx_g_fmt_vid_cap(struct file *file, void *prov,
> + struct v4l2_format *f)
> +{
> + struct ti_csi2rx_dev *csi = video_drvdata(file);
> +
> + *f = csi->v_fmt;
> +
> + return 0;
> +}
> +
> +static int ti_csi2rx_try_fmt_vid_cap(struct file *file, void *priv,
> + struct v4l2_format *f)
> +{
> + const struct ti_csi2rx_fmt *fmt;
> +
> + /*
> + * Default to the first format if the requested pixel format code isn't
> + * supported.
> + */
> + fmt = find_format_by_pix(f->fmt.pix.pixelformat);
> + if (!fmt)
> + fmt = &formats[0];
> +
> + if (f->fmt.pix.field == V4L2_FIELD_ANY)
> + f->fmt.pix.field = V4L2_FIELD_NONE;
> +
> + if (f->fmt.pix.field != V4L2_FIELD_NONE)
> + return -EINVAL;
> +
> + ti_csi2rx_fill_fmt(fmt, f);
> +
> + return 0;
> +}
> +
> +static int ti_csi2rx_s_fmt_vid_cap(struct file *file, void *priv,
> + struct v4l2_format *f)
> +{
> + struct ti_csi2rx_dev *csi = video_drvdata(file);
> + struct vb2_queue *q = &csi->vidq;
> + int ret;
> +
> + if (vb2_is_busy(q))
> + return -EBUSY;
> +
> + ret = ti_csi2rx_try_fmt_vid_cap(file, priv, f);
> + if (ret < 0)
> + return ret;
> +
> + csi->v_fmt = *f;
> +
> + return 0;
> +}
> +
> +static int ti_csi2rx_enum_framesizes(struct file *file, void *fh,
> + struct v4l2_frmsizeenum *fsize)
> +{
> + const struct ti_csi2rx_fmt *fmt;
> + unsigned int pixels_in_word;
> + u8 bpp;
> +
> + fmt = find_format_by_pix(fsize->pixel_format);
> + if (!fmt)
> + return -EINVAL;
> +
> + bpp = ALIGN(fmt->bpp, 8);
> +
> + /*
> + * Number of pixels in one PSI-L word. The transfer happens in multiples
> + * of PSI-L word sizes.
> + */
> + pixels_in_word = PSIL_WORD_SIZE_BYTES * 8 / bpp;
> +
> + fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
> + fsize->stepwise.min_width = pixels_in_word;
> + fsize->stepwise.max_width = rounddown(MAX_WIDTH_BYTES, pixels_in_word);
> + fsize->stepwise.step_width = pixels_in_word;
> + fsize->stepwise.min_height = 1;
> + fsize->stepwise.max_height = MAX_HEIGHT_BYTES;
> + fsize->stepwise.step_height = 1;
> +
> + return 0;
> +}
> +
> +static const struct v4l2_ioctl_ops csi_ioctl_ops = {
> + .vidioc_querycap = ti_csi2rx_querycap,
> + .vidioc_enum_fmt_vid_cap = ti_csi2rx_enum_fmt_vid_cap,
> + .vidioc_try_fmt_vid_cap = ti_csi2rx_try_fmt_vid_cap,
> + .vidioc_g_fmt_vid_cap = ti_csi2rx_g_fmt_vid_cap,
> + .vidioc_s_fmt_vid_cap = ti_csi2rx_s_fmt_vid_cap,
> + .vidioc_enum_framesizes = ti_csi2rx_enum_framesizes,
> + .vidioc_reqbufs = vb2_ioctl_reqbufs,
> + .vidioc_create_bufs = vb2_ioctl_create_bufs,
> + .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
> + .vidioc_querybuf = vb2_ioctl_querybuf,
> + .vidioc_qbuf = vb2_ioctl_qbuf,
> + .vidioc_dqbuf = vb2_ioctl_dqbuf,
> + .vidioc_expbuf = vb2_ioctl_expbuf,
> + .vidioc_streamon = vb2_ioctl_streamon,
> + .vidioc_streamoff = vb2_ioctl_streamoff,
> +};
> +
> +static const struct v4l2_file_operations csi_fops = {
> + .owner = THIS_MODULE,
> + .open = v4l2_fh_open,
> + .release = vb2_fop_release,
> + .read = vb2_fop_read,
> + .poll = vb2_fop_poll,
> + .unlocked_ioctl = video_ioctl2,
> + .mmap = vb2_fop_mmap,
> +};
> +
> +static int ti_csi2rx_video_register(struct ti_csi2rx_dev *csi)
> +{
> + struct video_device *vdev = &csi->vdev;
> + int ret, src_pad;
> +
> + ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
> + if (ret)
> + return ret;
> +
> + src_pad = media_entity_get_fwnode_pad(&csi->subdev->entity,
> + csi->subdev->fwnode,
> + MEDIA_PAD_FL_SOURCE);
> + if (src_pad < 0) {
> + dev_err(csi->dev, "Couldn't find source pad for subdev\n");
> + return src_pad;
> + }
> +
> + ret = media_create_pad_link(&csi->subdev->entity, src_pad,
> + &vdev->entity, 0,
> + MEDIA_LNK_FL_IMMUTABLE |
> + MEDIA_LNK_FL_ENABLED);
> + if (ret) {
> + video_unregister_device(vdev);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int csi_async_notifier_bound(struct v4l2_async_notifier *notifier,
> + struct v4l2_subdev *subdev,
> + struct v4l2_async_subdev *asd)
> +{
> + struct ti_csi2rx_dev *csi = dev_get_drvdata(notifier->v4l2_dev->dev);
> +
> + csi->subdev = subdev;
> +
> + return 0;
> +}
> +
> +static int csi_async_notifier_complete(struct v4l2_async_notifier *notifier)
> +{
> + struct ti_csi2rx_dev *csi = dev_get_drvdata(notifier->v4l2_dev->dev);
> + int ret;
> +
> + ret = ti_csi2rx_video_register(csi);
> + if (ret)
> + return ret;
> +
> + return v4l2_device_register_subdev_nodes(&csi->v4l2_dev);
> +}
> +
> +static const struct v4l2_async_notifier_operations csi_async_notifier_ops = {
> + .bound = csi_async_notifier_bound,
> + .complete = csi_async_notifier_complete,
> +};
> +
> +static int ti_csi2rx_init_subdev(struct ti_csi2rx_dev *csi)
> +{
> + struct fwnode_handle *fwnode;
> + struct v4l2_async_subdev *asd;
> + struct device_node *node;
> + int ret;
> +
> + node = of_get_child_by_name(csi->dev->of_node, "csi-bridge");
> + if (!node)
> + return -EINVAL;
> +
> + fwnode = of_fwnode_handle(node);
> + if (!fwnode) {
> + of_node_put(node);
> + return -EINVAL;
> + }
> +
> + v4l2_async_nf_init(&csi->notifier);
> + csi->notifier.ops = &csi_async_notifier_ops;
> +
> + asd = v4l2_async_nf_add_fwnode(&csi->notifier, fwnode,
> + struct v4l2_async_subdev);
> + of_node_put(node);
> + if (IS_ERR(asd)) {
> + v4l2_async_nf_cleanup(&csi->notifier);
> + return PTR_ERR(asd);
> + }
> +
> + ret = v4l2_async_nf_register(&csi->v4l2_dev, &csi->notifier);
> + if (ret) {
> + v4l2_async_nf_cleanup(&csi->notifier);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static void ti_csi2rx_setup_shim(struct ti_csi2rx_dev *csi)
> +{
> + const struct ti_csi2rx_fmt *fmt;
> + unsigned int reg;
> +
> + fmt = find_format_by_pix(csi->v_fmt.fmt.pix.pixelformat);
> + if (!fmt) {
> + dev_err(csi->dev, "Unknown format\n");
> + return;
> + }
> +
> + /* De-assert the pixel interface reset. */
> + reg = SHIM_CNTL_PIX_RST;
> + writel(reg, csi->shim + SHIM_CNTL);
> +
> + reg = SHIM_DMACNTX_EN;
> + reg |= FIELD_PREP(SHIM_DMACNTX_FMT, fmt->csi_df);
> +
> + /*
> + * Using the values from the documentation gives incorrect ordering for
> + * the luma and chroma components. In practice, the "reverse" format
> + * gives the correct image. So for example, if the image is in UYVY, the
> + * reverse would be YVYU.
> + */
> + switch (fmt->fourcc) {
> + case V4L2_PIX_FMT_UYVY:
> + reg |= FIELD_PREP(SHIM_DMACNTX_YUV422,
> + SHIM_DMACNTX_YVYU);
> + break;
> + case V4L2_PIX_FMT_VYUY:
> + reg |= FIELD_PREP(SHIM_DMACNTX_YUV422,
> + SHIM_DMACNTX_YUYV);
> + break;
> + case V4L2_PIX_FMT_YUYV:
> + reg |= FIELD_PREP(SHIM_DMACNTX_YUV422,
> + SHIM_DMACNTX_VYUY);
> + break;
> + case V4L2_PIX_FMT_YVYU:
> + reg |= FIELD_PREP(SHIM_DMACNTX_YUV422,
> + SHIM_DMACNTX_UYVY);
> + break;
> + default:
> + /* Ignore if not YUV 4:2:2 */
> + break;
> + }
> +
> + writel(reg, csi->shim + SHIM_DMACNTX);
> +
> + reg = FIELD_PREP(SHIM_PSI_CFG0_SRC_TAG, 0) |
> + FIELD_PREP(SHIM_PSI_CFG0_DST_TAG, 1);
> + writel(reg, csi->shim + SHIM_PSI_CFG0);
> +}
> +
> +static void ti_csi2rx_dma_callback(void *param)
> +{
> + struct ti_csi2rx_buffer *buf = param;
> + struct ti_csi2rx_dev *csi = buf->csi;
> + struct ti_csi2rx_dma *dma = &csi->dma;
> + unsigned long flags = 0;
> +
> + buf->vb.vb2_buf.timestamp = ktime_get_ns();
> + buf->vb.sequence = csi->sequence++;
> +
> + spin_lock_irqsave(&dma->lock, flags);
> +
> + WARN_ON(dma->curr != buf);
> + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
> +
> + /* If there are more buffers to process then start their transfer. */
> + dma->curr = NULL;
> + while (!list_empty(&dma->queue)) {
> + buf = list_entry(dma->queue.next, struct ti_csi2rx_buffer, list);
> + list_del(&buf->list);
> +
> + if (ti_csi2rx_start_dma(csi, buf)) {
> + dev_err(csi->dev, "Failed to queue the next buffer for DMA\n");
> + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
> + } else {
> + dma->curr = buf;
> + break;
> + }
> + }
> +
> + if (!dma->curr)
> + dma->state = TI_CSI2RX_DMA_IDLE;
> +
> + spin_unlock_irqrestore(&dma->lock, flags);
> +}
> +
> +static int ti_csi2rx_start_dma(struct ti_csi2rx_dev *csi,
> + struct ti_csi2rx_buffer *buf)
> +{
> + unsigned long addr;
> + struct dma_async_tx_descriptor *desc;
> + size_t len = csi->v_fmt.fmt.pix.sizeimage;
> + dma_cookie_t cookie;
> + int ret = 0;
> +
> + addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
> + desc = dmaengine_prep_slave_single(csi->dma.chan, addr, len,
> + DMA_DEV_TO_MEM,
> + DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
> + if (!desc)
> + return -EIO;
> +
> + desc->callback = ti_csi2rx_dma_callback;
> + desc->callback_param = buf;
> +
> + cookie = dmaengine_submit(desc);
> + ret = dma_submit_error(cookie);
> + if (ret)
> + return ret;
> +
> + dma_async_issue_pending(csi->dma.chan);
> +
> + return 0;
> +}
> +
> +static int ti_csi2rx_queue_setup(struct vb2_queue *q, unsigned int *nbuffers,
> + unsigned int *nplanes, unsigned int sizes[],
> + struct device *alloc_devs[])
> +{
> + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(q);
> + unsigned int size = csi->v_fmt.fmt.pix.sizeimage;
> +
> + if (*nplanes) {
> + if (sizes[0] < size)
> + return -EINVAL;
> + size = sizes[0];
> + }
> +
> + *nplanes = 1;
> + sizes[0] = size;
> +
> + return 0;
> +}
> +
> +static int ti_csi2rx_buffer_prepare(struct vb2_buffer *vb)
> +{
> + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vb->vb2_queue);
> + unsigned long size = csi->v_fmt.fmt.pix.sizeimage;
> +
> + if (vb2_plane_size(vb, 0) < size) {
> + dev_err(csi->dev, "Data will not fit into plane\n");
> + return -EINVAL;
> + }
> +
> + vb2_set_plane_payload(vb, 0, size);
> + return 0;
> +}
> +
> +static void ti_csi2rx_buffer_queue(struct vb2_buffer *vb)
> +{
> + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vb->vb2_queue);
> + struct ti_csi2rx_buffer *buf;
> + struct ti_csi2rx_dma *dma = &csi->dma;
> + unsigned long flags = 0;
> + int ret;
> +
> + buf = container_of(vb, struct ti_csi2rx_buffer, vb.vb2_buf);
> + buf->csi = csi;
> +
> + spin_lock_irqsave(&dma->lock, flags);
> + /*
> + * Usually the DMA callback takes care of queueing the pending buffers.
> + * But if DMA has stalled due to lack of buffers, restart it now.
> + */
> + if (dma->state == TI_CSI2RX_DMA_IDLE) {
> + ret = ti_csi2rx_start_dma(csi, buf);
> + if (ret) {
> + dev_err(csi->dev, "Failed to start DMA: %d\n", ret);
> + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
> + goto unlock;
> + }
> +
> + dma->curr = buf;
> + dma->state = TI_CSI2RX_DMA_ACTIVE;
> + } else {
> + list_add_tail(&buf->list, &dma->queue);
> + }
> +
> +unlock:
> + spin_unlock_irqrestore(&dma->lock, flags);
> +}
> +
> +static int ti_csi2rx_start_streaming(struct vb2_queue *vq, unsigned int count)
> +{
> + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vq);
> + struct ti_csi2rx_dma *dma = &csi->dma;
> + struct ti_csi2rx_buffer *buf, *tmp;
> + unsigned long flags;
> + int ret = 0;
> +
> + spin_lock_irqsave(&dma->lock, flags);
> + if (list_empty(&dma->queue))
> + ret = -EIO;
> + spin_unlock_irqrestore(&dma->lock, flags);
> + if (ret)
> + return ret;
> +
> + ret = media_pipeline_start(&csi->vdev.entity, &csi->pipe);
> + if (ret)
> + goto err;
> +
> + ti_csi2rx_setup_shim(csi);
> +
> + ret = v4l2_subdev_call(csi->subdev, video, s_stream, 1);
> + if (ret)
> + goto err_pipeline;
> +
> + csi->sequence = 0;
> +
> + spin_lock_irqsave(&dma->lock, flags);
> + buf = list_entry(dma->queue.next, struct ti_csi2rx_buffer, list);
> + list_del(&buf->list);
> + dma->state = TI_CSI2RX_DMA_ACTIVE;
> +
> + ret = ti_csi2rx_start_dma(csi, buf);
> + if (ret) {
> + dev_err(csi->dev, "Failed to start DMA: %d\n", ret);
> + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
> + spin_unlock_irqrestore(&dma->lock, flags);
> + goto err_stream;
> + }
> +
> + dma->curr = buf;
> + spin_unlock_irqrestore(&dma->lock, flags);
> +
> + return 0;
> +
> +err_stream:
> + v4l2_subdev_call(csi->subdev, video, s_stream, 0);
> +err_pipeline:
> + media_pipeline_stop(&csi->vdev.entity);
> +err:
> + spin_lock_irqsave(&dma->lock, flags);
> + list_for_each_entry_safe(buf, tmp, &dma->queue, list) {
> + list_del(&buf->list);
> + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
> + }
> + csi->dma.state = TI_CSI2RX_DMA_STOPPED;
> + spin_unlock_irqrestore(&dma->lock, flags);
> +
> + return ret;
> +}
> +
> +static void ti_csi2rx_stop_streaming(struct vb2_queue *vq)
> +{
> + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vq);
> + struct ti_csi2rx_buffer *buf = NULL, *tmp;
> + struct ti_csi2rx_dma *dma = &csi->dma;
> + unsigned long flags = 0;
> + int ret;
> +
> + media_pipeline_stop(&csi->vdev.entity);
> +
> + ret = v4l2_subdev_call(csi->subdev, video, s_stream, 0);
> + if (ret)
> + dev_err(csi->dev, "Failed to stop subdev stream\n");
> +
> + writel(0, csi->shim + SHIM_CNTL);
> +
> + ret = dmaengine_terminate_sync(csi->dma.chan);
> + if (ret)
> + dev_err(csi->dev, "Failed to stop DMA\n");
> +
> + writel(0, csi->shim + SHIM_DMACNTX);
> +
> + spin_lock_irqsave(&dma->lock, flags);
> + list_for_each_entry_safe(buf, tmp, &csi->dma.queue, list) {
> + list_del(&buf->list);
> + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
> + }
> +
> + if (dma->curr)
> + vb2_buffer_done(&dma->curr->vb.vb2_buf, VB2_BUF_STATE_ERROR);
> +
> + dma->curr = NULL;
> + dma->state = TI_CSI2RX_DMA_STOPPED;
> + spin_unlock_irqrestore(&dma->lock, flags);
> +}
> +
> +static const struct vb2_ops csi_vb2_qops = {
> + .queue_setup = ti_csi2rx_queue_setup,
> + .buf_prepare = ti_csi2rx_buffer_prepare,
> + .buf_queue = ti_csi2rx_buffer_queue,
> + .start_streaming = ti_csi2rx_start_streaming,
> + .stop_streaming = ti_csi2rx_stop_streaming,
> + .wait_prepare = vb2_ops_wait_prepare,
> + .wait_finish = vb2_ops_wait_finish,
> +};
> +
> +static int ti_csi2rx_init_vb2q(struct ti_csi2rx_dev *csi)
> +{
> + struct vb2_queue *q = &csi->vidq;
> + int ret;
> +
> + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
> + q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
> + q->drv_priv = csi;
> + q->buf_struct_size = sizeof(struct ti_csi2rx_buffer);
> + q->ops = &csi_vb2_qops;
> + q->mem_ops = &vb2_dma_contig_memops;
> + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
> + q->dev = dmaengine_get_dma_device(csi->dma.chan);
> + q->lock = &csi->mutex;
> +
> + ret = vb2_queue_init(q);
> + if (ret)
> + return ret;
> +
> + csi->vdev.queue = q;
> +
> + return 0;
> +}
> +
> +static int ti_csi2rx_init_dma(struct ti_csi2rx_dev *csi)
> +{
> + struct dma_slave_config cfg;
> + int ret;
> +
> + INIT_LIST_HEAD(&csi->dma.queue);
> + spin_lock_init(&csi->dma.lock);
> +
> + csi->dma.state = TI_CSI2RX_DMA_STOPPED;
> +
> + csi->dma.chan = dma_request_chan(csi->dev, "rx0");
> + if (IS_ERR(csi->dma.chan))
> + return PTR_ERR(csi->dma.chan);
> +
> + memset(&cfg, 0, sizeof(cfg));
> +
> + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_16_BYTES;
You could do this when you declare cfg, and omit the memset.
> +
> + ret = dmaengine_slave_config(csi->dma.chan, &cfg);
> + if (ret)
dma_release_chan() ?
> + return ret;
> +
> + return 0;
> +}
> +
> +static int ti_csi2rx_v4l2_init(struct ti_csi2rx_dev *csi)
> +{
> + struct media_device *mdev = &csi->mdev;
> + struct video_device *vdev = &csi->vdev;
> + const struct ti_csi2rx_fmt *fmt;
> + struct v4l2_pix_format *pix_fmt = &csi->v_fmt.fmt.pix;
> + int ret;
> +
> + fmt = find_format_by_pix(V4L2_PIX_FMT_UYVY);
> + if (!fmt)
> + return -EINVAL;
> +
> + pix_fmt->width = 640;
> + pix_fmt->height = 480;
> +
> + ti_csi2rx_fill_fmt(fmt, &csi->v_fmt);
> +
> + mdev->dev = csi->dev;
> + mdev->hw_revision = 1;
> + strscpy(mdev->model, "TI-CSI2RX", sizeof(mdev->model));
> + snprintf(mdev->bus_info, sizeof(mdev->bus_info), "platform:%s",
> + dev_name(mdev->dev));
> +
> + media_device_init(mdev);
> +
> + strscpy(vdev->name, TI_CSI2RX_MODULE_NAME, sizeof(vdev->name));
> + vdev->v4l2_dev = &csi->v4l2_dev;
> + vdev->vfl_dir = VFL_DIR_RX;
> + vdev->fops = &csi_fops;
> + vdev->ioctl_ops = &csi_ioctl_ops;
> + vdev->release = video_device_release_empty;
> + vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE |
> + V4L2_CAP_STREAMING | V4L2_CAP_IO_MC;
> + vdev->lock = &csi->mutex;
> + video_set_drvdata(vdev, csi);
> +
> + csi->pad.flags = MEDIA_PAD_FL_SINK;
You'll need to provide entity ops for the vdev entity with at least
link_validate assigned. See e.g.
drivers/media/pci/intel/ipu3/ipu3-cio2-main.cdrivers/media/pci/intel/ipu3/ipu3-cio2-main.c
.
> + ret = media_entity_pads_init(&csi->vdev.entity, 1, &csi->pad);
> + if (ret)
> + return ret;
> +
> + csi->v4l2_dev.mdev = mdev;
> +
> + ret = v4l2_device_register(csi->dev, &csi->v4l2_dev);
> + if (ret)
> + return ret;
> +
> + ret = media_device_register(mdev);
> + if (ret) {
> + v4l2_device_unregister(&csi->v4l2_dev);
> + media_device_cleanup(mdev);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static void ti_csi2rx_cleanup_dma(struct ti_csi2rx_dev *csi)
> +{
> + dma_release_channel(csi->dma.chan);
> +}
> +
> +static void ti_csi2rx_cleanup_v4l2(struct ti_csi2rx_dev *csi)
> +{
> + media_device_unregister(&csi->mdev);
> + v4l2_device_unregister(&csi->v4l2_dev);
> + media_device_cleanup(&csi->mdev);
> +}
> +
> +static void ti_csi2rx_cleanup_subdev(struct ti_csi2rx_dev *csi)
> +{
> + v4l2_async_nf_unregister(&csi->notifier);
> + v4l2_async_nf_cleanup(&csi->notifier);
> +}
> +
> +static void ti_csi2rx_cleanup_vb2q(struct ti_csi2rx_dev *csi)
> +{
> + vb2_queue_release(&csi->vidq);
> +}
> +
> +static int ti_csi2rx_probe(struct platform_device *pdev)
> +{
> + struct ti_csi2rx_dev *csi;
> + struct resource *res;
> + int ret;
> +
> + csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL);
> + if (!csi)
> + return -ENOMEM;
> +
> + csi->dev = &pdev->dev;
> + platform_set_drvdata(pdev, csi);
> +
> + mutex_init(&csi->mutex);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + csi->shim = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(csi->shim))
Remember mutex_destroy(). I'd add one more label below.
> + return PTR_ERR(csi->shim);
> +
> + ret = ti_csi2rx_init_dma(csi);
> + if (ret)
> + return ret;
> +
> + ret = ti_csi2rx_v4l2_init(csi);
> + if (ret)
> + goto err_dma;
> +
> + ret = ti_csi2rx_init_vb2q(csi);
> + if (ret)
> + goto err_v4l2;
> +
> + ret = ti_csi2rx_init_subdev(csi);
> + if (ret)
> + goto err_vb2q;
> +
> + ret = of_platform_populate(csi->dev->of_node, NULL, NULL, csi->dev);
> + if (ret) {
> + dev_err(csi->dev, "Failed to create children: %d\n", ret);
> + goto err_subdev;
> + }
> +
> + return 0;
> +
> +err_subdev:
> + ti_csi2rx_cleanup_subdev(csi);
> +err_vb2q:
> + ti_csi2rx_cleanup_vb2q(csi);
> +err_v4l2:
> + ti_csi2rx_cleanup_v4l2(csi);
> +err_dma:
> + ti_csi2rx_cleanup_dma(csi);
> + return ret;
> +}
> +
> +static int ti_csi2rx_remove(struct platform_device *pdev)
> +{
> + struct ti_csi2rx_dev *csi = platform_get_drvdata(pdev);
> +
> + if (vb2_is_busy(&csi->vidq))
> + return -EBUSY;
Hmm. I don't think this is useful.
Unbinding MC-enabled devices is broken at the moment, so I think you can
safely ignore this bit in drivers.
> +
> + video_unregister_device(&csi->vdev);
> +
> + ti_csi2rx_cleanup_vb2q(csi);
> + ti_csi2rx_cleanup_subdev(csi);
> + ti_csi2rx_cleanup_v4l2(csi);
> + ti_csi2rx_cleanup_dma(csi);
mutex_destroy() here, too.
> +
> + return 0;
> +}
> +
> +static const struct of_device_id ti_csi2rx_of_match[] = {
> + { .compatible = "ti,j721e-csi2rx", },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, ti_csi2rx_of_match);
> +
> +static struct platform_driver ti_csi2rx_pdrv = {
> + .probe = ti_csi2rx_probe,
> + .remove = ti_csi2rx_remove,
> + .driver = {
> + .name = TI_CSI2RX_MODULE_NAME,
> + .of_match_table = ti_csi2rx_of_match,
> + },
> +};
> +
> +module_platform_driver(ti_csi2rx_pdrv);
> +
> +MODULE_DESCRIPTION("TI J721E CSI2 RX Driver");
> +MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>");
> +MODULE_LICENSE("GPL v2");
> +MODULE_VERSION("1.0");
--
Kind regards,
Sakari Ailus
^ permalink raw reply
* Napływ Klientów ze strony
From: Mikołaj Rudzik @ 2022-01-24 9:16 UTC (permalink / raw)
To: devicetree
Dzień dobry,
chciałbym poinformować Państwa o możliwości pozyskania nowych zleceń ze strony www.
Widzimy zainteresowanie potencjalnych Klientów Państwa firmą, dlatego chętnie pomożemy Państwu dotrzeć z ofertą do większego grona odbiorców poprzez efektywne metody pozycjonowania strony w Google.
Czy mógłbym liczyć na kontakt zwrotny?
Pozdrawiam
Mikołaj Rudzik
^ permalink raw reply
* [PATCH V1 1/6] iio: accel: sca3300: add define for temp channel for reuse.
From: LI Qingwu @ 2022-01-24 9:39 UTC (permalink / raw)
To: qing-wu.li, jic23, lars, robh+dt, tomas.melin, andy.shevchenko,
devicetree, linux-kernel
Cc: LI Qingwu
In-Reply-To: <20220124093912.2429190-1-Qing-wu.Li@leica-geosystems.com.cn>
Add define of SCA3300_TEMP_CHANNEL for reuse.
Signed-off-by: LI Qingwu <Qing-wu.Li@leica-geosystems.com.cn>
---
drivers/iio/accel/sca3300.c | 28 +++++++++++++++-------------
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/iio/accel/sca3300.c b/drivers/iio/accel/sca3300.c
index f7ef8ecfd34a..083ae2a47ad9 100644
--- a/drivers/iio/accel/sca3300.c
+++ b/drivers/iio/accel/sca3300.c
@@ -72,23 +72,25 @@ enum sca3300_scan_indexes {
}, \
}
+#define SCA3300_TEMP_CHANNEL(index, reg) { \
+ .type = IIO_TEMP, \
+ .address = reg, \
+ .scan_index = index, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
+ .scan_type = { \
+ .sign = 's', \
+ .realbits = 16, \
+ .storagebits = 16, \
+ .endianness = IIO_CPU, \
+ }, \
+}
+
static const struct iio_chan_spec sca3300_channels[] = {
SCA3300_ACCEL_CHANNEL(SCA3300_ACC_X, 0x1, X),
SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y),
SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z),
- {
- .type = IIO_TEMP,
- .address = 0x5,
- .scan_index = SCA3300_TEMP,
- .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
- .scan_type = {
- .sign = 's',
- .realbits = 16,
- .storagebits = 16,
- .endianness = IIO_CPU,
- },
- },
- IIO_CHAN_SOFT_TIMESTAMP(4),
+ SCA3300_TEMP_CHANNEL(SCA3300_TEMP, 0x05),
+ IIO_CHAN_SOFT_TIMESTAMP(4)
};
static const int sca3300_lp_freq[] = {70, 70, 70, 10};
--
2.25.1
^ permalink raw reply related
* [PATCH V1 0/6] i iio: accel: sca3300: add compitible for scl3300
From: LI Qingwu @ 2022-01-24 9:39 UTC (permalink / raw)
To: qing-wu.li, jic23, lars, robh+dt, tomas.melin, andy.shevchenko,
devicetree, linux-kernel
Cc: LI Qingwu
The current driver support sca3300 only.
Modifed for support SCL3300.
Verifed with SCL3300 on IMX8MM.
Splited the change for review.
LI Qingwu (6):
iio: accel: sca3300: add define for temp channel for reuse.
iio: accel: sca3300: Add interface for operation modes.
iio: accel: sca3300: modified to support multi chips
iio: accel: sca3300: Add support for SCL3300
iio: accel: sca3300: Add inclination channels.
dt-bindings: iio: accel: sca3300: Document murata,scl3300
.../bindings/iio/accel/murata,sca3300.yaml | 1 +
drivers/iio/accel/sca3300.c | 284 +++++++++++++++---
2 files changed, 238 insertions(+), 47 deletions(-)
--
2.25.1
^ permalink raw reply
* [PATCH V1 3/6] iio: accel: sca3300: modified to support multi chips
From: LI Qingwu @ 2022-01-24 9:39 UTC (permalink / raw)
To: qing-wu.li, jic23, lars, robh+dt, tomas.melin, andy.shevchenko,
devicetree, linux-kernel
Cc: LI Qingwu
In-Reply-To: <20220124093912.2429190-1-Qing-wu.Li@leica-geosystems.com.cn>
The drive support sca3300 only,there are some other similar chips,
for instance, SCL3300.
modified the driver to read the device id,
add the tables for the corresponding id to support multiple chips.
Signed-off-by: LI Qingwu <Qing-wu.Li@leica-geosystems.com.cn>
---
drivers/iio/accel/sca3300.c | 108 +++++++++++++++++++++++++-----------
1 file changed, 75 insertions(+), 33 deletions(-)
diff --git a/drivers/iio/accel/sca3300.c b/drivers/iio/accel/sca3300.c
index e26b3175b3c6..26e6fab88a8f 100644
--- a/drivers/iio/accel/sca3300.c
+++ b/drivers/iio/accel/sca3300.c
@@ -37,11 +37,11 @@
/* Device ID */
#define SCA3300_REG_WHOAMI 0x10
-#define SCA3300_WHOAMI_ID 0x51
/* Device return status and mask */
#define SCA3300_VALUE_RS_ERROR 0x3
#define SCA3300_MASK_RS_STATUS GENMASK(1, 0)
+
enum sca3300_op_mode_indexes {
OP_MOD_1 = 0,
OP_MOD_2,
@@ -75,6 +75,11 @@ static const struct iio_chan_spec_ext_info sca3300_ext_info[] = {
{ }
};
+enum sca3300_chip_type {
+ CHIP_SCA3300 = 0,
+ CHIP_CNT
+};
+
enum sca3300_scan_indexes {
SCA3300_ACC_X = 0,
SCA3300_ACC_Y,
@@ -126,8 +131,13 @@ static const struct iio_chan_spec sca3300_channels[] = {
IIO_CHAN_SOFT_TIMESTAMP(4)
};
-static const int sca3300_lp_freq[] = {70, 70, 70, 10};
-static const int sca3300_accel_scale[][2] = {{0, 370}, {0, 741}, {0, 185}, {0, 185}};
+static const int sca3300_lp_freq[CHIP_CNT][OP_MOD_CNT] = {
+ [CHIP_SCA3300] = {70, 70, 70, 10},
+};
+
+static const int sca3300_accel_scale[CHIP_CNT][OP_MOD_CNT][2] = {
+ [CHIP_SCA3300] = {{0, 370}, {0, 741}, {0, 185}, {0, 185}},
+};
static const unsigned long sca3300_scan_masks[] = {
BIT(SCA3300_ACC_X) | BIT(SCA3300_ACC_Y) | BIT(SCA3300_ACC_Z) |
@@ -135,6 +145,15 @@ static const unsigned long sca3300_scan_masks[] = {
0
};
+struct sca3300_chip_info {
+ enum sca3300_chip_type chip_type;
+ const char *name;
+ u8 chip_id;
+ const struct iio_chan_spec *channels;
+ int num_channels;
+ unsigned long scan_masks;
+};
+
/**
* struct sca3300_data - device data
* @spi: SPI device structure
@@ -150,8 +169,21 @@ struct sca3300_data {
s16 channels[4];
s64 ts __aligned(sizeof(s64));
} scan;
+ const struct sca3300_chip_info *chip_info;
u8 txbuf[4] ____cacheline_aligned;
u8 rxbuf[4];
+
+};
+
+static const struct sca3300_chip_info sca3300_chip_info_tbl[] = {
+ [CHIP_SCA3300] = {
+ .chip_type = CHIP_SCA3300,
+ .name = "sca3300",
+ .chip_id = 0x51,
+ .channels = sca3300_channels,
+ .num_channels = ARRAY_SIZE(sca3300_channels),
+ .scan_masks = sca3300_scan_masks,
+ },
};
DECLARE_CRC8_TABLE(sca3300_crc_table);
@@ -271,23 +303,20 @@ static int sca3300_write_raw(struct iio_dev *indio_dev,
switch (mask) {
case IIO_CHAN_INFO_SCALE:
- if (val)
- return -EINVAL;
-
- for (i = 0; i < ARRAY_SIZE(sca3300_accel_scale); i++) {
- if (val2 == sca3300_accel_scale[i][1])
+ for (i = 0; i < OP_MOD_CNT; i++) {
+ if ((val == sca3300_accel_scale[data->chip_info->chip_type][0]) &&
+ (val2 == sca3300_accel_scale[data->chip_info->chip_type][1]))
return sca3300_write_reg(data, SCA3300_REG_MODE, i);
}
return -EINVAL;
-
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
ret = sca3300_read_reg(data, SCA3300_REG_MODE, ®_val);
if (ret)
return ret;
/* freq. change is possible only for mode 3 and 4 */
- if (reg_val == 2 && val == sca3300_lp_freq[3])
+ if (reg_val == 2 && val == sca3300_lp_freq[data->chip_info->chip_type][3])
return sca3300_write_reg(data, SCA3300_REG_MODE, 3);
- if (reg_val == 3 && val == sca3300_lp_freq[2])
+ if (reg_val == 3 && val == sca3300_lp_freq[data->chip_info->chip_type][2])
return sca3300_write_reg(data, SCA3300_REG_MODE, 2);
return -EINVAL;
default:
@@ -313,14 +342,18 @@ static int sca3300_read_raw(struct iio_dev *indio_dev,
ret = sca3300_read_reg(data, SCA3300_REG_MODE, ®_val);
if (ret)
return ret;
- *val = 0;
- *val2 = sca3300_accel_scale[reg_val][1];
+ if (chan->type == IIO_ACCEL) {
+ *val = sca3300_accel_scale[data->chip_info->chip_type][reg_val][0];
+ *val2 = sca3300_accel_scale[data->chip_info->chip_type][reg_val][1];
+ } else {
+ return -EINVAL;
+ }
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
ret = sca3300_read_reg(data, SCA3300_REG_MODE, ®_val);
if (ret)
return ret;
- *val = sca3300_lp_freq[reg_val];
+ *val = sca3300_lp_freq[data->chip_info->chip_type][reg_val];
return IIO_VAL_INT;
default:
return -EINVAL;
@@ -364,6 +397,7 @@ static int sca3300_init(struct sca3300_data *sca_data,
{
int value = 0;
int ret;
+ int i = 0;
ret = sca3300_write_reg(sca_data, SCA3300_REG_MODE,
SCA3300_MODE_SW_RESET);
@@ -375,15 +409,22 @@ static int sca3300_init(struct sca3300_data *sca_data,
* Wait 15ms for settling of signal paths.
*/
usleep_range(16e3, 50e3);
-
- ret = sca3300_read_reg(sca_data, SCA3300_REG_WHOAMI, &value);
- if (ret)
- return ret;
-
- if (value != SCA3300_WHOAMI_ID) {
- dev_err(&sca_data->spi->dev,
- "device id not expected value, %d != %u\n",
- value, SCA3300_WHOAMI_ID);
+ for (i = 0; i < ARRAY_SIZE(sca3300_chip_info_tbl); i++) {
+ ret = sca3300_read_reg(sca_data, SCA3300_REG_WHOAMI, &value);
+ if (ret)
+ return ret;
+ if (sca3300_chip_info_tbl[i].chip_id == value) {
+ sca_data->chip_info = &sca3300_chip_info_tbl[i];
+ indio_dev->name = sca3300_chip_info_tbl[i].name;
+ indio_dev->channels = sca3300_chip_info_tbl[i].channels;
+ indio_dev->num_channels = sca3300_chip_info_tbl[i].num_channels;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->available_scan_masks = sca3300_chip_info_tbl[i].scan_masks;
+ break;
+ }
+ }
+ if (i == ARRAY_SIZE(sca3300_chip_info_tbl)) {
+ dev_err(&sca_data->spi->dev, "Invalid chip %x\n", value);
return -ENODEV;
}
return 0;
@@ -417,15 +458,21 @@ static int sca3300_read_avail(struct iio_dev *indio_dev,
const int **vals, int *type, int *length,
long mask)
{
+ struct sca3300_data *data = iio_priv(indio_dev);
+
switch (mask) {
case IIO_CHAN_INFO_SCALE:
- *vals = (const int *)sca3300_accel_scale;
- *length = ARRAY_SIZE(sca3300_accel_scale) * 2 - 2;
+ if (chan->type == IIO_ACCEL) {
+ *vals = (const int *)sca3300_accel_scale[data->chip_info->chip_type];
+ *length = ARRAY_SIZE(sca3300_accel_scale[data->chip_info->chip_type]) * 2;
+ } else {
+ return -EINVAL;
+ }
*type = IIO_VAL_INT_PLUS_MICRO;
return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
- *vals = &sca3300_lp_freq[2];
- *length = 2;
+ *vals = (const int *)sca3300_lp_freq[data->chip_info->chip_type];
+ *length = ARRAY_SIZE(sca3300_lp_freq[data->chip_info->chip_type]);
*type = IIO_VAL_INT;
return IIO_AVAIL_LIST;
default:
@@ -471,7 +518,6 @@ static int sca3300_probe(struct spi_device *spi)
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*sca_data));
if (!indio_dev)
return -ENOMEM;
-
sca_data = iio_priv(indio_dev);
mutex_init(&sca_data->lock);
sca_data->spi = spi;
@@ -479,11 +525,7 @@ static int sca3300_probe(struct spi_device *spi)
crc8_populate_msb(sca3300_crc_table, SCA3300_CRC8_POLYNOMIAL);
indio_dev->info = &sca3300_info;
- indio_dev->name = SCA3300_ALIAS;
- indio_dev->modes = INDIO_DIRECT_MODE;
- indio_dev->channels = sca3300_channels;
- indio_dev->num_channels = ARRAY_SIZE(sca3300_channels);
- indio_dev->available_scan_masks = sca3300_scan_masks;
+
ret = sca3300_init(sca_data, indio_dev);
if (ret) {
--
2.25.1
^ permalink raw reply related
* [PATCH V1 2/6] iio: accel: sca3300: Add interface for operation modes.
From: LI Qingwu @ 2022-01-24 9:39 UTC (permalink / raw)
To: qing-wu.li, jic23, lars, robh+dt, tomas.melin, andy.shevchenko,
devicetree, linux-kernel
Cc: LI Qingwu
In-Reply-To: <20220124093912.2429190-1-Qing-wu.Li@leica-geosystems.com.cn>
The acceleration scale and the frequency were set via operation modes,
the scal and frequency are both non-uniqueness,
this leads to logic confusion for setting scale.and.frequency.
it getting worse if add more different sensor types into the driver.
The commit add an interface for set and get the operation modes.
the following interfaces added:
in_accel_op_mode_available
in_op_mode
SCA3300 operation modes table:
| Mode | Full-scale | low pass filter frequency |
| ---- | ---------- | ------------------------- |
| 1 | ± 3 g | 70 Hz |
| 2 | ± 6 g | 70 Hz |
| 3 | ± 1.5 g | 70 Hz |
| 4 | ± 1.5 g | 10 Hz |
Signed-off-by: LI Qingwu <Qing-wu.Li@leica-geosystems.com.cn>
---
drivers/iio/accel/sca3300.c | 55 +++++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/drivers/iio/accel/sca3300.c b/drivers/iio/accel/sca3300.c
index 083ae2a47ad9..e26b3175b3c6 100644
--- a/drivers/iio/accel/sca3300.c
+++ b/drivers/iio/accel/sca3300.c
@@ -42,6 +42,38 @@
/* Device return status and mask */
#define SCA3300_VALUE_RS_ERROR 0x3
#define SCA3300_MASK_RS_STATUS GENMASK(1, 0)
+enum sca3300_op_mode_indexes {
+ OP_MOD_1 = 0,
+ OP_MOD_2,
+ OP_MOD_3,
+ OP_MOD_4,
+ OP_MOD_CNT
+};
+
+static const char * const sca3300_op_modes[] = {
+ [OP_MOD_1] = "1",
+ [OP_MOD_2] = "2",
+ [OP_MOD_3] = "3",
+ [OP_MOD_4] = "4"
+};
+
+static int sca3300_get_op_mode(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan);
+static int sca3300_set_op_mode(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan, unsigned int mode);
+
+static const struct iio_enum sca3300_op_mode_enum = {
+ .items = sca3300_op_modes,
+ .num_items = ARRAY_SIZE(sca3300_op_modes),
+ .get = sca3300_get_op_mode,
+ .set = sca3300_set_op_mode,
+};
+
+static const struct iio_chan_spec_ext_info sca3300_ext_info[] = {
+ IIO_ENUM("op_mode", IIO_SHARED_BY_DIR, &sca3300_op_mode_enum),
+ IIO_ENUM_AVAILABLE("op_mode", &sca3300_op_mode_enum),
+ { }
+};
enum sca3300_scan_indexes {
SCA3300_ACC_X = 0,
@@ -70,6 +102,7 @@ enum sca3300_scan_indexes {
.storagebits = 16, \
.endianness = IIO_CPU, \
}, \
+ .ext_info = sca3300_ext_info, \
}
#define SCA3300_TEMP_CHANNEL(index, reg) { \
@@ -400,6 +433,28 @@ static int sca3300_read_avail(struct iio_dev *indio_dev,
}
}
+static int sca3300_get_op_mode(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan)
+{
+ int mode;
+ int ret;
+ struct sca3300_data *data = iio_priv(indio_dev);
+
+ ret = sca3300_read_reg(data, SCA3300_REG_MODE, &mode);
+ if (ret)
+ return ret;
+ return mode;
+
+}
+
+static int sca3300_set_op_mode(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan, unsigned int mode)
+{
+ struct sca3300_data *data = iio_priv(indio_dev);
+
+ return sca3300_write_reg(data, SCA3300_REG_MODE, mode);
+}
+
static const struct iio_info sca3300_info = {
.read_raw = sca3300_read_raw,
.write_raw = sca3300_write_raw,
--
2.25.1
^ permalink raw reply related
* [PATCH V1 4/6] iio: accel: sca3300: Add support for SCL3300
From: LI Qingwu @ 2022-01-24 9:39 UTC (permalink / raw)
To: qing-wu.li, jic23, lars, robh+dt, tomas.melin, andy.shevchenko,
devicetree, linux-kernel
Cc: LI Qingwu
In-Reply-To: <20220124093912.2429190-1-Qing-wu.Li@leica-geosystems.com.cn>
Add support for Murata SCL3300, a 3-axis MEMS inclination.
same as SCA3300, it has accel and temperature output.
Datasheet link:
www.murata.com/en-us/products/sensor/inclinometer/overview/lineup/scl3300
Signed-off-by: LI Qingwu <Qing-wu.Li@leica-geosystems.com.cn>
---
drivers/iio/accel/sca3300.c | 29 ++++++++++++++++++++++++++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/drivers/iio/accel/sca3300.c b/drivers/iio/accel/sca3300.c
index 26e6fab88a8f..7ea3e202d474 100644
--- a/drivers/iio/accel/sca3300.c
+++ b/drivers/iio/accel/sca3300.c
@@ -68,7 +68,6 @@ static const struct iio_enum sca3300_op_mode_enum = {
.get = sca3300_get_op_mode,
.set = sca3300_set_op_mode,
};
-
static const struct iio_chan_spec_ext_info sca3300_ext_info[] = {
IIO_ENUM("op_mode", IIO_SHARED_BY_DIR, &sca3300_op_mode_enum),
IIO_ENUM_AVAILABLE("op_mode", &sca3300_op_mode_enum),
@@ -77,6 +76,7 @@ static const struct iio_chan_spec_ext_info sca3300_ext_info[] = {
enum sca3300_chip_type {
CHIP_SCA3300 = 0,
+ CHIP_SCL3300,
CHIP_CNT
};
@@ -131,12 +131,23 @@ static const struct iio_chan_spec sca3300_channels[] = {
IIO_CHAN_SOFT_TIMESTAMP(4)
};
+static const struct iio_chan_spec scl3300_channels[] = {
+ SCA3300_ACCEL_CHANNEL(SCA3300_ACC_X, 0x1, X),
+ SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y),
+ SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z),
+ SCA3300_TEMP_CHANNEL(SCA3300_TEMP, 0x05),
+ IIO_CHAN_SOFT_TIMESTAMP(4),
+};
+
+
static const int sca3300_lp_freq[CHIP_CNT][OP_MOD_CNT] = {
[CHIP_SCA3300] = {70, 70, 70, 10},
+ [CHIP_SCL3300] = {40, 70, 10, 10},
};
static const int sca3300_accel_scale[CHIP_CNT][OP_MOD_CNT][2] = {
[CHIP_SCA3300] = {{0, 370}, {0, 741}, {0, 185}, {0, 185}},
+ [CHIP_SCL3300] = {{0, 167}, {0, 333}, {0, 83}, {0, 83}}
};
static const unsigned long sca3300_scan_masks[] = {
@@ -184,6 +195,14 @@ static const struct sca3300_chip_info sca3300_chip_info_tbl[] = {
.num_channels = ARRAY_SIZE(sca3300_channels),
.scan_masks = sca3300_scan_masks,
},
+ [CHIP_SCL3300] = {
+ .chip_type = CHIP_SCL3300,
+ .name = "scl3300",
+ .chip_id = 0xC1,
+ .channels = scl3300_channels,
+ .num_channels = ARRAY_SIZE(scl3300_channels),
+ .scan_masks = sca3300_scan_masks,
+ },
};
DECLARE_CRC8_TABLE(sca3300_crc_table);
@@ -310,10 +329,14 @@ static int sca3300_write_raw(struct iio_dev *indio_dev,
}
return -EINVAL;
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
+ if (data->chip_info->chip_type == CHIP_SCL3300) {
+ /*SCL3300 freq.tied to accel scale, not allowed to set separately.*/
+ return -EINVAL;
+ }
ret = sca3300_read_reg(data, SCA3300_REG_MODE, ®_val);
if (ret)
return ret;
- /* freq. change is possible only for mode 3 and 4 */
+ /* SCA330 freq. change is possible only for mode 3 and 4 */
if (reg_val == 2 && val == sca3300_lp_freq[data->chip_info->chip_type][3])
return sca3300_write_reg(data, SCA3300_REG_MODE, 3);
if (reg_val == 3 && val == sca3300_lp_freq[data->chip_info->chip_type][2])
@@ -459,7 +482,6 @@ static int sca3300_read_avail(struct iio_dev *indio_dev,
long mask)
{
struct sca3300_data *data = iio_priv(indio_dev);
-
switch (mask) {
case IIO_CHAN_INFO_SCALE:
if (chan->type == IIO_ACCEL) {
@@ -553,6 +575,7 @@ static int sca3300_probe(struct spi_device *spi)
static const struct of_device_id sca3300_dt_ids[] = {
{ .compatible = "murata,sca3300"},
+ { .compatible = "murata,scl3300"},
{}
};
MODULE_DEVICE_TABLE(of, sca3300_dt_ids);
--
2.25.1
^ permalink raw reply related
* [PATCH V1 5/6] iio: accel: sca3300: Add inclination channels.
From: LI Qingwu @ 2022-01-24 9:39 UTC (permalink / raw)
To: qing-wu.li, jic23, lars, robh+dt, tomas.melin, andy.shevchenko,
devicetree, linux-kernel
Cc: LI Qingwu
In-Reply-To: <20220124093912.2429190-1-Qing-wu.Li@leica-geosystems.com.cn>
Different with SCA3300, SCL3300 can output inclination angles.
Angles are formed from acceleration with following equations:
ANG_X = atan2(accx / √(accy^2 + accz^2)),
ANG_Y = atan2(accy / √(accx^2 + accz^2)),
ANG_Z = atan2(accz / √(accx^2 + accy^2)),
The commit add output of the raw value,scale
and scale_available of angles.
add interface for enable/disable of the angle output.
new interfaces:
in_incli_en
in_incli_scale
in_incli_scale_available
in_incli_x_raw
in_incli_y_raw
in_incli_z_raw
Signed-off-by: LI Qingwu <Qing-wu.Li@leica-geosystems.com.cn>
---
drivers/iio/accel/sca3300.c | 82 +++++++++++++++++++++++++++++++++----
1 file changed, 75 insertions(+), 7 deletions(-)
diff --git a/drivers/iio/accel/sca3300.c b/drivers/iio/accel/sca3300.c
index 7ea3e202d474..535d14b58acf 100644
--- a/drivers/iio/accel/sca3300.c
+++ b/drivers/iio/accel/sca3300.c
@@ -42,6 +42,8 @@
#define SCA3300_VALUE_RS_ERROR 0x3
#define SCA3300_MASK_RS_STATUS GENMASK(1, 0)
+#define SCA3300_REG_ANG_CTRL 0x0C
+
enum sca3300_op_mode_indexes {
OP_MOD_1 = 0,
OP_MOD_2,
@@ -85,6 +87,9 @@ enum sca3300_scan_indexes {
SCA3300_ACC_Y,
SCA3300_ACC_Z,
SCA3300_TEMP,
+ SCA3300_INCLI_X,
+ SCA3300_INCLI_Y,
+ SCA3300_INCLI_Z,
SCA3300_TIMESTAMP,
};
@@ -110,6 +115,26 @@ enum sca3300_scan_indexes {
.ext_info = sca3300_ext_info, \
}
+#define SCA3300_INCLI_CHANNEL(index, reg, axis) { \
+ .type = IIO_INCLI, \
+ .address = reg, \
+ .modified = 1, \
+ .channel2 = IIO_MOD_##axis, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
+ .info_mask_shared_by_type = \
+ BIT(IIO_CHAN_INFO_SCALE) | \
+ BIT(IIO_CHAN_INFO_ENABLE), \
+ .info_mask_shared_by_type_available = \
+ BIT(IIO_CHAN_INFO_SCALE), \
+ .scan_index = index, \
+ .scan_type = { \
+ .sign = 's', \
+ .realbits = 16, \
+ .storagebits = 16, \
+ .endianness = IIO_CPU, \
+ }, \
+}
+
#define SCA3300_TEMP_CHANNEL(index, reg) { \
.type = IIO_TEMP, \
.address = reg, \
@@ -128,7 +153,7 @@ static const struct iio_chan_spec sca3300_channels[] = {
SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y),
SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z),
SCA3300_TEMP_CHANNEL(SCA3300_TEMP, 0x05),
- IIO_CHAN_SOFT_TIMESTAMP(4)
+ IIO_CHAN_SOFT_TIMESTAMP(SCA3300_TIMESTAMP)
};
static const struct iio_chan_spec scl3300_channels[] = {
@@ -136,7 +161,10 @@ static const struct iio_chan_spec scl3300_channels[] = {
SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y),
SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z),
SCA3300_TEMP_CHANNEL(SCA3300_TEMP, 0x05),
- IIO_CHAN_SOFT_TIMESTAMP(4),
+ SCA3300_INCLI_CHANNEL(SCA3300_INCLI_X, 0x09, X),
+ SCA3300_INCLI_CHANNEL(SCA3300_INCLI_Y, 0x0A, Y),
+ SCA3300_INCLI_CHANNEL(SCA3300_INCLI_Z, 0x0B, Z),
+ IIO_CHAN_SOFT_TIMESTAMP(SCA3300_TIMESTAMP)
};
@@ -150,12 +178,24 @@ static const int sca3300_accel_scale[CHIP_CNT][OP_MOD_CNT][2] = {
[CHIP_SCL3300] = {{0, 167}, {0, 333}, {0, 83}, {0, 83}}
};
+static const int sca3300_incli_scale[CHIP_CNT][OP_MOD_CNT][2] = {
+ [CHIP_SCA3300] = {{0, 0}, {0, 0}, {0, 0}, {0, 0}},
+ [CHIP_SCL3300] = {{0, 5495}, {0, 5495}, {0, 5495}, {0, 5495}}
+};
+
static const unsigned long sca3300_scan_masks[] = {
BIT(SCA3300_ACC_X) | BIT(SCA3300_ACC_Y) | BIT(SCA3300_ACC_Z) |
BIT(SCA3300_TEMP),
0
};
+static const unsigned long scl3300_scan_masks[] = {
+ BIT(SCA3300_ACC_X) | BIT(SCA3300_ACC_Y) | BIT(SCA3300_ACC_Z) |
+ BIT(SCA3300_TEMP) |
+ BIT(SCA3300_INCLI_X) | BIT(SCA3300_INCLI_Y) | BIT(SCA3300_INCLI_Z),
+ 0
+};
+
struct sca3300_chip_info {
enum sca3300_chip_type chip_type;
const char *name;
@@ -177,13 +217,12 @@ struct sca3300_data {
struct spi_device *spi;
struct mutex lock;
struct {
- s16 channels[4];
+ s16 channels[SCA3300_TIMESTAMP-1];
s64 ts __aligned(sizeof(s64));
} scan;
const struct sca3300_chip_info *chip_info;
u8 txbuf[4] ____cacheline_aligned;
u8 rxbuf[4];
-
};
static const struct sca3300_chip_info sca3300_chip_info_tbl[] = {
@@ -201,7 +240,7 @@ static const struct sca3300_chip_info sca3300_chip_info_tbl[] = {
.chip_id = 0xC1,
.channels = scl3300_channels,
.num_channels = ARRAY_SIZE(scl3300_channels),
- .scan_masks = sca3300_scan_masks,
+ .scan_masks = scl3300_scan_masks,
},
};
@@ -322,11 +361,15 @@ static int sca3300_write_raw(struct iio_dev *indio_dev,
switch (mask) {
case IIO_CHAN_INFO_SCALE:
+ if (chan->type != IIO_ACCEL)
+ return -EINVAL;
for (i = 0; i < OP_MOD_CNT; i++) {
if ((val == sca3300_accel_scale[data->chip_info->chip_type][0]) &&
(val2 == sca3300_accel_scale[data->chip_info->chip_type][1]))
return sca3300_write_reg(data, SCA3300_REG_MODE, i);
}
+ /*Inclination scale info tied to accel scale.*/
+ /*not allowed to set separately. */
return -EINVAL;
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
if (data->chip_info->chip_type == CHIP_SCL3300) {
@@ -342,6 +385,17 @@ static int sca3300_write_raw(struct iio_dev *indio_dev,
if (reg_val == 3 && val == sca3300_lp_freq[data->chip_info->chip_type][2])
return sca3300_write_reg(data, SCA3300_REG_MODE, 2);
return -EINVAL;
+ case IIO_CHAN_INFO_ENABLE:
+ if (data->chip_info->chip_type == CHIP_SCL3300) {
+ if (chan->type == IIO_INCLI) {
+ if (val != 0)
+ reg_val = 0x1F;
+ else
+ reg_val = 0x00;
+ return sca3300_write_reg(data, SCA3300_REG_ANG_CTRL, reg_val);
+ }
+ }
+ return -EINVAL;
default:
return -EINVAL;
}
@@ -365,7 +419,11 @@ static int sca3300_read_raw(struct iio_dev *indio_dev,
ret = sca3300_read_reg(data, SCA3300_REG_MODE, ®_val);
if (ret)
return ret;
- if (chan->type == IIO_ACCEL) {
+
+ if (chan->type == IIO_INCLI) {
+ *val = sca3300_incli_scale[data->chip_info->chip_type][reg_val][0];
+ *val2 = sca3300_incli_scale[data->chip_info->chip_type][reg_val][1];
+ } else if (chan->type == IIO_ACCEL) {
*val = sca3300_accel_scale[data->chip_info->chip_type][reg_val][0];
*val2 = sca3300_accel_scale[data->chip_info->chip_type][reg_val][1];
} else {
@@ -378,6 +436,13 @@ static int sca3300_read_raw(struct iio_dev *indio_dev,
return ret;
*val = sca3300_lp_freq[data->chip_info->chip_type][reg_val];
return IIO_VAL_INT;
+ case IIO_CHAN_INFO_ENABLE:
+ if (chan->type == IIO_INCLI) {
+ ret = sca3300_read_reg(data, SCA3300_REG_ANG_CTRL, ®_val);
+ *val = reg_val;
+ return IIO_VAL_INT;
+ }
+ return -EINVAL;
default:
return -EINVAL;
}
@@ -484,7 +549,10 @@ static int sca3300_read_avail(struct iio_dev *indio_dev,
struct sca3300_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_SCALE:
- if (chan->type == IIO_ACCEL) {
+ if (chan->type == IIO_INCLI) {
+ *vals = (const int *)sca3300_incli_scale[data->chip_info->chip_type];
+ *length = ARRAY_SIZE(sca3300_incli_scale[data->chip_info->chip_type]) * 2;
+ } else if (chan->type == IIO_ACCEL) {
*vals = (const int *)sca3300_accel_scale[data->chip_info->chip_type];
*length = ARRAY_SIZE(sca3300_accel_scale[data->chip_info->chip_type]) * 2;
} else {
--
2.25.1
^ permalink raw reply related
* [PATCH V1 6/6] dt-bindings: iio: accel: sca3300: Document murata,scl3300
From: LI Qingwu @ 2022-01-24 9:39 UTC (permalink / raw)
To: qing-wu.li, jic23, lars, robh+dt, tomas.melin, andy.shevchenko,
devicetree, linux-kernel
Cc: LI Qingwu
In-Reply-To: <20220124093912.2429190-1-Qing-wu.Li@leica-geosystems.com.cn>
initial DT bindings for Murata scl3300 inclinometer.
Signed-off-by: LI Qingwu <Qing-wu.Li@leica-geosystems.com.cn>
---
Documentation/devicetree/bindings/iio/accel/murata,sca3300.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iio/accel/murata,sca3300.yaml b/Documentation/devicetree/bindings/iio/accel/murata,sca3300.yaml
index 55fd3548e3b6..f6e2a16a710b 100644
--- a/Documentation/devicetree/bindings/iio/accel/murata,sca3300.yaml
+++ b/Documentation/devicetree/bindings/iio/accel/murata,sca3300.yaml
@@ -17,6 +17,7 @@ properties:
compatible:
enum:
- murata,sca3300
+ - murata,scl3300
reg:
maxItems: 1
--
2.25.1
^ permalink raw reply related
* Re: [PATCH RFC 1/4] brcmfmac: use separate firmware for 43430 revision 4
From: Arend van Spriel @ 2022-01-24 9:43 UTC (permalink / raw)
To: Stefan Wahren, Rob Herring, Florian Fainelli,
Nicolas Saenz Julienne, Arend van Spriel, Franky Lin,
Hante Meuleman, Chi-hsien Lin, Wright Feng, Chung-hsien Hsu,
Kalle Valo
Cc: Ray Jui, Scott Branden, bcm-kernel-feedback-list, Arnd Bergmann,
Olof Johansson, Phil Elwell, devicetree, soc, linux-arm-kernel,
linux-wireless, brcm80211-dev-list.pdl, linux-rpi-kernel
In-Reply-To: <8ed4450d-85d9-c69b-761a-7695b3f1bbb3@i2se.com>
[-- Attachment #1: Type: text/plain, Size: 2575 bytes --]
On 1/22/2022 1:35 PM, Stefan Wahren wrote:
> Am 01.01.22 um 21:26 schrieb Stefan Wahren:
>> A separate firmware is needed, for Broadcom 43430 revision 4. This
>> chip can be found on e.g. certain revisions of Raspberry Pi Zero 2 W.
>> Original firmware file from IC vendor is named 'brcmfmac43436-sdio.bin',
>> but brcmfmac and also btbcm drivers report chip id 43430, so requested
>> firmware file name is 'brcmfmac43430c0-sdio.bin' in line with other
>> 43430 revisions.
>>
>> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
>> ---
>>
>> Hi,
>> i'm not sure about all these mappings. All i can say is that the wifi
>> interface of the RPi Zero 2 cames up with this patch.
> gentle ping (yes, i'm aware of the merge window)
Sorry, Stefan
Should have seen this earlier, but here it is....
>>
>> drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
>> index 8effeb7..c79bd47 100644
>> --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
>> +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
>> @@ -618,6 +618,7 @@ BRCMF_FW_DEF(43430A0, "brcmfmac43430a0-sdio");
>> /* Note the names are not postfixed with a1 for backward compatibility */
>> BRCMF_FW_CLM_DEF(43430A1, "brcmfmac43430-sdio");
>> BRCMF_FW_DEF(43430B0, "brcmfmac43430b0-sdio");
>> +BRCMF_FW_CLM_DEF(43430C0, "brcmfmac43430c0-sdio");
>> BRCMF_FW_CLM_DEF(43455, "brcmfmac43455-sdio");
>> BRCMF_FW_DEF(43456, "brcmfmac43456-sdio");
>> BRCMF_FW_CLM_DEF(4354, "brcmfmac4354-sdio");
>> @@ -649,7 +650,8 @@ static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
>> BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
>> BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000001, 43430A0),
>> BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000002, 43430A1),
>> - BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFC, 43430B0),
>> + BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000004, 43430C0),
According to the revision mask your firmware seems to be for numerical
revision 2 of this chip...
>> + BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFF8, 43430B0),
and for the b0 the chip revision is 3 (or higher). So the alphanumeric
revision of your chip would be 'a2' instead of 'c0'.
>> BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0x00000200, 43456),
>> BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFDC0, 43455),
>> BRCMF_FW_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354),
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4219 bytes --]
^ permalink raw reply
* [PATCH 2/6] dt-bindings: firmware: arm,scmi: Add atomic_threshold optional property
From: Cristian Marussi @ 2022-01-24 10:03 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel
Cc: sudeep.holla, james.quinlan, Jonathan.Cameron, f.fainelli,
etienne.carriere, vincent.guittot, souvik.chakravarty,
peter.hilber, igor.skalkin, cristian.marussi, Rob Herring,
devicetree
In-Reply-To: <20220124100341.41191-1-cristian.marussi@arm.com>
SCMI protocols in the platform can optionally signal to the OSPM agent
the expected execution latency for a specific resource/operation pair.
Introduce an SCMI system wide optional property to describe a global time
threshold which can be configured on a per-platform base to determine the
opportunity, or not, for an SCMI command advertised to have a higher
latency than the threshold, to be considered for atomic operations:
high-latency SCMI synchronous commands should be preferably issued in the
usual non-atomic mode.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
---
.../devicetree/bindings/firmware/arm,scmi.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
index eae15df36eef..8edda54dff5b 100644
--- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
+++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
@@ -81,6 +81,14 @@ properties:
'#size-cells':
const: 0
+ atomic_threshold:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ An optional time value, expressed in microseconds, representing the
+ threshold above which, on this platform, any SCMI command advertised to
+ have a higher execution latency, should not be used in atomic mode, even
+ if requested. If left unconfigured defaults to zero.
+
arm,smc-id:
$ref: /schemas/types.yaml#/definitions/uint32
description:
@@ -264,6 +272,8 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
+ atomic_threshold = <10000>;
+
scmi_devpd: protocol@11 {
reg = <0x11>;
#power-domain-cells = <1>;
--
2.17.1
^ permalink raw reply related
* [PATCH V4 1/2] dt-bindings: pinctrl: Add binding for BCM4908 pinctrl
From: Rafał Miłecki @ 2022-01-24 10:22 UTC (permalink / raw)
To: Rob Herring, Linus Walleij
Cc: Álvaro Fernández Rojas, Jonas Gorski, Randy Dunlap,
Florian Fainelli, linux-gpio, devicetree,
bcm-kernel-feedback-list, Andy Shevchenko,
Rafał Miłecki, Rob Herring
From: Rafał Miłecki <rafal@milecki.pl>
It's hardware block that is part of every SoC from BCM4908 family.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: Rob Herring <robh@kernel.org>
---
V4: Rebased on top of the latest for-next which includes 5.17-rc1 now
---
.../pinctrl/brcm,bcm4908-pinctrl.yaml | 72 +++++++++++++++++++
MAINTAINERS | 7 ++
2 files changed, 79 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
new file mode 100644
index 000000000000..175a992f15e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm4908-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM4908 pin controller
+
+maintainers:
+ - Rafał Miłecki <rafal@milecki.pl>
+
+description:
+ Binding for pin controller present on BCM4908 family SoCs.
+
+properties:
+ compatible:
+ const: brcm,bcm4908-pinctrl
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ '-pins$':
+ type: object
+ $ref: pinmux-node.yaml#
+
+ properties:
+ function:
+ enum: [ led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7, led_8,
+ led_9, led_10, led_11, led_12, led_13, led_14, led_15, led_16,
+ led_17, led_18, led_19, led_20, led_21, led_22, led_23, led_24,
+ led_25, led_26, led_27, led_28, led_29, led_30, led_31,
+ hs_uart, i2c, i2s, nand_ctrl, nand_data, emmc_ctrl, usb0_pwr,
+ usb1_pwr ]
+
+ groups:
+ minItems: 1
+ maxItems: 2
+ items:
+ enum: [ led_0_grp_a, led_1_grp_a, led_2_grp_a, led_3_grp_a,
+ led_4_grp_a, led_5_grp_a, led_6_grp_a, led_7_grp_a,
+ led_8_grp_a, led_9_grp_a, led_10_grp_a, led_10_grp_b,
+ led_11_grp_a, led_11_grp_b, led_12_grp_a, led_12_grp_b,
+ led_13_grp_a, led_13_grp_b, led_14_grp_a, led_15_grp_a,
+ led_16_grp_a, led_17_grp_a, led_18_grp_a, led_19_grp_a,
+ led_20_grp_a, led_21_grp_a, led_22_grp_a, led_23_grp_a,
+ led_24_grp_a, led_25_grp_a, led_26_grp_a, led_27_grp_a,
+ led_28_grp_a, led_29_grp_a, led_30_grp_a, led_31_grp_a,
+ led_31_grp_b, hs_uart_grp, i2c_grp_a, i2c_grp_b, i2s_grp,
+ nand_ctrl_grp, nand_data_grp, emmc_ctrl_grp, usb0_pwr_grp,
+ usb1_pwr_grp ]
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ pinctrl@ff800560 {
+ compatible = "brcm,bcm4908-pinctrl";
+ reg = <0xff800560 0x10>;
+
+ led_0-a-pins {
+ function = "led_0";
+ groups = "led_0_grp_a";
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index ea3e6c914384..dc12f93a5df4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3688,6 +3688,13 @@ F: Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
F: drivers/net/ethernet/broadcom/bcm4908_enet.*
F: drivers/net/ethernet/broadcom/unimac.h
+BROADCOM BCM4908 PINMUX DRIVER
+M: Rafał Miłecki <rafal@milecki.pl>
+M: bcm-kernel-feedback-list@broadcom.com
+L: linux-gpio@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
+
BROADCOM BCM5301X ARM ARCHITECTURE
M: Florian Fainelli <f.fainelli@gmail.com>
M: Hauke Mehrtens <hauke@hauke-m.de>
--
2.31.1
^ permalink raw reply related
* [PATCH V4 2/2] pinctrl: bcm: add driver for BCM4908 pinmux
From: Rafał Miłecki @ 2022-01-24 10:22 UTC (permalink / raw)
To: Rob Herring, Linus Walleij
Cc: Álvaro Fernández Rojas, Jonas Gorski, Randy Dunlap,
Florian Fainelli, linux-gpio, devicetree,
bcm-kernel-feedback-list, Andy Shevchenko,
Rafał Miłecki
In-Reply-To: <20220124102243.14912-1-zajec5@gmail.com>
From: Rafał Miłecki <rafal@milecki.pl>
BCM4908 has its own pins layout so it needs a custom binding and a Linux
driver.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
---
V2: Formatting fixes
Kconfig fix
Cleanup of #include-s
Use devm_kasprintf_strarray()
V3: Bring back OF dependency - required by pinconf_generic_dt_node_to_map()
V4: Rebased on top of the latest for-next which includes 5.17-rc1 now
---
MAINTAINERS | 1 +
drivers/pinctrl/bcm/Kconfig | 14 +
drivers/pinctrl/bcm/Makefile | 1 +
drivers/pinctrl/bcm/pinctrl-bcm4908.c | 563 ++++++++++++++++++++++++++
4 files changed, 579 insertions(+)
create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm4908.c
diff --git a/MAINTAINERS b/MAINTAINERS
index dc12f93a5df4..847394a6ef1d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3694,6 +3694,7 @@ M: bcm-kernel-feedback-list@broadcom.com
L: linux-gpio@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
+F: drivers/pinctrl/bcm/pinctrl-bcm4908.c
BROADCOM BCM5301X ARM ARCHITECTURE
M: Florian Fainelli <f.fainelli@gmail.com>
diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig
index 5123f4c33854..042ec2494698 100644
--- a/drivers/pinctrl/bcm/Kconfig
+++ b/drivers/pinctrl/bcm/Kconfig
@@ -29,6 +29,20 @@ config PINCTRL_BCM2835
help
Say Y here to enable the Broadcom BCM2835 GPIO driver.
+config PINCTRL_BCM4908
+ tristate "Broadcom BCM4908 pinmux driver"
+ depends on OF && (ARCH_BCM4908 || COMPILE_TEST)
+ select PINMUX
+ select PINCONF
+ select GENERIC_PINCONF
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ default ARCH_BCM4908
+ help
+ Driver for BCM4908 family SoCs with integrated pin controller.
+
+ If compiled as module it will be called pinctrl-bcm4908.
+
config PINCTRL_BCM63XX
bool
select PINMUX
diff --git a/drivers/pinctrl/bcm/Makefile b/drivers/pinctrl/bcm/Makefile
index 00c7b7775e63..82b868ec1471 100644
--- a/drivers/pinctrl/bcm/Makefile
+++ b/drivers/pinctrl/bcm/Makefile
@@ -3,6 +3,7 @@
obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
+obj-$(CONFIG_PINCTRL_BCM4908) += pinctrl-bcm4908.o
obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o
obj-$(CONFIG_PINCTRL_BCM6318) += pinctrl-bcm6318.o
obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o
diff --git a/drivers/pinctrl/bcm/pinctrl-bcm4908.c b/drivers/pinctrl/bcm/pinctrl-bcm4908.c
new file mode 100644
index 000000000000..cdfa165fc033
--- /dev/null
+++ b/drivers/pinctrl/bcm/pinctrl-bcm4908.c
@@ -0,0 +1,563 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl> */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/string_helpers.h>
+
+#include "../core.h"
+#include "../pinmux.h"
+
+#define BCM4908_NUM_PINS 86
+
+#define BCM4908_TEST_PORT_BLOCK_EN_LSB 0x00
+#define BCM4908_TEST_PORT_BLOCK_DATA_MSB 0x04
+#define BCM4908_TEST_PORT_BLOCK_DATA_LSB 0x08
+#define BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT 12
+#define BCM4908_TEST_PORT_COMMAND 0x0c
+#define BCM4908_TEST_PORT_CMD_LOAD_MUX_REG 0x00000021
+
+struct bcm4908_pinctrl {
+ struct device *dev;
+ void __iomem *base;
+ struct mutex mutex;
+ struct pinctrl_dev *pctldev;
+ struct pinctrl_desc pctldesc;
+};
+
+/*
+ * Groups
+ */
+
+struct bcm4908_pinctrl_pin_setup {
+ unsigned int number;
+ unsigned int function;
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_0_pins_a[] = {
+ { 0, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_1_pins_a[] = {
+ { 1, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_2_pins_a[] = {
+ { 2, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_3_pins_a[] = {
+ { 3, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_4_pins_a[] = {
+ { 4, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_5_pins_a[] = {
+ { 5, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_6_pins_a[] = {
+ { 6, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_7_pins_a[] = {
+ { 7, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_8_pins_a[] = {
+ { 8, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_9_pins_a[] = {
+ { 9, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_10_pins_a[] = {
+ { 10, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_11_pins_a[] = {
+ { 11, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_12_pins_a[] = {
+ { 12, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_13_pins_a[] = {
+ { 13, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_14_pins_a[] = {
+ { 14, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_15_pins_a[] = {
+ { 15, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_16_pins_a[] = {
+ { 16, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_17_pins_a[] = {
+ { 17, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_18_pins_a[] = {
+ { 18, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_19_pins_a[] = {
+ { 19, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_20_pins_a[] = {
+ { 20, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_21_pins_a[] = {
+ { 21, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_22_pins_a[] = {
+ { 22, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_23_pins_a[] = {
+ { 23, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_24_pins_a[] = {
+ { 24, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_25_pins_a[] = {
+ { 25, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_26_pins_a[] = {
+ { 26, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_27_pins_a[] = {
+ { 27, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_28_pins_a[] = {
+ { 28, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_29_pins_a[] = {
+ { 29, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_30_pins_a[] = {
+ { 30, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_31_pins_a[] = {
+ { 31, 3 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_10_pins_b[] = {
+ { 8, 2 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_11_pins_b[] = {
+ { 9, 2 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_12_pins_b[] = {
+ { 0, 2 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_13_pins_b[] = {
+ { 1, 2 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup led_31_pins_b[] = {
+ { 30, 2 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup hs_uart_pins[] = {
+ { 10, 0 }, /* CTS */
+ { 11, 0 }, /* RTS */
+ { 12, 0 }, /* RXD */
+ { 13, 0 }, /* TXD */
+};
+
+static const struct bcm4908_pinctrl_pin_setup i2c_pins_a[] = {
+ { 18, 0 }, /* SDA */
+ { 19, 0 }, /* SCL */
+};
+
+static const struct bcm4908_pinctrl_pin_setup i2c_pins_b[] = {
+ { 22, 0 }, /* SDA */
+ { 23, 0 }, /* SCL */
+};
+
+static const struct bcm4908_pinctrl_pin_setup i2s_pins[] = {
+ { 27, 0 }, /* MCLK */
+ { 28, 0 }, /* LRCK */
+ { 29, 0 }, /* SDATA */
+ { 30, 0 }, /* SCLK */
+};
+
+static const struct bcm4908_pinctrl_pin_setup nand_ctrl_pins[] = {
+ { 32, 0 },
+ { 33, 0 },
+ { 34, 0 },
+ { 43, 0 },
+ { 44, 0 },
+ { 45, 0 },
+ { 56, 1 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup nand_data_pins[] = {
+ { 35, 0 },
+ { 36, 0 },
+ { 37, 0 },
+ { 38, 0 },
+ { 39, 0 },
+ { 40, 0 },
+ { 41, 0 },
+ { 42, 0 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup emmc_ctrl_pins[] = {
+ { 46, 0 },
+ { 47, 0 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup usb0_pwr_pins[] = {
+ { 63, 0 },
+ { 64, 0 },
+};
+
+static const struct bcm4908_pinctrl_pin_setup usb1_pwr_pins[] = {
+ { 66, 0 },
+ { 67, 0 },
+};
+
+struct bcm4908_pinctrl_grp {
+ const char *name;
+ const struct bcm4908_pinctrl_pin_setup *pins;
+ const unsigned int num_pins;
+};
+
+static const struct bcm4908_pinctrl_grp bcm4908_pinctrl_grps[] = {
+ { "led_0_grp_a", led_0_pins_a, ARRAY_SIZE(led_0_pins_a) },
+ { "led_1_grp_a", led_1_pins_a, ARRAY_SIZE(led_1_pins_a) },
+ { "led_2_grp_a", led_2_pins_a, ARRAY_SIZE(led_2_pins_a) },
+ { "led_3_grp_a", led_3_pins_a, ARRAY_SIZE(led_3_pins_a) },
+ { "led_4_grp_a", led_4_pins_a, ARRAY_SIZE(led_4_pins_a) },
+ { "led_5_grp_a", led_5_pins_a, ARRAY_SIZE(led_5_pins_a) },
+ { "led_6_grp_a", led_6_pins_a, ARRAY_SIZE(led_6_pins_a) },
+ { "led_7_grp_a", led_7_pins_a, ARRAY_SIZE(led_7_pins_a) },
+ { "led_8_grp_a", led_8_pins_a, ARRAY_SIZE(led_8_pins_a) },
+ { "led_9_grp_a", led_9_pins_a, ARRAY_SIZE(led_9_pins_a) },
+ { "led_10_grp_a", led_10_pins_a, ARRAY_SIZE(led_10_pins_a) },
+ { "led_11_grp_a", led_11_pins_a, ARRAY_SIZE(led_11_pins_a) },
+ { "led_12_grp_a", led_12_pins_a, ARRAY_SIZE(led_12_pins_a) },
+ { "led_13_grp_a", led_13_pins_a, ARRAY_SIZE(led_13_pins_a) },
+ { "led_14_grp_a", led_14_pins_a, ARRAY_SIZE(led_14_pins_a) },
+ { "led_15_grp_a", led_15_pins_a, ARRAY_SIZE(led_15_pins_a) },
+ { "led_16_grp_a", led_16_pins_a, ARRAY_SIZE(led_16_pins_a) },
+ { "led_17_grp_a", led_17_pins_a, ARRAY_SIZE(led_17_pins_a) },
+ { "led_18_grp_a", led_18_pins_a, ARRAY_SIZE(led_18_pins_a) },
+ { "led_19_grp_a", led_19_pins_a, ARRAY_SIZE(led_19_pins_a) },
+ { "led_20_grp_a", led_20_pins_a, ARRAY_SIZE(led_20_pins_a) },
+ { "led_21_grp_a", led_21_pins_a, ARRAY_SIZE(led_21_pins_a) },
+ { "led_22_grp_a", led_22_pins_a, ARRAY_SIZE(led_22_pins_a) },
+ { "led_23_grp_a", led_23_pins_a, ARRAY_SIZE(led_23_pins_a) },
+ { "led_24_grp_a", led_24_pins_a, ARRAY_SIZE(led_24_pins_a) },
+ { "led_25_grp_a", led_25_pins_a, ARRAY_SIZE(led_25_pins_a) },
+ { "led_26_grp_a", led_26_pins_a, ARRAY_SIZE(led_26_pins_a) },
+ { "led_27_grp_a", led_27_pins_a, ARRAY_SIZE(led_27_pins_a) },
+ { "led_28_grp_a", led_28_pins_a, ARRAY_SIZE(led_28_pins_a) },
+ { "led_29_grp_a", led_29_pins_a, ARRAY_SIZE(led_29_pins_a) },
+ { "led_30_grp_a", led_30_pins_a, ARRAY_SIZE(led_30_pins_a) },
+ { "led_31_grp_a", led_31_pins_a, ARRAY_SIZE(led_31_pins_a) },
+ { "led_10_grp_b", led_10_pins_b, ARRAY_SIZE(led_10_pins_b) },
+ { "led_11_grp_b", led_11_pins_b, ARRAY_SIZE(led_11_pins_b) },
+ { "led_12_grp_b", led_12_pins_b, ARRAY_SIZE(led_12_pins_b) },
+ { "led_13_grp_b", led_13_pins_b, ARRAY_SIZE(led_13_pins_b) },
+ { "led_31_grp_b", led_31_pins_b, ARRAY_SIZE(led_31_pins_b) },
+ { "hs_uart_grp", hs_uart_pins, ARRAY_SIZE(hs_uart_pins) },
+ { "i2c_grp_a", i2c_pins_a, ARRAY_SIZE(i2c_pins_a) },
+ { "i2c_grp_b", i2c_pins_b, ARRAY_SIZE(i2c_pins_b) },
+ { "i2s_grp", i2s_pins, ARRAY_SIZE(i2s_pins) },
+ { "nand_ctrl_grp", nand_ctrl_pins, ARRAY_SIZE(nand_ctrl_pins) },
+ { "nand_data_grp", nand_data_pins, ARRAY_SIZE(nand_data_pins) },
+ { "emmc_ctrl_grp", emmc_ctrl_pins, ARRAY_SIZE(emmc_ctrl_pins) },
+ { "usb0_pwr_grp", usb0_pwr_pins, ARRAY_SIZE(usb0_pwr_pins) },
+ { "usb1_pwr_grp", usb1_pwr_pins, ARRAY_SIZE(usb1_pwr_pins) },
+};
+
+/*
+ * Functions
+ */
+
+struct bcm4908_pinctrl_function {
+ const char *name;
+ const char * const *groups;
+ const unsigned int num_groups;
+};
+
+static const char * const led_0_groups[] = { "led_0_grp_a" };
+static const char * const led_1_groups[] = { "led_1_grp_a" };
+static const char * const led_2_groups[] = { "led_2_grp_a" };
+static const char * const led_3_groups[] = { "led_3_grp_a" };
+static const char * const led_4_groups[] = { "led_4_grp_a" };
+static const char * const led_5_groups[] = { "led_5_grp_a" };
+static const char * const led_6_groups[] = { "led_6_grp_a" };
+static const char * const led_7_groups[] = { "led_7_grp_a" };
+static const char * const led_8_groups[] = { "led_8_grp_a" };
+static const char * const led_9_groups[] = { "led_9_grp_a" };
+static const char * const led_10_groups[] = { "led_10_grp_a", "led_10_grp_b" };
+static const char * const led_11_groups[] = { "led_11_grp_a", "led_11_grp_b" };
+static const char * const led_12_groups[] = { "led_12_grp_a", "led_12_grp_b" };
+static const char * const led_13_groups[] = { "led_13_grp_a", "led_13_grp_b" };
+static const char * const led_14_groups[] = { "led_14_grp_a" };
+static const char * const led_15_groups[] = { "led_15_grp_a" };
+static const char * const led_16_groups[] = { "led_16_grp_a" };
+static const char * const led_17_groups[] = { "led_17_grp_a" };
+static const char * const led_18_groups[] = { "led_18_grp_a" };
+static const char * const led_19_groups[] = { "led_19_grp_a" };
+static const char * const led_20_groups[] = { "led_20_grp_a" };
+static const char * const led_21_groups[] = { "led_21_grp_a" };
+static const char * const led_22_groups[] = { "led_22_grp_a" };
+static const char * const led_23_groups[] = { "led_23_grp_a" };
+static const char * const led_24_groups[] = { "led_24_grp_a" };
+static const char * const led_25_groups[] = { "led_25_grp_a" };
+static const char * const led_26_groups[] = { "led_26_grp_a" };
+static const char * const led_27_groups[] = { "led_27_grp_a" };
+static const char * const led_28_groups[] = { "led_28_grp_a" };
+static const char * const led_29_groups[] = { "led_29_grp_a" };
+static const char * const led_30_groups[] = { "led_30_grp_a" };
+static const char * const led_31_groups[] = { "led_31_grp_a", "led_31_grp_b" };
+static const char * const hs_uart_groups[] = { "hs_uart_grp" };
+static const char * const i2c_groups[] = { "i2c_grp_a", "i2c_grp_b" };
+static const char * const i2s_groups[] = { "i2s_grp" };
+static const char * const nand_ctrl_groups[] = { "nand_ctrl_grp" };
+static const char * const nand_data_groups[] = { "nand_data_grp" };
+static const char * const emmc_ctrl_groups[] = { "emmc_ctrl_grp" };
+static const char * const usb0_pwr_groups[] = { "usb0_pwr_grp" };
+static const char * const usb1_pwr_groups[] = { "usb1_pwr_grp" };
+
+static const struct bcm4908_pinctrl_function bcm4908_pinctrl_functions[] = {
+ { "led_0", led_0_groups, ARRAY_SIZE(led_0_groups) },
+ { "led_1", led_1_groups, ARRAY_SIZE(led_1_groups) },
+ { "led_2", led_2_groups, ARRAY_SIZE(led_2_groups) },
+ { "led_3", led_3_groups, ARRAY_SIZE(led_3_groups) },
+ { "led_4", led_4_groups, ARRAY_SIZE(led_4_groups) },
+ { "led_5", led_5_groups, ARRAY_SIZE(led_5_groups) },
+ { "led_6", led_6_groups, ARRAY_SIZE(led_6_groups) },
+ { "led_7", led_7_groups, ARRAY_SIZE(led_7_groups) },
+ { "led_8", led_8_groups, ARRAY_SIZE(led_8_groups) },
+ { "led_9", led_9_groups, ARRAY_SIZE(led_9_groups) },
+ { "led_10", led_10_groups, ARRAY_SIZE(led_10_groups) },
+ { "led_11", led_11_groups, ARRAY_SIZE(led_11_groups) },
+ { "led_12", led_12_groups, ARRAY_SIZE(led_12_groups) },
+ { "led_13", led_13_groups, ARRAY_SIZE(led_13_groups) },
+ { "led_14", led_14_groups, ARRAY_SIZE(led_14_groups) },
+ { "led_15", led_15_groups, ARRAY_SIZE(led_15_groups) },
+ { "led_16", led_16_groups, ARRAY_SIZE(led_16_groups) },
+ { "led_17", led_17_groups, ARRAY_SIZE(led_17_groups) },
+ { "led_18", led_18_groups, ARRAY_SIZE(led_18_groups) },
+ { "led_19", led_19_groups, ARRAY_SIZE(led_19_groups) },
+ { "led_20", led_20_groups, ARRAY_SIZE(led_20_groups) },
+ { "led_21", led_21_groups, ARRAY_SIZE(led_21_groups) },
+ { "led_22", led_22_groups, ARRAY_SIZE(led_22_groups) },
+ { "led_23", led_23_groups, ARRAY_SIZE(led_23_groups) },
+ { "led_24", led_24_groups, ARRAY_SIZE(led_24_groups) },
+ { "led_25", led_25_groups, ARRAY_SIZE(led_25_groups) },
+ { "led_26", led_26_groups, ARRAY_SIZE(led_26_groups) },
+ { "led_27", led_27_groups, ARRAY_SIZE(led_27_groups) },
+ { "led_28", led_28_groups, ARRAY_SIZE(led_28_groups) },
+ { "led_29", led_29_groups, ARRAY_SIZE(led_29_groups) },
+ { "led_30", led_30_groups, ARRAY_SIZE(led_30_groups) },
+ { "led_31", led_31_groups, ARRAY_SIZE(led_31_groups) },
+ { "hs_uart", hs_uart_groups, ARRAY_SIZE(hs_uart_groups) },
+ { "i2c", i2c_groups, ARRAY_SIZE(i2c_groups) },
+ { "i2s", i2s_groups, ARRAY_SIZE(i2s_groups) },
+ { "nand_ctrl", nand_ctrl_groups, ARRAY_SIZE(nand_ctrl_groups) },
+ { "nand_data", nand_data_groups, ARRAY_SIZE(nand_data_groups) },
+ { "emmc_ctrl", emmc_ctrl_groups, ARRAY_SIZE(emmc_ctrl_groups) },
+ { "usb0_pwr", usb0_pwr_groups, ARRAY_SIZE(usb0_pwr_groups) },
+ { "usb1_pwr", usb1_pwr_groups, ARRAY_SIZE(usb1_pwr_groups) },
+};
+
+/*
+ * Groups code
+ */
+
+static const struct pinctrl_ops bcm4908_pinctrl_ops = {
+ .get_groups_count = pinctrl_generic_get_group_count,
+ .get_group_name = pinctrl_generic_get_group_name,
+ .get_group_pins = pinctrl_generic_get_group_pins,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
+ .dt_free_map = pinconf_generic_dt_free_map,
+};
+
+/*
+ * Functions code
+ */
+
+static int bcm4908_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,
+ unsigned int func_selector,
+ unsigned int group_selector)
+{
+ struct bcm4908_pinctrl *bcm4908_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+ const struct bcm4908_pinctrl_grp *group;
+ struct group_desc *group_desc;
+ int i;
+
+ group_desc = pinctrl_generic_get_group(pctrl_dev, group_selector);
+ if (!group_desc)
+ return -EINVAL;
+ group = group_desc->data;
+
+ mutex_lock(&bcm4908_pinctrl->mutex);
+ for (i = 0; i < group->num_pins; i++) {
+ u32 lsb = 0;
+
+ lsb |= group->pins[i].number;
+ lsb |= group->pins[i].function << BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT;
+
+ writel(0x0, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_MSB);
+ writel(lsb, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_LSB);
+ writel(BCM4908_TEST_PORT_CMD_LOAD_MUX_REG,
+ bcm4908_pinctrl->base + BCM4908_TEST_PORT_COMMAND);
+ }
+ mutex_unlock(&bcm4908_pinctrl->mutex);
+
+ return 0;
+}
+
+static const struct pinmux_ops bcm4908_pinctrl_pmxops = {
+ .get_functions_count = pinmux_generic_get_function_count,
+ .get_function_name = pinmux_generic_get_function_name,
+ .get_function_groups = pinmux_generic_get_function_groups,
+ .set_mux = bcm4908_pinctrl_set_mux,
+};
+
+/*
+ * Controller code
+ */
+
+static struct pinctrl_desc bcm4908_pinctrl_desc = {
+ .name = "bcm4908-pinctrl",
+ .pctlops = &bcm4908_pinctrl_ops,
+ .pmxops = &bcm4908_pinctrl_pmxops,
+};
+
+static const struct of_device_id bcm4908_pinctrl_of_match_table[] = {
+ { .compatible = "brcm,bcm4908-pinctrl", },
+ { }
+};
+
+static int bcm4908_pinctrl_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct bcm4908_pinctrl *bcm4908_pinctrl;
+ struct pinctrl_desc *pctldesc;
+ struct pinctrl_pin_desc *pins;
+ char **pin_names;
+ int i;
+
+ bcm4908_pinctrl = devm_kzalloc(dev, sizeof(*bcm4908_pinctrl), GFP_KERNEL);
+ if (!bcm4908_pinctrl)
+ return -ENOMEM;
+ pctldesc = &bcm4908_pinctrl->pctldesc;
+ platform_set_drvdata(pdev, bcm4908_pinctrl);
+
+ /* Set basic properties */
+
+ bcm4908_pinctrl->dev = dev;
+
+ bcm4908_pinctrl->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(bcm4908_pinctrl->base))
+ return PTR_ERR(bcm4908_pinctrl->base);
+
+ mutex_init(&bcm4908_pinctrl->mutex);
+
+ memcpy(pctldesc, &bcm4908_pinctrl_desc, sizeof(*pctldesc));
+
+ /* Set pinctrl properties */
+
+ pin_names = devm_kasprintf_strarray(dev, "pin", BCM4908_NUM_PINS);
+ if (IS_ERR(pin_names))
+ return PTR_ERR(pin_names);
+
+ pins = devm_kcalloc(dev, BCM4908_NUM_PINS, sizeof(*pins), GFP_KERNEL);
+ if (!pins)
+ return -ENOMEM;
+ for (i = 0; i < BCM4908_NUM_PINS; i++) {
+ pins[i].number = i;
+ pins[i].name = pin_names[i];
+ }
+ pctldesc->pins = pins;
+ pctldesc->npins = BCM4908_NUM_PINS;
+
+ /* Register */
+
+ bcm4908_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, bcm4908_pinctrl);
+ if (IS_ERR(bcm4908_pinctrl->pctldev))
+ return dev_err_probe(dev, PTR_ERR(bcm4908_pinctrl->pctldev),
+ "Failed to register pinctrl\n");
+
+ /* Groups */
+
+ for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_grps); i++) {
+ const struct bcm4908_pinctrl_grp *group = &bcm4908_pinctrl_grps[i];
+ int *pins;
+ int j;
+
+ pins = devm_kcalloc(dev, group->num_pins, sizeof(*pins), GFP_KERNEL);
+ if (!pins)
+ return -ENOMEM;
+ for (j = 0; j < group->num_pins; j++)
+ pins[j] = group->pins[j].number;
+
+ pinctrl_generic_add_group(bcm4908_pinctrl->pctldev, group->name,
+ pins, group->num_pins, (void *)group);
+ }
+
+ /* Functions */
+
+ for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_functions); i++) {
+ const struct bcm4908_pinctrl_function *function = &bcm4908_pinctrl_functions[i];
+
+ pinmux_generic_add_function(bcm4908_pinctrl->pctldev,
+ function->name,
+ function->groups,
+ function->num_groups, NULL);
+ }
+
+ return 0;
+}
+
+static struct platform_driver bcm4908_pinctrl_driver = {
+ .probe = bcm4908_pinctrl_probe,
+ .driver = {
+ .name = "bcm4908-pinctrl",
+ .of_match_table = bcm4908_pinctrl_of_match_table,
+ },
+};
+
+module_platform_driver(bcm4908_pinctrl_driver);
+
+MODULE_AUTHOR("Rafał Miłecki");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table);
--
2.31.1
^ permalink raw reply related
* Re: [PATCH v3 3/5] Documentation: DT bindings for HID over SPI.
From: Felipe Balbi @ 2022-01-24 10:32 UTC (permalink / raw)
To: Dmitry Antipov
Cc: Jiri Kosina, Benjamin Tissoires, Dmitry Torokhov, Rob Herring,
Mark Brown, linux-input, devicetree, linux-spi, Dmitry Antipov
In-Reply-To: <20220115023135.234667-4-dmanti@microsoft.com>
Dmitry Antipov <daantipov@gmail.com> writes:
> From: Dmitry Antipov <dmanti@microsoft.com>
>
> Added documentation describes the required properties for implementing
> Device Tree for a device supporting HID over SPI and also provides an
> example.
>
> Signed-off-by: Dmitry Antipov <dmanti@microsoft.com>
> ---
> .../bindings/input/hid-over-spi.txt | 43 +++++++++++++++++++
> 1 file changed, 43 insertions(+)
> create mode 100755 Documentation/devicetree/bindings/input/hid-over-spi.txt
>
> diff --git a/Documentation/devicetree/bindings/input/hid-over-spi.txt b/Documentation/devicetree/bindings/input/hid-over-spi.txt
> new file mode 100755
> index 000000000000..5eba95b5724e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/input/hid-over-spi.txt
> @@ -0,0 +1,43 @@
> +* HID over SPI Device-Tree bindings
> +
Some windows-style line endings leaked here. Perhaps run dos2unix on the file?
--
balbi
^ permalink raw reply
* Re: [PATCH v21 5/8] soc: mediatek: SVS: add debug commands
From: Roger Lu @ 2022-01-24 10:40 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger,
Enric Balletbo Serra, Kevin Hilman, Rob Herring, Nicolas Boichat,
Stephen Boyd, Philipp Zabel
Cc: Fan Chen, HenryC Chen, YT Lee, Xiaoqing Liu, Charles Yang,
Angus Lin, Mark Rutland, Nishanth Menon, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, linux-pm,
Project_Global_Chrome_Upstream_Group, Guenter Roeck
In-Reply-To: <47bcbffc-42f6-335e-dfab-990e0ab5f103@collabora.com>
Hi AngeloGioacchino,
Sorry for the late reply and thanks for the advice.
On Fri, 2022-01-07 at 15:34 +0100, AngeloGioacchino Del Regno wrote:
> Il 07/01/22 10:51, Roger Lu ha scritto:
> > The purpose of SVS is to help find the suitable voltages
> > for DVFS. Therefore, if SVS bank voltages are concerned
> > to be wrong, we can adjust SVS bank voltages by this patch.
> >
> > Signed-off-by: Roger Lu <roger.lu@mediatek.com>
> > ---
> > drivers/soc/mediatek/mtk-svs.c | 321 ++++++++++++++++++++++++++++++++-
> > 1 file changed, 318 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c
> > index 042c6e8e9069..93cdaecadd6d 100644
> > --- a/drivers/soc/mediatek/mtk-svs.c
> > +++ b/drivers/soc/mediatek/mtk-svs.c
>
> ..snip..
>
> > @@ -605,6 +896,16 @@ static void svs_set_bank_phase(struct svs_platform
> > *svsp,
> > }
> > }
> >
> > +static inline void svs_save_bank_register_data(struct svs_platform *svsp,
> > + enum svsb_phase phase)
> > +{
> > + struct svs_bank *svsb = svsp->pbank;
> > + enum svs_reg_index rg_i;
> > +
>
> I think that it'd be a good idea to add an `enable` parameter, so that we
> don't always do a register dump; after all, this is a debugging feature and
> it's going to be completely irrelevant to the user, so keeping this disabled
> by default would ensure to get no performance degradation (even if small)
> unless really wanted.
>
> So, in this case, here we'd have
>
> if (!svsp->debug_enabled)
> return;
Thanks for pointing out the concern. Excuse us, we really need this to be
enabled by default. If we add a enable flag here, we'll face below problems and
make debug more difficult.
1. If we enable it afterward by cmd, init0[1~2] registers' data cannot be
recorded expectedly because the init flow has been finished already and won't be
run anymore. So, it doesn't work by using cmd to enable the flag.
2. If we add a enable flag here, it means we have to re-build the kernel load in
order to enable this flag. However, we cannot re-build the kernel load and needs
to debug directly sometimes. It's a sad situation... :(
>
> > + for (rg_i = DESCHAR; rg_i < SVS_REG_MAX; rg_i++)
> > + svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i);
> > +}
> > +
>
> Of course, this implies adding a new debugfs entry to enable/disable the
> debugging.
> Everything else looks good :)
Oh, excuse us, we have to keep the old design for better instant support and
thanks for the understanding.
> > static inline void svs_error_isr_handler(struct svs_platform *svsp)
> > {
> > struct svs_bank *svsb = svsp->pbank;
> > @@ -619,6 +920,8 @@ static inline void svs_error_isr_handler(struct
> > svs_platform *svsp)
> > svs_readl_relaxed(svsp, SMSTATE1));
> > dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP));
> >
> > + svs_save_bank_register_data(svsp, SVSB_PHASE_ERROR);
> > +
> > svsb->mode_support = SVSB_MODE_ALL_DISABLE;
> > svsb->phase = SVSB_PHASE_ERROR;
[snip]
^ permalink raw reply
* Re: [PATCH v21 7/8] arm64: dts: mt8192: add svs device information
From: Roger Lu @ 2022-01-24 10:48 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger,
Enric Balletbo Serra, Kevin Hilman, Rob Herring, Nicolas Boichat,
Stephen Boyd, Philipp Zabel
Cc: Fan Chen, HenryC Chen, Xiaoqing Liu, Charles Yang, Angus Lin,
Mark Rutland, Nishanth Menon, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel, linux-pm,
Project_Global_Chrome_Upstream_Group, Guenter Roeck
In-Reply-To: <010f9b6a-d6bf-b27a-cb2d-c5fd181c3ac7@collabora.com>
Hi AngeloGioacchino,
On Fri, 2022-01-07 at 15:33 +0100, AngeloGioacchino Del Regno wrote:
> Il 07/01/22 10:51, Roger Lu ha scritto:
> > Add compitable/reg/irq/clock/efuse/reset setting in svs node.
>
> Typo: compitable => compatible
> .. also, you're not only adding the svs node, but also efuse: please add that
> information in the commit description.
>
> >
> > Signed-off-by: Roger Lu <roger.lu@mediatek.com>
>
> This patch seems to not apply on top of the current linux-next, can you please
> rebase it? That would resolve issues with this series and would be picked
> sooner.
>
> Apart from that...
Sorry to make you confuse. After having discussion internally, we'll submit
another complete mt8192.dtsi patch including this svs node. Therefore, I'll drop
this path from svs patchset in order not to make the reviewer confuse. Thanks
for the comments a lot.
>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 39 ++++++++++++++++++++++++
> > 1 file changed, 39 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index c7c7d4e017ae..c111e26489dd 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -9,6 +9,8 @@
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include <dt-bindings/interrupt-controller/irq.h>
> > #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > +#include <dt-bindings/reset/ti-syscon.h>
> > +
> >
> > / {
> > compatible = "mediatek,mt8192";
> > @@ -268,6 +270,14 @@
> > compatible = "mediatek,mt8192-infracfg", "syscon";
> > reg = <0 0x10001000 0 0x1000>;
> > #clock-cells = <1>;
> > +
> > + infracfg_rst: reset-controller {
> > + compatible = "mediatek,infra-reset", "ti,syscon-
> > reset";
> > + #reset-cells = <1>;
> > + ti,reset-bits = <
> > + 0x150 5 0x154 5 0 0 (ASSERT_SET |
> > DEASSERT_SET | STATUS_NONE) /* 0: svs */
> > + >;
> > + };
> > };
> >
> > pericfg: syscon@10003000 {
> > @@ -362,6 +372,20 @@
> > status = "disabled";
> > };
> >
> > + svs: svs@1100b000 {
> > + compatible = "mediatek,mt8192-svs";
> > + reg = <0 0x1100b000 0 0x1000>;
> > + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&infracfg CLK_INFRA_THERM>;
> > + clock-names = "main";
> > + nvmem-cells = <&svs_calibration>,
> > + <&lvts_e_data1>;
> > + nvmem-cell-names = "svs-calibration-data",
> > + "t-calibration-data";
> > + resets = <&infracfg_rst 0>;
> > + reset-names = "svs_rst";
> > + };
> > +
> > spi1: spi@11010000 {
> > compatible = "mediatek,mt8192-spi",
> > "mediatek,mt6765-spi";
> > @@ -479,6 +503,21 @@
> > #clock-cells = <1>;
> > };
> >
> > + efuse: efuse@11c10000 {
> > + compatible = "mediatek,efuse";
> > + reg = <0 0x11c10000 0 0x1000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + lvts_e_data1: data1@1c0 {
> > + reg = <0x1c0 0x58>;
> > + };
> > +
> > + svs_calibration: calib@580 {
> > + reg = <0x580 0x68>;
> > + };
> > + };
> > +
> > i2c3: i2c3@11cb0000 {
> > compatible = "mediatek,mt8192-i2c";
> > reg = <0 0x11cb0000 0 0x1000>,
> >
>
>
^ permalink raw reply
* Re: Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Bananapi R2 Pro
From: Sascha Hauer @ 2022-01-24 11:03 UTC (permalink / raw)
To: Frank Wunderlich
Cc: Frank Wunderlich, linux-rockchip, Rob Herring, Heiko Stuebner,
Peter Geis, Johan Jonker, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <trinity-2e9cf5db-4c9b-4ad7-b684-74541e639edf-1643014505272@3c-app-gmx-bs10>
On Mon, Jan 24, 2022 at 09:55:05AM +0100, Frank Wunderlich wrote:
> Hi
>
> > Gesendet: Montag, 24. Januar 2022 um 09:31 Uhr
> > Von: "Sascha Hauer" <sha@pengutronix.de>
> > An: "Frank Wunderlich" <linux@fw-web.de>
> > Cc: linux-rockchip@lists.infradead.org, "Frank Wunderlich" <frank-w@public-files.de>, "Rob Herring" <robh+dt@kernel.org>, "Heiko Stuebner" <heiko@sntech.de>, "Peter Geis" <pgwipeout@gmail.com>, "Johan Jonker" <jbx6244@gmail.com>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
> > Betreff: Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Bananapi R2 Pro
> >
> > On Sun, Jan 23, 2022 at 02:51:16PM +0100, Frank Wunderlich wrote:
> > > From: Frank Wunderlich <frank-w@public-files.de>
> > >
> > > This patch adds Devicetree for Bananapi R2 Pro based on RK3568.
> > > Add uart/sd/emmc/i2c/rk809/tsadc nodes for basic function.
> > > Gmac0 is directly connected to wan-port so usable without additional
> > > driver.
> > > On gmac1 there is a switch (rtl8367rb) connected which have not yet a
> > > driver in mainline.
> > >
> > > Patch also prepares nodes for GPIO header.
> > >
> > > Co-developed-by: Peter Geis <pgwipeout@gmail.com>
> > > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> > > ---
> > > +&gmac0 {
> > > + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
> > > + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
> > > + clock_in_out = "input";
> > > + phy-handle = <&rgmii_phy0>;
> > > + phy-mode = "rgmii";
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&gmac0_miim
> > > + &gmac0_tx_bus2
> > > + &gmac0_rx_bus2
> > > + &gmac0_rgmii_clk
> > > + &gmac0_rgmii_bus>;
> > > +
> > > + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
> > > + snps,reset-active-low;
> > > + /* Reset time is 20ms, 100ms for rtl8211f */
> >
> > Is this really a rtl8211f? I don't know and it could indeed be a
> > rtl8211f, I'm just asking because the comment is copy pasted from
> > the Quartz64 board.
>
> i know thats a RTL8211 phy, but i see no additional letter on the
> chip, based on shematics it's a RTL8211F-CG
Ok. I just wanted to make sure you checked that.
>
> > > + snps,reset-delays-us = <0 20000 100000>;
> > > +
> > > +&mdio0 {
> > > + rgmii_phy0: ethernet-phy@0 {
> > > + compatible = "ethernet-phy-ieee802.3-c22";
> > > + reg = <0x0>;
> > > + };
> >
> > 0 is the broadcast address. I'm not sure if it's a good idea to use it.
> > There should be another address the phy listens on.
>
> took this from the 3568-EVB (like the most parts, as the board is
> mostly the same), and in linux it's the same and working. The switch
> have also phy-id 0 on mdio bus #1, are you sure this is invalid?
It's not invalid, it's just the broadcast address to which other phys
might answer as well. Anyway, as long as there's only a single phy on
the bus it's probably okay.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* Re: [PATCH] arm64: dts: rockchip: fix rk3399-puma eMMC HS400 signal integrity
From: Quentin Schulz @ 2022-01-24 11:17 UTC (permalink / raw)
To: Peter Geis
Cc: Rob Herring, Heiko Stuebner, devicetree, arm-mail-list,
open list:ARM/Rockchip SoC..., Linux Kernel Mailing List,
Jakob Unterwurzacher, Quentin Schulz
In-Reply-To: <CAMdYzYpT8BUrukUozRSQDHgiQHMPbS5GtV7huL4xFFRsdxw0qQ@mail.gmail.com>
Hi Peter,
On 1/20/22 18:14, Peter Geis wrote:
> On Thu, Jan 20, 2022 at 11:03 AM Quentin Schulz
> <quentin.schulz@theobroma-systems.com> wrote:
>>
>> Hi Peter,
>>
>> On 1/20/22 16:06, Peter Geis wrote:
>>> On Wed, Jan 19, 2022 at 8:52 AM <quentin.schulz@theobroma-systems.com> wrote:
>>>>
>>>> From: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
>>>>
>>>> There are signal integrity issues running the eMMC at 200MHz on Puma
>>>> RK3399-Q7.
>>>>
>>>> Similar to the work-around found for RK3399 Gru boards, lowering the
>>>> frequency to 100MHz made the eMMC much more stable, so let's lower the
>>>> frequency to 100MHz.
>>>>
>>>> It might be possible to run at 150MHz as on RK3399 Gru boards but only
>>>> 100MHz was extensively tested.
>>>>
>>>> Cc: Quentin Schulz <foss+kernel@0leil.net>
>>>> Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
>>>> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
>>>> ---
>>>>
>>>> Note/RFC: as opposed to gru DTSI, max-frequency is used here instead of
>>>> assigned-clock-rates.
>>>>
>>>> AFAIU, max-frequency applies to the SD bus rate, while
>>>> assigned-clock-rates applies to the clock fed to the SD host controller
>>>> inside the SoC. max-frequency does not interact with the clock subsystem
>>>> AFAICT. assigned-clock-rates sets the clock rate at probe, regardless of
>>>> eMMC tuning.
>>>> Technically, the Arasan SDHC IP supports silicon-hardcoded clock
>>>> multiplier so I think setting assigned-clock-rates as a way of rate
>>>> limiting the eMMC block is incorrect and max-frequency should be used
>>>> instead (as done in this patch). Otherwise the SDHC could still potentially
>>>> derive a 200MHz clock from a lower rate clock thanks to its multiplier.
>>>>
>>>> arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 6 ++++++
>>>> 1 file changed, 6 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
>>>> index fb67db4619ea..a6108578aae0 100644
>>>> --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
>>>> +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
>>>> @@ -425,6 +425,12 @@ vcc5v0_host_en: vcc5v0-host-en {
>>>> };
>>>>
>>>> &sdhci {
>>>> + /*
>>>> + * Signal integrity isn't great at 200MHz but 100MHz has proven stable
>>>> + * enough.
>>>> + */
>>>> + max-frequency = <100000000>;
>>>> +
>>>> bus-width = <8>;
>>>> mmc-hs400-1_8v;
>>>> mmc-hs400-enhanced-strobe;
>>>
>>> I don't have these boards nor the schematics handy for them, but
>>> wouldn't it be better to simply switch to mmc-hs200-1_8v?
>>
>> Thanks for the suggestion, I just tested, by removing mmc-hs400-1_8v;
>> and mmc-hs400-enhanced-strobe; but keeping the clock rate at 200MHz and
>> adding mmc-hs200-1_8v; failed a basic dd test.
>
> Quite understandable.
> I more meant it may permit you to reach a higher clock rate than
> 100mhz and thus possibly a higher data rate, for example perhaps
> 150mhz would be reachable.
> For example I would do a bandwidth test for hs400-es at 100mhz, then
> test at hs200 and find the maximum stable clock rate.
> If 200mhz is stable enough to probe and /sys/kernel/debug/mmc<x>/ios
> shows you are in 8bit hs200, you can adjust the clock rate through
> /sys/kernel/debug/mmc<x>/clock without needing to reboot.
> It will speed up testing.
>
> If hs200 permits a higher overall data rate than hs400-es, it would be
> worth making that switch.
>
Got the HW dept to look into this and they said that since the main
difference between HS200 and HS400-ES is that for the same clock rate,
twice the data rate is possible and that the signal integrity issue we
have is on the clock line, anything that impacts HS400-ES wrt clock rate
will impact HS200 too. Therefore HS200 should practically be half data
rate on our board and no improvement should be observed.
Lemme know if there's something we misunderstood or check more thoroughly.
Thanks!
Quentin
> Always,
> Peter
>
>>
>> Cheers,
>> Quentin
>>
>>> Other rk3399 boards don't have issues with hs200 at full 200mhz, and
>>> as I understand it hs400-es exhibits stability issues on most rk3399
>>> boards.
>>>
>>> Feel free to disregard my comments if you've already tested this.
>>>
>>>> --
>>>> 2.34.1
>>>>
>>>>
>>>> _______________________________________________
>>>> Linux-rockchip mailing list
>>>> Linux-rockchip@lists.infradead.org
>>>> https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_mailman_listinfo_linux-2Drockchip&d=DwIBaQ&c=_sEr5x9kUWhuk4_nFwjJtA&r=LYjLexDn7rXIzVmkNPvw5ymA1XTSqHGq8yBP6m6qZZ4njZguQhZhkI_-172IIy1t&m=OTusi9XARCbef1Ba5t1gv4_LqRkOaxFY3UtvYky6NVLpeiziqqmdOJ8-R5WXWFNr&s=xBnqhBu20rxvu_V-5EhXyA_yNxcJpa4Dq6HO2Ow3Gk8&e=
^ permalink raw reply
* [PATCH v3 0/4] Add I2C and PWM support for T234
From: Akhil R @ 2022-01-24 11:18 UTC (permalink / raw)
To: devicetree, digetx, jonathanh, ldewangan, linux-i2c, linux-kernel,
linux-tegra, mperttunen, robh+dt, thierry.reding
Cc: akhilrajeev
The patchset contains driver and devicetree changes to support I2C and
PWM for Tegra234
v2->v3:
* Sorted clock and reset based on ID
v1->v2:
* Reverted changes in i2c-tegra.c. using tegra194_i2c_hw for tegra234
as the values are compatible.
Akhil R (4):
dt-bindings: Add headers for Tegra234 I2C
arm64: tegra: Add Tegra234 I2C devicetree nodes
dt-bindings: Add headers for Tegra234 PWM
arm64: tegra: Add Tegra234 PWM devicetree nodes
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 133 +++++++++++++++++++++++++++++
include/dt-bindings/clock/tegra234-clock.h | 35 +++++++-
include/dt-bindings/reset/tegra234-reset.h | 16 ++++
3 files changed, 183 insertions(+), 1 deletion(-)
--
2.7.4
^ permalink raw reply
* [PATCH v3 2/4] arm64: tegra: Add Tegra234 I2C devicetree nodes
From: Akhil R @ 2022-01-24 11:18 UTC (permalink / raw)
To: devicetree, digetx, jonathanh, ldewangan, linux-i2c, linux-kernel,
linux-tegra, mperttunen, robh+dt, thierry.reding
Cc: akhilrajeev
In-Reply-To: <1643023097-5221-1-git-send-email-akhilrajeev@nvidia.com>
Add device tree nodes for Tegra234 I2C controllers
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 121 +++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 6b6f1580..c686827 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -144,6 +144,96 @@
status = "disabled";
};
+ gen1_i2c: i2c@3160000 {
+ compatible = "nvidia,tegra194-i2c";
+ reg = <0x3160000 0x100>;
+ status = "disabled";
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <400000>;
+ clocks = <&bpmp TEGRA234_CLK_I2C1
+ &bpmp TEGRA234_CLK_PLLP_OUT0>;
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ clock-names = "div-clk", "parent";
+ resets = <&bpmp TEGRA234_RESET_I2C1>;
+ reset-names = "i2c";
+ };
+
+ cam_i2c: i2c@3180000 {
+ compatible = "nvidia,tegra194-i2c";
+ reg = <0x3180000 0x100>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clock-frequency = <400000>;
+ clocks = <&bpmp TEGRA234_CLK_I2C3
+ &bpmp TEGRA234_CLK_PLLP_OUT0>;
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ clock-names = "div-clk", "parent";
+ resets = <&bpmp TEGRA234_RESET_I2C3>;
+ reset-names = "i2c";
+ };
+
+ dp_aux_ch1_i2c: i2c@3190000 {
+ compatible = "nvidia,tegra194-i2c";
+ reg = <0x3190000 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clock-frequency = <100000>;
+ clocks = <&bpmp TEGRA234_CLK_I2C4
+ &bpmp TEGRA234_CLK_PLLP_OUT0>;
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ clock-names = "div-clk", "parent";
+ resets = <&bpmp TEGRA234_RESET_I2C4>;
+ reset-names = "i2c";
+ };
+
+ dp_aux_ch0_i2c: i2c@31b0000 {
+ compatible = "nvidia,tegra194-i2c";
+ reg = <0x31b0000 0x100>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clock-frequency = <100000>;
+ clocks = <&bpmp TEGRA234_CLK_I2C6
+ &bpmp TEGRA234_CLK_PLLP_OUT0>;
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ clock-names = "div-clk", "parent";
+ resets = <&bpmp TEGRA234_RESET_I2C6>;
+ reset-names = "i2c";
+ };
+
+ dp_aux_ch2_i2c: i2c@31c0000 {
+ compatible = "nvidia,tegra194-i2c";
+ reg = <0x31c0000 0x100>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clock-frequency = <100000>;
+ clocks = <&bpmp TEGRA234_CLK_I2C7
+ &bpmp TEGRA234_CLK_PLLP_OUT0>;
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ clock-names = "div-clk", "parent";
+ resets = <&bpmp TEGRA234_RESET_I2C7>;
+ reset-names = "i2c";
+ };
+
+ dp_aux_ch3_i2c: i2c@31e0000 {
+ compatible = "nvidia,tegra194-i2c";
+ reg = <0x31e0000 0x100>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clock-frequency = <100000>;
+ clocks = <&bpmp TEGRA234_CLK_I2C9
+ &bpmp TEGRA234_CLK_PLLP_OUT0>;
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ clock-names = "div-clk", "parent";
+ resets = <&bpmp TEGRA234_RESET_I2C9>;
+ reset-names = "i2c";
+ };
+
mmc@3460000 {
compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
reg = <0x03460000 0x20000>;
@@ -212,6 +302,37 @@
#mbox-cells = <2>;
};
+ gen2_i2c: i2c@c240000 {
+ compatible = "nvidia,tegra194-i2c";
+ reg = <0xc240000 0x100>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clock-frequency = <100000>;
+ clocks = <&bpmp TEGRA234_CLK_I2C2
+ &bpmp TEGRA234_CLK_PLLP_OUT0>;
+ clock-names = "div-clk", "parent";
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ resets = <&bpmp TEGRA234_RESET_I2C2>;
+ reset-names = "i2c";
+ };
+
+ gen8_i2c: i2c@c250000 {
+ compatible = "nvidia,tegra194-i2c";
+ reg = <0xc250000 0x100>;
+ nvidia,hw-instance-id = <0x7>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clock-frequency = <400000>;
+ clocks = <&bpmp TEGRA234_CLK_I2C8
+ &bpmp TEGRA234_CLK_PLLP_OUT0>;
+ clock-names = "div-clk", "parent";
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ resets = <&bpmp TEGRA234_RESET_I2C8>;
+ reset-names = "i2c";
+ };
+
rtc@c2a0000 {
compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
reg = <0x0c2a0000 0x10000>;
--
2.7.4
^ permalink raw reply related
* [PATCH v3 3/4] dt-bindings: Add headers for Tegra234 PWM
From: Akhil R @ 2022-01-24 11:18 UTC (permalink / raw)
To: devicetree, digetx, jonathanh, ldewangan, linux-i2c, linux-kernel,
linux-tegra, mperttunen, robh+dt, thierry.reding
Cc: akhilrajeev
In-Reply-To: <1643023097-5221-1-git-send-email-akhilrajeev@nvidia.com>
Add dt-bindings header files for PWM of Tegra234
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
include/dt-bindings/clock/tegra234-clock.h | 16 ++++++++++++++++
include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++
2 files changed, 24 insertions(+)
diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
index dc524e6..2529e7e 100644
--- a/include/dt-bindings/clock/tegra234-clock.h
+++ b/include/dt-bindings/clock/tegra234-clock.h
@@ -38,6 +38,22 @@
#define TEGRA234_CLK_I2C9 55U
/** @brief PLLP clk output */
#define TEGRA234_CLK_PLLP_OUT0 102U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
+#define TEGRA234_CLK_PWM1 105U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
+#define TEGRA234_CLK_PWM2 106U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
+#define TEGRA234_CLK_PWM3 107U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
+#define TEGRA234_CLK_PWM4 108U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
+#define TEGRA234_CLK_PWM5 109U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
+#define TEGRA234_CLK_PWM6 110U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
+#define TEGRA234_CLK_PWM7 111U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
+#define TEGRA234_CLK_PWM8 112U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
#define TEGRA234_CLK_SDMMC4 123U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h
index 2963259..ba390b8 100644
--- a/include/dt-bindings/reset/tegra234-reset.h
+++ b/include/dt-bindings/reset/tegra234-reset.h
@@ -18,6 +18,14 @@
#define TEGRA234_RESET_I2C7 33U
#define TEGRA234_RESET_I2C8 34U
#define TEGRA234_RESET_I2C9 35U
+#define TEGRA234_RESET_PWM1 68U
+#define TEGRA234_RESET_PWM2 69U
+#define TEGRA234_RESET_PWM3 70U
+#define TEGRA234_RESET_PWM4 71U
+#define TEGRA234_RESET_PWM5 72U
+#define TEGRA234_RESET_PWM6 73U
+#define TEGRA234_RESET_PWM7 74U
+#define TEGRA234_RESET_PWM8 75U
#define TEGRA234_RESET_SDMMC4 85U
#define TEGRA234_RESET_UARTA 100U
--
2.7.4
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox