* [PATCH 2/6] ASoC: dt-bindings: samsung,arndale: convert to dtschema
From: Krzysztof Kozlowski @ 2022-01-24 17:03 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Sylwester Nawrocki, Jonathan Bakker, alsa-devel, devicetree,
linux-kernel
In-Reply-To: <20220124170336.164320-1-krzysztof.kozlowski@canonical.com>
Convert the audio complex on Arndale boards with Samsung Exynos SoC to
DT schema format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../devicetree/bindings/sound/arndale.txt | 25 -----------
.../bindings/sound/samsung,arndale.yaml | 44 +++++++++++++++++++
2 files changed, 44 insertions(+), 25 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/arndale.txt
create mode 100644 Documentation/devicetree/bindings/sound/samsung,arndale.yaml
diff --git a/Documentation/devicetree/bindings/sound/arndale.txt b/Documentation/devicetree/bindings/sound/arndale.txt
deleted file mode 100644
index 17530120ccfc..000000000000
--- a/Documentation/devicetree/bindings/sound/arndale.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Audio Binding for Arndale boards
-
-Required properties:
-- compatible : Can be one of the following:
- "samsung,arndale-rt5631",
- "samsung,arndale-wm1811"
-
-- samsung,audio-cpu: The phandle of the Samsung I2S controller
-- samsung,audio-codec: The phandle of the audio codec
-
-Optional:
-- samsung,model: The name of the sound-card
-
-Arndale Boards has many audio daughter cards, one of them is
-rt5631/alc5631. Below example shows audio bindings for rt5631/
-alc5631 based codec.
-
-Example:
-
-sound {
- compatible = "samsung,arndale-rt5631";
-
- samsung,audio-cpu = <&i2s0>
- samsung,audio-codec = <&rt5631>;
-};
diff --git a/Documentation/devicetree/bindings/sound/samsung,arndale.yaml b/Documentation/devicetree/bindings/sound/samsung,arndale.yaml
new file mode 100644
index 000000000000..e7dc65637f02
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/samsung,arndale.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/samsung,arndale.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Insignal Arndale boards audio complex
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+
+properties:
+ compatible:
+ enum:
+ - samsung,arndale-rt5631
+ - samsung,arndale-wm1811
+
+ samsung,audio-codec:
+ description: Phandle to the audio codec.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ samsung,audio-cpu:
+ description: Phandle to the Samsung I2S controller.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ samsung,model:
+ description: The user-visible name of this sound complex.
+ $ref: /schemas/types.yaml#/definitions/string
+
+required:
+ - compatible
+ - samsung,audio-codec
+ - samsung,audio-cpu
+
+additionalProperties: false
+
+examples:
+ - |
+ sound {
+ compatible = "samsung,arndale-rt5631";
+ samsung,audio-cpu = <&i2s0>;
+ samsung,audio-codec = <&rt5631>;
+ };
--
2.32.0
^ permalink raw reply related
* [PATCH 4/6] ASoC: dt-bindings: samsung,smdk5250: convert to dtschema
From: Krzysztof Kozlowski @ 2022-01-24 17:03 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Sylwester Nawrocki, Jonathan Bakker, alsa-devel, devicetree,
linux-kernel
In-Reply-To: <20220124170336.164320-1-krzysztof.kozlowski@canonical.com>
Convert the audio complex on SMDK5250 boards with Samsung Exynos SoC to
DT schema format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/sound/samsung,smdk-wm8994.txt | 14 -------
.../bindings/sound/samsung,smdk5250.yaml | 38 +++++++++++++++++++
2 files changed, 38 insertions(+), 14 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/samsung,smdk-wm8994.txt
create mode 100644 Documentation/devicetree/bindings/sound/samsung,smdk5250.yaml
diff --git a/Documentation/devicetree/bindings/sound/samsung,smdk-wm8994.txt b/Documentation/devicetree/bindings/sound/samsung,smdk-wm8994.txt
deleted file mode 100644
index 4686646fb122..000000000000
--- a/Documentation/devicetree/bindings/sound/samsung,smdk-wm8994.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-Samsung SMDK audio complex
-
-Required properties:
-- compatible : "samsung,smdk-wm8994"
-- samsung,i2s-controller: The phandle of the Samsung I2S0 controller
-- samsung,audio-codec: The phandle of the WM8994 audio codec
-Example:
-
-sound {
- compatible = "samsung,smdk-wm8994";
-
- samsung,i2s-controller = <&i2s0>;
- samsung,audio-codec = <&wm8994>;
-};
diff --git a/Documentation/devicetree/bindings/sound/samsung,smdk5250.yaml b/Documentation/devicetree/bindings/sound/samsung,smdk5250.yaml
new file mode 100644
index 000000000000..cb51af90435e
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/samsung,smdk5250.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/samsung,smdk5250.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SMDK5250 audio complex with WM8994 codec
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+
+properties:
+ compatible:
+ const: samsung,smdk-wm8994
+
+ samsung,audio-codec:
+ description: Phandle to the audio codec.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ samsung,i2s-controller:
+ description: Phandle to the Samsung I2S controller.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+required:
+ - compatible
+ - samsung,audio-codec
+ - samsung,i2s-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ sound {
+ compatible = "samsung,smdk-wm8994";
+ samsung,i2s-controller = <&i2s0>;
+ samsung,audio-codec = <&wm8994>;
+ };
--
2.32.0
^ permalink raw reply related
* [RFC 5/6] ASoC: dt-bindings: samsung,snow: convert to dtschema
From: Krzysztof Kozlowski @ 2022-01-24 17:03 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Sylwester Nawrocki, Jonathan Bakker, alsa-devel, devicetree,
linux-kernel
In-Reply-To: <20220124170336.164320-1-krzysztof.kozlowski@canonical.com>
Convert the audio complex on Google Snow boards with Samsung Exynos SoC
to DT schema format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
TODO: The DTS do not pass cleanly. cpu/sound-dai should be fixed.
---
.../bindings/sound/samsung,snow.yaml | 78 +++++++++++++++++++
.../devicetree/bindings/sound/snow.txt | 31 --------
2 files changed, 78 insertions(+), 31 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/samsung,snow.yaml
delete mode 100644 Documentation/devicetree/bindings/sound/snow.txt
diff --git a/Documentation/devicetree/bindings/sound/samsung,snow.yaml b/Documentation/devicetree/bindings/sound/samsung,snow.yaml
new file mode 100644
index 000000000000..df969b384839
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/samsung,snow.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/samsung,snow.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google Snow audio complex with MAX9809x codec
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+
+properties:
+ compatible:
+ enum:
+ - google,snow-audio-max98090
+ - google,snow-audio-max98091
+ - google,snow-audio-max98095
+
+ codec:
+ type: object
+ properties:
+ sound-dai:
+ description: List of phandles to the CODEC and HDMI IP nodes.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - description: Phandle to the MAX98090, MAX98091 or MAX98095 CODEC.
+ - description: Phandle to the HDMI IP block node.
+ required:
+ - sound-dai
+
+ cpu:
+ type: object
+ properties:
+ sound-dai:
+ description: Phandle to the Samsung I2S controller.
+ $ref: /schemas/types.yaml#/definitions/phandle
+ items:
+ - description: Phandle of the I2S controller.
+ - description: Index of the I2S controller.
+ required:
+ - sound-dai
+
+ samsung,audio-codec:
+ description: Phandle to the audio codec.
+ $ref: /schemas/types.yaml#/definitions/phandle
+ deprecated: true
+
+ samsung,i2s-controller:
+ description: Phandle to the Samsung I2S controller.
+ $ref: /schemas/types.yaml#/definitions/phandle
+ deprecated: true
+
+ samsung,model:
+ description: The user-visible name of this sound complex.
+ $ref: /schemas/types.yaml#/definitions/string
+
+required:
+ - compatible
+ - codec
+ - cpu
+
+additionalProperties: false
+
+examples:
+ - |
+ sound {
+ compatible = "google,snow-audio-max98095";
+ samsung,model = "Snow-I2S-MAX98095";
+
+ cpu {
+ sound-dai = <&i2s0 0>;
+ };
+
+ codec {
+ sound-dai = <&max98095 0>, <&hdmi>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/sound/snow.txt b/Documentation/devicetree/bindings/sound/snow.txt
deleted file mode 100644
index 80fd9a87bb3f..000000000000
--- a/Documentation/devicetree/bindings/sound/snow.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-Audio Binding for Snow boards
-
-Required properties:
-- compatible : Can be one of the following,
- "google,snow-audio-max98090" or
- "google,snow-audio-max98091" or
- "google,snow-audio-max98095"
-- samsung,i2s-controller (deprecated): The phandle of the Samsung I2S controller
-- samsung,audio-codec (deprecated): The phandle of the audio codec
-
-Required sub-nodes:
-
- - 'cpu' subnode with a 'sound-dai' property containing the phandle of the I2S
- controller
- - 'codec' subnode with a 'sound-dai' property containing list of phandles
- to the CODEC nodes, first entry must be the phandle of the MAX98090,
- MAX98091 or MAX98095 CODEC (exact device type is indicated by the compatible
- string) and the second entry must be the phandle of the HDMI IP block node
-
-Optional:
-- samsung,model: The name of the sound-card
-
-Example:
-
-sound {
- compatible = "google,snow-audio-max98095";
-
- samsung,model = "Snow-I2S-MAX98095";
- samsung,i2s-controller = <&i2s0>;
- samsung,audio-codec = <&max98095>;
-};
--
2.32.0
^ permalink raw reply related
* Re: [PATCH 1/3] dt-bindings: display: add bindings for MIPI DBI compatible SPI panels
From: Noralf Trønnes @ 2022-01-24 17:04 UTC (permalink / raw)
To: Rob Herring
Cc: maxime, thierry.reding, sam, dave.stevenson, david, devicetree,
dri-devel
In-Reply-To: <CAL_JsqLiw42zfaRPmszs2bmGbAcL5STSTVUtP0PyWnm=CaG8ug@mail.gmail.com>
Den 24.01.2022 17.42, skrev Rob Herring:
> On Mon, Jan 24, 2022 at 10:28 AM Noralf Trønnes <noralf@tronnes.org> wrote:
>>
>>
>>
>> Den 24.01.2022 17.08, skrev Rob Herring:
>>> On Sun, Jan 23, 2022 at 11:25 AM Noralf Trønnes <noralf@tronnes.org> wrote:
>>>>
>>>> Add binding for MIPI DBI compatible SPI panels.
>>>
>>> I'm sure we already have MIPI DBI panels. What's this for?
>>>
>>
>> It aims to use one driver to cover all MIPI DBI panels where the
>> controller setup is loaded from userspace in a firmware file.
>
> What's the solution when the user wants a splash screen in the
> bootloader and also wants multiple panels supported?
>
In that case the bootloader needs builtin support for the screen. The OS
driver can then detect that the controller is configured and just skip
the configure stage. I have yet to see someone implement suppport for
such a SPI panel in a bootloader though.
> Also, 1 driver doesn't dictate 1 compatible. A one to many
> relationship is fine and makes the decision entirely the OS's.
>
>> The cover
>> letter points to the discussion where Maxime proposed this:
>>
>> https://lore.kernel.org/dri-devel/20211129093946.xhp22mvdut3m67sc@houat/
>
> The proposal there is:
>
>> compatible = "panel-spi";
>> model = "panel-from-random-place-42";
>
> The same thing can be accomplished with this:
>
> compatible = "panel-from-random-place-42", "panel-spi";
>
> What's the advantage of hijacking 'model'?
>
That's what Maxime proposed, but having it in the compatible like this
is even better. I suppose it's ok for the driver to use the compatible
to load the firmware file?
Noralf.
^ permalink raw reply
* Re: [PATCH v4 2/2] arm64: dts: imx8mm: Add support for emtrion emCON-MX8M Mini
From: Fabio Estevam @ 2022-01-24 17:05 UTC (permalink / raw)
To: Mueller, Reinhold
Cc: Rob Herring, Sascha Hauer, Sascha Hauer, Shawn Guo,
NXP Linux Team,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel
In-Reply-To: <e6adf5d9473e417d85a1845b007a4ee1@emtrion.de>
Hi Reinhold,
On Tue, Dec 21, 2021 at 4:33 AM Mueller, Reinhold
<Reinhold.Mueller@emtrion.de> wrote:
> Yes, of course the emCON provides a connector connecting two slaves on the spi bus.
In this case, then please pass gpio5 13 to the cs-gpios property too.
^ permalink raw reply
* [PATCH 6/6] ASoC: dt-bindings: samsung,tm2: convert to dtschema
From: Krzysztof Kozlowski @ 2022-01-24 17:03 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Sylwester Nawrocki, Jonathan Bakker, alsa-devel, devicetree,
linux-kernel
In-Reply-To: <20220124170336.164320-1-krzysztof.kozlowski@canonical.com>
Convert the audio complex on Samsung TM2 boards with Samsung Exynos SoC
to DT schema format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/sound/samsung,tm2-audio.txt | 42 ----------
.../bindings/sound/samsung,tm2.yaml | 80 +++++++++++++++++++
2 files changed, 80 insertions(+), 42 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt
create mode 100644 Documentation/devicetree/bindings/sound/samsung,tm2.yaml
diff --git a/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt b/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt
deleted file mode 100644
index f5ccc12ddc00..000000000000
--- a/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Samsung Exynos5433 TM2(E) audio complex with WM5110 codec
-
-Required properties:
-
- - compatible : "samsung,tm2-audio"
- - model : the user-visible name of this sound complex
- - audio-codec : the first entry should be phandle of the wm5110 audio
- codec node, as described in ../mfd/arizona.txt;
- the second entry should be phandle of the HDMI
- transmitter node
- - i2s-controller : the list of phandle and argument tuples pointing to
- I2S controllers, the first entry should be I2S0 and
- the second one I2S1
- - audio-amplifier : the phandle of the MAX98504 amplifier
- - samsung,audio-routing : a list of the connections between audio components;
- each entry is a pair of strings, the first being the
- connection's sink, the second being the connection's
- source; valid names for sources and sinks are the
- WM5110's and MAX98504's pins and the jacks on the
- board: HP, SPK, Main Mic, Sub Mic, Third Mic,
- Headset Mic
- - mic-bias-gpios : GPIO pin that enables the Main Mic bias regulator
-
-
-Example:
-
-sound {
- compatible = "samsung,tm2-audio";
- audio-codec = <&wm5110>, <&hdmi>;
- i2s-controller = <&i2s0 0>, <&i2s1 0>;
- audio-amplifier = <&max98504>;
- mic-bias-gpios = <&gpr3 2 0>;
- model = "wm5110";
- samsung,audio-routing =
- "HP", "HPOUT1L",
- "HP", "HPOUT1R",
- "SPK", "SPKOUT",
- "SPKOUT", "HPOUT2L",
- "SPKOUT", "HPOUT2R",
- "Main Mic", "MICBIAS2",
- "IN1R", "Main Mic";
-};
diff --git a/Documentation/devicetree/bindings/sound/samsung,tm2.yaml b/Documentation/devicetree/bindings/sound/samsung,tm2.yaml
new file mode 100644
index 000000000000..74712d6f3ef4
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/samsung,tm2.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/samsung,tm2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos5433 TM2(E) audio complex with WM5110 codec
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+
+properties:
+ compatible:
+ const: samsung,tm2-audio
+
+ audio-amplifier:
+ description: Phandle to the MAX98504 amplifier.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ audio-codec:
+ description: Phandles to the codecs.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - description: Phandle to the WM5110 audio codec.
+ - description: Phandle to the HDMI transmitter node.
+
+ samsung,audio-routing:
+ description: |
+ List of the connections between audio components; each entry is
+ a pair of strings, the first being the connection's sink, the second
+ being the connection's source; valid names for sources and sinks are the
+ WM5110's and MAX98504's pins and the jacks on the board: HP, SPK, Main
+ Mic, Sub Mic, Third Mic, Headset Mic.
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+
+ i2s-controller:
+ description: Phandles to the I2S controllers.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - description: Phandle to I2S0.
+ - description: Phandle to I2S1.
+
+ mic-bias-gpios:
+ description: GPIO pin that enables the Main Mic bias regulator.
+
+ model:
+ description: The user-visible name of this sound complex.
+ $ref: /schemas/types.yaml#/definitions/string
+
+required:
+ - compatible
+ - audio-amplifier
+ - audio-codec
+ - samsung,audio-routing
+ - i2s-controller
+ - mic-bias-gpios
+ - model
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ sound {
+ compatible = "samsung,tm2-audio";
+ audio-codec = <&wm5110>, <&hdmi>;
+ i2s-controller = <&i2s0 0>, <&i2s1 0>;
+ audio-amplifier = <&max98504>;
+ mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
+ model = "wm5110";
+ samsung,audio-routing = "HP", "HPOUT1L",
+ "HP", "HPOUT1R",
+ "SPK", "SPKOUT",
+ "SPKOUT", "HPOUT2L",
+ "SPKOUT", "HPOUT2R",
+ "RCV", "HPOUT3L",
+ "RCV", "HPOUT3R";
+ };
--
2.32.0
^ permalink raw reply related
* Re: [PATCH V4 4/4] thermal: qcom: add support for PMIC5 Gen2 ADCTM
From: kernel test robot @ 2022-01-24 17:05 UTC (permalink / raw)
To: Jishnu Prakash, agross, bjorn.andersson, devicetree, mka,
dmitry.baryshkov, robh+dt, knaack.h, lars, pmeerw,
manivannan.sadhasivam
Cc: kbuild-all
In-Reply-To: <1642998194-12899-5-git-send-email-quic_jprakash@quicinc.com>
Hi Jishnu,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on rafael-pm/thermal]
[also build test ERROR on jic23-iio/togreg robh/for-next v5.17-rc1 next-20220124]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Jishnu-Prakash/thermal-qcom-Add-support-for-PMIC5-Gen2-ADC_TM/20220124-122541
base: https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git thermal
config: xtensa-allyesconfig (https://download.01.org/0day-ci/archive/20220125/202201250011.1S70DeEF-lkp@intel.com/config)
compiler: xtensa-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/ced19e8d00bc35c712b9cee1e8bc2bf741a50f9c
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Jishnu-Prakash/thermal-qcom-Add-support-for-PMIC5-Gen2-ADC_TM/20220124-122541
git checkout ced19e8d00bc35c712b9cee1e8bc2bf741a50f9c
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=xtensa SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/thermal/qcom/qcom-spmi-adc-tm5.c:21:10: fatal error: linux/unaligned/le_byteshift.h: No such file or directory
21 | #include <linux/unaligned/le_byteshift.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
vim +21 drivers/thermal/qcom/qcom-spmi-adc-tm5.c
> 21 #include <linux/unaligned/le_byteshift.h>
22
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply
* Re: MT7621 SoC Traffic Won't Flow on RGMII2 Bus/2nd GMAC
From: Florian Fainelli @ 2022-01-24 17:13 UTC (permalink / raw)
To: Andrew Lunn, Arınç ÜNAL
Cc: DENG Qingfang, Luiz Angelo Daros de Luca, Matthias Brugger,
John Crispin, Siddhant Gupta, Ilya Lipnitskiy, Sergio Paracuellos,
Felix Fietkau, Sean Wang, Mark Lee, Russell King, Jakub Kicinski,
David Miller, René van Dorst,
moderated list:ARM/Mediatek SoC support, netdev, linux-mips,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
openwrt-devel, erkin.bozoglu
In-Reply-To: <Ye1zwIFUa5LPQbQm@lunn.ch>
On 1/23/2022 7:26 AM, Andrew Lunn wrote:
> On Sun, Jan 23, 2022 at 11:33:04AM +0300, Arınç ÜNAL wrote:
>> Hey Deng,
>>
>> On 23/01/2022 09:51, DENG Qingfang wrote:
>>> Hi,
>>>
>>> Do you set the ethernet pinmux correctly?
>>>
>>> ðernet {
>>> pinctrl-names = "default";
>>> pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
>>> };
>>
>> This fixed it! We did have &rgmii2_pins on the gmac1 node (it was originally
>> on external_phy) so we never thought to investigate the pinctrl
>> configuration further! Turns out &rgmii2_pins needs to be defined on the
>> ethernet node instead.
>
> PHYs are generally external, so pinmux on them makes no sense. PHYs in
> DT are not devices in the usual sense, so i don't think the driver
> core will handle pinmux for them, even if you did list them.
Not sure I understand your comment here, this is configuring the pinmux
on the SoC side in order for the second RGMII interface's data path to work.
It is not uncommon for the same set of I/O pads to be used by different
functions within the chip. For instance the chips I work with happily
offer RGMII, MTSIF, PDM (I2S), TSIO on the same pads via different
pinmuxing options.
Also, this is declaring a pinmuxing function for the Ethernet MAC, which
is a perfectly valid use case and typically how pinmuxing is declared
for a given SoC.
--
Florian
^ permalink raw reply
* Re: MT7621 SoC Traffic Won't Flow on RGMII2 Bus/2nd GMAC
From: Russell King (Oracle) @ 2022-01-24 17:26 UTC (permalink / raw)
To: Florian Fainelli
Cc: Andrew Lunn, Arınç ÜNAL, DENG Qingfang,
Luiz Angelo Daros de Luca, Matthias Brugger, John Crispin,
Siddhant Gupta, Ilya Lipnitskiy, Sergio Paracuellos,
Felix Fietkau, Sean Wang, Mark Lee, Jakub Kicinski, David Miller,
René van Dorst, moderated list:ARM/Mediatek SoC support,
netdev, linux-mips,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
openwrt-devel, erkin.bozoglu
In-Reply-To: <acf98ec3-1120-bcc0-2a2f-85d97c48febd@gmail.com>
On Mon, Jan 24, 2022 at 09:13:38AM -0800, Florian Fainelli wrote:
> On 1/23/2022 7:26 AM, Andrew Lunn wrote:
> > On Sun, Jan 23, 2022 at 11:33:04AM +0300, Arınç ÜNAL wrote:
> > > Hey Deng,
> > >
> > > On 23/01/2022 09:51, DENG Qingfang wrote:
> > > > Hi,
> > > >
> > > > Do you set the ethernet pinmux correctly?
> > > >
> > > > ðernet {
> > > > pinctrl-names = "default";
> > > > pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
> > > > };
> > >
> > > This fixed it! We did have &rgmii2_pins on the gmac1 node (it was originally
> > > on external_phy) so we never thought to investigate the pinctrl
> > > configuration further! Turns out &rgmii2_pins needs to be defined on the
> > > ethernet node instead.
> >
> > PHYs are generally external, so pinmux on them makes no sense. PHYs in
> > DT are not devices in the usual sense, so i don't think the driver
> > core will handle pinmux for them, even if you did list them.
>
> Not sure I understand your comment here, this is configuring the pinmux on
> the SoC side in order for the second RGMII interface's data path to work.
The pinmux configuration was listed under the external PHY node, which
is qutie unusual. In the case of phylib and external ethernet PHYs,
this can be a problem.
The pinmux configuration is normally handled at device probe time by
the device model, but remember phylib bypasses that when it attaches
the generic PHY driver - meaning you don't get the pinmux configured.
What this means is that pinmux configuration in ethernet PHY nodes is
unreliable. It will only happen if we have a specific driver for the
PHY and the driver model binds that driver.
Of course, if we killed the generic driver, that would get around this
issue by requiring every PHY to have its own specific driver, but there
would be many complaints because likely lots would stop working.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply
* [PATCH 1/3] dt-bindings: pinctrl: qcom,pmic-mpp: Document PM8226 compatible
From: Rayyan Ansari @ 2022-01-24 17:15 UTC (permalink / raw)
To: linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel, Rayyan Ansari, Andy Gross,
Bjorn Andersson, Linus Walleij, Rob Herring, linux-gpio,
devicetree, linux-kernel
Document the Device Tree binding for PM8226 MPPs.
Signed-off-by: Rayyan Ansari <rayyan@ansari.sh>
---
Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml
index 35c846f59979..df79274d0ec3 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml
@@ -21,6 +21,7 @@ properties:
- qcom,pm8019-mpp
- qcom,pm8038-mpp
- qcom,pm8058-mpp
+ - qcom,pm8226-mpp
- qcom,pm8821-mpp
- qcom,pm8841-mpp
- qcom,pm8916-mpp
--
2.34.1
^ permalink raw reply related
* [PATCH 3/3] ARM: dts: qcom: pm8226: Add node for the MPP
From: Rayyan Ansari @ 2022-01-24 17:15 UTC (permalink / raw)
To: linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel, Rayyan Ansari, Andy Gross,
Bjorn Andersson, Rob Herring, devicetree, linux-kernel
In-Reply-To: <20220124171538.18088-1-rayyan@ansari.sh>
The PM8226 provides 8 Multi-Purpose Pins (or MPPs for short).
Add a node to support them.
Signed-off-by: Rayyan Ansari <rayyan@ansari.sh>
---
arch/arm/boot/dts/qcom-pm8226.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom-pm8226.dtsi
index dddb5150dfd7..9db3ea28b321 100644
--- a/arch/arm/boot/dts/qcom-pm8226.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8226.dtsi
@@ -16,6 +16,16 @@ pwrkey@800 {
debounce = <15625>;
bias-pull-up;
};
+
+ pm8226_mpps: mpps@a000 {
+ compatible = "qcom,pm8226-mpp", "qcom,spmi-mpp";
+ reg = <0xa000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8226_mpps 0 0 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
};
pm8226_1: pm8226@1 {
--
2.34.1
^ permalink raw reply related
* Re: MT7621 SoC Traffic Won't Flow on RGMII2 Bus/2nd GMAC
From: Florian Fainelli @ 2022-01-24 17:34 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Andrew Lunn, Arınç ÜNAL, DENG Qingfang,
Luiz Angelo Daros de Luca, Matthias Brugger, John Crispin,
Siddhant Gupta, Ilya Lipnitskiy, Sergio Paracuellos,
Felix Fietkau, Sean Wang, Mark Lee, Jakub Kicinski, David Miller,
René van Dorst, moderated list:ARM/Mediatek SoC support,
netdev, linux-mips,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
openwrt-devel, erkin.bozoglu
In-Reply-To: <Ye7hMWRR4URUnSFp@shell.armlinux.org.uk>
On 1/24/2022 9:26 AM, Russell King (Oracle) wrote:
> On Mon, Jan 24, 2022 at 09:13:38AM -0800, Florian Fainelli wrote:
>> On 1/23/2022 7:26 AM, Andrew Lunn wrote:
>>> On Sun, Jan 23, 2022 at 11:33:04AM +0300, Arınç ÜNAL wrote:
>>>> Hey Deng,
>>>>
>>>> On 23/01/2022 09:51, DENG Qingfang wrote:
>>>>> Hi,
>>>>>
>>>>> Do you set the ethernet pinmux correctly?
>>>>>
>>>>> ðernet {
>>>>> pinctrl-names = "default";
>>>>> pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
>>>>> };
>>>>
>>>> This fixed it! We did have &rgmii2_pins on the gmac1 node (it was originally
>>>> on external_phy) so we never thought to investigate the pinctrl
>>>> configuration further! Turns out &rgmii2_pins needs to be defined on the
>>>> ethernet node instead.
>>>
>>> PHYs are generally external, so pinmux on them makes no sense. PHYs in
>>> DT are not devices in the usual sense, so i don't think the driver
>>> core will handle pinmux for them, even if you did list them.
>>
>> Not sure I understand your comment here, this is configuring the pinmux on
>> the SoC side in order for the second RGMII interface's data path to work.
>
> The pinmux configuration was listed under the external PHY node, which
> is qutie unusual. In the case of phylib and external ethernet PHYs,
> this can be a problem.
>
> The pinmux configuration is normally handled at device probe time by
> the device model, but remember phylib bypasses that when it attaches
> the generic PHY driver - meaning you don't get the pinmux configured.
>
> What this means is that pinmux configuration in ethernet PHY nodes is
> unreliable. It will only happen if we have a specific driver for the
> PHY and the driver model binds that driver.
>
> Of course, if we killed the generic driver, that would get around this
> issue by requiring every PHY to have its own specific driver, but there
> would be many complaints because likely lots would stop working.
I suppose that explains why this is still in staging then :) Andrew's
answer makes more sense now, thanks.
--
Florian
^ permalink raw reply
* Re: [PATCH V3 09/10] media: hantro: Add support for i.MX8MM Hantro-G1
From: Ezequiel Garcia @ 2022-01-24 17:48 UTC (permalink / raw)
To: Adam Ford
Cc: linux-media, linux-arm-kernel, shawnguo, aford, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
linux-kernel, linux-staging
In-Reply-To: <20220124023125.414794-10-aford173@gmail.com>
Hi Adam,
On Sun, Jan 23, 2022 at 08:31:23PM -0600, Adam Ford wrote:
> The i.MX8MM has a Hantro G1 video decoder similar to the
> imx8mq but lacks the post-processor present in the imx8mq.
> Add support in the driver for it with the post-processing
> removed.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Thanks a lot,
Ezequiel
> diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
> index a670ddd29c4c..b281ac4fb79c 100644
> --- a/drivers/staging/media/hantro/hantro_drv.c
> +++ b/drivers/staging/media/hantro/hantro_drv.c
> @@ -615,6 +615,7 @@ static const struct of_device_id of_hantro_match[] = {
> { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
> #endif
> #ifdef CONFIG_VIDEO_HANTRO_IMX8M
> + { .compatible = "nxp,imx8mm-vpu-g1", .data = &imx8mm_vpu_g1_variant, },
> { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
> { .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant },
> { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant },
> diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
> index f0bd2ffe290b..c00b46e06055 100644
> --- a/drivers/staging/media/hantro/hantro_hw.h
> +++ b/drivers/staging/media/hantro/hantro_hw.h
> @@ -299,6 +299,7 @@ enum hantro_enc_fmt {
> ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3,
> };
>
> +extern const struct hantro_variant imx8mm_vpu_g1_variant;
> extern const struct hantro_variant imx8mq_vpu_g1_variant;
> extern const struct hantro_variant imx8mq_vpu_g2_variant;
> extern const struct hantro_variant imx8mq_vpu_variant;
> diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
> index 849ea7122d47..9802508bade2 100644
> --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
> +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
> @@ -327,3 +327,15 @@ const struct hantro_variant imx8mq_vpu_g2_variant = {
> .clk_names = imx8mq_g2_clk_names,
> .num_clocks = ARRAY_SIZE(imx8mq_g2_clk_names),
> };
> +
> +const struct hantro_variant imx8mm_vpu_g1_variant = {
> + .dec_fmts = imx8m_vpu_dec_fmts,
> + .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts),
> + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
> + HANTRO_H264_DECODER,
> + .codec_ops = imx8mq_vpu_g1_codec_ops,
> + .irqs = imx8mq_irqs,
> + .num_irqs = ARRAY_SIZE(imx8mq_irqs),
> + .clk_names = imx8mq_g1_clk_names,
> + .num_clocks = ARRAY_SIZE(imx8mq_g1_clk_names),
> +};
> --
> 2.32.0
>
^ permalink raw reply
* Re: [PATCH V3 08/10] dt-bindings: media: nxp, imx8mq-vpu: Add support for G1 on imx8mm
From: Ezequiel Garcia @ 2022-01-24 17:55 UTC (permalink / raw)
To: Adam Ford
Cc: linux-media, linux-arm-kernel, shawnguo, aford, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
linux-kernel, linux-staging
In-Reply-To: <20220124023125.414794-9-aford173@gmail.com>
On Sun, Jan 23, 2022 at 08:31:22PM -0600, Adam Ford wrote:
> The i.MX8M mini appears to have a similar G1 decoder but the
> post-processing isn't present, so different compatible flag is required.
> Since all the other parameters are the same with imx8mq, just add
> the new compatible flag to nxp,imx8mq-vpu.yaml.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> index 9c28d562112b..7dc13a4b1805 100644
> --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> @@ -5,7 +5,7 @@
> $id: "http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#"
> $schema: "http://devicetree.org/meta-schemas/core.yaml#"
>
> -title: Hantro G1/G2 VPU codecs implemented on i.MX8MQ SoCs
> +title: Hantro G1/G2 VPU codecs implemented on i.MX8M SoCs
>
> maintainers:
> - Philipp Zabel <p.zabel@pengutronix.de>
> @@ -20,6 +20,7 @@ properties:
> deprecated: true
> - const: nxp,imx8mq-vpu-g1
> - const: nxp,imx8mq-vpu-g2
> + - const: nxp,imx8mm-vpu-g1
>
> reg:
> maxItems: 1
> --
> 2.32.0
>
^ permalink raw reply
* Re: [PATCH V3 06/10] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
From: Ezequiel Garcia @ 2022-01-24 17:59 UTC (permalink / raw)
To: Adam Ford
Cc: linux-media, linux-arm-kernel, shawnguo, aford, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
linux-kernel, linux-staging
In-Reply-To: <20220124023125.414794-7-aford173@gmail.com>
On Sun, Jan 23, 2022 at 08:31:20PM -0600, Adam Ford wrote:
> With the Hantro G1 and G2 now setup to run independently, update
> the device tree to allow both to operate. This requires the
> vpu-blk-ctrl node to be configured. Since vpu-blk-ctrl needs
> certain clock enabled to handle the gating of the G1 and G2
> fuses, the clock-parents and clock-rates for the various VPU's
> to be moved into the pgc_vpu because they cannot get re-parented
> once enabled, and the pgc_vpu is the highest in the chain.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Thanks,
Ezequiel
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 2df2510d0118..549b2440f55d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
> pgc_vpu: power-domain@6 {
> #power-domain-cells = <0>;
> reg = <IMX8M_POWER_DOMAIN_VPU>;
> - clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>,
> + <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> + <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> + <&clk IMX8MQ_CLK_VPU_G2>,
> + <&clk IMX8MQ_CLK_VPU_BUS>,
> + <&clk IMX8MQ_VPU_PLL_BYPASS>;
> + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> + <&clk IMX8MQ_VPU_PLL_OUT>,
> + <&clk IMX8MQ_SYS1_PLL_800M>,
> + <&clk IMX8MQ_VPU_PLL>;
> + assigned-clock-rates = <600000000>,
> + <600000000>,
> + <800000000>,
> + <0>;
> };
>
> pgc_disp: power-domain@7 {
> @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
> status = "disabled";
> };
>
> - vpu: video-codec@38300000 {
> - compatible = "nxp,imx8mq-vpu";
> - reg = <0x38300000 0x10000>,
> - <0x38310000 0x10000>,
> - <0x38320000 0x10000>;
> - reg-names = "g1", "g2", "ctrl";
> - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "g1", "g2";
> + vpu_g1: video-codec@38300000 {
> + compatible = "nxp,imx8mq-vpu-g1";
> + reg = <0x38300000 0x10000>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
> + };
> +
> + vpu_g2: video-codec@38310000 {
> + compatible = "nxp,imx8mq-vpu-g2";
> + reg = <0x38310000 0x10000>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
> + };
> +
> + vpu_blk_ctrl: blk-ctrl@38320000 {
> + compatible = "fsl,imx8mq-vpu-blk-ctrl";
> + reg = <0x38320000 0x100>;
> + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
> + power-domain-names = "bus", "g1", "g2";
> clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> - <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> - clock-names = "g1", "g2", "bus";
> - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> - <&clk IMX8MQ_CLK_VPU_G2>,
> - <&clk IMX8MQ_CLK_VPU_BUS>,
> - <&clk IMX8MQ_VPU_PLL_BYPASS>;
> - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> - <&clk IMX8MQ_VPU_PLL_OUT>,
> - <&clk IMX8MQ_SYS1_PLL_800M>,
> - <&clk IMX8MQ_VPU_PLL>;
> - assigned-clock-rates = <600000000>, <600000000>,
> - <800000000>, <0>;
> - power-domains = <&pgc_vpu>;
> + <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> + clock-names = "g1", "g2";
> + #power-domain-cells = <1>;
> };
>
> pcie0: pcie@33800000 {
> --
> 2.32.0
>
^ permalink raw reply
* Re: [PATCH V3 05/10] media: hantro: Allow i.MX8MQ G1 and G2 to run independently
From: Ezequiel Garcia @ 2022-01-24 18:09 UTC (permalink / raw)
To: Adam Ford
Cc: linux-media, linux-arm-kernel, shawnguo, aford, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
linux-kernel, linux-staging
In-Reply-To: <20220124023125.414794-6-aford173@gmail.com>
Hi Adam,
On Sun, Jan 23, 2022 at 08:31:19PM -0600, Adam Ford wrote:
> The VPU in the i.MX8MQ is really the combination of Hantro G1 and
> Hantro G2. With the updated vpu-blk-ctrl, the power domains system
> can enable and disable them separately as well as pull them out of
> reset. This simplifies the code and lets them run independently
> while still retaining backwards compatibility with older device
> trees for those using G1.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
>
> diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
> index 6a51f39dde56..a670ddd29c4c 100644
> --- a/drivers/staging/media/hantro/hantro_drv.c
> +++ b/drivers/staging/media/hantro/hantro_drv.c
> @@ -616,6 +616,7 @@ static const struct of_device_id of_hantro_match[] = {
> #endif
> #ifdef CONFIG_VIDEO_HANTRO_IMX8M
> { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
Since you might need to resend the series anyway due to the
issue with arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi,
could you add a small warning for the deprecated compatible string?
This will be a useful hint for kernel developers and system integrators
about the devicetree changes.
Something along these lines, maybe?
match = of_match_node(of_hantro_match, pdev->dev.of_node);
vpu->variant = match->data;
/*
* Support for nxp,imx8mq-vpu is kept for backwards compatibility
* but it's deprecated. Please update your DTS file to use
* nxp,imx8mq-vpu-g1 or nxp,imx8mq-vpu-g2 instead.
*/
if (of_device_is_compatible(pdev->dev.of_node, "nxp,imx8mq-vpu"))
dev_warn(&pdev->dev, "%s compatible is deprecated\n",
match->compatible);
In any case, the patch looks good:
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Thanks,
Ezequiel
> + { .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant },
> { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant },
> #endif
> #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4
> diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
> index 4a19ae8940b9..f0bd2ffe290b 100644
> --- a/drivers/staging/media/hantro/hantro_hw.h
> +++ b/drivers/staging/media/hantro/hantro_hw.h
> @@ -299,6 +299,7 @@ enum hantro_enc_fmt {
> ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3,
> };
>
> +extern const struct hantro_variant imx8mq_vpu_g1_variant;
> extern const struct hantro_variant imx8mq_vpu_g2_variant;
> extern const struct hantro_variant imx8mq_vpu_variant;
> extern const struct hantro_variant px30_vpu_variant;
> diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
> index f5991b8e553a..849ea7122d47 100644
> --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
> +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
> @@ -205,13 +205,6 @@ static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx)
> imx8m_soft_reset(vpu, RESET_G1);
> }
>
> -static void imx8m_vpu_g2_reset(struct hantro_ctx *ctx)
> -{
> - struct hantro_dev *vpu = ctx->dev;
> -
> - imx8m_soft_reset(vpu, RESET_G2);
> -}
> -
> /*
> * Supported codec ops.
> */
> @@ -237,17 +230,33 @@ static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = {
> },
> };
>
> +static const struct hantro_codec_ops imx8mq_vpu_g1_codec_ops[] = {
> + [HANTRO_MODE_MPEG2_DEC] = {
> + .run = hantro_g1_mpeg2_dec_run,
> + .init = hantro_mpeg2_dec_init,
> + .exit = hantro_mpeg2_dec_exit,
> + },
> + [HANTRO_MODE_VP8_DEC] = {
> + .run = hantro_g1_vp8_dec_run,
> + .init = hantro_vp8_dec_init,
> + .exit = hantro_vp8_dec_exit,
> + },
> + [HANTRO_MODE_H264_DEC] = {
> + .run = hantro_g1_h264_dec_run,
> + .init = hantro_h264_dec_init,
> + .exit = hantro_h264_dec_exit,
> + },
> +};
> +
> static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = {
> [HANTRO_MODE_HEVC_DEC] = {
> .run = hantro_g2_hevc_dec_run,
> - .reset = imx8m_vpu_g2_reset,
> .init = hantro_hevc_dec_init,
> .exit = hantro_hevc_dec_exit,
> },
> [HANTRO_MODE_VP9_DEC] = {
> .run = hantro_g2_vp9_dec_run,
> .done = hantro_g2_vp9_dec_done,
> - .reset = imx8m_vpu_g2_reset,
> .init = hantro_vp9_dec_init,
> .exit = hantro_vp9_dec_exit,
> },
> @@ -267,6 +276,8 @@ static const struct hantro_irq imx8mq_g2_irqs[] = {
>
> static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" };
> static const char * const imx8mq_reg_names[] = { "g1", "g2", "ctrl" };
> +static const char * const imx8mq_g1_clk_names[] = { "g1" };
> +static const char * const imx8mq_g2_clk_names[] = { "g2" };
>
> const struct hantro_variant imx8mq_vpu_variant = {
> .dec_fmts = imx8m_vpu_dec_fmts,
> @@ -287,6 +298,21 @@ const struct hantro_variant imx8mq_vpu_variant = {
> .num_regs = ARRAY_SIZE(imx8mq_reg_names)
> };
>
> +const struct hantro_variant imx8mq_vpu_g1_variant = {
> + .dec_fmts = imx8m_vpu_dec_fmts,
> + .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts),
> + .postproc_fmts = imx8m_vpu_postproc_fmts,
> + .num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts),
> + .postproc_ops = &hantro_g1_postproc_ops,
> + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
> + HANTRO_H264_DECODER,
> + .codec_ops = imx8mq_vpu_g1_codec_ops,
> + .irqs = imx8mq_irqs,
> + .num_irqs = ARRAY_SIZE(imx8mq_irqs),
> + .clk_names = imx8mq_g1_clk_names,
> + .num_clocks = ARRAY_SIZE(imx8mq_g1_clk_names),
> +};
> +
> const struct hantro_variant imx8mq_vpu_g2_variant = {
> .dec_offset = 0x0,
> .dec_fmts = imx8m_vpu_g2_dec_fmts,
> @@ -296,10 +322,8 @@ const struct hantro_variant imx8mq_vpu_g2_variant = {
> .postproc_ops = &hantro_g2_postproc_ops,
> .codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER,
> .codec_ops = imx8mq_vpu_g2_codec_ops,
> - .init = imx8mq_vpu_hw_init,
> - .runtime_resume = imx8mq_runtime_resume,
> .irqs = imx8mq_g2_irqs,
> .num_irqs = ARRAY_SIZE(imx8mq_g2_irqs),
> - .clk_names = imx8mq_clk_names,
> - .num_clocks = ARRAY_SIZE(imx8mq_clk_names),
> + .clk_names = imx8mq_g2_clk_names,
> + .num_clocks = ARRAY_SIZE(imx8mq_g2_clk_names),
> };
> --
> 2.32.0
>
^ permalink raw reply
* Re: [PATCH V3 04/10] dt-bindings: media: nxp, imx8mq-vpu: Split G1 and G2 nodes
From: Ezequiel Garcia @ 2022-01-24 18:10 UTC (permalink / raw)
To: Adam Ford
Cc: linux-media, linux-arm-kernel, shawnguo, aford, Rob Herring,
Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
linux-kernel, linux-staging
In-Reply-To: <20220124023125.414794-5-aford173@gmail.com>
On Sun, Jan 23, 2022 at 08:31:18PM -0600, Adam Ford wrote:
> The G1 and G2 are independent and separate decoder blocks
> that are enabled by the vpu-blk-ctrl power-domain controller,
> which now has a proper driver.
>
> Because these blocks only share the power-domain, and can be
> independently fused out, update the bindings to support separate
> nodes for the G1 and G2 decoders with vpu-blk-ctrl power-domain
> support.
>
> The new DT + old kernel isn't a supported configuration.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Thanks,
Ezequiel
> diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> index 762be3f96ce9..9c28d562112b 100644
> --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> @@ -15,33 +15,20 @@ description:
>
> properties:
> compatible:
> - const: nxp,imx8mq-vpu
> + oneOf:
> + - const: nxp,imx8mq-vpu
> + deprecated: true
> + - const: nxp,imx8mq-vpu-g1
> + - const: nxp,imx8mq-vpu-g2
>
> reg:
> - maxItems: 3
> -
> - reg-names:
> - items:
> - - const: g1
> - - const: g2
> - - const: ctrl
> + maxItems: 1
>
> interrupts:
> - maxItems: 2
> -
> - interrupt-names:
> - items:
> - - const: g1
> - - const: g2
> + maxItems: 1
>
> clocks:
> - maxItems: 3
> -
> - clock-names:
> - items:
> - - const: g1
> - - const: g2
> - - const: bus
> + maxItems: 1
>
> power-domains:
> maxItems: 1
> @@ -49,31 +36,33 @@ properties:
> required:
> - compatible
> - reg
> - - reg-names
> - interrupts
> - - interrupt-names
> - clocks
> - - clock-names
>
> additionalProperties: false
>
> examples:
> - |
> #include <dt-bindings/clock/imx8mq-clock.h>
> + #include <dt-bindings/power/imx8mq-power.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + vpu_g1: video-codec@38300000 {
> + compatible = "nxp,imx8mq-vpu-g1";
> + reg = <0x38300000 0x10000>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
> + };
> + - |
> + #include <dt-bindings/clock/imx8mq-clock.h>
> + #include <dt-bindings/power/imx8mq-power.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
>
> - vpu: video-codec@38300000 {
> - compatible = "nxp,imx8mq-vpu";
> - reg = <0x38300000 0x10000>,
> - <0x38310000 0x10000>,
> - <0x38320000 0x10000>;
> - reg-names = "g1", "g2", "ctrl";
> - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "g1", "g2";
> - clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> - <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> - clock-names = "g1", "g2", "bus";
> - power-domains = <&pgc_vpu>;
> + vpu_g2: video-codec@38300000 {
> + compatible = "nxp,imx8mq-vpu-g2";
> + reg = <0x38310000 0x10000>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
> };
> --
> 2.32.0
>
^ permalink raw reply
* [PATCH v1 0/2] Add support for the eDP panel on sc7280 CRD
From: Sankeerth Billakanti @ 2022-01-24 18:15 UTC (permalink / raw)
To: dri-devel, linux-arm-msm, freedreno, linux-kernel, devicetree,
agross, bjorn.andersson, robh+dt
Cc: Sankeerth Billakanti, robdclark, seanpaul, swboyd, quic_kalyant,
quic_abhinavk, dianders, quic_khsieh, quic_mkrishn
Add support for the eDP panel on sc7280 CRD platform.
These changes are dependent on the following series:
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=586263&archive=both&state=*
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=560587&state=%2A&archive=both
Sankeerth Billakanti (2):
ARM64: dts: qcom: enable eDP panel support for sc7280
drm/panel-edp: Add sharp panel support for sc7280
arch/arm64/boot/dts/qcom/sc7280-crd.dts | 127 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/panel/panel-edp.c | 11 +++
2 files changed, 138 insertions(+)
--
2.7.4
^ permalink raw reply
* [PATCH v1 1/2] ARM64: dts: qcom: enable eDP panel support for sc7280
From: Sankeerth Billakanti @ 2022-01-24 18:15 UTC (permalink / raw)
To: dri-devel, linux-arm-msm, freedreno, linux-kernel, devicetree,
agross, bjorn.andersson, robh+dt
Cc: Sankeerth Billakanti, robdclark, seanpaul, swboyd, quic_kalyant,
quic_abhinavk, dianders, quic_khsieh, quic_mkrishn
In-Reply-To: <1643048114-2996-1-git-send-email-quic_sbillaka@quicinc.com>
Enable the eDP display panel support with backlight on sc7280 platform.
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
---
arch/arm64/boot/dts/qcom/sc7280-crd.dts | 127 ++++++++++++++++++++++++++++++++
1 file changed, 127 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-crd.dts
index cd2755c..fde6f75 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-crd.dts
@@ -64,6 +64,47 @@ ap_ts_pen_1v8: &i2c13 {
};
};
+&mdss {
+ status = "okay";
+};
+
+&mdss_mdp {
+ status = "okay";
+};
+
+&mdss_edp {
+ status = "okay";
+
+ vdda-1p2-supply = <&vreg_l6b_1p2>;
+ vdda-0p9-supply = <&vreg_l10c_0p8>;
+
+ ports {
+ port@1 {
+ reg = <1>;
+ edp_out: endpoint {
+ remote-endpoint = <&edp_panel_in>;
+ };
+ };
+ };
+};
+
+&mdss_edp_phy {
+ status = "okay";
+
+ vdda-1p2-supply = <&vreg_l6b_1p2>;
+ vdda-0p9-supply = <&vreg_l10c_0p8>;
+};
+
+&mdss_dp {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp_hot_plug_det>;
+ data-lanes = <0 1>;
+ vdda-1p2-supply = <&vreg_l6b_1p2>;
+ vdda-0p9-supply = <&vreg_l1b_0p8>;
+};
+
&nvme_3v3_regulator {
gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>;
};
@@ -72,7 +113,93 @@ ap_ts_pen_1v8: &i2c13 {
pins = "gpio51";
};
+&pm8350c_pwm{
+ status = "okay";
+};
+
+&pm8350c_gpios {
+ backlight_pwm_default: backlight_pwm_default {
+ pinconf {
+ pins = "gpio8";
+ function = "func1";
+ output-low;
+ bias-disable;
+ power-source = <0>;
+ qcom,drive-strength = <3>;
+ };
+ };
+};
+
+&soc {
+ backlight_power: backlight_power {
+ compatible = "regulator-fixed";
+ regulator-name = "backlight_power";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ edp_power: edp_power {
+ compatible = "regulator-fixed";
+ regulator-name = "edp_power";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&edp_panel_power_default>;
+ };
+
+ edp_backlight: edp_backlight {
+ compatible = "pwm-backlight";
+
+ pwms = <&pm8350c_pwm 3 65535>;
+ power-supply = <&backlight_power>;
+ enable-gpio = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&backlight_pwm_default>;
+ };
+
+ edp_panel: edp_panel {
+ compatible = "sharp_lq140m1jw46";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&edp_hot_plug_det>;
+
+ power-supply = <&edp_power>;
+ backlight = <&edp_backlight>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ edp_panel_in: endpoint {
+ remote-endpoint = <&edp_out>;
+ };
+ };
+ };
+ };
+};
+
&tlmm {
+ edp_hot_plug_det: edp-hot-plug-det {
+ pins = "gpio60";
+ function = "edp_hot";
+ bias-pull-down;
+ input-enable;
+ };
+
+ edp_panel_power_default: edp_panel_power_default {
+ pins = "gpio80";
+ function = "gpio";
+ drive-strength = <2>;
+ output-high;
+ };
+
tp_int_odl: tp-int-odl {
pins = "gpio7";
function = "gpio";
--
2.7.4
^ permalink raw reply related
* [PATCH v1 2/2] drm/panel-edp: Add sharp panel support for sc7280
From: Sankeerth Billakanti @ 2022-01-24 18:15 UTC (permalink / raw)
To: dri-devel, linux-arm-msm, freedreno, linux-kernel, devicetree,
agross, bjorn.andersson, robh+dt
Cc: Sankeerth Billakanti, robdclark, seanpaul, swboyd, quic_kalyant,
quic_abhinavk, dianders, quic_khsieh, quic_mkrishn
In-Reply-To: <1643048114-2996-1-git-send-email-quic_sbillaka@quicinc.com>
Add eDP panel support for sc7280 CRD platform.
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
---
drivers/gpu/drm/panel/panel-edp.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c
index 176ef0c..bb2e346 100644
--- a/drivers/gpu/drm/panel/panel-edp.c
+++ b/drivers/gpu/drm/panel/panel-edp.c
@@ -1605,6 +1605,14 @@ static const struct panel_desc sharp_lq123p1jx31 = {
},
};
+static const struct panel_desc sharp_lq140m1jw46 = {
+ .bpc = 8,
+ .size = {
+ .width = 309,
+ .height = 173,
+ },
+};
+
static const struct drm_display_mode starry_kr122ea0sra_mode = {
.clock = 147000,
.hdisplay = 1920,
@@ -1719,6 +1727,9 @@ static const struct of_device_id platform_of_match[] = {
.compatible = "sharp,lq123p1jx31",
.data = &sharp_lq123p1jx31,
}, {
+ .compatible = "sharp_lq140m1jw46",
+ .data = &sharp_lq140m1jw46,
+ }, {
.compatible = "starry,kr122ea0sra",
.data = &starry_kr122ea0sra,
}, {
--
2.7.4
^ permalink raw reply related
* [PATCH v1] arm64: dts: qcom: sc7280: Add camcc clock node
From: Taniya Das @ 2022-01-24 18:44 UTC (permalink / raw)
To: Rob Herring, Bjorn Andersson
Cc: Douglas Anderson, Stephen Boyd, Andy Gross, devicetree,
linux-arm-msm, linux-kernel, Taniya Das
Add the camera clock controller node for SC7280 SoC.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 937c2e0e93eb..2b4596f2b4cb 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -4,7 +4,7 @@
*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
-
+#include <dt-bindings/clock/qcom,camcc-sc7280.h>
#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,gpucc-sc7280.h>
@@ -2761,6 +2761,18 @@
#power-domain-cells = <1>;
};
+ camcc: clock-controller@ad00000 {
+ compatible = "qcom,sc7280-camcc";
+ reg = <0 0x0ad00000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
dispcc: clock-controller@af00000 {
compatible = "qcom,sc7280-dispcc";
reg = <0 0xaf00000 0 0x20000>;
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply related
* Re: [PATCH v1 1/2] ARM64: dts: qcom: enable eDP panel support for sc7280
From: Doug Anderson @ 2022-01-24 19:04 UTC (permalink / raw)
To: Sankeerth Billakanti
Cc: dri-devel, linux-arm-msm, freedreno, LKML,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andy Gross, Bjorn Andersson, Rob Herring, Rob Clark, Sean Paul,
Stephen Boyd, quic_kalyant, quic_abhinavk, quic_khsieh,
quic_mkrishn
In-Reply-To: <1643048114-2996-2-git-send-email-quic_sbillaka@quicinc.com>
Hi,
On Mon, Jan 24, 2022 at 10:15 AM Sankeerth Billakanti
<quic_sbillaka@quicinc.com> wrote:
>
> Enable the eDP display panel support with backlight on sc7280 platform.
>
> Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sc7280-crd.dts | 127 ++++++++++++++++++++++++++++++++
> 1 file changed, 127 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-crd.dts
> index cd2755c..fde6f75 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-crd.dts
> @@ -64,6 +64,47 @@ ap_ts_pen_1v8: &i2c13 {
> };
> };
>
> +&mdss {
> + status = "okay";
> +};
> +
> +&mdss_mdp {
> + status = "okay";
> +};
"mdss_mdp" sorts after "mdss_edp",
> +&mdss_edp {
> + status = "okay";
> +
> + vdda-1p2-supply = <&vreg_l6b_1p2>;
> + vdda-0p9-supply = <&vreg_l10c_0p8>;
> +
> + ports {
> + port@1 {
> + reg = <1>;
> + edp_out: endpoint {
> + remote-endpoint = <&edp_panel_in>;
> + };
> + };
> + };
I think part of the above should be in sc7280.dtsi. Basically in
sc7820.dtsi I think you should have:
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
edp_in: endpoint {
remote-endpoint = <&dpu_intf5_out>;
};
};
port@1 {
reg = <1>;
edp_out: endpoint {
};
};
};
...and then the crd dts file just needs:
&edp_out {
remote-endpoint = <&edp_panel_in>;
};
Right?
> +};
> +
> +&mdss_edp_phy {
> + status = "okay";
> +
> + vdda-1p2-supply = <&vreg_l6b_1p2>;
> + vdda-0p9-supply = <&vreg_l10c_0p8>;
> +};
> +
> +&mdss_dp {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&dp_hot_plug_det>;
> + data-lanes = <0 1>;
> + vdda-1p2-supply = <&vreg_l6b_1p2>;
> + vdda-0p9-supply = <&vreg_l1b_0p8>;
> +};
> +
> &nvme_3v3_regulator {
> gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>;
> };
> @@ -72,7 +113,93 @@ ap_ts_pen_1v8: &i2c13 {
> pins = "gpio51";
> };
>
> +&pm8350c_pwm{
nit: space after "pwm" and before "{"
> + status = "okay";
Don't you need:
pinctrl-names = "default";
pinctrl-0 = <&backlight_pwm_default>;
> +};
> +
> +&pm8350c_gpios {
> + backlight_pwm_default: backlight_pwm_default {
nit: node name should have dashes, not underscores. Also, don't
include the word "default".
> + pinconf {
> + pins = "gpio8";
> + function = "func1";
> + output-low;
> + bias-disable;
> + power-source = <0>;
> + qcom,drive-strength = <3>;
Instead of 3, should be PMIC_GPIO_STRENGTH_LOW
> + };
Don't need the "pinconf" subnode.
> + };
> +};
> +
> +&soc {
Don't need to put the regulators under &soc. They can be top level, right?
> + backlight_power: backlight_power {
nit: node names should have "-", not "_"
> + compatible = "regulator-fixed";
> + regulator-name = "backlight_power";
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + edp_power: edp_power {
nit: node names should have "-", not "_"
> + compatible = "regulator-fixed";
> + regulator-name = "edp_power";
> +
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&edp_panel_power_default>;
> + };
> +
> + edp_backlight: edp_backlight {
nit: node names should have a "-", not an "_".
> + compatible = "pwm-backlight";
> +
> + pwms = <&pm8350c_pwm 3 65535>;
> + power-supply = <&backlight_power>;
> + enable-gpio = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>;
So wait. Why do you have a "bogus" backlight_power regulator and then
a separate enable-gpio? Why
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&backlight_pwm_default>;
This pinctrl belongs as part of the PWM, not as part of the backlight.
...but where's the pinctrl for pm8350c_gpios #7? That _should_ be here
since that's the backlight enable.
> + };
> +
> + edp_panel: edp_panel {
> + compatible = "sharp_lq140m1jw46";
Device tree compatible strings separate the manufacturer from the
model with ",", not "_".
> + pinctrl-names = "default";
> + pinctrl-0 = <&edp_hot_plug_det>;
I think for eDP we probably want the pinctrl to be in the sc7280.dtsi
file. It seems highly likely that people will hook up the eDP HPD pin
to the standard place. If they don't then boards can override it.
> + power-supply = <&edp_power>;
> + backlight = <&edp_backlight>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + edp_panel_in: endpoint {
> + remote-endpoint = <&edp_out>;
> + };
> + };
Like for DP, much of this "ports" stuff should be in sc7280.dtsi.
> + };
> + };
> +};
> +
> &tlmm {
> + edp_hot_plug_det: edp-hot-plug-det {
> + pins = "gpio60";
> + function = "edp_hot";
The "pins" and "function" belong in sc7280.dtsi.
> + bias-pull-down;
This part belongs in the CRD file.
> + input-enable;
You don't need "input-enable".
> + };
> + edp_panel_power_default: edp_panel_power_default {
Nit: node name shouldn't have underscores.
...and remove the word "default".
^ permalink raw reply
* Re: [PATCH v1 2/2] drm/panel-edp: Add sharp panel support for sc7280
From: Doug Anderson @ 2022-01-24 19:10 UTC (permalink / raw)
To: Sankeerth Billakanti
Cc: dri-devel, linux-arm-msm, freedreno, LKML,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andy Gross, Bjorn Andersson, Rob Herring, Rob Clark, Sean Paul,
Stephen Boyd, quic_kalyant, quic_abhinavk, quic_khsieh,
quic_mkrishn
In-Reply-To: <1643048114-2996-3-git-send-email-quic_sbillaka@quicinc.com>
Hi,
On Mon, Jan 24, 2022 at 10:16 AM Sankeerth Billakanti
<quic_sbillaka@quicinc.com> wrote:
>
> Add eDP panel support for sc7280 CRD platform.
>
> Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
> ---
> drivers/gpu/drm/panel/panel-edp.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c
> index 176ef0c..bb2e346 100644
> --- a/drivers/gpu/drm/panel/panel-edp.c
> +++ b/drivers/gpu/drm/panel/panel-edp.c
> @@ -1605,6 +1605,14 @@ static const struct panel_desc sharp_lq123p1jx31 = {
> },
> };
>
> +static const struct panel_desc sharp_lq140m1jw46 = {
> + .bpc = 8,
> + .size = {
> + .width = 309,
> + .height = 173,
> + },
Where are your delays? I very much doubt that they are all 0.
I guess you're also not putting timings in here and you're relying on
these coming from the EDID? My own preference would be:
1. If you are relying on a reliable way to read the EDID of the panel
then you shouldn't even need to add anything to this section of the
file. You should use the "edp-panel" compatible string and then add an
entry to the "edp_panels" structure.
2. If you want to support folks that don't have a reliable way to read
the EDID then you can add things here, but you should add a mode.
> +};
> +
> static const struct drm_display_mode starry_kr122ea0sra_mode = {
> .clock = 147000,
> .hdisplay = 1920,
> @@ -1719,6 +1727,9 @@ static const struct of_device_id platform_of_match[] = {
> .compatible = "sharp,lq123p1jx31",
> .data = &sharp_lq123p1jx31,
> }, {
> + .compatible = "sharp_lq140m1jw46",
> + .data = &sharp_lq140m1jw46,
Two problems:
1. You should use a ",", not a "_" to separate the vendor from the model.
2. You need to post device tree bindings for this.
NOTE: if instead your eDP controller supports DP AUX bus then you
don't need to add to this table at all and you don't need to add
bindings. Instead, you'd add your EDID panel ID to the "edp_panels"
structure.
^ permalink raw reply
* Re: [PATCH 3/4] crypto: xilinx: Add Xilinx SHA3 driver
From: kernel test robot @ 2022-01-24 19:24 UTC (permalink / raw)
To: Harsha, herbert, davem, linux-crypto, linux-kernel, michals,
linux-arm-kernel, robh+dt, devicetree
Cc: kbuild-all, saratcha, harshj
In-Reply-To: <1642931227-20706-4-git-send-email-harsha.harsha@xilinx.com>
Hi Harsha,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on herbert-cryptodev-2.6/master]
[also build test WARNING on herbert-crypto-2.6/master]
[cannot apply to xilinx-xlnx/master v5.17-rc1 next-20220124]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Harsha/crypto-Add-Xilinx-ZynqMP-SHA3-driver-support/20220123-175102
base: https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git master
config: s390-allyesconfig (https://download.01.org/0day-ci/archive/20220125/202201250209.WqpE2vMF-lkp@intel.com/config)
compiler: s390-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/fc7aea6e3118ca7210454fdb7c9c588c05c1f171
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Harsha/crypto-Add-Xilinx-ZynqMP-SHA3-driver-support/20220123-175102
git checkout fc7aea6e3118ca7210454fdb7c9c588c05c1f171
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=s390 SHELL=/bin/bash drivers/crypto/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
In file included from ./arch/s390/include/generated/asm/cacheflush.h:1,
from drivers/crypto/xilinx/zynqmp-sha.c:6:
>> include/asm-generic/cacheflush.h:53:46: warning: 'struct folio' declared inside parameter list will not be visible outside of this definition or declaration
53 | static inline void flush_dcache_folio(struct folio *folio) { }
| ^~~~~
vim +53 include/asm-generic/cacheflush.h
08b0b0059bf1c2 Matthew Wilcox (Oracle 2020-12-16 52)
08b0b0059bf1c2 Matthew Wilcox (Oracle 2020-12-16 @53) static inline void flush_dcache_folio(struct folio *folio) { }
76b3b58fac350c Christoph Hellwig 2020-06-07 54 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
08b0b0059bf1c2 Matthew Wilcox (Oracle 2020-12-16 55) #define ARCH_IMPLEMENTS_FLUSH_DCACHE_FOLIO
4f0bd808134d73 Mike Rapoport 2019-12-23 56 #endif
c296d4dc13aefe Qian Cai 2019-07-16 57
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply
* Re: [PATCH v3 2/2] clk: qcom: lpass: Add support for LPASS clock controller for SC7280
From: Stephen Boyd @ 2022-01-24 19:46 UTC (permalink / raw)
To: Michael Turquette, Taniya Das
Cc: Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk, linux-kernel,
devicetree, robh, robh+dt, Taniya Das
In-Reply-To: <20220124162442.29497-3-tdas@codeaurora.org>
Quoting Taniya Das (2022-01-24 08:24:42)
> diff --git a/drivers/clk/qcom/lpasscorecc-sc7280.c b/drivers/clk/qcom/lpasscorecc-sc7280.c
> new file mode 100644
> index 000000000000..3ac62ea5767e
> --- /dev/null
> +++ b/drivers/clk/qcom/lpasscorecc-sc7280.c
> @@ -0,0 +1,430 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of.h>
Is the of.h include used?
> +#include <linux/pm_clock.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "common.h"
> +#include "gdsc.h"
> +
[...]
> +
> +static struct regmap_config lpass_core_cc_sc7280_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .fast_io = true,
What's the max_register? Please set it so that debugfs works.
^ permalink raw reply
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