* [PATCH 2/2] ARM: dts: Use 32KiHz oscillator on devkit8000
From: Anthoine Bourgeois @ 2022-01-25 19:11 UTC (permalink / raw)
To: linux-omap, devicetree, tony, bcousson; +Cc: robh+dt, Anthoine Bourgeois
In-Reply-To: <20220125191139.2429555-1-anthoine.bourgeois@gmail.com>
Devkit8000 board seems to always used 32k_counter as clocksource.
Restore this behavior.
If clocksource is back to 32k_counter, timer12 is now the clockevent
source (as before) and timer2 is not longer needed here.
This commit fixes the same issue observed with commit 23885389dbbb
("ARM: dts: Fix timer regression for beagleboard revision c") when sleep
is blocked until hitting keys over serial console.
Fixed: aba1ad05da08 ("clocksource/drivers/timer-ti-dm: Add clockevent and clocksource support")
Fixed: e428e250fde6 ("ARM: dts: Configure system timers for omap3")
Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
---
arch/arm/boot/dts/omap3-devkit8000-common.dtsi | 17 +----------------
drivers/clocksource/timer-ti-dm-systimer.c | 3 +--
2 files changed, 2 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
index f5197bb31ed8..54cd37336be7 100644
--- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
+++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
@@ -158,11 +158,6 @@ &mmc3 {
status = "disabled";
};
-/* Unusable as clocksource because of unreliable oscillator */
-&counter32k {
- status = "disabled";
-};
-
/* Unusable as clockevent because if unreliable oscillator, allow to idle */
&timer1_target {
/delete-property/ti,no-reset-on-init;
@@ -172,7 +167,7 @@ timer@0 {
};
};
-/* Preferred always-on timer for clocksource */
+/* Preferred timer for clockevent */
&timer12_target {
ti,no-reset-on-init;
ti,no-idle;
@@ -181,16 +176,6 @@ timer@0 {
};
};
-/* Preferred timer for clockevent */
-&timer2_target {
- ti,no-reset-on-init;
- ti,no-idle;
- timer@0 {
- assigned-clocks = <&gpt2_fck>;
- assigned-clock-parents = <&sys_ck>;
- };
-};
-
&twl_gpio {
ti,use-leds;
/*
diff --git a/drivers/clocksource/timer-ti-dm-systimer.c b/drivers/clocksource/timer-ti-dm-systimer.c
index 5c40ca1d4740..1fccb457fcc5 100644
--- a/drivers/clocksource/timer-ti-dm-systimer.c
+++ b/drivers/clocksource/timer-ti-dm-systimer.c
@@ -241,8 +241,7 @@ static void __init dmtimer_systimer_assign_alwon(void)
bool quirk_unreliable_oscillator = false;
/* Quirk unreliable 32 KiHz oscillator with incomplete dts */
- if (of_machine_is_compatible("ti,omap3-beagle-ab4") ||
- of_machine_is_compatible("timll,omap3-devkit8000")) {
+ if (of_machine_is_compatible("ti,omap3-beagle-ab4")) {
quirk_unreliable_oscillator = true;
counter_32k = -ENODEV;
}
--
2.34.1
^ permalink raw reply related
* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
From: Adam Ford @ 2022-01-25 19:08 UTC (permalink / raw)
To: Ezequiel Garcia
Cc: linux-media, Adam Ford-BE, Chris Healy, kernel test robot,
Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Greg Kroah-Hartman, Lucas Stach,
open list:HANTRO VPU CODEC DRIVER, devicetree, arm-soc,
Linux Kernel Mailing List, open list:STAGING SUBSYSTEM
In-Reply-To: <YfBJxmgwLGbVqGba@eze-laptop>
On Tue, Jan 25, 2022 at 1:04 PM Ezequiel Garcia
<ezequiel@vanguardiasur.com.ar> wrote:
>
> On Tue, Jan 25, 2022 at 11:11:24AM -0600, Adam Ford wrote:
> > With the Hantro G1 and G2 now setup to run independently, update
> > the device tree to allow both to operate. This requires the
> > vpu-blk-ctrl node to be configured. Since vpu-blk-ctrl needs
> > certain clock enabled to handle the gating of the G1 and G2
> > fuses, the clock-parents and clock-rates for the various VPU's
> > to be moved into the pgc_vpu because they cannot get re-parented
> > once enabled, and the pgc_vpu is the highest in the chain.
> >
> > Signed-off-by: Adam Ford <aford173@gmail.com>
> > Reported-by: kernel test robot <lkp@intel.com>
>
> It doesn't seem correct to have the Reported-by on this commit.
I didn't put it here, because I fixed it in a whole different patch
(Patch 1/11). This patch remains unchanged. I probably should have
put in the other patch, but I didn't think it was essential. Sorry
about that. Do I need to resend to just add the r-b tag?
adam
>
> Thanks,
> Ezequiel
>
> > Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > index 2df2510d0118..549b2440f55d 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
> > pgc_vpu: power-domain@6 {
> > #power-domain-cells = <0>;
> > reg = <IMX8M_POWER_DOMAIN_VPU>;
> > - clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> > + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>,
> > + <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> > + <&clk IMX8MQ_CLK_VPU_G2>,
> > + <&clk IMX8MQ_CLK_VPU_BUS>,
> > + <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > + <&clk IMX8MQ_VPU_PLL_OUT>,
> > + <&clk IMX8MQ_SYS1_PLL_800M>,
> > + <&clk IMX8MQ_VPU_PLL>;
> > + assigned-clock-rates = <600000000>,
> > + <600000000>,
> > + <800000000>,
> > + <0>;
> > };
> >
> > pgc_disp: power-domain@7 {
> > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
> > status = "disabled";
> > };
> >
> > - vpu: video-codec@38300000 {
> > - compatible = "nxp,imx8mq-vpu";
> > - reg = <0x38300000 0x10000>,
> > - <0x38310000 0x10000>,
> > - <0x38320000 0x10000>;
> > - reg-names = "g1", "g2", "ctrl";
> > - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > - interrupt-names = "g1", "g2";
> > + vpu_g1: video-codec@38300000 {
> > + compatible = "nxp,imx8mq-vpu-g1";
> > + reg = <0x38300000 0x10000>;
> > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> > + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
> > + };
> > +
> > + vpu_g2: video-codec@38310000 {
> > + compatible = "nxp,imx8mq-vpu-g2";
> > + reg = <0x38310000 0x10000>;
> > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
> > + };
> > +
> > + vpu_blk_ctrl: blk-ctrl@38320000 {
> > + compatible = "fsl,imx8mq-vpu-blk-ctrl";
> > + reg = <0x38320000 0x100>;
> > + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
> > + power-domain-names = "bus", "g1", "g2";
> > clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> > - <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> > - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> > - clock-names = "g1", "g2", "bus";
> > - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> > - <&clk IMX8MQ_CLK_VPU_G2>,
> > - <&clk IMX8MQ_CLK_VPU_BUS>,
> > - <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > - <&clk IMX8MQ_VPU_PLL_OUT>,
> > - <&clk IMX8MQ_SYS1_PLL_800M>,
> > - <&clk IMX8MQ_VPU_PLL>;
> > - assigned-clock-rates = <600000000>, <600000000>,
> > - <800000000>, <0>;
> > - power-domains = <&pgc_vpu>;
> > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > + clock-names = "g1", "g2";
> > + #power-domain-cells = <1>;
> > };
> >
> > pcie0: pcie@33800000 {
> > --
> > 2.32.0
> >
^ permalink raw reply
* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
From: Ezequiel Garcia @ 2022-01-25 19:04 UTC (permalink / raw)
To: Adam Ford
Cc: linux-media, aford, cphealy, kernel test robot, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
linux-arm-kernel, linux-kernel, linux-staging
In-Reply-To: <20220125171129.472775-8-aford173@gmail.com>
On Tue, Jan 25, 2022 at 11:11:24AM -0600, Adam Ford wrote:
> With the Hantro G1 and G2 now setup to run independently, update
> the device tree to allow both to operate. This requires the
> vpu-blk-ctrl node to be configured. Since vpu-blk-ctrl needs
> certain clock enabled to handle the gating of the G1 and G2
> fuses, the clock-parents and clock-rates for the various VPU's
> to be moved into the pgc_vpu because they cannot get re-parented
> once enabled, and the pgc_vpu is the highest in the chain.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Reported-by: kernel test robot <lkp@intel.com>
It doesn't seem correct to have the Reported-by on this commit.
Thanks,
Ezequiel
> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 2df2510d0118..549b2440f55d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
> pgc_vpu: power-domain@6 {
> #power-domain-cells = <0>;
> reg = <IMX8M_POWER_DOMAIN_VPU>;
> - clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>,
> + <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> + <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> + <&clk IMX8MQ_CLK_VPU_G2>,
> + <&clk IMX8MQ_CLK_VPU_BUS>,
> + <&clk IMX8MQ_VPU_PLL_BYPASS>;
> + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> + <&clk IMX8MQ_VPU_PLL_OUT>,
> + <&clk IMX8MQ_SYS1_PLL_800M>,
> + <&clk IMX8MQ_VPU_PLL>;
> + assigned-clock-rates = <600000000>,
> + <600000000>,
> + <800000000>,
> + <0>;
> };
>
> pgc_disp: power-domain@7 {
> @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
> status = "disabled";
> };
>
> - vpu: video-codec@38300000 {
> - compatible = "nxp,imx8mq-vpu";
> - reg = <0x38300000 0x10000>,
> - <0x38310000 0x10000>,
> - <0x38320000 0x10000>;
> - reg-names = "g1", "g2", "ctrl";
> - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "g1", "g2";
> + vpu_g1: video-codec@38300000 {
> + compatible = "nxp,imx8mq-vpu-g1";
> + reg = <0x38300000 0x10000>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
> + };
> +
> + vpu_g2: video-codec@38310000 {
> + compatible = "nxp,imx8mq-vpu-g2";
> + reg = <0x38310000 0x10000>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
> + };
> +
> + vpu_blk_ctrl: blk-ctrl@38320000 {
> + compatible = "fsl,imx8mq-vpu-blk-ctrl";
> + reg = <0x38320000 0x100>;
> + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
> + power-domain-names = "bus", "g1", "g2";
> clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> - <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> - clock-names = "g1", "g2", "bus";
> - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> - <&clk IMX8MQ_CLK_VPU_G2>,
> - <&clk IMX8MQ_CLK_VPU_BUS>,
> - <&clk IMX8MQ_VPU_PLL_BYPASS>;
> - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> - <&clk IMX8MQ_VPU_PLL_OUT>,
> - <&clk IMX8MQ_SYS1_PLL_800M>,
> - <&clk IMX8MQ_VPU_PLL>;
> - assigned-clock-rates = <600000000>, <600000000>,
> - <800000000>, <0>;
> - power-domains = <&pgc_vpu>;
> + <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> + clock-names = "g1", "g2";
> + #power-domain-cells = <1>;
> };
>
> pcie0: pcie@33800000 {
> --
> 2.32.0
>
^ permalink raw reply
* Re: [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference
From: Ezequiel Garcia @ 2022-01-25 18:57 UTC (permalink / raw)
To: Adam Ford
Cc: linux-media, aford, cphealy, Philipp Zabel, Mauro Carvalho Chehab,
Rob Herring, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Greg Kroah-Hartman, Lucas Stach,
linux-rockchip, devicetree, linux-arm-kernel, linux-kernel,
linux-staging
In-Reply-To: <20220125171129.472775-2-aford173@gmail.com>
On Tue, Jan 25, 2022 at 11:11:18AM -0600, Adam Ford wrote:
> The vpu is enabled by default, so there is no need to manually
> enable it.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> index 8aedcddfeab8..38ffcd145b33 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> @@ -272,10 +272,6 @@ &usdhc1 {
> status = "okay";
> };
>
> -&vpu {
> - status = "okay";
> -};
> -
> /* Attention: wdog reset forcing POR needs baseboard support */
> &wdog1 {
> status = "okay";
> --
> 2.32.0
>
^ permalink raw reply
* Re: [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference
From: Lucas Stach @ 2022-01-25 18:22 UTC (permalink / raw)
To: Adam Ford, linux-media
Cc: aford, cphealy, Ezequiel Garcia, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Greg Kroah-Hartman, linux-rockchip, devicetree, linux-arm-kernel,
linux-kernel, linux-staging
In-Reply-To: <20220125171129.472775-2-aford173@gmail.com>
Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> The vpu is enabled by default, so there is no need to manually
> enable it.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> index 8aedcddfeab8..38ffcd145b33 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> @@ -272,10 +272,6 @@ &usdhc1 {
> status = "okay";
> };
>
> -&vpu {
> - status = "okay";
> -};
> -
> /* Attention: wdog reset forcing POR needs baseboard support */
> &wdog1 {
> status = "okay";
^ permalink raw reply
* Re: [PATCH V4 11/11] arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders
From: Lucas Stach @ 2022-01-25 18:21 UTC (permalink / raw)
To: Adam Ford, linux-media
Cc: aford, cphealy, Ezequiel Garcia, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Greg Kroah-Hartman, linux-rockchip, devicetree, linux-arm-kernel,
linux-kernel, linux-staging
In-Reply-To: <20220125171129.472775-12-aford173@gmail.com>
Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> There are two decoders on the i.MX8M Mini controlled by the
> vpu-blk-ctrl. The G1 supports H264 and VP8 while the
> G2 support HEVC and VP9.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 0c7a72c51a31..98aec4421713 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1272,6 +1272,22 @@ gpu_2d: gpu@38008000 {
> power-domains = <&pgc_gpu>;
> };
>
> + vpu_g1: video-codec@38300000 {
> + compatible = "nxp,imx8mm-vpu-g1";
> + reg = <0x38300000 0x10000>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
> + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
> + };
> +
> + vpu_g2: video-codec@38310000 {
> + compatible = "nxp,imx8mq-vpu-g2";
> + reg = <0x38310000 0x10000>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
> + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
> + };
> +
> vpu_blk_ctrl: blk-ctrl@38330000 {
> compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
> reg = <0x38330000 0x100>;
> @@ -1282,6 +1298,12 @@ vpu_blk_ctrl: blk-ctrl@38330000 {
> <&clk IMX8MM_CLK_VPU_G2_ROOT>,
> <&clk IMX8MM_CLK_VPU_H1_ROOT>;
> clock-names = "g1", "g2", "h1";
> + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
> + <&clk IMX8MM_CLK_VPU_G2>;
> + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
> + <&clk IMX8MM_VPU_PLL_OUT>;
> + assigned-clock-rates = <600000000>,
> + <600000000>;
> #power-domain-cells = <1>;
> };
>
^ permalink raw reply
* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
From: Lucas Stach @ 2022-01-25 18:20 UTC (permalink / raw)
To: Adam Ford, linux-media
Cc: aford, cphealy, kernel test robot, Ezequiel Garcia, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Greg Kroah-Hartman, linux-rockchip, devicetree, linux-arm-kernel,
linux-kernel, linux-staging
In-Reply-To: <20220125171129.472775-8-aford173@gmail.com>
Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> With the Hantro G1 and G2 now setup to run independently, update
> the device tree to allow both to operate. This requires the
> vpu-blk-ctrl node to be configured. Since vpu-blk-ctrl needs
> certain clock enabled to handle the gating of the G1 and G2
> fuses, the clock-parents and clock-rates for the various VPU's
> to be moved into the pgc_vpu because they cannot get re-parented
> once enabled, and the pgc_vpu is the highest in the chain.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Reported-by: kernel test robot <lkp@intel.com>
> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 2df2510d0118..549b2440f55d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
> pgc_vpu: power-domain@6 {
> #power-domain-cells = <0>;
> reg = <IMX8M_POWER_DOMAIN_VPU>;
> - clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>,
> + <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> + <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> + <&clk IMX8MQ_CLK_VPU_G2>,
> + <&clk IMX8MQ_CLK_VPU_BUS>,
> + <&clk IMX8MQ_VPU_PLL_BYPASS>;
> + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> + <&clk IMX8MQ_VPU_PLL_OUT>,
> + <&clk IMX8MQ_SYS1_PLL_800M>,
> + <&clk IMX8MQ_VPU_PLL>;
> + assigned-clock-rates = <600000000>,
> + <600000000>,
> + <800000000>,
> + <0>;
> };
>
> pgc_disp: power-domain@7 {
> @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
> status = "disabled";
> };
>
> - vpu: video-codec@38300000 {
> - compatible = "nxp,imx8mq-vpu";
> - reg = <0x38300000 0x10000>,
> - <0x38310000 0x10000>,
> - <0x38320000 0x10000>;
> - reg-names = "g1", "g2", "ctrl";
> - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "g1", "g2";
> + vpu_g1: video-codec@38300000 {
> + compatible = "nxp,imx8mq-vpu-g1";
> + reg = <0x38300000 0x10000>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
> + };
> +
> + vpu_g2: video-codec@38310000 {
> + compatible = "nxp,imx8mq-vpu-g2";
> + reg = <0x38310000 0x10000>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
> + };
> +
> + vpu_blk_ctrl: blk-ctrl@38320000 {
> + compatible = "fsl,imx8mq-vpu-blk-ctrl";
> + reg = <0x38320000 0x100>;
> + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
> + power-domain-names = "bus", "g1", "g2";
> clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> - <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> - clock-names = "g1", "g2", "bus";
> - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> - <&clk IMX8MQ_CLK_VPU_G2>,
> - <&clk IMX8MQ_CLK_VPU_BUS>,
> - <&clk IMX8MQ_VPU_PLL_BYPASS>;
> - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> - <&clk IMX8MQ_VPU_PLL_OUT>,
> - <&clk IMX8MQ_SYS1_PLL_800M>,
> - <&clk IMX8MQ_VPU_PLL>;
> - assigned-clock-rates = <600000000>, <600000000>,
> - <800000000>, <0>;
> - power-domains = <&pgc_vpu>;
> + <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> + clock-names = "g1", "g2";
> + #power-domain-cells = <1>;
> };
>
> pcie0: pcie@33800000 {
^ permalink raw reply
* Re: [PATCH V4 08/11] arm64: dts: imx8mm: Fix VPU Hanging
From: Lucas Stach @ 2022-01-25 18:19 UTC (permalink / raw)
To: Adam Ford, linux-media
Cc: aford, cphealy, Ezequiel Garcia, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Greg Kroah-Hartman, linux-rockchip, devicetree, linux-arm-kernel,
linux-kernel, linux-staging
In-Reply-To: <20220125171129.472775-9-aford173@gmail.com>
Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> The vpumix power domain has a reset assigned to it, however
> when used, it causes a system hang. Testing has shown that
> it does not appear to be needed anywhere.
>
> Fixes: d39d4bb15310 ("arm64: dts: imx8mm: add GPC node")
> Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index f77f90ed416f..0c7a72c51a31 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -707,7 +707,6 @@ pgc_vpumix: power-domain@6 {
> clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
> assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
> assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
> - resets = <&src IMX8MQ_RESET_VPU_RESET>;
> };
>
> pgc_vpu_g1: power-domain@7 {
^ permalink raw reply
* [PATCH 2/2] dt-bindings: nvmem: cells: add MAC address cell
From: Rafał Miłecki @ 2022-01-25 18:01 UTC (permalink / raw)
To: Rob Herring, Srinivas Kandagatla, Michael Walle
Cc: linux-mtd, devicetree, linux-kernel, linux-arm-kernel, netdev,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra, Shawn Guo,
Li Yang, Frank Rowand, David S . Miller, Jakub Kicinski,
Ansuel Smith, Andrew Lunn, Florian Fainelli, Hauke Mehrtens,
Rafał Miłecki
In-Reply-To: <20220125180114.12286-1-zajec5@gmail.com>
From: Rafał Miłecki <rafal@milecki.pl>
This adds support for describing details of NVMEM cell containing MAC
address. Those are often device specific and could be nicely stored in
DT.
Initial documentation includes support for describing:
1. Cell data format (e.g. Broadcom's NVRAM uses ASCII to store MAC)
2. Reversed bytes flash (required for i.MX6/i.MX7 OCOTP support)
3. Source for multiple addresses (very common in home routers)
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
.../bindings/nvmem/cells/mac-address.yaml | 94 +++++++++++++++++++
1 file changed, 94 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/cells/mac-address.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/cells/mac-address.yaml b/Documentation/devicetree/bindings/nvmem/cells/mac-address.yaml
new file mode 100644
index 000000000000..f8d19e87cdf0
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/cells/mac-address.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/cells/mac-address.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVMEM cell containing a MAC address
+
+maintainers:
+ - Rafał Miłecki <rafal@milecki.pl>
+
+properties:
+ compatible:
+ const: mac-address
+
+ format:
+ description: |
+ Some NVMEM cells contain MAC in a non-binary format.
+
+ ASCII should be specified if MAC is string formatted like:
+ - "01:23:45:67:89:AB" (30 31 3a 32 33 3a 34 35 3a 36 37 3a 38 39 3a 41 42)
+ - "01-23-45-67-89-AB"
+ - "0123456789AB"
+ enum:
+ - ascii
+
+ reversed-bytes:
+ type: boolean
+ description: |
+ MAC is stored in reversed bytes order. Example:
+ Stored value: AB 89 67 45 23 01
+ Actual MAC: 01 23 45 67 89 AB
+
+ base-address:
+ type: boolean
+ description: |
+ Marks NVMEM cell as provider of multiple addresses that are relative to
+ the one actually stored physically. Respective addresses can be requested
+ by specifying cell index of NVMEM cell.
+
+allOf:
+ - $ref: cell.yaml#
+ - if:
+ required:
+ - base-address
+ then:
+ properties:
+ "#nvmem-cell-cells":
+ const: 1
+ required:
+ - "#nvmem-cell-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@f00000 {
+ compatible = "nvmem-cells";
+ label = "calibration";
+ reg = <0xf00000 0x100000>;
+ ranges = <0 0xf00000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mac@100 {
+ compatible = "mac-address";
+ reg = <0x100 0x6>;
+ };
+
+ mac@200 {
+ compatible = "mac-address";
+ reg = <0x200 0x6>;
+ reversed-bytes;
+ };
+
+ mac@300 {
+ compatible = "mac-address";
+ reg = <0x300 0x11>;
+ format = "ascii";
+ };
+
+ mac@400 {
+ compatible = "mac-address";
+ reg = <0x400 0x6>;
+ base-address;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
--
2.31.1
^ permalink raw reply related
* [PATCH 0/2] dt-bindings: nvmem: support describing cells
From: Rafał Miłecki @ 2022-01-25 18:01 UTC (permalink / raw)
To: Rob Herring, Srinivas Kandagatla, Michael Walle
Cc: linux-mtd, devicetree, linux-kernel, linux-arm-kernel, netdev,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra, Shawn Guo,
Li Yang, Frank Rowand, David S . Miller, Jakub Kicinski,
Ansuel Smith, Andrew Lunn, Florian Fainelli, Hauke Mehrtens,
Rafał Miłecki
From: Rafał Miłecki <rafal@milecki.pl>
Michael has recently posted a cleaned up patchset for NVMEM
transformations support:
[PATCH 0/8] nvmem: add ethernet address offset support
https://lore.kernel.org/lkml/20211228142549.1275412-1-michael@walle.cc/T/
https://patchwork.ozlabs.org/project/linux-mtd/list/?series=278644&state=*
I find it very important & fully support it. In home routers we very
often deal with just one MAC address that:
1. Is a base for calculating multiple Ethernet addresses
2. Can be stored in binary as well as ASCII format
I'd like to suggest just a slightly different solution though. I think
that using something like:
otp-1 {
compatible = "kontron,sl28-vpd", "user-otp";
#address-cells = <1>;
#size-cells = <1>;
base_mac_address: base-mac-address@17 {
#nvmem-cell-cells = <1>;
reg = <17 6>;
};
};
isn't clear enough and requires too much conditional code in Linux /
whatever implementation. DT doesn't make it clear which NVMEM cells
are used for what and how should be handled. That has to be hardcoded in
a Linux / whatever driver.
My idea is to add "compatible" & additional flags to NVMEM cells.
Example:
otp-1 {
compatible = "user-otp";
#address-cells = <1>;
#size-cells = <1>;
base_mac_address: base-mac-address@17 {
compatible = "mac-address";
reg = <17 6>;
#nvmem-cell-cells = <1>;
};
};
(for more examples see PATCH 2/2 and its mac-address.yaml .
Rafał Miłecki (2):
dt-bindings: nvmem: extract NVMEM cell to separated file
dt-bindings: nvmem: cells: add MAC address cell
.../devicetree/bindings/nvmem/cells/cell.yaml | 35 +++++++
.../bindings/nvmem/cells/mac-address.yaml | 94 +++++++++++++++++++
.../devicetree/bindings/nvmem/nvmem.yaml | 25 +----
3 files changed, 131 insertions(+), 23 deletions(-)
create mode 100644 Documentation/devicetree/bindings/nvmem/cells/cell.yaml
create mode 100644 Documentation/devicetree/bindings/nvmem/cells/mac-address.yaml
--
2.31.1
^ permalink raw reply
* [PATCH 1/2] dt-bindings: nvmem: extract NVMEM cell to separated file
From: Rafał Miłecki @ 2022-01-25 18:01 UTC (permalink / raw)
To: Rob Herring, Srinivas Kandagatla, Michael Walle
Cc: linux-mtd, devicetree, linux-kernel, linux-arm-kernel, netdev,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra, Shawn Guo,
Li Yang, Frank Rowand, David S . Miller, Jakub Kicinski,
Ansuel Smith, Andrew Lunn, Florian Fainelli, Hauke Mehrtens,
Rafał Miłecki
In-Reply-To: <20220125180114.12286-1-zajec5@gmail.com>
From: Rafał Miłecki <rafal@milecki.pl>
This will allow adding binding for more specific cells and reusing
(sharing) common code.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
.../devicetree/bindings/nvmem/cells/cell.yaml | 35 +++++++++++++++++++
.../devicetree/bindings/nvmem/nvmem.yaml | 25 ++-----------
2 files changed, 37 insertions(+), 23 deletions(-)
create mode 100644 Documentation/devicetree/bindings/nvmem/cells/cell.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/cells/cell.yaml b/Documentation/devicetree/bindings/nvmem/cells/cell.yaml
new file mode 100644
index 000000000000..5d62d0c8f1e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/cells/cell.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/cells/cell.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVMEM cell
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: NVMEM cell is a data entry of NVMEM device.
+
+properties:
+ reg:
+ maxItems: 1
+ description:
+ Offset and size in bytes within the storage device.
+
+ bits:
+ maxItems: 1
+ items:
+ items:
+ - minimum: 0
+ maximum: 7
+ description:
+ Offset in bit within the address range specified by reg.
+ - minimum: 1
+ description:
+ Size in bit within the address range specified by reg.
+
+required:
+ - reg
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/nvmem/nvmem.yaml b/Documentation/devicetree/bindings/nvmem/nvmem.yaml
index 456fb808100a..6b075c1db446 100644
--- a/Documentation/devicetree/bindings/nvmem/nvmem.yaml
+++ b/Documentation/devicetree/bindings/nvmem/nvmem.yaml
@@ -40,29 +40,8 @@ properties:
maxItems: 1
patternProperties:
- "@[0-9a-f]+(,[0-7])?$":
- type: object
-
- properties:
- reg:
- maxItems: 1
- description:
- Offset and size in bytes within the storage device.
-
- bits:
- maxItems: 1
- items:
- items:
- - minimum: 0
- maximum: 7
- description:
- Offset in bit within the address range specified by reg.
- - minimum: 1
- description:
- Size in bit within the address range specified by reg.
-
- required:
- - reg
+ "@[0-9a-f]+$":
+ $ref: cells/cell.yaml#
additionalProperties: true
--
2.31.1
^ permalink raw reply related
* [PATCH v2 3/3] drm/panel: Add MIPI DBI compatible SPI driver
From: Noralf Trønnes @ 2022-01-25 17:57 UTC (permalink / raw)
To: robh+dt, thierry.reding
Cc: sam, maxime, dave.stevenson, david, devicetree, dri-devel,
Noralf Trønnes
In-Reply-To: <20220125175700.37408-1-noralf@tronnes.org>
Add a driver that will work with most MIPI DBI compatible SPI panels.
This avoids adding a driver for every new MIPI DBI compatible controller
that is to be used by Linux. The 'compatible' Device Tree property with
a '.bin' suffix will be used to load a firmware file that contains the
controller configuration.
Example (driver will load sainsmart18.bin):
display@0 {
compatible = "sainsmart18", "panel-mipi-dbi-spi";
reg = <0>;
reset-gpios = <&gpio 25 0>;
dc-gpios = <&gpio 24 0>;
};
v2:
- Drop model property and use compatible instead (Rob)
- Add wiki entry in MAINTAINERS
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
---
MAINTAINERS | 8 +
drivers/gpu/drm/panel/Kconfig | 11 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-mipi-dbi.c | 394 +++++++++++++++++++++++++
4 files changed, 414 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-mipi-dbi.c
diff --git a/MAINTAINERS b/MAINTAINERS
index d03ad8da1f36..8baa98723bdc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6047,6 +6047,14 @@ T: git git://anongit.freedesktop.org/drm/drm-misc
F: Documentation/devicetree/bindings/display/multi-inno,mi0283qt.txt
F: drivers/gpu/drm/tiny/mi0283qt.c
+DRM DRIVER FOR MIPI DBI compatible panels
+M: Noralf Trønnes <noralf@tronnes.org>
+S: Maintained
+W: https://github.com/notro/panel-mipi-dbi/wiki
+T: git git://anongit.freedesktop.org/drm/drm-misc
+F: Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml
+F: drivers/gpu/drm/panel/panel-mipi-dbi.c
+
DRM DRIVER FOR MSM ADRENO GPU
M: Rob Clark <robdclark@gmail.com>
M: Sean Paul <sean@poorly.run>
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 434c2861bb40..1851cda5f877 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -274,6 +274,17 @@ config DRM_PANEL_LG_LG4573
Say Y here if you want to enable support for LG4573 RGB panel.
To compile this driver as a module, choose M here.
+config DRM_PANEL_MIPI_DBI
+ tristate "MIPI DBI compatible panel"
+ depends on SPI
+ depends on BACKLIGHT_CLASS_DEVICE
+ depends on DRM_KMS_HELPER
+ select DRM_KMS_CMA_HELPER
+ select DRM_MIPI_DBI
+ help
+ Say Y here if you want to enable support for MIPI DBI compatible panels.
+ To compile this driver as a module, choose M here.
+
config DRM_PANEL_NEC_NL8048HL11
tristate "NEC NL8048HL11 RGB panel"
depends on GPIOLIB && OF && SPI
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index d99fbbce49d1..a90c30459964 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W) += panel-leadtek-ltk050h3146w.o
obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829) += panel-leadtek-ltk500hd1829.o
obj-$(CONFIG_DRM_PANEL_LG_LB035Q02) += panel-lg-lb035q02.o
obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
+obj-$(CONFIG_DRM_PANEL_MIPI_DBI) += panel-mipi-dbi.o
obj-$(CONFIG_DRM_PANEL_NEC_NL8048HL11) += panel-nec-nl8048hl11.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35510) += panel-novatek-nt35510.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35950) += panel-novatek-nt35950.o
diff --git a/drivers/gpu/drm/panel/panel-mipi-dbi.c b/drivers/gpu/drm/panel/panel-mipi-dbi.c
new file mode 100644
index 000000000000..6e3dc2de21d2
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-mipi-dbi.c
@@ -0,0 +1,394 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DRM driver for MIPI DBI compatible display panels
+ *
+ * Copyright 2022 Noralf Trønnes
+ */
+
+#include <linux/backlight.h>
+#include <linux/delay.h>
+#include <linux/firmware.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/property.h>
+#include <linux/regulator/consumer.h>
+#include <linux/spi/spi.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_gem_atomic_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_managed.h>
+#include <drm/drm_mipi_dbi.h>
+#include <drm/drm_modeset_helper.h>
+#include <video/mipi_display.h>
+
+static const u8 panel_mipi_dbi_magic[15] = { 'M', 'I', 'P', 'I', ' ', 'D', 'B', 'I',
+ 0, 0, 0, 0, 0, 0, 0 };
+
+/*
+ * The display panel configuration is stored in a firmware file. The Device Tree 'compatible'
+ * property value with a '.bin' suffix is passed to request_firmware() to fetch this file.
+ */
+struct panel_mipi_dbi_config {
+ /* Magic string: panel_mipi_dbi_magic */
+ u8 magic[15];
+
+ /* Config file format version */
+ u8 file_format_version;
+
+ /* Width in pixels */
+ __be16 width;
+ /* Height in pixels */
+ __be16 height;
+
+ /* Width in millimeters (optional) */
+ __be16 width_mm;
+ /* Height in millimeters (optional) */
+ __be16 height_mm;
+
+ /* X-axis panel offset */
+ __be16 x_offset;
+ /* Y-axis panel offset */
+ __be16 y_offset;
+
+ /* 4 pad bytes, must be zero */
+ u8 pad[4];
+
+ /*
+ * Optional MIPI commands to execute when the display pipeline is enabled.
+ * This can be used to configure the display controller.
+ *
+ * The commands are stored in a byte array with the format:
+ * command, num_parameters, [ parameter, ...], command, ...
+ *
+ * Some commands require a pause before the next command can be received.
+ * Inserting a delay in the command sequence is done by using the NOP command with one
+ * parameter: delay in miliseconds (the No Operation command is part of the MIPI Display
+ * Command Set where it has no parameters).
+ *
+ * Example:
+ * command 0x11
+ * sleep 120ms
+ * command 0xb1 parameters 0x01, 0x2c, 0x2d
+ * command 0x29
+ *
+ * Byte sequence:
+ * 0x11 0x00
+ * 0x00 0x01 0x78
+ * 0xb1 0x03 0x01 0x2c 0x2d
+ * 0x29 0x00
+ */
+ u8 commands[];
+};
+
+struct panel_mipi_dbi_commands {
+ const u8 *buf;
+ size_t len;
+};
+
+static void panel_mipi_dbi_enable(struct drm_simple_display_pipe *pipe,
+ struct drm_crtc_state *crtc_state,
+ struct drm_plane_state *plane_state)
+{
+ struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
+ struct panel_mipi_dbi_commands *commands = dbidev->driver_private;
+ struct mipi_dbi *dbi = &dbidev->dbi;
+ unsigned int i = 0;
+ int ret, idx;
+
+ if (!drm_dev_enter(pipe->crtc.dev, &idx))
+ return;
+
+ drm_dbg(pipe->crtc.dev, "\n");
+
+ ret = mipi_dbi_poweron_conditional_reset(dbidev);
+ if (ret < 0)
+ goto out_exit;
+ if (ret == 1)
+ goto out_enable;
+
+ if (!commands)
+ goto out_enable;
+
+ while (i < commands->len) {
+ u8 command = commands->buf[i++];
+ u8 num_parameters = commands->buf[i++];
+ const u8 *parameters = &commands->buf[i];
+
+ if (command == 0x00 && num_parameters == 1)
+ msleep(parameters[0]);
+ else if (num_parameters)
+ mipi_dbi_command_stackbuf(dbi, command, parameters, num_parameters);
+ else
+ mipi_dbi_command(dbi, command);
+
+ i += num_parameters;
+ }
+
+out_enable:
+ mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
+out_exit:
+ drm_dev_exit(idx);
+}
+
+static const struct drm_simple_display_pipe_funcs panel_mipi_dbi_pipe_funcs = {
+ .enable = panel_mipi_dbi_enable,
+ .disable = mipi_dbi_pipe_disable,
+ .update = mipi_dbi_pipe_update,
+};
+
+DEFINE_DRM_GEM_CMA_FOPS(panel_mipi_dbi_fops);
+
+static const struct drm_driver panel_mipi_dbi_driver = {
+ .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
+ .fops = &panel_mipi_dbi_fops,
+ DRM_GEM_CMA_DRIVER_OPS_VMAP,
+ .debugfs_init = mipi_dbi_debugfs_init,
+ .name = "panel-mipi-dbi",
+ .desc = "MIPI DBI compatible display panel",
+ .date = "20220103",
+ .major = 1,
+ .minor = 0,
+};
+
+static int panel_mipi_dbi_parse_config(struct mipi_dbi_dev *dbidev,
+ struct drm_display_mode *mode,
+ const struct firmware *fw)
+{
+ const struct panel_mipi_dbi_config *config = (struct panel_mipi_dbi_config *)fw->data;
+ unsigned int width, height, x_offset, y_offset;
+ struct panel_mipi_dbi_commands *commands;
+ struct drm_device *drm = &dbidev->drm;
+ struct device *dev = dbidev->drm.dev;
+ size_t size = fw->size, commands_len;
+ unsigned int i = 0;
+
+ if (size < sizeof(*config)) {
+ dev_err(dev, "config: file size=%zu is too small\n", size);
+ return -EINVAL;
+ }
+
+ if (memcmp(config->magic, panel_mipi_dbi_magic, sizeof(config->magic))) {
+ dev_err(dev, "config: Bad magic: %15ph\n", config->magic);
+ return -EINVAL;
+ }
+
+ if (config->file_format_version != 1) {
+ dev_err(dev, "config: version=%u is not supported\n", config->file_format_version);
+ return -EINVAL;
+ }
+
+ width = be16_to_cpu(config->width);
+ height = be16_to_cpu(config->height);
+ x_offset = be16_to_cpu(config->x_offset);
+ y_offset = be16_to_cpu(config->y_offset);
+
+ drm_dbg(drm, "size=%zu version=%u\n", size, config->file_format_version);
+ drm_dbg(drm, "width=%u height=%u\n", width, height);
+ drm_dbg(drm, "x_offset=%u y_offset=%u\n", x_offset, y_offset);
+
+ if (width && height) {
+ struct drm_display_mode simple_mode = {
+ DRM_SIMPLE_MODE(width, height, be16_to_cpu(config->width_mm),
+ be16_to_cpu(config->height_mm))
+ };
+
+ *mode = simple_mode;
+ } else {
+ dev_err(dev, "config: width or height can't be zero\n");
+ return -EINVAL;
+ }
+
+ dbidev->left_offset = x_offset;
+ dbidev->top_offset = y_offset;
+
+ commands_len = size - sizeof(*config);
+ if (!commands_len)
+ return 0;
+
+ while ((i + 1) < commands_len) {
+ u8 command = config->commands[i++];
+ u8 num_parameters = config->commands[i++];
+ const u8 *parameters = &config->commands[i];
+
+ i += num_parameters;
+ if (i > commands_len) {
+ dev_err(dev, "config: command=0x%02x num_parameters=%u overflows\n",
+ command, num_parameters);
+ return -EINVAL;
+ }
+
+ if (command == 0x00 && num_parameters == 1)
+ drm_dbg(drm, "sleep %ums\n", parameters[0]);
+ else
+ drm_dbg(drm, "command %02x %*ph\n", command, num_parameters, parameters);
+ }
+
+ if (i != commands_len) {
+ dev_err(dev, "config: malformed command array\n");
+ return -EINVAL;
+ }
+
+ commands = devm_kzalloc(dev, sizeof(*commands), GFP_KERNEL);
+ if (!commands)
+ return -ENOMEM;
+
+ commands->len = commands_len;
+ commands->buf = devm_kmemdup(dev, config->commands, commands->len, GFP_KERNEL);
+ if (!commands->buf)
+ return -ENOMEM;
+
+ dbidev->driver_private = commands;
+
+ return 0;
+}
+
+static int panel_mipi_dbi_spi_probe(struct spi_device *spi)
+{
+ struct device *dev = &spi->dev;
+ struct drm_display_mode mode;
+ struct mipi_dbi_dev *dbidev;
+ const struct firmware *fw;
+ const char *compatible;
+ struct drm_device *drm;
+ struct property *prop;
+ bool fw_found = false;
+ struct mipi_dbi *dbi;
+ struct gpio_desc *dc;
+ char fw_name[40];
+ int ret;
+
+ dbidev = devm_drm_dev_alloc(dev, &panel_mipi_dbi_driver, struct mipi_dbi_dev, drm);
+ if (IS_ERR(dbidev))
+ return PTR_ERR(dbidev);
+
+ dbi = &dbidev->dbi;
+ drm = &dbidev->drm;
+
+ of_property_for_each_string(dev->of_node, "compatible", prop, compatible) {
+ snprintf(fw_name, sizeof(fw_name), "%s.bin", compatible);
+
+ ret = firmware_request_nowarn(&fw, fw_name, dev);
+ if (ret) {
+ drm_dbg(drm, "No config file found for compatible: '%s' (error=%d)\n",
+ compatible, ret);
+ continue;
+ }
+
+ ret = panel_mipi_dbi_parse_config(dbidev, &mode, fw);
+ release_firmware(fw);
+ if (ret)
+ return ret;
+
+ fw_found = true;
+ break;
+ }
+
+ if (!fw_found) {
+ dev_err(dev, "No config file found\n");
+ return -ENOENT;
+ }
+
+ dbidev->regulator = devm_regulator_get(dev, "power");
+ if (IS_ERR(dbidev->regulator))
+ return dev_err_probe(dev, PTR_ERR(dbidev->regulator),
+ "Failed to get regulator 'power'\n");
+
+ dbi->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(dbi->reset))
+ return dev_err_probe(dev, PTR_ERR(dbi->reset), "Failed to get GPIO 'reset'\n");
+
+ dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);
+ if (IS_ERR(dc))
+ return dev_err_probe(dev, PTR_ERR(dc), "Failed to get GPIO 'dc'\n");
+
+ dbidev->backlight = devm_of_find_backlight(dev);
+ if (IS_ERR(dbidev->backlight))
+ return dev_err_probe(dev, PTR_ERR(dbidev->backlight), "Failed to get backlight\n");
+
+ ret = mipi_dbi_spi_init(spi, dbi, dc);
+ if (ret)
+ return ret;
+
+ if (device_property_present(dev, "write-only"))
+ dbi->read_commands = NULL;
+
+ ret = mipi_dbi_dev_init(dbidev, &panel_mipi_dbi_pipe_funcs, &mode, 0);
+ if (ret)
+ return ret;
+
+ drm_mode_config_reset(drm);
+
+ ret = drm_dev_register(drm, 0);
+ if (ret)
+ return ret;
+
+ spi_set_drvdata(spi, drm);
+
+ drm_fbdev_generic_setup(drm, 0);
+
+ return 0;
+}
+
+static int panel_mipi_dbi_spi_remove(struct spi_device *spi)
+{
+ struct drm_device *drm = spi_get_drvdata(spi);
+
+ drm_dev_unplug(drm);
+ drm_atomic_helper_shutdown(drm);
+
+ return 0;
+}
+
+static void panel_mipi_dbi_spi_shutdown(struct spi_device *spi)
+{
+ drm_atomic_helper_shutdown(spi_get_drvdata(spi));
+}
+
+static int __maybe_unused panel_mipi_dbi_pm_suspend(struct device *dev)
+{
+ return drm_mode_config_helper_suspend(dev_get_drvdata(dev));
+}
+
+static int __maybe_unused panel_mipi_dbi_pm_resume(struct device *dev)
+{
+ drm_mode_config_helper_resume(dev_get_drvdata(dev));
+
+ return 0;
+}
+
+static const struct dev_pm_ops panel_mipi_dbi_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(panel_mipi_dbi_pm_suspend, panel_mipi_dbi_pm_resume)
+};
+
+static const struct of_device_id panel_mipi_dbi_spi_of_match[] = {
+ { .compatible = "panel-mipi-dbi-spi" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, panel_mipi_dbi_spi_of_match);
+
+static const struct spi_device_id panel_mipi_dbi_spi_id[] = {
+ { "panel-mipi-dbi-spi", 0 },
+ { },
+};
+MODULE_DEVICE_TABLE(spi, panel_mipi_dbi_spi_id);
+
+static struct spi_driver panel_mipi_dbi_spi_driver = {
+ .driver = {
+ .name = "panel-mipi-dbi-spi",
+ .owner = THIS_MODULE,
+ .of_match_table = panel_mipi_dbi_spi_of_match,
+ .pm = &panel_mipi_dbi_pm_ops,
+ },
+ .id_table = panel_mipi_dbi_spi_id,
+ .probe = panel_mipi_dbi_spi_probe,
+ .remove = panel_mipi_dbi_spi_remove,
+ .shutdown = panel_mipi_dbi_spi_shutdown,
+};
+module_spi_driver(panel_mipi_dbi_spi_driver);
+
+MODULE_DESCRIPTION("MIPI DBI compatible display panel driver");
+MODULE_AUTHOR("Noralf Trønnes");
+MODULE_LICENSE("GPL");
--
2.33.0
^ permalink raw reply related
* [PATCH v2 0/3] drm/panel: Add MIPI DBI compatible SPI driver
From: Noralf Trønnes @ 2022-01-25 17:56 UTC (permalink / raw)
To: robh+dt, thierry.reding
Cc: sam, maxime, dave.stevenson, david, devicetree, dri-devel,
Noralf Trønnes
Hi,
This patchset adds a driver that will work with most MIPI DBI compatible
SPI panels out there.
It's a follow up on 'drm/tiny/st7735r: Match up with staging/fbtft
driver'[1] which aimed at making the st7735r driver work with all panels
adding DT properties.
Maxime gave[2] a good overview of the situation with these displays and
proposed to make a driver that works with all MIPI DBI compatible
controllers and use a firmware file to provide the controller setup for
a particular panel.
Main change since previous version:
- Drop model property and use the compatible property instead (Rob)
Noralf.
[1] https://lore.kernel.org/dri-devel/20211124150757.17929-1-noralf@tronnes.org/
[2] https://lore.kernel.org/dri-devel/20211129093946.xhp22mvdut3m67sc@houat/
Noralf Trønnes (3):
dt-bindings: display: add bindings for MIPI DBI compatible SPI panels
drm/mipi-dbi: Add driver_private member to struct mipi_dbi_dev
drm/panel: Add MIPI DBI compatible SPI driver
.../display/panel/panel-mipi-dbi-spi.yaml | 59 +++
MAINTAINERS | 8 +
drivers/gpu/drm/panel/Kconfig | 11 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-mipi-dbi.c | 394 ++++++++++++++++++
include/drm/drm_mipi_dbi.h | 2 +
6 files changed, 475 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml
create mode 100644 drivers/gpu/drm/panel/panel-mipi-dbi.c
--
2.33.0
^ permalink raw reply
* [PATCH v2 1/3] dt-bindings: display: add bindings for MIPI DBI compatible SPI panels
From: Noralf Trønnes @ 2022-01-25 17:56 UTC (permalink / raw)
To: robh+dt, thierry.reding
Cc: sam, maxime, dave.stevenson, david, devicetree, dri-devel,
Noralf Trønnes
In-Reply-To: <20220125175700.37408-1-noralf@tronnes.org>
Add binding for MIPI DBI compatible SPI panels.
v2:
- Fix path for panel-common.yaml
- Use unevaluatedProperties
- Drop properties which are in the allOf section
- Drop model property (Rob)
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
---
.../display/panel/panel-mipi-dbi-spi.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml
diff --git a/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml b/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml
new file mode 100644
index 000000000000..b7cbeea0f8aa
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/panel-mipi-dbi-spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPI DBI SPI Panels Device Tree Bindings
+
+maintainers:
+ - Noralf Trønnes <noralf@tronnes.org>
+
+description:
+ This binding is for display panels using a MIPI DBI controller
+ in SPI mode.
+
+allOf:
+ - $ref: panel-common.yaml#
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+ compatible:
+ const: panel-mipi-dbi-spi
+
+ write-only:
+ type: boolean
+ description:
+ Controller is not readable (ie. MISO is not wired up).
+
+ dc-gpios:
+ maxItems: 1
+ description: |
+ Controller data/command selection (D/CX) in 4-line SPI mode.
+ If not set, the controller is in 3-line SPI mode.
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ display@0{
+ compatible = "panel-mipi-dbi-spi";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ dc-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+ write-only;
+ };
+ };
+
+...
--
2.33.0
^ permalink raw reply related
* [PATCH v2 2/3] drm/mipi-dbi: Add driver_private member to struct mipi_dbi_dev
From: Noralf Trønnes @ 2022-01-25 17:56 UTC (permalink / raw)
To: robh+dt, thierry.reding
Cc: sam, maxime, dave.stevenson, david, devicetree, dri-devel,
Noralf Trønnes
In-Reply-To: <20220125175700.37408-1-noralf@tronnes.org>
devm_drm_dev_alloc() can't allocate structures that embed a structure
which then again embeds drm_device. Workaround this by adding a
driver_private pointer to struct mipi_dbi_dev which the driver can use for
its additional state.
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
---
include/drm/drm_mipi_dbi.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/drm_mipi_dbi.h b/include/drm/drm_mipi_dbi.h
index 6fe13cce2670..76aac6decfde 100644
--- a/include/drm/drm_mipi_dbi.h
+++ b/include/drm/drm_mipi_dbi.h
@@ -130,6 +130,8 @@ struct mipi_dbi_dev {
* @dbi: MIPI DBI interface
*/
struct mipi_dbi dbi;
+
+ void *driver_private;
};
static inline struct mipi_dbi_dev *drm_to_mipi_dbi_dev(struct drm_device *drm)
--
2.33.0
^ permalink raw reply related
* Re: [PATCH net-next v2 2/2] net: dsa: microchip: Add property to disable reference clock
From: Andrew Lunn @ 2022-01-25 17:32 UTC (permalink / raw)
To: Robert Hancock
Cc: netdev, woojung.huh, UNGLinuxDriver, vivien.didelot, f.fainelli,
olteanv, davem, kuba, robh+dt, marex, devicetree
In-Reply-To: <20220125171140.258190-3-robert.hancock@calian.com>
> dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
> "microchip,synclko-125");
> + dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
> + "microchip,synclko-disable");
It seems like microchip,synclko-125 and microchip,synclko-disable are
mutually exclusive? Please add an -EINVAL if both a present.
This should also be mentioned in the binding document.
Thanks
Andrew
^ permalink raw reply
* Re: [PATCH v5 00/16] Add support for Tesla Full Self-Driving (FSD) SoC
From: Krzysztof Kozlowski @ 2022-01-25 17:26 UTC (permalink / raw)
To: Alim Akhtar, linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, s.nawrocki, linux-samsung-soc,
pankaj.dubey, sboyd
In-Reply-To: <d9682f16-13b7-b6dc-5afd-b2d319143de5@canonical.com>
On 25/01/2022 18:12, Krzysztof Kozlowski wrote:
> On 24/01/2022 15:16, Alim Akhtar wrote:
>> Adds basic support for the Tesla Full Self-Driving (FSD)
>> SoC. This SoC contains three clusters of four Cortex-A72 CPUs,
>> as well as several IPs.
>>
>> Patches 1 to 9 provide support for the clock controller
>> (which is designed similarly to Exynos SoCs).
>>
>> The remaining changes provide pinmux support, initial device tree support.
>>
>> - Changes since v4
>> * fixed 'make dtbs_check' warnings on patch 14/16
>>
>> - Changes since v3
>> * Addressed Stefen's review comments on patch 14/16
>> * Fixed kernel test robot warning on patch 04/16
>> * rebsaed this series on Krzysztof's pinmux new binding schema work [1]
>>
>> - Changes since v2
>> * Addressed Krzysztof's and Stephen's review comments
>> * Added Reviewed-by and Acked-by tags
>> * Rebased on next-20220120
>>
>> - Changes since v1
>> * fixed make dt_binding_check error as pointed by Rob
>> * Addressed Krzysztof's and Rob's review comments
>> * Added Reviewed-by and Acked-by tags
>> * Dropped SPI, MCT and ADC from this series (to be posted in small sets)
>>
>> NOTE: These patches are based on Krzysztof's pinmux for-next branch
>> commit 832ae134ccc1 ("pinctrl: samsung: add support for Exynos850 and ExynosAutov9 wake-ups")
>> [1] https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git/log/?h=for-next
>>
>>
>
> Thanks, applied DTS/soc and pinctrl patches.
>
> I expect Sylwester will pick up the clock ones. Otherwise please let me
> know to pick it up as well.
I forgot that clock macros are used in DTS. This does not compile and I
cannot take drivers into DTS branch.
Alim,
DTS changes dropped. Please resend with the same trick we did for
Exynos850 board - hard-coded clock IDs as defines. See:
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git/diff/arch/arm64/boot/dts/exynos/exynos850.dtsi?h=samsung-dt64-5.17-2&id=e3493220fd3e474abcdcefbe14fb60485097ce06
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v15 13/13] MAINTAINERS: add AMPHION VPU CODEC V4L2 driver entry
From: Joe Perches @ 2022-01-25 17:19 UTC (permalink / raw)
To: Ming Qian, mchehab, shawnguo, robh+dt, s.hauer
Cc: hverkuil-cisco, kernel, festevam, linux-imx, aisheng.dong,
linux-media, linux-kernel, devicetree, linux-arm-kernel
In-Reply-To: <2f695f6a597a4372842d75105b654fba6db27d59.1643077283.git.ming.qian@nxp.com>
On Tue, 2022-01-25 at 15:11 +0800, Ming Qian wrote:
> Add AMPHION VPU CODEC v4l2 driver entry
[]
> diff --git a/MAINTAINERS b/MAINTAINERS
[]
> @@ -13913,6 +13913,15 @@ S: Maintained
> F: Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
> F: drivers/media/platform/imx-jpeg
>
> +AMPHION VPU CODEC V4L2 DRIVER
> +M: Ming Qian <ming.qian@nxp.com>
> +M: Shijie Qin <shijie.qin@nxp.com>
> +M: Zhou Peng <eagle.zhou@nxp.com>
> +L: linux-media@vger.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/media/amphion,vpu.yaml
> +F: drivers/media/platform/amphion/
> +
Alphabetic section ordering please.
> NZXT-KRAKEN2 HARDWARE MONITORING DRIVER
> M: Jonas Malaco <jonas@protocubo.io>
> L: linux-hwmon@vger.kernel.org
^ permalink raw reply
* Re: [PATCH v5 00/16] Add support for Tesla Full Self-Driving (FSD) SoC
From: Krzysztof Kozlowski @ 2022-01-25 17:12 UTC (permalink / raw)
To: Alim Akhtar, linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, s.nawrocki, linux-samsung-soc,
pankaj.dubey, sboyd
In-Reply-To: <20220124141644.71052-1-alim.akhtar@samsung.com>
On 24/01/2022 15:16, Alim Akhtar wrote:
> Adds basic support for the Tesla Full Self-Driving (FSD)
> SoC. This SoC contains three clusters of four Cortex-A72 CPUs,
> as well as several IPs.
>
> Patches 1 to 9 provide support for the clock controller
> (which is designed similarly to Exynos SoCs).
>
> The remaining changes provide pinmux support, initial device tree support.
>
> - Changes since v4
> * fixed 'make dtbs_check' warnings on patch 14/16
>
> - Changes since v3
> * Addressed Stefen's review comments on patch 14/16
> * Fixed kernel test robot warning on patch 04/16
> * rebsaed this series on Krzysztof's pinmux new binding schema work [1]
>
> - Changes since v2
> * Addressed Krzysztof's and Stephen's review comments
> * Added Reviewed-by and Acked-by tags
> * Rebased on next-20220120
>
> - Changes since v1
> * fixed make dt_binding_check error as pointed by Rob
> * Addressed Krzysztof's and Rob's review comments
> * Added Reviewed-by and Acked-by tags
> * Dropped SPI, MCT and ADC from this series (to be posted in small sets)
>
> NOTE: These patches are based on Krzysztof's pinmux for-next branch
> commit 832ae134ccc1 ("pinctrl: samsung: add support for Exynos850 and ExynosAutov9 wake-ups")
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git/log/?h=for-next
>
>
Thanks, applied DTS/soc and pinctrl patches.
I expect Sylwester will pick up the clock ones. Otherwise please let me
know to pick it up as well.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v10 1/3] pwm: driver for qualcomm ipq6018 pwm block
From: Uwe Kleine-König @ 2022-01-25 17:15 UTC (permalink / raw)
To: Baruch Siach
Cc: Thierry Reding, Andy Gross, Bjorn Andersson, Balaji Prakash J,
Rob Herring, Robert Marko, Kathiravan T, linux-pwm, devicetree,
linux-arm-msm, linux-arm-kernel
In-Reply-To: <87pmof93wf.fsf@tarshish>
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Hello Baruch,
On Tue, Jan 25, 2022 at 06:22:45PM +0200, Baruch Siach wrote:
> On Tue, Jan 25 2022, Uwe Kleine-König wrote:
> > On Tue, Jan 25, 2022 at 03:03:08PM +0200, Baruch Siach wrote:
> >> On Wed, Jan 19 2022, Uwe Kleine-König wrote:
> >> > The task here is to calculate the biggest pwm_div for a given pre_div
> >> > such that
> >> >
> >> >
> >> > (pre_div + 1) * (pwm_div + 1) * NSEC_PER_SEC
> >> > -------------------------------------------- <= period_ns
> >> > rate
> >> >
> >> > right?
> >> >
> >> > This is equivalent to:
> >> >
> >> > period_ns * rate
> >> > pre_div <= ---------------------------- - 1
> >> > (pre_div + 1) * NSEC_PER_SEC
> >> >
> >> > As pre_div is integer, rounding down should be fine?!
> >>
> >> I can't follow. With round down (as in v8) the result is always:
> >>
> >> NSEC_PER_SEC * (pre_div + 1) * (pwm_div + 1) <= period_rate
> >
> > Yes, that's the condition that a valid configuration should fulfill
> > because then the configured period is never bigger than the requested
> > period.
> >
> >> As a result, 'diff' calculation below will always produce diff <= 0. When
> >> there is no diff == 0 result (bingo) we get IPQ_PWM_MAX_DIV in both best_
> >> values at the end of the loop.
> >
> > Looking again, your check is wrong. I think you need:
> >
> > diff = period_rate - NSEC_PER_SEC * (pre_div + 1) * (pwm_div + 1)
> >
> > . Given the calculations for pre_div and pwm_div this should never be
> > negative and you should pick values that minimize diff.
>
> So, if I understand correctly, you suggest to leave round up as in v10,
> and invert the diff calculation. Is that correct?
If you agree that this results in the intended setting and keeps dmesg
clean even with PWM_DEBUG enabled: yes.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
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^ permalink raw reply
* [PATCH V4 11/11] arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders
From: Adam Ford @ 2022-01-25 17:11 UTC (permalink / raw)
To: linux-media
Cc: aford, cphealy, Adam Ford, Ezequiel Garcia, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
linux-arm-kernel, linux-kernel, linux-staging
In-Reply-To: <20220125171129.472775-1-aford173@gmail.com>
There are two decoders on the i.MX8M Mini controlled by the
vpu-blk-ctrl. The G1 supports H264 and VP8 while the
G2 support HEVC and VP9.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 0c7a72c51a31..98aec4421713 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1272,6 +1272,22 @@ gpu_2d: gpu@38008000 {
power-domains = <&pgc_gpu>;
};
+ vpu_g1: video-codec@38300000 {
+ compatible = "nxp,imx8mm-vpu-g1";
+ reg = <0x38300000 0x10000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
+ power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
+ };
+
+ vpu_g2: video-codec@38310000 {
+ compatible = "nxp,imx8mq-vpu-g2";
+ reg = <0x38310000 0x10000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
+ power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
+ };
+
vpu_blk_ctrl: blk-ctrl@38330000 {
compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
reg = <0x38330000 0x100>;
@@ -1282,6 +1298,12 @@ vpu_blk_ctrl: blk-ctrl@38330000 {
<&clk IMX8MM_CLK_VPU_G2_ROOT>,
<&clk IMX8MM_CLK_VPU_H1_ROOT>;
clock-names = "g1", "g2", "h1";
+ assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
+ <&clk IMX8MM_CLK_VPU_G2>;
+ assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
+ <&clk IMX8MM_VPU_PLL_OUT>;
+ assigned-clock-rates = <600000000>,
+ <600000000>;
#power-domain-cells = <1>;
};
--
2.32.0
^ permalink raw reply related
* Re: (subset) [PATCH v5 15/16] arm64: dts: fsd: Add initial pinctrl support
From: Krzysztof Kozlowski @ 2022-01-25 17:11 UTC (permalink / raw)
To: linux-arm-kernel, Alim Akhtar, linux-kernel
Cc: Krzysztof Kozlowski, devicetree, linus.walleij, sboyd, olof, soc,
linux-fsd, linux-clk, arnd, linux-samsung-soc, Shashank Prashar,
catalin.marinas, Aswani Reddy, robh+dt, pankaj.dubey, s.nawrocki
In-Reply-To: <20220124141644.71052-16-alim.akhtar@samsung.com>
On Mon, 24 Jan 2022 19:46:43 +0530, Alim Akhtar wrote:
> Add initial pin configuration nodes for FSD SoC.
>
>
Applied, thanks!
[15/16] arm64: dts: fsd: Add initial pinctrl support
commit: 773d685fd406514af4b365aaa54fe493cf523602
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
^ permalink raw reply
* Re: (subset) [PATCH v5 16/16] arm64: defconfig: Enable Tesla FSD SoC
From: Krzysztof Kozlowski @ 2022-01-25 17:11 UTC (permalink / raw)
To: linux-arm-kernel, Alim Akhtar, linux-kernel
Cc: Krzysztof Kozlowski, linus.walleij, linux-fsd, devicetree, olof,
soc, sboyd, linux-clk, arnd, linux-samsung-soc, catalin.marinas,
robh+dt, pankaj.dubey, s.nawrocki
In-Reply-To: <20220124141644.71052-17-alim.akhtar@samsung.com>
On Mon, 24 Jan 2022 19:46:44 +0530, Alim Akhtar wrote:
> This patch enables the Tesla FSD SoC in arm64 defconfig.
>
>
Applied, thanks!
[16/16] arm64: defconfig: Enable Tesla FSD SoC
commit: aeb62e360c0fffd9cf218a314647d0c7254becbe
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
^ permalink raw reply
* [PATCH V4 00/11] media: hantro: imx8mq/imx8mm: Let VPU decoders get controlled by vpu-blk-ctrl
From: Adam Ford @ 2022-01-25 17:11 UTC (permalink / raw)
To: linux-media
Cc: aford, cphealy, Adam Ford, Ezequiel Garcia, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
linux-arm-kernel, linux-kernel, linux-staging
Both the i.MX8MQ and i.MX8MM have G1 and G2 decoders.
The two decoders are similar, but the imx8mm lacks the
post-processor, so they will have distinct compatible flags.
From what I can tell, the G2 decoder wasn't working, so splitting
the i.MX8MQ VPU into G1 and G2 makes it easier to control them
independently since the TRM of both the i.MX8MQ and
i.MX8MM list them as distinct IP blocks. This also allowed G2 to
become available.
With them being split, the power-domain can shift to the
vpu-blk-ctrl which is available on both i.MX8MQ and i.MX8MM,
but some of bits are different, so they'll have separate bindings.
Lastly, with the G1 and G2 operational, enable the i.MX8MM.
On the i.MX8MM, the clock speed of 600MHz was chosen to match
the default of the kernel repo from NXP and can be overwritten
by board files for anyone who under/over volts the power rail.
There seems to be some disagreement between the TRM and the Datasheet
for the imx8mq as to whether the speed should be 300MHz (TRM) or
600MHz (datasheet), so feedback from NXP would be very much
appreciated.
The repo used as the starting point was:
5.17-rc1
Fluster was run on both i.MX8MM and i.MX8MQ
At 600 MHz, the i.MX8MM had the following:
./fluster.py run -d GStreamer-VP8-V4L2SL-Gst1.0
Ran 55/61 tests successfully in 8.299 secs
./fluster.py run -dGStreamer-H.264-V4L2SL-Gst1.0
Ran 90/135 tests successfully in 71.200 secs
./fluster.py run -d GStreamer-VP9-V4L2SL-Gst1.0
Ran 139/303 tests successfully in 218.079 secs
The i.MX8MQ had the following:
./fluster.py run -d GStreamer-VP8-V4L2SL-Gst1.0
Ran 55/61 tests successfully in 7.732 secs
./fluster.py run -dGStreamer-H.264-V4L2SL-Gst1.0
Ran 90/135 tests successfully in 58.558 secs
./fluster.py run -d GStreamer-VP9-V4L2SL-Gst1.0
Ran 144/303 tests successfully in 271.373 secs
V4: Add a comment and a notice based on feedback from Ezequiel Garcia
if the older compatible flag is used.
Add new patch which removes a reference to vpu from imx8mq-tqma8mq
because the VPU is enabled by default and it's not needed. Without
this change, its device tree would fail to build.
V3: Rebase on 5.17-RC1.
Remove imx8mm-vpu-g2 since it's identical to imx8mq-vpu-g2
Remove unnecessary examples in YAML files.
Remove some unused variables.
V2: Remove references to legacy dt-binding from YAML, but keep
it in the driver so older device trees can still be used.
Fix typos in YAML
Remove reg-names, interrupt-names, and clock-names from YAML,
since each node will only have one of each, they're not necessary
Add Fluster scores to cover letter for i.MX8MQ
Adam Ford (8):
arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference
dt-bindings: media: nxp, imx8mq-vpu: Split G1 and G2 nodes
media: hantro: Allow i.MX8MQ G1 and G2 to run independently
arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
arm64: dts: imx8mm: Fix VPU Hanging
dt-bindings: media: nxp, imx8mq-vpu: Add support for G1 on imx8mm
media: hantro: Add support for i.MX8MM Hantro-G1
arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders
Lucas Stach (3):
dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains
dt-bindings: soc: add binding for i.MX8MQ VPU blk-ctrl
soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl
.../bindings/media/nxp,imx8mq-vpu.yaml | 68 ++++++++----------
.../soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml | 71 +++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 23 +++++-
.../boot/dts/freescale/imx8mq-tqma8mq.dtsi | 4 --
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 63 +++++++++-------
drivers/soc/imx/imx8m-blk-ctrl.c | 66 +++++++++++++++++
drivers/staging/media/hantro/hantro_drv.c | 11 +++
drivers/staging/media/hantro/hantro_hw.h | 2 +
drivers/staging/media/hantro/imx8m_vpu_hw.c | 62 ++++++++++++----
include/dt-bindings/power/imx8mq-power.h | 3 +
10 files changed, 292 insertions(+), 81 deletions(-)
create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml
base-commit: e783362eb54cd99b2cac8b3a9aeac942e6f6ac07
--
2.32.0
^ permalink raw reply
* [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference
From: Adam Ford @ 2022-01-25 17:11 UTC (permalink / raw)
To: linux-media
Cc: aford, cphealy, Adam Ford, Ezequiel Garcia, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
linux-arm-kernel, linux-kernel, linux-staging
In-Reply-To: <20220125171129.472775-1-aford173@gmail.com>
The vpu is enabled by default, so there is no need to manually
enable it.
Signed-off-by: Adam Ford <aford173@gmail.com>
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
index 8aedcddfeab8..38ffcd145b33 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
@@ -272,10 +272,6 @@ &usdhc1 {
status = "okay";
};
-&vpu {
- status = "okay";
-};
-
/* Attention: wdog reset forcing POR needs baseboard support */
&wdog1 {
status = "okay";
--
2.32.0
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