* [PATCH 2/2] ARM: dts: Use 32KiHz oscillator on devkit8000
From: Anthoine Bourgeois @ 2022-01-25 19:11 UTC (permalink / raw)
To: linux-omap, devicetree, tony, bcousson; +Cc: robh+dt, Anthoine Bourgeois
In-Reply-To: <20220125191139.2429555-1-anthoine.bourgeois@gmail.com>
Devkit8000 board seems to always used 32k_counter as clocksource.
Restore this behavior.
If clocksource is back to 32k_counter, timer12 is now the clockevent
source (as before) and timer2 is not longer needed here.
This commit fixes the same issue observed with commit 23885389dbbb
("ARM: dts: Fix timer regression for beagleboard revision c") when sleep
is blocked until hitting keys over serial console.
Fixed: aba1ad05da08 ("clocksource/drivers/timer-ti-dm: Add clockevent and clocksource support")
Fixed: e428e250fde6 ("ARM: dts: Configure system timers for omap3")
Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
---
arch/arm/boot/dts/omap3-devkit8000-common.dtsi | 17 +----------------
drivers/clocksource/timer-ti-dm-systimer.c | 3 +--
2 files changed, 2 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
index f5197bb31ed8..54cd37336be7 100644
--- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
+++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
@@ -158,11 +158,6 @@ &mmc3 {
status = "disabled";
};
-/* Unusable as clocksource because of unreliable oscillator */
-&counter32k {
- status = "disabled";
-};
-
/* Unusable as clockevent because if unreliable oscillator, allow to idle */
&timer1_target {
/delete-property/ti,no-reset-on-init;
@@ -172,7 +167,7 @@ timer@0 {
};
};
-/* Preferred always-on timer for clocksource */
+/* Preferred timer for clockevent */
&timer12_target {
ti,no-reset-on-init;
ti,no-idle;
@@ -181,16 +176,6 @@ timer@0 {
};
};
-/* Preferred timer for clockevent */
-&timer2_target {
- ti,no-reset-on-init;
- ti,no-idle;
- timer@0 {
- assigned-clocks = <&gpt2_fck>;
- assigned-clock-parents = <&sys_ck>;
- };
-};
-
&twl_gpio {
ti,use-leds;
/*
diff --git a/drivers/clocksource/timer-ti-dm-systimer.c b/drivers/clocksource/timer-ti-dm-systimer.c
index 5c40ca1d4740..1fccb457fcc5 100644
--- a/drivers/clocksource/timer-ti-dm-systimer.c
+++ b/drivers/clocksource/timer-ti-dm-systimer.c
@@ -241,8 +241,7 @@ static void __init dmtimer_systimer_assign_alwon(void)
bool quirk_unreliable_oscillator = false;
/* Quirk unreliable 32 KiHz oscillator with incomplete dts */
- if (of_machine_is_compatible("ti,omap3-beagle-ab4") ||
- of_machine_is_compatible("timll,omap3-devkit8000")) {
+ if (of_machine_is_compatible("ti,omap3-beagle-ab4")) {
quirk_unreliable_oscillator = true;
counter_32k = -ENODEV;
}
--
2.34.1
^ permalink raw reply related
* [PATCH 1/2] ARM: dts: switch timer config to common devkit8000 devicetree
From: Anthoine Bourgeois @ 2022-01-25 19:11 UTC (permalink / raw)
To: linux-omap, devicetree, tony, bcousson; +Cc: robh+dt, Anthoine Bourgeois
This patch allow lcd43 and lcd70 flavors to benefit from timer
evolution.
Fixed: e428e250fde6 ("ARM: dts: Configure system timers for omap3")
Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
---
.../arm/boot/dts/omap3-devkit8000-common.dtsi | 33 +++++++++++++++++++
arch/arm/boot/dts/omap3-devkit8000.dts | 33 -------------------
2 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
index 5e55198e4576..f5197bb31ed8 100644
--- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
+++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
@@ -158,6 +158,39 @@ &mmc3 {
status = "disabled";
};
+/* Unusable as clocksource because of unreliable oscillator */
+&counter32k {
+ status = "disabled";
+};
+
+/* Unusable as clockevent because if unreliable oscillator, allow to idle */
+&timer1_target {
+ /delete-property/ti,no-reset-on-init;
+ /delete-property/ti,no-idle;
+ timer@0 {
+ /delete-property/ti,timer-alwon;
+ };
+};
+
+/* Preferred always-on timer for clocksource */
+&timer12_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ /* Always clocked by secure_32k_fck */
+ };
+};
+
+/* Preferred timer for clockevent */
+&timer2_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&gpt2_fck>;
+ assigned-clock-parents = <&sys_ck>;
+ };
+};
+
&twl_gpio {
ti,use-leds;
/*
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index c2995a280729..162d0726b008 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -14,36 +14,3 @@ aliases {
display2 = &tv0;
};
};
-
-/* Unusable as clocksource because of unreliable oscillator */
-&counter32k {
- status = "disabled";
-};
-
-/* Unusable as clockevent because if unreliable oscillator, allow to idle */
-&timer1_target {
- /delete-property/ti,no-reset-on-init;
- /delete-property/ti,no-idle;
- timer@0 {
- /delete-property/ti,timer-alwon;
- };
-};
-
-/* Preferred always-on timer for clocksource */
-&timer12_target {
- ti,no-reset-on-init;
- ti,no-idle;
- timer@0 {
- /* Always clocked by secure_32k_fck */
- };
-};
-
-/* Preferred timer for clockevent */
-&timer2_target {
- ti,no-reset-on-init;
- ti,no-idle;
- timer@0 {
- assigned-clocks = <&gpt2_fck>;
- assigned-clock-parents = <&sys_ck>;
- };
-};
--
2.34.1
^ permalink raw reply related
* [PATCH stable 5.4 1/7] pinctrl: bcm2835: Drop unused define
From: Florian Fainelli @ 2022-01-25 19:42 UTC (permalink / raw)
To: stable
Cc: Stefan Wahren, Nicolas Saenz Julienne, Linus Walleij,
Florian Fainelli, Rob Herring, Mark Rutland, Ray Jui,
Scott Branden,
maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...,
Eric Anholt, Stefan Wahren, Nicolas Saenz Julienne, Phil Elwell,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:PIN CONTROL SUBSYSTEM,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
In-Reply-To: <20220125194222.12783-1-f.fainelli@gmail.com>
From: Stefan Wahren <stefan.wahren@i2se.com>
commit be30d5de0a5a52c6ee2cc453a51301037ab94aa upstream
There is no usage for this define, so drop it.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Link: https://lore.kernel.org/r/1580148908-4863-2-git-send-email-stefan.wahren@i2se.com
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/pinctrl/bcm/pinctrl-bcm2835.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
index 0de1a3a96984..3fc26389a573 100644
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
@@ -40,9 +40,6 @@
#define BCM2835_NUM_BANKS 2
#define BCM2835_NUM_IRQS 3
-#define BCM2835_PIN_BITMAP_SZ \
- DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
-
/* GPIO register offsets */
#define GPFSEL0 0x0 /* Function Select */
#define GPSET0 0x1c /* Pin Output Set */
--
2.25.1
^ permalink raw reply related
* [PATCH stable 5.4 0/7] pinctrl-bcm2835 gpio-ranges bugfix
From: Florian Fainelli @ 2022-01-25 19:42 UTC (permalink / raw)
To: stable
Cc: Florian Fainelli, Rob Herring, Mark Rutland, Ray Jui,
Scott Branden,
maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...,
Linus Walleij, Eric Anholt, Stefan Wahren, Nicolas Saenz Julienne,
Phil Elwell,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:PIN CONTROL SUBSYSTEM,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
Hi all,
This patch series is intended to backport the fix from Phil "pinctrl:
bcm2835: Change init order for gpio hogs" into the 5.4 tree since the
blamed commit:
73345a18d464b ("pinctrl: bcm2835: Pass irqchip when adding gpiochip")
is in 5.4. To get there, I did backport a number of changes in order for
the commit "pinctrl: bcm2835: Change init order for gpio hogs" to apply
cleanly with no hunks.
Those should have no functional impact since we do not have support for
7211 or 2711 in the upstream stable 5.4.
Both the pinctrl *and* the DTS changes must be taken in lockstep
otherwise the GPIO pins are simply not usable unfortunately.
Thanks!
Florian Fainelli (2):
pinctrl: bcm2835: Match BCM7211 compatible string
pinctrl: bcm2835: Add support for wake-up interrupts
Phil Elwell (2):
pinctrl: bcm2835: Change init order for gpio hogs
ARM: dts: gpio-ranges property is now required
Stefan Wahren (3):
pinctrl: bcm2835: Drop unused define
pinctrl: bcm2835: Refactor platform data
pinctrl: bcm2835: Add support for all GPIOs on BCM2711
arch/arm/boot/dts/bcm283x.dtsi | 1 +
drivers/pinctrl/bcm/pinctrl-bcm2835.c | 209 +++++++++++++++++++++-----
2 files changed, 175 insertions(+), 35 deletions(-)
--
2.25.1
^ permalink raw reply
* [PATCH stable 5.4 2/7] pinctrl: bcm2835: Refactor platform data
From: Florian Fainelli @ 2022-01-25 19:42 UTC (permalink / raw)
To: stable
Cc: Stefan Wahren, Nicolas Saenz Julienne, Linus Walleij,
Florian Fainelli, Rob Herring, Mark Rutland, Ray Jui,
Scott Branden,
maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...,
Eric Anholt, Stefan Wahren, Nicolas Saenz Julienne, Phil Elwell,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:PIN CONTROL SUBSYSTEM,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
In-Reply-To: <20220125194222.12783-1-f.fainelli@gmail.com>
From: Stefan Wahren <stefan.wahren@i2se.com>
commit 90bfaf028d61a6d523c685b63c2bcc94eebb8057 upstream
This prepares the platform data to be easier to extend for more GPIOs.
Except of this there is no functional change.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Link: https://lore.kernel.org/r/1581166975-22949-3-git-send-email-stefan.wahren@i2se.com
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/pinctrl/bcm/pinctrl-bcm2835.c | 57 +++++++++++++++++++++------
1 file changed, 44 insertions(+), 13 deletions(-)
diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
index 3fc26389a573..7f0a9c647927 100644
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
@@ -82,6 +82,7 @@ struct bcm2835_pinctrl {
struct pinctrl_dev *pctl_dev;
struct gpio_chip gpio_chip;
+ struct pinctrl_desc pctl_desc;
struct pinctrl_gpio_range gpio_range;
raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
@@ -1051,7 +1052,7 @@ static const struct pinconf_ops bcm2711_pinconf_ops = {
.pin_config_set = bcm2711_pinconf_set,
};
-static struct pinctrl_desc bcm2835_pinctrl_desc = {
+static const struct pinctrl_desc bcm2835_pinctrl_desc = {
.name = MODULE_NAME,
.pins = bcm2835_gpio_pins,
.npins = ARRAY_SIZE(bcm2835_gpio_pins),
@@ -1061,19 +1062,47 @@ static struct pinctrl_desc bcm2835_pinctrl_desc = {
.owner = THIS_MODULE,
};
-static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
+static const struct pinctrl_desc bcm2711_pinctrl_desc = {
+ .name = MODULE_NAME,
+ .pins = bcm2835_gpio_pins,
+ .npins = ARRAY_SIZE(bcm2835_gpio_pins),
+ .pctlops = &bcm2835_pctl_ops,
+ .pmxops = &bcm2835_pmx_ops,
+ .confops = &bcm2711_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
.name = MODULE_NAME,
.npins = BCM2835_NUM_GPIOS,
};
+struct bcm_plat_data {
+ const struct gpio_chip *gpio_chip;
+ const struct pinctrl_desc *pctl_desc;
+ const struct pinctrl_gpio_range *gpio_range;
+};
+
+static const struct bcm_plat_data bcm2835_plat_data = {
+ .gpio_chip = &bcm2835_gpio_chip,
+ .pctl_desc = &bcm2835_pinctrl_desc,
+ .gpio_range = &bcm2835_pinctrl_gpio_range,
+};
+
+static const struct bcm_plat_data bcm2711_plat_data = {
+ .gpio_chip = &bcm2835_gpio_chip,
+ .pctl_desc = &bcm2711_pinctrl_desc,
+ .gpio_range = &bcm2835_pinctrl_gpio_range,
+};
+
static const struct of_device_id bcm2835_pinctrl_match[] = {
{
.compatible = "brcm,bcm2835-gpio",
- .data = &bcm2835_pinconf_ops,
+ .data = &bcm2835_plat_data,
},
{
.compatible = "brcm,bcm2711-gpio",
- .data = &bcm2711_pinconf_ops,
+ .data = &bcm2711_plat_data,
},
{}
};
@@ -1082,6 +1111,7 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
+ const struct bcm_plat_data *pdata;
struct bcm2835_pinctrl *pc;
struct gpio_irq_chip *girq;
struct resource iomem;
@@ -1108,7 +1138,13 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
if (IS_ERR(pc->base))
return PTR_ERR(pc->base);
- pc->gpio_chip = bcm2835_gpio_chip;
+ match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
+ if (!match)
+ return -EINVAL;
+
+ pdata = match->data;
+
+ pc->gpio_chip = *pdata->gpio_chip;
pc->gpio_chip.parent = dev;
pc->gpio_chip.of_node = np;
@@ -1159,19 +1195,14 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
return err;
}
- match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
- if (match) {
- bcm2835_pinctrl_desc.confops =
- (const struct pinconf_ops *)match->data;
- }
-
- pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
+ pc->pctl_desc = *pdata->pctl_desc;
+ pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
if (IS_ERR(pc->pctl_dev)) {
gpiochip_remove(&pc->gpio_chip);
return PTR_ERR(pc->pctl_dev);
}
- pc->gpio_range = bcm2835_pinctrl_gpio_range;
+ pc->gpio_range = *pdata->gpio_range;
pc->gpio_range.base = pc->gpio_chip.base;
pc->gpio_range.gc = &pc->gpio_chip;
pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
--
2.25.1
^ permalink raw reply related
* [PATCH stable 5.4 5/7] pinctrl: bcm2835: Add support for wake-up interrupts
From: Florian Fainelli @ 2022-01-25 19:42 UTC (permalink / raw)
To: stable
Cc: Florian Fainelli, Linus Walleij, Rob Herring, Mark Rutland,
Ray Jui, Scott Branden,
maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...,
Eric Anholt, Stefan Wahren, Nicolas Saenz Julienne, Phil Elwell,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:PIN CONTROL SUBSYSTEM,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
In-Reply-To: <20220125194222.12783-1-f.fainelli@gmail.com>
commit 920fecc1aa4591da27ef9dcb338fc5da86b404d7 upstream
Leverage the IRQCHIP_MASK_ON_SUSPEND flag in order to avoid having to
specifically treat the GPIO interrupts during suspend and resume, and
simply implement an irq_set_wake() callback that is responsible for
enabling the parent wake-up interrupt as a wake-up interrupt.
To avoid allocating unnecessary resources for other chips, the wake-up
interrupts are only initialized if we have a brcm,bcm7211-gpio
compatibility string.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20200531001101.24945-5-f.fainelli@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/pinctrl/bcm/pinctrl-bcm2835.c | 76 ++++++++++++++++++++++++++-
1 file changed, 75 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
index e763c680b9c2..436184ebd2ef 100644
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
@@ -19,6 +19,7 @@
#include <linux/irq.h>
#include <linux/irqdesc.h>
#include <linux/init.h>
+#include <linux/interrupt.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/of_irq.h>
@@ -76,6 +77,7 @@
struct bcm2835_pinctrl {
struct device *dev;
void __iomem *base;
+ int *wake_irq;
/* note: locking assumes each bank will have its own unsigned long */
unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
@@ -432,6 +434,11 @@ static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
chained_irq_exit(host_chip, desc);
}
+static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)
+{
+ return IRQ_HANDLED;
+}
+
static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
unsigned reg, unsigned offset, bool enable)
{
@@ -631,6 +638,34 @@ static void bcm2835_gpio_irq_ack(struct irq_data *data)
bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
}
+static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
+ struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
+ unsigned gpio = irqd_to_hwirq(data);
+ unsigned int irqgroup;
+ int ret = -EINVAL;
+
+ if (!pc->wake_irq)
+ return ret;
+
+ if (gpio <= 27)
+ irqgroup = 0;
+ else if (gpio >= 28 && gpio <= 45)
+ irqgroup = 1;
+ else if (gpio >= 46 && gpio <= 57)
+ irqgroup = 2;
+ else
+ return ret;
+
+ if (on)
+ ret = enable_irq_wake(pc->wake_irq[irqgroup]);
+ else
+ ret = disable_irq_wake(pc->wake_irq[irqgroup]);
+
+ return ret;
+}
+
static struct irq_chip bcm2835_gpio_irq_chip = {
.name = MODULE_NAME,
.irq_enable = bcm2835_gpio_irq_enable,
@@ -639,6 +674,8 @@ static struct irq_chip bcm2835_gpio_irq_chip = {
.irq_ack = bcm2835_gpio_irq_ack,
.irq_mask = bcm2835_gpio_irq_disable,
.irq_unmask = bcm2835_gpio_irq_enable,
+ .irq_set_wake = bcm2835_gpio_irq_set_wake,
+ .flags = IRQCHIP_MASK_ON_SUSPEND,
};
static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
@@ -1151,6 +1188,7 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
struct resource iomem;
int err, i;
const struct of_device_id *match;
+ int is_7211 = 0;
BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
@@ -1177,6 +1215,7 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
return -EINVAL;
pdata = match->data;
+ is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio");
pc->gpio_chip = *pdata->gpio_chip;
pc->gpio_chip.parent = dev;
@@ -1211,6 +1250,15 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
+
+ if (is_7211) {
+ pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
+ sizeof(*pc->wake_irq),
+ GFP_KERNEL);
+ if (!pc->wake_irq)
+ return -ENOMEM;
+ }
+
/*
* Use the same handler for all groups: this is necessary
* since we use one gpiochip to cover all lines - the
@@ -1218,8 +1266,34 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
* bank that was firing the IRQ and look up the per-group
* and bank data.
*/
- for (i = 0; i < BCM2835_NUM_IRQS; i++)
+ for (i = 0; i < BCM2835_NUM_IRQS; i++) {
+ int len;
+ char *name;
+
girq->parents[i] = irq_of_parse_and_map(np, i);
+ if (!is_7211)
+ continue;
+
+ /* Skip over the all banks interrupts */
+ pc->wake_irq[i] = irq_of_parse_and_map(np, i +
+ BCM2835_NUM_IRQS + 1);
+
+ len = strlen(dev_name(pc->dev)) + 16;
+ name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
+ if (!name)
+ return -ENOMEM;
+
+ snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
+
+ /* These are optional interrupts */
+ err = devm_request_irq(dev, pc->wake_irq[i],
+ bcm2835_gpio_wake_irq_handler,
+ IRQF_SHARED, name, pc);
+ if (err)
+ dev_warn(dev, "unable to request wake IRQ %d\n",
+ pc->wake_irq[i]);
+ }
+
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
--
2.25.1
^ permalink raw reply related
* [PATCH stable 5.4 3/7] pinctrl: bcm2835: Add support for all GPIOs on BCM2711
From: Florian Fainelli @ 2022-01-25 19:42 UTC (permalink / raw)
To: stable
Cc: Stefan Wahren, Nicolas Saenz Julienne, Linus Walleij,
Florian Fainelli, Rob Herring, Mark Rutland, Ray Jui,
Scott Branden,
maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...,
Eric Anholt, Stefan Wahren, Nicolas Saenz Julienne, Phil Elwell,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:PIN CONTROL SUBSYSTEM,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
In-Reply-To: <20220125194222.12783-1-f.fainelli@gmail.com>
From: Stefan Wahren <stefan.wahren@i2se.com>
commit b1d84a3d0a26c5844a22bc09a42704b9371208bb upstream
The BCM2711 supports 58 GPIOs. So extend pinctrl and GPIOs accordingly.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Link: https://lore.kernel.org/r/1581166975-22949-4-git-send-email-stefan.wahren@i2se.com
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/pinctrl/bcm/pinctrl-bcm2835.c | 54 +++++++++++++++++++++------
1 file changed, 42 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
index 7f0a9c647927..061e70ed17a7 100644
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
@@ -37,6 +37,7 @@
#define MODULE_NAME "pinctrl-bcm2835"
#define BCM2835_NUM_GPIOS 54
+#define BCM2711_NUM_GPIOS 58
#define BCM2835_NUM_BANKS 2
#define BCM2835_NUM_IRQS 3
@@ -78,7 +79,7 @@ struct bcm2835_pinctrl {
/* note: locking assumes each bank will have its own unsigned long */
unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
- unsigned int irq_type[BCM2835_NUM_GPIOS];
+ unsigned int irq_type[BCM2711_NUM_GPIOS];
struct pinctrl_dev *pctl_dev;
struct gpio_chip gpio_chip;
@@ -145,6 +146,10 @@ static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
BCM2835_GPIO_PIN(51),
BCM2835_GPIO_PIN(52),
BCM2835_GPIO_PIN(53),
+ BCM2835_GPIO_PIN(54),
+ BCM2835_GPIO_PIN(55),
+ BCM2835_GPIO_PIN(56),
+ BCM2835_GPIO_PIN(57),
};
/* one pin per group */
@@ -203,6 +208,10 @@ static const char * const bcm2835_gpio_groups[] = {
"gpio51",
"gpio52",
"gpio53",
+ "gpio54",
+ "gpio55",
+ "gpio56",
+ "gpio57",
};
enum bcm2835_fsel {
@@ -353,6 +362,22 @@ static const struct gpio_chip bcm2835_gpio_chip = {
.can_sleep = false,
};
+static const struct gpio_chip bcm2711_gpio_chip = {
+ .label = "pinctrl-bcm2711",
+ .owner = THIS_MODULE,
+ .request = gpiochip_generic_request,
+ .free = gpiochip_generic_free,
+ .direction_input = bcm2835_gpio_direction_input,
+ .direction_output = bcm2835_gpio_direction_output,
+ .get_direction = bcm2835_gpio_get_direction,
+ .get = bcm2835_gpio_get,
+ .set = bcm2835_gpio_set,
+ .set_config = gpiochip_generic_config,
+ .base = -1,
+ .ngpio = BCM2711_NUM_GPIOS,
+ .can_sleep = false,
+};
+
static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
unsigned int bank, u32 mask)
{
@@ -399,7 +424,7 @@ static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
break;
- case 2: /* IRQ2 covers GPIOs 46-53 */
+ case 2: /* IRQ2 covers GPIOs 46-57 */
bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
break;
}
@@ -618,7 +643,7 @@ static struct irq_chip bcm2835_gpio_irq_chip = {
static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
{
- return ARRAY_SIZE(bcm2835_gpio_groups);
+ return BCM2835_NUM_GPIOS;
}
static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
@@ -776,7 +801,7 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
if (err)
goto out;
- if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
+ if (pin >= pc->pctl_desc.npins) {
dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
np, pin);
err = -EINVAL;
@@ -852,7 +877,7 @@ static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
{
/* every pin can do every function */
*groups = bcm2835_gpio_groups;
- *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
+ *num_groups = BCM2835_NUM_GPIOS;
return 0;
}
@@ -1055,7 +1080,7 @@ static const struct pinconf_ops bcm2711_pinconf_ops = {
static const struct pinctrl_desc bcm2835_pinctrl_desc = {
.name = MODULE_NAME,
.pins = bcm2835_gpio_pins,
- .npins = ARRAY_SIZE(bcm2835_gpio_pins),
+ .npins = BCM2835_NUM_GPIOS,
.pctlops = &bcm2835_pctl_ops,
.pmxops = &bcm2835_pmx_ops,
.confops = &bcm2835_pinconf_ops,
@@ -1063,9 +1088,9 @@ static const struct pinctrl_desc bcm2835_pinctrl_desc = {
};
static const struct pinctrl_desc bcm2711_pinctrl_desc = {
- .name = MODULE_NAME,
+ .name = "pinctrl-bcm2711",
.pins = bcm2835_gpio_pins,
- .npins = ARRAY_SIZE(bcm2835_gpio_pins),
+ .npins = BCM2711_NUM_GPIOS,
.pctlops = &bcm2835_pctl_ops,
.pmxops = &bcm2835_pmx_ops,
.confops = &bcm2711_pinconf_ops,
@@ -1077,6 +1102,11 @@ static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
.npins = BCM2835_NUM_GPIOS,
};
+static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
+ .name = "pinctrl-bcm2711",
+ .npins = BCM2711_NUM_GPIOS,
+};
+
struct bcm_plat_data {
const struct gpio_chip *gpio_chip;
const struct pinctrl_desc *pctl_desc;
@@ -1090,9 +1120,9 @@ static const struct bcm_plat_data bcm2835_plat_data = {
};
static const struct bcm_plat_data bcm2711_plat_data = {
- .gpio_chip = &bcm2835_gpio_chip,
+ .gpio_chip = &bcm2711_gpio_chip,
.pctl_desc = &bcm2711_pinctrl_desc,
- .gpio_range = &bcm2835_pinctrl_gpio_range,
+ .gpio_range = &bcm2711_pinctrl_gpio_range,
};
static const struct of_device_id bcm2835_pinctrl_match[] = {
@@ -1118,8 +1148,8 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
int err, i;
const struct of_device_id *match;
- BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
- BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
+ BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
+ BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
if (!pc)
--
2.25.1
^ permalink raw reply related
* [PATCH stable 5.4 4/7] pinctrl: bcm2835: Match BCM7211 compatible string
From: Florian Fainelli @ 2022-01-25 19:42 UTC (permalink / raw)
To: stable
Cc: Florian Fainelli, Linus Walleij, Rob Herring, Mark Rutland,
Ray Jui, Scott Branden,
maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...,
Eric Anholt, Stefan Wahren, Nicolas Saenz Julienne, Phil Elwell,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:PIN CONTROL SUBSYSTEM,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
In-Reply-To: <20220125194222.12783-1-f.fainelli@gmail.com>
commit 562c856f96d22ef1204b0a314bc52e85617199b4 upstream
The BCM7211 SoC uses the same pinconf_ops as the ones defined for the
BCM2711 SoC, match the compatible string and use the correct set of
options.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20200531001101.24945-4-f.fainelli@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/pinctrl/bcm/pinctrl-bcm2835.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
index 061e70ed17a7..e763c680b9c2 100644
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
@@ -1134,6 +1134,10 @@ static const struct of_device_id bcm2835_pinctrl_match[] = {
.compatible = "brcm,bcm2711-gpio",
.data = &bcm2711_plat_data,
},
+ {
+ .compatible = "brcm,bcm7211-gpio",
+ .data = &bcm2711_plat_data,
+ },
{}
};
--
2.25.1
^ permalink raw reply related
* [PATCH stable 5.4 6/7] pinctrl: bcm2835: Change init order for gpio hogs
From: Florian Fainelli @ 2022-01-25 19:42 UTC (permalink / raw)
To: stable
Cc: Phil Elwell, Florian Fainelli, Linus Walleij, Rob Herring,
Mark Rutland, Ray Jui, Scott Branden,
maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...,
Eric Anholt, Stefan Wahren, Nicolas Saenz Julienne,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:PIN CONTROL SUBSYSTEM,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
In-Reply-To: <20220125194222.12783-1-f.fainelli@gmail.com>
From: Phil Elwell <phil@raspberrypi.com>
commit 266423e60ea1b953fcc0cd97f3dad85857e434d1 upstream
...and gpio-ranges
pinctrl-bcm2835 is a combined pinctrl/gpio driver. Currently the gpio
side is registered first, but this breaks gpio hogs (which are
configured during gpiochip_add_data). Part of the hog initialisation
is a call to pinctrl_gpio_request, and since the pinctrl driver hasn't
yet been registered this results in an -EPROBE_DEFER from which it can
never recover.
Change the initialisation sequence to register the pinctrl driver
first.
This also solves a similar problem with the gpio-ranges property, which
is required in order for released pins to be returned to inputs.
Fixes: 73345a18d464b ("pinctrl: bcm2835: Pass irqchip when adding gpiochip")
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20211206092237.4105895-2-phil@raspberrypi.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/pinctrl/bcm/pinctrl-bcm2835.c | 29 +++++++++++++++------------
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
index 436184ebd2ef..fa742535f679 100644
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
@@ -1241,6 +1241,18 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
raw_spin_lock_init(&pc->irq_lock[i]);
}
+ pc->pctl_desc = *pdata->pctl_desc;
+ pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
+ if (IS_ERR(pc->pctl_dev)) {
+ gpiochip_remove(&pc->gpio_chip);
+ return PTR_ERR(pc->pctl_dev);
+ }
+
+ pc->gpio_range = *pdata->gpio_range;
+ pc->gpio_range.base = pc->gpio_chip.base;
+ pc->gpio_range.gc = &pc->gpio_chip;
+ pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
+
girq = &pc->gpio_chip.irq;
girq->chip = &bcm2835_gpio_irq_chip;
girq->parent_handler = bcm2835_gpio_irq_handler;
@@ -1248,8 +1260,10 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
sizeof(*girq->parents),
GFP_KERNEL);
- if (!girq->parents)
+ if (!girq->parents) {
+ pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);
return -ENOMEM;
+ }
if (is_7211) {
pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
@@ -1300,21 +1314,10 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
err = gpiochip_add_data(&pc->gpio_chip, pc);
if (err) {
dev_err(dev, "could not add GPIO chip\n");
+ pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);
return err;
}
- pc->pctl_desc = *pdata->pctl_desc;
- pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
- if (IS_ERR(pc->pctl_dev)) {
- gpiochip_remove(&pc->gpio_chip);
- return PTR_ERR(pc->pctl_dev);
- }
-
- pc->gpio_range = *pdata->gpio_range;
- pc->gpio_range.base = pc->gpio_chip.base;
- pc->gpio_range.gc = &pc->gpio_chip;
- pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
-
return 0;
}
--
2.25.1
^ permalink raw reply related
* [PATCH stable 5.4 7/7] ARM: dts: gpio-ranges property is now required
From: Florian Fainelli @ 2022-01-25 19:42 UTC (permalink / raw)
To: stable
Cc: Phil Elwell, Stefan Wahren, Florian Fainelli, Jan Kiszka,
Linus Walleij, Olof Johansson, Rob Herring, Mark Rutland, Ray Jui,
Scott Branden,
maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...,
Eric Anholt, Stefan Wahren, Nicolas Saenz Julienne,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:PIN CONTROL SUBSYSTEM,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
In-Reply-To: <20220125194222.12783-1-f.fainelli@gmail.com>
From: Phil Elwell <phil@raspberrypi.com>
commit c8013355ead68dce152cf426686f8a5f80d88b40 upstream
Since [1], added in 5.7, the absence of a gpio-ranges property has
prevented GPIOs from being restored to inputs when released.
Add those properties for BCM283x and BCM2711 devices.
[1] commit 2ab73c6d8323 ("gpio: Support GPIO controllers without
pin-ranges")
Link: https://lore.kernel.org/r/20220104170247.956760-1-linus.walleij@linaro.org
Fixes: 2ab73c6d8323 ("gpio: Support GPIO controllers without pin-ranges")
Fixes: 266423e60ea1 ("pinctrl: bcm2835: Change init order for gpio hogs")
Reported-by: Stefan Wahren <stefan.wahren@i2se.com>
Reported-by: Florian Fainelli <f.fainelli@gmail.com>
Reported-by: Jan Kiszka <jan.kiszka@web.de>
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20211206092237.4105895-3-phil@raspberrypi.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
[florian: Remove bcm2711.dtsi hunk which does not exist in 5.4]
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm283x.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index 50c64146d492..af81f386793c 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -183,6 +183,7 @@
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <&gpio 0 0 54>;
/* Defines pin muxing groups according to
* BCM2835-ARM-Peripherals.pdf page 102.
--
2.25.1
^ permalink raw reply related
* [PATCH] Adding architectural support for HPE's GXP BMC. This is the first of a series of patches to support HPE's BMC with Linux Kernel.
From: nick.hawkins @ 2022-01-25 19:46 UTC (permalink / raw)
To: verdun
Cc: nick.hawkins, Rob Herring, Russell King, Krzysztof Kozlowski,
Shawn Guo, Stanislav Jakubek, Sam Ravnborg, Linus Walleij,
Hao Fang, Arnd Bergmann, Russell King (Oracle),
Geert Uytterhoeven, Mark Rutland, Ard Biesheuvel,
Anshuman Khandual, Lukas Bulwahn, Masahiro Yamada, devicetree,
linux-kernel, linux-arm-kernel
From: Nick Hawkins <nick.hawkins@hpe.com>
Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
---
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 8 +
arch/arm/Kconfig | 2 +
arch/arm/boot/dts/gxp.dts | 700 ++++++++++++++++++
arch/arm/configs/gxp_defconfig | 243 ++++++
arch/arm/mach-hpe/Kconfig | 20 +
arch/arm/mach-hpe/Makefile | 1 +
arch/arm/mach-hpe/gxp.c | 63 ++
8 files changed, 1039 insertions(+)
create mode 100644 arch/arm/boot/dts/gxp.dts
create mode 100644 arch/arm/configs/gxp_defconfig
create mode 100644 arch/arm/mach-hpe/Kconfig
create mode 100644 arch/arm/mach-hpe/Makefile
create mode 100644 arch/arm/mach-hpe/gxp.c
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 294093d45a23..e8b0ec874aed 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -515,6 +515,8 @@ patternProperties:
description: Jiangsu HopeRun Software Co., Ltd.
"^hp,.*":
description: Hewlett Packard
+ "^hpe,.*":
+ description: Hewlett Packard Enterprise
"^hsg,.*":
description: HannStar Display Co.
"^holtek,.*":
diff --git a/MAINTAINERS b/MAINTAINERS
index ea3e6c914384..007d99734dd1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8382,6 +8382,14 @@ L: linux-efi@vger.kernel.org
S: Maintained
F: block/partitions/efi.*
+GXP ARCHITECTURE
+M: Jean-Marie Verdun <verdun@hpe.com>
+M: Nick Hawkins <nick.hawkins@hpe.com>
+S: Maintained
+F: arch/arm/boot/dts/gxp.dts
+F: arch/arm/configs/gxp_defconfig
+F: arch/arm/mach-hpe/gxp.c
+
H8/300 ARCHITECTURE
M: Yoshinori Sato <ysato@users.sourceforge.jp>
L: uclinux-h8-devel@lists.sourceforge.jp (moderated for non-subscribers)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fabe39169b12..d428d0d35889 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -708,6 +708,8 @@ source "arch/arm/mach-vt8500/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
+source "arch/arm/mach-hpe/Kconfig"
+
# ARMv7-M architecture
config ARCH_LPC18XX
bool "NXP LPC18xx/LPC43xx"
diff --git a/arch/arm/boot/dts/gxp.dts b/arch/arm/boot/dts/gxp.dts
new file mode 100644
index 000000000000..7bd814ecaaee
--- /dev/null
+++ b/arch/arm/boot/dts/gxp.dts
@@ -0,0 +1,700 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for HPE GXP
+ */
+
+/dts-v1/;
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "HPE,GXP";
+ model = "GXP";
+
+ chosen {
+ bootargs = "earlyprintk console=ttyS0,115200 user_debug=31";
+ };
+
+ aliases {
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x20000000>;
+ };
+
+ ahb@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ vic0: vic@ceff0000 {
+ compatible = "arm,pl192-vic";
+ interrupt-controller;
+ reg = <0xceff0000 0x1000>;
+ #interrupt-cells = <1>;
+ };
+
+ vic1: vic@80f00000 {
+ compatible = "arm,pl192-vic";
+ interrupt-controller;
+ reg = <0x80f00000 0x1000>;
+ #interrupt-cells = <1>;
+ };
+
+ timer0: timer@c0000080 {
+ compatible = "hpe,gxp-timer";
+ reg = <0xc0000080 0x1>, <0xc0000094 0x01>, <0xc0000088 0x08>;
+ interrupts = <0>;
+ interrupt-parent = <&vic0>;
+ clock-frequency = <400000000>;
+ };
+
+ watchdog: watchdog@c0000090 {
+ compatible = "hpe,gxp-wdt";
+ reg = <0xc0000090 0x02>, <0xc0000096 0x01>;
+ };
+
+ uartc: serial@c00000f0 {
+ compatible = "ns16550a";
+ reg = <0xc00000f0 0x8>;
+ interrupts = <19>;
+ interrupt-parent = <&vic0>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+
+ uarta: serial@c00000e0 {
+ compatible = "ns16550a";
+ reg = <0xc00000e0 0x8>;
+ interrupts = <17>;
+ interrupt-parent = <&vic0>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+
+ uartb: serial@c00000e8 {
+ compatible = "ns16550a";
+ reg = <0xc00000e8 0x8>;
+ interrupts = <18>;
+ interrupt-parent = <&vic0>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+
+ vuart_a_cfg: vuarta_cfg@80fc0230 {
+ compatible = "hpe,gxp-vuarta_cfg", "simple-mfd", "syscon";
+ reg = <0x80fc0230 0x100>;
+ reg-io-width = <1>;
+ };
+
+ vuart_a: vuart_a@80fd0200 {
+ compatible = "hpe,gxp-vuart";
+ reg = <0x80fd0200 0x100>;
+ interrupts = <2>;
+ interrupt-parent = <&vic1>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ status = "okay";
+ serial-line = <3>;
+ vuart_cfg = <&vuart_a_cfg>;
+ };
+
+ usb0: ehci@cefe0000 {
+ compatible = "generic-ehci";
+ reg = <0xcefe0000 0x100>;
+ interrupts = <7>;
+ interrupt-parent = <&vic0>;
+ };
+
+ usb1: ohci@cefe0100 {
+ compatible = "generic-ohci";
+ reg = <0xcefe0100 0x110>;
+ interrupts = <6>;
+ interrupt-parent = <&vic0>;
+ };
+
+ spifi0: spifi@c0000200 {
+ compatible = "hpe,gxp-spifi";
+ reg = <0xc0000200 0x80>, <0xc000c000 0x100>, <0xf8000000 0x8000000>;
+ interrupts = <20>;
+ interrupt-parent = <&vic0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bmc@0 {
+ label = "bmc";
+ reg = <0x0 0x2000000>;
+ };
+ u-boot@0 {
+ label = "u-boot";
+ reg = <0x0 0x60000>;
+ };
+ u-boot-env@60000 {
+ label = "u-boot-env";
+ reg = <0x60000 0x20000>;
+ };
+ kernel@80000 {
+ label = "kernel";
+ reg = <0x80000 0x4c0000>;
+ };
+ rofs@540000 {
+ label = "rofs";
+ reg = <0x540000 0x1740000>;
+ };
+ rwfs@1c80000 {
+ label = "rwfs";
+ reg = <0x1c80000 0x250000>;
+ };
+ section@1edf000{
+ label = "section";
+ reg = <0x1ed0000 0x130000>;
+ };
+ };
+ };
+
+ flash@1 {
+ compatible = "jedec,spi-nor";
+ reg = <1>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ host-prime@0 {
+ label = "host-prime";
+ reg = <0x0 0x02000000>;
+ };
+ host-second@0 {
+ label = "host-second";
+ reg = <0x02000000 0x02000000>;
+ };
+ };
+ };
+ };
+
+ sram@d0000000 {
+ compatible = "mtd-ram";
+ reg = <0xd0000000 0x80000>;
+ bank-width = <1>;
+ erase-size =<1>;
+ partition@0 {
+ label = "host-reserved";
+ reg = <0x0 0x10000>;
+ };
+ partition@10000 {
+ label = "nvram";
+ reg = <0x10000 0x70000>;
+ };
+ };
+
+ srom@80fc0000 {
+ compatible = "hpe,gxp-srom", "simple-mfd", "syscon";
+ reg = <0x80fc0000 0x100>;
+ };
+
+ vrom@58000000 {
+ compatible = "mtd-ram";
+ bank-width = <4>;
+ reg = <0x58000000 0x4000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "vrom-prime";
+ reg = <0x0 0x2000000>;
+ };
+ partition@2000000 {
+ label = "vrom-second";
+ reg = <0x2000000 0x2000000>;
+ };
+ };
+
+ i2cg: i2cg@c00000f8 {
+ compatible = "syscon";
+ reg = <0xc00000f8 0x08>;
+ };
+
+ i2c0: i2c@c0002000 {
+ compatible = "hpe,gxp-i2c";
+ reg = <0xc0002000 0x70>;
+ interrupts = <9>;
+ interrupt-parent = <&vic0>;
+ i2cg-handle = <&i2cg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@c0002100 {
+ compatible = "hpe,gxp-i2c";
+ reg = <0xc0002100 0x70>;
+ interrupts = <9>;
+ interrupt-parent = <&vic0>;
+ i2cg-handle = <&i2cg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@c0002200 {
+ compatible = "hpe,gxp-i2c";
+ reg = <0xc0002200 0x70>;
+ interrupts = <9>;
+ interrupt-parent = <&vic0>;
+ i2cg-handle = <&i2cg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ 24c02@50 {
+ compatible = "atmel,24c02";
+ pagesize = <8>;
+ reg = <0x50>;
+ };
+ };
+
+ i2c3: i2c@c0002300 {
+ compatible = "hpe,gxp-i2c";
+ reg = <0xc0002300 0x70>;
+ interrupts = <9>;
+ interrupt-parent = <&vic0>;
+ i2cg-handle = <&i2cg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c@c0002400 {
+ compatible = "hpe,gxp-i2c";
+ reg = <0xc0002400 0x70>;
+ interrupts = <9>;
+ interrupt-parent = <&vic0>;
+ i2cg-handle = <&i2cg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c5: i2c@c0002500 {
+ compatible = "hpe,gxp-i2c";
+ reg = <0xc0002500 0x70>;
+ interrupts = <9>;
+ interrupt-parent = <&vic0>;
+ i2cg-handle = <&i2cg>;
+ };
+
+ i2c6: i2c@c0002600 {
+ compatible = "hpe,gxp-i2c";
+ reg = <0xc0002600 0x70>;
+ interrupts = <9>;
+ interrupt-parent = <&vic0>;
+ i2cg-handle = <&i2cg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c7: i2c@c0002700 {
+ compatible = "hpe,gxp-i2c";
+ reg = <0xc0002700 0x70>;
+ interrupts = <9>;
+ interrupt-parent = <&vic0>;
+ i2cg-handle = <&i2cg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ psu1: psu@58 {
+ compatible = "hpe,gxp-psu";
+ reg = <0x58>;
+ };
+
+ psu2: psu@59 {
+ compatible = "hpe,gxp-psu";
+ reg = <0x59>;
+ };
+ };
+
+ i2c8: i2c@c0002800 {
+ compatible = "hpe,gxp-i2c";
+ reg = <0xc0002800 0x70>;
+ interrupts = <9>;
+ interrupt-parent = <&vic0>;
+ i2cg-handle = <&i2cg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c9: i2c@c0002900 {
+ compatible = "hpe,gxp-i2c";
+ reg = <0xc0002900 0x70>;
+ interrupts = <9>;
+ interrupt-parent = <&vic0>;
+ i2cg-handle = <&i2cg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2cmux@4 {
+ compatible = "i2c-mux-reg";
+ i2c-parent = <&i2c4>;
+ reg = <0xd1000074 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c4@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ i2cmux@6 {
+ compatible = "i2c-mux-reg";
+ i2c-parent = <&i2c6>;
+ reg = <0xd1000076 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c6@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c6@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c6@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c6@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c6@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ mdio0: mdio@c0004080 {
+ compatible = "hpe,gxp-umac-mdio";
+ reg = <0xc0004080 0x10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ext_phy0: ethernt-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ phy-mode = "sgmii";
+ reg = <0>;
+ };
+ };
+
+ mdio1: mdio@c0005080 {
+ compatible = "hpe,gxp-umac-mdio";
+ reg = <0xc0005080 0x10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_phy0: ethernt-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ phy-mode = "gmii";
+ reg = <0>;
+ };
+ int_phy1: ethernt-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ phy-mode = "gmii";
+ reg = <1>;
+ };
+ };
+
+ umac0: umac@c0004000 {
+ compatible = "hpe, gxp-umac";
+ reg = <0xc0004000 0x80>;
+ interrupts = <10>;
+ interrupt-parent = <&vic0>;
+ mac-address = [94 18 82 16 04 d8];
+ phy-handle = <&ext_phy0>;
+ int-phy-handle = <&int_phy0>;
+ };
+
+ umac1: umac@c0005000 {
+ compatible = "hpe, gxp-umac";
+ use-ncsi;
+ reg = <0xc0005000 0x80>;
+ interrupts = <11>;
+ interrupt-parent = <&vic0>;
+ mac-address = [94 18 82 16 04 d9];
+ phy-handle = <&int_phy1>;
+ };
+
+ kcs_conf: kcs_conf@80fc0430 {
+ compatible = "hpe,gxp-kcs-bmc-cfg", "simple-mfd", "syscon";
+ reg = <0x80fc0430 0x100>;
+ };
+
+ kcs_reg: kcs_reg@080fd0400 {
+ compatible = "hpe,gxp-kcs-bmc";
+ reg = <0x80fd0400 0x8>;
+ interrupts = <6>;
+ interrupt-parent = <&vic1>;
+ kcs_chan = <1>;
+ status = "okay";
+ kcs-bmc-cfg = <&kcs_conf>;
+ };
+
+ thumbnail: thumbnail@c0000500 {
+ compatible = "hpe,gxp-thumbnail";
+ reg = <0xc0000500 0x20>;
+ bits-per-pixel = <32>;
+ width = <800>;
+ height = <600>;
+ };
+
+ xreg: xreg@d1000000 {
+ compatible = "hpe,gxp-xreg", "simple-mfd", "syscon";
+ reg = <0xd1000000 0xFF>;
+ interrupts = <26>;
+ interrupt-parent = <&vic0>;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "", "", "", "", "", "", "POWER", "HEARTBEAT", "FAN1_INST", "FAN2_INST",
+ "FAN3_INST", "FAN4_INST", "FAN5_INST", "FAN6_INST", "FAN7_INST",
+ "FAN8_INST", "FAN9_INST", "FAN10_INST", "FAN11_INST", "FAN12_INST",
+ "FAN13_INST", "FAN14_INST", "FAN15_INST", "FAN16_INST", "FAN1_FAIL",
+ "FAN2_FAIL", "FAN3_FAIL", "FAN4_FAIL", "FAN5_FAIL", "FAN6_FAIL",
+ "FAN7_FAIL", "FAN8_FAIL", "FAN9_FAIL", "FAN10_FAIL", "FAN11_FAIL",
+ "FAN12_FAIL", "FAN13_FAIL", "FAN14_FAIL", "FAN15_FAIL", "FAN16_FAIL",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "IDENTIFY", "HEALTH_RED", "HEALTH_AMBER",
+ "POWER_BUTTON", "", "SIO_POWER_GOOD", "NMI_BUTTON", "RESET_BUTTON",
+ "SIO_S5", "SIO_ONCONTROL", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "";
+ };
+
+ fanctrl: fanctrl@c1000c00 {
+ compatible = "hpe,gxp-fan-ctrl";
+ reg = <0xc1000c00 0x200>;
+ xreg_handle = <&xreg>;
+ fn2_handle = <&fn2>;
+ };
+
+ fn2: fn2@80200000 {
+ compatible = "hpe,gxp-fn2", "simple-mfd", "syscon";
+ reg = <0x80200000 0x100000>;
+ xreg_handle = <&xreg>;
+ interrupts = <0>;
+ interrupt-parent = <&vic1>;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "POWER_OUT", "PS_PWROK", "PCIERST", "POST_COMPLETE", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "";
+ chif {
+ compatible = "hpe,gxp-chif";
+ interrupts = <12>;
+ };
+ };
+
+ csm: csm@80000000 {
+ compatible = "hpe,gxp-csm", "simple-mfd", "syscon";
+ reg = <0x80000000 0x400>;
+ };
+
+ gpio: gpio@0 {
+ compatible = "hpe,gxp-gpio";
+ #gpio-cells = <2>;
+ csm_handle = <&csm>;
+ vuhc0_handle = <&vuhc0>;
+ gpio-line-names =
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "RESET_OUT", "NMI_OUT", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "";
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+
+ power {
+ gpios = <&xreg 6 0>;
+ default-state = "off";
+ };
+
+ heartbeat {
+ gpios = <&xreg 7 0>;
+ default-state = "off";
+ };
+
+ identify {
+ gpios = <&xreg 56 0>;
+ default-state = "off";
+ };
+
+ health_red {
+ gpios = <&xreg 57 0>;
+ default-state = "off";
+ };
+
+ health_amber {
+ gpios = <&xreg 58 0>;
+ default-state = "off";
+ };
+ };
+
+ xreg_kyes: xreg_keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+
+ IdButton {
+ label = "ID Button";
+ linux,code = <200>;
+ gpios = <&xreg 60 1>;
+ };
+ };
+
+ vuhc: vuhc {
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+
+ PortOwner@0 {
+ label = "Port Owner";
+ linux,code = <200>;
+ gpios = <&gpio 250 1>;
+ };
+
+ PortOwner@1 {
+ label = "Port Owner";
+ linux,code = <201>;
+ gpios = <&gpio 251 1>;
+ };
+ };
+
+ vuhc0: vuhc@80400080 {
+ compatible = "syscon";
+ reg = <0x80400000 0x80>;
+ };
+
+ udcg: udcg@80400800 {
+ compatible = "syscon";
+ reg = <0x80400800 0x200>;
+ };
+
+ udc0: udc@80401000 {
+ compatible = "hpe, gxp-udc";
+ reg = <0x80401000 0x1000>;
+ interrupts = <13>;
+ interrupt-parent = <&vic1>;
+ vdevnum = <0>;
+ fepnum = <7>;
+ udcg-handle = <&udcg>;
+ };
+
+ udc1: udc@80402000 {
+ compatible = "hpe, gxp-udc";
+ reg = <0x80402000 0x1000>;
+ interrupts = <13>;
+ interrupt-parent = <&vic1>;
+ vdevnum = <1>;
+ fepnum = <7>;
+ udcg-handle = <&udcg>;
+ };
+
+ coretemp: coretemp@c0000130 {
+ compatible = "hpe,gxp-coretemp";
+ reg = <0xc0000130 0x8>;
+ };
+
+ syspower: syspower {
+ compatible = "hpe,gxp-power";
+ psu_phandle = <&psu1>, <&psu2>;
+ };
+
+ peci: peci@80000400 {
+ compatible = "hpe,gxp-peci";
+ reg = <0x80000400 0x200>;
+ interrupts = <22>;
+ interrupt-parent = <&vic1>;
+ };
+ };
+
+ clocks {
+ osc: osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "osc";
+ clock-frequency = <33333333>;
+ };
+
+ iopclk: iopclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&osc>;
+ clock-out-put-names = "iopclk";
+ clock-frequency = <400000000>;
+ };
+
+ memclk: memclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&osc>;
+ clock-out-put-names = "memclk";
+ clock-frequency = <800000000>;
+ };
+ };
+};
diff --git a/arch/arm/configs/gxp_defconfig b/arch/arm/configs/gxp_defconfig
new file mode 100644
index 000000000000..f37c6630e06d
--- /dev/null
+++ b/arch/arm/configs/gxp_defconfig
@@ -0,0 +1,243 @@
+CONFIG_KERNEL_XZ=y
+CONFIG_DEFAULT_HOSTNAME="gxp"
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_NAMESPACES=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_ARCH_MULTI_V6=y
+CONFIG_ARCH_HPE=y
+CONFIG_ARCH_HPE_GXP=y
+CONFIG_SECCOMP=y
+# CONFIG_ATAGS is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+# CONFIG_SUSPEND is not set
+CONFIG_JUMP_LABEL=y
+# CONFIG_STRICT_KERNEL_RWX is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_KSM=y
+CONFIG_CLEANCACHE=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=y
+CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_INET=y
+CONFIG_VLAN_8021Q=y
+CONFIG_NETLINK_DIAG=y
+CONFIG_NET_NCSI=y
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_PLATRAM=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_SPI_GXP_SPIFI=y
+CONFIG_BLK_DEV_NULL_BLK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NBD=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_EEPROM_AT24=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_NET_VENDOR_AMAZON is not set
+# CONFIG_NET_VENDOR_AQUANTIA is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_AURORA is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CADENCE is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_GOOGLE is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_NET_VENDOR_XILINX is not set
+CONFIG_UMAC=y
+# CONFIG_USB_NET_DRIVERS is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_LEDS is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIO_LIBPS2=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_GXP_VUART=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_TTY_PRINTK=y
+CONFIG_IPMI_HANDLER=y
+CONFIG_IPMI_DEVICE_INTERFACE=y
+CONFIG_IPMI_SI=y
+CONFIG_IPMI_SSIF=y
+CONFIG_HPE_KCS_IPMI_BMC=y
+CONFIG_HW_RANDOM_TIMERIOMEM=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_GXP=y
+CONFIG_I2C_SLAVE=y
+CONFIG_I2C_SLAVE_EEPROM=y
+CONFIG_SPI=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_GXP=y
+CONFIG_SENSORS_EMC1403=y
+CONFIG_SENSORS_GXP_FAN_CTRL=y
+CONFIG_SENSORS_GXP_CORETEMP=y
+CONFIG_SENSORS_GXP_PSU=y
+CONFIG_SENSORS_GXP_POWER=y
+CONFIG_WATCHDOG=y
+CONFIG_GXP_WATCHDOG=y
+CONFIG_MFD_SYSCON=y
+CONFIG_FB=y
+CONFIG_FB_THUMBNAIL=y
+CONFIG_FB_SIMPLE=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GXP_UDC=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_LB_SS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_USB_CONFIGFS_F_PRINTER=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_MTD=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+# CONFIG_VIRTIO_MENU is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_HPE_GXP_XREG=y
+CONFIG_HPE_GXP_FN2=y
+CONFIG_HPE_GXP_CSM=y
+CONFIG_HPE_GXP_SROM=y
+CONFIG_FANOTIFY=y
+CONFIG_OVERLAY_FS=y
+CONFIG_OVERLAY_FS_REDIRECT_DIR=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_JFFS2_FS=y
+# CONFIG_JFFS2_FS_WRITEBUFFER is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+# CONFIG_JFFS2_FS_POSIX_ACL is not set
+# CONFIG_JFFS2_FS_SECURITY is not set
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CRYPTO_USER_API_HASH=y
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC16=y
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+CONFIG_DMA_API_DEBUG=y
+CONFIG_PRINTK_TIME=y
+CONFIG_BOOT_PRINTK_DELAY=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_FUNCTION_PROFILER=y
+CONFIG_STACK_TRACER=y
+CONFIG_SCHED_TRACER=y
+CONFIG_STRICT_DEVMEM=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0xC00000F0
+CONFIG_DEBUG_UART_VIRT=0xF00000F0
+CONFIG_DEBUG_UART_8250_SHIFT=0
+CONFIG_EARLY_PRINTK=y
+CONFIG_TEST_KSTRTOX=y
diff --git a/arch/arm/mach-hpe/Kconfig b/arch/arm/mach-hpe/Kconfig
new file mode 100644
index 000000000000..9b27f97c6536
--- /dev/null
+++ b/arch/arm/mach-hpe/Kconfig
@@ -0,0 +1,20 @@
+menuconfig ARCH_HPE
+ bool "HPE SoC support"
+ help
+ This enables support for HPE ARM based SoC chips
+if ARCH_HPE
+
+config ARCH_HPE_GXP
+ bool "HPE GXP SoC"
+ select ARM_VIC
+ select PINCTRL
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_CHIP
+ select MULTI_IRQ_HANDLER
+ select SPARSE_IRQ
+ select CLKSRC_MMIO
+ depends on ARCH_MULTI_V7
+ help
+ Support for GXP SoCs
+
+endif
diff --git a/arch/arm/mach-hpe/Makefile b/arch/arm/mach-hpe/Makefile
new file mode 100644
index 000000000000..8b0a91234df4
--- /dev/null
+++ b/arch/arm/mach-hpe/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_HPE_GXP) += gxp.o
diff --git a/arch/arm/mach-hpe/gxp.c b/arch/arm/mach-hpe/gxp.c
new file mode 100644
index 000000000000..b58f25fbae5a
--- /dev/null
+++ b/arch/arm/mach-hpe/gxp.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+#include <linux/init.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/clk-provider.h>
+#include <linux/clocksource.h>
+
+#define IOP_REGS_PHYS_BASE 0xc0000000
+#define IOP_REGS_VIRT_BASE 0xf0000000
+#define IOP_REGS_SIZE (240*SZ_1M)
+
+#define IOP_EHCI_USBCMD 0x0efe0010
+
+static struct map_desc gxp_io_desc[] __initdata = {
+ {
+ .virtual = (unsigned long)IOP_REGS_VIRT_BASE,
+ .pfn = __phys_to_pfn(IOP_REGS_PHYS_BASE),
+ .length = IOP_REGS_SIZE,
+ .type = MT_DEVICE,
+ },
+};
+
+void __init gxp_map_io(void)
+{
+ iotable_init(gxp_io_desc, ARRAY_SIZE(gxp_io_desc));
+}
+
+static void __init gxp_dt_init(void)
+{
+ //reset EHCI host controller for clear start
+ __raw_writel(0x00080002,
+ (void __iomem *)(IOP_REGS_VIRT_BASE + IOP_EHCI_USBCMD));
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static void gxp_restart(enum reboot_mode mode, const char *cmd)
+{
+ pr_info("gpx restart");
+ __raw_writel(1, (void __iomem *) IOP_REGS_VIRT_BASE);
+}
+
+static const char * const gxp_board_dt_compat[] = {
+ "HPE,GXP",
+ NULL,
+};
+
+DT_MACHINE_START(GXP_DT, "HPE GXP")
+ .init_machine = gxp_dt_init,
+ .map_io = gxp_map_io,
+ .restart = gxp_restart,
+ .dt_compat = gxp_board_dt_compat,
+MACHINE_END
--
2.17.1
^ permalink raw reply related
* [PATCH 09/10] dt-bindings: rtc: pcf2127: add PCF2131
From: Hugo Villeneuve @ 2022-01-25 20:00 UTC (permalink / raw)
To: Alessandro Zummo, Alexandre Belloni, Rob Herring
Cc: hugo, Hugo Villeneuve, linux-rtc, devicetree, linux-kernel
In-Reply-To: <20220125200009.900660-1-hugo@hugovil.com>
From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Add support for new NXP RTC PCF2131.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
.../devicetree/bindings/rtc/nxp,pcf2127.yaml | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml
index cde7b1675ead..57eb0a58afa3 100644
--- a/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml
+++ b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml
@@ -14,7 +14,9 @@ maintainers:
properties:
compatible:
- const: nxp,pcf2127
+ enum:
+ - nxp,pcf2127
+ - nxp,pcf2131
reg:
maxItems: 1
@@ -48,4 +50,19 @@ examples:
};
};
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@53 {
+ compatible = "nxp,pcf2131";
+ reg = <0x53>;
+ pinctrl-0 = <&rtc_nint_pins>;
+ interrupts-extended = <&gpio1 16 IRQ_TYPE_LEVEL_HIGH>;
+ reset-source;
+ };
+ };
+
...
--
2.30.2
^ permalink raw reply related
* [PATCH 10/10] dt-bindings: rtc: pcf2127: add PCF2131 INT_A and INT_B support
From: Hugo Villeneuve @ 2022-01-25 20:00 UTC (permalink / raw)
To: Alessandro Zummo, Alexandre Belloni, Rob Herring
Cc: hugo, Hugo Villeneuve, linux-rtc, devicetree, linux-kernel
In-Reply-To: <20220125200009.900660-1-hugo@hugovil.com>
From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
The PCF2131 has two output interrupt pins, named INT_A and INT_B.
Add properties to identify onto which pin we want the alarm interrupt
to be routed. It can be either one, or both.
These properties are automatically set to false for variants other
than PCF2131 (ex: PCF2127).
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
.../devicetree/bindings/rtc/nxp,pcf2127.yaml | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml
index 57eb0a58afa3..83656dd2f97f 100644
--- a/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml
+++ b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml
@@ -24,6 +24,16 @@ properties:
interrupts:
maxItems: 1
+ alarm-output-a:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Enable alarm interrupt on INT_A output pin.
+
+ alarm-output-b:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Enable alarm interrupt on INT_B output pin.
+
start-year: true
reset-source: true
@@ -32,6 +42,18 @@ required:
- compatible
- reg
+if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nxp,pcf2131
+then:
+ properties:
+ alarm-output-a: false
+ alarm-output-b: false
+
additionalProperties: false
examples:
@@ -62,6 +84,7 @@ examples:
pinctrl-0 = <&rtc_nint_pins>;
interrupts-extended = <&gpio1 16 IRQ_TYPE_LEVEL_HIGH>;
reset-source;
+ alarm-output-b;
};
};
--
2.30.2
^ permalink raw reply related
* Re: [PATCH v3 6/6] RISC-V: Do not use cpumask data structure for hartid bitmap
From: Geert Uytterhoeven @ 2022-01-25 20:12 UTC (permalink / raw)
To: Atish Patra
Cc: Linux Kernel Mailing List, Anup Patel, Albert Ou, Atish Patra,
Damien Le Moal,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Jisheng Zhang, Krzysztof Kozlowski, linux-riscv, Palmer Dabbelt,
Paul Walmsley, Rob Herring, Emil Renner Berthing
In-Reply-To: <20220120090918.2646626-7-atishp@rivosinc.com>
Hi Atish,
On Thu, Jan 20, 2022 at 10:12 AM Atish Patra <atishp@rivosinc.com> wrote:
> Currently, SBI APIs accept a hartmask that is generated from struct
> cpumask. Cpumask data structure can hold upto NR_CPUs value. Thus, it
> is not the correct data structure for hartids as it can be higher
> than NR_CPUs for platforms with sparse or discontguous hartids.
>
> Remove all association between hartid mask and struct cpumask.
>
> Reviewed-by: Anup Patel <anup@brainfault.org> (For Linux RISC-V changes)
> Acked-by: Anup Patel <anup@brainfault.org> (For KVM RISC-V changes)
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Thanks for your patch, which is now commit 26fb751ca37846c9 ("RISC-V:
Do not use cpumask data structure for hartid bitmap") in v5.17-rc1.
I am having an issue with random userspace SEGVs on Starlight Beta
(which needs out-of-tree patches). It doesn't always manifest
itself immediately, so it took a while to bisect, but I suspect the
above commit to be the culprit.
So far the Icicle looks unaffected.
Do you have a clue?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v3 6/6] RISC-V: Do not use cpumask data structure for hartid bitmap
From: Atish Patra @ 2022-01-25 20:17 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Atish Patra, Linux Kernel Mailing List, Anup Patel, Albert Ou,
Damien Le Moal,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Jisheng Zhang, Krzysztof Kozlowski, linux-riscv, Palmer Dabbelt,
Paul Walmsley, Rob Herring, Emil Renner Berthing
In-Reply-To: <CAMuHMdXJoREF7jZaYWrDUjJqKUSCd82qDVaMEo7VO38ok8J-AA@mail.gmail.com>
On Tue, Jan 25, 2022 at 12:12 PM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>
> Hi Atish,
>
> On Thu, Jan 20, 2022 at 10:12 AM Atish Patra <atishp@rivosinc.com> wrote:
> > Currently, SBI APIs accept a hartmask that is generated from struct
> > cpumask. Cpumask data structure can hold upto NR_CPUs value. Thus, it
> > is not the correct data structure for hartids as it can be higher
> > than NR_CPUs for platforms with sparse or discontguous hartids.
> >
> > Remove all association between hartid mask and struct cpumask.
> >
> > Reviewed-by: Anup Patel <anup@brainfault.org> (For Linux RISC-V changes)
> > Acked-by: Anup Patel <anup@brainfault.org> (For KVM RISC-V changes)
> > Signed-off-by: Atish Patra <atishp@rivosinc.com>
>
> Thanks for your patch, which is now commit 26fb751ca37846c9 ("RISC-V:
> Do not use cpumask data structure for hartid bitmap") in v5.17-rc1.
>
> I am having an issue with random userspace SEGVs on Starlight Beta
> (which needs out-of-tree patches). It doesn't always manifest
> itself immediately, so it took a while to bisect, but I suspect the
> above commit to be the culprit.
>
I have never seen one before during my testing. How frequently do you see them?
Does it happen while running anything or just idle user space results
in SEGVs randomly.
Do you have a trace that I can look into ?
> So far the Icicle looks unaffected.
>
> Do you have a clue?
> Thanks!
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Regards,
Atish
^ permalink raw reply
* Re: [RFC PATCH 1/2] dt-bindings: mtd: partitions: Document new dynamic-partitions node
From: Rafał Miłecki @ 2022-01-25 20:21 UTC (permalink / raw)
To: Ansuel Smith
Cc: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Rob Herring, linux-mtd, devicetree, linux-kernel
In-Reply-To: <61ef243a.1c69fb81.26cae.716b@mx.google.com>
On 24.01.2022 23:12, Ansuel Smith wrote:
> On Mon, Jan 24, 2022 at 11:02:24PM +0100, Rafał Miłecki wrote:
>> On 20.01.2022 21:26, Ansuel Smith wrote:
>>> Document new dynamic-partitions node used to provide an of node for
>>> partition registred at runtime by parsers. This is required for nvmem
>>> system to declare and detect nvmem-cells.
>>>
>>> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
>>> ---
>>> .../mtd/partitions/dynamic-partitions.yaml | 59 +++++++++++++++++++
>>> 1 file changed, 59 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/mtd/partitions/dynamic-partitions.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/mtd/partitions/dynamic-partitions.yaml b/Documentation/devicetree/bindings/mtd/partitions/dynamic-partitions.yaml
>>> new file mode 100644
>>> index 000000000000..7528e49f2d7e
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/mtd/partitions/dynamic-partitions.yaml
>>> @@ -0,0 +1,59 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/mtd/partitions/dynamic-partitions.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Dynamic partitions
>>> +
>>> +description: |
>>> + This binding can be used on platforms which have partitions registered at
>>> + runtime by parsers or partition table present on the flash. Example are
>>> + partitions declared from smem parser or cmdlinepart. This will create an
>>> + of node for these dynamic partition where systems like Nvmem can get a
>>> + reference to register nvmem-cells.
>>> +
>>> + The partition table should be a node named "dynamic-partitions".
>>> + Partitions are then defined as subnodes. Only the label is required
>>> + as any other data will be taken from the parser.
>>> +
>>> +maintainers:
>>> + - Ansuel Smith <ansuelsmth@gmail.com>
>>> +
>>> +properties:
>>> + compatible:
>>> + const: dynamic-partitions
>>> +
>>> +patternProperties:
>>> + "@[0-9a-f]+$":
>>> + $ref: "partition.yaml#"
>>> +
>>> +additionalProperties: true
>>> +
>>> +examples:
>>> + - |
>>> + partitions {
>>> + compatible = "qcom,smem";
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + };
>>> +
>>> + dynamic-partitions {
>>> + compatible = "dynamic-partitions";
>>> +
>>> + art: art {
>>> + label = "0:art";
>>> + read-only;
>>> + compatible = "nvmem-cells";
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> +
>>> + macaddr_art_0: macaddr@0 {
>>> + reg = <0x0 0x6>;
>>> + };
>>> +
>>> + macaddr_art_6: macaddr@6 {
>>> + reg = <0x6 0x6>;
>>> + };
>>> + };
>>> + };
>>
>> First of all: I fully support such a feature. I need it for Broadom
>> platforms that use "brcm,bcm947xx-cfe-partitions" dynamic partitions.
>> In my case bootloader partition is created dynamically (it doesn't have
>> const offset and size). It contains NVMEM data however that needs to be
>> described in DT.
>>
>> This binding however looks loose and confusing to me.
>>
>
> I agree.
>
>> First of all did you really mean to use "qcom,smem"? My first guess is
>> you meant "qcom,smem-part".
>>
>
> Yes sorry, I was referring to the smem parser qcom,smem-part
>
>> Secondly can't we have partitions defined just as subnodes of the
>> partitions { ... }; node?
>>
>
> I would love to use it. My only concern is that due to the fact
> that we have to support legacy partition declaring, wonder if this could
> create some problem. I'm referring to declaring fixed partition without
> using any compatible/standard binding name.
Legacy partitioning won't kick in if you have "partitions" with
"compatible" string. We're safe here. Just checked to be sure.
> I remember we improved that with the introduction of the nvmem binding
> by making the fixed-partition compatible mandatory. But I would like to
> have extra check. Wonder if to be on the safe part we can consider
> appending to the "dynamic parser" a compatible like "dynamic-partitions"
> and use your way to declare them (aka keeping the dynamic-partition and
> removing the extra parallel partitions list)
>
> Feel free to tell me it's just a stupid and unnecessary idea. I just
> have fear to introduce regression in the partition parsing logic.
I'm confused. I think all dynamic partitioners already have a
"compatible" set.
Can you post an example of DT binging you described above, please?
^ permalink raw reply
* Re: [PATCH v9 2/2] clk: microchip: Add driver for Microchip PolarFire SoC
From: Stephen Boyd @ 2022-01-25 20:23 UTC (permalink / raw)
To: conor.dooley
Cc: conor.dooley, cyril.jean, daire.mcnamara, david.abdurachmanov,
devicetree, geert, krzysztof.kozlowski, linux-clk, mturquette,
padmarao.begari, palmer, robh+dt
In-Reply-To: <20220125134010.2528785-1-conor.dooley@microchip.com>
Quoting conor.dooley@microchip.com (2022-01-25 05:40:11)
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Quoting conor.dooley@microchip.com (2021-12-16 06:00:22)
> > > diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile
> > > index f34b247e870f..0dce0b12eac4 100644
> > > --- a/drivers/clk/microchip/Makefile
> > > +++ b/drivers/clk/microchip/Makefile
>
> Snipping the rest, will/have addressed them.
>
> > > +static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws,
> > > + unsigned int num_clks, struct mpfs_clock_data *data,
> > > + struct clk *clk_parent)
> > > +{
> > > + struct clk_hw *hw;
> > > + void __iomem *sys_base = data->base;
> > > + unsigned int i, id;
> > > +
> > > + for (i = 0; i < num_clks; i++) {
> > > + struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];
> > > +
> > > + cfg_hw->cfg.parent = __clk_get_hw(clk_parent);
> > > + cfg_hw->hw.init = CLK_HW_INIT_HW(cfg_hw->cfg.name, cfg_hw->cfg.parent,
> > > + &mpfs_clk_cfg_ops, cfg_hw->cfg.flags);
> > > + hw = mpfs_clk_register_cfg(dev, cfg_hw, sys_base);
> > > + if (IS_ERR(hw)) {
> > > + dev_err(dev, "failed to register clock %s\n", cfg_hw->cfg.name);
> > > + goto err_clk;
> > > + }
> > > +
> > > + id = cfg_hws[i].cfg.id;
> > > + data->hw_data.hws[id] = hw;
> > > + }
> > > +
> > > + return 0;
> > > +
> > > +err_clk:
> > > + while (i--)
> > > + devm_clk_hw_unregister(dev, data->hw_data.hws[cfg_hws[i].cfg.id]);
> >
> > > + clk_parent = devm_clk_get(dev, NULL);
> >
> > Use clk_parent_data instead please.
> >
> > > + if (IS_ERR(clk_parent))
> > > + return PTR_ERR(clk_parent);
>
>
> Please correct me if I am misinterpreting:
> I had the devm_clk_get() in there to pickup the refclk from the device
> tree as a result of previous feedback. I have replaced this with the
> following, which I have found in several other drivers - does it achieve
> the same thing?
> If it does, all of the args to CLK_HW_INIT_PARENTS_DATA are now set at
> compile time & I will take CLK_HW_INIT_PARENTS_DATA back out of this
> function.
>
> static struct clk_parent_data mpfs_cfg_parent[] = {
> { .index = 0 },
> };
Yes this should be sufficient. Make it const though.
>
> static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws,
> unsigned int num_clks, struct mpfs_clock_data *data)
> {
> void __iomem *sys_base = data->base;
> unsigned int i, id;
> int ret;
>
> for (i = 0; i < num_clks; i++) {
> struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];
>
> cfg_hw->hw.init = CLK_HW_INIT_PARENTS_DATA(cfg_hw->cfg.name, mpfs_cfg_parent,
> &mpfs_clk_cfg_ops, cfg_hw->cfg.flags);
>
> ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base);
> if (ret) {
> dev_err_probe(dev, ret, "failed to register clock %s\n",
> cfg_hw->cfg.name);
> return ret;
> }
>
> id = cfg_hws[i].cfg.id;
> data->hw_data.hws[id] = &cfg_hw->hw;
> }
>
> return 0;
> }
Looks good. Thanks.
^ permalink raw reply
* Re: [EXT] Re: [PATCH v8 04/15] media:Add v4l2 event codec_error and skip
From: Nicolas Dufresne @ 2022-01-25 20:23 UTC (permalink / raw)
To: Ming Qian, mchehab@kernel.org, shawnguo@kernel.org,
robh+dt@kernel.org, s.hauer@pengutronix.de
Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de,
festevam@gmail.com, dl-linux-imx, linux-media@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, Alexandre Courbot
In-Reply-To: <AM6PR04MB63414D140EC922139260A8B4E75F9@AM6PR04MB6341.eurprd04.prod.outlook.com>
Le mardi 25 janvier 2022 à 01:54 +0000, Ming Qian a écrit :
> > -----Original Message-----
> > From: Nicolas Dufresne [mailto:nicolas@ndufresne.ca]
> > Sent: Saturday, January 22, 2022 6:25 AM
> > To: Ming Qian <ming.qian@nxp.com>; mchehab@kernel.org;
> > shawnguo@kernel.org; robh+dt@kernel.org; s.hauer@pengutronix.de
> > Cc: hverkuil-cisco@xs4all.nl; kernel@pengutronix.de; festevam@gmail.com;
> > dl-linux-imx <linux-imx@nxp.com>; linux-media@vger.kernel.org;
> > linux-kernel@vger.kernel.org; devicetree@vger.kernel.org;
> > linux-arm-kernel@lists.infradead.org
> > Subject: Re: [EXT] Re: [PATCH v8 04/15] media:Add v4l2 event codec_error and
> > skip
> >
> > Caution: EXT Email
> >
> > Le jeudi 13 janvier 2022 à 07:18 +0000, Ming Qian a écrit :
> > > Hi Nicolas,
> > >
> > > I have question about skip event or similar concepts.
> > > If the client control the input frame count, and it won't queue any more
> > frames unless some frame is decoded.
> > > But after seek, There is no requirement to begin queuing coded data
> > > starting
> > exactly from a resume point (e.g. SPS or a keyframe). Any queued OUTPUT
> > buffers will be processed and returned to the client until a suitable resume
> > point is found. While looking for a resume point, the decoder should not
> > produce any decoded frames into CAPTURE buffers.
> > >
> > > So client may have queued some frames but without any resume point, in
> > this case the decoder won't produce any decoded frames into CAPTURE buffers,
> > and the client won't queue frames into output buffers. This creates some
> > kind
> > of deadlock.
> > >
> > > In our previous solution, we send skip event to client to tell it that
> > > some
> > frame is skipped instead of decoded, then the client can continue to queue
> > frames.
> > > But the skip event is flawed, so we need some solution to resolve it.
> > > 1. decoder can produce an empty buffer with V4L2_BUF_FLAG_SKIPPED (or
> > V4L2_BUF_FLAG_ERROR) as you advised, but this seems to conflict with the
> > above description in specification.
> > > 2. Define a notification mechanism to notify the client
> > >
> > > Can you give some advice? This constraint of frame depth is common on
> > > android
> >
> > Without going against the spec, you can as of today pop a capture buffer and
> > mark it done with error. As it has nothing valid in it, I would also set the
> > payload size to 0.
> >
> > So I'd say, for every unique input timestamp, that didn't yield a frame
> > (skipped),
> > pop a capture buffer, copy the timestamp, set the payload size to 0 and set
> > it
> > as done with error.
> >
> > I'm not sure though if we that we can specify this, as I'm not sure this is
> > possible with all the existing HW. I must admit, I don't myself had to deal
> > with
> > that issue as I'm not using a dummy framework. In GStreamer, we take care of
> > locating the next sync point. So unless there was an error in the framework,
> > this case does not exist for us.
> >
> Hi Nicolas,
> If the decoder can detect the output buffer that may trigger a error, is
> it better setting error flag on the output buffer, but without producing an
> empty capture buffer with error flag set?, or we should return both output and
> capture buffer with error flag set?
> As I can see the following description in spec:
>
> if the decoder is able to precisely report the OUTPUT buffer that triggered
> the error, such buffer will be returned with the V4L2_BUF_FLAG_ERROR flag set.
Interesting, I never noticed this one. I suppose this would mean some early
notification of decode error. I have always assumed that for m2m, the flags
after DQBUF had no meaning, considering we are just getting back an empty
buffer. I do see possible enhancement of error handling if that was to be
implemented.
For more context, if a reordered frame failed, we will only know after we had
notice failures / errors on dependent frame that are earlier in display order.
Such mechanism would tell us earlier. I wonder if it could not also be earlier
still when no reordering take place ? In general, the main goal with such
mechanism is to request a new keyframe (typically in WebRTC / RTP use cases).
To answer you question, the spec says "if the decoder is able", which looks like
a MAY in specification terminology. So if you don't also produce a capture
buffer for the error, I would be worried existing userland will not notice and
keep waiting for the lost frame. Adding Alexandre Courbot in CC, he may have
more context around this, and perhaps Chromium is using that.
>
>
> > >
> > > Ming
> > >
> > > > > > > + * - ``V4L2_EVENT_SKIP``
> > > > > > > + - 8
> > > > > > > + - This event is triggered when one frame is decoded,
> > > > > > > + but it won't
> > > > > > > be
> > > > > > outputed
> > > > > > > + to the display. So the application can't get this frame,
> > > > > > > + and the
> > > > > > > input
> > > > > > frame count
> > > > > > > + is dismatch with the output frame count. And this evevt
> > > > > > > + is telling
> > > > > > > the
> > > > > > client to
> > > > > > > + handle this case.
> > > > > >
> > > > > > Similar to my previous comment, this event is flawed, since
> > > > > > userspace cannot know were the skip is located in the queued
> > > > > > buffers. Currently, all decoders are mandated to support
> > > > > > V4L2_BUF_FLAG_TIMESTAMP_COPY. The timestamp must NOT be
> > > > interpreted
> > > > > > by the driver and must be reproduce as-is in the associated
> > > > > > CAPTURE buffer. It is possible to "garbage" collect skipped
> > > > > > frames with this method, though tedious.
> > > > > >
> > > > > > An alternative, and I think it would be much nicer then this,
> > > > > > would be to use the v4l2_buffer.sequence counter, and just make
> > > > > > it skip 1 on skips. Though, the down side is that userspace must
> > > > > > also know how to reorder frames (a driver job for stateless
> > > > > > codecs) in order to identify which frame was skipped. So this is
> > > > > > perhaps not that useful, other then knowing something was skipped in
> > the past.
> > > > > >
> > > > > > A third option would be to introduce V4L2_BUF_FLAG_SKIPPED. This
> > > > > > way the driver could return an empty payload (bytesused = 0)
> > > > > > buffer with this flag set, and the proper timestamp properly
> > > > > > copied. This would let the driver communicate skipped frames in
> > > > > > real-time. Note that this could break with existing userspace,
> > > > > > so it would need to be opted-in somehow (a control or some flags).
> > > > >
> > > > > Hi Nicolas,
> > > > > The problem we meet is that userspace doesn't care which frame
> > > > > is skipped, it just need to know that there are a frame is
> > > > > skipped, the driver should promise the input frame count is equals
> > > > > to the output frame
> > > > count.
> > > > > Your first method is possible in theory, but we find the
> > > > > timestamp may be unreliable, we meet many timestamp issues that
> > > > > userspace may enqueue invalid timestamp or repeated timestamp and
> > > > > so on, so we can't
> > > > accept this solution.
> > > >
> > > > The driver should not interpret the provided timestamp, so it should
> > > > not be able to say if the timestamp is valid or not, this is not the
> > > > driver's
> > task.
> > > >
> > > > The driver task is to match the timestamp to the CAPTURE buffer (if
> > > > that buffer was produced), and reproduce it exactly.
> > > >
> > > > > I think your second option is better. And there are only 1
> > > > > question, we find some application prefer to use the
> > > > > V4L2_EVENT_EOS to check the eos, not checking the empty buffer, if
> > > > > we use this method to check skipped frame, the
> > > >
> > > > Checking the empty buffer is a legacy method, only available in
> > > > Samsung MFC driver. The spec says that the last buffer should be
> > > > flagged with _LAST, and any further attempt to poll should unblock and
> > DQBUF return EPIPE.
> > > >
> > > > > application should check empty buffer instead of V4L2_EVENT_EOS,
> > > > > otherwise if the last frame is skipped, the application will miss it.
> > > > > Of course this is not a problem, it just increases the complexity
> > > > > of the userspace implementation
> > > >
> > > > The EPIPE mechanism covers this issue, which we initially had with
> > > > the LAST flag.
> > > >
> > > > > I don't think your third method is feasible, the reasons are as
> > > > > below
> > > > > 1. usually the empty payload means eos, and as you
> > > > > say, it may introduce confusion.
> > > > > 2. The driver may not have the opportunity to return an
> > > > > empty payload during decoding, in our driver, driver will pass the
> > > > > capture buffer to firmware, and when some frame is skipped, the
> > > > > firmware won't return the buffer, driver may not find an available
> > > > > capture buffer to return to userspace.
> > > > >
> > > > > The requirement is that userspace need to match the input frame
> > > > > count and output frame count. It doesn't care which frame is
> > > > > skipped, so the V4L2_EVENT_SKIP is the easiest way for driver and
> > userspace.
> > > > > If you think this event is really inappropriate, I prefer to
> > > > > adopt your second option
> > > >
> > > > Please, drop SKIP from you driver and this patchset and fix your
> > > > draining process handling to follow the spec. The Samsung OMX
> > > > component is irrelevant to mainline submission, the OMX code should
> > > > be updated to follow the spec.
> > > >
> > > > >
>
^ permalink raw reply
* Re: [RFC PATCH v2 2/2] leds: Add PWM multicolor driver
From: Marek Behún @ 2022-01-25 20:21 UTC (permalink / raw)
To: sven
Cc: linux-leds, devicetree, linux-pwm, Sven Schwermer, pavel, dmurphy,
robh+dt, thierry.reding, u.kleine-koenig, lee.jones, post
In-Reply-To: <20220125151226.31049-3-sven@svenschwermer.de>
On Tue, 25 Jan 2022 16:12:26 +0100
sven@svenschwermer.de wrote:
> From: Sven Schwermer <sven.schwermer@disruptive-technologies.com>
>
> By allowing to group multiple monochrome PWM LEDs into multicolor LEDs,
> all involved LEDs can be controlled in-sync. This enables using effects
> using triggers, etc.
>
> Signed-off-by: Sven Schwermer <sven.schwermer@disruptive-technologies.com>
> ---
> drivers/leds/Kconfig | 8 ++
> drivers/leds/Makefile | 1 +
> drivers/leds/leds-pwm-multicolor.c | 184 +++++++++++++++++++++++++++++
> 3 files changed, 193 insertions(+)
> create mode 100644 drivers/leds/leds-pwm-multicolor.c
>
> diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
> index 6090e647daee..bae1f63f6195 100644
> --- a/drivers/leds/Kconfig
> +++ b/drivers/leds/Kconfig
> @@ -552,6 +552,14 @@ config LEDS_PWM
> help
> This option enables support for pwm driven LEDs
>
> +config LEDS_PWM_MULTICOLOR
> + tristate "PWM driven multi-color LED Support"
> + depends on LEDS_CLASS_MULTICOLOR
> + depends on PWM
> + help
> + This option enables support for PWM driven monochrome LEDs that are
> + grouped into multicolor LEDs.
> +
> config LEDS_REGULATOR
> tristate "REGULATOR driven LED support"
> depends on LEDS_CLASS
> diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
> index e58ecb36360f..ba2c2c1edf12 100644
> --- a/drivers/leds/Makefile
> +++ b/drivers/leds/Makefile
> @@ -73,6 +73,7 @@ obj-$(CONFIG_LEDS_PCA963X) += leds-pca963x.o
> obj-$(CONFIG_LEDS_PM8058) += leds-pm8058.o
> obj-$(CONFIG_LEDS_POWERNV) += leds-powernv.o
> obj-$(CONFIG_LEDS_PWM) += leds-pwm.o
> +obj-$(CONFIG_LEDS_PWM_MULTICOLOR) += leds-pwm-multicolor.o
> obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o
> obj-$(CONFIG_LEDS_S3C24XX) += leds-s3c24xx.o
> obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o
> diff --git a/drivers/leds/leds-pwm-multicolor.c b/drivers/leds/leds-pwm-multicolor.c
> new file mode 100644
> index 000000000000..c54bed4536d3
> --- /dev/null
> +++ b/drivers/leds/leds-pwm-multicolor.c
> @@ -0,0 +1,184 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * PWM-based multi-color LED control
> + *
> + * Copyright 2022 Sven Schwermer <sven.schwermer@disruptive-technologies.com>
> + */
> +
> +#include <linux/module.h>
> +#include <linux/kernel.h>
> +#include <linux/platform_device.h>
> +#include <linux/led-class-multicolor.h>
> +#include <linux/leds.h>
> +#include <linux/err.h>
> +#include <linux/pwm.h>
> +#include <linux/mutex.h>
sort headers alphabetically
> +
> +struct pwm_led {
> + struct pwm_device *pwm;
> + struct pwm_state pwmstate;
maybe rename pwmstate to just state?
> +};
> +
> +struct pwm_mc_led {
> + struct led_classdev_mc mc_cdev;
> + struct mutex lock;
> + struct pwm_led leds[];
> +};
> +
> +static int led_pwm_mc_set(struct led_classdev *cdev,
> + enum led_brightness brightness)
> +{
> + int i;
> + unsigned long long duty;
> + int ret = 0;
> + struct led_classdev_mc *mc_cdev = lcdev_to_mccdev(cdev);
> + struct pwm_mc_led *priv = container_of(mc_cdev, struct pwm_mc_led, mc_cdev);
> +
> + led_mc_calc_color_components(mc_cdev, brightness);
> +
> + mutex_lock(&priv->lock);
> +
> + for (i = 0; i < mc_cdev->num_colors; ++i) {
> + duty = priv->leds[i].pwmstate.period;
> + duty *= mc_cdev->subled_info[i].brightness;
> + do_div(duty, cdev->max_brightness);
> +
> + priv->leds[i].pwmstate.duty_cycle = duty;
> + priv->leds[i].pwmstate.enabled = duty > 0;
> + ret = pwm_apply_state(priv->leds[i].pwm,
> + &priv->leds[i].pwmstate);
> + if (ret)
> + break;
> + }
> +
> + mutex_unlock(&priv->lock);
> +
> + return ret;
> +}
> +
> +static int led_pwm_mc_probe(struct platform_device *pdev)
> +{
> + struct fwnode_handle *mcnode, *fwnode;
> + int count = 0;
> + struct pwm_mc_led *priv;
> + struct mc_subled *subled;
> + struct led_classdev *cdev;
> + struct pwm_led *pwmled;
> + u32 color;
> + int ret = 0;
> + struct led_init_data init_data = {};
> +
> + mcnode = device_get_named_child_node(&pdev->dev, "multi-led");
> + if (!mcnode) {
> + dev_err(&pdev->dev, "expected multi-led node\n");
> + ret = -ENODEV;
> + goto out;
> + }
> +
> + /* count the nodes inside the multi-led node */
> + fwnode_for_each_child_node(mcnode, fwnode)
> + ++count;
> +
> + priv = devm_kzalloc(&pdev->dev, struct_size(priv, leds, count),
> + GFP_KERNEL);
> + if (!priv) {
> + ret = -ENOMEM;
> + goto out;
> + }
> + mutex_init(&priv->lock);
> +
> + subled = devm_kcalloc(&pdev->dev, count, sizeof(*subled), GFP_KERNEL);
> + if (!subled) {
> + ret = -ENOMEM;
> + goto destroy_mutex;
> + }
> + priv->mc_cdev.subled_info = subled;
> +
> + /* init the multicolor's LED class device */
> + cdev = &priv->mc_cdev.led_cdev;
> + fwnode_property_read_string(mcnode, "label", &cdev->name);
label is deprecated, do not introduce in new bindings
> + cdev->brightness = LED_OFF;
dont use this LED_OFF/LED_ON constants, they are deprecated
> + fwnode_property_read_u32(mcnode, "max-brightness",
> + &cdev->max_brightness);
> + cdev->flags = LED_CORE_SUSPENDRESUME;
> + cdev->brightness_set_blocking = led_pwm_mc_set;
> +
> + /* iterate over the nodes inside the multi-led node */
> + fwnode_for_each_child_node(mcnode, fwnode) {
> + pwmled = &priv->leds[priv->mc_cdev.num_colors];
> + pwmled->pwm = devm_fwnode_pwm_get(&pdev->dev, fwnode, NULL);
> + if (IS_ERR(pwmled->pwm)) {
> + ret = PTR_ERR(pwmled->pwm);
> + dev_err(&pdev->dev, "unable to request PWM: %d\n", ret);
you need to release the fwnode with fwnode_handle_put(fwnode) here
> + goto destroy_mutex;
> + }
> + pwm_init_state(pwmled->pwm, &pwmled->pwmstate);
> +
> + ret = fwnode_property_read_u32(fwnode, "color", &color);
> + if (ret) {
> + dev_err(&pdev->dev, "cannot read color: %d\n", ret);
you need to release the fwnode with fwnode_handle_put(fwnode) here
> + goto destroy_mutex;
> + }
> +
> + subled[priv->mc_cdev.num_colors].color_index = color;
> + subled[priv->mc_cdev.num_colors].channel =
> + priv->mc_cdev.num_colors;
> + ++priv->mc_cdev.num_colors;
> + }
> +
> + init_data.fwnode = mcnode;
> + ret = devm_led_classdev_multicolor_register_ext(&pdev->dev,
> + &priv->mc_cdev,
> + &init_data);
> + if (ret) {
> + dev_err(&pdev->dev,
> + "failed to register multicolor PWM led for %s: %d\n",
> + cdev->name, ret);
> + goto destroy_mutex;
> + }
> +
> + ret = led_pwm_mc_set(cdev, cdev->brightness);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to set led PWM value for %s: %d",
> + cdev->name, ret);
> + goto destroy_mutex;
> + }
> +
you need to release mcnode with fwnode_handle_put(). You increased reference
count with device_get_named_child_node()
> + platform_set_drvdata(pdev, priv);
> + return 0;
> +
> +destroy_mutex:
> + mutex_destroy(&priv->lock);
> +out:
here as well you need to release mcnode with fwnode_handle_put()
> + return ret;
> +}
> +
> +static int led_pwm_mc_remove(struct platform_device *pdev)
> +{
> + struct pwm_mc_led *priv = platform_get_drvdata(pdev);
> +
> + mutex_destroy(&priv->lock);
> + return 0;
> +}
> +
> +static const struct of_device_id of_pwm_leds_mc_match[] = {
> + { .compatible = "pwm-leds-multicolor", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, of_pwm_leds_mc_match);
> +
> +static struct platform_driver led_pwm_mc_driver = {
> + .probe = led_pwm_mc_probe,
> + .remove = led_pwm_mc_remove,
> + .driver = {
> + .name = "leds_pwm_multicolor",
> + .of_match_table = of_pwm_leds_mc_match,
> + },
> +};
> +
> +module_platform_driver(led_pwm_mc_driver);
> +
> +MODULE_AUTHOR("Sven Schwermer <sven.schwermer@disruptive-technologies.com>");
> +MODULE_DESCRIPTION("multi-color PWM LED driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:leds-pwm-multicolor");
^ permalink raw reply
* Re: [RFC PATCH v2 1/2] dt-bindings: leds: Add multicolor PWM LED bindings
From: Marek Behún @ 2022-01-25 20:27 UTC (permalink / raw)
To: sven
Cc: linux-leds, devicetree, linux-pwm, Sven Schwermer, pavel, dmurphy,
robh+dt, thierry.reding, u.kleine-koenig, lee.jones, post
In-Reply-To: <20220125151226.31049-2-sven@svenschwermer.de>
On Tue, 25 Jan 2022 16:12:25 +0100
sven@svenschwermer.de wrote:
> From: Sven Schwermer <sven.schwermer@disruptive-technologies.com>
>
> This allows to group multiple PWM-connected monochrome LEDs into
> multicolor LEDs, e.g. RGB LEDs.
>
> Signed-off-by: Sven Schwermer <sven.schwermer@disruptive-technologies.com>
> ---
> .../bindings/leds/leds-pwm-multicolor.yaml | 76 +++++++++++++++++++
> 1 file changed, 76 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/leds/leds-pwm-multicolor.yaml
>
> diff --git a/Documentation/devicetree/bindings/leds/leds-pwm-multicolor.yaml b/Documentation/devicetree/bindings/leds/leds-pwm-multicolor.yaml
> new file mode 100644
> index 000000000000..b82b26f2e140
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/leds/leds-pwm-multicolor.yaml
> @@ -0,0 +1,76 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/leds/leds-pwm-multicolor.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Multi-color LEDs connected to PWM
> +
> +maintainers:
> + - Sven Schwermer <sven.schwermer@disruptive-technologies.com>
> +
> +description: |
> + This driver combines several monochrome PWM LEDs into one multi-color
> + LED using the multicolor LED class.
> +
> +properties:
> + compatible:
> + const: pwm-leds-multicolor
> +
> +patternProperties:
> + '^multi-led@[0-9a-f]$':
> + type: object
> + allOf:
> + - $ref: leds-class-multicolor.yaml#
> +
> + patternProperties:
> + "^led-[0-9a-z]+$":
> + type: object
> + properties:
> + pwms:
> + maxItems: 1
> +
> + pwm-names: true
> +
> + color:
> + $ref: common.yaml#/properties/color
> +
> + required:
> + - pwms
> + - color
> +
> +required:
> + - compatible
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/leds/common.h>
> +
> + rgb-led {
> + compatible = "pwm-leds-multicolor";
> +
> + multi-led@0 {
> + color = <LED_COLOR_ID_RGB>;
> + function = LED_FUNCTION_INDICATOR;
> + max-brightness = <65535>;
> +
> + led-red {
> + pwms = <&pwm1 0 1000000>;
> + color = <LED_COLOR_ID_RED>;
> + };
> +
> + led-green {
> + pwms = <&pwm2 0 1000000>;
> + color = <LED_COLOR_ID_GREEN>;
> + };
> +
> + led-blue {
> + pwms = <&pwm3 0 1000000>;
> + color = <LED_COLOR_ID_BLUE>;
> + };
> + };
what about
multi-led@0 {
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_INDICATOR;
pwms = <&pwm1 0 1000000>,
<&pwm2 0 1000000>,
<&pwm3 0 1000000>;
channels = <LED_COLOR_ID_RED>,
<LED_COLOR_ID_GREEN>,
<LED_COLOR_ID_BLUE>;
};
I am not saying that it is necessarily better, just comenting that
maybe it is, since it saves some space. `pwms` is phandle-array, so it
can contain references to multiple pwms, and we have functions which
make getting these pwms in driver code easy...
Also this example won't compile with
make dt_bindings_check
because you don't have pwm1, pwm2
and pwm3 defined...
Marek
^ permalink raw reply
* Re: [RFC PATCH 1/2] dt-bindings: mtd: partitions: Document new dynamic-partitions node
From: Ansuel Smith @ 2022-01-25 20:30 UTC (permalink / raw)
To: Rafał Miłecki
Cc: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Rob Herring, linux-mtd, devicetree, linux-kernel
In-Reply-To: <ef34a0b2-3b13-863b-86b9-71832eace360@gmail.com>
On Tue, Jan 25, 2022 at 09:21:04PM +0100, Rafał Miłecki wrote:
> On 24.01.2022 23:12, Ansuel Smith wrote:
> > On Mon, Jan 24, 2022 at 11:02:24PM +0100, Rafał Miłecki wrote:
> > > On 20.01.2022 21:26, Ansuel Smith wrote:
> > > > Document new dynamic-partitions node used to provide an of node for
> > > > partition registred at runtime by parsers. This is required for nvmem
> > > > system to declare and detect nvmem-cells.
> > > >
> > > > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > > > ---
> > > > .../mtd/partitions/dynamic-partitions.yaml | 59 +++++++++++++++++++
> > > > 1 file changed, 59 insertions(+)
> > > > create mode 100644 Documentation/devicetree/bindings/mtd/partitions/dynamic-partitions.yaml
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/mtd/partitions/dynamic-partitions.yaml b/Documentation/devicetree/bindings/mtd/partitions/dynamic-partitions.yaml
> > > > new file mode 100644
> > > > index 000000000000..7528e49f2d7e
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/mtd/partitions/dynamic-partitions.yaml
> > > > @@ -0,0 +1,59 @@
> > > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/mtd/partitions/dynamic-partitions.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: Dynamic partitions
> > > > +
> > > > +description: |
> > > > + This binding can be used on platforms which have partitions registered at
> > > > + runtime by parsers or partition table present on the flash. Example are
> > > > + partitions declared from smem parser or cmdlinepart. This will create an
> > > > + of node for these dynamic partition where systems like Nvmem can get a
> > > > + reference to register nvmem-cells.
> > > > +
> > > > + The partition table should be a node named "dynamic-partitions".
> > > > + Partitions are then defined as subnodes. Only the label is required
> > > > + as any other data will be taken from the parser.
> > > > +
> > > > +maintainers:
> > > > + - Ansuel Smith <ansuelsmth@gmail.com>
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + const: dynamic-partitions
> > > > +
> > > > +patternProperties:
> > > > + "@[0-9a-f]+$":
> > > > + $ref: "partition.yaml#"
> > > > +
> > > > +additionalProperties: true
> > > > +
> > > > +examples:
> > > > + - |
> > > > + partitions {
> > > > + compatible = "qcom,smem";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + };
> > > > +
> > > > + dynamic-partitions {
> > > > + compatible = "dynamic-partitions";
> > > > +
> > > > + art: art {
> > > > + label = "0:art";
> > > > + read-only;
> > > > + compatible = "nvmem-cells";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > +
> > > > + macaddr_art_0: macaddr@0 {
> > > > + reg = <0x0 0x6>;
> > > > + };
> > > > +
> > > > + macaddr_art_6: macaddr@6 {
> > > > + reg = <0x6 0x6>;
> > > > + };
> > > > + };
> > > > + };
> > >
> > > First of all: I fully support such a feature. I need it for Broadom
> > > platforms that use "brcm,bcm947xx-cfe-partitions" dynamic partitions.
> > > In my case bootloader partition is created dynamically (it doesn't have
> > > const offset and size). It contains NVMEM data however that needs to be
> > > described in DT.
> > >
> > > This binding however looks loose and confusing to me.
> > >
> >
> > I agree.
> >
> > > First of all did you really mean to use "qcom,smem"? My first guess is
> > > you meant "qcom,smem-part".
> > >
> >
> > Yes sorry, I was referring to the smem parser qcom,smem-part
> >
> > > Secondly can't we have partitions defined just as subnodes of the
> > > partitions { ... }; node?
> > >
> >
> > I would love to use it. My only concern is that due to the fact
> > that we have to support legacy partition declaring, wonder if this could
> > create some problem. I'm referring to declaring fixed partition without
> > using any compatible/standard binding name.
>
> Legacy partitioning won't kick in if you have "partitions" with
> "compatible" string. We're safe here. Just checked to be sure.
>
Oh ok then the dynamic partition compatible stuff is not needed.
To make sure I will change the "connect" function part and skip the
of_node assign if a compatible is not present. (The of_node assign
should be done only with the nvmem-cell compatible currently.)
>
> > I remember we improved that with the introduction of the nvmem binding
> > by making the fixed-partition compatible mandatory. But I would like to
> > have extra check. Wonder if to be on the safe part we can consider
> > appending to the "dynamic parser" a compatible like "dynamic-partitions"
> > and use your way to declare them (aka keeping the dynamic-partition and
> > removing the extra parallel partitions list)
> >
> > Feel free to tell me it's just a stupid and unnecessary idea. I just
> > have fear to introduce regression in the partition parsing logic.
>
> I'm confused. I think all dynamic partitioners already have a
> "compatible" set.
Now that I think about it you are right. If a dynamic partition is
present in the system, a compatible must be present to use the correct
parser. And as I said up, all the nvmem cells should have the
correct compatible.
>
> Can you post an example of DT binging you described above, please?
Was thinking something like this. But not needed.
partitions {
compatible = "brcm,bcm947xx-cfe-partitions", "dynamic-partitions";
partition-0 {
compatible = "nvmem-cells";
label = "boot";
#address-cells = <1>;
#size-cells = <1>;
mac: macaddr@0 {
reg = <0x100 0x6>;
};
}
};
So in short, a scheme like this should NOT be handled/should not have
of_node assigned. (and is actually very wrong)
partitions {
compatible = "brcm,bcm947xx-cfe-partitions";
partition-0 {
label = "boot";
#address-cells = <1>;
#size-cells = <1>;
mac: macaddr@0 {
reg = <0x100 0x6>;
};
}
};
--
Ansuel
^ permalink raw reply
* Re: [PATCH v7 3/6] dt-bindings: mvebu-uart: document DT bindings for marvell,armada-3700-uart-clock
From: Stephen Boyd @ 2022-01-25 20:40 UTC (permalink / raw)
To: Pali Rohár
Cc: Marek Behún, Greg Kroah-Hartman, Michael Turquette,
Rob Herring, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Vladimir Vid, linux-clk, linux-serial, linux-kernel,
linux-arm-kernel, devicetree
In-Reply-To: <20220120092641.o4ffzeyakhuuf3c7@pali>
Quoting Pali Rohár (2022-01-20 01:26:41)
> On Wednesday 19 January 2022 22:01:47 Stephen Boyd wrote:
> > >
> > > Ok, now I see what you mean.
> > >
> > > But problem is that this is not backward compatible change. And would
> > > not work per existing DT bindings definitions, which defines how
> > > bootloader should set configured clocks.
> > >
> > > As I wrote in emails 3 months ago, this new "proposed" DTS definition is
> > > something which I would have chosen if I had designed this driver and
> > > bindings in past. But that did not happen and different approach is
> > > already widely in used.
> > >
> > > To support existing DTS definitions and bootloaders, it is really
> > > required to have current structure backward compatible like it is
> > > defined in current DT bindings document. And my changes in this patch
> > > series are backward compatible.
> >
> > I'm lost. Is the bootloader the one that's expecting some particular
> > serial node format and updating something? What is the bootloader doing?
>
> If bootloader uses or configures UART to different clock it needs to
> update "clocks" property in DT. Otherwise UART would be unusable and
> there would be no dmesg output.
Got it! I didn't see that part mentioned anywhere in the commit text
though. To the uninformed reviewer like me it is hard to know about this
bootloader design unless the commit text explains that there's no other
way to do this.
>
> A3720 heavily depends that bootloader patches at boot time DTB file to
> the layout of the current hardware.
>
> > >
> > > To change DTS structure, it would be needed to provide uart nodes in DTS
> > > files two times: once in old style (the current one) and second time in
> > > this new style.
> >
> > That's not a good idea. Why do we need to support both at the same time?
>
> Because old bootloaders do not and will never support this new style. It
> is not only linux kernel project who provides DTB files. Also bootloader
> itself has own DTB files and use it for booting (e.g kernel). For some
> boards is in-kernel-tree DTS file only as a reference. So it is
> important that kernel can use and support DTS files from old version and
> also from the new patched version. Gregory (A3720 DTS files maintainer)
> always ask me what happens if I try to boot new patched kernel drivers
> with old unmodified DTS files and wants to know if nothing is broken by
> introduced changed.
>
> > >
> > > But such thing would even more complicate updating driver and it needs
> > > to be implemented.
> > >
> > > Plus this would open a question how to define default stdout-path if
> > > there would be 4 serial nodes, where one pair would describe old style
> > > and second pair new style; meaning that 2 cross nodes would describe
> > > same define.
> >
> > Huh? We shouldn't have both bindings present in the DTB.
>
> Ideally yes, I would like to see to prevent it. But for backward
> compatibility we really need old bindings still present (as explained
> above).
>
> So really I see two options here: Make changes in patches backward
> compatible (old nodes stay in DT and also kernel would be able to use
> old DT). Or let old bindings untouched in DT and new backward
> incompatible definitions would have to be in separate nodes.
Ok I understand now. We have to keep both the serial nodes because the
bootloader is patching them. To make matters worse, one or the other
node may be disabled so we can't even add the new bits to the uart1
node. Can you update the commit text to record this sad state of affairs
and indicate that the only way to support this is to make a new node in
DT that the bootloader doesn't know about?
^ permalink raw reply
* Re: [PATCH] Adding architectural support for HPE's GXP BMC. This is the first of a series of patches to support HPE's BMC with Linux Kernel.
From: Krzysztof Kozlowski @ 2022-01-25 20:41 UTC (permalink / raw)
To: nick.hawkins, verdun
Cc: Rob Herring, Russell King, Shawn Guo, Stanislav Jakubek,
Sam Ravnborg, Linus Walleij, Hao Fang, Arnd Bergmann,
Russell King (Oracle), Geert Uytterhoeven, Mark Rutland,
Ard Biesheuvel, Anshuman Khandual, Lukas Bulwahn, Masahiro Yamada,
devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20220125194609.32314-1-nick.hawkins@hpe.com>
On 25/01/2022 20:46, nick.hawkins@hpe.com wrote:
> From: Nick Hawkins <nick.hawkins@hpe.com>
>
Thanks for the patches. The commit should come with description. Please
check other commits adding new sub-arch or boards for nice examples.
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
> ---
> .../devicetree/bindings/vendor-prefixes.yaml | 2 +
> MAINTAINERS | 8 +
> arch/arm/Kconfig | 2 +
> arch/arm/boot/dts/gxp.dts | 700 ++++++++++++++++++
DTS goes separately.
> arch/arm/configs/gxp_defconfig | 243 ++++++
Defconfig is separate commit.
> arch/arm/mach-hpe/Kconfig | 20 +
> arch/arm/mach-hpe/Makefile | 1 +
> arch/arm/mach-hpe/gxp.c | 63 ++
> 8 files changed, 1039 insertions(+)
> create mode 100644 arch/arm/boot/dts/gxp.dts
> create mode 100644 arch/arm/configs/gxp_defconfig
> create mode 100644 arch/arm/mach-hpe/Kconfig
> create mode 100644 arch/arm/mach-hpe/Makefile
> create mode 100644 arch/arm/mach-hpe/gxp.c
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index 294093d45a23..e8b0ec874aed 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -515,6 +515,8 @@ patternProperties:
> description: Jiangsu HopeRun Software Co., Ltd.
> "^hp,.*":
> description: Hewlett Packard
Is Hewlett Packard not an Enterprise?
> + "^hpe,.*":
> + description: Hewlett Packard Enterprise
...
> "^hsg,.*":
> description: HannStar Display Co.
> "^holtek,.*":
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ea3e6c914384..007d99734dd1 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -8382,6 +8382,14 @@ L: linux-efi@vger.kernel.org
> S: Maintained
> F: block/partitions/efi.*
>
> +GXP ARCHITECTURE
> +M: Jean-Marie Verdun <verdun@hpe.com>
> +M: Nick Hawkins <nick.hawkins@hpe.com>
> +S: Maintained
> +F: arch/arm/boot/dts/gxp.dts
> +F: arch/arm/configs/gxp_defconfig
> +F: arch/arm/mach-hpe/gxp.c
> +
> H8/300 ARCHITECTURE
> M: Yoshinori Sato <ysato@users.sourceforge.jp>
> L: uclinux-h8-devel@lists.sourceforge.jp (moderated for non-subscribers)
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index fabe39169b12..d428d0d35889 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -708,6 +708,8 @@ source "arch/arm/mach-vt8500/Kconfig"
>
> source "arch/arm/mach-zynq/Kconfig"
>
> +source "arch/arm/mach-hpe/Kconfig"
All entries in that secion are ordered alphabetically, so mach-hp or
mach-hpe should not stick out.
> +
> # ARMv7-M architecture
> config ARCH_LPC18XX
> bool "NXP LPC18xx/LPC43xx"
> diff --git a/arch/arm/boot/dts/gxp.dts b/arch/arm/boot/dts/gxp.dts
This needs some better, longer name than just gxp... Look how other
files are named in that directory.
> new file mode 100644
> index 000000000000..7bd814ecaaee
> --- /dev/null
> +++ b/arch/arm/boot/dts/gxp.dts
Where is DTSI? What is this file about? Why there is no description?
What's the purpose?
Where is the dts Makefile change? How do you compile it?
> @@ -0,0 +1,700 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree file for HPE GXP
> + */
> +
> +/dts-v1/;
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "HPE,GXP";
Didn't checkpatch complain about undocumented compatible?
If even if it did not, you need to document it. And solve all the issues
like - why uppercase, where is DTSI or SoC compatible... and what is it
exactly?
> + model = "GXP";
So informative... Model GXP like compatible.
> +
> + chosen {
> + bootargs = "earlyprintk console=ttyS0,115200 user_debug=31";
earlyprint is a debugging feature, not suitable for mainline DTS. The
same seems with "user_debug=31". Remove both.
Console should go to chosen stdout-path node instead.
> + };
> +
> + aliases {
> + };
No need for an empty node.
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x40000000 0x20000000>;
> + };
> +
> + ahb@80000000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + vic0: vic@ceff0000 {
Node names should be generic, so this is interrupt-controller.
> + compatible = "arm,pl192-vic";
> + interrupt-controller;
> + reg = <0xceff0000 0x1000>;
> + #interrupt-cells = <1>;
> + };
> +
> + vic1: vic@80f00000 {
> + compatible = "arm,pl192-vic";
> + interrupt-controller;
> + reg = <0x80f00000 0x1000>;
> + #interrupt-cells = <1>;
> + };
> +
> + timer0: timer@c0000080 {
> + compatible = "hpe,gxp-timer";
Undocumented compatible. Also looks too generic.
> + reg = <0xc0000080 0x1>, <0xc0000094 0x01>, <0xc0000088 0x08>;
> + interrupts = <0>;
> + interrupt-parent = <&vic0>;
> + clock-frequency = <400000000>;
> + };
> +
> + watchdog: watchdog@c0000090 {
> + compatible = "hpe,gxp-wdt";
Undocumented compatible. Also looks too generic.
> + reg = <0xc0000090 0x02>, <0xc0000096 0x01>;
> + };
> +
> + uartc: serial@c00000f0 {
> + compatible = "ns16550a";
> + reg = <0xc00000f0 0x8>;
> + interrupts = <19>;
> + interrupt-parent = <&vic0>;
> + clock-frequency = <1846153>;
> + reg-shift = <0>;
> + };
> +
> + uarta: serial@c00000e0 {
> + compatible = "ns16550a";
> + reg = <0xc00000e0 0x8>;
> + interrupts = <17>;
> + interrupt-parent = <&vic0>;
> + clock-frequency = <1846153>;
> + reg-shift = <0>;
> + };
> +
> + uartb: serial@c00000e8 {
> + compatible = "ns16550a";
> + reg = <0xc00000e8 0x8>;
> + interrupts = <18>;
> + interrupt-parent = <&vic0>;
> + clock-frequency = <1846153>;
> + reg-shift = <0>;
> + };
> +
> + vuart_a_cfg: vuarta_cfg@80fc0230 {
> + compatible = "hpe,gxp-vuarta_cfg", "simple-mfd", "syscon";
> + reg = <0x80fc0230 0x100>;
> + reg-io-width = <1>;
> + };
> +
> + vuart_a: vuart_a@80fd0200 {
> + compatible = "hpe,gxp-vuart";
> + reg = <0x80fd0200 0x100>;
> + interrupts = <2>;
> + interrupt-parent = <&vic1>;
> + clock-frequency = <1846153>;
> + reg-shift = <0>;
> + status = "okay";
> + serial-line = <3>;
> + vuart_cfg = <&vuart_a_cfg>;
> + };
> +
> + usb0: ehci@cefe0000 {
> + compatible = "generic-ehci";
> + reg = <0xcefe0000 0x100>;
> + interrupts = <7>;
> + interrupt-parent = <&vic0>;
> + };
> +
> + usb1: ohci@cefe0100 {
> + compatible = "generic-ohci";
> + reg = <0xcefe0100 0x110>;
> + interrupts = <6>;
> + interrupt-parent = <&vic0>;
> + };
> +
> + spifi0: spifi@c0000200 {
What is spifi? Maybe "spi"?
> + compatible = "hpe,gxp-spifi";
Undocumented compatible. Also looks too generic.
> + reg = <0xc0000200 0x80>, <0xc000c000 0x100>, <0xf8000000 0x8000000>;
> + interrupts = <20>;
> + interrupt-parent = <&vic0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + bmc@0 {
> + label = "bmc";
> + reg = <0x0 0x2000000>;
> + };
> + u-boot@0 {
> + label = "u-boot";
> + reg = <0x0 0x60000>;
> + };
> + u-boot-env@60000 {
> + label = "u-boot-env";
> + reg = <0x60000 0x20000>;
> + };
> + kernel@80000 {
> + label = "kernel";
> + reg = <0x80000 0x4c0000>;
> + };
> + rofs@540000 {
> + label = "rofs";
> + reg = <0x540000 0x1740000>;
> + };
> + rwfs@1c80000 {
> + label = "rwfs";
> + reg = <0x1c80000 0x250000>;
> + };
> + section@1edf000{
> + label = "section";
> + reg = <0x1ed0000 0x130000>;
> + };
> + };
> + };
> +
> + flash@1 {
> + compatible = "jedec,spi-nor";
> + reg = <1>;
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + host-prime@0 {
> + label = "host-prime";
> + reg = <0x0 0x02000000>;
> + };
> + host-second@0 {
> + label = "host-second";
> + reg = <0x02000000 0x02000000>;
> + };
> + };
> + };
> + };
> +
> + sram@d0000000 {
> + compatible = "mtd-ram";
> + reg = <0xd0000000 0x80000>;
> + bank-width = <1>;
> + erase-size =<1>;
> + partition@0 {
> + label = "host-reserved";
> + reg = <0x0 0x10000>;
> + };
> + partition@10000 {
> + label = "nvram";
> + reg = <0x10000 0x70000>;
> + };
> + };
> +
> + srom@80fc0000 {
> + compatible = "hpe,gxp-srom", "simple-mfd", "syscon";
> + reg = <0x80fc0000 0x100>;
> + };
> +
> + vrom@58000000 {
> + compatible = "mtd-ram";
> + bank-width = <4>;
> + reg = <0x58000000 0x4000000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + partition@0 {
> + label = "vrom-prime";
> + reg = <0x0 0x2000000>;
> + };
> + partition@2000000 {
> + label = "vrom-second";
> + reg = <0x2000000 0x2000000>;
> + };
> + };
> +
> + i2cg: i2cg@c00000f8 {
What's this exactly?
> + compatible = "syscon";
> + reg = <0xc00000f8 0x08>;
> + };
> +
> + i2c0: i2c@c0002000 {
> + compatible = "hpe,gxp-i2c";
> + reg = <0xc0002000 0x70>;
> + interrupts = <9>;
> + interrupt-parent = <&vic0>;
> + i2cg-handle = <&i2cg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c@c0002100 {
> + compatible = "hpe,gxp-i2c";
> + reg = <0xc0002100 0x70>;
> + interrupts = <9>;
> + interrupt-parent = <&vic0>;
> + i2cg-handle = <&i2cg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c@c0002200 {
> + compatible = "hpe,gxp-i2c";
> + reg = <0xc0002200 0x70>;
> + interrupts = <9>;
> + interrupt-parent = <&vic0>;
> + i2cg-handle = <&i2cg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + 24c02@50 {
> + compatible = "atmel,24c02";
> + pagesize = <8>;
> + reg = <0x50>;
> + };
> + };
> +
> + i2c3: i2c@c0002300 {
> + compatible = "hpe,gxp-i2c";
> + reg = <0xc0002300 0x70>;
> + interrupts = <9>;
> + interrupt-parent = <&vic0>;
> + i2cg-handle = <&i2cg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c4: i2c@c0002400 {
> + compatible = "hpe,gxp-i2c";
> + reg = <0xc0002400 0x70>;
> + interrupts = <9>;
> + interrupt-parent = <&vic0>;
> + i2cg-handle = <&i2cg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c5: i2c@c0002500 {
> + compatible = "hpe,gxp-i2c";
> + reg = <0xc0002500 0x70>;
> + interrupts = <9>;
> + interrupt-parent = <&vic0>;
> + i2cg-handle = <&i2cg>;
> + };
> +
> + i2c6: i2c@c0002600 {
> + compatible = "hpe,gxp-i2c";
> + reg = <0xc0002600 0x70>;
> + interrupts = <9>;
> + interrupt-parent = <&vic0>;
> + i2cg-handle = <&i2cg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c7: i2c@c0002700 {
> + compatible = "hpe,gxp-i2c";
> + reg = <0xc0002700 0x70>;
> + interrupts = <9>;
> + interrupt-parent = <&vic0>;
> + i2cg-handle = <&i2cg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + psu1: psu@58 {
> + compatible = "hpe,gxp-psu";
> + reg = <0x58>;
> + };
> +
> + psu2: psu@59 {
> + compatible = "hpe,gxp-psu";
> + reg = <0x59>;
> + };
> + };
> +
> + i2c8: i2c@c0002800 {
> + compatible = "hpe,gxp-i2c";
> + reg = <0xc0002800 0x70>;
> + interrupts = <9>;
> + interrupt-parent = <&vic0>;
> + i2cg-handle = <&i2cg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c9: i2c@c0002900 {
> + compatible = "hpe,gxp-i2c";
> + reg = <0xc0002900 0x70>;
> + interrupts = <9>;
> + interrupt-parent = <&vic0>;
> + i2cg-handle = <&i2cg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2cmux@4 {
Does it even compile with W=1? The unit address looks quite different
than what is below.
Also - node name should be generic.
> + compatible = "i2c-mux-reg";
> + i2c-parent = <&i2c4>;
> + reg = <0xd1000074 1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + i2c4@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c4@3 {
> + reg = <3>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c4@4 {
> + reg = <4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + i2cmux@6 {
> + compatible = "i2c-mux-reg";
> + i2c-parent = <&i2c6>;
> + reg = <0xd1000076 1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + i2c6@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c6@2 {
> + reg = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c6@3 {
> + reg = <3>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c6@4 {
> + reg = <4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c6@5 {
> + reg = <5>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + mdio0: mdio@c0004080 {
> + compatible = "hpe,gxp-umac-mdio";
> + reg = <0xc0004080 0x10>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + ext_phy0: ethernt-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + phy-mode = "sgmii";
> + reg = <0>;
> + };
> + };
> +
> + mdio1: mdio@c0005080 {
> + compatible = "hpe,gxp-umac-mdio";
> + reg = <0xc0005080 0x10>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + int_phy0: ethernt-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + phy-mode = "gmii";
> + reg = <0>;
> + };
> + int_phy1: ethernt-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + phy-mode = "gmii";
> + reg = <1>;
> + };
> + };
> +
> + umac0: umac@c0004000 {
> + compatible = "hpe, gxp-umac";
No spaces in compatibles. Previous comments about compatibles also
apply. About node name as well.
I'll stop on DTS now, because it does not look much better below.
> + reg = <0xc0004000 0x80>;
> + interrupts = <10>;
> + interrupt-parent = <&vic0>;
> + mac-address = [94 18 82 16 04 d8];
> + phy-handle = <&ext_phy0>;
> + int-phy-handle = <&int_phy0>;
> + };
> +
(...)
> diff --git a/arch/arm/configs/gxp_defconfig b/arch/arm/configs/gxp_defconfig
> new file mode 100644
> index 000000000000..f37c6630e06d
> --- /dev/null
> +++ b/arch/arm/configs/gxp_defconfig
> @@ -0,0 +1,243 @@
> +CONFIG_KERNEL_XZ=y
> +CONFIG_DEFAULT_HOSTNAME="gxp"
> +CONFIG_SYSVIPC=y
> +CONFIG_NO_HZ=y
> +CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_BSD_PROCESS_ACCT=y
> +CONFIG_BSD_PROCESS_ACCT_V3=y
> +CONFIG_LOG_BUF_SHIFT=18
> +CONFIG_CFS_BANDWIDTH=y
> +CONFIG_RT_GROUP_SCHED=y
> +CONFIG_CGROUP_FREEZER=y
> +CONFIG_CGROUP_DEVICE=y
> +CONFIG_CGROUP_CPUACCT=y
> +CONFIG_NAMESPACES=y
> +CONFIG_SCHED_AUTOGROUP=y
> +CONFIG_RELAY=y
> +CONFIG_BLK_DEV_INITRD=y
> +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> +CONFIG_KALLSYMS_ALL=y
> +CONFIG_EMBEDDED=y
> +# CONFIG_COMPAT_BRK is not set
> +CONFIG_SLAB=y
> +CONFIG_ARCH_MULTI_V6=y
> +CONFIG_ARCH_HPE=y
> +CONFIG_ARCH_HPE_GXP=y
> +CONFIG_SECCOMP=y
> +# CONFIG_ATAGS is not set
> +CONFIG_ZBOOT_ROM_TEXT=0x0
> +CONFIG_ZBOOT_ROM_BSS=0x0
> +# CONFIG_SUSPEND is not set
> +CONFIG_JUMP_LABEL=y
> +# CONFIG_STRICT_KERNEL_RWX is not set
> +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> +CONFIG_KSM=y
> +CONFIG_CLEANCACHE=y
> +CONFIG_NET=y
> +CONFIG_PACKET=y
> +CONFIG_PACKET_DIAG=y
> +CONFIG_UNIX=y
> +CONFIG_UNIX_DIAG=y
> +CONFIG_XFRM_USER=y
> +CONFIG_XFRM_STATISTICS=y
> +CONFIG_INET=y
> +CONFIG_VLAN_8021Q=y
> +CONFIG_NETLINK_DIAG=y
> +CONFIG_NET_NCSI=y
> +# CONFIG_WIRELESS is not set
> +CONFIG_DEVTMPFS=y
> +CONFIG_DEVTMPFS_MOUNT=y
> +# CONFIG_STANDALONE is not set
> +CONFIG_MTD=y
> +CONFIG_MTD_BLOCK=y
> +CONFIG_MTD_PHYSMAP=y
> +CONFIG_MTD_PHYSMAP_OF=y
> +CONFIG_MTD_PLATRAM=y
> +CONFIG_MTD_SPI_NOR=y
> +CONFIG_SPI_GXP_SPIFI=y
> +CONFIG_BLK_DEV_NULL_BLK=y
> +CONFIG_BLK_DEV_LOOP=y
> +CONFIG_BLK_DEV_NBD=y
> +CONFIG_BLK_DEV_RAM=y
> +CONFIG_EEPROM_AT24=y
> +CONFIG_SCSI=y
> +CONFIG_BLK_DEV_SD=y
> +# CONFIG_SCSI_LOWLEVEL is not set
> +CONFIG_NETDEVICES=y
> +# CONFIG_NET_VENDOR_ALACRITECH is not set
> +# CONFIG_NET_VENDOR_AMAZON is not set
> +# CONFIG_NET_VENDOR_AQUANTIA is not set
> +# CONFIG_NET_VENDOR_ARC is not set
> +# CONFIG_NET_VENDOR_AURORA is not set
> +# CONFIG_NET_VENDOR_BROADCOM is not set
> +# CONFIG_NET_VENDOR_CADENCE is not set
> +# CONFIG_NET_VENDOR_CAVIUM is not set
> +# CONFIG_NET_VENDOR_CIRRUS is not set
> +# CONFIG_NET_VENDOR_CORTINA is not set
> +# CONFIG_NET_VENDOR_EZCHIP is not set
> +# CONFIG_NET_VENDOR_FARADAY is not set
> +# CONFIG_NET_VENDOR_GOOGLE is not set
> +# CONFIG_NET_VENDOR_HISILICON is not set
> +# CONFIG_NET_VENDOR_HUAWEI is not set
> +# CONFIG_NET_VENDOR_INTEL is not set
> +# CONFIG_NET_VENDOR_MARVELL is not set
> +# CONFIG_NET_VENDOR_MELLANOX is not set
> +# CONFIG_NET_VENDOR_MICREL is not set
> +# CONFIG_NET_VENDOR_MICROCHIP is not set
> +# CONFIG_NET_VENDOR_MICROSEMI is not set
> +# CONFIG_NET_VENDOR_NATSEMI is not set
> +# CONFIG_NET_VENDOR_NETRONOME is not set
> +# CONFIG_NET_VENDOR_NI is not set
> +# CONFIG_NET_VENDOR_QUALCOMM is not set
> +# CONFIG_NET_VENDOR_RENESAS is not set
> +# CONFIG_NET_VENDOR_ROCKER is not set
> +# CONFIG_NET_VENDOR_SAMSUNG is not set
> +# CONFIG_NET_VENDOR_SEEQ is not set
> +# CONFIG_NET_VENDOR_SOLARFLARE is not set
> +# CONFIG_NET_VENDOR_SMSC is not set
> +# CONFIG_NET_VENDOR_SOCIONEXT is not set
> +# CONFIG_NET_VENDOR_STMICRO is not set
> +# CONFIG_NET_VENDOR_SYNOPSYS is not set
> +# CONFIG_NET_VENDOR_VIA is not set
> +# CONFIG_NET_VENDOR_WIZNET is not set
> +# CONFIG_NET_VENDOR_XILINX is not set
> +CONFIG_UMAC=y
> +# CONFIG_USB_NET_DRIVERS is not set
> +# CONFIG_WLAN is not set
> +# CONFIG_INPUT_LEDS is not set
> +CONFIG_INPUT_EVDEV=y
> +# CONFIG_KEYBOARD_ATKBD is not set
> +CONFIG_KEYBOARD_GPIO=y
> +CONFIG_KEYBOARD_GPIO_POLLED=y
> +# CONFIG_INPUT_MOUSE is not set
> +CONFIG_SERIO_LIBPS2=y
> +CONFIG_VT_HW_CONSOLE_BINDING=y
> +# CONFIG_LEGACY_PTYS is not set
> +CONFIG_SERIAL_8250=y
> +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
> +CONFIG_SERIAL_8250_CONSOLE=y
> +CONFIG_SERIAL_8250_NR_UARTS=6
> +CONFIG_SERIAL_8250_RUNTIME_UARTS=6
> +CONFIG_SERIAL_8250_EXTENDED=y
> +CONFIG_SERIAL_8250_SHARE_IRQ=y
> +CONFIG_SERIAL_8250_GXP_VUART=y
> +CONFIG_SERIAL_OF_PLATFORM=y
> +CONFIG_TTY_PRINTK=y
> +CONFIG_IPMI_HANDLER=y
> +CONFIG_IPMI_DEVICE_INTERFACE=y
> +CONFIG_IPMI_SI=y
> +CONFIG_IPMI_SSIF=y
> +CONFIG_HPE_KCS_IPMI_BMC=y
> +CONFIG_HW_RANDOM_TIMERIOMEM=y
> +CONFIG_I2C_CHARDEV=y
> +CONFIG_I2C_GXP=y
> +CONFIG_I2C_SLAVE=y
> +CONFIG_I2C_SLAVE_EEPROM=y
> +CONFIG_SPI=y
> +CONFIG_GPIOLIB=y
> +CONFIG_GPIO_SYSFS=y
> +CONFIG_GPIO_GXP=y
> +CONFIG_SENSORS_EMC1403=y
> +CONFIG_SENSORS_GXP_FAN_CTRL=y
> +CONFIG_SENSORS_GXP_CORETEMP=y
> +CONFIG_SENSORS_GXP_PSU=y
> +CONFIG_SENSORS_GXP_POWER=y
> +CONFIG_WATCHDOG=y
> +CONFIG_GXP_WATCHDOG=y
> +CONFIG_MFD_SYSCON=y
> +CONFIG_FB=y
> +CONFIG_FB_THUMBNAIL=y
> +CONFIG_FB_SIMPLE=y
> +CONFIG_USB=y
> +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_EHCI_ROOT_HUB_TT=y
> +CONFIG_USB_OHCI_HCD=y
> +CONFIG_USB_OHCI_HCD_PLATFORM=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GXP_UDC=y
> +CONFIG_USB_CONFIGFS=y
> +CONFIG_USB_CONFIGFS_SERIAL=y
> +CONFIG_USB_CONFIGFS_ACM=y
> +CONFIG_USB_CONFIGFS_OBEX=y
> +CONFIG_USB_CONFIGFS_NCM=y
> +CONFIG_USB_CONFIGFS_ECM=y
> +CONFIG_USB_CONFIGFS_ECM_SUBSET=y
> +CONFIG_USB_CONFIGFS_RNDIS=y
> +CONFIG_USB_CONFIGFS_EEM=y
> +CONFIG_USB_CONFIGFS_MASS_STORAGE=y
> +CONFIG_USB_CONFIGFS_F_LB_SS=y
> +CONFIG_USB_CONFIGFS_F_FS=y
> +CONFIG_USB_CONFIGFS_F_HID=y
> +CONFIG_USB_CONFIGFS_F_PRINTER=y
> +CONFIG_NEW_LEDS=y
> +CONFIG_LEDS_CLASS=y
> +CONFIG_LEDS_GPIO=y
> +CONFIG_LEDS_TRIGGERS=y
> +CONFIG_LEDS_TRIGGER_TIMER=y
> +CONFIG_LEDS_TRIGGER_ONESHOT=y
> +CONFIG_LEDS_TRIGGER_MTD=y
> +CONFIG_LEDS_TRIGGER_HEARTBEAT=y
> +CONFIG_LEDS_TRIGGER_CPU=y
> +CONFIG_LEDS_TRIGGER_GPIO=y
> +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
> +CONFIG_LEDS_TRIGGER_TRANSIENT=y
> +CONFIG_LEDS_TRIGGER_PANIC=y
> +# CONFIG_VIRTIO_MENU is not set
> +# CONFIG_IOMMU_SUPPORT is not set
> +CONFIG_HPE_GXP_XREG=y
> +CONFIG_HPE_GXP_FN2=y
> +CONFIG_HPE_GXP_CSM=y
> +CONFIG_HPE_GXP_SROM=y
> +CONFIG_FANOTIFY=y
> +CONFIG_OVERLAY_FS=y
> +CONFIG_OVERLAY_FS_REDIRECT_DIR=y
> +CONFIG_TMPFS=y
> +CONFIG_TMPFS_POSIX_ACL=y
> +CONFIG_JFFS2_FS=y
> +# CONFIG_JFFS2_FS_WRITEBUFFER is not set
> +CONFIG_JFFS2_SUMMARY=y
> +CONFIG_JFFS2_FS_XATTR=y
> +# CONFIG_JFFS2_FS_POSIX_ACL is not set
> +# CONFIG_JFFS2_FS_SECURITY is not set
> +CONFIG_SQUASHFS=y
> +CONFIG_SQUASHFS_XZ=y
> +CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
> +# CONFIG_NETWORK_FILESYSTEMS is not set
> +CONFIG_NLS_CODEPAGE_437=y
> +CONFIG_NLS_ASCII=y
> +CONFIG_NLS_ISO8859_1=y
> +CONFIG_NLS_UTF8=y
> +CONFIG_CRYPTO_CCM=y
> +CONFIG_CRYPTO_GCM=y
> +CONFIG_CRYPTO_CRC32C=y
> +CONFIG_CRYPTO_ARC4=y
> +CONFIG_CRYPTO_DEFLATE=y
> +CONFIG_CRYPTO_LZO=y
> +CONFIG_CRYPTO_ZSTD=y
> +CONFIG_CRYPTO_USER_API_HASH=y
> +# CONFIG_CRYPTO_HW is not set
> +CONFIG_CRC16=y
> +# CONFIG_XZ_DEC_ARM is not set
> +# CONFIG_XZ_DEC_ARMTHUMB is not set
> +CONFIG_DMA_API_DEBUG=y
> +CONFIG_PRINTK_TIME=y
> +CONFIG_BOOT_PRINTK_DELAY=y
> +CONFIG_DYNAMIC_DEBUG=y
> +CONFIG_DEBUG_INFO=y
> +# CONFIG_ENABLE_MUST_CHECK is not set
> +CONFIG_MAGIC_SYSRQ=y
> +CONFIG_PANIC_ON_OOPS=y
> +CONFIG_FUNCTION_PROFILER=y
> +CONFIG_STACK_TRACER=y
> +CONFIG_SCHED_TRACER=y
> +CONFIG_STRICT_DEVMEM=y
> +CONFIG_DEBUG_USER=y
> +CONFIG_DEBUG_LL=y
> +CONFIG_DEBUG_LL_UART_8250=y
> +CONFIG_DEBUG_UART_PHYS=0xC00000F0
> +CONFIG_DEBUG_UART_VIRT=0xF00000F0
> +CONFIG_DEBUG_UART_8250_SHIFT=0
> +CONFIG_EARLY_PRINTK=y
> +CONFIG_TEST_KSTRTOX=y
> diff --git a/arch/arm/mach-hpe/Kconfig b/arch/arm/mach-hpe/Kconfig
> new file mode 100644
> index 000000000000..9b27f97c6536
> --- /dev/null
> +++ b/arch/arm/mach-hpe/Kconfig
> @@ -0,0 +1,20 @@
> +menuconfig ARCH_HPE
> + bool "HPE SoC support"
> + help
> + This enables support for HPE ARM based SoC chips
> +if ARCH_HPE
> +
> +config ARCH_HPE_GXP
> + bool "HPE GXP SoC"
> + select ARM_VIC
> + select PINCTRL
> + select IRQ_DOMAIN
> + select GENERIC_IRQ_CHIP
> + select MULTI_IRQ_HANDLER
> + select SPARSE_IRQ
> + select CLKSRC_MMIO
> + depends on ARCH_MULTI_V7
> + help
> + Support for GXP SoCs
> +
> +endif
> diff --git a/arch/arm/mach-hpe/Makefile b/arch/arm/mach-hpe/Makefile
> new file mode 100644
> index 000000000000..8b0a91234df4
> --- /dev/null
> +++ b/arch/arm/mach-hpe/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_ARCH_HPE_GXP) += gxp.o
> diff --git a/arch/arm/mach-hpe/gxp.c b/arch/arm/mach-hpe/gxp.c
> new file mode 100644
> index 000000000000..b58f25fbae5a
> --- /dev/null
> +++ b/arch/arm/mach-hpe/gxp.c
> @@ -0,0 +1,63 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P.
> + *
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +
> +#include <linux/init.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/map.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clocksource.h>
> +
> +#define IOP_REGS_PHYS_BASE 0xc0000000
> +#define IOP_REGS_VIRT_BASE 0xf0000000
> +#define IOP_REGS_SIZE (240*SZ_1M)
> +
> +#define IOP_EHCI_USBCMD 0x0efe0010
> +
> +static struct map_desc gxp_io_desc[] __initdata = {
> + {
> + .virtual = (unsigned long)IOP_REGS_VIRT_BASE,
> + .pfn = __phys_to_pfn(IOP_REGS_PHYS_BASE),
> + .length = IOP_REGS_SIZE,
> + .type = MT_DEVICE,
> + },
> +};
> +
> +void __init gxp_map_io(void)
> +{
> + iotable_init(gxp_io_desc, ARRAY_SIZE(gxp_io_desc));
> +}
> +
> +static void __init gxp_dt_init(void)
> +{
> + //reset EHCI host controller for clear start
Linux style comments please, so /*.
> + __raw_writel(0x00080002,
What is this magic value?
> + (void __iomem *)(IOP_REGS_VIRT_BASE + IOP_EHCI_USBCMD));
Why do you need the cast?
> + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> +}
> +
> +static void gxp_restart(enum reboot_mode mode, const char *cmd)
> +{
> + pr_info("gpx restart");
Skip it.
> + __raw_writel(1, (void __iomem *) IOP_REGS_VIRT_BASE);
> +}
> +
> +static const char * const gxp_board_dt_compat[] = {
> + "HPE,GXP",
> + NULL,
> +};
> +
> +DT_MACHINE_START(GXP_DT, "HPE GXP")
> + .init_machine = gxp_dt_init,
> + .map_io = gxp_map_io,
> + .restart = gxp_restart,
> + .dt_compat = gxp_board_dt_compat,
> +MACHINE_END
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 10/15] drivers: clk: qcom: gcc-ipq806x: add additional freq for sdc table
From: Stephen Boyd @ 2022-01-25 20:45 UTC (permalink / raw)
To: Andy Gross, Ansuel Smith, Bjorn Andersson, Michael Turquette,
Philipp Zabel, Rob Herring, Taniya Das, devicetree, linux-arm-msm,
linux-clk, linux-kernel
In-Reply-To: <20220121210340.32362-11-ansuelsmth@gmail.com>
Quoting Ansuel Smith (2022-01-21 13:03:35)
> Add additional freq supported for the sdc table.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
> drivers/clk/qcom/gcc-ipq806x.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
> index 77bc3d94f580..dbd61e4844b0 100644
> --- a/drivers/clk/qcom/gcc-ipq806x.c
> +++ b/drivers/clk/qcom/gcc-ipq806x.c
> @@ -1292,6 +1292,7 @@ static const struct freq_tbl clk_tbl_sdc[] = {
> { 20210000, P_PLL8, 1, 1, 19 },
> { 24000000, P_PLL8, 4, 1, 4 },
> { 48000000, P_PLL8, 4, 1, 2 },
> + { 52000000, P_PLL8, 1, 2, 15 }, /* 51.2 Mhz */
Why the comment and fake rate? Can it be 51200000 instead and drop the
comment?
^ permalink raw reply
* Re: [PATCH v3 11/15] dt-bindings: clock: add ipq8064 ce5 clk define
From: Stephen Boyd @ 2022-01-25 20:47 UTC (permalink / raw)
To: Andy Gross, Ansuel Smith, Bjorn Andersson, Michael Turquette,
Philipp Zabel, Rob Herring, Taniya Das, devicetree, linux-arm-msm,
linux-clk, linux-kernel
In-Reply-To: <20220121210340.32362-12-ansuelsmth@gmail.com>
Quoting Ansuel Smith (2022-01-21 13:03:36)
> Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
> include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
> index 7deec14a6dee..02262d2ac899 100644
> --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
> +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
> @@ -240,7 +240,7 @@
> #define PLL14 232
> #define PLL14_VOTE 233
> #define PLL18 234
> -#define CE5_SRC 235
> +#define CE5_A_CLK 235
Technically this is ABI and changing it is bad. I see that CE5_SRC isn't
used though so I guess it's OK.
> #define CE5_H_CLK 236
> #define CE5_CORE_CLK 237
> #define CE3_SLEEP_CLK 238
> @@ -283,5 +283,8 @@
> #define EBI2_AON_CLK 281
> #define NSSTCM_CLK_SRC 282
> #define NSSTCM_CLK 283
> +#define CE5_A_CLK_SRC 285
> +#define CE5_H_CLK_SRC 286
> +#define CE5_CORE_CLK_SRC 287
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox